1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 enum ecc_resource_type { 59 ECC_RESOURCE_QPC, 60 ECC_RESOURCE_CQC, 61 ECC_RESOURCE_MPT, 62 ECC_RESOURCE_SRQC, 63 ECC_RESOURCE_GMV, 64 ECC_RESOURCE_QPC_TIMER, 65 ECC_RESOURCE_CQC_TIMER, 66 ECC_RESOURCE_SCCC, 67 ECC_RESOURCE_COUNT, 68 }; 69 70 static const struct { 71 const char *name; 72 u8 read_bt0_op; 73 u8 write_bt0_op; 74 } fmea_ram_res[] = { 75 { "ECC_RESOURCE_QPC", 76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 77 { "ECC_RESOURCE_CQC", 78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 79 { "ECC_RESOURCE_MPT", 80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 81 { "ECC_RESOURCE_SRQC", 82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 84 { "ECC_RESOURCE_GMV", 85 0, 0 }, 86 { "ECC_RESOURCE_QPC_TIMER", 87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 88 { "ECC_RESOURCE_CQC_TIMER", 89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 90 { "ECC_RESOURCE_SCCC", 91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 92 }; 93 94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 95 struct ib_sge *sg) 96 { 97 dseg->lkey = cpu_to_le32(sg->lkey); 98 dseg->addr = cpu_to_le64(sg->addr); 99 dseg->len = cpu_to_le32(sg->length); 100 } 101 102 /* 103 * mapped-value = 1 + real-value 104 * The hns wr opcode real value is start from 0, In order to distinguish between 105 * initialized and uninitialized map values, we plus 1 to the actual value when 106 * defining the mapping, so that the validity can be identified by checking the 107 * mapped value is greater than 0. 108 */ 109 #define HR_OPC_MAP(ib_key, hr_key) \ 110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 111 112 static const u32 hns_roce_op_code[] = { 113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 115 HR_OPC_MAP(SEND, SEND), 116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 117 HR_OPC_MAP(RDMA_READ, RDMA_READ), 118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 121 HR_OPC_MAP(LOCAL_INV, LOCAL_INV), 122 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 123 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 124 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 125 }; 126 127 static u32 to_hr_opcode(u32 ib_opcode) 128 { 129 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 130 return HNS_ROCE_V2_WQE_OP_MASK; 131 132 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 133 HNS_ROCE_V2_WQE_OP_MASK; 134 } 135 136 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 137 const struct ib_reg_wr *wr) 138 { 139 struct hns_roce_wqe_frmr_seg *fseg = 140 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 141 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 142 u64 pbl_ba; 143 144 /* use ib_access_flags */ 145 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 146 hr_reg_write_bool(fseg, FRMR_ATOMIC, 147 wr->access & IB_ACCESS_REMOTE_ATOMIC); 148 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 149 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 150 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 151 152 /* Data structure reuse may lead to confusion */ 153 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 154 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 155 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 156 157 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 158 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 159 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 160 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 161 162 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 163 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 164 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 165 hr_reg_clear(fseg, FRMR_BLK_MODE); 166 } 167 168 static void set_atomic_seg(const struct ib_send_wr *wr, 169 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 170 unsigned int valid_num_sge) 171 { 172 struct hns_roce_v2_wqe_data_seg *dseg = 173 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 174 struct hns_roce_wqe_atomic_seg *aseg = 175 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 176 177 set_data_seg_v2(dseg, wr->sg_list); 178 179 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 180 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 181 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 182 } else { 183 aseg->fetchadd_swap_data = 184 cpu_to_le64(atomic_wr(wr)->compare_add); 185 aseg->cmp_data = 0; 186 } 187 188 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 189 } 190 191 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 192 const struct ib_send_wr *wr, 193 unsigned int *sge_idx, u32 msg_len) 194 { 195 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 196 unsigned int ext_sge_sz = qp->sq.max_gs * HNS_ROCE_SGE_SIZE; 197 unsigned int left_len_in_pg; 198 unsigned int idx = *sge_idx; 199 unsigned int i = 0; 200 unsigned int len; 201 void *addr; 202 void *dseg; 203 204 if (msg_len > ext_sge_sz) { 205 ibdev_err(ibdev, 206 "no enough extended sge space for inline data.\n"); 207 return -EINVAL; 208 } 209 210 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 211 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 212 len = wr->sg_list[0].length; 213 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 214 215 /* When copying data to extended sge space, the left length in page may 216 * not long enough for current user's sge. So the data should be 217 * splited into several parts, one in the first page, and the others in 218 * the subsequent pages. 219 */ 220 while (1) { 221 if (len <= left_len_in_pg) { 222 memcpy(dseg, addr, len); 223 224 idx += len / HNS_ROCE_SGE_SIZE; 225 226 i++; 227 if (i >= wr->num_sge) 228 break; 229 230 left_len_in_pg -= len; 231 len = wr->sg_list[i].length; 232 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 233 dseg += len; 234 } else { 235 memcpy(dseg, addr, left_len_in_pg); 236 237 len -= left_len_in_pg; 238 addr += left_len_in_pg; 239 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 240 dseg = hns_roce_get_extend_sge(qp, 241 idx & (qp->sge.sge_cnt - 1)); 242 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 243 } 244 } 245 246 *sge_idx = idx; 247 248 return 0; 249 } 250 251 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 252 unsigned int *sge_ind, unsigned int cnt) 253 { 254 struct hns_roce_v2_wqe_data_seg *dseg; 255 unsigned int idx = *sge_ind; 256 257 while (cnt > 0) { 258 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 259 if (likely(sge->length)) { 260 set_data_seg_v2(dseg, sge); 261 idx++; 262 cnt--; 263 } 264 sge++; 265 } 266 267 *sge_ind = idx; 268 } 269 270 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 271 { 272 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 273 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 274 275 if (len > qp->max_inline_data || len > mtu) { 276 ibdev_err(&hr_dev->ib_dev, 277 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 278 len, qp->max_inline_data, mtu); 279 return false; 280 } 281 282 return true; 283 } 284 285 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 286 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 287 unsigned int *sge_idx) 288 { 289 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 290 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 291 struct ib_device *ibdev = &hr_dev->ib_dev; 292 unsigned int curr_idx = *sge_idx; 293 void *dseg = rc_sq_wqe; 294 unsigned int i; 295 int ret; 296 297 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 298 ibdev_err(ibdev, "invalid inline parameters!\n"); 299 return -EINVAL; 300 } 301 302 if (!check_inl_data_len(qp, msg_len)) 303 return -EINVAL; 304 305 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 306 307 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 308 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 309 310 for (i = 0; i < wr->num_sge; i++) { 311 memcpy(dseg, ((void *)wr->sg_list[i].addr), 312 wr->sg_list[i].length); 313 dseg += wr->sg_list[i].length; 314 } 315 } else { 316 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 317 318 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 319 if (ret) 320 return ret; 321 322 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 323 } 324 325 *sge_idx = curr_idx; 326 327 return 0; 328 } 329 330 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 331 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 332 unsigned int *sge_ind, 333 unsigned int valid_num_sge) 334 { 335 struct hns_roce_v2_wqe_data_seg *dseg = 336 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 337 struct hns_roce_qp *qp = to_hr_qp(ibqp); 338 int j = 0; 339 int i; 340 341 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 342 (*sge_ind) & (qp->sge.sge_cnt - 1)); 343 344 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 345 !!(wr->send_flags & IB_SEND_INLINE)); 346 if (wr->send_flags & IB_SEND_INLINE) 347 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 348 349 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 350 for (i = 0; i < wr->num_sge; i++) { 351 if (likely(wr->sg_list[i].length)) { 352 set_data_seg_v2(dseg, wr->sg_list + i); 353 dseg++; 354 } 355 } 356 } else { 357 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 358 if (likely(wr->sg_list[i].length)) { 359 set_data_seg_v2(dseg, wr->sg_list + i); 360 dseg++; 361 j++; 362 } 363 } 364 365 set_extend_sge(qp, wr->sg_list + i, sge_ind, 366 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 367 } 368 369 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 370 371 return 0; 372 } 373 374 static int check_send_valid(struct hns_roce_dev *hr_dev, 375 struct hns_roce_qp *hr_qp) 376 { 377 struct ib_device *ibdev = &hr_dev->ib_dev; 378 struct ib_qp *ibqp = &hr_qp->ibqp; 379 380 if (unlikely(ibqp->qp_type != IB_QPT_RC && 381 ibqp->qp_type != IB_QPT_GSI && 382 ibqp->qp_type != IB_QPT_UD)) { 383 ibdev_err(ibdev, "not supported QP(0x%x)type!\n", 384 ibqp->qp_type); 385 return -EOPNOTSUPP; 386 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 387 hr_qp->state == IB_QPS_INIT || 388 hr_qp->state == IB_QPS_RTR)) { 389 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 390 hr_qp->state); 391 return -EINVAL; 392 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 393 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 394 hr_dev->state); 395 return -EIO; 396 } 397 398 return 0; 399 } 400 401 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 402 unsigned int *sge_len) 403 { 404 unsigned int valid_num = 0; 405 unsigned int len = 0; 406 int i; 407 408 for (i = 0; i < wr->num_sge; i++) { 409 if (likely(wr->sg_list[i].length)) { 410 len += wr->sg_list[i].length; 411 valid_num++; 412 } 413 } 414 415 *sge_len = len; 416 return valid_num; 417 } 418 419 static __le32 get_immtdata(const struct ib_send_wr *wr) 420 { 421 switch (wr->opcode) { 422 case IB_WR_SEND_WITH_IMM: 423 case IB_WR_RDMA_WRITE_WITH_IMM: 424 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 425 default: 426 return 0; 427 } 428 } 429 430 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 431 const struct ib_send_wr *wr) 432 { 433 u32 ib_op = wr->opcode; 434 435 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 436 return -EINVAL; 437 438 ud_sq_wqe->immtdata = get_immtdata(wr); 439 440 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 441 442 return 0; 443 } 444 445 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 446 struct hns_roce_ah *ah) 447 { 448 struct ib_device *ib_dev = ah->ibah.device; 449 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 450 451 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 452 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 453 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 454 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 455 456 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 457 return -EINVAL; 458 459 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 460 461 ud_sq_wqe->sgid_index = ah->av.gid_index; 462 463 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 464 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 465 466 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 467 return 0; 468 469 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 470 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 471 472 return 0; 473 } 474 475 static inline int set_ud_wqe(struct hns_roce_qp *qp, 476 const struct ib_send_wr *wr, 477 void *wqe, unsigned int *sge_idx, 478 unsigned int owner_bit) 479 { 480 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 481 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 482 unsigned int curr_idx = *sge_idx; 483 unsigned int valid_num_sge; 484 u32 msg_len = 0; 485 int ret; 486 487 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 488 489 ret = set_ud_opcode(ud_sq_wqe, wr); 490 if (WARN_ON(ret)) 491 return ret; 492 493 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 494 495 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 496 !!(wr->send_flags & IB_SEND_SIGNALED)); 497 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 498 !!(wr->send_flags & IB_SEND_SOLICITED)); 499 500 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 501 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 502 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 503 curr_idx & (qp->sge.sge_cnt - 1)); 504 505 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 506 qp->qkey : ud_wr(wr)->remote_qkey); 507 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 508 509 ret = fill_ud_av(ud_sq_wqe, ah); 510 if (ret) 511 return ret; 512 513 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 514 515 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 516 517 /* 518 * The pipeline can sequentially post all valid WQEs into WQ buffer, 519 * including new WQEs waiting for the doorbell to update the PI again. 520 * Therefore, the owner bit of WQE MUST be updated after all fields 521 * and extSGEs have been written into DDR instead of cache. 522 */ 523 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 524 dma_wmb(); 525 526 *sge_idx = curr_idx; 527 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 528 529 return 0; 530 } 531 532 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 533 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 534 const struct ib_send_wr *wr) 535 { 536 u32 ib_op = wr->opcode; 537 int ret = 0; 538 539 rc_sq_wqe->immtdata = get_immtdata(wr); 540 541 switch (ib_op) { 542 case IB_WR_RDMA_READ: 543 case IB_WR_RDMA_WRITE: 544 case IB_WR_RDMA_WRITE_WITH_IMM: 545 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 546 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 547 break; 548 case IB_WR_SEND: 549 case IB_WR_SEND_WITH_IMM: 550 break; 551 case IB_WR_ATOMIC_CMP_AND_SWP: 552 case IB_WR_ATOMIC_FETCH_AND_ADD: 553 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 554 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 555 break; 556 case IB_WR_REG_MR: 557 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 558 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 559 else 560 ret = -EOPNOTSUPP; 561 break; 562 case IB_WR_LOCAL_INV: 563 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_SO); 564 fallthrough; 565 case IB_WR_SEND_WITH_INV: 566 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 567 break; 568 default: 569 ret = -EINVAL; 570 } 571 572 if (unlikely(ret)) 573 return ret; 574 575 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 576 577 return ret; 578 } 579 580 static inline int set_rc_wqe(struct hns_roce_qp *qp, 581 const struct ib_send_wr *wr, 582 void *wqe, unsigned int *sge_idx, 583 unsigned int owner_bit) 584 { 585 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 586 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 587 unsigned int curr_idx = *sge_idx; 588 unsigned int valid_num_sge; 589 u32 msg_len = 0; 590 int ret; 591 592 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 593 594 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 595 596 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 597 if (WARN_ON(ret)) 598 return ret; 599 600 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE, 601 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 602 603 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 604 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 605 606 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 607 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 608 609 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 610 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 611 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 612 else if (wr->opcode != IB_WR_REG_MR) 613 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 614 &curr_idx, valid_num_sge); 615 616 /* 617 * The pipeline can sequentially post all valid WQEs into WQ buffer, 618 * including new WQEs waiting for the doorbell to update the PI again. 619 * Therefore, the owner bit of WQE MUST be updated after all fields 620 * and extSGEs have been written into DDR instead of cache. 621 */ 622 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 623 dma_wmb(); 624 625 *sge_idx = curr_idx; 626 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 627 628 return ret; 629 } 630 631 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 632 struct hns_roce_qp *qp) 633 { 634 if (unlikely(qp->state == IB_QPS_ERR)) { 635 flush_cqe(hr_dev, qp); 636 } else { 637 struct hns_roce_v2_db sq_db = {}; 638 639 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 640 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 641 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 642 hr_reg_write(&sq_db, DB_SL, qp->sl); 643 644 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 645 } 646 } 647 648 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 649 struct hns_roce_qp *qp) 650 { 651 if (unlikely(qp->state == IB_QPS_ERR)) { 652 flush_cqe(hr_dev, qp); 653 } else { 654 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 655 *qp->rdb.db_record = 656 qp->rq.head & V2_DB_PRODUCER_IDX_M; 657 } else { 658 struct hns_roce_v2_db rq_db = {}; 659 660 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 661 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 662 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 663 664 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 665 qp->rq.db_reg); 666 } 667 } 668 } 669 670 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 671 u64 __iomem *dest) 672 { 673 #define HNS_ROCE_WRITE_TIMES 8 674 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 675 struct hnae3_handle *handle = priv->handle; 676 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 677 int i; 678 679 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 680 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 681 writeq_relaxed(*(val + i), dest + i); 682 } 683 684 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 685 void *wqe) 686 { 687 #define HNS_ROCE_SL_SHIFT 2 688 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 689 690 /* All kinds of DirectWQE have the same header field layout */ 691 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 692 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 693 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 694 qp->sl >> HNS_ROCE_SL_SHIFT); 695 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 696 697 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 698 } 699 700 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 701 const struct ib_send_wr *wr, 702 const struct ib_send_wr **bad_wr) 703 { 704 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 705 struct ib_device *ibdev = &hr_dev->ib_dev; 706 struct hns_roce_qp *qp = to_hr_qp(ibqp); 707 unsigned long flags = 0; 708 unsigned int owner_bit; 709 unsigned int sge_idx; 710 unsigned int wqe_idx; 711 void *wqe = NULL; 712 u32 nreq; 713 int ret; 714 715 spin_lock_irqsave(&qp->sq.lock, flags); 716 717 ret = check_send_valid(hr_dev, qp); 718 if (unlikely(ret)) { 719 *bad_wr = wr; 720 nreq = 0; 721 goto out; 722 } 723 724 sge_idx = qp->next_sge; 725 726 for (nreq = 0; wr; ++nreq, wr = wr->next) { 727 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 728 ret = -ENOMEM; 729 *bad_wr = wr; 730 goto out; 731 } 732 733 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 734 735 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 736 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 737 wr->num_sge, qp->sq.max_gs); 738 ret = -EINVAL; 739 *bad_wr = wr; 740 goto out; 741 } 742 743 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 744 qp->sq.wrid[wqe_idx] = wr->wr_id; 745 owner_bit = 746 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 747 748 /* Corresponding to the QP type, wqe process separately */ 749 if (ibqp->qp_type == IB_QPT_RC) 750 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 751 else 752 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 753 754 if (unlikely(ret)) { 755 *bad_wr = wr; 756 goto out; 757 } 758 } 759 760 out: 761 if (likely(nreq)) { 762 qp->sq.head += nreq; 763 qp->next_sge = sge_idx; 764 765 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 766 write_dwqe(hr_dev, qp, wqe); 767 else 768 update_sq_db(hr_dev, qp); 769 } 770 771 spin_unlock_irqrestore(&qp->sq.lock, flags); 772 773 return ret; 774 } 775 776 static int check_recv_valid(struct hns_roce_dev *hr_dev, 777 struct hns_roce_qp *hr_qp) 778 { 779 struct ib_device *ibdev = &hr_dev->ib_dev; 780 struct ib_qp *ibqp = &hr_qp->ibqp; 781 782 if (unlikely(ibqp->qp_type != IB_QPT_RC && 783 ibqp->qp_type != IB_QPT_GSI && 784 ibqp->qp_type != IB_QPT_UD)) { 785 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n", 786 ibqp->qp_type); 787 return -EOPNOTSUPP; 788 } 789 790 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 791 return -EIO; 792 793 if (hr_qp->state == IB_QPS_RESET) 794 return -EINVAL; 795 796 return 0; 797 } 798 799 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 800 u32 max_sge, bool rsv) 801 { 802 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 803 u32 i, cnt; 804 805 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 806 /* Skip zero-length sge */ 807 if (!wr->sg_list[i].length) 808 continue; 809 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 810 cnt++; 811 } 812 813 /* Fill a reserved sge to make hw stop reading remaining segments */ 814 if (rsv) { 815 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 816 dseg[cnt].addr = 0; 817 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 818 } else { 819 /* Clear remaining segments to make ROCEE ignore sges */ 820 if (cnt < max_sge) 821 memset(dseg + cnt, 0, 822 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 823 } 824 } 825 826 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 827 u32 wqe_idx, u32 max_sge) 828 { 829 struct hns_roce_rinl_sge *sge_list; 830 void *wqe = NULL; 831 u32 i; 832 833 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 834 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 835 836 /* rq support inline data */ 837 if (hr_qp->rq_inl_buf.wqe_cnt) { 838 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; 839 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge; 840 for (i = 0; i < wr->num_sge; i++) { 841 sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr; 842 sge_list[i].len = wr->sg_list[i].length; 843 } 844 } 845 } 846 847 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 848 const struct ib_recv_wr *wr, 849 const struct ib_recv_wr **bad_wr) 850 { 851 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 852 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 853 struct ib_device *ibdev = &hr_dev->ib_dev; 854 u32 wqe_idx, nreq, max_sge; 855 unsigned long flags; 856 int ret; 857 858 spin_lock_irqsave(&hr_qp->rq.lock, flags); 859 860 ret = check_recv_valid(hr_dev, hr_qp); 861 if (unlikely(ret)) { 862 *bad_wr = wr; 863 nreq = 0; 864 goto out; 865 } 866 867 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 868 for (nreq = 0; wr; ++nreq, wr = wr->next) { 869 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 870 hr_qp->ibqp.recv_cq))) { 871 ret = -ENOMEM; 872 *bad_wr = wr; 873 goto out; 874 } 875 876 if (unlikely(wr->num_sge > max_sge)) { 877 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 878 wr->num_sge, max_sge); 879 ret = -EINVAL; 880 *bad_wr = wr; 881 goto out; 882 } 883 884 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 885 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 886 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 887 } 888 889 out: 890 if (likely(nreq)) { 891 hr_qp->rq.head += nreq; 892 893 update_rq_db(hr_dev, hr_qp); 894 } 895 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 896 897 return ret; 898 } 899 900 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 901 { 902 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 903 } 904 905 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 906 { 907 return hns_roce_buf_offset(idx_que->mtr.kmem, 908 n << idx_que->entry_shift); 909 } 910 911 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 912 { 913 /* always called with interrupts disabled. */ 914 spin_lock(&srq->lock); 915 916 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 917 srq->idx_que.tail++; 918 919 spin_unlock(&srq->lock); 920 } 921 922 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 923 { 924 struct hns_roce_idx_que *idx_que = &srq->idx_que; 925 926 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 927 } 928 929 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 930 const struct ib_recv_wr *wr) 931 { 932 struct ib_device *ib_dev = srq->ibsrq.device; 933 934 if (unlikely(wr->num_sge > max_sge)) { 935 ibdev_err(ib_dev, 936 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 937 wr->num_sge, max_sge); 938 return -EINVAL; 939 } 940 941 if (unlikely(hns_roce_srqwq_overflow(srq))) { 942 ibdev_err(ib_dev, 943 "failed to check srqwq status, srqwq is full.\n"); 944 return -ENOMEM; 945 } 946 947 return 0; 948 } 949 950 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 951 { 952 struct hns_roce_idx_que *idx_que = &srq->idx_que; 953 u32 pos; 954 955 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 956 if (unlikely(pos == srq->wqe_cnt)) 957 return -ENOSPC; 958 959 bitmap_set(idx_que->bitmap, pos, 1); 960 *wqe_idx = pos; 961 return 0; 962 } 963 964 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 965 { 966 struct hns_roce_idx_que *idx_que = &srq->idx_que; 967 unsigned int head; 968 __le32 *buf; 969 970 head = idx_que->head & (srq->wqe_cnt - 1); 971 972 buf = get_idx_buf(idx_que, head); 973 *buf = cpu_to_le32(wqe_idx); 974 975 idx_que->head++; 976 } 977 978 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 979 { 980 hr_reg_write(db, DB_TAG, srq->srqn); 981 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 982 hr_reg_write(db, DB_PI, srq->idx_que.head); 983 } 984 985 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 986 const struct ib_recv_wr *wr, 987 const struct ib_recv_wr **bad_wr) 988 { 989 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 990 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 991 struct hns_roce_v2_db srq_db; 992 unsigned long flags; 993 int ret = 0; 994 u32 max_sge; 995 u32 wqe_idx; 996 void *wqe; 997 u32 nreq; 998 999 spin_lock_irqsave(&srq->lock, flags); 1000 1001 max_sge = srq->max_gs - srq->rsv_sge; 1002 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1003 ret = check_post_srq_valid(srq, max_sge, wr); 1004 if (ret) { 1005 *bad_wr = wr; 1006 break; 1007 } 1008 1009 ret = get_srq_wqe_idx(srq, &wqe_idx); 1010 if (unlikely(ret)) { 1011 *bad_wr = wr; 1012 break; 1013 } 1014 1015 wqe = get_srq_wqe_buf(srq, wqe_idx); 1016 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 1017 fill_wqe_idx(srq, wqe_idx); 1018 srq->wrid[wqe_idx] = wr->wr_id; 1019 } 1020 1021 if (likely(nreq)) { 1022 update_srq_db(&srq_db, srq); 1023 1024 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 1025 } 1026 1027 spin_unlock_irqrestore(&srq->lock, flags); 1028 1029 return ret; 1030 } 1031 1032 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1033 unsigned long instance_stage, 1034 unsigned long reset_stage) 1035 { 1036 /* When hardware reset has been completed once or more, we should stop 1037 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1038 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1039 * stage of soft reset process, we should exit with error, and then 1040 * HNAE3_INIT_CLIENT related process can rollback the operation like 1041 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1042 * process will exit with error to notify NIC driver to reschedule soft 1043 * reset process once again. 1044 */ 1045 hr_dev->is_reset = true; 1046 hr_dev->dis_db = true; 1047 1048 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1049 instance_stage == HNS_ROCE_STATE_INIT) 1050 return CMD_RST_PRC_EBUSY; 1051 1052 return CMD_RST_PRC_SUCCESS; 1053 } 1054 1055 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1056 unsigned long instance_stage, 1057 unsigned long reset_stage) 1058 { 1059 #define HW_RESET_TIMEOUT_US 1000000 1060 #define HW_RESET_SLEEP_US 1000 1061 1062 struct hns_roce_v2_priv *priv = hr_dev->priv; 1063 struct hnae3_handle *handle = priv->handle; 1064 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1065 unsigned long val; 1066 int ret; 1067 1068 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1069 * doorbell to hardware. If now in .init_instance() function, we should 1070 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1071 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1072 * related process can rollback the operation like notifing hardware to 1073 * free resources, HNAE3_INIT_CLIENT related process will exit with 1074 * error to notify NIC driver to reschedule soft reset process once 1075 * again. 1076 */ 1077 hr_dev->dis_db = true; 1078 1079 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1080 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1081 HW_RESET_TIMEOUT_US, false, handle); 1082 if (!ret) 1083 hr_dev->is_reset = true; 1084 1085 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1086 instance_stage == HNS_ROCE_STATE_INIT) 1087 return CMD_RST_PRC_EBUSY; 1088 1089 return CMD_RST_PRC_SUCCESS; 1090 } 1091 1092 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1093 { 1094 struct hns_roce_v2_priv *priv = hr_dev->priv; 1095 struct hnae3_handle *handle = priv->handle; 1096 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1097 1098 /* When software reset is detected at .init_instance() function, we 1099 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1100 * with error. 1101 */ 1102 hr_dev->dis_db = true; 1103 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1104 hr_dev->is_reset = true; 1105 1106 return CMD_RST_PRC_EBUSY; 1107 } 1108 1109 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1110 struct hnae3_handle *handle) 1111 { 1112 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1113 unsigned long instance_stage; /* the current instance stage */ 1114 unsigned long reset_stage; /* the current reset stage */ 1115 unsigned long reset_cnt; 1116 bool sw_resetting; 1117 bool hw_resetting; 1118 1119 /* Get information about reset from NIC driver or RoCE driver itself, 1120 * the meaning of the following variables from NIC driver are described 1121 * as below: 1122 * reset_cnt -- The count value of completed hardware reset. 1123 * hw_resetting -- Whether hardware device is resetting now. 1124 * sw_resetting -- Whether NIC's software reset process is running now. 1125 */ 1126 instance_stage = handle->rinfo.instance_state; 1127 reset_stage = handle->rinfo.reset_state; 1128 reset_cnt = ops->ae_dev_reset_cnt(handle); 1129 if (reset_cnt != hr_dev->reset_cnt) 1130 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1131 reset_stage); 1132 1133 hw_resetting = ops->get_cmdq_stat(handle); 1134 if (hw_resetting) 1135 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1136 reset_stage); 1137 1138 sw_resetting = ops->ae_dev_resetting(handle); 1139 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1140 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1141 1142 return CMD_RST_PRC_OTHERS; 1143 } 1144 1145 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1146 { 1147 struct hns_roce_v2_priv *priv = hr_dev->priv; 1148 struct hnae3_handle *handle = priv->handle; 1149 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1150 1151 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1152 return true; 1153 1154 if (ops->get_hw_reset_stat(handle)) 1155 return true; 1156 1157 if (ops->ae_dev_resetting(handle)) 1158 return true; 1159 1160 return false; 1161 } 1162 1163 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1164 { 1165 struct hns_roce_v2_priv *priv = hr_dev->priv; 1166 u32 status; 1167 1168 if (hr_dev->is_reset) 1169 status = CMD_RST_PRC_SUCCESS; 1170 else 1171 status = check_aedev_reset_status(hr_dev, priv->handle); 1172 1173 *busy = (status == CMD_RST_PRC_EBUSY); 1174 1175 return status == CMD_RST_PRC_OTHERS; 1176 } 1177 1178 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1179 struct hns_roce_v2_cmq_ring *ring) 1180 { 1181 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1182 1183 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1184 &ring->desc_dma_addr, GFP_KERNEL); 1185 if (!ring->desc) 1186 return -ENOMEM; 1187 1188 return 0; 1189 } 1190 1191 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1192 struct hns_roce_v2_cmq_ring *ring) 1193 { 1194 dma_free_coherent(hr_dev->dev, 1195 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1196 ring->desc, ring->desc_dma_addr); 1197 1198 ring->desc_dma_addr = 0; 1199 } 1200 1201 static int init_csq(struct hns_roce_dev *hr_dev, 1202 struct hns_roce_v2_cmq_ring *csq) 1203 { 1204 dma_addr_t dma; 1205 int ret; 1206 1207 csq->desc_num = CMD_CSQ_DESC_NUM; 1208 spin_lock_init(&csq->lock); 1209 csq->flag = TYPE_CSQ; 1210 csq->head = 0; 1211 1212 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1213 if (ret) 1214 return ret; 1215 1216 dma = csq->desc_dma_addr; 1217 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1218 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1219 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1220 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1221 1222 /* Make sure to write CI first and then PI */ 1223 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1224 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1225 1226 return 0; 1227 } 1228 1229 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1230 { 1231 struct hns_roce_v2_priv *priv = hr_dev->priv; 1232 int ret; 1233 1234 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1235 1236 ret = init_csq(hr_dev, &priv->cmq.csq); 1237 if (ret) 1238 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1239 1240 return ret; 1241 } 1242 1243 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1244 { 1245 struct hns_roce_v2_priv *priv = hr_dev->priv; 1246 1247 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1248 } 1249 1250 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1251 enum hns_roce_opcode_type opcode, 1252 bool is_read) 1253 { 1254 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1255 desc->opcode = cpu_to_le16(opcode); 1256 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1257 if (is_read) 1258 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1259 else 1260 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1261 } 1262 1263 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1264 { 1265 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1266 struct hns_roce_v2_priv *priv = hr_dev->priv; 1267 1268 return tail == priv->cmq.csq.head; 1269 } 1270 1271 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1272 { 1273 struct hns_roce_v2_priv *priv = hr_dev->priv; 1274 struct hnae3_handle *handle = priv->handle; 1275 1276 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1277 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1278 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1279 } 1280 1281 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1282 struct hns_roce_cmq_desc *desc, int num) 1283 { 1284 struct hns_roce_v2_priv *priv = hr_dev->priv; 1285 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1286 u32 timeout = 0; 1287 u16 desc_ret; 1288 u32 tail; 1289 int ret; 1290 int i; 1291 1292 spin_lock_bh(&csq->lock); 1293 1294 tail = csq->head; 1295 1296 for (i = 0; i < num; i++) { 1297 csq->desc[csq->head++] = desc[i]; 1298 if (csq->head == csq->desc_num) 1299 csq->head = 0; 1300 } 1301 1302 /* Write to hardware */ 1303 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1304 1305 do { 1306 if (hns_roce_cmq_csq_done(hr_dev)) 1307 break; 1308 udelay(1); 1309 } while (++timeout < priv->cmq.tx_timeout); 1310 1311 if (hns_roce_cmq_csq_done(hr_dev)) { 1312 ret = 0; 1313 for (i = 0; i < num; i++) { 1314 /* check the result of hardware write back */ 1315 desc[i] = csq->desc[tail++]; 1316 if (tail == csq->desc_num) 1317 tail = 0; 1318 1319 desc_ret = le16_to_cpu(desc[i].retval); 1320 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1321 continue; 1322 1323 dev_err_ratelimited(hr_dev->dev, 1324 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1325 desc->opcode, desc_ret); 1326 ret = -EIO; 1327 } 1328 } else { 1329 /* FW/HW reset or incorrect number of desc */ 1330 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1331 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1332 csq->head, tail); 1333 csq->head = tail; 1334 1335 update_cmdq_status(hr_dev); 1336 1337 ret = -EAGAIN; 1338 } 1339 1340 spin_unlock_bh(&csq->lock); 1341 1342 return ret; 1343 } 1344 1345 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1346 struct hns_roce_cmq_desc *desc, int num) 1347 { 1348 bool busy; 1349 int ret; 1350 1351 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1352 return -EIO; 1353 1354 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1355 return busy ? -EBUSY : 0; 1356 1357 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1358 if (ret) { 1359 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1360 return busy ? -EBUSY : 0; 1361 } 1362 1363 return ret; 1364 } 1365 1366 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1367 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1368 { 1369 struct hns_roce_cmd_mailbox *mbox; 1370 int ret; 1371 1372 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1373 if (IS_ERR(mbox)) 1374 return PTR_ERR(mbox); 1375 1376 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1377 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1378 return ret; 1379 } 1380 1381 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1382 { 1383 struct hns_roce_query_version *resp; 1384 struct hns_roce_cmq_desc desc; 1385 int ret; 1386 1387 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1388 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1389 if (ret) 1390 return ret; 1391 1392 resp = (struct hns_roce_query_version *)desc.data; 1393 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1394 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1395 1396 return 0; 1397 } 1398 1399 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1400 struct hnae3_handle *handle) 1401 { 1402 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1403 unsigned long end; 1404 1405 hr_dev->dis_db = true; 1406 1407 dev_warn(hr_dev->dev, 1408 "func clear is pending, device in resetting state.\n"); 1409 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1410 while (end) { 1411 if (!ops->get_hw_reset_stat(handle)) { 1412 hr_dev->is_reset = true; 1413 dev_info(hr_dev->dev, 1414 "func clear success after reset.\n"); 1415 return; 1416 } 1417 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1418 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1419 } 1420 1421 dev_warn(hr_dev->dev, "func clear failed.\n"); 1422 } 1423 1424 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1425 struct hnae3_handle *handle) 1426 { 1427 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1428 unsigned long end; 1429 1430 hr_dev->dis_db = true; 1431 1432 dev_warn(hr_dev->dev, 1433 "func clear is pending, device in resetting state.\n"); 1434 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1435 while (end) { 1436 if (ops->ae_dev_reset_cnt(handle) != 1437 hr_dev->reset_cnt) { 1438 hr_dev->is_reset = true; 1439 dev_info(hr_dev->dev, 1440 "func clear success after sw reset\n"); 1441 return; 1442 } 1443 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1444 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1445 } 1446 1447 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1448 } 1449 1450 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1451 int flag) 1452 { 1453 struct hns_roce_v2_priv *priv = hr_dev->priv; 1454 struct hnae3_handle *handle = priv->handle; 1455 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1456 1457 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1458 hr_dev->dis_db = true; 1459 hr_dev->is_reset = true; 1460 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1461 return; 1462 } 1463 1464 if (ops->get_hw_reset_stat(handle)) { 1465 func_clr_hw_resetting_state(hr_dev, handle); 1466 return; 1467 } 1468 1469 if (ops->ae_dev_resetting(handle) && 1470 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1471 func_clr_sw_resetting_state(hr_dev, handle); 1472 return; 1473 } 1474 1475 if (retval && !flag) 1476 dev_warn(hr_dev->dev, 1477 "func clear read failed, ret = %d.\n", retval); 1478 1479 dev_warn(hr_dev->dev, "func clear failed.\n"); 1480 } 1481 1482 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1483 { 1484 bool fclr_write_fail_flag = false; 1485 struct hns_roce_func_clear *resp; 1486 struct hns_roce_cmq_desc desc; 1487 unsigned long end; 1488 int ret = 0; 1489 1490 if (check_device_is_in_reset(hr_dev)) 1491 goto out; 1492 1493 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1494 resp = (struct hns_roce_func_clear *)desc.data; 1495 resp->rst_funcid_en = cpu_to_le32(vf_id); 1496 1497 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1498 if (ret) { 1499 fclr_write_fail_flag = true; 1500 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1501 ret); 1502 goto out; 1503 } 1504 1505 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1506 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1507 while (end) { 1508 if (check_device_is_in_reset(hr_dev)) 1509 goto out; 1510 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1511 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1512 1513 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1514 true); 1515 1516 resp->rst_funcid_en = cpu_to_le32(vf_id); 1517 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1518 if (ret) 1519 continue; 1520 1521 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1522 if (vf_id == 0) 1523 hr_dev->is_reset = true; 1524 return; 1525 } 1526 } 1527 1528 out: 1529 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1530 } 1531 1532 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1533 { 1534 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1535 struct hns_roce_cmq_desc desc[2]; 1536 struct hns_roce_cmq_req *req_a; 1537 1538 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1539 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1540 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1541 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1542 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1543 1544 return hns_roce_cmq_send(hr_dev, desc, 2); 1545 } 1546 1547 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1548 { 1549 int ret; 1550 int i; 1551 1552 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1553 return; 1554 1555 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1556 __hns_roce_function_clear(hr_dev, i); 1557 1558 if (i == 0) 1559 continue; 1560 1561 ret = hns_roce_free_vf_resource(hr_dev, i); 1562 if (ret) 1563 ibdev_err(&hr_dev->ib_dev, 1564 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1565 i, ret); 1566 } 1567 } 1568 1569 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1570 { 1571 struct hns_roce_cmq_desc desc; 1572 int ret; 1573 1574 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1575 false); 1576 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1577 if (ret) 1578 ibdev_err(&hr_dev->ib_dev, 1579 "failed to clear extended doorbell info, ret = %d.\n", 1580 ret); 1581 1582 return ret; 1583 } 1584 1585 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1586 { 1587 struct hns_roce_query_fw_info *resp; 1588 struct hns_roce_cmq_desc desc; 1589 int ret; 1590 1591 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1592 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1593 if (ret) 1594 return ret; 1595 1596 resp = (struct hns_roce_query_fw_info *)desc.data; 1597 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1598 1599 return 0; 1600 } 1601 1602 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1603 { 1604 struct hns_roce_cmq_desc desc; 1605 int ret; 1606 1607 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1608 hr_dev->func_num = 1; 1609 return 0; 1610 } 1611 1612 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1613 true); 1614 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1615 if (ret) { 1616 hr_dev->func_num = 1; 1617 return ret; 1618 } 1619 1620 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1621 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1622 1623 return 0; 1624 } 1625 1626 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1627 { 1628 struct hns_roce_cmq_desc desc; 1629 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1630 u32 clock_cycles_of_1us; 1631 1632 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1633 false); 1634 1635 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1636 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1637 else 1638 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1639 1640 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1641 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1642 1643 return hns_roce_cmq_send(hr_dev, &desc, 1); 1644 } 1645 1646 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1647 { 1648 struct hns_roce_cmq_desc desc[2]; 1649 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1650 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1651 struct hns_roce_caps *caps = &hr_dev->caps; 1652 enum hns_roce_opcode_type opcode; 1653 u32 func_num; 1654 int ret; 1655 1656 if (is_vf) { 1657 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1658 func_num = 1; 1659 } else { 1660 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1661 func_num = hr_dev->func_num; 1662 } 1663 1664 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1665 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1666 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1667 1668 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1669 if (ret) 1670 return ret; 1671 1672 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1673 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1674 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1675 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1676 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1677 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1678 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1679 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1680 1681 if (is_vf) { 1682 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1683 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1684 func_num; 1685 } else { 1686 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1687 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1688 func_num; 1689 } 1690 1691 return 0; 1692 } 1693 1694 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1695 { 1696 struct hns_roce_cmq_desc desc; 1697 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1698 struct hns_roce_caps *caps = &hr_dev->caps; 1699 u32 func_num, qp_num; 1700 int ret; 1701 1702 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true); 1703 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1704 if (ret) 1705 return ret; 1706 1707 func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num); 1708 qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num; 1709 caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1710 1711 qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num; 1712 caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1713 1714 return 0; 1715 } 1716 1717 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1718 { 1719 struct hns_roce_cmq_desc desc; 1720 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1721 struct hns_roce_caps *caps = &hr_dev->caps; 1722 int ret; 1723 1724 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1725 true); 1726 1727 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1728 if (ret) 1729 return ret; 1730 1731 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1732 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1733 1734 return 0; 1735 } 1736 1737 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1738 { 1739 struct device *dev = hr_dev->dev; 1740 int ret; 1741 1742 ret = load_func_res_caps(hr_dev, is_vf); 1743 if (ret) { 1744 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret, 1745 is_vf ? "vf" : "pf"); 1746 return ret; 1747 } 1748 1749 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1750 ret = load_ext_cfg_caps(hr_dev, is_vf); 1751 if (ret) 1752 dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n", 1753 ret, is_vf ? "vf" : "pf"); 1754 } 1755 1756 return ret; 1757 } 1758 1759 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1760 { 1761 struct device *dev = hr_dev->dev; 1762 int ret; 1763 1764 ret = query_func_resource_caps(hr_dev, false); 1765 if (ret) 1766 return ret; 1767 1768 ret = load_pf_timer_res_caps(hr_dev); 1769 if (ret) 1770 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1771 ret); 1772 1773 return ret; 1774 } 1775 1776 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1777 { 1778 return query_func_resource_caps(hr_dev, true); 1779 } 1780 1781 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1782 u32 vf_id) 1783 { 1784 struct hns_roce_vf_switch *swt; 1785 struct hns_roce_cmq_desc desc; 1786 int ret; 1787 1788 swt = (struct hns_roce_vf_switch *)desc.data; 1789 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1790 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1791 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1792 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1793 if (ret) 1794 return ret; 1795 1796 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1797 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1798 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1799 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1800 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1801 1802 return hns_roce_cmq_send(hr_dev, &desc, 1); 1803 } 1804 1805 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1806 { 1807 u32 vf_id; 1808 int ret; 1809 1810 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1811 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1812 if (ret) 1813 return ret; 1814 } 1815 return 0; 1816 } 1817 1818 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1819 { 1820 struct hns_roce_cmq_desc desc[2]; 1821 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1822 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1823 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1824 struct hns_roce_caps *caps = &hr_dev->caps; 1825 1826 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1827 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1828 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1829 1830 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1831 1832 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1833 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1834 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1835 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1836 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1837 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1838 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1839 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1840 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1841 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1842 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1843 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1844 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1845 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1846 1847 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1848 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1849 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1850 vf_id * caps->gmv_bt_num); 1851 } else { 1852 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1853 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1854 vf_id * caps->sgid_bt_num); 1855 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1856 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1857 vf_id * caps->smac_bt_num); 1858 } 1859 1860 return hns_roce_cmq_send(hr_dev, desc, 2); 1861 } 1862 1863 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id) 1864 { 1865 struct hns_roce_cmq_desc desc; 1866 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1867 struct hns_roce_caps *caps = &hr_dev->caps; 1868 1869 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false); 1870 1871 hr_reg_write(req, EXT_CFG_VF_ID, vf_id); 1872 1873 hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps); 1874 hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps); 1875 hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps); 1876 hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps); 1877 1878 return hns_roce_cmq_send(hr_dev, &desc, 1); 1879 } 1880 1881 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1882 { 1883 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1884 u32 vf_id; 1885 int ret; 1886 1887 for (vf_id = 0; vf_id < func_num; vf_id++) { 1888 ret = config_vf_hem_resource(hr_dev, vf_id); 1889 if (ret) { 1890 dev_err(hr_dev->dev, 1891 "failed to config vf-%u hem res, ret = %d.\n", 1892 vf_id, ret); 1893 return ret; 1894 } 1895 1896 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1897 ret = config_vf_ext_resource(hr_dev, vf_id); 1898 if (ret) { 1899 dev_err(hr_dev->dev, 1900 "failed to config vf-%u ext res, ret = %d.\n", 1901 vf_id, ret); 1902 return ret; 1903 } 1904 } 1905 } 1906 1907 return 0; 1908 } 1909 1910 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1911 { 1912 struct hns_roce_cmq_desc desc; 1913 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1914 struct hns_roce_caps *caps = &hr_dev->caps; 1915 1916 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1917 1918 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1919 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1920 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1921 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1922 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1923 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1924 1925 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1926 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1927 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1928 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1929 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1930 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1931 1932 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1933 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1934 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1935 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1936 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1937 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1938 1939 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1940 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1941 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1942 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1943 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1944 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1945 1946 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1947 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1948 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1949 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1950 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1951 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1952 1953 return hns_roce_cmq_send(hr_dev, &desc, 1); 1954 } 1955 1956 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */ 1957 static void set_default_caps(struct hns_roce_dev *hr_dev) 1958 { 1959 struct hns_roce_caps *caps = &hr_dev->caps; 1960 1961 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1962 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1963 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1964 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1965 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1966 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1967 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1968 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1969 1970 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1971 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1972 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1973 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1974 caps->num_comp_vectors = 0; 1975 1976 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1977 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1978 caps->qpc_timer_bt_num = HNS_ROCE_V2_MAX_QPC_TIMER_BT_NUM; 1979 caps->cqc_timer_bt_num = HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM; 1980 1981 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1982 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1983 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1984 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1985 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1986 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1987 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1988 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1989 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1990 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1991 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1992 caps->reserved_lkey = 0; 1993 caps->reserved_pds = 0; 1994 caps->reserved_mrws = 1; 1995 caps->reserved_uars = 0; 1996 caps->reserved_cqs = 0; 1997 caps->reserved_srqs = 0; 1998 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 1999 2000 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 2001 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 2002 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 2003 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 2004 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 2005 2006 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 2007 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 2008 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 2009 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 2010 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 2011 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 2012 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 2013 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 2014 2015 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 2016 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 2017 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB | 2018 HNS_ROCE_CAP_FLAG_QP_RECORD_DB; 2019 2020 caps->pkey_table_len[0] = 1; 2021 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 2022 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 2023 caps->local_ca_ack_delay = 0; 2024 caps->max_mtu = IB_MTU_4096; 2025 2026 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 2027 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 2028 2029 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 2030 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 2031 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC; 2032 2033 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 2034 2035 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2036 caps->flags |= HNS_ROCE_CAP_FLAG_STASH | 2037 HNS_ROCE_CAP_FLAG_DIRECT_WQE; 2038 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE; 2039 } else { 2040 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 2041 2042 /* The following configuration are only valid for HIP08 */ 2043 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; 2044 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; 2045 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; 2046 } 2047 } 2048 2049 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2050 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2051 { 2052 u64 obj_per_chunk; 2053 u64 bt_chunk_size = PAGE_SIZE; 2054 u64 buf_chunk_size = PAGE_SIZE; 2055 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2056 2057 *buf_page_size = 0; 2058 *bt_page_size = 0; 2059 2060 switch (hop_num) { 2061 case 3: 2062 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2063 (bt_chunk_size / BA_BYTE_LEN) * 2064 (bt_chunk_size / BA_BYTE_LEN) * 2065 obj_per_chunk_default; 2066 break; 2067 case 2: 2068 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2069 (bt_chunk_size / BA_BYTE_LEN) * 2070 obj_per_chunk_default; 2071 break; 2072 case 1: 2073 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2074 obj_per_chunk_default; 2075 break; 2076 case HNS_ROCE_HOP_NUM_0: 2077 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2078 break; 2079 default: 2080 pr_err("table %u not support hop_num = %u!\n", hem_type, 2081 hop_num); 2082 return; 2083 } 2084 2085 if (hem_type >= HEM_TYPE_MTT) 2086 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2087 else 2088 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2089 } 2090 2091 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2092 { 2093 struct hns_roce_caps *caps = &hr_dev->caps; 2094 2095 /* EQ */ 2096 caps->eqe_ba_pg_sz = 0; 2097 caps->eqe_buf_pg_sz = 0; 2098 2099 /* Link Table */ 2100 caps->llm_buf_pg_sz = 0; 2101 2102 /* MR */ 2103 caps->mpt_ba_pg_sz = 0; 2104 caps->mpt_buf_pg_sz = 0; 2105 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2106 caps->pbl_buf_pg_sz = 0; 2107 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2108 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2109 HEM_TYPE_MTPT); 2110 2111 /* QP */ 2112 caps->qpc_ba_pg_sz = 0; 2113 caps->qpc_buf_pg_sz = 0; 2114 caps->qpc_timer_ba_pg_sz = 0; 2115 caps->qpc_timer_buf_pg_sz = 0; 2116 caps->sccc_ba_pg_sz = 0; 2117 caps->sccc_buf_pg_sz = 0; 2118 caps->mtt_ba_pg_sz = 0; 2119 caps->mtt_buf_pg_sz = 0; 2120 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2121 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2122 HEM_TYPE_QPC); 2123 2124 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2125 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2126 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2127 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2128 2129 /* CQ */ 2130 caps->cqc_ba_pg_sz = 0; 2131 caps->cqc_buf_pg_sz = 0; 2132 caps->cqc_timer_ba_pg_sz = 0; 2133 caps->cqc_timer_buf_pg_sz = 0; 2134 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2135 caps->cqe_buf_pg_sz = 0; 2136 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2137 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2138 HEM_TYPE_CQC); 2139 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2140 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2141 2142 /* SRQ */ 2143 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2144 caps->srqc_ba_pg_sz = 0; 2145 caps->srqc_buf_pg_sz = 0; 2146 caps->srqwqe_ba_pg_sz = 0; 2147 caps->srqwqe_buf_pg_sz = 0; 2148 caps->idx_ba_pg_sz = 0; 2149 caps->idx_buf_pg_sz = 0; 2150 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2151 caps->srqc_hop_num, caps->srqc_bt_num, 2152 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2153 HEM_TYPE_SRQC); 2154 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2155 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2156 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2157 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2158 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2159 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2160 } 2161 2162 /* GMV */ 2163 caps->gmv_ba_pg_sz = 0; 2164 caps->gmv_buf_pg_sz = 0; 2165 } 2166 2167 /* Apply all loaded caps before setting to hardware */ 2168 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2169 { 2170 struct hns_roce_caps *caps = &hr_dev->caps; 2171 struct hns_roce_v2_priv *priv = hr_dev->priv; 2172 2173 /* The following configurations don't need to be got from firmware. */ 2174 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2175 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2176 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2177 2178 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2179 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2180 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2181 2182 caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; 2183 caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; 2184 2185 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2186 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2187 2188 if (!caps->num_comp_vectors) 2189 caps->num_comp_vectors = 2190 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2191 (u32)priv->handle->rinfo.num_vectors - 2192 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2193 2194 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2195 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2196 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2197 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2198 2199 /* The following configurations will be overwritten */ 2200 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2201 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2202 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2203 2204 /* The following configurations are not got from firmware */ 2205 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2206 2207 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2208 caps->gid_table_len[0] = caps->gmv_bt_num * 2209 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2210 2211 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2212 caps->gmv_entry_sz); 2213 } else { 2214 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2215 2216 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2217 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2218 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2219 caps->gid_table_len[0] /= func_num; 2220 } 2221 2222 if (hr_dev->is_vf) { 2223 caps->default_aeq_arm_st = 0x3; 2224 caps->default_ceq_arm_st = 0x3; 2225 caps->default_ceq_max_cnt = 0x1; 2226 caps->default_ceq_period = 0x10; 2227 caps->default_aeq_max_cnt = 0x1; 2228 caps->default_aeq_period = 0x10; 2229 } 2230 2231 set_hem_page_size(hr_dev); 2232 } 2233 2234 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 2235 { 2236 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2237 struct hns_roce_caps *caps = &hr_dev->caps; 2238 struct hns_roce_query_pf_caps_a *resp_a; 2239 struct hns_roce_query_pf_caps_b *resp_b; 2240 struct hns_roce_query_pf_caps_c *resp_c; 2241 struct hns_roce_query_pf_caps_d *resp_d; 2242 struct hns_roce_query_pf_caps_e *resp_e; 2243 int ctx_hop_num; 2244 int pbl_hop_num; 2245 int ret; 2246 int i; 2247 2248 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2249 hns_roce_cmq_setup_basic_desc(&desc[i], 2250 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 2251 true); 2252 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2253 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2254 else 2255 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2256 } 2257 2258 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2259 if (ret) 2260 return ret; 2261 2262 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2263 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2264 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2265 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2266 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2267 2268 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2269 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2270 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2271 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2272 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2273 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2274 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2275 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2276 caps->num_other_vectors = resp_a->num_other_vectors; 2277 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2278 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2279 caps->cqe_sz = resp_a->cqe_sz; 2280 2281 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2282 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2283 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2284 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2285 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2286 caps->idx_entry_sz = resp_b->idx_entry_sz; 2287 caps->sccc_sz = resp_b->sccc_sz; 2288 caps->max_mtu = resp_b->max_mtu; 2289 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2290 caps->min_cqes = resp_b->min_cqes; 2291 caps->min_wqes = resp_b->min_wqes; 2292 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2293 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2294 caps->phy_num_uars = resp_b->phy_num_uars; 2295 ctx_hop_num = resp_b->ctx_hop_num; 2296 pbl_hop_num = resp_b->pbl_hop_num; 2297 2298 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2299 2300 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2301 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2302 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2303 2304 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2305 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2306 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2307 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2308 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2309 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2310 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2311 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2312 2313 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2314 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE); 2315 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2316 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2317 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2318 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2319 caps->default_aeq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2320 caps->default_ceq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2321 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2322 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2323 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2324 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2325 2326 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2327 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2328 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2329 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2330 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2331 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2332 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2333 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2334 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2335 2336 caps->qpc_hop_num = ctx_hop_num; 2337 caps->sccc_hop_num = ctx_hop_num; 2338 caps->srqc_hop_num = ctx_hop_num; 2339 caps->cqc_hop_num = ctx_hop_num; 2340 caps->mpt_hop_num = ctx_hop_num; 2341 caps->mtt_hop_num = pbl_hop_num; 2342 caps->cqe_hop_num = pbl_hop_num; 2343 caps->srqwqe_hop_num = pbl_hop_num; 2344 caps->idx_hop_num = pbl_hop_num; 2345 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2346 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2347 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2348 2349 return 0; 2350 } 2351 2352 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2353 { 2354 struct hns_roce_cmq_desc desc; 2355 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2356 2357 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2358 false); 2359 2360 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2361 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2362 2363 return hns_roce_cmq_send(hr_dev, &desc, 1); 2364 } 2365 2366 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2367 { 2368 struct hns_roce_caps *caps = &hr_dev->caps; 2369 int ret; 2370 2371 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2372 return 0; 2373 2374 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2375 caps->qpc_sz); 2376 if (ret) { 2377 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2378 return ret; 2379 } 2380 2381 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2382 caps->sccc_sz); 2383 if (ret) 2384 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2385 2386 return ret; 2387 } 2388 2389 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2390 { 2391 struct device *dev = hr_dev->dev; 2392 int ret; 2393 2394 hr_dev->func_num = 1; 2395 2396 set_default_caps(hr_dev); 2397 2398 ret = hns_roce_query_vf_resource(hr_dev); 2399 if (ret) { 2400 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2401 return ret; 2402 } 2403 2404 apply_func_caps(hr_dev); 2405 2406 ret = hns_roce_v2_set_bt(hr_dev); 2407 if (ret) 2408 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2409 2410 return ret; 2411 } 2412 2413 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2414 { 2415 struct device *dev = hr_dev->dev; 2416 int ret; 2417 2418 ret = hns_roce_query_func_info(hr_dev); 2419 if (ret) { 2420 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2421 return ret; 2422 } 2423 2424 ret = hns_roce_config_global_param(hr_dev); 2425 if (ret) { 2426 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2427 return ret; 2428 } 2429 2430 ret = hns_roce_set_vf_switch_param(hr_dev); 2431 if (ret) { 2432 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2433 return ret; 2434 } 2435 2436 ret = hns_roce_query_pf_caps(hr_dev); 2437 if (ret) 2438 set_default_caps(hr_dev); 2439 2440 ret = hns_roce_query_pf_resource(hr_dev); 2441 if (ret) { 2442 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2443 return ret; 2444 } 2445 2446 apply_func_caps(hr_dev); 2447 2448 ret = hns_roce_alloc_vf_resource(hr_dev); 2449 if (ret) { 2450 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2451 return ret; 2452 } 2453 2454 ret = hns_roce_v2_set_bt(hr_dev); 2455 if (ret) { 2456 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2457 return ret; 2458 } 2459 2460 /* Configure the size of QPC, SCCC, etc. */ 2461 return hns_roce_config_entry_size(hr_dev); 2462 } 2463 2464 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2465 { 2466 struct device *dev = hr_dev->dev; 2467 int ret; 2468 2469 ret = hns_roce_cmq_query_hw_info(hr_dev); 2470 if (ret) { 2471 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2472 return ret; 2473 } 2474 2475 ret = hns_roce_query_fw_ver(hr_dev); 2476 if (ret) { 2477 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2478 return ret; 2479 } 2480 2481 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2482 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2483 2484 if (hr_dev->is_vf) 2485 return hns_roce_v2_vf_profile(hr_dev); 2486 else 2487 return hns_roce_v2_pf_profile(hr_dev); 2488 } 2489 2490 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2491 { 2492 u32 i, next_ptr, page_num; 2493 __le64 *entry = cfg_buf; 2494 dma_addr_t addr; 2495 u64 val; 2496 2497 page_num = data_buf->npages; 2498 for (i = 0; i < page_num; i++) { 2499 addr = hns_roce_buf_page(data_buf, i); 2500 if (i == (page_num - 1)) 2501 next_ptr = 0; 2502 else 2503 next_ptr = i + 1; 2504 2505 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2506 entry[i] = cpu_to_le64(val); 2507 } 2508 } 2509 2510 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2511 struct hns_roce_link_table *table) 2512 { 2513 struct hns_roce_cmq_desc desc[2]; 2514 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2515 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2516 struct hns_roce_buf *buf = table->buf; 2517 enum hns_roce_opcode_type opcode; 2518 dma_addr_t addr; 2519 2520 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2521 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2522 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2523 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2524 2525 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2526 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2527 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2528 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2529 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2530 2531 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2532 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2533 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2534 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2535 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2536 2537 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2538 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2539 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2540 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2541 2542 return hns_roce_cmq_send(hr_dev, desc, 2); 2543 } 2544 2545 static struct hns_roce_link_table * 2546 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2547 { 2548 struct hns_roce_v2_priv *priv = hr_dev->priv; 2549 struct hns_roce_link_table *link_tbl; 2550 u32 pg_shift, size, min_size; 2551 2552 link_tbl = &priv->ext_llm; 2553 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2554 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2555 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2556 2557 /* Alloc data table */ 2558 size = max(size, min_size); 2559 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2560 if (IS_ERR(link_tbl->buf)) 2561 return ERR_PTR(-ENOMEM); 2562 2563 /* Alloc config table */ 2564 size = link_tbl->buf->npages * sizeof(u64); 2565 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2566 &link_tbl->table.map, 2567 GFP_KERNEL); 2568 if (!link_tbl->table.buf) { 2569 hns_roce_buf_free(hr_dev, link_tbl->buf); 2570 return ERR_PTR(-ENOMEM); 2571 } 2572 2573 return link_tbl; 2574 } 2575 2576 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2577 struct hns_roce_link_table *tbl) 2578 { 2579 if (tbl->buf) { 2580 u32 size = tbl->buf->npages * sizeof(u64); 2581 2582 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2583 tbl->table.map); 2584 } 2585 2586 hns_roce_buf_free(hr_dev, tbl->buf); 2587 } 2588 2589 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2590 { 2591 struct hns_roce_link_table *link_tbl; 2592 int ret; 2593 2594 link_tbl = alloc_link_table_buf(hr_dev); 2595 if (IS_ERR(link_tbl)) 2596 return -ENOMEM; 2597 2598 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2599 ret = -EINVAL; 2600 goto err_alloc; 2601 } 2602 2603 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2604 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2605 if (ret) 2606 goto err_alloc; 2607 2608 return 0; 2609 2610 err_alloc: 2611 free_link_table_buf(hr_dev, link_tbl); 2612 return ret; 2613 } 2614 2615 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2616 { 2617 struct hns_roce_v2_priv *priv = hr_dev->priv; 2618 2619 free_link_table_buf(hr_dev, &priv->ext_llm); 2620 } 2621 2622 static void free_dip_list(struct hns_roce_dev *hr_dev) 2623 { 2624 struct hns_roce_dip *hr_dip; 2625 struct hns_roce_dip *tmp; 2626 unsigned long flags; 2627 2628 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2629 2630 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2631 list_del(&hr_dip->node); 2632 kfree(hr_dip); 2633 } 2634 2635 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2636 } 2637 2638 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2639 { 2640 struct hns_roce_v2_priv *priv = hr_dev->priv; 2641 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2642 int ret; 2643 int i; 2644 2645 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2646 if (free_mr->rsv_qp[i]) { 2647 ret = ib_destroy_qp(free_mr->rsv_qp[i]); 2648 if (ret) 2649 ibdev_err(&hr_dev->ib_dev, 2650 "failed to destroy qp in free mr.\n"); 2651 2652 free_mr->rsv_qp[i] = NULL; 2653 } 2654 } 2655 2656 if (free_mr->rsv_cq) { 2657 ib_destroy_cq(free_mr->rsv_cq); 2658 free_mr->rsv_cq = NULL; 2659 } 2660 2661 if (free_mr->rsv_pd) { 2662 ib_dealloc_pd(free_mr->rsv_pd); 2663 free_mr->rsv_pd = NULL; 2664 } 2665 } 2666 2667 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2668 { 2669 struct hns_roce_v2_priv *priv = hr_dev->priv; 2670 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2671 struct ib_device *ibdev = &hr_dev->ib_dev; 2672 struct ib_cq_init_attr cq_init_attr = {}; 2673 struct ib_qp_init_attr qp_init_attr = {}; 2674 struct ib_pd *pd; 2675 struct ib_cq *cq; 2676 struct ib_qp *qp; 2677 int ret; 2678 int i; 2679 2680 pd = ib_alloc_pd(ibdev, 0); 2681 if (IS_ERR(pd)) { 2682 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2683 return PTR_ERR(pd); 2684 } 2685 free_mr->rsv_pd = pd; 2686 2687 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2688 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_init_attr); 2689 if (IS_ERR(cq)) { 2690 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2691 ret = PTR_ERR(cq); 2692 goto create_failed; 2693 } 2694 free_mr->rsv_cq = cq; 2695 2696 qp_init_attr.qp_type = IB_QPT_RC; 2697 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2698 qp_init_attr.send_cq = free_mr->rsv_cq; 2699 qp_init_attr.recv_cq = free_mr->rsv_cq; 2700 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2701 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2702 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2703 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2704 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2705 2706 qp = ib_create_qp(free_mr->rsv_pd, &qp_init_attr); 2707 if (IS_ERR(qp)) { 2708 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2709 ret = PTR_ERR(qp); 2710 goto create_failed; 2711 } 2712 2713 free_mr->rsv_qp[i] = qp; 2714 } 2715 2716 return 0; 2717 2718 create_failed: 2719 free_mr_exit(hr_dev); 2720 2721 return ret; 2722 } 2723 2724 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2725 struct ib_qp_attr *attr, int sl_num) 2726 { 2727 struct hns_roce_v2_priv *priv = hr_dev->priv; 2728 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2729 struct ib_device *ibdev = &hr_dev->ib_dev; 2730 struct hns_roce_qp *hr_qp; 2731 int loopback; 2732 int mask; 2733 int ret; 2734 2735 hr_qp = to_hr_qp(free_mr->rsv_qp[sl_num]); 2736 hr_qp->free_mr_en = 1; 2737 2738 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2739 attr->qp_state = IB_QPS_INIT; 2740 attr->port_num = 1; 2741 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2742 ret = ib_modify_qp(&hr_qp->ibqp, attr, mask); 2743 if (ret) { 2744 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n", 2745 ret); 2746 return ret; 2747 } 2748 2749 loopback = hr_dev->loop_idc; 2750 /* Set qpc lbi = 1 incidate loopback IO */ 2751 hr_dev->loop_idc = 1; 2752 2753 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2754 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2755 attr->qp_state = IB_QPS_RTR; 2756 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2757 attr->path_mtu = IB_MTU_256; 2758 attr->dest_qp_num = hr_qp->qpn; 2759 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2760 2761 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2762 2763 ret = ib_modify_qp(&hr_qp->ibqp, attr, mask); 2764 hr_dev->loop_idc = loopback; 2765 if (ret) { 2766 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2767 ret); 2768 return ret; 2769 } 2770 2771 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2772 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2773 attr->qp_state = IB_QPS_RTS; 2774 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2775 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2776 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2777 ret = ib_modify_qp(&hr_qp->ibqp, attr, mask); 2778 if (ret) 2779 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2780 ret); 2781 2782 return ret; 2783 } 2784 2785 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2786 { 2787 struct hns_roce_v2_priv *priv = hr_dev->priv; 2788 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2789 struct ib_qp_attr attr = {}; 2790 int ret; 2791 int i; 2792 2793 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2794 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2795 rdma_ah_set_port_num(&attr.ah_attr, 1); 2796 2797 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2798 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2799 if (ret) 2800 return ret; 2801 } 2802 2803 return 0; 2804 } 2805 2806 static int free_mr_init(struct hns_roce_dev *hr_dev) 2807 { 2808 int ret; 2809 2810 ret = free_mr_alloc_res(hr_dev); 2811 if (ret) 2812 return ret; 2813 2814 ret = free_mr_modify_qp(hr_dev); 2815 if (ret) 2816 goto err_modify_qp; 2817 2818 return 0; 2819 2820 err_modify_qp: 2821 free_mr_exit(hr_dev); 2822 2823 return ret; 2824 } 2825 2826 static int get_hem_table(struct hns_roce_dev *hr_dev) 2827 { 2828 unsigned int qpc_count; 2829 unsigned int cqc_count; 2830 unsigned int gmv_count; 2831 int ret; 2832 int i; 2833 2834 /* Alloc memory for source address table buffer space chunk */ 2835 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2836 gmv_count++) { 2837 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2838 if (ret) 2839 goto err_gmv_failed; 2840 } 2841 2842 if (hr_dev->is_vf) 2843 return 0; 2844 2845 /* Alloc memory for QPC Timer buffer space chunk */ 2846 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2847 qpc_count++) { 2848 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2849 qpc_count); 2850 if (ret) { 2851 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2852 goto err_qpc_timer_failed; 2853 } 2854 } 2855 2856 /* Alloc memory for CQC Timer buffer space chunk */ 2857 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2858 cqc_count++) { 2859 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2860 cqc_count); 2861 if (ret) { 2862 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2863 goto err_cqc_timer_failed; 2864 } 2865 } 2866 2867 return 0; 2868 2869 err_cqc_timer_failed: 2870 for (i = 0; i < cqc_count; i++) 2871 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2872 2873 err_qpc_timer_failed: 2874 for (i = 0; i < qpc_count; i++) 2875 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2876 2877 err_gmv_failed: 2878 for (i = 0; i < gmv_count; i++) 2879 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2880 2881 return ret; 2882 } 2883 2884 static void put_hem_table(struct hns_roce_dev *hr_dev) 2885 { 2886 int i; 2887 2888 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2889 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2890 2891 if (hr_dev->is_vf) 2892 return; 2893 2894 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2895 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2896 2897 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2898 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2899 } 2900 2901 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2902 { 2903 int ret; 2904 2905 /* The hns ROCEE requires the extdb info to be cleared before using */ 2906 ret = hns_roce_clear_extdb_list_info(hr_dev); 2907 if (ret) 2908 return ret; 2909 2910 ret = get_hem_table(hr_dev); 2911 if (ret) 2912 return ret; 2913 2914 if (hr_dev->is_vf) 2915 return 0; 2916 2917 ret = hns_roce_init_link_table(hr_dev); 2918 if (ret) { 2919 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2920 goto err_llm_init_failed; 2921 } 2922 2923 return 0; 2924 2925 err_llm_init_failed: 2926 put_hem_table(hr_dev); 2927 2928 return ret; 2929 } 2930 2931 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2932 { 2933 hns_roce_function_clear(hr_dev); 2934 2935 if (!hr_dev->is_vf) 2936 hns_roce_free_link_table(hr_dev); 2937 2938 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2939 free_dip_list(hr_dev); 2940 } 2941 2942 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2943 struct hns_roce_mbox_msg *mbox_msg) 2944 { 2945 struct hns_roce_cmq_desc desc; 2946 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2947 2948 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2949 2950 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2951 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2952 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2953 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2954 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2955 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2956 mbox_msg->token); 2957 2958 return hns_roce_cmq_send(hr_dev, &desc, 1); 2959 } 2960 2961 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2962 u8 *complete_status) 2963 { 2964 struct hns_roce_mbox_status *mb_st; 2965 struct hns_roce_cmq_desc desc; 2966 unsigned long end; 2967 int ret = -EBUSY; 2968 u32 status; 2969 bool busy; 2970 2971 mb_st = (struct hns_roce_mbox_status *)desc.data; 2972 end = msecs_to_jiffies(timeout) + jiffies; 2973 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2974 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 2975 return -EIO; 2976 2977 status = 0; 2978 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2979 true); 2980 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2981 if (!ret) { 2982 status = le32_to_cpu(mb_st->mb_status_hw_run); 2983 /* No pending message exists in ROCEE mbox. */ 2984 if (!(status & MB_ST_HW_RUN_M)) 2985 break; 2986 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2987 break; 2988 } 2989 2990 if (time_after(jiffies, end)) { 2991 dev_err_ratelimited(hr_dev->dev, 2992 "failed to wait mbox status 0x%x\n", 2993 status); 2994 return -ETIMEDOUT; 2995 } 2996 2997 cond_resched(); 2998 ret = -EBUSY; 2999 } 3000 3001 if (!ret) { 3002 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3003 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3004 /* Ignore all errors if the mbox is unavailable. */ 3005 ret = 0; 3006 *complete_status = MB_ST_COMPLETE_M; 3007 } 3008 3009 return ret; 3010 } 3011 3012 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3013 struct hns_roce_mbox_msg *mbox_msg) 3014 { 3015 u8 status = 0; 3016 int ret; 3017 3018 /* Waiting for the mbox to be idle */ 3019 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3020 &status); 3021 if (unlikely(ret)) { 3022 dev_err_ratelimited(hr_dev->dev, 3023 "failed to check post mbox status = 0x%x, ret = %d.\n", 3024 status, ret); 3025 return ret; 3026 } 3027 3028 /* Post new message to mbox */ 3029 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3030 if (ret) 3031 dev_err_ratelimited(hr_dev->dev, 3032 "failed to post mailbox, ret = %d.\n", ret); 3033 3034 return ret; 3035 } 3036 3037 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3038 { 3039 u8 status = 0; 3040 int ret; 3041 3042 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3043 &status); 3044 if (!ret) { 3045 if (status != MB_ST_COMPLETE_SUCC) 3046 return -EBUSY; 3047 } else { 3048 dev_err_ratelimited(hr_dev->dev, 3049 "failed to check mbox status = 0x%x, ret = %d.\n", 3050 status, ret); 3051 } 3052 3053 return ret; 3054 } 3055 3056 static void copy_gid(void *dest, const union ib_gid *gid) 3057 { 3058 #define GID_SIZE 4 3059 const union ib_gid *src = gid; 3060 __le32 (*p)[GID_SIZE] = dest; 3061 int i; 3062 3063 if (!gid) 3064 src = &zgid; 3065 3066 for (i = 0; i < GID_SIZE; i++) 3067 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3068 } 3069 3070 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3071 int gid_index, const union ib_gid *gid, 3072 enum hns_roce_sgid_type sgid_type) 3073 { 3074 struct hns_roce_cmq_desc desc; 3075 struct hns_roce_cfg_sgid_tb *sgid_tb = 3076 (struct hns_roce_cfg_sgid_tb *)desc.data; 3077 3078 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3079 3080 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3081 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3082 3083 copy_gid(&sgid_tb->vf_sgid_l, gid); 3084 3085 return hns_roce_cmq_send(hr_dev, &desc, 1); 3086 } 3087 3088 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3089 int gid_index, const union ib_gid *gid, 3090 enum hns_roce_sgid_type sgid_type, 3091 const struct ib_gid_attr *attr) 3092 { 3093 struct hns_roce_cmq_desc desc[2]; 3094 struct hns_roce_cfg_gmv_tb_a *tb_a = 3095 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3096 struct hns_roce_cfg_gmv_tb_b *tb_b = 3097 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3098 3099 u16 vlan_id = VLAN_CFI_MASK; 3100 u8 mac[ETH_ALEN] = {}; 3101 int ret; 3102 3103 if (gid) { 3104 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3105 if (ret) 3106 return ret; 3107 } 3108 3109 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3110 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3111 3112 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3113 3114 copy_gid(&tb_a->vf_sgid_l, gid); 3115 3116 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3117 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3118 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3119 3120 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3121 3122 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3123 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3124 3125 return hns_roce_cmq_send(hr_dev, desc, 2); 3126 } 3127 3128 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3129 const union ib_gid *gid, 3130 const struct ib_gid_attr *attr) 3131 { 3132 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3133 int ret; 3134 3135 if (gid) { 3136 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3137 if (ipv6_addr_v4mapped((void *)gid)) 3138 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3139 else 3140 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3141 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3142 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3143 } 3144 } 3145 3146 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3147 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3148 else 3149 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3150 3151 if (ret) 3152 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3153 ret); 3154 3155 return ret; 3156 } 3157 3158 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3159 const u8 *addr) 3160 { 3161 struct hns_roce_cmq_desc desc; 3162 struct hns_roce_cfg_smac_tb *smac_tb = 3163 (struct hns_roce_cfg_smac_tb *)desc.data; 3164 u16 reg_smac_h; 3165 u32 reg_smac_l; 3166 3167 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3168 3169 reg_smac_l = *(u32 *)(&addr[0]); 3170 reg_smac_h = *(u16 *)(&addr[4]); 3171 3172 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3173 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3174 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3175 3176 return hns_roce_cmq_send(hr_dev, &desc, 1); 3177 } 3178 3179 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3180 struct hns_roce_v2_mpt_entry *mpt_entry, 3181 struct hns_roce_mr *mr) 3182 { 3183 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3184 struct ib_device *ibdev = &hr_dev->ib_dev; 3185 dma_addr_t pbl_ba; 3186 int i, count; 3187 3188 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3189 ARRAY_SIZE(pages), &pbl_ba); 3190 if (count < 1) { 3191 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3192 count); 3193 return -ENOBUFS; 3194 } 3195 3196 /* Aligned to the hardware address access unit */ 3197 for (i = 0; i < count; i++) 3198 pages[i] >>= 6; 3199 3200 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3201 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3202 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3203 3204 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3205 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3206 3207 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3208 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3209 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3210 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3211 3212 return 0; 3213 } 3214 3215 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3216 void *mb_buf, struct hns_roce_mr *mr) 3217 { 3218 struct hns_roce_v2_mpt_entry *mpt_entry; 3219 3220 mpt_entry = mb_buf; 3221 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3222 3223 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3224 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3225 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 3226 3227 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3228 mr->access & IB_ACCESS_MW_BIND); 3229 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3230 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3231 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3232 mr->access & IB_ACCESS_REMOTE_READ); 3233 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3234 mr->access & IB_ACCESS_REMOTE_WRITE); 3235 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3236 mr->access & IB_ACCESS_LOCAL_WRITE); 3237 3238 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3239 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3240 mpt_entry->lkey = cpu_to_le32(mr->key); 3241 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3242 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3243 3244 if (mr->type != MR_TYPE_MR) 3245 hr_reg_enable(mpt_entry, MPT_PA); 3246 3247 if (mr->type == MR_TYPE_DMA) 3248 return 0; 3249 3250 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3251 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3252 3253 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3254 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3255 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3256 3257 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3258 } 3259 3260 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3261 struct hns_roce_mr *mr, int flags, 3262 void *mb_buf) 3263 { 3264 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3265 u32 mr_access_flags = mr->access; 3266 int ret = 0; 3267 3268 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3269 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3270 3271 if (flags & IB_MR_REREG_ACCESS) { 3272 hr_reg_write(mpt_entry, MPT_BIND_EN, 3273 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3274 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3275 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3276 hr_reg_write(mpt_entry, MPT_RR_EN, 3277 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3278 hr_reg_write(mpt_entry, MPT_RW_EN, 3279 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3280 hr_reg_write(mpt_entry, MPT_LW_EN, 3281 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3282 } 3283 3284 if (flags & IB_MR_REREG_TRANS) { 3285 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3286 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3287 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3288 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3289 3290 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3291 } 3292 3293 return ret; 3294 } 3295 3296 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3297 void *mb_buf, struct hns_roce_mr *mr) 3298 { 3299 struct ib_device *ibdev = &hr_dev->ib_dev; 3300 struct hns_roce_v2_mpt_entry *mpt_entry; 3301 dma_addr_t pbl_ba = 0; 3302 3303 mpt_entry = mb_buf; 3304 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3305 3306 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3307 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3308 return -ENOBUFS; 3309 } 3310 3311 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3312 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3313 3314 hr_reg_enable(mpt_entry, MPT_RA_EN); 3315 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3316 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 3317 3318 hr_reg_enable(mpt_entry, MPT_FRE); 3319 hr_reg_clear(mpt_entry, MPT_MR_MW); 3320 hr_reg_enable(mpt_entry, MPT_BPD); 3321 hr_reg_clear(mpt_entry, MPT_PA); 3322 3323 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3324 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3325 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3326 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3327 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3328 3329 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3330 3331 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3332 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3333 3334 return 0; 3335 } 3336 3337 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3338 { 3339 struct hns_roce_v2_mpt_entry *mpt_entry; 3340 3341 mpt_entry = mb_buf; 3342 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3343 3344 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3345 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3346 3347 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3348 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 3349 hr_reg_enable(mpt_entry, MPT_LW_EN); 3350 3351 hr_reg_enable(mpt_entry, MPT_MR_MW); 3352 hr_reg_enable(mpt_entry, MPT_BPD); 3353 hr_reg_clear(mpt_entry, MPT_PA); 3354 hr_reg_write(mpt_entry, MPT_BQP, 3355 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3356 3357 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3358 3359 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3360 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3361 mw->pbl_hop_num); 3362 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3363 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3364 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3365 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3366 3367 return 0; 3368 } 3369 3370 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3371 { 3372 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3373 struct ib_device *ibdev = &hr_dev->ib_dev; 3374 const struct ib_send_wr *bad_wr; 3375 struct ib_rdma_wr rdma_wr = {}; 3376 struct ib_send_wr *send_wr; 3377 int ret; 3378 3379 send_wr = &rdma_wr.wr; 3380 send_wr->opcode = IB_WR_RDMA_WRITE; 3381 3382 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3383 if (ret) { 3384 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3385 ret); 3386 return ret; 3387 } 3388 3389 return 0; 3390 } 3391 3392 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3393 struct ib_wc *wc); 3394 3395 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3396 { 3397 struct hns_roce_v2_priv *priv = hr_dev->priv; 3398 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3399 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3400 struct ib_device *ibdev = &hr_dev->ib_dev; 3401 struct hns_roce_qp *hr_qp; 3402 unsigned long end; 3403 int cqe_cnt = 0; 3404 int npolled; 3405 int ret; 3406 int i; 3407 3408 /* 3409 * If the device initialization is not complete or in the uninstall 3410 * process, then there is no need to execute free mr. 3411 */ 3412 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3413 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3414 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3415 return; 3416 3417 mutex_lock(&free_mr->mutex); 3418 3419 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3420 hr_qp = to_hr_qp(free_mr->rsv_qp[i]); 3421 3422 ret = free_mr_post_send_lp_wqe(hr_qp); 3423 if (ret) { 3424 ibdev_err(ibdev, 3425 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3426 hr_qp->qpn, ret); 3427 break; 3428 } 3429 3430 cqe_cnt++; 3431 } 3432 3433 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3434 while (cqe_cnt) { 3435 npolled = hns_roce_v2_poll_cq(free_mr->rsv_cq, cqe_cnt, wc); 3436 if (npolled < 0) { 3437 ibdev_err(ibdev, 3438 "failed to poll cqe for free mr, remain %d cqe.\n", 3439 cqe_cnt); 3440 goto out; 3441 } 3442 3443 if (time_after(jiffies, end)) { 3444 ibdev_err(ibdev, 3445 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3446 cqe_cnt); 3447 goto out; 3448 } 3449 cqe_cnt -= npolled; 3450 } 3451 3452 out: 3453 mutex_unlock(&free_mr->mutex); 3454 } 3455 3456 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3457 { 3458 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3459 free_mr_send_cmd_to_hw(hr_dev); 3460 } 3461 3462 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3463 { 3464 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3465 } 3466 3467 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3468 { 3469 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3470 3471 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3472 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3473 NULL; 3474 } 3475 3476 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3477 struct hns_roce_cq *hr_cq) 3478 { 3479 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3480 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3481 } else { 3482 struct hns_roce_v2_db cq_db = {}; 3483 3484 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3485 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3486 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3487 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3488 3489 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3490 } 3491 } 3492 3493 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3494 struct hns_roce_srq *srq) 3495 { 3496 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3497 struct hns_roce_v2_cqe *cqe, *dest; 3498 u32 prod_index; 3499 int nfreed = 0; 3500 int wqe_index; 3501 u8 owner_bit; 3502 3503 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3504 ++prod_index) { 3505 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3506 break; 3507 } 3508 3509 /* 3510 * Now backwards through the CQ, removing CQ entries 3511 * that match our QP by overwriting them with next entries. 3512 */ 3513 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3514 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3515 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3516 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3517 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3518 hns_roce_free_srq_wqe(srq, wqe_index); 3519 } 3520 ++nfreed; 3521 } else if (nfreed) { 3522 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3523 hr_cq->ib_cq.cqe); 3524 owner_bit = hr_reg_read(dest, CQE_OWNER); 3525 memcpy(dest, cqe, hr_cq->cqe_size); 3526 hr_reg_write(dest, CQE_OWNER, owner_bit); 3527 } 3528 } 3529 3530 if (nfreed) { 3531 hr_cq->cons_index += nfreed; 3532 update_cq_db(hr_dev, hr_cq); 3533 } 3534 } 3535 3536 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3537 struct hns_roce_srq *srq) 3538 { 3539 spin_lock_irq(&hr_cq->lock); 3540 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3541 spin_unlock_irq(&hr_cq->lock); 3542 } 3543 3544 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3545 struct hns_roce_cq *hr_cq, void *mb_buf, 3546 u64 *mtts, dma_addr_t dma_handle) 3547 { 3548 struct hns_roce_v2_cq_context *cq_context; 3549 3550 cq_context = mb_buf; 3551 memset(cq_context, 0, sizeof(*cq_context)); 3552 3553 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3554 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3555 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3556 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3557 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3558 3559 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3560 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3561 3562 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3563 hr_reg_enable(cq_context, CQC_STASH); 3564 3565 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3566 to_hr_hw_page_addr(mtts[0])); 3567 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3568 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3569 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3570 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3571 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3572 to_hr_hw_page_addr(mtts[1])); 3573 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3574 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3575 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3576 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3577 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3578 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3579 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3580 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3581 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3582 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3583 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3584 ((u32)hr_cq->db.dma) >> 1); 3585 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3586 hr_cq->db.dma >> 32); 3587 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3588 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3589 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3590 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3591 } 3592 3593 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3594 enum ib_cq_notify_flags flags) 3595 { 3596 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3597 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3598 struct hns_roce_v2_db cq_db = {}; 3599 u32 notify_flag; 3600 3601 /* 3602 * flags = 0, then notify_flag : next 3603 * flags = 1, then notify flag : solocited 3604 */ 3605 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3606 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3607 3608 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3609 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3610 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3611 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3612 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3613 3614 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3615 3616 return 0; 3617 } 3618 3619 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 3620 struct hns_roce_qp *qp, 3621 struct ib_wc *wc) 3622 { 3623 struct hns_roce_rinl_sge *sge_list; 3624 u32 wr_num, wr_cnt, sge_num; 3625 u32 sge_cnt, data_len, size; 3626 void *wqe_buf; 3627 3628 wr_num = hr_reg_read(cqe, CQE_WQE_IDX); 3629 wr_cnt = wr_num & (qp->rq.wqe_cnt - 1); 3630 3631 sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list; 3632 sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 3633 wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt); 3634 data_len = wc->byte_len; 3635 3636 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 3637 size = min(sge_list[sge_cnt].len, data_len); 3638 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 3639 3640 data_len -= size; 3641 wqe_buf += size; 3642 } 3643 3644 if (unlikely(data_len)) { 3645 wc->status = IB_WC_LOC_LEN_ERR; 3646 return -EAGAIN; 3647 } 3648 3649 return 0; 3650 } 3651 3652 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3653 int num_entries, struct ib_wc *wc) 3654 { 3655 unsigned int left; 3656 int npolled = 0; 3657 3658 left = wq->head - wq->tail; 3659 if (left == 0) 3660 return 0; 3661 3662 left = min_t(unsigned int, (unsigned int)num_entries, left); 3663 while (npolled < left) { 3664 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3665 wc->status = IB_WC_WR_FLUSH_ERR; 3666 wc->vendor_err = 0; 3667 wc->qp = &hr_qp->ibqp; 3668 3669 wq->tail++; 3670 wc++; 3671 npolled++; 3672 } 3673 3674 return npolled; 3675 } 3676 3677 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3678 struct ib_wc *wc) 3679 { 3680 struct hns_roce_qp *hr_qp; 3681 int npolled = 0; 3682 3683 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3684 npolled += sw_comp(hr_qp, &hr_qp->sq, 3685 num_entries - npolled, wc + npolled); 3686 if (npolled >= num_entries) 3687 goto out; 3688 } 3689 3690 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3691 npolled += sw_comp(hr_qp, &hr_qp->rq, 3692 num_entries - npolled, wc + npolled); 3693 if (npolled >= num_entries) 3694 goto out; 3695 } 3696 3697 out: 3698 return npolled; 3699 } 3700 3701 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3702 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3703 struct ib_wc *wc) 3704 { 3705 static const struct { 3706 u32 cqe_status; 3707 enum ib_wc_status wc_status; 3708 } map[] = { 3709 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3710 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3711 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3712 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3713 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3714 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3715 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3716 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3717 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3718 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3719 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3720 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3721 IB_WC_RETRY_EXC_ERR }, 3722 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3723 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3724 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3725 }; 3726 3727 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3728 int i; 3729 3730 wc->status = IB_WC_GENERAL_ERR; 3731 for (i = 0; i < ARRAY_SIZE(map); i++) 3732 if (cqe_status == map[i].cqe_status) { 3733 wc->status = map[i].wc_status; 3734 break; 3735 } 3736 3737 if (likely(wc->status == IB_WC_SUCCESS || 3738 wc->status == IB_WC_WR_FLUSH_ERR)) 3739 return; 3740 3741 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3742 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3743 cq->cqe_size, false); 3744 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3745 3746 /* 3747 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3748 * the standard protocol, the driver must ignore it and needn't to set 3749 * the QP to an error state. 3750 */ 3751 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3752 return; 3753 3754 flush_cqe(hr_dev, qp); 3755 } 3756 3757 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3758 struct hns_roce_qp **cur_qp) 3759 { 3760 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3761 struct hns_roce_qp *hr_qp = *cur_qp; 3762 u32 qpn; 3763 3764 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3765 3766 if (!hr_qp || qpn != hr_qp->qpn) { 3767 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3768 if (unlikely(!hr_qp)) { 3769 ibdev_err(&hr_dev->ib_dev, 3770 "CQ %06lx with entry for unknown QPN %06x\n", 3771 hr_cq->cqn, qpn); 3772 return -EINVAL; 3773 } 3774 *cur_qp = hr_qp; 3775 } 3776 3777 return 0; 3778 } 3779 3780 /* 3781 * mapped-value = 1 + real-value 3782 * The ib wc opcode's real value is start from 0, In order to distinguish 3783 * between initialized and uninitialized map values, we plus 1 to the actual 3784 * value when defining the mapping, so that the validity can be identified by 3785 * checking whether the mapped value is greater than 0. 3786 */ 3787 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3788 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3789 3790 static const u32 wc_send_op_map[] = { 3791 HR_WC_OP_MAP(SEND, SEND), 3792 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3793 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3794 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3795 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3796 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3797 HR_WC_OP_MAP(LOCAL_INV, LOCAL_INV), 3798 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3799 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3800 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3801 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3802 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3803 HR_WC_OP_MAP(BIND_MW, REG_MR), 3804 }; 3805 3806 static int to_ib_wc_send_op(u32 hr_opcode) 3807 { 3808 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3809 return -EINVAL; 3810 3811 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3812 -EINVAL; 3813 } 3814 3815 static const u32 wc_recv_op_map[] = { 3816 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3817 HR_WC_OP_MAP(SEND, RECV), 3818 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3819 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3820 }; 3821 3822 static int to_ib_wc_recv_op(u32 hr_opcode) 3823 { 3824 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3825 return -EINVAL; 3826 3827 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3828 -EINVAL; 3829 } 3830 3831 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3832 { 3833 u32 hr_opcode; 3834 int ib_opcode; 3835 3836 wc->wc_flags = 0; 3837 3838 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3839 switch (hr_opcode) { 3840 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3841 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3842 break; 3843 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3844 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3845 wc->wc_flags |= IB_WC_WITH_IMM; 3846 break; 3847 case HNS_ROCE_V2_WQE_OP_LOCAL_INV: 3848 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3849 break; 3850 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3851 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3852 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3853 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3854 wc->byte_len = 8; 3855 break; 3856 default: 3857 break; 3858 } 3859 3860 ib_opcode = to_ib_wc_send_op(hr_opcode); 3861 if (ib_opcode < 0) 3862 wc->status = IB_WC_GENERAL_ERR; 3863 else 3864 wc->opcode = ib_opcode; 3865 } 3866 3867 static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode, 3868 struct hns_roce_v2_cqe *cqe) 3869 { 3870 return wc->qp->qp_type != IB_QPT_UD && wc->qp->qp_type != IB_QPT_GSI && 3871 (hr_opcode == HNS_ROCE_V2_OPCODE_SEND || 3872 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 3873 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 3874 hr_reg_read(cqe, CQE_RQ_INLINE); 3875 } 3876 3877 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3878 { 3879 struct hns_roce_qp *qp = to_hr_qp(wc->qp); 3880 u32 hr_opcode; 3881 int ib_opcode; 3882 int ret; 3883 3884 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3885 3886 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3887 switch (hr_opcode) { 3888 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3889 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3890 wc->wc_flags = IB_WC_WITH_IMM; 3891 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3892 break; 3893 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3894 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3895 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3896 break; 3897 default: 3898 wc->wc_flags = 0; 3899 } 3900 3901 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3902 if (ib_opcode < 0) 3903 wc->status = IB_WC_GENERAL_ERR; 3904 else 3905 wc->opcode = ib_opcode; 3906 3907 if (is_rq_inl_enabled(wc, hr_opcode, cqe)) { 3908 ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc); 3909 if (unlikely(ret)) 3910 return ret; 3911 } 3912 3913 wc->sl = hr_reg_read(cqe, CQE_SL); 3914 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3915 wc->slid = 0; 3916 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3917 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3918 wc->pkey_index = 0; 3919 3920 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3921 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3922 wc->wc_flags |= IB_WC_WITH_VLAN; 3923 } else { 3924 wc->vlan_id = 0xffff; 3925 } 3926 3927 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3928 3929 return 0; 3930 } 3931 3932 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3933 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3934 { 3935 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3936 struct hns_roce_qp *qp = *cur_qp; 3937 struct hns_roce_srq *srq = NULL; 3938 struct hns_roce_v2_cqe *cqe; 3939 struct hns_roce_wq *wq; 3940 int is_send; 3941 u16 wqe_idx; 3942 int ret; 3943 3944 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3945 if (!cqe) 3946 return -EAGAIN; 3947 3948 ++hr_cq->cons_index; 3949 /* Memory barrier */ 3950 rmb(); 3951 3952 ret = get_cur_qp(hr_cq, cqe, &qp); 3953 if (ret) 3954 return ret; 3955 3956 wc->qp = &qp->ibqp; 3957 wc->vendor_err = 0; 3958 3959 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3960 3961 is_send = !hr_reg_read(cqe, CQE_S_R); 3962 if (is_send) { 3963 wq = &qp->sq; 3964 3965 /* If sg_signal_bit is set, tail pointer will be updated to 3966 * the WQE corresponding to the current CQE. 3967 */ 3968 if (qp->sq_signal_bits) 3969 wq->tail += (wqe_idx - (u16)wq->tail) & 3970 (wq->wqe_cnt - 1); 3971 3972 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3973 ++wq->tail; 3974 3975 fill_send_wc(wc, cqe); 3976 } else { 3977 if (qp->ibqp.srq) { 3978 srq = to_hr_srq(qp->ibqp.srq); 3979 wc->wr_id = srq->wrid[wqe_idx]; 3980 hns_roce_free_srq_wqe(srq, wqe_idx); 3981 } else { 3982 wq = &qp->rq; 3983 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3984 ++wq->tail; 3985 } 3986 3987 ret = fill_recv_wc(wc, cqe); 3988 } 3989 3990 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3991 if (unlikely(wc->status != IB_WC_SUCCESS)) 3992 return 0; 3993 3994 return ret; 3995 } 3996 3997 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3998 struct ib_wc *wc) 3999 { 4000 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 4001 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 4002 struct hns_roce_qp *cur_qp = NULL; 4003 unsigned long flags; 4004 int npolled; 4005 4006 spin_lock_irqsave(&hr_cq->lock, flags); 4007 4008 /* 4009 * When the device starts to reset, the state is RST_DOWN. At this time, 4010 * there may still be some valid CQEs in the hardware that are not 4011 * polled. Therefore, it is not allowed to switch to the software mode 4012 * immediately. When the state changes to UNINIT, CQE no longer exists 4013 * in the hardware, and then switch to software mode. 4014 */ 4015 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 4016 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 4017 goto out; 4018 } 4019 4020 for (npolled = 0; npolled < num_entries; ++npolled) { 4021 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 4022 break; 4023 } 4024 4025 if (npolled) 4026 update_cq_db(hr_dev, hr_cq); 4027 4028 out: 4029 spin_unlock_irqrestore(&hr_cq->lock, flags); 4030 4031 return npolled; 4032 } 4033 4034 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4035 u32 step_idx, u8 *mbox_cmd) 4036 { 4037 u8 cmd; 4038 4039 switch (type) { 4040 case HEM_TYPE_QPC: 4041 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4042 break; 4043 case HEM_TYPE_MTPT: 4044 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4045 break; 4046 case HEM_TYPE_CQC: 4047 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4048 break; 4049 case HEM_TYPE_SRQC: 4050 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4051 break; 4052 case HEM_TYPE_SCCC: 4053 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4054 break; 4055 case HEM_TYPE_QPC_TIMER: 4056 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4057 break; 4058 case HEM_TYPE_CQC_TIMER: 4059 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4060 break; 4061 default: 4062 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4063 return -EINVAL; 4064 } 4065 4066 *mbox_cmd = cmd + step_idx; 4067 4068 return 0; 4069 } 4070 4071 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4072 dma_addr_t base_addr) 4073 { 4074 struct hns_roce_cmq_desc desc; 4075 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4076 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4077 u64 addr = to_hr_hw_page_addr(base_addr); 4078 4079 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4080 4081 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4082 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4083 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4084 4085 return hns_roce_cmq_send(hr_dev, &desc, 1); 4086 } 4087 4088 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4089 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4090 { 4091 int ret; 4092 u8 cmd; 4093 4094 if (unlikely(hem_type == HEM_TYPE_GMV)) 4095 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4096 4097 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4098 return 0; 4099 4100 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4101 if (ret < 0) 4102 return ret; 4103 4104 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4105 } 4106 4107 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4108 struct hns_roce_hem_table *table, int obj, 4109 u32 step_idx) 4110 { 4111 struct hns_roce_hem_iter iter; 4112 struct hns_roce_hem_mhop mhop; 4113 struct hns_roce_hem *hem; 4114 unsigned long mhop_obj = obj; 4115 int i, j, k; 4116 int ret = 0; 4117 u64 hem_idx = 0; 4118 u64 l1_idx = 0; 4119 u64 bt_ba = 0; 4120 u32 chunk_ba_num; 4121 u32 hop_num; 4122 4123 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4124 return 0; 4125 4126 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4127 i = mhop.l0_idx; 4128 j = mhop.l1_idx; 4129 k = mhop.l2_idx; 4130 hop_num = mhop.hop_num; 4131 chunk_ba_num = mhop.bt_chunk_size / 8; 4132 4133 if (hop_num == 2) { 4134 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4135 k; 4136 l1_idx = i * chunk_ba_num + j; 4137 } else if (hop_num == 1) { 4138 hem_idx = i * chunk_ba_num + j; 4139 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4140 hem_idx = i; 4141 } 4142 4143 if (table->type == HEM_TYPE_SCCC) 4144 obj = mhop.l0_idx; 4145 4146 if (check_whether_last_step(hop_num, step_idx)) { 4147 hem = table->hem[hem_idx]; 4148 for (hns_roce_hem_first(hem, &iter); 4149 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 4150 bt_ba = hns_roce_hem_addr(&iter); 4151 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 4152 step_idx); 4153 } 4154 } else { 4155 if (step_idx == 0) 4156 bt_ba = table->bt_l0_dma_addr[i]; 4157 else if (step_idx == 1 && hop_num == 2) 4158 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4159 4160 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4161 } 4162 4163 return ret; 4164 } 4165 4166 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4167 struct hns_roce_hem_table *table, 4168 int tag, u32 step_idx) 4169 { 4170 struct hns_roce_cmd_mailbox *mailbox; 4171 struct device *dev = hr_dev->dev; 4172 u8 cmd = 0xff; 4173 int ret; 4174 4175 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4176 return 0; 4177 4178 switch (table->type) { 4179 case HEM_TYPE_QPC: 4180 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4181 break; 4182 case HEM_TYPE_MTPT: 4183 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4184 break; 4185 case HEM_TYPE_CQC: 4186 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4187 break; 4188 case HEM_TYPE_SRQC: 4189 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4190 break; 4191 case HEM_TYPE_SCCC: 4192 case HEM_TYPE_QPC_TIMER: 4193 case HEM_TYPE_CQC_TIMER: 4194 case HEM_TYPE_GMV: 4195 return 0; 4196 default: 4197 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4198 table->type); 4199 return 0; 4200 } 4201 4202 cmd += step_idx; 4203 4204 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4205 if (IS_ERR(mailbox)) 4206 return PTR_ERR(mailbox); 4207 4208 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4209 4210 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4211 return ret; 4212 } 4213 4214 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4215 struct hns_roce_v2_qp_context *context, 4216 struct hns_roce_v2_qp_context *qpc_mask, 4217 struct hns_roce_qp *hr_qp) 4218 { 4219 struct hns_roce_cmd_mailbox *mailbox; 4220 int qpc_size; 4221 int ret; 4222 4223 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4224 if (IS_ERR(mailbox)) 4225 return PTR_ERR(mailbox); 4226 4227 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4228 qpc_size = hr_dev->caps.qpc_sz; 4229 memcpy(mailbox->buf, context, qpc_size); 4230 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4231 4232 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4233 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4234 4235 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4236 4237 return ret; 4238 } 4239 4240 static void set_access_flags(struct hns_roce_qp *hr_qp, 4241 struct hns_roce_v2_qp_context *context, 4242 struct hns_roce_v2_qp_context *qpc_mask, 4243 const struct ib_qp_attr *attr, int attr_mask) 4244 { 4245 u8 dest_rd_atomic; 4246 u32 access_flags; 4247 4248 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4249 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4250 4251 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4252 attr->qp_access_flags : hr_qp->atomic_rd_en; 4253 4254 if (!dest_rd_atomic) 4255 access_flags &= IB_ACCESS_REMOTE_WRITE; 4256 4257 hr_reg_write_bool(context, QPC_RRE, 4258 access_flags & IB_ACCESS_REMOTE_READ); 4259 hr_reg_clear(qpc_mask, QPC_RRE); 4260 4261 hr_reg_write_bool(context, QPC_RWE, 4262 access_flags & IB_ACCESS_REMOTE_WRITE); 4263 hr_reg_clear(qpc_mask, QPC_RWE); 4264 4265 hr_reg_write_bool(context, QPC_ATE, 4266 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4267 hr_reg_clear(qpc_mask, QPC_ATE); 4268 hr_reg_write_bool(context, QPC_EXT_ATE, 4269 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4270 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4271 } 4272 4273 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4274 struct hns_roce_v2_qp_context *context, 4275 struct hns_roce_v2_qp_context *qpc_mask) 4276 { 4277 hr_reg_write(context, QPC_SGE_SHIFT, 4278 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4279 hr_qp->sge.sge_shift)); 4280 4281 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4282 4283 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4284 } 4285 4286 static inline int get_cqn(struct ib_cq *ib_cq) 4287 { 4288 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4289 } 4290 4291 static inline int get_pdn(struct ib_pd *ib_pd) 4292 { 4293 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4294 } 4295 4296 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4297 const struct ib_qp_attr *attr, 4298 struct hns_roce_v2_qp_context *context, 4299 struct hns_roce_v2_qp_context *qpc_mask) 4300 { 4301 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4302 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4303 4304 /* 4305 * In v2 engine, software pass context and context mask to hardware 4306 * when modifying qp. If software need modify some fields in context, 4307 * we should set all bits of the relevant fields in context mask to 4308 * 0 at the same time, else set them to 0x1. 4309 */ 4310 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4311 4312 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4313 4314 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4315 4316 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4317 4318 /* No VLAN need to set 0xFFF */ 4319 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4320 4321 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4322 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4323 4324 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4325 } 4326 4327 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4328 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4329 4330 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4331 hr_reg_enable(context, QPC_OWNER_MODE); 4332 4333 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4334 lower_32_bits(hr_qp->rdb.dma) >> 1); 4335 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4336 upper_32_bits(hr_qp->rdb.dma)); 4337 4338 if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI) 4339 hr_reg_write_bool(context, QPC_RQIE, 4340 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE); 4341 4342 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4343 4344 if (ibqp->srq) { 4345 hr_reg_enable(context, QPC_SRQ_EN); 4346 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4347 } 4348 4349 hr_reg_enable(context, QPC_FRE); 4350 4351 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4352 4353 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4354 return; 4355 4356 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4357 hr_reg_enable(&context->ext, QPCEX_STASH); 4358 } 4359 4360 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4361 const struct ib_qp_attr *attr, 4362 struct hns_roce_v2_qp_context *context, 4363 struct hns_roce_v2_qp_context *qpc_mask) 4364 { 4365 /* 4366 * In v2 engine, software pass context and context mask to hardware 4367 * when modifying qp. If software need modify some fields in context, 4368 * we should set all bits of the relevant fields in context mask to 4369 * 0 at the same time, else set them to 0x1. 4370 */ 4371 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4372 hr_reg_clear(qpc_mask, QPC_TST); 4373 4374 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4375 hr_reg_clear(qpc_mask, QPC_PD); 4376 4377 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4378 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4379 4380 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4381 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4382 4383 if (ibqp->srq) { 4384 hr_reg_enable(context, QPC_SRQ_EN); 4385 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4386 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4387 hr_reg_clear(qpc_mask, QPC_SRQN); 4388 } 4389 } 4390 4391 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4392 struct hns_roce_qp *hr_qp, 4393 struct hns_roce_v2_qp_context *context, 4394 struct hns_roce_v2_qp_context *qpc_mask) 4395 { 4396 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4397 u64 wqe_sge_ba; 4398 int count; 4399 4400 /* Search qp buf's mtts */ 4401 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4402 MTT_MIN_COUNT, &wqe_sge_ba); 4403 if (hr_qp->rq.wqe_cnt && count < 1) { 4404 ibdev_err(&hr_dev->ib_dev, 4405 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4406 return -EINVAL; 4407 } 4408 4409 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4410 qpc_mask->wqe_sge_ba = 0; 4411 4412 /* 4413 * In v2 engine, software pass context and context mask to hardware 4414 * when modifying qp. If software need modify some fields in context, 4415 * we should set all bits of the relevant fields in context mask to 4416 * 0 at the same time, else set them to 0x1. 4417 */ 4418 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4419 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4420 4421 hr_reg_write(context, QPC_SQ_HOP_NUM, 4422 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4423 hr_qp->sq.wqe_cnt)); 4424 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4425 4426 hr_reg_write(context, QPC_SGE_HOP_NUM, 4427 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4428 hr_qp->sge.sge_cnt)); 4429 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4430 4431 hr_reg_write(context, QPC_RQ_HOP_NUM, 4432 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4433 hr_qp->rq.wqe_cnt)); 4434 4435 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4436 4437 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4438 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4439 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4440 4441 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4442 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4443 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4444 4445 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4446 qpc_mask->rq_cur_blk_addr = 0; 4447 4448 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4449 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4450 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4451 4452 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4453 qpc_mask->rq_nxt_blk_addr = 0; 4454 4455 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4456 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4457 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4458 4459 return 0; 4460 } 4461 4462 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4463 struct hns_roce_qp *hr_qp, 4464 struct hns_roce_v2_qp_context *context, 4465 struct hns_roce_v2_qp_context *qpc_mask) 4466 { 4467 struct ib_device *ibdev = &hr_dev->ib_dev; 4468 u64 sge_cur_blk = 0; 4469 u64 sq_cur_blk = 0; 4470 int count; 4471 4472 /* search qp buf's mtts */ 4473 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4474 if (count < 1) { 4475 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4476 hr_qp->qpn); 4477 return -EINVAL; 4478 } 4479 if (hr_qp->sge.sge_cnt > 0) { 4480 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4481 hr_qp->sge.offset, 4482 &sge_cur_blk, 1, NULL); 4483 if (count < 1) { 4484 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4485 hr_qp->qpn); 4486 return -EINVAL; 4487 } 4488 } 4489 4490 /* 4491 * In v2 engine, software pass context and context mask to hardware 4492 * when modifying qp. If software need modify some fields in context, 4493 * we should set all bits of the relevant fields in context mask to 4494 * 0 at the same time, else set them to 0x1. 4495 */ 4496 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4497 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4498 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4499 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4500 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4501 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4502 4503 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4504 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4505 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4506 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4507 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4508 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4509 4510 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4511 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4512 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4513 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4514 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4515 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4516 4517 return 0; 4518 } 4519 4520 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4521 const struct ib_qp_attr *attr) 4522 { 4523 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4524 return IB_MTU_4096; 4525 4526 return attr->path_mtu; 4527 } 4528 4529 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4530 const struct ib_qp_attr *attr, int attr_mask, 4531 struct hns_roce_v2_qp_context *context, 4532 struct hns_roce_v2_qp_context *qpc_mask) 4533 { 4534 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4535 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4536 struct ib_device *ibdev = &hr_dev->ib_dev; 4537 dma_addr_t trrl_ba; 4538 dma_addr_t irrl_ba; 4539 enum ib_mtu ib_mtu; 4540 const u8 *smac; 4541 u8 lp_pktn_ini; 4542 u64 *mtts; 4543 u8 *dmac; 4544 u32 port; 4545 int mtu; 4546 int ret; 4547 4548 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4549 if (ret) { 4550 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4551 return ret; 4552 } 4553 4554 /* Search IRRL's mtts */ 4555 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4556 hr_qp->qpn, &irrl_ba); 4557 if (!mtts) { 4558 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4559 return -EINVAL; 4560 } 4561 4562 /* Search TRRL's mtts */ 4563 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4564 hr_qp->qpn, &trrl_ba); 4565 if (!mtts) { 4566 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4567 return -EINVAL; 4568 } 4569 4570 if (attr_mask & IB_QP_ALT_PATH) { 4571 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4572 attr_mask); 4573 return -EINVAL; 4574 } 4575 4576 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4577 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4578 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4579 qpc_mask->trrl_ba = 0; 4580 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4581 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4582 4583 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4584 qpc_mask->irrl_ba = 0; 4585 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4586 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4587 4588 hr_reg_enable(context, QPC_RMT_E2E); 4589 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4590 4591 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4592 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4593 4594 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4595 4596 smac = (const u8 *)hr_dev->dev_addr[port]; 4597 dmac = (u8 *)attr->ah_attr.roce.dmac; 4598 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4599 if (ether_addr_equal_unaligned(dmac, smac) || 4600 hr_dev->loop_idc == 0x1) { 4601 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4602 hr_reg_clear(qpc_mask, QPC_LBI); 4603 } 4604 4605 if (attr_mask & IB_QP_DEST_QPN) { 4606 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4607 hr_reg_clear(qpc_mask, QPC_DQPN); 4608 } 4609 4610 memcpy(&context->dmac, dmac, sizeof(u32)); 4611 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4612 qpc_mask->dmac = 0; 4613 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4614 4615 ib_mtu = get_mtu(ibqp, attr); 4616 hr_qp->path_mtu = ib_mtu; 4617 4618 mtu = ib_mtu_enum_to_int(ib_mtu); 4619 if (WARN_ON(mtu <= 0)) 4620 return -EINVAL; 4621 #define MAX_LP_MSG_LEN 16384 4622 /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 16KB */ 4623 lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu); 4624 if (WARN_ON(lp_pktn_ini >= 0xF)) 4625 return -EINVAL; 4626 4627 if (attr_mask & IB_QP_PATH_MTU) { 4628 hr_reg_write(context, QPC_MTU, ib_mtu); 4629 hr_reg_clear(qpc_mask, QPC_MTU); 4630 } 4631 4632 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4633 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4634 4635 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4636 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4637 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4638 4639 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4640 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4641 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4642 4643 context->rq_rnr_timer = 0; 4644 qpc_mask->rq_rnr_timer = 0; 4645 4646 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4647 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4648 4649 /* rocee send 2^lp_sgen_ini segs every time */ 4650 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4651 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4652 4653 return 0; 4654 } 4655 4656 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4657 const struct ib_qp_attr *attr, int attr_mask, 4658 struct hns_roce_v2_qp_context *context, 4659 struct hns_roce_v2_qp_context *qpc_mask) 4660 { 4661 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4662 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4663 struct ib_device *ibdev = &hr_dev->ib_dev; 4664 int ret; 4665 4666 /* Not support alternate path and path migration */ 4667 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4668 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4669 return -EINVAL; 4670 } 4671 4672 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4673 if (ret) { 4674 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4675 return ret; 4676 } 4677 4678 /* 4679 * Set some fields in context to zero, Because the default values 4680 * of all fields in context are zero, we need not set them to 0 again. 4681 * but we should set the relevant fields of context mask to 0. 4682 */ 4683 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4684 4685 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4686 4687 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4688 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4689 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4690 4691 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4692 4693 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4694 4695 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4696 4697 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4698 4699 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4700 4701 return 0; 4702 } 4703 4704 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4705 u32 *dip_idx) 4706 { 4707 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4708 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4709 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4710 u32 *head = &hr_dev->qp_table.idx_table.head; 4711 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4712 struct hns_roce_dip *hr_dip; 4713 unsigned long flags; 4714 int ret = 0; 4715 4716 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4717 4718 spare_idx[*tail] = ibqp->qp_num; 4719 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4720 4721 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4722 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4723 *dip_idx = hr_dip->dip_idx; 4724 goto out; 4725 } 4726 } 4727 4728 /* If no dgid is found, a new dip and a mapping between dgid and 4729 * dip_idx will be created. 4730 */ 4731 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4732 if (!hr_dip) { 4733 ret = -ENOMEM; 4734 goto out; 4735 } 4736 4737 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4738 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4739 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4740 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4741 4742 out: 4743 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4744 return ret; 4745 } 4746 4747 enum { 4748 CONG_DCQCN, 4749 CONG_WINDOW, 4750 }; 4751 4752 enum { 4753 UNSUPPORT_CONG_LEVEL, 4754 SUPPORT_CONG_LEVEL, 4755 }; 4756 4757 enum { 4758 CONG_LDCP, 4759 CONG_HC3, 4760 }; 4761 4762 enum { 4763 DIP_INVALID, 4764 DIP_VALID, 4765 }; 4766 4767 enum { 4768 WND_LIMIT, 4769 WND_UNLIMIT, 4770 }; 4771 4772 static int check_cong_type(struct ib_qp *ibqp, 4773 struct hns_roce_congestion_algorithm *cong_alg) 4774 { 4775 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4776 4777 /* different congestion types match different configurations */ 4778 switch (hr_dev->caps.cong_type) { 4779 case CONG_TYPE_DCQCN: 4780 cong_alg->alg_sel = CONG_DCQCN; 4781 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4782 cong_alg->dip_vld = DIP_INVALID; 4783 cong_alg->wnd_mode_sel = WND_LIMIT; 4784 break; 4785 case CONG_TYPE_LDCP: 4786 cong_alg->alg_sel = CONG_WINDOW; 4787 cong_alg->alg_sub_sel = CONG_LDCP; 4788 cong_alg->dip_vld = DIP_INVALID; 4789 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4790 break; 4791 case CONG_TYPE_HC3: 4792 cong_alg->alg_sel = CONG_WINDOW; 4793 cong_alg->alg_sub_sel = CONG_HC3; 4794 cong_alg->dip_vld = DIP_INVALID; 4795 cong_alg->wnd_mode_sel = WND_LIMIT; 4796 break; 4797 case CONG_TYPE_DIP: 4798 cong_alg->alg_sel = CONG_DCQCN; 4799 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4800 cong_alg->dip_vld = DIP_VALID; 4801 cong_alg->wnd_mode_sel = WND_LIMIT; 4802 break; 4803 default: 4804 ibdev_err(&hr_dev->ib_dev, 4805 "error type(%u) for congestion selection.\n", 4806 hr_dev->caps.cong_type); 4807 return -EINVAL; 4808 } 4809 4810 return 0; 4811 } 4812 4813 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4814 struct hns_roce_v2_qp_context *context, 4815 struct hns_roce_v2_qp_context *qpc_mask) 4816 { 4817 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4818 struct hns_roce_congestion_algorithm cong_field; 4819 struct ib_device *ibdev = ibqp->device; 4820 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4821 u32 dip_idx = 0; 4822 int ret; 4823 4824 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4825 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4826 return 0; 4827 4828 ret = check_cong_type(ibqp, &cong_field); 4829 if (ret) 4830 return ret; 4831 4832 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4833 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4834 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4835 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4836 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4837 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4838 cong_field.alg_sub_sel); 4839 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4840 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4841 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4842 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4843 cong_field.wnd_mode_sel); 4844 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4845 4846 /* if dip is disabled, there is no need to set dip idx */ 4847 if (cong_field.dip_vld == 0) 4848 return 0; 4849 4850 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4851 if (ret) { 4852 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4853 return ret; 4854 } 4855 4856 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4857 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4858 4859 return 0; 4860 } 4861 4862 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4863 const struct ib_qp_attr *attr, 4864 int attr_mask, 4865 struct hns_roce_v2_qp_context *context, 4866 struct hns_roce_v2_qp_context *qpc_mask) 4867 { 4868 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4869 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4870 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4871 struct ib_device *ibdev = &hr_dev->ib_dev; 4872 const struct ib_gid_attr *gid_attr = NULL; 4873 int is_roce_protocol; 4874 u16 vlan_id = 0xffff; 4875 bool is_udp = false; 4876 u8 ib_port; 4877 u8 hr_port; 4878 int ret; 4879 4880 /* 4881 * If free_mr_en of qp is set, it means that this qp comes from 4882 * free mr. This qp will perform the loopback operation. 4883 * In the loopback scenario, only sl needs to be set. 4884 */ 4885 if (hr_qp->free_mr_en) { 4886 hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr)); 4887 hr_reg_clear(qpc_mask, QPC_SL); 4888 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4889 return 0; 4890 } 4891 4892 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4893 hr_port = ib_port - 1; 4894 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4895 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4896 4897 if (is_roce_protocol) { 4898 gid_attr = attr->ah_attr.grh.sgid_attr; 4899 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4900 if (ret) 4901 return ret; 4902 4903 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4904 } 4905 4906 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4907 if (vlan_id < VLAN_N_VID && 4908 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4909 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4910 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4911 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4912 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4913 } 4914 4915 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4916 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4917 4918 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4919 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4920 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4921 return -EINVAL; 4922 } 4923 4924 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4925 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4926 return -EINVAL; 4927 } 4928 4929 hr_reg_write(context, QPC_UDPSPN, 4930 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4931 attr->dest_qp_num) : 4932 0); 4933 4934 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4935 4936 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4937 4938 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4939 4940 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4941 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4942 4943 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4944 if (ret) 4945 return ret; 4946 4947 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4948 hr_reg_clear(qpc_mask, QPC_TC); 4949 4950 hr_reg_write(context, QPC_FL, grh->flow_label); 4951 hr_reg_clear(qpc_mask, QPC_FL); 4952 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4953 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4954 4955 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4956 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 4957 ibdev_err(ibdev, 4958 "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n", 4959 hr_qp->sl, MAX_SERVICE_LEVEL); 4960 return -EINVAL; 4961 } 4962 4963 hr_reg_write(context, QPC_SL, hr_qp->sl); 4964 hr_reg_clear(qpc_mask, QPC_SL); 4965 4966 return 0; 4967 } 4968 4969 static bool check_qp_state(enum ib_qp_state cur_state, 4970 enum ib_qp_state new_state) 4971 { 4972 static const bool sm[][IB_QPS_ERR + 1] = { 4973 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4974 [IB_QPS_INIT] = true }, 4975 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4976 [IB_QPS_INIT] = true, 4977 [IB_QPS_RTR] = true, 4978 [IB_QPS_ERR] = true }, 4979 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4980 [IB_QPS_RTS] = true, 4981 [IB_QPS_ERR] = true }, 4982 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4983 [IB_QPS_RTS] = true, 4984 [IB_QPS_ERR] = true }, 4985 [IB_QPS_SQD] = {}, 4986 [IB_QPS_SQE] = {}, 4987 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 4988 [IB_QPS_ERR] = true } 4989 }; 4990 4991 return sm[cur_state][new_state]; 4992 } 4993 4994 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4995 const struct ib_qp_attr *attr, 4996 int attr_mask, 4997 enum ib_qp_state cur_state, 4998 enum ib_qp_state new_state, 4999 struct hns_roce_v2_qp_context *context, 5000 struct hns_roce_v2_qp_context *qpc_mask) 5001 { 5002 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5003 int ret = 0; 5004 5005 if (!check_qp_state(cur_state, new_state)) { 5006 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 5007 return -EINVAL; 5008 } 5009 5010 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 5011 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 5012 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask); 5013 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 5014 modify_qp_init_to_init(ibqp, attr, context, qpc_mask); 5015 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5016 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5017 qpc_mask); 5018 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5019 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 5020 qpc_mask); 5021 } 5022 5023 return ret; 5024 } 5025 5026 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5027 { 5028 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5029 #define QP_ACK_TIMEOUT_OFFSET 10 5030 #define QP_ACK_TIMEOUT_MAX 31 5031 5032 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5033 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5034 ibdev_warn(&hr_dev->ib_dev, 5035 "local ACK timeout shall be 0 to 20.\n"); 5036 return false; 5037 } 5038 *timeout += QP_ACK_TIMEOUT_OFFSET; 5039 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5040 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5041 ibdev_warn(&hr_dev->ib_dev, 5042 "local ACK timeout shall be 0 to 31.\n"); 5043 return false; 5044 } 5045 } 5046 5047 return true; 5048 } 5049 5050 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5051 const struct ib_qp_attr *attr, 5052 int attr_mask, 5053 struct hns_roce_v2_qp_context *context, 5054 struct hns_roce_v2_qp_context *qpc_mask) 5055 { 5056 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5057 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5058 int ret = 0; 5059 u8 timeout; 5060 5061 if (attr_mask & IB_QP_AV) { 5062 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5063 qpc_mask); 5064 if (ret) 5065 return ret; 5066 } 5067 5068 if (attr_mask & IB_QP_TIMEOUT) { 5069 timeout = attr->timeout; 5070 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5071 hr_reg_write(context, QPC_AT, timeout); 5072 hr_reg_clear(qpc_mask, QPC_AT); 5073 } 5074 } 5075 5076 if (attr_mask & IB_QP_RETRY_CNT) { 5077 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5078 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5079 5080 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5081 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5082 } 5083 5084 if (attr_mask & IB_QP_RNR_RETRY) { 5085 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5086 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5087 5088 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5089 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5090 } 5091 5092 if (attr_mask & IB_QP_SQ_PSN) { 5093 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5094 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5095 5096 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5097 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5098 5099 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5100 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5101 5102 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5103 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5104 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5105 5106 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5107 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5108 5109 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5110 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5111 } 5112 5113 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5114 attr->max_dest_rd_atomic) { 5115 hr_reg_write(context, QPC_RR_MAX, 5116 fls(attr->max_dest_rd_atomic - 1)); 5117 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5118 } 5119 5120 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5121 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5122 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5123 } 5124 5125 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5126 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5127 5128 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5129 hr_reg_write(context, QPC_MIN_RNR_TIME, 5130 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5131 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5132 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5133 } 5134 5135 if (attr_mask & IB_QP_RQ_PSN) { 5136 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5137 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5138 5139 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5140 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5141 } 5142 5143 if (attr_mask & IB_QP_QKEY) { 5144 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5145 qpc_mask->qkey_xrcd = 0; 5146 hr_qp->qkey = attr->qkey; 5147 } 5148 5149 return ret; 5150 } 5151 5152 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5153 const struct ib_qp_attr *attr, 5154 int attr_mask) 5155 { 5156 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5157 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5158 5159 if (attr_mask & IB_QP_ACCESS_FLAGS) 5160 hr_qp->atomic_rd_en = attr->qp_access_flags; 5161 5162 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5163 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5164 if (attr_mask & IB_QP_PORT) { 5165 hr_qp->port = attr->port_num - 1; 5166 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5167 } 5168 } 5169 5170 static void clear_qp(struct hns_roce_qp *hr_qp) 5171 { 5172 struct ib_qp *ibqp = &hr_qp->ibqp; 5173 5174 if (ibqp->send_cq) 5175 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5176 hr_qp->qpn, NULL); 5177 5178 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5179 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5180 hr_qp->qpn, ibqp->srq ? 5181 to_hr_srq(ibqp->srq) : NULL); 5182 5183 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5184 *hr_qp->rdb.db_record = 0; 5185 5186 hr_qp->rq.head = 0; 5187 hr_qp->rq.tail = 0; 5188 hr_qp->sq.head = 0; 5189 hr_qp->sq.tail = 0; 5190 hr_qp->next_sge = 0; 5191 } 5192 5193 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5194 struct hns_roce_v2_qp_context *context, 5195 struct hns_roce_v2_qp_context *qpc_mask) 5196 { 5197 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5198 unsigned long sq_flag = 0; 5199 unsigned long rq_flag = 0; 5200 5201 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5202 return; 5203 5204 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5205 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5206 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5207 hr_qp->state = IB_QPS_ERR; 5208 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5209 5210 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5211 return; 5212 5213 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5214 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5215 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5216 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5217 } 5218 5219 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5220 const struct ib_qp_attr *attr, 5221 int attr_mask, enum ib_qp_state cur_state, 5222 enum ib_qp_state new_state) 5223 { 5224 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5225 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5226 struct hns_roce_v2_qp_context ctx[2]; 5227 struct hns_roce_v2_qp_context *context = ctx; 5228 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5229 struct ib_device *ibdev = &hr_dev->ib_dev; 5230 int ret; 5231 5232 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5233 return -EOPNOTSUPP; 5234 5235 /* 5236 * In v2 engine, software pass context and context mask to hardware 5237 * when modifying qp. If software need modify some fields in context, 5238 * we should set all bits of the relevant fields in context mask to 5239 * 0 at the same time, else set them to 0x1. 5240 */ 5241 memset(context, 0, hr_dev->caps.qpc_sz); 5242 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5243 5244 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5245 new_state, context, qpc_mask); 5246 if (ret) 5247 goto out; 5248 5249 /* When QP state is err, SQ and RQ WQE should be flushed */ 5250 if (new_state == IB_QPS_ERR) 5251 v2_set_flushed_fields(ibqp, context, qpc_mask); 5252 5253 /* Configure the optional fields */ 5254 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5255 qpc_mask); 5256 if (ret) 5257 goto out; 5258 5259 hr_reg_write_bool(context, QPC_INV_CREDIT, 5260 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5261 ibqp->srq); 5262 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5263 5264 /* Every status migrate must change state */ 5265 hr_reg_write(context, QPC_QP_ST, new_state); 5266 hr_reg_clear(qpc_mask, QPC_QP_ST); 5267 5268 /* SW pass context to HW */ 5269 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5270 if (ret) { 5271 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5272 goto out; 5273 } 5274 5275 hr_qp->state = new_state; 5276 5277 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5278 5279 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5280 clear_qp(hr_qp); 5281 5282 out: 5283 return ret; 5284 } 5285 5286 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5287 { 5288 static const enum ib_qp_state map[] = { 5289 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5290 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5291 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5292 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5293 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5294 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5295 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5296 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5297 }; 5298 5299 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5300 } 5301 5302 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5303 void *buffer) 5304 { 5305 struct hns_roce_cmd_mailbox *mailbox; 5306 int ret; 5307 5308 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5309 if (IS_ERR(mailbox)) 5310 return PTR_ERR(mailbox); 5311 5312 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5313 qpn); 5314 if (ret) 5315 goto out; 5316 5317 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5318 5319 out: 5320 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5321 return ret; 5322 } 5323 5324 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5325 int qp_attr_mask, 5326 struct ib_qp_init_attr *qp_init_attr) 5327 { 5328 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5329 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5330 struct hns_roce_v2_qp_context context = {}; 5331 struct ib_device *ibdev = &hr_dev->ib_dev; 5332 int tmp_qp_state; 5333 int state; 5334 int ret; 5335 5336 memset(qp_attr, 0, sizeof(*qp_attr)); 5337 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5338 5339 mutex_lock(&hr_qp->mutex); 5340 5341 if (hr_qp->state == IB_QPS_RESET) { 5342 qp_attr->qp_state = IB_QPS_RESET; 5343 ret = 0; 5344 goto done; 5345 } 5346 5347 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5348 if (ret) { 5349 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5350 ret = -EINVAL; 5351 goto out; 5352 } 5353 5354 state = hr_reg_read(&context, QPC_QP_ST); 5355 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5356 if (tmp_qp_state == -1) { 5357 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5358 ret = -EINVAL; 5359 goto out; 5360 } 5361 hr_qp->state = (u8)tmp_qp_state; 5362 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5363 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5364 qp_attr->path_mig_state = IB_MIG_ARMED; 5365 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5366 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5367 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5368 5369 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5370 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5371 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5372 qp_attr->qp_access_flags = 5373 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5374 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5375 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5376 5377 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5378 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5379 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5380 struct ib_global_route *grh = 5381 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5382 5383 rdma_ah_set_sl(&qp_attr->ah_attr, 5384 hr_reg_read(&context, QPC_SL)); 5385 grh->flow_label = hr_reg_read(&context, QPC_FL); 5386 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5387 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5388 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5389 5390 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5391 } 5392 5393 qp_attr->port_num = hr_qp->port + 1; 5394 qp_attr->sq_draining = 0; 5395 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5396 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5397 5398 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5399 qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT); 5400 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5401 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5402 5403 done: 5404 qp_attr->cur_qp_state = qp_attr->qp_state; 5405 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5406 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5407 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5408 5409 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5410 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5411 5412 qp_init_attr->qp_context = ibqp->qp_context; 5413 qp_init_attr->qp_type = ibqp->qp_type; 5414 qp_init_attr->recv_cq = ibqp->recv_cq; 5415 qp_init_attr->send_cq = ibqp->send_cq; 5416 qp_init_attr->srq = ibqp->srq; 5417 qp_init_attr->cap = qp_attr->cap; 5418 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5419 5420 out: 5421 mutex_unlock(&hr_qp->mutex); 5422 return ret; 5423 } 5424 5425 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5426 { 5427 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5428 hr_qp->ibqp.qp_type == IB_QPT_UD || 5429 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5430 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5431 hr_qp->state != IB_QPS_RESET); 5432 } 5433 5434 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5435 struct hns_roce_qp *hr_qp, 5436 struct ib_udata *udata) 5437 { 5438 struct ib_device *ibdev = &hr_dev->ib_dev; 5439 struct hns_roce_cq *send_cq, *recv_cq; 5440 unsigned long flags; 5441 int ret = 0; 5442 5443 if (modify_qp_is_ok(hr_qp)) { 5444 /* Modify qp to reset before destroying qp */ 5445 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5446 hr_qp->state, IB_QPS_RESET); 5447 if (ret) 5448 ibdev_err(ibdev, 5449 "failed to modify QP to RST, ret = %d.\n", 5450 ret); 5451 } 5452 5453 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5454 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5455 5456 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5457 hns_roce_lock_cqs(send_cq, recv_cq); 5458 5459 if (!udata) { 5460 if (recv_cq) 5461 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5462 (hr_qp->ibqp.srq ? 5463 to_hr_srq(hr_qp->ibqp.srq) : 5464 NULL)); 5465 5466 if (send_cq && send_cq != recv_cq) 5467 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5468 } 5469 5470 hns_roce_qp_remove(hr_dev, hr_qp); 5471 5472 hns_roce_unlock_cqs(send_cq, recv_cq); 5473 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5474 5475 return ret; 5476 } 5477 5478 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5479 { 5480 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5481 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5482 int ret; 5483 5484 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5485 if (ret) 5486 ibdev_err(&hr_dev->ib_dev, 5487 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5488 hr_qp->qpn, ret); 5489 5490 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5491 5492 return 0; 5493 } 5494 5495 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5496 struct hns_roce_qp *hr_qp) 5497 { 5498 struct ib_device *ibdev = &hr_dev->ib_dev; 5499 struct hns_roce_sccc_clr_done *resp; 5500 struct hns_roce_sccc_clr *clr; 5501 struct hns_roce_cmq_desc desc; 5502 int ret, i; 5503 5504 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5505 return 0; 5506 5507 mutex_lock(&hr_dev->qp_table.scc_mutex); 5508 5509 /* set scc ctx clear done flag */ 5510 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5511 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5512 if (ret) { 5513 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5514 goto out; 5515 } 5516 5517 /* clear scc context */ 5518 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5519 clr = (struct hns_roce_sccc_clr *)desc.data; 5520 clr->qpn = cpu_to_le32(hr_qp->qpn); 5521 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5522 if (ret) { 5523 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5524 goto out; 5525 } 5526 5527 /* query scc context clear is done or not */ 5528 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5529 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5530 hns_roce_cmq_setup_basic_desc(&desc, 5531 HNS_ROCE_OPC_QUERY_SCCC, true); 5532 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5533 if (ret) { 5534 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5535 ret); 5536 goto out; 5537 } 5538 5539 if (resp->clr_done) 5540 goto out; 5541 5542 msleep(20); 5543 } 5544 5545 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5546 ret = -ETIMEDOUT; 5547 5548 out: 5549 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5550 return ret; 5551 } 5552 5553 #define DMA_IDX_SHIFT 3 5554 #define DMA_WQE_SHIFT 3 5555 5556 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5557 struct hns_roce_srq_context *ctx) 5558 { 5559 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5560 struct ib_device *ibdev = srq->ibsrq.device; 5561 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5562 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5563 dma_addr_t dma_handle_idx = 0; 5564 int ret; 5565 5566 /* Get physical address of idx que buf */ 5567 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5568 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5569 if (ret < 1) { 5570 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5571 ret); 5572 return -ENOBUFS; 5573 } 5574 5575 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5576 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5577 5578 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5579 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5580 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5581 5582 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5583 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5584 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5585 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5586 5587 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5588 to_hr_hw_page_addr(mtts_idx[0])); 5589 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5590 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5591 5592 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5593 to_hr_hw_page_addr(mtts_idx[1])); 5594 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5595 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5596 5597 return 0; 5598 } 5599 5600 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5601 { 5602 struct ib_device *ibdev = srq->ibsrq.device; 5603 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5604 struct hns_roce_srq_context *ctx = mb_buf; 5605 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5606 dma_addr_t dma_handle_wqe = 0; 5607 int ret; 5608 5609 memset(ctx, 0, sizeof(*ctx)); 5610 5611 /* Get the physical address of srq buf */ 5612 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5613 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5614 if (ret < 1) { 5615 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5616 ret); 5617 return -ENOBUFS; 5618 } 5619 5620 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5621 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5622 srq->ibsrq.srq_type == IB_SRQT_XRC); 5623 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5624 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5625 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5626 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5627 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5628 hr_reg_write(ctx, SRQC_RQWS, 5629 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5630 5631 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5632 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5633 srq->wqe_cnt)); 5634 5635 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5636 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5637 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5638 5639 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5640 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5641 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5642 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5643 5644 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5645 } 5646 5647 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5648 struct ib_srq_attr *srq_attr, 5649 enum ib_srq_attr_mask srq_attr_mask, 5650 struct ib_udata *udata) 5651 { 5652 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5653 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5654 struct hns_roce_srq_context *srq_context; 5655 struct hns_roce_srq_context *srqc_mask; 5656 struct hns_roce_cmd_mailbox *mailbox; 5657 int ret; 5658 5659 /* Resizing SRQs is not supported yet */ 5660 if (srq_attr_mask & IB_SRQ_MAX_WR) 5661 return -EINVAL; 5662 5663 if (srq_attr_mask & IB_SRQ_LIMIT) { 5664 if (srq_attr->srq_limit > srq->wqe_cnt) 5665 return -EINVAL; 5666 5667 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5668 if (IS_ERR(mailbox)) 5669 return PTR_ERR(mailbox); 5670 5671 srq_context = mailbox->buf; 5672 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5673 5674 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5675 5676 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5677 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5678 5679 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5680 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5681 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5682 if (ret) { 5683 ibdev_err(&hr_dev->ib_dev, 5684 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5685 ret); 5686 return ret; 5687 } 5688 } 5689 5690 return 0; 5691 } 5692 5693 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5694 { 5695 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5696 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5697 struct hns_roce_srq_context *srq_context; 5698 struct hns_roce_cmd_mailbox *mailbox; 5699 int ret; 5700 5701 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5702 if (IS_ERR(mailbox)) 5703 return PTR_ERR(mailbox); 5704 5705 srq_context = mailbox->buf; 5706 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5707 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5708 if (ret) { 5709 ibdev_err(&hr_dev->ib_dev, 5710 "failed to process cmd of querying SRQ, ret = %d.\n", 5711 ret); 5712 goto out; 5713 } 5714 5715 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5716 attr->max_wr = srq->wqe_cnt; 5717 attr->max_sge = srq->max_gs - srq->rsv_sge; 5718 5719 out: 5720 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5721 return ret; 5722 } 5723 5724 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5725 { 5726 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5727 struct hns_roce_v2_cq_context *cq_context; 5728 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5729 struct hns_roce_v2_cq_context *cqc_mask; 5730 struct hns_roce_cmd_mailbox *mailbox; 5731 int ret; 5732 5733 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5734 if (IS_ERR(mailbox)) 5735 return PTR_ERR(mailbox); 5736 5737 cq_context = mailbox->buf; 5738 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5739 5740 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5741 5742 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5743 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5744 5745 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5746 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5747 dev_info(hr_dev->dev, 5748 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5749 cq_period); 5750 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5751 } 5752 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5753 } 5754 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5755 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5756 5757 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5758 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5759 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5760 if (ret) 5761 ibdev_err(&hr_dev->ib_dev, 5762 "failed to process cmd when modifying CQ, ret = %d.\n", 5763 ret); 5764 5765 return ret; 5766 } 5767 5768 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5769 void *buffer) 5770 { 5771 struct hns_roce_v2_cq_context *context; 5772 struct hns_roce_cmd_mailbox *mailbox; 5773 int ret; 5774 5775 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5776 if (IS_ERR(mailbox)) 5777 return PTR_ERR(mailbox); 5778 5779 context = mailbox->buf; 5780 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5781 HNS_ROCE_CMD_QUERY_CQC, cqn); 5782 if (ret) { 5783 ibdev_err(&hr_dev->ib_dev, 5784 "failed to process cmd when querying CQ, ret = %d.\n", 5785 ret); 5786 goto err_mailbox; 5787 } 5788 5789 memcpy(buffer, context, sizeof(*context)); 5790 5791 err_mailbox: 5792 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5793 5794 return ret; 5795 } 5796 5797 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5798 void *buffer) 5799 { 5800 struct hns_roce_v2_mpt_entry *context; 5801 struct hns_roce_cmd_mailbox *mailbox; 5802 int ret; 5803 5804 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5805 if (IS_ERR(mailbox)) 5806 return PTR_ERR(mailbox); 5807 5808 context = mailbox->buf; 5809 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5810 key_to_hw_index(key)); 5811 if (ret) { 5812 ibdev_err(&hr_dev->ib_dev, 5813 "failed to process cmd when querying MPT, ret = %d.\n", 5814 ret); 5815 goto err_mailbox; 5816 } 5817 5818 memcpy(buffer, context, sizeof(*context)); 5819 5820 err_mailbox: 5821 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5822 5823 return ret; 5824 } 5825 5826 static void hns_roce_irq_work_handle(struct work_struct *work) 5827 { 5828 struct hns_roce_work *irq_work = 5829 container_of(work, struct hns_roce_work, work); 5830 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5831 5832 switch (irq_work->event_type) { 5833 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5834 ibdev_info(ibdev, "path migrated succeeded.\n"); 5835 break; 5836 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5837 ibdev_warn(ibdev, "path migration failed.\n"); 5838 break; 5839 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5840 break; 5841 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5842 ibdev_warn(ibdev, "send queue drained.\n"); 5843 break; 5844 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5845 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 5846 irq_work->queue_num, irq_work->sub_type); 5847 break; 5848 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5849 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 5850 irq_work->queue_num); 5851 break; 5852 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5853 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 5854 irq_work->queue_num, irq_work->sub_type); 5855 break; 5856 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5857 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5858 break; 5859 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5860 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5861 break; 5862 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5863 ibdev_err(ibdev, "SRQ catas error.\n"); 5864 break; 5865 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5866 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5867 break; 5868 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5869 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5870 break; 5871 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5872 ibdev_warn(ibdev, "DB overflow.\n"); 5873 break; 5874 case HNS_ROCE_EVENT_TYPE_FLR: 5875 ibdev_warn(ibdev, "function level reset.\n"); 5876 break; 5877 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5878 ibdev_err(ibdev, "xrc domain violation error.\n"); 5879 break; 5880 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5881 ibdev_err(ibdev, "invalid xrceth error.\n"); 5882 break; 5883 default: 5884 break; 5885 } 5886 5887 kfree(irq_work); 5888 } 5889 5890 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5891 struct hns_roce_eq *eq, u32 queue_num) 5892 { 5893 struct hns_roce_work *irq_work; 5894 5895 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5896 if (!irq_work) 5897 return; 5898 5899 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 5900 irq_work->hr_dev = hr_dev; 5901 irq_work->event_type = eq->event_type; 5902 irq_work->sub_type = eq->sub_type; 5903 irq_work->queue_num = queue_num; 5904 queue_work(hr_dev->irq_workq, &irq_work->work); 5905 } 5906 5907 static void update_eq_db(struct hns_roce_eq *eq) 5908 { 5909 struct hns_roce_dev *hr_dev = eq->hr_dev; 5910 struct hns_roce_v2_db eq_db = {}; 5911 5912 if (eq->type_flag == HNS_ROCE_AEQ) { 5913 hr_reg_write(&eq_db, EQ_DB_CMD, 5914 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5915 HNS_ROCE_EQ_DB_CMD_AEQ : 5916 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5917 } else { 5918 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5919 5920 hr_reg_write(&eq_db, EQ_DB_CMD, 5921 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5922 HNS_ROCE_EQ_DB_CMD_CEQ : 5923 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5924 } 5925 5926 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5927 5928 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5929 } 5930 5931 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5932 { 5933 struct hns_roce_aeqe *aeqe; 5934 5935 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5936 (eq->cons_index & (eq->entries - 1)) * 5937 eq->eqe_size); 5938 5939 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 5940 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5941 } 5942 5943 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5944 struct hns_roce_eq *eq) 5945 { 5946 struct device *dev = hr_dev->dev; 5947 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5948 irqreturn_t aeqe_found = IRQ_NONE; 5949 int event_type; 5950 u32 queue_num; 5951 int sub_type; 5952 5953 while (aeqe) { 5954 /* Make sure we read AEQ entry after we have checked the 5955 * ownership bit 5956 */ 5957 dma_rmb(); 5958 5959 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 5960 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 5961 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 5962 5963 switch (event_type) { 5964 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5965 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5966 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5967 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5968 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5969 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5970 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5971 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5972 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5973 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5974 hns_roce_qp_event(hr_dev, queue_num, event_type); 5975 break; 5976 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5977 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5978 hns_roce_srq_event(hr_dev, queue_num, event_type); 5979 break; 5980 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5981 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5982 hns_roce_cq_event(hr_dev, queue_num, event_type); 5983 break; 5984 case HNS_ROCE_EVENT_TYPE_MB: 5985 hns_roce_cmd_event(hr_dev, 5986 le16_to_cpu(aeqe->event.cmd.token), 5987 aeqe->event.cmd.status, 5988 le64_to_cpu(aeqe->event.cmd.out_param)); 5989 break; 5990 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5991 case HNS_ROCE_EVENT_TYPE_FLR: 5992 break; 5993 default: 5994 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n", 5995 event_type, eq->eqn, eq->cons_index); 5996 break; 5997 } 5998 5999 eq->event_type = event_type; 6000 eq->sub_type = sub_type; 6001 ++eq->cons_index; 6002 aeqe_found = IRQ_HANDLED; 6003 6004 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6005 6006 aeqe = next_aeqe_sw_v2(eq); 6007 } 6008 6009 update_eq_db(eq); 6010 6011 return IRQ_RETVAL(aeqe_found); 6012 } 6013 6014 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6015 { 6016 struct hns_roce_ceqe *ceqe; 6017 6018 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6019 (eq->cons_index & (eq->entries - 1)) * 6020 eq->eqe_size); 6021 6022 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6023 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6024 } 6025 6026 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 6027 struct hns_roce_eq *eq) 6028 { 6029 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6030 irqreturn_t ceqe_found = IRQ_NONE; 6031 u32 cqn; 6032 6033 while (ceqe) { 6034 /* Make sure we read CEQ entry after we have checked the 6035 * ownership bit 6036 */ 6037 dma_rmb(); 6038 6039 cqn = hr_reg_read(ceqe, CEQE_CQN); 6040 6041 hns_roce_cq_completion(hr_dev, cqn); 6042 6043 ++eq->cons_index; 6044 ceqe_found = IRQ_HANDLED; 6045 6046 ceqe = next_ceqe_sw_v2(eq); 6047 } 6048 6049 update_eq_db(eq); 6050 6051 return IRQ_RETVAL(ceqe_found); 6052 } 6053 6054 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6055 { 6056 struct hns_roce_eq *eq = eq_ptr; 6057 struct hns_roce_dev *hr_dev = eq->hr_dev; 6058 irqreturn_t int_work; 6059 6060 if (eq->type_flag == HNS_ROCE_CEQ) 6061 /* Completion event interrupt */ 6062 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 6063 else 6064 /* Asynchronous event interrupt */ 6065 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6066 6067 return IRQ_RETVAL(int_work); 6068 } 6069 6070 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6071 u32 int_st) 6072 { 6073 struct pci_dev *pdev = hr_dev->pci_dev; 6074 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6075 const struct hnae3_ae_ops *ops = ae_dev->ops; 6076 irqreturn_t int_work = IRQ_NONE; 6077 u32 int_en; 6078 6079 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6080 6081 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6082 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6083 6084 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6085 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6086 6087 /* Set reset level for reset_event() */ 6088 if (ops->set_default_reset_request) 6089 ops->set_default_reset_request(ae_dev, 6090 HNAE3_FUNC_RESET); 6091 if (ops->reset_event) 6092 ops->reset_event(pdev, NULL); 6093 6094 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6095 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6096 6097 int_work = IRQ_HANDLED; 6098 } else { 6099 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6100 } 6101 6102 return IRQ_RETVAL(int_work); 6103 } 6104 6105 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6106 struct fmea_ram_ecc *ecc_info) 6107 { 6108 struct hns_roce_cmq_desc desc; 6109 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6110 int ret; 6111 6112 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6113 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6114 if (ret) 6115 return ret; 6116 6117 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6118 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6119 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6120 6121 return 0; 6122 } 6123 6124 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6125 { 6126 struct hns_roce_cmq_desc desc; 6127 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6128 u32 addr_upper; 6129 u32 addr_low; 6130 int ret; 6131 6132 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6133 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6134 6135 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6136 if (ret) { 6137 dev_err(hr_dev->dev, 6138 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6139 return ret; 6140 } 6141 6142 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6143 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6144 6145 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6146 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6147 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6148 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6149 6150 return hns_roce_cmq_send(hr_dev, &desc, 1); 6151 } 6152 6153 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6154 { 6155 if (res_type == ECC_RESOURCE_QPC_TIMER || 6156 res_type == ECC_RESOURCE_CQC_TIMER || 6157 res_type == ECC_RESOURCE_SCCC) 6158 return le64_to_cpu(*data); 6159 6160 return le64_to_cpu(*data) << PAGE_SHIFT; 6161 } 6162 6163 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6164 u32 index) 6165 { 6166 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6167 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6168 struct hns_roce_cmd_mailbox *mailbox; 6169 u64 addr; 6170 int ret; 6171 6172 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6173 if (IS_ERR(mailbox)) 6174 return PTR_ERR(mailbox); 6175 6176 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6177 if (ret) { 6178 dev_err(hr_dev->dev, 6179 "failed to execute cmd to read fmea ram, ret = %d.\n", 6180 ret); 6181 goto out; 6182 } 6183 6184 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6185 6186 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6187 if (ret) 6188 dev_err(hr_dev->dev, 6189 "failed to execute cmd to write fmea ram, ret = %d.\n", 6190 ret); 6191 6192 out: 6193 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6194 return ret; 6195 } 6196 6197 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6198 struct fmea_ram_ecc *ecc_info) 6199 { 6200 u32 res_type = ecc_info->res_type; 6201 u32 index = ecc_info->index; 6202 int ret; 6203 6204 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6205 6206 if (res_type >= ECC_RESOURCE_COUNT) { 6207 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6208 res_type); 6209 return; 6210 } 6211 6212 if (res_type == ECC_RESOURCE_GMV) 6213 ret = fmea_recover_gmv(hr_dev, index); 6214 else 6215 ret = fmea_recover_others(hr_dev, res_type, index); 6216 if (ret) 6217 dev_err(hr_dev->dev, 6218 "failed to recover %s, index = %u, ret = %d.\n", 6219 fmea_ram_res[res_type].name, index, ret); 6220 } 6221 6222 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6223 { 6224 struct hns_roce_dev *hr_dev = 6225 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6226 struct fmea_ram_ecc ecc_info = {}; 6227 6228 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6229 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6230 return; 6231 } 6232 6233 if (!ecc_info.is_ecc_err) { 6234 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6235 return; 6236 } 6237 6238 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6239 } 6240 6241 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6242 { 6243 struct hns_roce_dev *hr_dev = dev_id; 6244 irqreturn_t int_work = IRQ_NONE; 6245 u32 int_st; 6246 6247 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6248 6249 if (int_st) { 6250 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6251 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6252 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6253 int_work = IRQ_HANDLED; 6254 } else { 6255 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6256 } 6257 6258 return IRQ_RETVAL(int_work); 6259 } 6260 6261 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6262 int eq_num, u32 enable_flag) 6263 { 6264 int i; 6265 6266 for (i = 0; i < eq_num; i++) 6267 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6268 i * EQ_REG_OFFSET, enable_flag); 6269 6270 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6271 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6272 } 6273 6274 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) 6275 { 6276 struct device *dev = hr_dev->dev; 6277 int ret; 6278 u8 cmd; 6279 6280 if (eqn < hr_dev->caps.num_comp_vectors) 6281 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6282 else 6283 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6284 6285 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6286 if (ret) 6287 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn); 6288 } 6289 6290 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6291 { 6292 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6293 } 6294 6295 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6296 { 6297 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6298 eq->cons_index = 0; 6299 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6300 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6301 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6302 eq->shift = ilog2((unsigned int)eq->entries); 6303 } 6304 6305 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6306 void *mb_buf) 6307 { 6308 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6309 struct hns_roce_eq_context *eqc; 6310 u64 bt_ba = 0; 6311 int count; 6312 6313 eqc = mb_buf; 6314 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6315 6316 init_eq_config(hr_dev, eq); 6317 6318 /* if not multi-hop, eqe buffer only use one trunk */ 6319 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 6320 &bt_ba); 6321 if (count < 1) { 6322 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 6323 return -ENOBUFS; 6324 } 6325 6326 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6327 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6328 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6329 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6330 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6331 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6332 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6333 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6334 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6335 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6336 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6337 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6338 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6339 6340 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6341 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6342 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6343 eq->eq_period); 6344 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6345 } 6346 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6347 } 6348 6349 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6350 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6351 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6352 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6353 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6354 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6355 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6356 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6357 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6358 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6359 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6360 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6361 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6362 6363 return 0; 6364 } 6365 6366 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6367 { 6368 struct hns_roce_buf_attr buf_attr = {}; 6369 int err; 6370 6371 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6372 eq->hop_num = 0; 6373 else 6374 eq->hop_num = hr_dev->caps.eqe_hop_num; 6375 6376 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6377 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6378 buf_attr.region[0].hopnum = eq->hop_num; 6379 buf_attr.region_count = 1; 6380 6381 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6382 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6383 0); 6384 if (err) 6385 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6386 6387 return err; 6388 } 6389 6390 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6391 struct hns_roce_eq *eq, u8 eq_cmd) 6392 { 6393 struct hns_roce_cmd_mailbox *mailbox; 6394 int ret; 6395 6396 /* Allocate mailbox memory */ 6397 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6398 if (IS_ERR(mailbox)) 6399 return PTR_ERR(mailbox); 6400 6401 ret = alloc_eq_buf(hr_dev, eq); 6402 if (ret) 6403 goto free_cmd_mbox; 6404 6405 ret = config_eqc(hr_dev, eq, mailbox->buf); 6406 if (ret) 6407 goto err_cmd_mbox; 6408 6409 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6410 if (ret) { 6411 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6412 goto err_cmd_mbox; 6413 } 6414 6415 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6416 6417 return 0; 6418 6419 err_cmd_mbox: 6420 free_eq_buf(hr_dev, eq); 6421 6422 free_cmd_mbox: 6423 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6424 6425 return ret; 6426 } 6427 6428 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6429 int comp_num, int aeq_num, int other_num) 6430 { 6431 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6432 int i, j; 6433 int ret; 6434 6435 for (i = 0; i < irq_num; i++) { 6436 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6437 GFP_KERNEL); 6438 if (!hr_dev->irq_names[i]) { 6439 ret = -ENOMEM; 6440 goto err_kzalloc_failed; 6441 } 6442 } 6443 6444 /* irq contains: abnormal + AEQ + CEQ */ 6445 for (j = 0; j < other_num; j++) 6446 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6447 "hns-abn-%d", j); 6448 6449 for (j = other_num; j < (other_num + aeq_num); j++) 6450 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6451 "hns-aeq-%d", j - other_num); 6452 6453 for (j = (other_num + aeq_num); j < irq_num; j++) 6454 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6455 "hns-ceq-%d", j - other_num - aeq_num); 6456 6457 for (j = 0; j < irq_num; j++) { 6458 if (j < other_num) 6459 ret = request_irq(hr_dev->irq[j], 6460 hns_roce_v2_msix_interrupt_abn, 6461 0, hr_dev->irq_names[j], hr_dev); 6462 6463 else if (j < (other_num + comp_num)) 6464 ret = request_irq(eq_table->eq[j - other_num].irq, 6465 hns_roce_v2_msix_interrupt_eq, 6466 0, hr_dev->irq_names[j + aeq_num], 6467 &eq_table->eq[j - other_num]); 6468 else 6469 ret = request_irq(eq_table->eq[j - other_num].irq, 6470 hns_roce_v2_msix_interrupt_eq, 6471 0, hr_dev->irq_names[j - comp_num], 6472 &eq_table->eq[j - other_num]); 6473 if (ret) { 6474 dev_err(hr_dev->dev, "request irq error!\n"); 6475 goto err_request_failed; 6476 } 6477 } 6478 6479 return 0; 6480 6481 err_request_failed: 6482 for (j -= 1; j >= 0; j--) 6483 if (j < other_num) 6484 free_irq(hr_dev->irq[j], hr_dev); 6485 else 6486 free_irq(eq_table->eq[j - other_num].irq, 6487 &eq_table->eq[j - other_num]); 6488 6489 err_kzalloc_failed: 6490 for (i -= 1; i >= 0; i--) 6491 kfree(hr_dev->irq_names[i]); 6492 6493 return ret; 6494 } 6495 6496 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6497 { 6498 int irq_num; 6499 int eq_num; 6500 int i; 6501 6502 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6503 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6504 6505 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6506 free_irq(hr_dev->irq[i], hr_dev); 6507 6508 for (i = 0; i < eq_num; i++) 6509 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6510 6511 for (i = 0; i < irq_num; i++) 6512 kfree(hr_dev->irq_names[i]); 6513 } 6514 6515 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6516 { 6517 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6518 struct device *dev = hr_dev->dev; 6519 struct hns_roce_eq *eq; 6520 int other_num; 6521 int comp_num; 6522 int aeq_num; 6523 int irq_num; 6524 int eq_num; 6525 u8 eq_cmd; 6526 int ret; 6527 int i; 6528 6529 other_num = hr_dev->caps.num_other_vectors; 6530 comp_num = hr_dev->caps.num_comp_vectors; 6531 aeq_num = hr_dev->caps.num_aeq_vectors; 6532 6533 eq_num = comp_num + aeq_num; 6534 irq_num = eq_num + other_num; 6535 6536 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6537 if (!eq_table->eq) 6538 return -ENOMEM; 6539 6540 /* create eq */ 6541 for (i = 0; i < eq_num; i++) { 6542 eq = &eq_table->eq[i]; 6543 eq->hr_dev = hr_dev; 6544 eq->eqn = i; 6545 if (i < comp_num) { 6546 /* CEQ */ 6547 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6548 eq->type_flag = HNS_ROCE_CEQ; 6549 eq->entries = hr_dev->caps.ceqe_depth; 6550 eq->eqe_size = hr_dev->caps.ceqe_size; 6551 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6552 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6553 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6554 } else { 6555 /* AEQ */ 6556 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6557 eq->type_flag = HNS_ROCE_AEQ; 6558 eq->entries = hr_dev->caps.aeqe_depth; 6559 eq->eqe_size = hr_dev->caps.aeqe_size; 6560 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6561 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6562 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6563 } 6564 6565 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6566 if (ret) { 6567 dev_err(dev, "failed to create eq.\n"); 6568 goto err_create_eq_fail; 6569 } 6570 } 6571 6572 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6573 6574 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6575 if (!hr_dev->irq_workq) { 6576 dev_err(dev, "failed to create irq workqueue.\n"); 6577 ret = -ENOMEM; 6578 goto err_create_eq_fail; 6579 } 6580 6581 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6582 other_num); 6583 if (ret) { 6584 dev_err(dev, "failed to request irq.\n"); 6585 goto err_request_irq_fail; 6586 } 6587 6588 /* enable irq */ 6589 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6590 6591 return 0; 6592 6593 err_request_irq_fail: 6594 destroy_workqueue(hr_dev->irq_workq); 6595 6596 err_create_eq_fail: 6597 for (i -= 1; i >= 0; i--) 6598 free_eq_buf(hr_dev, &eq_table->eq[i]); 6599 kfree(eq_table->eq); 6600 6601 return ret; 6602 } 6603 6604 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6605 { 6606 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6607 int eq_num; 6608 int i; 6609 6610 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6611 6612 /* Disable irq */ 6613 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6614 6615 __hns_roce_free_irq(hr_dev); 6616 destroy_workqueue(hr_dev->irq_workq); 6617 6618 for (i = 0; i < eq_num; i++) { 6619 hns_roce_v2_destroy_eqc(hr_dev, i); 6620 6621 free_eq_buf(hr_dev, &eq_table->eq[i]); 6622 } 6623 6624 kfree(eq_table->eq); 6625 } 6626 6627 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6628 .destroy_qp = hns_roce_v2_destroy_qp, 6629 .modify_cq = hns_roce_v2_modify_cq, 6630 .poll_cq = hns_roce_v2_poll_cq, 6631 .post_recv = hns_roce_v2_post_recv, 6632 .post_send = hns_roce_v2_post_send, 6633 .query_qp = hns_roce_v2_query_qp, 6634 .req_notify_cq = hns_roce_v2_req_notify_cq, 6635 }; 6636 6637 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6638 .modify_srq = hns_roce_v2_modify_srq, 6639 .post_srq_recv = hns_roce_v2_post_srq_recv, 6640 .query_srq = hns_roce_v2_query_srq, 6641 }; 6642 6643 static const struct hns_roce_hw hns_roce_hw_v2 = { 6644 .cmq_init = hns_roce_v2_cmq_init, 6645 .cmq_exit = hns_roce_v2_cmq_exit, 6646 .hw_profile = hns_roce_v2_profile, 6647 .hw_init = hns_roce_v2_init, 6648 .hw_exit = hns_roce_v2_exit, 6649 .post_mbox = v2_post_mbox, 6650 .poll_mbox_done = v2_poll_mbox_done, 6651 .chk_mbox_avail = v2_chk_mbox_is_avail, 6652 .set_gid = hns_roce_v2_set_gid, 6653 .set_mac = hns_roce_v2_set_mac, 6654 .write_mtpt = hns_roce_v2_write_mtpt, 6655 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6656 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6657 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6658 .write_cqc = hns_roce_v2_write_cqc, 6659 .set_hem = hns_roce_v2_set_hem, 6660 .clear_hem = hns_roce_v2_clear_hem, 6661 .modify_qp = hns_roce_v2_modify_qp, 6662 .dereg_mr = hns_roce_v2_dereg_mr, 6663 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6664 .init_eq = hns_roce_v2_init_eq_table, 6665 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6666 .write_srqc = hns_roce_v2_write_srqc, 6667 .query_cqc = hns_roce_v2_query_cqc, 6668 .query_qpc = hns_roce_v2_query_qpc, 6669 .query_mpt = hns_roce_v2_query_mpt, 6670 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6671 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6672 }; 6673 6674 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6675 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6676 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6677 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6678 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6679 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6680 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6681 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6682 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6683 /* required last entry */ 6684 {0, } 6685 }; 6686 6687 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6688 6689 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6690 struct hnae3_handle *handle) 6691 { 6692 struct hns_roce_v2_priv *priv = hr_dev->priv; 6693 const struct pci_device_id *id; 6694 int i; 6695 6696 hr_dev->pci_dev = handle->pdev; 6697 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6698 hr_dev->is_vf = id->driver_data; 6699 hr_dev->dev = &handle->pdev->dev; 6700 hr_dev->hw = &hns_roce_hw_v2; 6701 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6702 hr_dev->odb_offset = hr_dev->sdb_offset; 6703 6704 /* Get info from NIC driver. */ 6705 hr_dev->reg_base = handle->rinfo.roce_io_base; 6706 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6707 hr_dev->caps.num_ports = 1; 6708 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6709 hr_dev->iboe.phy_port[0] = 0; 6710 6711 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6712 hr_dev->iboe.netdevs[0]->dev_addr); 6713 6714 for (i = 0; i < handle->rinfo.num_vectors; i++) 6715 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6716 i + handle->rinfo.base_vector); 6717 6718 /* cmd issue mode: 0 is poll, 1 is event */ 6719 hr_dev->cmd_mod = 1; 6720 hr_dev->loop_idc = 0; 6721 6722 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6723 priv->handle = handle; 6724 } 6725 6726 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6727 { 6728 struct hns_roce_dev *hr_dev; 6729 int ret; 6730 6731 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6732 if (!hr_dev) 6733 return -ENOMEM; 6734 6735 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6736 if (!hr_dev->priv) { 6737 ret = -ENOMEM; 6738 goto error_failed_kzalloc; 6739 } 6740 6741 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6742 6743 ret = hns_roce_init(hr_dev); 6744 if (ret) { 6745 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6746 goto error_failed_cfg; 6747 } 6748 6749 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6750 ret = free_mr_init(hr_dev); 6751 if (ret) { 6752 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6753 goto error_failed_roce_init; 6754 } 6755 } 6756 6757 handle->priv = hr_dev; 6758 6759 return 0; 6760 6761 error_failed_roce_init: 6762 hns_roce_exit(hr_dev); 6763 6764 error_failed_cfg: 6765 kfree(hr_dev->priv); 6766 6767 error_failed_kzalloc: 6768 ib_dealloc_device(&hr_dev->ib_dev); 6769 6770 return ret; 6771 } 6772 6773 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6774 bool reset) 6775 { 6776 struct hns_roce_dev *hr_dev = handle->priv; 6777 6778 if (!hr_dev) 6779 return; 6780 6781 handle->priv = NULL; 6782 6783 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6784 hns_roce_handle_device_err(hr_dev); 6785 6786 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 6787 free_mr_exit(hr_dev); 6788 6789 hns_roce_exit(hr_dev); 6790 kfree(hr_dev->priv); 6791 ib_dealloc_device(&hr_dev->ib_dev); 6792 } 6793 6794 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6795 { 6796 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6797 const struct pci_device_id *id; 6798 struct device *dev = &handle->pdev->dev; 6799 int ret; 6800 6801 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6802 6803 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6804 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6805 goto reset_chk_err; 6806 } 6807 6808 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6809 if (!id) 6810 return 0; 6811 6812 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6813 return 0; 6814 6815 ret = __hns_roce_hw_v2_init_instance(handle); 6816 if (ret) { 6817 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6818 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6819 if (ops->ae_dev_resetting(handle) || 6820 ops->get_hw_reset_stat(handle)) 6821 goto reset_chk_err; 6822 else 6823 return ret; 6824 } 6825 6826 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6827 6828 return 0; 6829 6830 reset_chk_err: 6831 dev_err(dev, "Device is busy in resetting state.\n" 6832 "please retry later.\n"); 6833 6834 return -EBUSY; 6835 } 6836 6837 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6838 bool reset) 6839 { 6840 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6841 return; 6842 6843 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6844 6845 __hns_roce_hw_v2_uninit_instance(handle, reset); 6846 6847 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6848 } 6849 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6850 { 6851 struct hns_roce_dev *hr_dev; 6852 6853 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6854 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6855 return 0; 6856 } 6857 6858 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6859 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6860 6861 hr_dev = handle->priv; 6862 if (!hr_dev) 6863 return 0; 6864 6865 hr_dev->active = false; 6866 hr_dev->dis_db = true; 6867 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6868 6869 return 0; 6870 } 6871 6872 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6873 { 6874 struct device *dev = &handle->pdev->dev; 6875 int ret; 6876 6877 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6878 &handle->rinfo.state)) { 6879 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6880 return 0; 6881 } 6882 6883 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6884 6885 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6886 ret = __hns_roce_hw_v2_init_instance(handle); 6887 if (ret) { 6888 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6889 * callback function, RoCE Engine reinitialize. If RoCE reinit 6890 * failed, we should inform NIC driver. 6891 */ 6892 handle->priv = NULL; 6893 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6894 } else { 6895 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6896 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 6897 } 6898 6899 return ret; 6900 } 6901 6902 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6903 { 6904 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6905 return 0; 6906 6907 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6908 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6909 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6910 __hns_roce_hw_v2_uninit_instance(handle, false); 6911 6912 return 0; 6913 } 6914 6915 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6916 enum hnae3_reset_notify_type type) 6917 { 6918 int ret = 0; 6919 6920 switch (type) { 6921 case HNAE3_DOWN_CLIENT: 6922 ret = hns_roce_hw_v2_reset_notify_down(handle); 6923 break; 6924 case HNAE3_INIT_CLIENT: 6925 ret = hns_roce_hw_v2_reset_notify_init(handle); 6926 break; 6927 case HNAE3_UNINIT_CLIENT: 6928 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6929 break; 6930 default: 6931 break; 6932 } 6933 6934 return ret; 6935 } 6936 6937 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6938 .init_instance = hns_roce_hw_v2_init_instance, 6939 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6940 .reset_notify = hns_roce_hw_v2_reset_notify, 6941 }; 6942 6943 static struct hnae3_client hns_roce_hw_v2_client = { 6944 .name = "hns_roce_hw_v2", 6945 .type = HNAE3_CLIENT_ROCE, 6946 .ops = &hns_roce_hw_v2_ops, 6947 }; 6948 6949 static int __init hns_roce_hw_v2_init(void) 6950 { 6951 return hnae3_register_client(&hns_roce_hw_v2_client); 6952 } 6953 6954 static void __exit hns_roce_hw_v2_exit(void) 6955 { 6956 hnae3_unregister_client(&hns_roce_hw_v2_client); 6957 } 6958 6959 module_init(hns_roce_hw_v2_init); 6960 module_exit(hns_roce_hw_v2_exit); 6961 6962 MODULE_LICENSE("Dual BSD/GPL"); 6963 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6964 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6965 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6966 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6967