1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/of_platform.h> 35 #include <linux/module.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_smi.h> 38 #include <rdma/ib_user_verbs.h> 39 #include <rdma/ib_cache.h> 40 #include "hns_roce_common.h" 41 #include "hns_roce_device.h" 42 #include <rdma/hns-abi.h> 43 #include "hns_roce_hem.h" 44 45 /** 46 * hns_get_gid_index - Get gid index. 47 * @hr_dev: pointer to structure hns_roce_dev. 48 * @port: port, value range: 0 ~ MAX 49 * @gid_index: gid_index, value range: 0 ~ MAX 50 * Description: 51 * N ports shared gids, allocation method as follow: 52 * GID[0][0], GID[1][0],.....GID[N - 1][0], 53 * GID[0][0], GID[1][0],.....GID[N - 1][0], 54 * And so on 55 */ 56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index) 57 { 58 return gid_index * hr_dev->caps.num_ports + port; 59 } 60 EXPORT_SYMBOL_GPL(hns_get_gid_index); 61 62 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr) 63 { 64 u8 phy_port; 65 u32 i = 0; 66 67 if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM)) 68 return 0; 69 70 for (i = 0; i < MAC_ADDR_OCTET_NUM; i++) 71 hr_dev->dev_addr[port][i] = addr[i]; 72 73 phy_port = hr_dev->iboe.phy_port[port]; 74 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 75 } 76 77 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 78 { 79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 80 u8 port = attr->port_num - 1; 81 unsigned long flags; 82 int ret; 83 84 if (port >= hr_dev->caps.num_ports) 85 return -EINVAL; 86 87 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 88 89 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr); 90 91 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 92 93 return ret; 94 } 95 96 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 97 { 98 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 99 struct ib_gid_attr zattr = { }; 100 u8 port = attr->port_num - 1; 101 unsigned long flags; 102 int ret; 103 104 if (port >= hr_dev->caps.num_ports) 105 return -EINVAL; 106 107 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 108 109 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr); 110 111 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 112 113 return ret; 114 } 115 116 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port, 117 unsigned long event) 118 { 119 struct device *dev = hr_dev->dev; 120 struct net_device *netdev; 121 int ret = 0; 122 123 netdev = hr_dev->iboe.netdevs[port]; 124 if (!netdev) { 125 dev_err(dev, "port(%d) can't find netdev\n", port); 126 return -ENODEV; 127 } 128 129 switch (event) { 130 case NETDEV_UP: 131 case NETDEV_CHANGE: 132 case NETDEV_REGISTER: 133 case NETDEV_CHANGEADDR: 134 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 135 break; 136 case NETDEV_DOWN: 137 /* 138 * In v1 engine, only support all ports closed together. 139 */ 140 break; 141 default: 142 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 143 break; 144 } 145 146 return ret; 147 } 148 149 static int hns_roce_netdev_event(struct notifier_block *self, 150 unsigned long event, void *ptr) 151 { 152 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 153 struct hns_roce_ib_iboe *iboe = NULL; 154 struct hns_roce_dev *hr_dev = NULL; 155 u8 port = 0; 156 int ret = 0; 157 158 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 159 iboe = &hr_dev->iboe; 160 161 for (port = 0; port < hr_dev->caps.num_ports; port++) { 162 if (dev == iboe->netdevs[port]) { 163 ret = handle_en_event(hr_dev, port, event); 164 if (ret) 165 return NOTIFY_DONE; 166 break; 167 } 168 } 169 170 return NOTIFY_DONE; 171 } 172 173 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 174 { 175 int ret; 176 u8 i; 177 178 for (i = 0; i < hr_dev->caps.num_ports; i++) { 179 if (hr_dev->hw->set_mtu) 180 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i], 181 hr_dev->caps.max_mtu); 182 ret = hns_roce_set_mac(hr_dev, i, 183 hr_dev->iboe.netdevs[i]->dev_addr); 184 if (ret) 185 return ret; 186 } 187 188 return 0; 189 } 190 191 static int hns_roce_query_device(struct ib_device *ib_dev, 192 struct ib_device_attr *props, 193 struct ib_udata *uhw) 194 { 195 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 196 197 memset(props, 0, sizeof(*props)); 198 199 props->fw_ver = hr_dev->caps.fw_ver; 200 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 201 props->max_mr_size = (u64)(~(0ULL)); 202 props->page_size_cap = hr_dev->caps.page_size_cap; 203 props->vendor_id = hr_dev->vendor_id; 204 props->vendor_part_id = hr_dev->vendor_part_id; 205 props->hw_ver = hr_dev->hw_rev; 206 props->max_qp = hr_dev->caps.num_qps; 207 props->max_qp_wr = hr_dev->caps.max_wqes; 208 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 209 IB_DEVICE_RC_RNR_NAK_GEN; 210 props->max_send_sge = hr_dev->caps.max_sq_sg; 211 props->max_recv_sge = hr_dev->caps.max_rq_sg; 212 props->max_sge_rd = 1; 213 props->max_cq = hr_dev->caps.num_cqs; 214 props->max_cqe = hr_dev->caps.max_cqes; 215 props->max_mr = hr_dev->caps.num_mtpts; 216 props->max_pd = hr_dev->caps.num_pds; 217 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 218 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 219 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 220 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 221 props->max_pkeys = 1; 222 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 223 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 224 props->max_srq = hr_dev->caps.max_srqs; 225 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 226 props->max_srq_sge = hr_dev->caps.max_srq_sges; 227 } 228 229 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) { 230 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 231 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; 232 } 233 234 return 0; 235 } 236 237 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num, 238 struct ib_port_attr *props) 239 { 240 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 241 struct device *dev = hr_dev->dev; 242 struct net_device *net_dev; 243 unsigned long flags; 244 enum ib_mtu mtu; 245 u8 port; 246 247 assert(port_num > 0); 248 port = port_num - 1; 249 250 /* props being zeroed by the caller, avoid zeroing it here */ 251 252 props->max_mtu = hr_dev->caps.max_mtu; 253 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 254 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 255 IB_PORT_VENDOR_CLASS_SUP | 256 IB_PORT_BOOT_MGMT_SUP; 257 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 258 props->pkey_tbl_len = 1; 259 props->active_width = IB_WIDTH_4X; 260 props->active_speed = 1; 261 262 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 263 264 net_dev = hr_dev->iboe.netdevs[port]; 265 if (!net_dev) { 266 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 267 dev_err(dev, "find netdev %d failed!\r\n", port); 268 return -EINVAL; 269 } 270 271 mtu = iboe_get_mtu(net_dev->mtu); 272 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 273 props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ? 274 IB_PORT_ACTIVE : IB_PORT_DOWN; 275 props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3; 276 277 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 278 279 return 0; 280 } 281 282 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 283 u8 port_num) 284 { 285 return IB_LINK_LAYER_ETHERNET; 286 } 287 288 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index, 289 u16 *pkey) 290 { 291 *pkey = PKEY_ID; 292 293 return 0; 294 } 295 296 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 297 struct ib_device_modify *props) 298 { 299 unsigned long flags; 300 301 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 302 return -EOPNOTSUPP; 303 304 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 305 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 306 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 307 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 308 } 309 310 return 0; 311 } 312 313 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask, 314 struct ib_port_modify *props) 315 { 316 return 0; 317 } 318 319 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, 320 struct ib_udata *udata) 321 { 322 int ret = 0; 323 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 324 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 325 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 326 327 if (!hr_dev->active) 328 return -EAGAIN; 329 330 resp.qp_tab_size = hr_dev->caps.num_qps; 331 332 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 333 if (ret) 334 goto error_fail_uar_alloc; 335 336 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 337 INIT_LIST_HEAD(&context->page_list); 338 mutex_init(&context->page_mutex); 339 } 340 341 ret = ib_copy_to_udata(udata, &resp, sizeof(resp)); 342 if (ret) 343 goto error_fail_copy_to_udata; 344 345 return 0; 346 347 error_fail_copy_to_udata: 348 hns_roce_uar_free(hr_dev, &context->uar); 349 350 error_fail_uar_alloc: 351 return ret; 352 } 353 354 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 355 { 356 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 357 358 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar); 359 } 360 361 static int hns_roce_mmap(struct ib_ucontext *context, 362 struct vm_area_struct *vma) 363 { 364 struct hns_roce_dev *hr_dev = to_hr_dev(context->device); 365 366 switch (vma->vm_pgoff) { 367 case 0: 368 return rdma_user_mmap_io(context, vma, 369 to_hr_ucontext(context)->uar.pfn, 370 PAGE_SIZE, 371 pgprot_noncached(vma->vm_page_prot)); 372 373 /* vm_pgoff: 1 -- TPTR */ 374 case 1: 375 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size) 376 return -EINVAL; 377 /* 378 * FIXME: using io_remap_pfn_range on the dma address returned 379 * by dma_alloc_coherent is totally wrong. 380 */ 381 return rdma_user_mmap_io(context, vma, 382 hr_dev->tptr_dma_addr >> PAGE_SHIFT, 383 hr_dev->tptr_size, 384 vma->vm_page_prot); 385 386 default: 387 return -EINVAL; 388 } 389 } 390 391 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num, 392 struct ib_port_immutable *immutable) 393 { 394 struct ib_port_attr attr; 395 int ret; 396 397 ret = ib_query_port(ib_dev, port_num, &attr); 398 if (ret) 399 return ret; 400 401 immutable->pkey_tbl_len = attr.pkey_tbl_len; 402 immutable->gid_tbl_len = attr.gid_tbl_len; 403 404 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 405 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 406 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 407 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 408 409 return 0; 410 } 411 412 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 413 { 414 } 415 416 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 417 { 418 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 419 420 hr_dev->active = false; 421 unregister_netdevice_notifier(&iboe->nb); 422 ib_unregister_device(&hr_dev->ib_dev); 423 } 424 425 static const struct ib_device_ops hns_roce_dev_ops = { 426 .add_gid = hns_roce_add_gid, 427 .alloc_pd = hns_roce_alloc_pd, 428 .alloc_ucontext = hns_roce_alloc_ucontext, 429 .create_ah = hns_roce_create_ah, 430 .create_cq = hns_roce_ib_create_cq, 431 .create_qp = hns_roce_create_qp, 432 .dealloc_pd = hns_roce_dealloc_pd, 433 .dealloc_ucontext = hns_roce_dealloc_ucontext, 434 .del_gid = hns_roce_del_gid, 435 .dereg_mr = hns_roce_dereg_mr, 436 .destroy_ah = hns_roce_destroy_ah, 437 .destroy_cq = hns_roce_ib_destroy_cq, 438 .disassociate_ucontext = hns_roce_disassociate_ucontext, 439 .fill_res_entry = hns_roce_fill_res_entry, 440 .get_dma_mr = hns_roce_get_dma_mr, 441 .get_link_layer = hns_roce_get_link_layer, 442 .get_port_immutable = hns_roce_port_immutable, 443 .mmap = hns_roce_mmap, 444 .modify_device = hns_roce_modify_device, 445 .modify_port = hns_roce_modify_port, 446 .modify_qp = hns_roce_modify_qp, 447 .query_ah = hns_roce_query_ah, 448 .query_device = hns_roce_query_device, 449 .query_pkey = hns_roce_query_pkey, 450 .query_port = hns_roce_query_port, 451 .reg_user_mr = hns_roce_reg_user_mr, 452 453 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah), 454 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 455 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 456 }; 457 458 static const struct ib_device_ops hns_roce_dev_mr_ops = { 459 .rereg_user_mr = hns_roce_rereg_user_mr, 460 }; 461 462 static const struct ib_device_ops hns_roce_dev_mw_ops = { 463 .alloc_mw = hns_roce_alloc_mw, 464 .dealloc_mw = hns_roce_dealloc_mw, 465 }; 466 467 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 468 .alloc_mr = hns_roce_alloc_mr, 469 .map_mr_sg = hns_roce_map_mr_sg, 470 }; 471 472 static const struct ib_device_ops hns_roce_dev_srq_ops = { 473 .create_srq = hns_roce_create_srq, 474 .destroy_srq = hns_roce_destroy_srq, 475 476 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), 477 }; 478 479 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 480 { 481 int ret; 482 struct hns_roce_ib_iboe *iboe = NULL; 483 struct ib_device *ib_dev = NULL; 484 struct device *dev = hr_dev->dev; 485 unsigned int i; 486 487 iboe = &hr_dev->iboe; 488 spin_lock_init(&iboe->lock); 489 490 ib_dev = &hr_dev->ib_dev; 491 492 ib_dev->owner = THIS_MODULE; 493 ib_dev->node_type = RDMA_NODE_IB_CA; 494 ib_dev->dev.parent = dev; 495 496 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 497 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 498 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 499 ib_dev->uverbs_abi_ver = 1; 500 ib_dev->uverbs_cmd_mask = 501 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) | 502 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) | 503 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) | 504 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) | 505 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) | 506 (1ULL << IB_USER_VERBS_CMD_REG_MR) | 507 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) | 508 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 509 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) | 510 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) | 511 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) | 512 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) | 513 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) | 514 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP); 515 516 ib_dev->uverbs_ex_cmd_mask |= 517 (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 518 519 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) { 520 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR); 521 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 522 } 523 524 /* MW */ 525 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) { 526 ib_dev->uverbs_cmd_mask |= 527 (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) | 528 (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW); 529 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 530 } 531 532 /* FRMR */ 533 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 534 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 535 536 /* SRQ */ 537 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 538 ib_dev->uverbs_cmd_mask |= 539 (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) | 540 (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) | 541 (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) | 542 (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) | 543 (1ULL << IB_USER_VERBS_CMD_POST_SRQ_RECV); 544 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 545 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 546 } 547 548 ib_dev->driver_id = RDMA_DRIVER_HNS; 549 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 550 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 551 for (i = 0; i < hr_dev->caps.num_ports; i++) { 552 if (!hr_dev->iboe.netdevs[i]) 553 continue; 554 555 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i], 556 i + 1); 557 if (ret) 558 return ret; 559 } 560 ret = ib_register_device(ib_dev, "hns_%d"); 561 if (ret) { 562 dev_err(dev, "ib_register_device failed!\n"); 563 return ret; 564 } 565 566 ret = hns_roce_setup_mtu_mac(hr_dev); 567 if (ret) { 568 dev_err(dev, "setup_mtu_mac failed!\n"); 569 goto error_failed_setup_mtu_mac; 570 } 571 572 iboe->nb.notifier_call = hns_roce_netdev_event; 573 ret = register_netdevice_notifier(&iboe->nb); 574 if (ret) { 575 dev_err(dev, "register_netdevice_notifier failed!\n"); 576 goto error_failed_setup_mtu_mac; 577 } 578 579 hr_dev->active = true; 580 return 0; 581 582 error_failed_setup_mtu_mac: 583 ib_unregister_device(ib_dev); 584 585 return ret; 586 } 587 588 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 589 { 590 int ret; 591 struct device *dev = hr_dev->dev; 592 593 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table, 594 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz, 595 hr_dev->caps.num_mtt_segs, 1); 596 if (ret) { 597 dev_err(dev, "Failed to init MTT context memory, aborting.\n"); 598 return ret; 599 } 600 601 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) { 602 ret = hns_roce_init_hem_table(hr_dev, 603 &hr_dev->mr_table.mtt_cqe_table, 604 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz, 605 hr_dev->caps.num_cqe_segs, 1); 606 if (ret) { 607 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n"); 608 goto err_unmap_cqe; 609 } 610 } 611 612 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 613 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 614 hr_dev->caps.num_mtpts, 1); 615 if (ret) { 616 dev_err(dev, "Failed to init MTPT context memory, aborting.\n"); 617 goto err_unmap_mtt; 618 } 619 620 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 621 HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz, 622 hr_dev->caps.num_qps, 1); 623 if (ret) { 624 dev_err(dev, "Failed to init QP context memory, aborting.\n"); 625 goto err_unmap_dmpt; 626 } 627 628 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 629 HEM_TYPE_IRRL, 630 hr_dev->caps.irrl_entry_sz * 631 hr_dev->caps.max_qp_init_rdma, 632 hr_dev->caps.num_qps, 1); 633 if (ret) { 634 dev_err(dev, "Failed to init irrl_table memory, aborting.\n"); 635 goto err_unmap_qp; 636 } 637 638 if (hr_dev->caps.trrl_entry_sz) { 639 ret = hns_roce_init_hem_table(hr_dev, 640 &hr_dev->qp_table.trrl_table, 641 HEM_TYPE_TRRL, 642 hr_dev->caps.trrl_entry_sz * 643 hr_dev->caps.max_qp_dest_rdma, 644 hr_dev->caps.num_qps, 1); 645 if (ret) { 646 dev_err(dev, 647 "Failed to init trrl_table memory, aborting.\n"); 648 goto err_unmap_irrl; 649 } 650 } 651 652 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 653 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 654 hr_dev->caps.num_cqs, 1); 655 if (ret) { 656 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 657 goto err_unmap_trrl; 658 } 659 660 if (hr_dev->caps.srqc_entry_sz) { 661 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 662 HEM_TYPE_SRQC, 663 hr_dev->caps.srqc_entry_sz, 664 hr_dev->caps.num_srqs, 1); 665 if (ret) { 666 dev_err(dev, 667 "Failed to init SRQ context memory, aborting.\n"); 668 goto err_unmap_cq; 669 } 670 } 671 672 if (hr_dev->caps.num_srqwqe_segs) { 673 ret = hns_roce_init_hem_table(hr_dev, 674 &hr_dev->mr_table.mtt_srqwqe_table, 675 HEM_TYPE_SRQWQE, 676 hr_dev->caps.mtt_entry_sz, 677 hr_dev->caps.num_srqwqe_segs, 1); 678 if (ret) { 679 dev_err(dev, 680 "Failed to init MTT srqwqe memory, aborting.\n"); 681 goto err_unmap_srq; 682 } 683 } 684 685 if (hr_dev->caps.num_idx_segs) { 686 ret = hns_roce_init_hem_table(hr_dev, 687 &hr_dev->mr_table.mtt_idx_table, 688 HEM_TYPE_IDX, 689 hr_dev->caps.idx_entry_sz, 690 hr_dev->caps.num_idx_segs, 1); 691 if (ret) { 692 dev_err(dev, 693 "Failed to init MTT idx memory, aborting.\n"); 694 goto err_unmap_srqwqe; 695 } 696 } 697 698 if (hr_dev->caps.sccc_entry_sz) { 699 ret = hns_roce_init_hem_table(hr_dev, 700 &hr_dev->qp_table.sccc_table, 701 HEM_TYPE_SCCC, 702 hr_dev->caps.sccc_entry_sz, 703 hr_dev->caps.num_qps, 1); 704 if (ret) { 705 dev_err(dev, 706 "Failed to init SCC context memory, aborting.\n"); 707 goto err_unmap_idx; 708 } 709 } 710 711 if (hr_dev->caps.qpc_timer_entry_sz) { 712 ret = hns_roce_init_hem_table(hr_dev, 713 &hr_dev->qpc_timer_table, 714 HEM_TYPE_QPC_TIMER, 715 hr_dev->caps.qpc_timer_entry_sz, 716 hr_dev->caps.num_qpc_timer, 1); 717 if (ret) { 718 dev_err(dev, 719 "Failed to init QPC timer memory, aborting.\n"); 720 goto err_unmap_ctx; 721 } 722 } 723 724 if (hr_dev->caps.cqc_timer_entry_sz) { 725 ret = hns_roce_init_hem_table(hr_dev, 726 &hr_dev->cqc_timer_table, 727 HEM_TYPE_CQC_TIMER, 728 hr_dev->caps.cqc_timer_entry_sz, 729 hr_dev->caps.num_cqc_timer, 1); 730 if (ret) { 731 dev_err(dev, 732 "Failed to init CQC timer memory, aborting.\n"); 733 goto err_unmap_qpc_timer; 734 } 735 } 736 737 return 0; 738 739 err_unmap_qpc_timer: 740 if (hr_dev->caps.qpc_timer_entry_sz) 741 hns_roce_cleanup_hem_table(hr_dev, 742 &hr_dev->qpc_timer_table); 743 744 err_unmap_ctx: 745 if (hr_dev->caps.sccc_entry_sz) 746 hns_roce_cleanup_hem_table(hr_dev, 747 &hr_dev->qp_table.sccc_table); 748 749 err_unmap_idx: 750 if (hr_dev->caps.num_idx_segs) 751 hns_roce_cleanup_hem_table(hr_dev, 752 &hr_dev->mr_table.mtt_idx_table); 753 754 err_unmap_srqwqe: 755 if (hr_dev->caps.num_srqwqe_segs) 756 hns_roce_cleanup_hem_table(hr_dev, 757 &hr_dev->mr_table.mtt_srqwqe_table); 758 759 err_unmap_srq: 760 if (hr_dev->caps.srqc_entry_sz) 761 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 762 763 err_unmap_cq: 764 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 765 766 err_unmap_trrl: 767 if (hr_dev->caps.trrl_entry_sz) 768 hns_roce_cleanup_hem_table(hr_dev, 769 &hr_dev->qp_table.trrl_table); 770 771 err_unmap_irrl: 772 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 773 774 err_unmap_qp: 775 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 776 777 err_unmap_dmpt: 778 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 779 780 err_unmap_mtt: 781 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) 782 hns_roce_cleanup_hem_table(hr_dev, 783 &hr_dev->mr_table.mtt_cqe_table); 784 785 err_unmap_cqe: 786 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table); 787 788 return ret; 789 } 790 791 /** 792 * hns_roce_setup_hca - setup host channel adapter 793 * @hr_dev: pointer to hns roce device 794 * Return : int 795 */ 796 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 797 { 798 int ret; 799 struct device *dev = hr_dev->dev; 800 801 spin_lock_init(&hr_dev->sm_lock); 802 spin_lock_init(&hr_dev->bt_cmd_lock); 803 804 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 805 INIT_LIST_HEAD(&hr_dev->pgdir_list); 806 mutex_init(&hr_dev->pgdir_mutex); 807 } 808 809 ret = hns_roce_init_uar_table(hr_dev); 810 if (ret) { 811 dev_err(dev, "Failed to initialize uar table. aborting\n"); 812 return ret; 813 } 814 815 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 816 if (ret) { 817 dev_err(dev, "Failed to allocate priv_uar.\n"); 818 goto err_uar_table_free; 819 } 820 821 ret = hns_roce_init_pd_table(hr_dev); 822 if (ret) { 823 dev_err(dev, "Failed to init protected domain table.\n"); 824 goto err_uar_alloc_free; 825 } 826 827 ret = hns_roce_init_mr_table(hr_dev); 828 if (ret) { 829 dev_err(dev, "Failed to init memory region table.\n"); 830 goto err_pd_table_free; 831 } 832 833 ret = hns_roce_init_cq_table(hr_dev); 834 if (ret) { 835 dev_err(dev, "Failed to init completion queue table.\n"); 836 goto err_mr_table_free; 837 } 838 839 ret = hns_roce_init_qp_table(hr_dev); 840 if (ret) { 841 dev_err(dev, "Failed to init queue pair table.\n"); 842 goto err_cq_table_free; 843 } 844 845 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 846 ret = hns_roce_init_srq_table(hr_dev); 847 if (ret) { 848 dev_err(dev, 849 "Failed to init share receive queue table.\n"); 850 goto err_qp_table_free; 851 } 852 } 853 854 return 0; 855 856 err_qp_table_free: 857 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 858 hns_roce_cleanup_qp_table(hr_dev); 859 860 err_cq_table_free: 861 hns_roce_cleanup_cq_table(hr_dev); 862 863 err_mr_table_free: 864 hns_roce_cleanup_mr_table(hr_dev); 865 866 err_pd_table_free: 867 hns_roce_cleanup_pd_table(hr_dev); 868 869 err_uar_alloc_free: 870 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar); 871 872 err_uar_table_free: 873 hns_roce_cleanup_uar_table(hr_dev); 874 return ret; 875 } 876 877 int hns_roce_init(struct hns_roce_dev *hr_dev) 878 { 879 int ret; 880 struct device *dev = hr_dev->dev; 881 882 if (hr_dev->hw->reset) { 883 ret = hr_dev->hw->reset(hr_dev, true); 884 if (ret) { 885 dev_err(dev, "Reset RoCE engine failed!\n"); 886 return ret; 887 } 888 } 889 hr_dev->is_reset = false; 890 891 if (hr_dev->hw->cmq_init) { 892 ret = hr_dev->hw->cmq_init(hr_dev); 893 if (ret) { 894 dev_err(dev, "Init RoCE Command Queue failed!\n"); 895 goto error_failed_cmq_init; 896 } 897 } 898 899 ret = hr_dev->hw->hw_profile(hr_dev); 900 if (ret) { 901 dev_err(dev, "Get RoCE engine profile failed!\n"); 902 goto error_failed_cmd_init; 903 } 904 905 ret = hns_roce_cmd_init(hr_dev); 906 if (ret) { 907 dev_err(dev, "cmd init failed!\n"); 908 goto error_failed_cmd_init; 909 } 910 911 ret = hr_dev->hw->init_eq(hr_dev); 912 if (ret) { 913 dev_err(dev, "eq init failed!\n"); 914 goto error_failed_eq_table; 915 } 916 917 if (hr_dev->cmd_mod) { 918 ret = hns_roce_cmd_use_events(hr_dev); 919 if (ret) { 920 dev_err(dev, "Switch to event-driven cmd failed!\n"); 921 goto error_failed_use_event; 922 } 923 } 924 925 ret = hns_roce_init_hem(hr_dev); 926 if (ret) { 927 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 928 goto error_failed_init_hem; 929 } 930 931 ret = hns_roce_setup_hca(hr_dev); 932 if (ret) { 933 dev_err(dev, "setup hca failed!\n"); 934 goto error_failed_setup_hca; 935 } 936 937 if (hr_dev->hw->hw_init) { 938 ret = hr_dev->hw->hw_init(hr_dev); 939 if (ret) { 940 dev_err(dev, "hw_init failed!\n"); 941 goto error_failed_engine_init; 942 } 943 } 944 945 ret = hns_roce_register_device(hr_dev); 946 if (ret) 947 goto error_failed_register_device; 948 949 return 0; 950 951 error_failed_register_device: 952 if (hr_dev->hw->hw_exit) 953 hr_dev->hw->hw_exit(hr_dev); 954 955 error_failed_engine_init: 956 hns_roce_cleanup_bitmap(hr_dev); 957 958 error_failed_setup_hca: 959 hns_roce_cleanup_hem(hr_dev); 960 961 error_failed_init_hem: 962 if (hr_dev->cmd_mod) 963 hns_roce_cmd_use_polling(hr_dev); 964 965 error_failed_use_event: 966 hr_dev->hw->cleanup_eq(hr_dev); 967 968 error_failed_eq_table: 969 hns_roce_cmd_cleanup(hr_dev); 970 971 error_failed_cmd_init: 972 if (hr_dev->hw->cmq_exit) 973 hr_dev->hw->cmq_exit(hr_dev); 974 975 error_failed_cmq_init: 976 if (hr_dev->hw->reset) { 977 if (hr_dev->hw->reset(hr_dev, false)) 978 dev_err(dev, "Dereset RoCE engine failed!\n"); 979 } 980 981 return ret; 982 } 983 EXPORT_SYMBOL_GPL(hns_roce_init); 984 985 void hns_roce_exit(struct hns_roce_dev *hr_dev) 986 { 987 hns_roce_unregister_device(hr_dev); 988 989 if (hr_dev->hw->hw_exit) 990 hr_dev->hw->hw_exit(hr_dev); 991 hns_roce_cleanup_bitmap(hr_dev); 992 hns_roce_cleanup_hem(hr_dev); 993 994 if (hr_dev->cmd_mod) 995 hns_roce_cmd_use_polling(hr_dev); 996 997 hr_dev->hw->cleanup_eq(hr_dev); 998 hns_roce_cmd_cleanup(hr_dev); 999 if (hr_dev->hw->cmq_exit) 1000 hr_dev->hw->cmq_exit(hr_dev); 1001 if (hr_dev->hw->reset) 1002 hr_dev->hw->reset(hr_dev, false); 1003 } 1004 EXPORT_SYMBOL_GPL(hns_roce_exit); 1005 1006 MODULE_LICENSE("Dual BSD/GPL"); 1007 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 1008 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 1009 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 1010 MODULE_DESCRIPTION("HNS RoCE Driver"); 1011