1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IB_H 34 #define MLX5_IB_H 35 36 #include <linux/kernel.h> 37 #include <linux/sched.h> 38 #include <rdma/ib_verbs.h> 39 #include <rdma/ib_umem.h> 40 #include <rdma/ib_smi.h> 41 #include <linux/mlx5/driver.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/fs.h> 44 #include <linux/mlx5/qp.h> 45 #include <linux/types.h> 46 #include <linux/mlx5/transobj.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/mlx5-abi.h> 49 #include <rdma/uverbs_ioctl.h> 50 #include <rdma/mlx5_user_ioctl_cmds.h> 51 #include <rdma/mlx5_user_ioctl_verbs.h> 52 53 #include "srq.h" 54 55 #define mlx5_ib_dbg(_dev, format, arg...) \ 56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 57 __LINE__, current->pid, ##arg) 58 59 #define mlx5_ib_err(_dev, format, arg...) \ 60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 61 __LINE__, current->pid, ##arg) 62 63 #define mlx5_ib_warn(_dev, format, arg...) \ 64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 65 __LINE__, current->pid, ##arg) 66 67 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 68 sizeof(((type *)0)->fld) <= (sz)) 69 #define MLX5_IB_DEFAULT_UIDX 0xffffff 70 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 71 72 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 73 74 enum { 75 MLX5_IB_MMAP_CMD_SHIFT = 8, 76 MLX5_IB_MMAP_CMD_MASK = 0xff, 77 }; 78 79 enum { 80 MLX5_RES_SCAT_DATA32_CQE = 0x1, 81 MLX5_RES_SCAT_DATA64_CQE = 0x2, 82 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 83 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 84 }; 85 86 enum mlx5_ib_mad_ifc_flags { 87 MLX5_MAD_IFC_IGNORE_MKEY = 1, 88 MLX5_MAD_IFC_IGNORE_BKEY = 2, 89 MLX5_MAD_IFC_NET_VIEW = 4, 90 }; 91 92 enum { 93 MLX5_CROSS_CHANNEL_BFREG = 0, 94 }; 95 96 enum { 97 MLX5_CQE_VERSION_V0, 98 MLX5_CQE_VERSION_V1, 99 }; 100 101 enum { 102 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 103 MLX5_TM_MAX_SGE = 1, 104 }; 105 106 enum { 107 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 108 MLX5_IB_INVALID_BFREG = BIT(31), 109 }; 110 111 enum { 112 MLX5_MAX_MEMIC_PAGES = 0x100, 113 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 114 }; 115 116 enum { 117 MLX5_MEMIC_BASE_ALIGN = 6, 118 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 119 }; 120 121 enum mlx5_ib_mmap_type { 122 MLX5_IB_MMAP_TYPE_MEMIC = 1, 123 }; 124 125 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) \ 126 (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) 127 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) 128 129 struct mlx5_ib_ucontext { 130 struct ib_ucontext ibucontext; 131 struct list_head db_page_list; 132 133 /* protect doorbell record alloc/free 134 */ 135 struct mutex db_page_mutex; 136 struct mlx5_bfreg_info bfregi; 137 u8 cqe_version; 138 /* Transport Domain number */ 139 u32 tdn; 140 141 u64 lib_caps; 142 u16 devx_uid; 143 /* For RoCE LAG TX affinity */ 144 atomic_t tx_port_affinity; 145 }; 146 147 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 148 { 149 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 150 } 151 152 struct mlx5_ib_pd { 153 struct ib_pd ibpd; 154 u32 pdn; 155 u16 uid; 156 }; 157 158 enum { 159 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 160 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 161 MLX5_IB_FLOW_ACTION_DECAP, 162 }; 163 164 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 165 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 166 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 167 #error "Invalid number of bypass priorities" 168 #endif 169 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 170 171 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 172 #define MLX5_IB_NUM_SNIFFER_FTS 2 173 #define MLX5_IB_NUM_EGRESS_FTS 1 174 struct mlx5_ib_flow_prio { 175 struct mlx5_flow_table *flow_table; 176 unsigned int refcount; 177 }; 178 179 struct mlx5_ib_flow_handler { 180 struct list_head list; 181 struct ib_flow ibflow; 182 struct mlx5_ib_flow_prio *prio; 183 struct mlx5_flow_handle *rule; 184 struct ib_counters *ibcounters; 185 struct mlx5_ib_dev *dev; 186 struct mlx5_ib_flow_matcher *flow_matcher; 187 }; 188 189 struct mlx5_ib_flow_matcher { 190 struct mlx5_ib_match_params matcher_mask; 191 int mask_len; 192 enum mlx5_ib_flow_type flow_type; 193 enum mlx5_flow_namespace_type ns_type; 194 u16 priority; 195 struct mlx5_core_dev *mdev; 196 atomic_t usecnt; 197 u8 match_criteria_enable; 198 }; 199 200 struct mlx5_ib_flow_db { 201 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 202 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 203 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 204 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 205 struct mlx5_ib_flow_prio fdb; 206 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 207 struct mlx5_flow_table *lag_demux_ft; 208 /* Protect flow steering bypass flow tables 209 * when add/del flow rules. 210 * only single add/removal of flow steering rule could be done 211 * simultaneously. 212 */ 213 struct mutex lock; 214 }; 215 216 /* Use macros here so that don't have to duplicate 217 * enum ib_send_flags and enum ib_qp_type for low-level driver 218 */ 219 220 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 221 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 222 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 223 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 224 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 225 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 226 227 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 228 /* 229 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 230 * creates the actual hardware QP. 231 */ 232 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 233 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 234 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 235 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 236 237 #define MLX5_IB_UMR_OCTOWORD 16 238 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 239 240 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 241 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 242 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 243 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 244 #define MLX5_IB_UPD_XLT_PD BIT(4) 245 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 246 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 247 248 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 249 * 250 * These flags are intended for internal use by the mlx5_ib driver, and they 251 * rely on the range reserved for that use in the ib_qp_create_flags enum. 252 */ 253 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 254 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 255 256 struct wr_list { 257 u16 opcode; 258 u16 next; 259 }; 260 261 enum mlx5_ib_rq_flags { 262 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 263 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 264 }; 265 266 struct mlx5_ib_wq { 267 struct mlx5_frag_buf_ctrl fbc; 268 u64 *wrid; 269 u32 *wr_data; 270 struct wr_list *w_list; 271 unsigned *wqe_head; 272 u16 unsig_count; 273 274 /* serialize post to the work queue 275 */ 276 spinlock_t lock; 277 int wqe_cnt; 278 int max_post; 279 int max_gs; 280 int offset; 281 int wqe_shift; 282 unsigned head; 283 unsigned tail; 284 u16 cur_post; 285 void *cur_edge; 286 }; 287 288 enum mlx5_ib_wq_flags { 289 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 290 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 291 }; 292 293 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 294 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 295 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 296 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 297 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 298 299 struct mlx5_ib_rwq { 300 struct ib_wq ibwq; 301 struct mlx5_core_qp core_qp; 302 u32 rq_num_pas; 303 u32 log_rq_stride; 304 u32 log_rq_size; 305 u32 rq_page_offset; 306 u32 log_page_size; 307 u32 log_num_strides; 308 u32 two_byte_shift_en; 309 u32 single_stride_log_num_of_bytes; 310 struct ib_umem *umem; 311 size_t buf_size; 312 unsigned int page_shift; 313 int create_type; 314 struct mlx5_db db; 315 u32 user_index; 316 u32 wqe_count; 317 u32 wqe_shift; 318 int wq_sig; 319 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 320 }; 321 322 enum { 323 MLX5_QP_USER, 324 MLX5_QP_KERNEL, 325 MLX5_QP_EMPTY 326 }; 327 328 enum { 329 MLX5_WQ_USER, 330 MLX5_WQ_KERNEL 331 }; 332 333 struct mlx5_ib_rwq_ind_table { 334 struct ib_rwq_ind_table ib_rwq_ind_tbl; 335 u32 rqtn; 336 u16 uid; 337 }; 338 339 struct mlx5_ib_ubuffer { 340 struct ib_umem *umem; 341 int buf_size; 342 u64 buf_addr; 343 }; 344 345 struct mlx5_ib_qp_base { 346 struct mlx5_ib_qp *container_mibqp; 347 struct mlx5_core_qp mqp; 348 struct mlx5_ib_ubuffer ubuffer; 349 }; 350 351 struct mlx5_ib_qp_trans { 352 struct mlx5_ib_qp_base base; 353 u16 xrcdn; 354 u8 alt_port; 355 u8 atomic_rd_en; 356 u8 resp_depth; 357 }; 358 359 struct mlx5_ib_rss_qp { 360 u32 tirn; 361 }; 362 363 struct mlx5_ib_rq { 364 struct mlx5_ib_qp_base base; 365 struct mlx5_ib_wq *rq; 366 struct mlx5_ib_ubuffer ubuffer; 367 struct mlx5_db *doorbell; 368 u32 tirn; 369 u8 state; 370 u32 flags; 371 }; 372 373 struct mlx5_ib_sq { 374 struct mlx5_ib_qp_base base; 375 struct mlx5_ib_wq *sq; 376 struct mlx5_ib_ubuffer ubuffer; 377 struct mlx5_db *doorbell; 378 struct mlx5_flow_handle *flow_rule; 379 u32 tisn; 380 u8 state; 381 }; 382 383 struct mlx5_ib_raw_packet_qp { 384 struct mlx5_ib_sq sq; 385 struct mlx5_ib_rq rq; 386 }; 387 388 struct mlx5_bf { 389 int buf_size; 390 unsigned long offset; 391 struct mlx5_sq_bfreg *bfreg; 392 }; 393 394 struct mlx5_ib_dct { 395 struct mlx5_core_dct mdct; 396 u32 *in; 397 }; 398 399 struct mlx5_ib_qp { 400 struct ib_qp ibqp; 401 union { 402 struct mlx5_ib_qp_trans trans_qp; 403 struct mlx5_ib_raw_packet_qp raw_packet_qp; 404 struct mlx5_ib_rss_qp rss_qp; 405 struct mlx5_ib_dct dct; 406 }; 407 struct mlx5_frag_buf buf; 408 409 struct mlx5_db db; 410 struct mlx5_ib_wq rq; 411 412 u8 sq_signal_bits; 413 u8 next_fence; 414 struct mlx5_ib_wq sq; 415 416 /* serialize qp state modifications 417 */ 418 struct mutex mutex; 419 u32 flags; 420 u8 port; 421 u8 state; 422 int wq_sig; 423 int scat_cqe; 424 int max_inline_data; 425 struct mlx5_bf bf; 426 int has_rq; 427 428 /* only for user space QPs. For kernel 429 * we have it from the bf object 430 */ 431 int bfregn; 432 433 int create_type; 434 435 struct list_head qps_list; 436 struct list_head cq_recv_list; 437 struct list_head cq_send_list; 438 struct mlx5_rate_limit rl; 439 u32 underlay_qpn; 440 u32 flags_en; 441 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ 442 enum ib_qp_type qp_sub_type; 443 /* A flag to indicate if there's a new counter is configured 444 * but not take effective 445 */ 446 u32 counter_pending; 447 }; 448 449 struct mlx5_ib_cq_buf { 450 struct mlx5_frag_buf_ctrl fbc; 451 struct mlx5_frag_buf frag_buf; 452 struct ib_umem *umem; 453 int cqe_size; 454 int nent; 455 }; 456 457 enum mlx5_ib_qp_flags { 458 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 459 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 460 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 461 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 462 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 463 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 464 /* QP uses 1 as its source QP number */ 465 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 466 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 467 MLX5_IB_QP_RSS = 1 << 8, 468 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, 469 MLX5_IB_QP_UNDERLAY = 1 << 10, 470 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, 471 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, 472 MLX5_IB_QP_PACKET_BASED_CREDIT = 1 << 13, 473 }; 474 475 struct mlx5_umr_wr { 476 struct ib_send_wr wr; 477 u64 virt_addr; 478 u64 offset; 479 struct ib_pd *pd; 480 unsigned int page_shift; 481 unsigned int xlt_size; 482 u64 length; 483 int access_flags; 484 u32 mkey; 485 u8 ignore_free_state:1; 486 }; 487 488 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 489 { 490 return container_of(wr, struct mlx5_umr_wr, wr); 491 } 492 493 struct mlx5_shared_mr_info { 494 int mr_id; 495 struct ib_umem *umem; 496 }; 497 498 enum mlx5_ib_cq_pr_flags { 499 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 500 }; 501 502 struct mlx5_ib_cq { 503 struct ib_cq ibcq; 504 struct mlx5_core_cq mcq; 505 struct mlx5_ib_cq_buf buf; 506 struct mlx5_db db; 507 508 /* serialize access to the CQ 509 */ 510 spinlock_t lock; 511 512 /* protect resize cq 513 */ 514 struct mutex resize_mutex; 515 struct mlx5_ib_cq_buf *resize_buf; 516 struct ib_umem *resize_umem; 517 int cqe_size; 518 struct list_head list_send_qp; 519 struct list_head list_recv_qp; 520 u32 create_flags; 521 struct list_head wc_list; 522 enum ib_cq_notify_flags notify_flags; 523 struct work_struct notify_work; 524 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 525 }; 526 527 struct mlx5_ib_wc { 528 struct ib_wc wc; 529 struct list_head list; 530 }; 531 532 struct mlx5_ib_srq { 533 struct ib_srq ibsrq; 534 struct mlx5_core_srq msrq; 535 struct mlx5_frag_buf buf; 536 struct mlx5_db db; 537 struct mlx5_frag_buf_ctrl fbc; 538 u64 *wrid; 539 /* protect SRQ hanlding 540 */ 541 spinlock_t lock; 542 int head; 543 int tail; 544 u16 wqe_ctr; 545 struct ib_umem *umem; 546 /* serialize arming a SRQ 547 */ 548 struct mutex mutex; 549 int wq_sig; 550 }; 551 552 struct mlx5_ib_xrcd { 553 struct ib_xrcd ibxrcd; 554 u32 xrcdn; 555 }; 556 557 enum mlx5_ib_mtt_access_flags { 558 MLX5_IB_MTT_READ = (1 << 0), 559 MLX5_IB_MTT_WRITE = (1 << 1), 560 }; 561 562 struct mlx5_user_mmap_entry { 563 struct rdma_user_mmap_entry rdma_entry; 564 u8 mmap_flag; 565 u64 address; 566 }; 567 568 struct mlx5_ib_dm { 569 struct ib_dm ibdm; 570 phys_addr_t dev_addr; 571 u32 type; 572 size_t size; 573 union { 574 struct { 575 u32 obj_id; 576 } icm_dm; 577 /* other dm types specific params should be added here */ 578 }; 579 struct mlx5_user_mmap_entry mentry; 580 }; 581 582 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 583 584 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 585 IB_ACCESS_REMOTE_WRITE |\ 586 IB_ACCESS_REMOTE_READ |\ 587 IB_ACCESS_REMOTE_ATOMIC |\ 588 IB_ZERO_BASED) 589 590 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 591 IB_ACCESS_REMOTE_WRITE |\ 592 IB_ACCESS_REMOTE_READ |\ 593 IB_ZERO_BASED) 594 595 #define mlx5_update_odp_stats(mr, counter_name, value) \ 596 atomic64_add(value, &((mr)->odp_stats.counter_name)) 597 598 struct mlx5_ib_mr { 599 struct ib_mr ibmr; 600 void *descs; 601 dma_addr_t desc_map; 602 int ndescs; 603 int data_length; 604 int meta_ndescs; 605 int meta_length; 606 int max_descs; 607 int desc_size; 608 int access_mode; 609 struct mlx5_core_mkey mmkey; 610 struct ib_umem *umem; 611 struct mlx5_shared_mr_info *smr_info; 612 struct list_head list; 613 int order; 614 bool allocated_from_cache; 615 int npages; 616 struct mlx5_ib_dev *dev; 617 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 618 struct mlx5_core_sig_ctx *sig; 619 void *descs_alloc; 620 int access_flags; /* Needed for rereg MR */ 621 622 struct mlx5_ib_mr *parent; 623 /* Needed for IB_MR_TYPE_INTEGRITY */ 624 struct mlx5_ib_mr *pi_mr; 625 struct mlx5_ib_mr *klm_mr; 626 struct mlx5_ib_mr *mtt_mr; 627 u64 data_iova; 628 u64 pi_iova; 629 630 /* For ODP and implicit */ 631 atomic_t num_deferred_work; 632 struct xarray implicit_children; 633 union { 634 struct rcu_head rcu; 635 struct list_head elm; 636 struct work_struct work; 637 } odp_destroy; 638 struct ib_odp_counters odp_stats; 639 bool is_odp_implicit; 640 641 struct mlx5_async_work cb_work; 642 }; 643 644 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 645 { 646 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 647 mr->umem->is_odp; 648 } 649 650 struct mlx5_ib_mw { 651 struct ib_mw ibmw; 652 struct mlx5_core_mkey mmkey; 653 int ndescs; 654 }; 655 656 struct mlx5_ib_devx_mr { 657 struct mlx5_core_mkey mmkey; 658 int ndescs; 659 }; 660 661 struct mlx5_ib_umr_context { 662 struct ib_cqe cqe; 663 enum ib_wc_status status; 664 struct completion done; 665 }; 666 667 struct umr_common { 668 struct ib_pd *pd; 669 struct ib_cq *cq; 670 struct ib_qp *qp; 671 /* control access to UMR QP 672 */ 673 struct semaphore sem; 674 }; 675 676 enum { 677 MLX5_FMR_INVALID, 678 MLX5_FMR_VALID, 679 MLX5_FMR_BUSY, 680 }; 681 682 struct mlx5_cache_ent { 683 struct list_head head; 684 /* sync access to the cahce entry 685 */ 686 spinlock_t lock; 687 688 689 char name[4]; 690 u32 order; 691 u32 xlt; 692 u32 access_mode; 693 u32 page; 694 695 u32 size; 696 u32 cur; 697 u32 miss; 698 u32 limit; 699 700 struct mlx5_ib_dev *dev; 701 struct work_struct work; 702 struct delayed_work dwork; 703 int pending; 704 struct completion compl; 705 }; 706 707 struct mlx5_mr_cache { 708 struct workqueue_struct *wq; 709 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 710 int stopped; 711 struct dentry *root; 712 unsigned long last_add; 713 }; 714 715 struct mlx5_ib_gsi_qp; 716 717 struct mlx5_ib_port_resources { 718 struct mlx5_ib_resources *devr; 719 struct mlx5_ib_gsi_qp *gsi; 720 struct work_struct pkey_change_work; 721 }; 722 723 struct mlx5_ib_resources { 724 struct ib_cq *c0; 725 struct ib_xrcd *x0; 726 struct ib_xrcd *x1; 727 struct ib_pd *p0; 728 struct ib_srq *s0; 729 struct ib_srq *s1; 730 struct mlx5_ib_port_resources ports[2]; 731 /* Protects changes to the port resources */ 732 struct mutex mutex; 733 }; 734 735 struct mlx5_ib_counters { 736 const char **names; 737 size_t *offsets; 738 u32 num_q_counters; 739 u32 num_cong_counters; 740 u32 num_ext_ppcnt_counters; 741 u16 set_id; 742 bool set_id_valid; 743 }; 744 745 struct mlx5_ib_multiport_info; 746 747 struct mlx5_ib_multiport { 748 struct mlx5_ib_multiport_info *mpi; 749 /* To be held when accessing the multiport info */ 750 spinlock_t mpi_lock; 751 }; 752 753 struct mlx5_roce { 754 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 755 * netdev pointer 756 */ 757 rwlock_t netdev_lock; 758 struct net_device *netdev; 759 struct notifier_block nb; 760 atomic_t tx_port_affinity; 761 enum ib_port_state last_port_state; 762 struct mlx5_ib_dev *dev; 763 u8 native_port_num; 764 }; 765 766 struct mlx5_ib_port { 767 struct mlx5_ib_counters cnts; 768 struct mlx5_ib_multiport mp; 769 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 770 struct mlx5_roce roce; 771 struct mlx5_eswitch_rep *rep; 772 }; 773 774 struct mlx5_ib_dbg_param { 775 int offset; 776 struct mlx5_ib_dev *dev; 777 struct dentry *dentry; 778 u8 port_num; 779 }; 780 781 enum mlx5_ib_dbg_cc_types { 782 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 783 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 784 MLX5_IB_DBG_CC_RP_TIME_RESET, 785 MLX5_IB_DBG_CC_RP_BYTE_RESET, 786 MLX5_IB_DBG_CC_RP_THRESHOLD, 787 MLX5_IB_DBG_CC_RP_AI_RATE, 788 MLX5_IB_DBG_CC_RP_HAI_RATE, 789 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 790 MLX5_IB_DBG_CC_RP_MIN_RATE, 791 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 792 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 793 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 794 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 795 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 796 MLX5_IB_DBG_CC_RP_GD, 797 MLX5_IB_DBG_CC_NP_CNP_DSCP, 798 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 799 MLX5_IB_DBG_CC_NP_CNP_PRIO, 800 MLX5_IB_DBG_CC_MAX, 801 }; 802 803 struct mlx5_ib_dbg_cc_params { 804 struct dentry *root; 805 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 806 }; 807 808 enum { 809 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 810 }; 811 812 struct mlx5_ib_delay_drop { 813 struct mlx5_ib_dev *dev; 814 struct work_struct delay_drop_work; 815 /* serialize setting of delay drop */ 816 struct mutex lock; 817 u32 timeout; 818 bool activate; 819 atomic_t events_cnt; 820 atomic_t rqs_cnt; 821 struct dentry *dir_debugfs; 822 }; 823 824 enum mlx5_ib_stages { 825 MLX5_IB_STAGE_INIT, 826 MLX5_IB_STAGE_FLOW_DB, 827 MLX5_IB_STAGE_CAPS, 828 MLX5_IB_STAGE_NON_DEFAULT_CB, 829 MLX5_IB_STAGE_ROCE, 830 MLX5_IB_STAGE_SRQ, 831 MLX5_IB_STAGE_DEVICE_RESOURCES, 832 MLX5_IB_STAGE_DEVICE_NOTIFIER, 833 MLX5_IB_STAGE_ODP, 834 MLX5_IB_STAGE_COUNTERS, 835 MLX5_IB_STAGE_CONG_DEBUGFS, 836 MLX5_IB_STAGE_UAR, 837 MLX5_IB_STAGE_BFREG, 838 MLX5_IB_STAGE_PRE_IB_REG_UMR, 839 MLX5_IB_STAGE_WHITELIST_UID, 840 MLX5_IB_STAGE_IB_REG, 841 MLX5_IB_STAGE_POST_IB_REG_UMR, 842 MLX5_IB_STAGE_DELAY_DROP, 843 MLX5_IB_STAGE_CLASS_ATTR, 844 MLX5_IB_STAGE_MAX, 845 }; 846 847 struct mlx5_ib_stage { 848 int (*init)(struct mlx5_ib_dev *dev); 849 void (*cleanup)(struct mlx5_ib_dev *dev); 850 }; 851 852 #define STAGE_CREATE(_stage, _init, _cleanup) \ 853 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 854 855 struct mlx5_ib_profile { 856 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 857 }; 858 859 struct mlx5_ib_multiport_info { 860 struct list_head list; 861 struct mlx5_ib_dev *ibdev; 862 struct mlx5_core_dev *mdev; 863 struct notifier_block mdev_events; 864 struct completion unref_comp; 865 u64 sys_image_guid; 866 u32 mdev_refcnt; 867 bool is_master; 868 bool unaffiliate; 869 }; 870 871 struct mlx5_ib_flow_action { 872 struct ib_flow_action ib_action; 873 union { 874 struct { 875 u64 ib_flags; 876 struct mlx5_accel_esp_xfrm *ctx; 877 } esp_aes_gcm; 878 struct { 879 struct mlx5_ib_dev *dev; 880 u32 sub_type; 881 union { 882 struct mlx5_modify_hdr *modify_hdr; 883 struct mlx5_pkt_reformat *pkt_reformat; 884 }; 885 } flow_action_raw; 886 }; 887 }; 888 889 struct mlx5_dm { 890 struct mlx5_core_dev *dev; 891 /* This lock is used to protect the access to the shared 892 * allocation map when concurrent requests by different 893 * processes are handled. 894 */ 895 spinlock_t lock; 896 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 897 }; 898 899 struct mlx5_read_counters_attr { 900 struct mlx5_fc *hw_cntrs_hndl; 901 u64 *out; 902 u32 flags; 903 }; 904 905 enum mlx5_ib_counters_type { 906 MLX5_IB_COUNTERS_FLOW, 907 }; 908 909 struct mlx5_ib_mcounters { 910 struct ib_counters ibcntrs; 911 enum mlx5_ib_counters_type type; 912 /* number of counters supported for this counters type */ 913 u32 counters_num; 914 struct mlx5_fc *hw_cntrs_hndl; 915 /* read function for this counters type */ 916 int (*read_counters)(struct ib_device *ibdev, 917 struct mlx5_read_counters_attr *read_attr); 918 /* max index set as part of create_flow */ 919 u32 cntrs_max_index; 920 /* number of counters data entries (<description,index> pair) */ 921 u32 ncounters; 922 /* counters data array for descriptions and indexes */ 923 struct mlx5_ib_flow_counters_desc *counters_data; 924 /* protects access to mcounters internal data */ 925 struct mutex mcntrs_mutex; 926 }; 927 928 static inline struct mlx5_ib_mcounters * 929 to_mcounters(struct ib_counters *ibcntrs) 930 { 931 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 932 } 933 934 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 935 bool is_egress, 936 struct mlx5_flow_act *action); 937 struct mlx5_ib_lb_state { 938 /* protect the user_td */ 939 struct mutex mutex; 940 u32 user_td; 941 int qps; 942 bool enabled; 943 }; 944 945 struct mlx5_ib_pf_eq { 946 struct notifier_block irq_nb; 947 struct mlx5_ib_dev *dev; 948 struct mlx5_eq *core; 949 struct work_struct work; 950 spinlock_t lock; /* Pagefaults spinlock */ 951 struct workqueue_struct *wq; 952 mempool_t *pool; 953 }; 954 955 struct mlx5_devx_event_table { 956 struct mlx5_nb devx_nb; 957 /* serialize updating the event_xa */ 958 struct mutex event_xa_lock; 959 struct xarray event_xa; 960 }; 961 962 struct mlx5_ib_dev { 963 struct ib_device ib_dev; 964 struct mlx5_core_dev *mdev; 965 struct notifier_block mdev_events; 966 int num_ports; 967 /* serialize update of capability mask 968 */ 969 struct mutex cap_mask_mutex; 970 u8 ib_active:1; 971 u8 fill_delay:1; 972 u8 is_rep:1; 973 u8 lag_active:1; 974 u8 wc_support:1; 975 struct umr_common umrc; 976 /* sync used page count stats 977 */ 978 struct mlx5_ib_resources devr; 979 struct mlx5_mr_cache cache; 980 struct timer_list delay_timer; 981 /* Prevents soft lock on massive reg MRs */ 982 struct mutex slow_path_mutex; 983 struct ib_odp_caps odp_caps; 984 u64 odp_max_size; 985 struct mlx5_ib_pf_eq odp_pf_eq; 986 987 /* 988 * Sleepable RCU that prevents destruction of MRs while they are still 989 * being used by a page fault handler. 990 */ 991 struct srcu_struct odp_srcu; 992 struct xarray odp_mkeys; 993 994 u32 null_mkey; 995 struct mlx5_ib_flow_db *flow_db; 996 /* protect resources needed as part of reset flow */ 997 spinlock_t reset_flow_resource_lock; 998 struct list_head qp_list; 999 /* Array with num_ports elements */ 1000 struct mlx5_ib_port *port; 1001 struct mlx5_sq_bfreg bfreg; 1002 struct mlx5_sq_bfreg wc_bfreg; 1003 struct mlx5_sq_bfreg fp_bfreg; 1004 struct mlx5_ib_delay_drop delay_drop; 1005 const struct mlx5_ib_profile *profile; 1006 1007 struct mlx5_ib_lb_state lb; 1008 u8 umr_fence; 1009 struct list_head ib_dev_list; 1010 u64 sys_image_guid; 1011 struct mlx5_dm dm; 1012 u16 devx_whitelist_uid; 1013 struct mlx5_srq_table srq_table; 1014 struct mlx5_async_ctx async_ctx; 1015 struct mlx5_devx_event_table devx_event_table; 1016 1017 struct xarray sig_mrs; 1018 }; 1019 1020 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1021 { 1022 return container_of(mcq, struct mlx5_ib_cq, mcq); 1023 } 1024 1025 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1026 { 1027 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1028 } 1029 1030 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1031 { 1032 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1033 } 1034 1035 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1036 { 1037 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1038 udata, struct mlx5_ib_ucontext, ibucontext); 1039 1040 return to_mdev(context->ibucontext.device); 1041 } 1042 1043 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1044 { 1045 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1046 } 1047 1048 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1049 { 1050 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1051 } 1052 1053 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1054 { 1055 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1056 } 1057 1058 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) 1059 { 1060 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 1061 } 1062 1063 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1064 { 1065 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1066 } 1067 1068 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1069 { 1070 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1071 } 1072 1073 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1074 { 1075 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1076 } 1077 1078 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1079 { 1080 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1081 } 1082 1083 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1084 { 1085 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1086 } 1087 1088 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1089 { 1090 return container_of(msrq, struct mlx5_ib_srq, msrq); 1091 } 1092 1093 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 1094 { 1095 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 1096 } 1097 1098 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1099 { 1100 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1101 } 1102 1103 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1104 { 1105 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1106 } 1107 1108 static inline struct mlx5_ib_flow_action * 1109 to_mflow_act(struct ib_flow_action *ibact) 1110 { 1111 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1112 } 1113 1114 static inline struct mlx5_user_mmap_entry * 1115 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1116 { 1117 return container_of(rdma_entry, 1118 struct mlx5_user_mmap_entry, rdma_entry); 1119 } 1120 1121 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, 1122 struct ib_udata *udata, unsigned long virt, 1123 struct mlx5_db *db); 1124 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1125 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1126 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1127 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1128 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, u32 flags, 1129 struct ib_udata *udata); 1130 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1131 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags); 1132 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1133 struct ib_udata *udata); 1134 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1135 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1136 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1137 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1138 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1139 const struct ib_recv_wr **bad_wr); 1140 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1141 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1142 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1143 struct ib_qp_init_attr *init_attr, 1144 struct ib_udata *udata); 1145 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1146 int attr_mask, struct ib_udata *udata); 1147 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1148 struct ib_qp_init_attr *qp_init_attr); 1149 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1150 void mlx5_ib_drain_sq(struct ib_qp *qp); 1151 void mlx5_ib_drain_rq(struct ib_qp *qp); 1152 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 1153 const struct ib_send_wr **bad_wr); 1154 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 1155 const struct ib_recv_wr **bad_wr); 1156 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1157 int buflen, size_t *bc); 1158 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1159 int buflen, size_t *bc); 1160 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, 1161 void *buffer, int buflen, size_t *bc); 1162 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1163 struct ib_udata *udata); 1164 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1165 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1166 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1167 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1168 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1169 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1170 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1171 u64 virt_addr, int access_flags, 1172 struct ib_udata *udata); 1173 int mlx5_ib_advise_mr(struct ib_pd *pd, 1174 enum ib_uverbs_advise_mr_advice advice, 1175 u32 flags, 1176 struct ib_sge *sg_list, 1177 u32 num_sge, 1178 struct uverbs_attr_bundle *attrs); 1179 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1180 struct ib_udata *udata); 1181 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1182 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1183 int page_shift, int flags); 1184 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1185 struct ib_udata *udata, 1186 int access_flags); 1187 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1188 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr); 1189 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1190 u64 length, u64 virt_addr, int access_flags, 1191 struct ib_pd *pd, struct ib_udata *udata); 1192 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1193 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1194 u32 max_num_sg, struct ib_udata *udata); 1195 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1196 u32 max_num_sg, 1197 u32 max_num_meta_sg); 1198 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1199 unsigned int *sg_offset); 1200 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1201 int data_sg_nents, unsigned int *data_sg_offset, 1202 struct scatterlist *meta_sg, int meta_sg_nents, 1203 unsigned int *meta_sg_offset); 1204 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1205 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1206 const struct ib_mad *in, struct ib_mad *out, 1207 size_t *out_mad_size, u16 *out_mad_pkey_index); 1208 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 1209 struct ib_udata *udata); 1210 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1211 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1212 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1213 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1214 struct ib_smp *out_mad); 1215 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1216 __be64 *sys_image_guid); 1217 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1218 u16 *max_pkeys); 1219 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1220 u32 *vendor_id); 1221 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1222 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1223 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1224 u16 *pkey); 1225 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1226 union ib_gid *gid); 1227 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1228 struct ib_port_attr *props); 1229 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1230 struct ib_port_attr *props); 1231 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 1232 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 1233 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1234 unsigned long max_page_shift, 1235 int *count, int *shift, 1236 int *ncont, int *order); 1237 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1238 int page_shift, size_t offset, size_t num_pages, 1239 __be64 *pas, int access_flags); 1240 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1241 int page_shift, __be64 *pas, int access_flags); 1242 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1243 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1244 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1245 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1246 1247 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); 1248 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1249 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr); 1250 1251 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1252 struct ib_mr_status *mr_status); 1253 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1254 struct ib_wq_init_attr *init_attr, 1255 struct ib_udata *udata); 1256 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1257 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1258 u32 wq_attr_mask, struct ib_udata *udata); 1259 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1260 struct ib_rwq_ind_table_init_attr *init_attr, 1261 struct ib_udata *udata); 1262 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1263 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1264 struct ib_ucontext *context, 1265 struct ib_dm_alloc_attr *attr, 1266 struct uverbs_attr_bundle *attrs); 1267 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs); 1268 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1269 struct ib_dm_mr_attr *attr, 1270 struct uverbs_attr_bundle *attrs); 1271 1272 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1273 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1274 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1275 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1276 int __init mlx5_ib_odp_init(void); 1277 void mlx5_ib_odp_cleanup(void); 1278 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1279 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1280 size_t nentries, struct mlx5_ib_mr *mr, int flags); 1281 1282 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1283 enum ib_uverbs_advise_mr_advice advice, 1284 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1285 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1286 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1287 { 1288 return; 1289 } 1290 1291 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1292 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1293 static inline int mlx5_ib_odp_init(void) { return 0; } 1294 static inline void mlx5_ib_odp_cleanup(void) {} 1295 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1296 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, 1297 size_t nentries, struct mlx5_ib_mr *mr, 1298 int flags) {} 1299 1300 static inline int 1301 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1302 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1303 struct ib_sge *sg_list, u32 num_sge) 1304 { 1305 return -EOPNOTSUPP; 1306 } 1307 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1308 1309 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1310 1311 /* Needed for rep profile */ 1312 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1313 const struct mlx5_ib_profile *profile, 1314 int stage); 1315 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1316 const struct mlx5_ib_profile *profile); 1317 1318 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1319 u8 port, struct ifla_vf_info *info); 1320 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1321 u8 port, int state); 1322 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1323 u8 port, struct ifla_vf_stats *stats); 1324 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u8 port, 1325 struct ifla_vf_guid *node_guid, 1326 struct ifla_vf_guid *port_guid); 1327 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1328 u64 guid, int type); 1329 1330 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, 1331 const struct ib_gid_attr *attr); 1332 1333 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1334 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1335 1336 /* GSI QP helper functions */ 1337 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1338 struct ib_qp_init_attr *init_attr); 1339 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1340 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1341 int attr_mask); 1342 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1343 int qp_attr_mask, 1344 struct ib_qp_init_attr *qp_init_attr); 1345 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1346 const struct ib_send_wr **bad_wr); 1347 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1348 const struct ib_recv_wr **bad_wr); 1349 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1350 1351 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1352 1353 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1354 int bfregn); 1355 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1356 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1357 u8 ib_port_num, 1358 u8 *native_port_num); 1359 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1360 u8 port_num); 1361 int mlx5_ib_fill_res_entry(struct sk_buff *msg, 1362 struct rdma_restrack_entry *res); 1363 int mlx5_ib_fill_stat_entry(struct sk_buff *msg, 1364 struct rdma_restrack_entry *res); 1365 1366 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) 1367 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user); 1368 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid); 1369 void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev); 1370 void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev); 1371 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void); 1372 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1373 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1374 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add( 1375 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher, 1376 struct mlx5_flow_context *flow_context, 1377 struct mlx5_flow_act *flow_act, u32 counter_id, 1378 void *cmd_in, int inlen, int dest_id, int dest_type); 1379 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type); 1380 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 offset, u32 *counter_id); 1381 int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root); 1382 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction); 1383 #else 1384 static inline int 1385 mlx5_ib_devx_create(struct mlx5_ib_dev *dev, 1386 bool is_user) { return -EOPNOTSUPP; } 1387 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {} 1388 static inline void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) {} 1389 static inline void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) {} 1390 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, 1391 int *dest_type) 1392 { 1393 return false; 1394 } 1395 static inline void 1396 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction) 1397 { 1398 return; 1399 }; 1400 #endif 1401 static inline void init_query_mad(struct ib_smp *mad) 1402 { 1403 mad->base_version = 1; 1404 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1405 mad->class_version = 1; 1406 mad->method = IB_MGMT_METHOD_GET; 1407 } 1408 1409 static inline u8 convert_access(int acc) 1410 { 1411 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1412 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1413 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1414 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1415 MLX5_PERM_LOCAL_READ; 1416 } 1417 1418 static inline int is_qp1(enum ib_qp_type qp_type) 1419 { 1420 return qp_type == MLX5_IB_QPT_HW_GSI; 1421 } 1422 1423 #define MLX5_MAX_UMR_SHIFT 16 1424 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1425 1426 static inline u32 check_cq_create_flags(u32 flags) 1427 { 1428 /* 1429 * It returns non-zero value for unsupported CQ 1430 * create flags, otherwise it returns zero. 1431 */ 1432 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1433 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1434 } 1435 1436 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1437 u32 *user_index) 1438 { 1439 if (cqe_version) { 1440 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1441 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1442 return -EINVAL; 1443 *user_index = cmd_uidx; 1444 } else { 1445 *user_index = MLX5_IB_DEFAULT_UIDX; 1446 } 1447 1448 return 0; 1449 } 1450 1451 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1452 struct mlx5_ib_create_qp *ucmd, 1453 int inlen, 1454 u32 *user_index) 1455 { 1456 u8 cqe_version = ucontext->cqe_version; 1457 1458 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1459 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1460 return 0; 1461 1462 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1463 !!cqe_version)) 1464 return -EINVAL; 1465 1466 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1467 } 1468 1469 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1470 struct mlx5_ib_create_srq *ucmd, 1471 int inlen, 1472 u32 *user_index) 1473 { 1474 u8 cqe_version = ucontext->cqe_version; 1475 1476 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1477 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1478 return 0; 1479 1480 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1481 !!cqe_version)) 1482 return -EINVAL; 1483 1484 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1485 } 1486 1487 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1488 { 1489 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1490 MLX5_UARS_IN_PAGE : 1; 1491 } 1492 1493 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1494 struct mlx5_bfreg_info *bfregi) 1495 { 1496 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1497 } 1498 1499 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1500 void mlx5_ib_put_xlt_emergency_page(void); 1501 1502 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1503 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1504 bool dyn_bfreg); 1505 1506 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter); 1507 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num); 1508 1509 static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev, 1510 bool do_modify_atomic) 1511 { 1512 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1513 return false; 1514 1515 if (do_modify_atomic && 1516 MLX5_CAP_GEN(dev->mdev, atomic) && 1517 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 1518 return false; 1519 1520 return true; 1521 } 1522 1523 int mlx5_ib_enable_driver(struct ib_device *dev); 1524 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1525 #endif /* MLX5_IB_H */ 1526