1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #include <dt-bindings/interconnect/qcom,sm6115.h> 9 #include <linux/device.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 16 #include "icc-rpm.h" 17 18 static const char * const snoc_intf_clocks[] = { 19 "cpu_axi", 20 "ufs_axi", 21 "usb_axi", 22 "ipa", /* Required by qxm_ipa */ 23 }; 24 25 static const char * const cnoc_intf_clocks[] = { 26 "usb_axi", 27 }; 28 29 enum { 30 SM6115_MASTER_AMPSS_M0, 31 SM6115_MASTER_ANOC_SNOC, 32 SM6115_MASTER_BIMC_SNOC, 33 SM6115_MASTER_CAMNOC_HF, 34 SM6115_MASTER_CAMNOC_SF, 35 SM6115_MASTER_CRYPTO_CORE0, 36 SM6115_MASTER_GRAPHICS_3D, 37 SM6115_MASTER_IPA, 38 SM6115_MASTER_MDP_PORT0, 39 SM6115_MASTER_PIMEM, 40 SM6115_MASTER_QDSS_BAM, 41 SM6115_MASTER_QDSS_DAP, 42 SM6115_MASTER_QDSS_ETR, 43 SM6115_MASTER_QPIC, 44 SM6115_MASTER_QUP_0, 45 SM6115_MASTER_QUP_CORE_0, 46 SM6115_MASTER_SDCC_1, 47 SM6115_MASTER_SDCC_2, 48 SM6115_MASTER_SNOC_BIMC_NRT, 49 SM6115_MASTER_SNOC_BIMC_RT, 50 SM6115_MASTER_SNOC_BIMC, 51 SM6115_MASTER_SNOC_CFG, 52 SM6115_MASTER_SNOC_CNOC, 53 SM6115_MASTER_TCU_0, 54 SM6115_MASTER_TIC, 55 SM6115_MASTER_USB3, 56 SM6115_MASTER_VIDEO_P0, 57 SM6115_MASTER_VIDEO_PROC, 58 59 SM6115_SLAVE_AHB2PHY_USB, 60 SM6115_SLAVE_ANOC_SNOC, 61 SM6115_SLAVE_APPSS, 62 SM6115_SLAVE_APSS_THROTTLE_CFG, 63 SM6115_SLAVE_BIMC_CFG, 64 SM6115_SLAVE_BIMC_SNOC, 65 SM6115_SLAVE_BOOT_ROM, 66 SM6115_SLAVE_CAMERA_CFG, 67 SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, 68 SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, 69 SM6115_SLAVE_CLK_CTL, 70 SM6115_SLAVE_CNOC_MSS, 71 SM6115_SLAVE_CRYPTO_0_CFG, 72 SM6115_SLAVE_DCC_CFG, 73 SM6115_SLAVE_DDR_PHY_CFG, 74 SM6115_SLAVE_DDR_SS_CFG, 75 SM6115_SLAVE_DISPLAY_CFG, 76 SM6115_SLAVE_DISPLAY_THROTTLE_CFG, 77 SM6115_SLAVE_EBI_CH0, 78 SM6115_SLAVE_GPU_CFG, 79 SM6115_SLAVE_GPU_THROTTLE_CFG, 80 SM6115_SLAVE_HWKM_CORE, 81 SM6115_SLAVE_IMEM_CFG, 82 SM6115_SLAVE_IPA_CFG, 83 SM6115_SLAVE_LPASS, 84 SM6115_SLAVE_MAPSS, 85 SM6115_SLAVE_MDSP_MPU_CFG, 86 SM6115_SLAVE_MESSAGE_RAM, 87 SM6115_SLAVE_OCIMEM, 88 SM6115_SLAVE_PDM, 89 SM6115_SLAVE_PIMEM_CFG, 90 SM6115_SLAVE_PIMEM, 91 SM6115_SLAVE_PKA_CORE, 92 SM6115_SLAVE_PMIC_ARB, 93 SM6115_SLAVE_QDSS_CFG, 94 SM6115_SLAVE_QDSS_STM, 95 SM6115_SLAVE_QM_CFG, 96 SM6115_SLAVE_QM_MPU_CFG, 97 SM6115_SLAVE_QPIC, 98 SM6115_SLAVE_QUP_0, 99 SM6115_SLAVE_QUP_CORE_0, 100 SM6115_SLAVE_RBCPR_CX_CFG, 101 SM6115_SLAVE_RBCPR_MX_CFG, 102 SM6115_SLAVE_RPM, 103 SM6115_SLAVE_SDCC_1, 104 SM6115_SLAVE_SDCC_2, 105 SM6115_SLAVE_SECURITY, 106 SM6115_SLAVE_SERVICE_CNOC, 107 SM6115_SLAVE_SERVICE_SNOC, 108 SM6115_SLAVE_SNOC_BIMC_NRT, 109 SM6115_SLAVE_SNOC_BIMC_RT, 110 SM6115_SLAVE_SNOC_BIMC, 111 SM6115_SLAVE_SNOC_CFG, 112 SM6115_SLAVE_SNOC_CNOC, 113 SM6115_SLAVE_TCSR, 114 SM6115_SLAVE_TCU, 115 SM6115_SLAVE_TLMM, 116 SM6115_SLAVE_USB3, 117 SM6115_SLAVE_VENUS_CFG, 118 SM6115_SLAVE_VENUS_THROTTLE_CFG, 119 SM6115_SLAVE_VSENSE_CTRL_CFG, 120 }; 121 122 static const u16 slv_ebi_slv_bimc_snoc_links[] = { 123 SM6115_SLAVE_EBI_CH0, 124 SM6115_SLAVE_BIMC_SNOC, 125 }; 126 127 static struct qcom_icc_node apps_proc = { 128 .name = "apps_proc", 129 .id = SM6115_MASTER_AMPSS_M0, 130 .channels = 1, 131 .buswidth = 16, 132 .qos.qos_port = 0, 133 .qos.qos_mode = NOC_QOS_MODE_FIXED, 134 .qos.prio_level = 0, 135 .qos.areq_prio = 0, 136 .mas_rpm_id = 0, 137 .slv_rpm_id = -1, 138 .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), 139 .links = slv_ebi_slv_bimc_snoc_links, 140 }; 141 142 static const u16 link_slv_ebi[] = { 143 SM6115_SLAVE_EBI_CH0, 144 }; 145 146 static struct qcom_icc_node mas_snoc_bimc_rt = { 147 .name = "mas_snoc_bimc_rt", 148 .id = SM6115_MASTER_SNOC_BIMC_RT, 149 .channels = 1, 150 .buswidth = 16, 151 .qos.qos_port = 2, 152 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 153 .qos.areq_prio = 0, 154 .qos.prio_level = 0, 155 .mas_rpm_id = -1, 156 .slv_rpm_id = -1, 157 .num_links = ARRAY_SIZE(link_slv_ebi), 158 .links = link_slv_ebi, 159 }; 160 161 static struct qcom_icc_node mas_snoc_bimc_nrt = { 162 .name = "mas_snoc_bimc_nrt", 163 .id = SM6115_MASTER_SNOC_BIMC_NRT, 164 .channels = 1, 165 .buswidth = 16, 166 .qos.qos_port = 3, 167 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 168 .qos.areq_prio = 0, 169 .qos.prio_level = 0, 170 .mas_rpm_id = -1, 171 .slv_rpm_id = -1, 172 .num_links = ARRAY_SIZE(link_slv_ebi), 173 .links = link_slv_ebi, 174 }; 175 176 static struct qcom_icc_node mas_snoc_bimc = { 177 .name = "mas_snoc_bimc", 178 .id = SM6115_MASTER_SNOC_BIMC, 179 .channels = 1, 180 .buswidth = 16, 181 .qos.qos_port = 6, 182 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 183 .qos.areq_prio = 0, 184 .qos.prio_level = 0, 185 .mas_rpm_id = 3, 186 .slv_rpm_id = -1, 187 .num_links = ARRAY_SIZE(link_slv_ebi), 188 .links = link_slv_ebi, 189 }; 190 191 static struct qcom_icc_node qnm_gpu = { 192 .name = "qnm_gpu", 193 .id = SM6115_MASTER_GRAPHICS_3D, 194 .channels = 1, 195 .buswidth = 32, 196 .qos.qos_port = 1, 197 .qos.qos_mode = NOC_QOS_MODE_FIXED, 198 .qos.prio_level = 0, 199 .qos.areq_prio = 0, 200 .mas_rpm_id = -1, 201 .slv_rpm_id = -1, 202 .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), 203 .links = slv_ebi_slv_bimc_snoc_links, 204 }; 205 206 static struct qcom_icc_node tcu_0 = { 207 .name = "tcu_0", 208 .id = SM6115_MASTER_TCU_0, 209 .channels = 1, 210 .buswidth = 8, 211 .qos.qos_port = 4, 212 .qos.qos_mode = NOC_QOS_MODE_FIXED, 213 .qos.prio_level = 6, 214 .qos.areq_prio = 6, 215 .mas_rpm_id = -1, 216 .slv_rpm_id = -1, 217 .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), 218 .links = slv_ebi_slv_bimc_snoc_links, 219 }; 220 221 static const u16 qup_core_0_links[] = { 222 SM6115_SLAVE_QUP_CORE_0, 223 }; 224 225 static struct qcom_icc_node qup0_core_master = { 226 .name = "qup0_core_master", 227 .id = SM6115_MASTER_QUP_CORE_0, 228 .channels = 1, 229 .buswidth = 4, 230 .mas_rpm_id = 170, 231 .slv_rpm_id = -1, 232 .num_links = ARRAY_SIZE(qup_core_0_links), 233 .links = qup_core_0_links, 234 }; 235 236 static const u16 link_slv_anoc_snoc[] = { 237 SM6115_SLAVE_ANOC_SNOC, 238 }; 239 240 static struct qcom_icc_node crypto_c0 = { 241 .name = "crypto_c0", 242 .id = SM6115_MASTER_CRYPTO_CORE0, 243 .channels = 1, 244 .buswidth = 8, 245 .qos.qos_port = 43, 246 .qos.qos_mode = NOC_QOS_MODE_FIXED, 247 .qos.areq_prio = 2, 248 .mas_rpm_id = 23, 249 .slv_rpm_id = -1, 250 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 251 .links = link_slv_anoc_snoc, 252 }; 253 254 static const u16 mas_snoc_cnoc_links[] = { 255 SM6115_SLAVE_AHB2PHY_USB, 256 SM6115_SLAVE_APSS_THROTTLE_CFG, 257 SM6115_SLAVE_BIMC_CFG, 258 SM6115_SLAVE_BOOT_ROM, 259 SM6115_SLAVE_CAMERA_CFG, 260 SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, 261 SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, 262 SM6115_SLAVE_CLK_CTL, 263 SM6115_SLAVE_CNOC_MSS, 264 SM6115_SLAVE_CRYPTO_0_CFG, 265 SM6115_SLAVE_DCC_CFG, 266 SM6115_SLAVE_DDR_PHY_CFG, 267 SM6115_SLAVE_DDR_SS_CFG, 268 SM6115_SLAVE_DISPLAY_CFG, 269 SM6115_SLAVE_DISPLAY_THROTTLE_CFG, 270 SM6115_SLAVE_GPU_CFG, 271 SM6115_SLAVE_GPU_THROTTLE_CFG, 272 SM6115_SLAVE_HWKM_CORE, 273 SM6115_SLAVE_IMEM_CFG, 274 SM6115_SLAVE_IPA_CFG, 275 SM6115_SLAVE_LPASS, 276 SM6115_SLAVE_MAPSS, 277 SM6115_SLAVE_MDSP_MPU_CFG, 278 SM6115_SLAVE_MESSAGE_RAM, 279 SM6115_SLAVE_PDM, 280 SM6115_SLAVE_PIMEM_CFG, 281 SM6115_SLAVE_PKA_CORE, 282 SM6115_SLAVE_PMIC_ARB, 283 SM6115_SLAVE_QDSS_CFG, 284 SM6115_SLAVE_QM_CFG, 285 SM6115_SLAVE_QM_MPU_CFG, 286 SM6115_SLAVE_QPIC, 287 SM6115_SLAVE_QUP_0, 288 SM6115_SLAVE_RBCPR_CX_CFG, 289 SM6115_SLAVE_RBCPR_MX_CFG, 290 SM6115_SLAVE_RPM, 291 SM6115_SLAVE_SDCC_1, 292 SM6115_SLAVE_SDCC_2, 293 SM6115_SLAVE_SECURITY, 294 SM6115_SLAVE_SERVICE_CNOC, 295 SM6115_SLAVE_SNOC_CFG, 296 SM6115_SLAVE_TCSR, 297 SM6115_SLAVE_TLMM, 298 SM6115_SLAVE_USB3, 299 SM6115_SLAVE_VENUS_CFG, 300 SM6115_SLAVE_VENUS_THROTTLE_CFG, 301 SM6115_SLAVE_VSENSE_CTRL_CFG, 302 }; 303 304 static struct qcom_icc_node mas_snoc_cnoc = { 305 .name = "mas_snoc_cnoc", 306 .id = SM6115_MASTER_SNOC_CNOC, 307 .channels = 1, 308 .buswidth = 8, 309 .mas_rpm_id = -1, 310 .slv_rpm_id = -1, 311 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 312 .links = mas_snoc_cnoc_links, 313 }; 314 315 static struct qcom_icc_node xm_dap = { 316 .name = "xm_dap", 317 .id = SM6115_MASTER_QDSS_DAP, 318 .channels = 1, 319 .buswidth = 8, 320 .mas_rpm_id = -1, 321 .slv_rpm_id = -1, 322 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 323 .links = mas_snoc_cnoc_links, 324 }; 325 326 static const u16 link_slv_snoc_bimc_nrt[] = { 327 SM6115_SLAVE_SNOC_BIMC_NRT, 328 }; 329 330 static struct qcom_icc_node qnm_camera_nrt = { 331 .name = "qnm_camera_nrt", 332 .id = SM6115_MASTER_CAMNOC_SF, 333 .channels = 1, 334 .buswidth = 32, 335 .qos.qos_port = 25, 336 .qos.qos_mode = NOC_QOS_MODE_FIXED, 337 .qos.areq_prio = 3, 338 .mas_rpm_id = -1, 339 .slv_rpm_id = -1, 340 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), 341 .links = link_slv_snoc_bimc_nrt, 342 }; 343 344 static struct qcom_icc_node qxm_venus0 = { 345 .name = "qxm_venus0", 346 .id = SM6115_MASTER_VIDEO_P0, 347 .channels = 1, 348 .buswidth = 16, 349 .qos.qos_port = 30, 350 .qos.qos_mode = NOC_QOS_MODE_FIXED, 351 .qos.areq_prio = 3, 352 .qos.urg_fwd_en = true, 353 .mas_rpm_id = -1, 354 .slv_rpm_id = -1, 355 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), 356 .links = link_slv_snoc_bimc_nrt, 357 }; 358 359 static struct qcom_icc_node qxm_venus_cpu = { 360 .name = "qxm_venus_cpu", 361 .id = SM6115_MASTER_VIDEO_PROC, 362 .channels = 1, 363 .buswidth = 8, 364 .qos.qos_port = 34, 365 .qos.qos_mode = NOC_QOS_MODE_FIXED, 366 .qos.areq_prio = 4, 367 .mas_rpm_id = -1, 368 .slv_rpm_id = -1, 369 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), 370 .links = link_slv_snoc_bimc_nrt, 371 }; 372 373 static const u16 link_slv_snoc_bimc_rt[] = { 374 SM6115_SLAVE_SNOC_BIMC_RT, 375 }; 376 377 static struct qcom_icc_node qnm_camera_rt = { 378 .name = "qnm_camera_rt", 379 .id = SM6115_MASTER_CAMNOC_HF, 380 .channels = 1, 381 .buswidth = 32, 382 .qos.qos_port = 31, 383 .qos.qos_mode = NOC_QOS_MODE_FIXED, 384 .qos.areq_prio = 3, 385 .qos.urg_fwd_en = true, 386 .mas_rpm_id = -1, 387 .slv_rpm_id = -1, 388 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt), 389 .links = link_slv_snoc_bimc_rt, 390 }; 391 392 static struct qcom_icc_node qxm_mdp0 = { 393 .name = "qxm_mdp0", 394 .id = SM6115_MASTER_MDP_PORT0, 395 .channels = 1, 396 .buswidth = 16, 397 .qos.qos_port = 26, 398 .qos.qos_mode = NOC_QOS_MODE_FIXED, 399 .qos.areq_prio = 3, 400 .qos.urg_fwd_en = true, 401 .mas_rpm_id = -1, 402 .slv_rpm_id = -1, 403 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt), 404 .links = link_slv_snoc_bimc_rt, 405 }; 406 407 static const u16 slv_service_snoc_links[] = { 408 SM6115_SLAVE_SERVICE_SNOC, 409 }; 410 411 static struct qcom_icc_node qhm_snoc_cfg = { 412 .name = "qhm_snoc_cfg", 413 .id = SM6115_MASTER_SNOC_CFG, 414 .channels = 1, 415 .buswidth = 4, 416 .mas_rpm_id = -1, 417 .slv_rpm_id = -1, 418 .num_links = ARRAY_SIZE(slv_service_snoc_links), 419 .links = slv_service_snoc_links, 420 }; 421 422 static const u16 mas_tic_links[] = { 423 SM6115_SLAVE_APPSS, 424 SM6115_SLAVE_OCIMEM, 425 SM6115_SLAVE_PIMEM, 426 SM6115_SLAVE_QDSS_STM, 427 SM6115_SLAVE_TCU, 428 SM6115_SLAVE_SNOC_BIMC, 429 SM6115_SLAVE_SNOC_CNOC, 430 }; 431 432 static struct qcom_icc_node qhm_tic = { 433 .name = "qhm_tic", 434 .id = SM6115_MASTER_TIC, 435 .channels = 1, 436 .buswidth = 4, 437 .qos.qos_port = 29, 438 .qos.qos_mode = NOC_QOS_MODE_FIXED, 439 .qos.areq_prio = 2, 440 .mas_rpm_id = -1, 441 .slv_rpm_id = -1, 442 .num_links = ARRAY_SIZE(mas_tic_links), 443 .links = mas_tic_links, 444 }; 445 446 static struct qcom_icc_node mas_anoc_snoc = { 447 .name = "mas_anoc_snoc", 448 .id = SM6115_MASTER_ANOC_SNOC, 449 .channels = 1, 450 .buswidth = 16, 451 .mas_rpm_id = -1, 452 .slv_rpm_id = -1, 453 .num_links = ARRAY_SIZE(mas_tic_links), 454 .links = mas_tic_links, 455 }; 456 457 static const u16 mas_bimc_snoc_links[] = { 458 SM6115_SLAVE_APPSS, 459 SM6115_SLAVE_SNOC_CNOC, 460 SM6115_SLAVE_OCIMEM, 461 SM6115_SLAVE_PIMEM, 462 SM6115_SLAVE_QDSS_STM, 463 SM6115_SLAVE_TCU, 464 }; 465 466 static struct qcom_icc_node mas_bimc_snoc = { 467 .name = "mas_bimc_snoc", 468 .id = SM6115_MASTER_BIMC_SNOC, 469 .channels = 1, 470 .buswidth = 8, 471 .mas_rpm_id = 21, 472 .slv_rpm_id = -1, 473 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 474 .links = mas_bimc_snoc_links, 475 }; 476 477 static const u16 mas_pimem_links[] = { 478 SM6115_SLAVE_OCIMEM, 479 SM6115_SLAVE_SNOC_BIMC, 480 }; 481 482 static struct qcom_icc_node qxm_pimem = { 483 .name = "qxm_pimem", 484 .id = SM6115_MASTER_PIMEM, 485 .channels = 1, 486 .buswidth = 8, 487 .qos.qos_port = 41, 488 .qos.qos_mode = NOC_QOS_MODE_FIXED, 489 .qos.areq_prio = 2, 490 .mas_rpm_id = -1, 491 .slv_rpm_id = -1, 492 .num_links = ARRAY_SIZE(mas_pimem_links), 493 .links = mas_pimem_links, 494 }; 495 496 static struct qcom_icc_node qhm_qdss_bam = { 497 .name = "qhm_qdss_bam", 498 .id = SM6115_MASTER_QDSS_BAM, 499 .channels = 1, 500 .buswidth = 4, 501 .qos.qos_port = 23, 502 .qos.qos_mode = NOC_QOS_MODE_FIXED, 503 .qos.areq_prio = 2, 504 .mas_rpm_id = -1, 505 .slv_rpm_id = -1, 506 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 507 .links = link_slv_anoc_snoc, 508 }; 509 510 static struct qcom_icc_node qhm_qpic = { 511 .name = "qhm_qpic", 512 .id = SM6115_MASTER_QPIC, 513 .channels = 1, 514 .buswidth = 4, 515 .mas_rpm_id = -1, 516 .slv_rpm_id = -1, 517 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 518 .links = link_slv_anoc_snoc, 519 }; 520 521 static struct qcom_icc_node qhm_qup0 = { 522 .name = "qhm_qup0", 523 .id = SM6115_MASTER_QUP_0, 524 .channels = 1, 525 .buswidth = 4, 526 .qos.qos_port = 21, 527 .qos.qos_mode = NOC_QOS_MODE_FIXED, 528 .qos.areq_prio = 2, 529 .mas_rpm_id = 166, 530 .slv_rpm_id = -1, 531 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 532 .links = link_slv_anoc_snoc, 533 }; 534 535 static struct qcom_icc_node qxm_ipa = { 536 .name = "qxm_ipa", 537 .id = SM6115_MASTER_IPA, 538 .channels = 1, 539 .buswidth = 8, 540 .qos.qos_port = 24, 541 .qos.qos_mode = NOC_QOS_MODE_FIXED, 542 .qos.areq_prio = 2, 543 .mas_rpm_id = 59, 544 .slv_rpm_id = -1, 545 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 546 .links = link_slv_anoc_snoc, 547 }; 548 549 static struct qcom_icc_node xm_qdss_etr = { 550 .name = "xm_qdss_etr", 551 .id = SM6115_MASTER_QDSS_ETR, 552 .channels = 1, 553 .buswidth = 8, 554 .qos.qos_port = 33, 555 .qos.qos_mode = NOC_QOS_MODE_FIXED, 556 .qos.areq_prio = 2, 557 .mas_rpm_id = -1, 558 .slv_rpm_id = -1, 559 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 560 .links = link_slv_anoc_snoc, 561 }; 562 563 static struct qcom_icc_node xm_sdc1 = { 564 .name = "xm_sdc1", 565 .id = SM6115_MASTER_SDCC_1, 566 .channels = 1, 567 .buswidth = 8, 568 .qos.qos_port = 38, 569 .qos.qos_mode = NOC_QOS_MODE_FIXED, 570 .qos.areq_prio = 2, 571 .mas_rpm_id = 33, 572 .slv_rpm_id = -1, 573 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 574 .links = link_slv_anoc_snoc, 575 }; 576 577 static struct qcom_icc_node xm_sdc2 = { 578 .name = "xm_sdc2", 579 .id = SM6115_MASTER_SDCC_2, 580 .channels = 1, 581 .buswidth = 8, 582 .qos.qos_port = 44, 583 .qos.qos_mode = NOC_QOS_MODE_FIXED, 584 .qos.areq_prio = 2, 585 .mas_rpm_id = 35, 586 .slv_rpm_id = -1, 587 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 588 .links = link_slv_anoc_snoc, 589 }; 590 591 static struct qcom_icc_node xm_usb3_0 = { 592 .name = "xm_usb3_0", 593 .id = SM6115_MASTER_USB3, 594 .channels = 1, 595 .buswidth = 8, 596 .qos.qos_port = 45, 597 .qos.qos_mode = NOC_QOS_MODE_FIXED, 598 .qos.areq_prio = 2, 599 .mas_rpm_id = -1, 600 .slv_rpm_id = -1, 601 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 602 .links = link_slv_anoc_snoc, 603 }; 604 605 static struct qcom_icc_node ebi = { 606 .name = "ebi", 607 .id = SM6115_SLAVE_EBI_CH0, 608 .channels = 2, 609 .buswidth = 4, 610 .mas_rpm_id = -1, 611 .slv_rpm_id = 0, 612 }; 613 614 static const u16 slv_bimc_snoc_links[] = { 615 SM6115_MASTER_BIMC_SNOC, 616 }; 617 618 static struct qcom_icc_node slv_bimc_snoc = { 619 .name = "slv_bimc_snoc", 620 .id = SM6115_SLAVE_BIMC_SNOC, 621 .channels = 1, 622 .buswidth = 16, 623 .mas_rpm_id = -1, 624 .slv_rpm_id = 2, 625 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 626 .links = slv_bimc_snoc_links, 627 }; 628 629 static struct qcom_icc_node qup0_core_slave = { 630 .name = "qup0_core_slave", 631 .id = SM6115_SLAVE_QUP_CORE_0, 632 .channels = 1, 633 .buswidth = 4, 634 .mas_rpm_id = -1, 635 .slv_rpm_id = -1, 636 }; 637 638 static struct qcom_icc_node qhs_ahb2phy_usb = { 639 .name = "qhs_ahb2phy_usb", 640 .id = SM6115_SLAVE_AHB2PHY_USB, 641 .channels = 1, 642 .buswidth = 4, 643 .mas_rpm_id = -1, 644 .slv_rpm_id = -1, 645 }; 646 647 static struct qcom_icc_node qhs_apss_throttle_cfg = { 648 .name = "qhs_apss_throttle_cfg", 649 .id = SM6115_SLAVE_APSS_THROTTLE_CFG, 650 .channels = 1, 651 .buswidth = 4, 652 .mas_rpm_id = -1, 653 .slv_rpm_id = -1, 654 }; 655 656 static struct qcom_icc_node qhs_bimc_cfg = { 657 .name = "qhs_bimc_cfg", 658 .id = SM6115_SLAVE_BIMC_CFG, 659 .channels = 1, 660 .buswidth = 4, 661 .mas_rpm_id = -1, 662 .slv_rpm_id = -1, 663 }; 664 665 static struct qcom_icc_node qhs_boot_rom = { 666 .name = "qhs_boot_rom", 667 .id = SM6115_SLAVE_BOOT_ROM, 668 .channels = 1, 669 .buswidth = 4, 670 .mas_rpm_id = -1, 671 .slv_rpm_id = -1, 672 }; 673 674 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { 675 .name = "qhs_camera_nrt_throttle_cfg", 676 .id = SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, 677 .channels = 1, 678 .buswidth = 4, 679 .mas_rpm_id = -1, 680 .slv_rpm_id = -1, 681 }; 682 683 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 684 .name = "qhs_camera_rt_throttle_cfg", 685 .id = SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, 686 .channels = 1, 687 .buswidth = 4, 688 .mas_rpm_id = -1, 689 .slv_rpm_id = -1, 690 }; 691 692 static struct qcom_icc_node qhs_camera_ss_cfg = { 693 .name = "qhs_camera_ss_cfg", 694 .id = SM6115_SLAVE_CAMERA_CFG, 695 .channels = 1, 696 .buswidth = 4, 697 .mas_rpm_id = -1, 698 .slv_rpm_id = -1, 699 }; 700 701 static struct qcom_icc_node qhs_clk_ctl = { 702 .name = "qhs_clk_ctl", 703 .id = SM6115_SLAVE_CLK_CTL, 704 .channels = 1, 705 .buswidth = 4, 706 .mas_rpm_id = -1, 707 .slv_rpm_id = -1, 708 }; 709 710 static struct qcom_icc_node qhs_cpr_cx = { 711 .name = "qhs_cpr_cx", 712 .id = SM6115_SLAVE_RBCPR_CX_CFG, 713 .channels = 1, 714 .buswidth = 4, 715 .mas_rpm_id = -1, 716 .slv_rpm_id = -1, 717 }; 718 719 static struct qcom_icc_node qhs_cpr_mx = { 720 .name = "qhs_cpr_mx", 721 .id = SM6115_SLAVE_RBCPR_MX_CFG, 722 .channels = 1, 723 .buswidth = 4, 724 .mas_rpm_id = -1, 725 .slv_rpm_id = -1, 726 }; 727 728 static struct qcom_icc_node qhs_crypto0_cfg = { 729 .name = "qhs_crypto0_cfg", 730 .id = SM6115_SLAVE_CRYPTO_0_CFG, 731 .channels = 1, 732 .buswidth = 4, 733 .mas_rpm_id = -1, 734 .slv_rpm_id = -1, 735 }; 736 737 static struct qcom_icc_node qhs_dcc_cfg = { 738 .name = "qhs_dcc_cfg", 739 .id = SM6115_SLAVE_DCC_CFG, 740 .channels = 1, 741 .buswidth = 4, 742 .mas_rpm_id = -1, 743 .slv_rpm_id = -1, 744 }; 745 746 static struct qcom_icc_node qhs_ddr_phy_cfg = { 747 .name = "qhs_ddr_phy_cfg", 748 .id = SM6115_SLAVE_DDR_PHY_CFG, 749 .channels = 1, 750 .buswidth = 4, 751 .mas_rpm_id = -1, 752 .slv_rpm_id = -1, 753 }; 754 755 static struct qcom_icc_node qhs_ddr_ss_cfg = { 756 .name = "qhs_ddr_ss_cfg", 757 .id = SM6115_SLAVE_DDR_SS_CFG, 758 .channels = 1, 759 .buswidth = 4, 760 .mas_rpm_id = -1, 761 .slv_rpm_id = -1, 762 }; 763 764 static struct qcom_icc_node qhs_disp_ss_cfg = { 765 .name = "qhs_disp_ss_cfg", 766 .id = SM6115_SLAVE_DISPLAY_CFG, 767 .channels = 1, 768 .buswidth = 4, 769 .mas_rpm_id = -1, 770 .slv_rpm_id = -1, 771 }; 772 773 static struct qcom_icc_node qhs_display_throttle_cfg = { 774 .name = "qhs_display_throttle_cfg", 775 .id = SM6115_SLAVE_DISPLAY_THROTTLE_CFG, 776 .channels = 1, 777 .buswidth = 4, 778 .mas_rpm_id = -1, 779 .slv_rpm_id = -1, 780 }; 781 782 static struct qcom_icc_node qhs_gpu_cfg = { 783 .name = "qhs_gpu_cfg", 784 .id = SM6115_SLAVE_GPU_CFG, 785 .channels = 1, 786 .buswidth = 8, 787 .mas_rpm_id = -1, 788 .slv_rpm_id = -1, 789 }; 790 791 static struct qcom_icc_node qhs_gpu_throttle_cfg = { 792 .name = "qhs_gpu_throttle_cfg", 793 .id = SM6115_SLAVE_GPU_THROTTLE_CFG, 794 .channels = 1, 795 .buswidth = 4, 796 .mas_rpm_id = -1, 797 .slv_rpm_id = -1, 798 }; 799 800 static struct qcom_icc_node qhs_hwkm = { 801 .name = "qhs_hwkm", 802 .id = SM6115_SLAVE_HWKM_CORE, 803 .channels = 1, 804 .buswidth = 4, 805 .mas_rpm_id = -1, 806 .slv_rpm_id = -1, 807 }; 808 809 static struct qcom_icc_node qhs_imem_cfg = { 810 .name = "qhs_imem_cfg", 811 .id = SM6115_SLAVE_IMEM_CFG, 812 .channels = 1, 813 .buswidth = 4, 814 .mas_rpm_id = -1, 815 .slv_rpm_id = -1, 816 }; 817 818 static struct qcom_icc_node qhs_ipa_cfg = { 819 .name = "qhs_ipa_cfg", 820 .id = SM6115_SLAVE_IPA_CFG, 821 .channels = 1, 822 .buswidth = 4, 823 .mas_rpm_id = -1, 824 .slv_rpm_id = -1, 825 }; 826 827 static struct qcom_icc_node qhs_lpass = { 828 .name = "qhs_lpass", 829 .id = SM6115_SLAVE_LPASS, 830 .channels = 1, 831 .buswidth = 4, 832 .mas_rpm_id = -1, 833 .slv_rpm_id = -1, 834 }; 835 836 static struct qcom_icc_node qhs_mapss = { 837 .name = "qhs_mapss", 838 .id = SM6115_SLAVE_MAPSS, 839 .channels = 1, 840 .buswidth = 4, 841 .mas_rpm_id = -1, 842 .slv_rpm_id = -1, 843 }; 844 845 static struct qcom_icc_node qhs_mdsp_mpu_cfg = { 846 .name = "qhs_mdsp_mpu_cfg", 847 .id = SM6115_SLAVE_MDSP_MPU_CFG, 848 .channels = 1, 849 .buswidth = 4, 850 .mas_rpm_id = -1, 851 .slv_rpm_id = -1, 852 }; 853 854 static struct qcom_icc_node qhs_mesg_ram = { 855 .name = "qhs_mesg_ram", 856 .id = SM6115_SLAVE_MESSAGE_RAM, 857 .channels = 1, 858 .buswidth = 4, 859 .mas_rpm_id = -1, 860 .slv_rpm_id = -1, 861 }; 862 863 static struct qcom_icc_node qhs_mss = { 864 .name = "qhs_mss", 865 .id = SM6115_SLAVE_CNOC_MSS, 866 .channels = 1, 867 .buswidth = 4, 868 .mas_rpm_id = -1, 869 .slv_rpm_id = -1, 870 }; 871 872 static struct qcom_icc_node qhs_pdm = { 873 .name = "qhs_pdm", 874 .id = SM6115_SLAVE_PDM, 875 .channels = 1, 876 .buswidth = 4, 877 .mas_rpm_id = -1, 878 .slv_rpm_id = -1, 879 }; 880 881 static struct qcom_icc_node qhs_pimem_cfg = { 882 .name = "qhs_pimem_cfg", 883 .id = SM6115_SLAVE_PIMEM_CFG, 884 .channels = 1, 885 .buswidth = 4, 886 .mas_rpm_id = -1, 887 .slv_rpm_id = -1, 888 }; 889 890 static struct qcom_icc_node qhs_pka_wrapper = { 891 .name = "qhs_pka_wrapper", 892 .id = SM6115_SLAVE_PKA_CORE, 893 .channels = 1, 894 .buswidth = 4, 895 .mas_rpm_id = -1, 896 .slv_rpm_id = -1, 897 }; 898 899 static struct qcom_icc_node qhs_pmic_arb = { 900 .name = "qhs_pmic_arb", 901 .id = SM6115_SLAVE_PMIC_ARB, 902 .channels = 1, 903 .buswidth = 4, 904 .mas_rpm_id = -1, 905 .slv_rpm_id = -1, 906 }; 907 908 static struct qcom_icc_node qhs_qdss_cfg = { 909 .name = "qhs_qdss_cfg", 910 .id = SM6115_SLAVE_QDSS_CFG, 911 .channels = 1, 912 .buswidth = 4, 913 .mas_rpm_id = -1, 914 .slv_rpm_id = -1, 915 }; 916 917 static struct qcom_icc_node qhs_qm_cfg = { 918 .name = "qhs_qm_cfg", 919 .id = SM6115_SLAVE_QM_CFG, 920 .channels = 1, 921 .buswidth = 4, 922 .mas_rpm_id = -1, 923 .slv_rpm_id = -1, 924 }; 925 926 static struct qcom_icc_node qhs_qm_mpu_cfg = { 927 .name = "qhs_qm_mpu_cfg", 928 .id = SM6115_SLAVE_QM_MPU_CFG, 929 .channels = 1, 930 .buswidth = 4, 931 .mas_rpm_id = -1, 932 .slv_rpm_id = -1, 933 }; 934 935 static struct qcom_icc_node qhs_qpic = { 936 .name = "qhs_qpic", 937 .id = SM6115_SLAVE_QPIC, 938 .channels = 1, 939 .buswidth = 4, 940 .mas_rpm_id = -1, 941 .slv_rpm_id = -1, 942 }; 943 944 static struct qcom_icc_node qhs_qup0 = { 945 .name = "qhs_qup0", 946 .id = SM6115_SLAVE_QUP_0, 947 .channels = 1, 948 .buswidth = 4, 949 .mas_rpm_id = -1, 950 .slv_rpm_id = -1, 951 }; 952 953 static struct qcom_icc_node qhs_rpm = { 954 .name = "qhs_rpm", 955 .id = SM6115_SLAVE_RPM, 956 .channels = 1, 957 .buswidth = 4, 958 .mas_rpm_id = -1, 959 .slv_rpm_id = -1, 960 }; 961 962 static struct qcom_icc_node qhs_sdc1 = { 963 .name = "qhs_sdc1", 964 .id = SM6115_SLAVE_SDCC_1, 965 .channels = 1, 966 .buswidth = 4, 967 .mas_rpm_id = -1, 968 .slv_rpm_id = -1, 969 }; 970 971 static struct qcom_icc_node qhs_sdc2 = { 972 .name = "qhs_sdc2", 973 .id = SM6115_SLAVE_SDCC_2, 974 .channels = 1, 975 .buswidth = 4, 976 .mas_rpm_id = -1, 977 .slv_rpm_id = -1, 978 }; 979 980 static struct qcom_icc_node qhs_security = { 981 .name = "qhs_security", 982 .id = SM6115_SLAVE_SECURITY, 983 .channels = 1, 984 .buswidth = 4, 985 .mas_rpm_id = -1, 986 .slv_rpm_id = -1, 987 }; 988 989 static const u16 slv_snoc_cfg_links[] = { 990 SM6115_MASTER_SNOC_CFG, 991 }; 992 993 static struct qcom_icc_node qhs_snoc_cfg = { 994 .name = "qhs_snoc_cfg", 995 .id = SM6115_SLAVE_SNOC_CFG, 996 .channels = 1, 997 .buswidth = 4, 998 .mas_rpm_id = -1, 999 .slv_rpm_id = -1, 1000 .num_links = ARRAY_SIZE(slv_snoc_cfg_links), 1001 .links = slv_snoc_cfg_links, 1002 }; 1003 1004 static struct qcom_icc_node qhs_tcsr = { 1005 .name = "qhs_tcsr", 1006 .id = SM6115_SLAVE_TCSR, 1007 .channels = 1, 1008 .buswidth = 4, 1009 .mas_rpm_id = -1, 1010 .slv_rpm_id = -1, 1011 }; 1012 1013 static struct qcom_icc_node qhs_tlmm = { 1014 .name = "qhs_tlmm", 1015 .id = SM6115_SLAVE_TLMM, 1016 .channels = 1, 1017 .buswidth = 4, 1018 .mas_rpm_id = -1, 1019 .slv_rpm_id = -1, 1020 }; 1021 1022 static struct qcom_icc_node qhs_usb3 = { 1023 .name = "qhs_usb3", 1024 .id = SM6115_SLAVE_USB3, 1025 .channels = 1, 1026 .buswidth = 4, 1027 .mas_rpm_id = -1, 1028 .slv_rpm_id = -1, 1029 }; 1030 1031 static struct qcom_icc_node qhs_venus_cfg = { 1032 .name = "qhs_venus_cfg", 1033 .id = SM6115_SLAVE_VENUS_CFG, 1034 .channels = 1, 1035 .buswidth = 4, 1036 .mas_rpm_id = -1, 1037 .slv_rpm_id = -1, 1038 }; 1039 1040 static struct qcom_icc_node qhs_venus_throttle_cfg = { 1041 .name = "qhs_venus_throttle_cfg", 1042 .id = SM6115_SLAVE_VENUS_THROTTLE_CFG, 1043 .channels = 1, 1044 .buswidth = 4, 1045 .mas_rpm_id = -1, 1046 .slv_rpm_id = -1, 1047 }; 1048 1049 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1050 .name = "qhs_vsense_ctrl_cfg", 1051 .id = SM6115_SLAVE_VSENSE_CTRL_CFG, 1052 .channels = 1, 1053 .buswidth = 4, 1054 .mas_rpm_id = -1, 1055 .slv_rpm_id = -1, 1056 }; 1057 1058 static struct qcom_icc_node srvc_cnoc = { 1059 .name = "srvc_cnoc", 1060 .id = SM6115_SLAVE_SERVICE_CNOC, 1061 .channels = 1, 1062 .buswidth = 4, 1063 .mas_rpm_id = -1, 1064 .slv_rpm_id = -1, 1065 }; 1066 1067 static const u16 slv_snoc_bimc_nrt_links[] = { 1068 SM6115_MASTER_SNOC_BIMC_NRT, 1069 }; 1070 1071 static struct qcom_icc_node slv_snoc_bimc_nrt = { 1072 .name = "slv_snoc_bimc_nrt", 1073 .id = SM6115_SLAVE_SNOC_BIMC_NRT, 1074 .channels = 1, 1075 .buswidth = 16, 1076 .mas_rpm_id = -1, 1077 .slv_rpm_id = -1, 1078 .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links), 1079 .links = slv_snoc_bimc_nrt_links, 1080 }; 1081 1082 static const u16 slv_snoc_bimc_rt_links[] = { 1083 SM6115_MASTER_SNOC_BIMC_RT, 1084 }; 1085 1086 static struct qcom_icc_node slv_snoc_bimc_rt = { 1087 .name = "slv_snoc_bimc_rt", 1088 .id = SM6115_SLAVE_SNOC_BIMC_RT, 1089 .channels = 1, 1090 .buswidth = 16, 1091 .mas_rpm_id = -1, 1092 .slv_rpm_id = -1, 1093 .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links), 1094 .links = slv_snoc_bimc_rt_links, 1095 }; 1096 1097 static struct qcom_icc_node qhs_apss = { 1098 .name = "qhs_apss", 1099 .id = SM6115_SLAVE_APPSS, 1100 .channels = 1, 1101 .buswidth = 8, 1102 .mas_rpm_id = -1, 1103 .slv_rpm_id = -1, 1104 }; 1105 1106 static const u16 slv_snoc_cnoc_links[] = { 1107 SM6115_MASTER_SNOC_CNOC 1108 }; 1109 1110 static struct qcom_icc_node slv_snoc_cnoc = { 1111 .name = "slv_snoc_cnoc", 1112 .id = SM6115_SLAVE_SNOC_CNOC, 1113 .channels = 1, 1114 .buswidth = 8, 1115 .mas_rpm_id = -1, 1116 .slv_rpm_id = 25, 1117 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1118 .links = slv_snoc_cnoc_links, 1119 }; 1120 1121 static struct qcom_icc_node qxs_imem = { 1122 .name = "qxs_imem", 1123 .id = SM6115_SLAVE_OCIMEM, 1124 .channels = 1, 1125 .buswidth = 8, 1126 .mas_rpm_id = -1, 1127 .slv_rpm_id = 26, 1128 }; 1129 1130 static struct qcom_icc_node qxs_pimem = { 1131 .name = "qxs_pimem", 1132 .id = SM6115_SLAVE_PIMEM, 1133 .channels = 1, 1134 .buswidth = 8, 1135 .mas_rpm_id = -1, 1136 .slv_rpm_id = -1, 1137 }; 1138 1139 static const u16 slv_snoc_bimc_links[] = { 1140 SM6115_MASTER_SNOC_BIMC, 1141 }; 1142 1143 static struct qcom_icc_node slv_snoc_bimc = { 1144 .name = "slv_snoc_bimc", 1145 .id = SM6115_SLAVE_SNOC_BIMC, 1146 .channels = 1, 1147 .buswidth = 16, 1148 .mas_rpm_id = -1, 1149 .slv_rpm_id = 24, 1150 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1151 .links = slv_snoc_bimc_links, 1152 }; 1153 1154 static struct qcom_icc_node srvc_snoc = { 1155 .name = "srvc_snoc", 1156 .id = SM6115_SLAVE_SERVICE_SNOC, 1157 .channels = 1, 1158 .buswidth = 4, 1159 .mas_rpm_id = -1, 1160 .slv_rpm_id = -1, 1161 }; 1162 1163 static struct qcom_icc_node xs_qdss_stm = { 1164 .name = "xs_qdss_stm", 1165 .id = SM6115_SLAVE_QDSS_STM, 1166 .channels = 1, 1167 .buswidth = 4, 1168 .mas_rpm_id = -1, 1169 .slv_rpm_id = 30, 1170 }; 1171 1172 static struct qcom_icc_node xs_sys_tcu_cfg = { 1173 .name = "xs_sys_tcu_cfg", 1174 .id = SM6115_SLAVE_TCU, 1175 .channels = 1, 1176 .buswidth = 8, 1177 .mas_rpm_id = -1, 1178 .slv_rpm_id = -1, 1179 }; 1180 1181 static const u16 slv_anoc_snoc_links[] = { 1182 SM6115_MASTER_ANOC_SNOC, 1183 }; 1184 1185 static struct qcom_icc_node slv_anoc_snoc = { 1186 .name = "slv_anoc_snoc", 1187 .id = SM6115_SLAVE_ANOC_SNOC, 1188 .channels = 1, 1189 .buswidth = 16, 1190 .mas_rpm_id = -1, 1191 .slv_rpm_id = -1, 1192 .num_links = ARRAY_SIZE(slv_anoc_snoc_links), 1193 .links = slv_anoc_snoc_links, 1194 }; 1195 1196 static struct qcom_icc_node *bimc_nodes[] = { 1197 [MASTER_AMPSS_M0] = &apps_proc, 1198 [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, 1199 [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, 1200 [SNOC_BIMC_MAS] = &mas_snoc_bimc, 1201 [MASTER_GRAPHICS_3D] = &qnm_gpu, 1202 [MASTER_TCU_0] = &tcu_0, 1203 [SLAVE_EBI_CH0] = &ebi, 1204 [BIMC_SNOC_SLV] = &slv_bimc_snoc, 1205 }; 1206 1207 static const struct regmap_config bimc_regmap_config = { 1208 .reg_bits = 32, 1209 .reg_stride = 4, 1210 .val_bits = 32, 1211 .max_register = 0x80000, 1212 .fast_io = true, 1213 }; 1214 1215 static const struct qcom_icc_desc sm6115_bimc = { 1216 .type = QCOM_ICC_BIMC, 1217 .nodes = bimc_nodes, 1218 .num_nodes = ARRAY_SIZE(bimc_nodes), 1219 .regmap_cfg = &bimc_regmap_config, 1220 .bus_clk_desc = &bimc_clk, 1221 .keep_alive = true, 1222 .qos_offset = 0x8000, 1223 .ab_coeff = 153, 1224 }; 1225 1226 static struct qcom_icc_node *config_noc_nodes[] = { 1227 [SNOC_CNOC_MAS] = &mas_snoc_cnoc, 1228 [MASTER_QDSS_DAP] = &xm_dap, 1229 [SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb, 1230 [SLAVE_APSS_THROTTLE_CFG] = &qhs_apss_throttle_cfg, 1231 [SLAVE_BIMC_CFG] = &qhs_bimc_cfg, 1232 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1233 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, 1234 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 1235 [SLAVE_CAMERA_CFG] = &qhs_camera_ss_cfg, 1236 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1237 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1238 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1239 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1240 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1241 [SLAVE_DDR_PHY_CFG] = &qhs_ddr_phy_cfg, 1242 [SLAVE_DDR_SS_CFG] = &qhs_ddr_ss_cfg, 1243 [SLAVE_DISPLAY_CFG] = &qhs_disp_ss_cfg, 1244 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, 1245 [SLAVE_GPU_CFG] = &qhs_gpu_cfg, 1246 [SLAVE_GPU_THROTTLE_CFG] = &qhs_gpu_throttle_cfg, 1247 [SLAVE_HWKM_CORE] = &qhs_hwkm, 1248 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1249 [SLAVE_IPA_CFG] = &qhs_ipa_cfg, 1250 [SLAVE_LPASS] = &qhs_lpass, 1251 [SLAVE_MAPSS] = &qhs_mapss, 1252 [SLAVE_MDSP_MPU_CFG] = &qhs_mdsp_mpu_cfg, 1253 [SLAVE_MESSAGE_RAM] = &qhs_mesg_ram, 1254 [SLAVE_CNOC_MSS] = &qhs_mss, 1255 [SLAVE_PDM] = &qhs_pdm, 1256 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1257 [SLAVE_PKA_CORE] = &qhs_pka_wrapper, 1258 [SLAVE_PMIC_ARB] = &qhs_pmic_arb, 1259 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1260 [SLAVE_QM_CFG] = &qhs_qm_cfg, 1261 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 1262 [SLAVE_QPIC] = &qhs_qpic, 1263 [SLAVE_QUP_0] = &qhs_qup0, 1264 [SLAVE_RPM] = &qhs_rpm, 1265 [SLAVE_SDCC_1] = &qhs_sdc1, 1266 [SLAVE_SDCC_2] = &qhs_sdc2, 1267 [SLAVE_SECURITY] = &qhs_security, 1268 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1269 [SLAVE_TCSR] = &qhs_tcsr, 1270 [SLAVE_TLMM] = &qhs_tlmm, 1271 [SLAVE_USB3] = &qhs_usb3, 1272 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1273 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1274 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1275 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1276 }; 1277 1278 static const struct regmap_config cnoc_regmap_config = { 1279 .reg_bits = 32, 1280 .reg_stride = 4, 1281 .val_bits = 32, 1282 .max_register = 0x6200, 1283 .fast_io = true, 1284 }; 1285 1286 static const struct qcom_icc_desc sm6115_config_noc = { 1287 .type = QCOM_ICC_QNOC, 1288 .nodes = config_noc_nodes, 1289 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1290 .regmap_cfg = &cnoc_regmap_config, 1291 .intf_clocks = cnoc_intf_clocks, 1292 .num_intf_clocks = ARRAY_SIZE(cnoc_intf_clocks), 1293 .bus_clk_desc = &bus_1_clk, 1294 .keep_alive = true, 1295 }; 1296 1297 static struct qcom_icc_node *sys_noc_nodes[] = { 1298 [MASTER_CRYPTO_CORE0] = &crypto_c0, 1299 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1300 [MASTER_TIC] = &qhm_tic, 1301 [MASTER_ANOC_SNOC] = &mas_anoc_snoc, 1302 [BIMC_SNOC_MAS] = &mas_bimc_snoc, 1303 [MASTER_PIMEM] = &qxm_pimem, 1304 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1305 [MASTER_QPIC] = &qhm_qpic, 1306 [MASTER_QUP_0] = &qhm_qup0, 1307 [MASTER_IPA] = &qxm_ipa, 1308 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1309 [MASTER_SDCC_1] = &xm_sdc1, 1310 [MASTER_SDCC_2] = &xm_sdc2, 1311 [MASTER_USB3] = &xm_usb3_0, 1312 [SLAVE_APPSS] = &qhs_apss, 1313 [SNOC_CNOC_SLV] = &slv_snoc_cnoc, 1314 [SLAVE_OCIMEM] = &qxs_imem, 1315 [SLAVE_PIMEM] = &qxs_pimem, 1316 [SNOC_BIMC_SLV] = &slv_snoc_bimc, 1317 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1318 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1319 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1320 [SLAVE_ANOC_SNOC] = &slv_anoc_snoc, 1321 }; 1322 1323 static const struct regmap_config sys_noc_regmap_config = { 1324 .reg_bits = 32, 1325 .reg_stride = 4, 1326 .val_bits = 32, 1327 .max_register = 0x5f080, 1328 .fast_io = true, 1329 }; 1330 1331 static const struct qcom_icc_desc sm6115_sys_noc = { 1332 .type = QCOM_ICC_QNOC, 1333 .nodes = sys_noc_nodes, 1334 .num_nodes = ARRAY_SIZE(sys_noc_nodes), 1335 .regmap_cfg = &sys_noc_regmap_config, 1336 .intf_clocks = snoc_intf_clocks, 1337 .num_intf_clocks = ARRAY_SIZE(snoc_intf_clocks), 1338 .bus_clk_desc = &bus_2_clk, 1339 .keep_alive = true, 1340 }; 1341 1342 static struct qcom_icc_node *clk_virt_nodes[] = { 1343 [MASTER_QUP_CORE_0] = &qup0_core_master, 1344 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1345 }; 1346 1347 static const struct qcom_icc_desc sm6115_clk_virt = { 1348 .type = QCOM_ICC_QNOC, 1349 .nodes = clk_virt_nodes, 1350 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1351 .regmap_cfg = &sys_noc_regmap_config, 1352 .bus_clk_desc = &qup_clk, 1353 .keep_alive = true, 1354 }; 1355 1356 static struct qcom_icc_node *mmnrt_virt_nodes[] = { 1357 [MASTER_CAMNOC_SF] = &qnm_camera_nrt, 1358 [MASTER_VIDEO_P0] = &qxm_venus0, 1359 [MASTER_VIDEO_PROC] = &qxm_venus_cpu, 1360 [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, 1361 }; 1362 1363 static const struct qcom_icc_desc sm6115_mmnrt_virt = { 1364 .type = QCOM_ICC_QNOC, 1365 .nodes = mmnrt_virt_nodes, 1366 .num_nodes = ARRAY_SIZE(mmnrt_virt_nodes), 1367 .regmap_cfg = &sys_noc_regmap_config, 1368 .bus_clk_desc = &mmaxi_0_clk, 1369 .keep_alive = true, 1370 .ab_coeff = 142, 1371 }; 1372 1373 static struct qcom_icc_node *mmrt_virt_nodes[] = { 1374 [MASTER_CAMNOC_HF] = &qnm_camera_rt, 1375 [MASTER_MDP_PORT0] = &qxm_mdp0, 1376 [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, 1377 }; 1378 1379 static const struct qcom_icc_desc sm6115_mmrt_virt = { 1380 .type = QCOM_ICC_QNOC, 1381 .nodes = mmrt_virt_nodes, 1382 .num_nodes = ARRAY_SIZE(mmrt_virt_nodes), 1383 .regmap_cfg = &sys_noc_regmap_config, 1384 .bus_clk_desc = &mmaxi_1_clk, 1385 .keep_alive = true, 1386 .ab_coeff = 139, 1387 }; 1388 1389 static const struct of_device_id qnoc_of_match[] = { 1390 { .compatible = "qcom,sm6115-bimc", .data = &sm6115_bimc }, 1391 { .compatible = "qcom,sm6115-clk-virt", .data = &sm6115_clk_virt }, 1392 { .compatible = "qcom,sm6115-cnoc", .data = &sm6115_config_noc }, 1393 { .compatible = "qcom,sm6115-mmrt-virt", .data = &sm6115_mmrt_virt }, 1394 { .compatible = "qcom,sm6115-mmnrt-virt", .data = &sm6115_mmnrt_virt }, 1395 { .compatible = "qcom,sm6115-snoc", .data = &sm6115_sys_noc }, 1396 { } 1397 }; 1398 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1399 1400 static struct platform_driver qnoc_driver = { 1401 .probe = qnoc_probe, 1402 .remove_new = qnoc_remove, 1403 .driver = { 1404 .name = "qnoc-sm6115", 1405 .of_match_table = qnoc_of_match, 1406 .sync_state = icc_sync_state, 1407 }, 1408 }; 1409 1410 static int __init qnoc_driver_init(void) 1411 { 1412 return platform_driver_register(&qnoc_driver); 1413 } 1414 core_initcall(qnoc_driver_init); 1415 1416 static void __exit qnoc_driver_exit(void) 1417 { 1418 platform_driver_unregister(&qnoc_driver); 1419 } 1420 module_exit(qnoc_driver_exit); 1421 1422 MODULE_DESCRIPTION("SM6115 NoC driver"); 1423 MODULE_LICENSE("GPL"); 1424