1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Implementation of the IOMMU SVA API for the ARM SMMUv3 4 */ 5 6 #include <linux/mm.h> 7 #include <linux/mmu_context.h> 8 #include <linux/mmu_notifier.h> 9 #include <linux/sched/mm.h> 10 #include <linux/slab.h> 11 12 #include "arm-smmu-v3.h" 13 #include "../../iommu-sva.h" 14 #include "../../io-pgtable-arm.h" 15 16 struct arm_smmu_mmu_notifier { 17 struct mmu_notifier mn; 18 struct arm_smmu_ctx_desc *cd; 19 bool cleared; 20 refcount_t refs; 21 struct list_head list; 22 struct arm_smmu_domain *domain; 23 }; 24 25 #define mn_to_smmu(mn) container_of(mn, struct arm_smmu_mmu_notifier, mn) 26 27 struct arm_smmu_bond { 28 struct mm_struct *mm; 29 struct arm_smmu_mmu_notifier *smmu_mn; 30 struct list_head list; 31 }; 32 33 #define sva_to_bond(handle) \ 34 container_of(handle, struct arm_smmu_bond, sva) 35 36 static DEFINE_MUTEX(sva_lock); 37 38 /* 39 * Write the CD to the CD tables for all masters that this domain is attached 40 * to. Note that this is only used to update existing CD entries in the target 41 * CD table, for which it's assumed that arm_smmu_write_ctx_desc can't fail. 42 */ 43 static void arm_smmu_update_ctx_desc_devices(struct arm_smmu_domain *smmu_domain, 44 int ssid, 45 struct arm_smmu_ctx_desc *cd) 46 { 47 struct arm_smmu_master *master; 48 unsigned long flags; 49 50 spin_lock_irqsave(&smmu_domain->devices_lock, flags); 51 list_for_each_entry(master, &smmu_domain->devices, domain_head) { 52 arm_smmu_write_ctx_desc(master, ssid, cd); 53 } 54 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); 55 } 56 57 /* 58 * Check if the CPU ASID is available on the SMMU side. If a private context 59 * descriptor is using it, try to replace it. 60 */ 61 static struct arm_smmu_ctx_desc * 62 arm_smmu_share_asid(struct mm_struct *mm, u16 asid) 63 { 64 int ret; 65 u32 new_asid; 66 struct arm_smmu_ctx_desc *cd; 67 struct arm_smmu_device *smmu; 68 struct arm_smmu_domain *smmu_domain; 69 70 cd = xa_load(&arm_smmu_asid_xa, asid); 71 if (!cd) 72 return NULL; 73 74 if (cd->mm) { 75 if (WARN_ON(cd->mm != mm)) 76 return ERR_PTR(-EINVAL); 77 /* All devices bound to this mm use the same cd struct. */ 78 refcount_inc(&cd->refs); 79 return cd; 80 } 81 82 smmu_domain = container_of(cd, struct arm_smmu_domain, cd); 83 smmu = smmu_domain->smmu; 84 85 ret = xa_alloc(&arm_smmu_asid_xa, &new_asid, cd, 86 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); 87 if (ret) 88 return ERR_PTR(-ENOSPC); 89 /* 90 * Race with unmap: TLB invalidations will start targeting the new ASID, 91 * which isn't assigned yet. We'll do an invalidate-all on the old ASID 92 * later, so it doesn't matter. 93 */ 94 cd->asid = new_asid; 95 /* 96 * Update ASID and invalidate CD in all associated masters. There will 97 * be some overlap between use of both ASIDs, until we invalidate the 98 * TLB. 99 */ 100 arm_smmu_update_ctx_desc_devices(smmu_domain, IOMMU_NO_PASID, cd); 101 102 /* Invalidate TLB entries previously associated with that context */ 103 arm_smmu_tlb_inv_asid(smmu, asid); 104 105 xa_erase(&arm_smmu_asid_xa, asid); 106 return NULL; 107 } 108 109 static struct arm_smmu_ctx_desc *arm_smmu_alloc_shared_cd(struct mm_struct *mm) 110 { 111 u16 asid; 112 int err = 0; 113 u64 tcr, par, reg; 114 struct arm_smmu_ctx_desc *cd; 115 struct arm_smmu_ctx_desc *ret = NULL; 116 117 /* Don't free the mm until we release the ASID */ 118 mmgrab(mm); 119 120 asid = arm64_mm_context_get(mm); 121 if (!asid) { 122 err = -ESRCH; 123 goto out_drop_mm; 124 } 125 126 cd = kzalloc(sizeof(*cd), GFP_KERNEL); 127 if (!cd) { 128 err = -ENOMEM; 129 goto out_put_context; 130 } 131 132 refcount_set(&cd->refs, 1); 133 134 mutex_lock(&arm_smmu_asid_lock); 135 ret = arm_smmu_share_asid(mm, asid); 136 if (ret) { 137 mutex_unlock(&arm_smmu_asid_lock); 138 goto out_free_cd; 139 } 140 141 err = xa_insert(&arm_smmu_asid_xa, asid, cd, GFP_KERNEL); 142 mutex_unlock(&arm_smmu_asid_lock); 143 144 if (err) 145 goto out_free_asid; 146 147 tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - vabits_actual) | 148 FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, ARM_LPAE_TCR_RGN_WBWA) | 149 FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, ARM_LPAE_TCR_RGN_WBWA) | 150 FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS) | 151 CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; 152 153 switch (PAGE_SIZE) { 154 case SZ_4K: 155 tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_4K); 156 break; 157 case SZ_16K: 158 tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_16K); 159 break; 160 case SZ_64K: 161 tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_64K); 162 break; 163 default: 164 WARN_ON(1); 165 err = -EINVAL; 166 goto out_free_asid; 167 } 168 169 reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 170 par = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_PARANGE_SHIFT); 171 tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par); 172 173 cd->ttbr = virt_to_phys(mm->pgd); 174 cd->tcr = tcr; 175 /* 176 * MAIR value is pretty much constant and global, so we can just get it 177 * from the current CPU register 178 */ 179 cd->mair = read_sysreg(mair_el1); 180 cd->asid = asid; 181 cd->mm = mm; 182 183 return cd; 184 185 out_free_asid: 186 arm_smmu_free_asid(cd); 187 out_free_cd: 188 kfree(cd); 189 out_put_context: 190 arm64_mm_context_put(mm); 191 out_drop_mm: 192 mmdrop(mm); 193 return err < 0 ? ERR_PTR(err) : ret; 194 } 195 196 static void arm_smmu_free_shared_cd(struct arm_smmu_ctx_desc *cd) 197 { 198 if (arm_smmu_free_asid(cd)) { 199 /* Unpin ASID */ 200 arm64_mm_context_put(cd->mm); 201 mmdrop(cd->mm); 202 kfree(cd); 203 } 204 } 205 206 /* 207 * Cloned from the MAX_TLBI_OPS in arch/arm64/include/asm/tlbflush.h, this 208 * is used as a threshold to replace per-page TLBI commands to issue in the 209 * command queue with an address-space TLBI command, when SMMU w/o a range 210 * invalidation feature handles too many per-page TLBI commands, which will 211 * otherwise result in a soft lockup. 212 */ 213 #define CMDQ_MAX_TLBI_OPS (1 << (PAGE_SHIFT - 3)) 214 215 static void arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier *mn, 216 struct mm_struct *mm, 217 unsigned long start, 218 unsigned long end) 219 { 220 struct arm_smmu_mmu_notifier *smmu_mn = mn_to_smmu(mn); 221 struct arm_smmu_domain *smmu_domain = smmu_mn->domain; 222 size_t size; 223 224 /* 225 * The mm_types defines vm_end as the first byte after the end address, 226 * different from IOMMU subsystem using the last address of an address 227 * range. So do a simple translation here by calculating size correctly. 228 */ 229 size = end - start; 230 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_RANGE_INV)) { 231 if (size >= CMDQ_MAX_TLBI_OPS * PAGE_SIZE) 232 size = 0; 233 } else { 234 if (size == ULONG_MAX) 235 size = 0; 236 } 237 238 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM)) { 239 if (!size) 240 arm_smmu_tlb_inv_asid(smmu_domain->smmu, 241 smmu_mn->cd->asid); 242 else 243 arm_smmu_tlb_inv_range_asid(start, size, 244 smmu_mn->cd->asid, 245 PAGE_SIZE, false, 246 smmu_domain); 247 } 248 249 arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, start, size); 250 } 251 252 static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) 253 { 254 struct arm_smmu_mmu_notifier *smmu_mn = mn_to_smmu(mn); 255 struct arm_smmu_domain *smmu_domain = smmu_mn->domain; 256 257 mutex_lock(&sva_lock); 258 if (smmu_mn->cleared) { 259 mutex_unlock(&sva_lock); 260 return; 261 } 262 263 /* 264 * DMA may still be running. Keep the cd valid to avoid C_BAD_CD events, 265 * but disable translation. 266 */ 267 arm_smmu_update_ctx_desc_devices(smmu_domain, mm->pasid, &quiet_cd); 268 269 arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_mn->cd->asid); 270 arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, 0, 0); 271 272 smmu_mn->cleared = true; 273 mutex_unlock(&sva_lock); 274 } 275 276 static void arm_smmu_mmu_notifier_free(struct mmu_notifier *mn) 277 { 278 kfree(mn_to_smmu(mn)); 279 } 280 281 static const struct mmu_notifier_ops arm_smmu_mmu_notifier_ops = { 282 .arch_invalidate_secondary_tlbs = arm_smmu_mm_arch_invalidate_secondary_tlbs, 283 .release = arm_smmu_mm_release, 284 .free_notifier = arm_smmu_mmu_notifier_free, 285 }; 286 287 /* Allocate or get existing MMU notifier for this {domain, mm} pair */ 288 static struct arm_smmu_mmu_notifier * 289 arm_smmu_mmu_notifier_get(struct arm_smmu_domain *smmu_domain, 290 struct mm_struct *mm) 291 { 292 int ret; 293 unsigned long flags; 294 struct arm_smmu_ctx_desc *cd; 295 struct arm_smmu_mmu_notifier *smmu_mn; 296 struct arm_smmu_master *master; 297 298 list_for_each_entry(smmu_mn, &smmu_domain->mmu_notifiers, list) { 299 if (smmu_mn->mn.mm == mm) { 300 refcount_inc(&smmu_mn->refs); 301 return smmu_mn; 302 } 303 } 304 305 cd = arm_smmu_alloc_shared_cd(mm); 306 if (IS_ERR(cd)) 307 return ERR_CAST(cd); 308 309 smmu_mn = kzalloc(sizeof(*smmu_mn), GFP_KERNEL); 310 if (!smmu_mn) { 311 ret = -ENOMEM; 312 goto err_free_cd; 313 } 314 315 refcount_set(&smmu_mn->refs, 1); 316 smmu_mn->cd = cd; 317 smmu_mn->domain = smmu_domain; 318 smmu_mn->mn.ops = &arm_smmu_mmu_notifier_ops; 319 320 ret = mmu_notifier_register(&smmu_mn->mn, mm); 321 if (ret) { 322 kfree(smmu_mn); 323 goto err_free_cd; 324 } 325 326 spin_lock_irqsave(&smmu_domain->devices_lock, flags); 327 list_for_each_entry(master, &smmu_domain->devices, domain_head) { 328 ret = arm_smmu_write_ctx_desc(master, mm->pasid, cd); 329 if (ret) { 330 list_for_each_entry_from_reverse(master, &smmu_domain->devices, domain_head) 331 arm_smmu_write_ctx_desc(master, mm->pasid, NULL); 332 break; 333 } 334 } 335 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); 336 if (ret) 337 goto err_put_notifier; 338 339 list_add(&smmu_mn->list, &smmu_domain->mmu_notifiers); 340 return smmu_mn; 341 342 err_put_notifier: 343 /* Frees smmu_mn */ 344 mmu_notifier_put(&smmu_mn->mn); 345 err_free_cd: 346 arm_smmu_free_shared_cd(cd); 347 return ERR_PTR(ret); 348 } 349 350 static void arm_smmu_mmu_notifier_put(struct arm_smmu_mmu_notifier *smmu_mn) 351 { 352 struct mm_struct *mm = smmu_mn->mn.mm; 353 struct arm_smmu_ctx_desc *cd = smmu_mn->cd; 354 struct arm_smmu_domain *smmu_domain = smmu_mn->domain; 355 356 if (!refcount_dec_and_test(&smmu_mn->refs)) 357 return; 358 359 list_del(&smmu_mn->list); 360 361 arm_smmu_update_ctx_desc_devices(smmu_domain, mm->pasid, NULL); 362 363 /* 364 * If we went through clear(), we've already invalidated, and no 365 * new TLB entry can have been formed. 366 */ 367 if (!smmu_mn->cleared) { 368 arm_smmu_tlb_inv_asid(smmu_domain->smmu, cd->asid); 369 arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, 0, 0); 370 } 371 372 /* Frees smmu_mn */ 373 mmu_notifier_put(&smmu_mn->mn); 374 arm_smmu_free_shared_cd(cd); 375 } 376 377 static int __arm_smmu_sva_bind(struct device *dev, struct mm_struct *mm) 378 { 379 int ret; 380 struct arm_smmu_bond *bond; 381 struct arm_smmu_master *master = dev_iommu_priv_get(dev); 382 struct iommu_domain *domain = iommu_get_domain_for_dev(dev); 383 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); 384 385 if (!master || !master->sva_enabled) 386 return -ENODEV; 387 388 bond = kzalloc(sizeof(*bond), GFP_KERNEL); 389 if (!bond) 390 return -ENOMEM; 391 392 bond->mm = mm; 393 394 bond->smmu_mn = arm_smmu_mmu_notifier_get(smmu_domain, mm); 395 if (IS_ERR(bond->smmu_mn)) { 396 ret = PTR_ERR(bond->smmu_mn); 397 goto err_free_bond; 398 } 399 400 list_add(&bond->list, &master->bonds); 401 return 0; 402 403 err_free_bond: 404 kfree(bond); 405 return ret; 406 } 407 408 bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) 409 { 410 unsigned long reg, fld; 411 unsigned long oas; 412 unsigned long asid_bits; 413 u32 feat_mask = ARM_SMMU_FEAT_COHERENCY; 414 415 if (vabits_actual == 52) 416 feat_mask |= ARM_SMMU_FEAT_VAX; 417 418 if ((smmu->features & feat_mask) != feat_mask) 419 return false; 420 421 if (!(smmu->pgsize_bitmap & PAGE_SIZE)) 422 return false; 423 424 /* 425 * Get the smallest PA size of all CPUs (sanitized by cpufeature). We're 426 * not even pretending to support AArch32 here. Abort if the MMU outputs 427 * addresses larger than what we support. 428 */ 429 reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 430 fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_PARANGE_SHIFT); 431 oas = id_aa64mmfr0_parange_to_phys_shift(fld); 432 if (smmu->oas < oas) 433 return false; 434 435 /* We can support bigger ASIDs than the CPU, but not smaller */ 436 fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT); 437 asid_bits = fld ? 16 : 8; 438 if (smmu->asid_bits < asid_bits) 439 return false; 440 441 /* 442 * See max_pinned_asids in arch/arm64/mm/context.c. The following is 443 * generally the maximum number of bindable processes. 444 */ 445 if (arm64_kernel_unmapped_at_el0()) 446 asid_bits--; 447 dev_dbg(smmu->dev, "%d shared contexts\n", (1 << asid_bits) - 448 num_possible_cpus() - 2); 449 450 return true; 451 } 452 453 bool arm_smmu_master_iopf_supported(struct arm_smmu_master *master) 454 { 455 /* We're not keeping track of SIDs in fault events */ 456 if (master->num_streams != 1) 457 return false; 458 459 return master->stall_enabled; 460 } 461 462 bool arm_smmu_master_sva_supported(struct arm_smmu_master *master) 463 { 464 if (!(master->smmu->features & ARM_SMMU_FEAT_SVA)) 465 return false; 466 467 /* SSID support is mandatory for the moment */ 468 return master->ssid_bits; 469 } 470 471 bool arm_smmu_master_sva_enabled(struct arm_smmu_master *master) 472 { 473 bool enabled; 474 475 mutex_lock(&sva_lock); 476 enabled = master->sva_enabled; 477 mutex_unlock(&sva_lock); 478 return enabled; 479 } 480 481 static int arm_smmu_master_sva_enable_iopf(struct arm_smmu_master *master) 482 { 483 int ret; 484 struct device *dev = master->dev; 485 486 /* 487 * Drivers for devices supporting PRI or stall should enable IOPF first. 488 * Others have device-specific fault handlers and don't need IOPF. 489 */ 490 if (!arm_smmu_master_iopf_supported(master)) 491 return 0; 492 493 if (!master->iopf_enabled) 494 return -EINVAL; 495 496 ret = iopf_queue_add_device(master->smmu->evtq.iopf, dev); 497 if (ret) 498 return ret; 499 500 ret = iommu_register_device_fault_handler(dev, iommu_queue_iopf, dev); 501 if (ret) { 502 iopf_queue_remove_device(master->smmu->evtq.iopf, dev); 503 return ret; 504 } 505 return 0; 506 } 507 508 static void arm_smmu_master_sva_disable_iopf(struct arm_smmu_master *master) 509 { 510 struct device *dev = master->dev; 511 512 if (!master->iopf_enabled) 513 return; 514 515 iommu_unregister_device_fault_handler(dev); 516 iopf_queue_remove_device(master->smmu->evtq.iopf, dev); 517 } 518 519 int arm_smmu_master_enable_sva(struct arm_smmu_master *master) 520 { 521 int ret; 522 523 mutex_lock(&sva_lock); 524 ret = arm_smmu_master_sva_enable_iopf(master); 525 if (!ret) 526 master->sva_enabled = true; 527 mutex_unlock(&sva_lock); 528 529 return ret; 530 } 531 532 int arm_smmu_master_disable_sva(struct arm_smmu_master *master) 533 { 534 mutex_lock(&sva_lock); 535 if (!list_empty(&master->bonds)) { 536 dev_err(master->dev, "cannot disable SVA, device is bound\n"); 537 mutex_unlock(&sva_lock); 538 return -EBUSY; 539 } 540 arm_smmu_master_sva_disable_iopf(master); 541 master->sva_enabled = false; 542 mutex_unlock(&sva_lock); 543 544 return 0; 545 } 546 547 void arm_smmu_sva_notifier_synchronize(void) 548 { 549 /* 550 * Some MMU notifiers may still be waiting to be freed, using 551 * arm_smmu_mmu_notifier_free(). Wait for them. 552 */ 553 mmu_notifier_synchronize(); 554 } 555 556 void arm_smmu_sva_remove_dev_pasid(struct iommu_domain *domain, 557 struct device *dev, ioasid_t id) 558 { 559 struct mm_struct *mm = domain->mm; 560 struct arm_smmu_bond *bond = NULL, *t; 561 struct arm_smmu_master *master = dev_iommu_priv_get(dev); 562 563 mutex_lock(&sva_lock); 564 list_for_each_entry(t, &master->bonds, list) { 565 if (t->mm == mm) { 566 bond = t; 567 break; 568 } 569 } 570 571 if (!WARN_ON(!bond)) { 572 list_del(&bond->list); 573 arm_smmu_mmu_notifier_put(bond->smmu_mn); 574 kfree(bond); 575 } 576 mutex_unlock(&sva_lock); 577 } 578 579 static int arm_smmu_sva_set_dev_pasid(struct iommu_domain *domain, 580 struct device *dev, ioasid_t id) 581 { 582 int ret = 0; 583 struct mm_struct *mm = domain->mm; 584 585 mutex_lock(&sva_lock); 586 ret = __arm_smmu_sva_bind(dev, mm); 587 mutex_unlock(&sva_lock); 588 589 return ret; 590 } 591 592 static void arm_smmu_sva_domain_free(struct iommu_domain *domain) 593 { 594 kfree(domain); 595 } 596 597 static const struct iommu_domain_ops arm_smmu_sva_domain_ops = { 598 .set_dev_pasid = arm_smmu_sva_set_dev_pasid, 599 .free = arm_smmu_sva_domain_free 600 }; 601 602 struct iommu_domain *arm_smmu_sva_domain_alloc(void) 603 { 604 struct iommu_domain *domain; 605 606 domain = kzalloc(sizeof(*domain), GFP_KERNEL); 607 if (!domain) 608 return NULL; 609 domain->ops = &arm_smmu_sva_domain_ops; 610 611 return domain; 612 } 613