1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2006, Intel Corporation. 4 * 5 * Copyright (C) 2006-2008 Intel Corporation 6 * Author: Ashok Raj <ashok.raj@intel.com> 7 * Author: Shaohua Li <shaohua.li@intel.com> 8 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> 9 * 10 * This file implements early detection/parsing of Remapping Devices 11 * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI 12 * tables. 13 * 14 * These routines are used by both DMA-remapping and Interrupt-remapping 15 */ 16 17 #define pr_fmt(fmt) "DMAR: " fmt 18 19 #include <linux/pci.h> 20 #include <linux/dmar.h> 21 #include <linux/iova.h> 22 #include <linux/timer.h> 23 #include <linux/irq.h> 24 #include <linux/interrupt.h> 25 #include <linux/tboot.h> 26 #include <linux/dmi.h> 27 #include <linux/slab.h> 28 #include <linux/iommu.h> 29 #include <linux/numa.h> 30 #include <linux/limits.h> 31 #include <asm/irq_remapping.h> 32 33 #include "iommu.h" 34 #include "../irq_remapping.h" 35 #include "perf.h" 36 #include "trace.h" 37 #include "perfmon.h" 38 39 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *); 40 struct dmar_res_callback { 41 dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED]; 42 void *arg[ACPI_DMAR_TYPE_RESERVED]; 43 bool ignore_unhandled; 44 bool print_entry; 45 }; 46 47 /* 48 * Assumptions: 49 * 1) The hotplug framework guarentees that DMAR unit will be hot-added 50 * before IO devices managed by that unit. 51 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed 52 * after IO devices managed by that unit. 53 * 3) Hotplug events are rare. 54 * 55 * Locking rules for DMA and interrupt remapping related global data structures: 56 * 1) Use dmar_global_lock in process context 57 * 2) Use RCU in interrupt context 58 */ 59 DECLARE_RWSEM(dmar_global_lock); 60 LIST_HEAD(dmar_drhd_units); 61 62 struct acpi_table_header * __initdata dmar_tbl; 63 static int dmar_dev_scope_status = 1; 64 static DEFINE_IDA(dmar_seq_ids); 65 66 static int alloc_iommu(struct dmar_drhd_unit *drhd); 67 static void free_iommu(struct intel_iommu *iommu); 68 69 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd) 70 { 71 /* 72 * add INCLUDE_ALL at the tail, so scan the list will find it at 73 * the very end. 74 */ 75 if (drhd->include_all) 76 list_add_tail_rcu(&drhd->list, &dmar_drhd_units); 77 else 78 list_add_rcu(&drhd->list, &dmar_drhd_units); 79 } 80 81 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt) 82 { 83 struct acpi_dmar_device_scope *scope; 84 85 *cnt = 0; 86 while (start < end) { 87 scope = start; 88 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE || 89 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || 90 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) 91 (*cnt)++; 92 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && 93 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { 94 pr_warn("Unsupported device scope\n"); 95 } 96 start += scope->length; 97 } 98 if (*cnt == 0) 99 return NULL; 100 101 return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL); 102 } 103 104 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt) 105 { 106 int i; 107 struct device *tmp_dev; 108 109 if (*devices && *cnt) { 110 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev) 111 put_device(tmp_dev); 112 kfree(*devices); 113 } 114 115 *devices = NULL; 116 *cnt = 0; 117 } 118 119 /* Optimize out kzalloc()/kfree() for normal cases */ 120 static char dmar_pci_notify_info_buf[64]; 121 122 static struct dmar_pci_notify_info * 123 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event) 124 { 125 int level = 0; 126 size_t size; 127 struct pci_dev *tmp; 128 struct dmar_pci_notify_info *info; 129 130 BUG_ON(dev->is_virtfn); 131 132 /* 133 * Ignore devices that have a domain number higher than what can 134 * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000 135 */ 136 if (pci_domain_nr(dev->bus) > U16_MAX) 137 return NULL; 138 139 /* Only generate path[] for device addition event */ 140 if (event == BUS_NOTIFY_ADD_DEVICE) 141 for (tmp = dev; tmp; tmp = tmp->bus->self) 142 level++; 143 144 size = struct_size(info, path, level); 145 if (size <= sizeof(dmar_pci_notify_info_buf)) { 146 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf; 147 } else { 148 info = kzalloc(size, GFP_KERNEL); 149 if (!info) { 150 if (dmar_dev_scope_status == 0) 151 dmar_dev_scope_status = -ENOMEM; 152 return NULL; 153 } 154 } 155 156 info->event = event; 157 info->dev = dev; 158 info->seg = pci_domain_nr(dev->bus); 159 info->level = level; 160 if (event == BUS_NOTIFY_ADD_DEVICE) { 161 for (tmp = dev; tmp; tmp = tmp->bus->self) { 162 level--; 163 info->path[level].bus = tmp->bus->number; 164 info->path[level].device = PCI_SLOT(tmp->devfn); 165 info->path[level].function = PCI_FUNC(tmp->devfn); 166 if (pci_is_root_bus(tmp->bus)) 167 info->bus = tmp->bus->number; 168 } 169 } 170 171 return info; 172 } 173 174 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info) 175 { 176 if ((void *)info != dmar_pci_notify_info_buf) 177 kfree(info); 178 } 179 180 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus, 181 struct acpi_dmar_pci_path *path, int count) 182 { 183 int i; 184 185 if (info->bus != bus) 186 goto fallback; 187 if (info->level != count) 188 goto fallback; 189 190 for (i = 0; i < count; i++) { 191 if (path[i].device != info->path[i].device || 192 path[i].function != info->path[i].function) 193 goto fallback; 194 } 195 196 return true; 197 198 fallback: 199 200 if (count != 1) 201 return false; 202 203 i = info->level - 1; 204 if (bus == info->path[i].bus && 205 path[0].device == info->path[i].device && 206 path[0].function == info->path[i].function) { 207 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n", 208 bus, path[0].device, path[0].function); 209 return true; 210 } 211 212 return false; 213 } 214 215 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */ 216 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, 217 void *start, void*end, u16 segment, 218 struct dmar_dev_scope *devices, 219 int devices_cnt) 220 { 221 int i, level; 222 struct device *tmp, *dev = &info->dev->dev; 223 struct acpi_dmar_device_scope *scope; 224 struct acpi_dmar_pci_path *path; 225 226 if (segment != info->seg) 227 return 0; 228 229 for (; start < end; start += scope->length) { 230 scope = start; 231 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 232 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 233 continue; 234 235 path = (struct acpi_dmar_pci_path *)(scope + 1); 236 level = (scope->length - sizeof(*scope)) / sizeof(*path); 237 if (!dmar_match_pci_path(info, scope->bus, path, level)) 238 continue; 239 240 /* 241 * We expect devices with endpoint scope to have normal PCI 242 * headers, and devices with bridge scope to have bridge PCI 243 * headers. However PCI NTB devices may be listed in the 244 * DMAR table with bridge scope, even though they have a 245 * normal PCI header. NTB devices are identified by class 246 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch 247 * for this special case. 248 */ 249 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 250 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) || 251 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE && 252 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 253 info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) { 254 pr_warn("Device scope type does not match for %s\n", 255 pci_name(info->dev)); 256 return -EINVAL; 257 } 258 259 for_each_dev_scope(devices, devices_cnt, i, tmp) 260 if (tmp == NULL) { 261 devices[i].bus = info->dev->bus->number; 262 devices[i].devfn = info->dev->devfn; 263 rcu_assign_pointer(devices[i].dev, 264 get_device(dev)); 265 return 1; 266 } 267 BUG_ON(i >= devices_cnt); 268 } 269 270 return 0; 271 } 272 273 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment, 274 struct dmar_dev_scope *devices, int count) 275 { 276 int index; 277 struct device *tmp; 278 279 if (info->seg != segment) 280 return 0; 281 282 for_each_active_dev_scope(devices, count, index, tmp) 283 if (tmp == &info->dev->dev) { 284 RCU_INIT_POINTER(devices[index].dev, NULL); 285 synchronize_rcu(); 286 put_device(tmp); 287 return 1; 288 } 289 290 return 0; 291 } 292 293 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info) 294 { 295 int ret = 0; 296 struct dmar_drhd_unit *dmaru; 297 struct acpi_dmar_hardware_unit *drhd; 298 299 for_each_drhd_unit(dmaru) { 300 if (dmaru->include_all) 301 continue; 302 303 drhd = container_of(dmaru->hdr, 304 struct acpi_dmar_hardware_unit, header); 305 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1), 306 ((void *)drhd) + drhd->header.length, 307 dmaru->segment, 308 dmaru->devices, dmaru->devices_cnt); 309 if (ret) 310 break; 311 } 312 if (ret >= 0) 313 ret = dmar_iommu_notify_scope_dev(info); 314 if (ret < 0 && dmar_dev_scope_status == 0) 315 dmar_dev_scope_status = ret; 316 317 if (ret >= 0) 318 intel_irq_remap_add_device(info); 319 320 return ret; 321 } 322 323 static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info) 324 { 325 struct dmar_drhd_unit *dmaru; 326 327 for_each_drhd_unit(dmaru) 328 if (dmar_remove_dev_scope(info, dmaru->segment, 329 dmaru->devices, dmaru->devices_cnt)) 330 break; 331 dmar_iommu_notify_scope_dev(info); 332 } 333 334 static inline void vf_inherit_msi_domain(struct pci_dev *pdev) 335 { 336 struct pci_dev *physfn = pci_physfn(pdev); 337 338 dev_set_msi_domain(&pdev->dev, dev_get_msi_domain(&physfn->dev)); 339 } 340 341 static int dmar_pci_bus_notifier(struct notifier_block *nb, 342 unsigned long action, void *data) 343 { 344 struct pci_dev *pdev = to_pci_dev(data); 345 struct dmar_pci_notify_info *info; 346 347 /* Only care about add/remove events for physical functions. 348 * For VFs we actually do the lookup based on the corresponding 349 * PF in device_to_iommu() anyway. */ 350 if (pdev->is_virtfn) { 351 /* 352 * Ensure that the VF device inherits the irq domain of the 353 * PF device. Ideally the device would inherit the domain 354 * from the bus, but DMAR can have multiple units per bus 355 * which makes this impossible. The VF 'bus' could inherit 356 * from the PF device, but that's yet another x86'sism to 357 * inflict on everybody else. 358 */ 359 if (action == BUS_NOTIFY_ADD_DEVICE) 360 vf_inherit_msi_domain(pdev); 361 return NOTIFY_DONE; 362 } 363 364 if (action != BUS_NOTIFY_ADD_DEVICE && 365 action != BUS_NOTIFY_REMOVED_DEVICE) 366 return NOTIFY_DONE; 367 368 info = dmar_alloc_pci_notify_info(pdev, action); 369 if (!info) 370 return NOTIFY_DONE; 371 372 down_write(&dmar_global_lock); 373 if (action == BUS_NOTIFY_ADD_DEVICE) 374 dmar_pci_bus_add_dev(info); 375 else if (action == BUS_NOTIFY_REMOVED_DEVICE) 376 dmar_pci_bus_del_dev(info); 377 up_write(&dmar_global_lock); 378 379 dmar_free_pci_notify_info(info); 380 381 return NOTIFY_OK; 382 } 383 384 static struct notifier_block dmar_pci_bus_nb = { 385 .notifier_call = dmar_pci_bus_notifier, 386 .priority = 1, 387 }; 388 389 static struct dmar_drhd_unit * 390 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd) 391 { 392 struct dmar_drhd_unit *dmaru; 393 394 list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list, 395 dmar_rcu_check()) 396 if (dmaru->segment == drhd->segment && 397 dmaru->reg_base_addr == drhd->address) 398 return dmaru; 399 400 return NULL; 401 } 402 403 /* 404 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition 405 * structure which uniquely represent one DMA remapping hardware unit 406 * present in the platform 407 */ 408 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg) 409 { 410 struct acpi_dmar_hardware_unit *drhd; 411 struct dmar_drhd_unit *dmaru; 412 int ret; 413 414 drhd = (struct acpi_dmar_hardware_unit *)header; 415 dmaru = dmar_find_dmaru(drhd); 416 if (dmaru) 417 goto out; 418 419 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL); 420 if (!dmaru) 421 return -ENOMEM; 422 423 /* 424 * If header is allocated from slab by ACPI _DSM method, we need to 425 * copy the content because the memory buffer will be freed on return. 426 */ 427 dmaru->hdr = (void *)(dmaru + 1); 428 memcpy(dmaru->hdr, header, header->length); 429 dmaru->reg_base_addr = drhd->address; 430 dmaru->segment = drhd->segment; 431 /* The size of the register set is 2 ^ N 4 KB pages. */ 432 dmaru->reg_size = 1UL << (drhd->size + 12); 433 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ 434 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1), 435 ((void *)drhd) + drhd->header.length, 436 &dmaru->devices_cnt); 437 if (dmaru->devices_cnt && dmaru->devices == NULL) { 438 kfree(dmaru); 439 return -ENOMEM; 440 } 441 442 ret = alloc_iommu(dmaru); 443 if (ret) { 444 dmar_free_dev_scope(&dmaru->devices, 445 &dmaru->devices_cnt); 446 kfree(dmaru); 447 return ret; 448 } 449 dmar_register_drhd_unit(dmaru); 450 451 out: 452 if (arg) 453 (*(int *)arg)++; 454 455 return 0; 456 } 457 458 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru) 459 { 460 if (dmaru->devices && dmaru->devices_cnt) 461 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); 462 if (dmaru->iommu) 463 free_iommu(dmaru->iommu); 464 kfree(dmaru); 465 } 466 467 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header, 468 void *arg) 469 { 470 struct acpi_dmar_andd *andd = (void *)header; 471 472 /* Check for NUL termination within the designated length */ 473 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { 474 pr_warn(FW_BUG 475 "Your BIOS is broken; ANDD object name is not NUL-terminated\n" 476 "BIOS vendor: %s; Ver: %s; Product Version: %s\n", 477 dmi_get_system_info(DMI_BIOS_VENDOR), 478 dmi_get_system_info(DMI_BIOS_VERSION), 479 dmi_get_system_info(DMI_PRODUCT_VERSION)); 480 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 481 return -EINVAL; 482 } 483 pr_info("ANDD device: %x name: %s\n", andd->device_number, 484 andd->device_name); 485 486 return 0; 487 } 488 489 #ifdef CONFIG_ACPI_NUMA 490 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg) 491 { 492 struct acpi_dmar_rhsa *rhsa; 493 struct dmar_drhd_unit *drhd; 494 495 rhsa = (struct acpi_dmar_rhsa *)header; 496 for_each_drhd_unit(drhd) { 497 if (drhd->reg_base_addr == rhsa->base_address) { 498 int node = pxm_to_node(rhsa->proximity_domain); 499 500 if (node != NUMA_NO_NODE && !node_online(node)) 501 node = NUMA_NO_NODE; 502 drhd->iommu->node = node; 503 return 0; 504 } 505 } 506 pr_warn(FW_BUG 507 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" 508 "BIOS vendor: %s; Ver: %s; Product Version: %s\n", 509 rhsa->base_address, 510 dmi_get_system_info(DMI_BIOS_VENDOR), 511 dmi_get_system_info(DMI_BIOS_VERSION), 512 dmi_get_system_info(DMI_PRODUCT_VERSION)); 513 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 514 515 return 0; 516 } 517 #else 518 #define dmar_parse_one_rhsa dmar_res_noop 519 #endif 520 521 static void 522 dmar_table_print_dmar_entry(struct acpi_dmar_header *header) 523 { 524 struct acpi_dmar_hardware_unit *drhd; 525 struct acpi_dmar_reserved_memory *rmrr; 526 struct acpi_dmar_atsr *atsr; 527 struct acpi_dmar_rhsa *rhsa; 528 struct acpi_dmar_satc *satc; 529 530 switch (header->type) { 531 case ACPI_DMAR_TYPE_HARDWARE_UNIT: 532 drhd = container_of(header, struct acpi_dmar_hardware_unit, 533 header); 534 pr_info("DRHD base: %#016Lx flags: %#x\n", 535 (unsigned long long)drhd->address, drhd->flags); 536 break; 537 case ACPI_DMAR_TYPE_RESERVED_MEMORY: 538 rmrr = container_of(header, struct acpi_dmar_reserved_memory, 539 header); 540 pr_info("RMRR base: %#016Lx end: %#016Lx\n", 541 (unsigned long long)rmrr->base_address, 542 (unsigned long long)rmrr->end_address); 543 break; 544 case ACPI_DMAR_TYPE_ROOT_ATS: 545 atsr = container_of(header, struct acpi_dmar_atsr, header); 546 pr_info("ATSR flags: %#x\n", atsr->flags); 547 break; 548 case ACPI_DMAR_TYPE_HARDWARE_AFFINITY: 549 rhsa = container_of(header, struct acpi_dmar_rhsa, header); 550 pr_info("RHSA base: %#016Lx proximity domain: %#x\n", 551 (unsigned long long)rhsa->base_address, 552 rhsa->proximity_domain); 553 break; 554 case ACPI_DMAR_TYPE_NAMESPACE: 555 /* We don't print this here because we need to sanity-check 556 it first. So print it in dmar_parse_one_andd() instead. */ 557 break; 558 case ACPI_DMAR_TYPE_SATC: 559 satc = container_of(header, struct acpi_dmar_satc, header); 560 pr_info("SATC flags: 0x%x\n", satc->flags); 561 break; 562 } 563 } 564 565 /** 566 * dmar_table_detect - checks to see if the platform supports DMAR devices 567 */ 568 static int __init dmar_table_detect(void) 569 { 570 acpi_status status = AE_OK; 571 572 /* if we could find DMAR table, then there are DMAR devices */ 573 status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl); 574 575 if (ACPI_SUCCESS(status) && !dmar_tbl) { 576 pr_warn("Unable to map DMAR\n"); 577 status = AE_NOT_FOUND; 578 } 579 580 return ACPI_SUCCESS(status) ? 0 : -ENOENT; 581 } 582 583 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start, 584 size_t len, struct dmar_res_callback *cb) 585 { 586 struct acpi_dmar_header *iter, *next; 587 struct acpi_dmar_header *end = ((void *)start) + len; 588 589 for (iter = start; iter < end; iter = next) { 590 next = (void *)iter + iter->length; 591 if (iter->length == 0) { 592 /* Avoid looping forever on bad ACPI tables */ 593 pr_debug(FW_BUG "Invalid 0-length structure\n"); 594 break; 595 } else if (next > end) { 596 /* Avoid passing table end */ 597 pr_warn(FW_BUG "Record passes table end\n"); 598 return -EINVAL; 599 } 600 601 if (cb->print_entry) 602 dmar_table_print_dmar_entry(iter); 603 604 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) { 605 /* continue for forward compatibility */ 606 pr_debug("Unknown DMAR structure type %d\n", 607 iter->type); 608 } else if (cb->cb[iter->type]) { 609 int ret; 610 611 ret = cb->cb[iter->type](iter, cb->arg[iter->type]); 612 if (ret) 613 return ret; 614 } else if (!cb->ignore_unhandled) { 615 pr_warn("No handler for DMAR structure type %d\n", 616 iter->type); 617 return -EINVAL; 618 } 619 } 620 621 return 0; 622 } 623 624 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar, 625 struct dmar_res_callback *cb) 626 { 627 return dmar_walk_remapping_entries((void *)(dmar + 1), 628 dmar->header.length - sizeof(*dmar), cb); 629 } 630 631 /** 632 * parse_dmar_table - parses the DMA reporting table 633 */ 634 static int __init 635 parse_dmar_table(void) 636 { 637 struct acpi_table_dmar *dmar; 638 int drhd_count = 0; 639 int ret; 640 struct dmar_res_callback cb = { 641 .print_entry = true, 642 .ignore_unhandled = true, 643 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count, 644 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd, 645 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr, 646 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr, 647 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa, 648 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd, 649 .cb[ACPI_DMAR_TYPE_SATC] = &dmar_parse_one_satc, 650 }; 651 652 /* 653 * Do it again, earlier dmar_tbl mapping could be mapped with 654 * fixed map. 655 */ 656 dmar_table_detect(); 657 658 /* 659 * ACPI tables may not be DMA protected by tboot, so use DMAR copy 660 * SINIT saved in SinitMleData in TXT heap (which is DMA protected) 661 */ 662 dmar_tbl = tboot_get_dmar_table(dmar_tbl); 663 664 dmar = (struct acpi_table_dmar *)dmar_tbl; 665 if (!dmar) 666 return -ENODEV; 667 668 if (dmar->width < PAGE_SHIFT - 1) { 669 pr_warn("Invalid DMAR haw\n"); 670 return -EINVAL; 671 } 672 673 pr_info("Host address width %d\n", dmar->width + 1); 674 ret = dmar_walk_dmar_table(dmar, &cb); 675 if (ret == 0 && drhd_count == 0) 676 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n"); 677 678 return ret; 679 } 680 681 static int dmar_pci_device_match(struct dmar_dev_scope devices[], 682 int cnt, struct pci_dev *dev) 683 { 684 int index; 685 struct device *tmp; 686 687 while (dev) { 688 for_each_active_dev_scope(devices, cnt, index, tmp) 689 if (dev_is_pci(tmp) && dev == to_pci_dev(tmp)) 690 return 1; 691 692 /* Check our parent */ 693 dev = dev->bus->self; 694 } 695 696 return 0; 697 } 698 699 struct dmar_drhd_unit * 700 dmar_find_matched_drhd_unit(struct pci_dev *dev) 701 { 702 struct dmar_drhd_unit *dmaru; 703 struct acpi_dmar_hardware_unit *drhd; 704 705 dev = pci_physfn(dev); 706 707 rcu_read_lock(); 708 for_each_drhd_unit(dmaru) { 709 drhd = container_of(dmaru->hdr, 710 struct acpi_dmar_hardware_unit, 711 header); 712 713 if (dmaru->include_all && 714 drhd->segment == pci_domain_nr(dev->bus)) 715 goto out; 716 717 if (dmar_pci_device_match(dmaru->devices, 718 dmaru->devices_cnt, dev)) 719 goto out; 720 } 721 dmaru = NULL; 722 out: 723 rcu_read_unlock(); 724 725 return dmaru; 726 } 727 728 static void __init dmar_acpi_insert_dev_scope(u8 device_number, 729 struct acpi_device *adev) 730 { 731 struct dmar_drhd_unit *dmaru; 732 struct acpi_dmar_hardware_unit *drhd; 733 struct acpi_dmar_device_scope *scope; 734 struct device *tmp; 735 int i; 736 struct acpi_dmar_pci_path *path; 737 738 for_each_drhd_unit(dmaru) { 739 drhd = container_of(dmaru->hdr, 740 struct acpi_dmar_hardware_unit, 741 header); 742 743 for (scope = (void *)(drhd + 1); 744 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; 745 scope = ((void *)scope) + scope->length) { 746 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) 747 continue; 748 if (scope->enumeration_id != device_number) 749 continue; 750 751 path = (void *)(scope + 1); 752 pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n", 753 dev_name(&adev->dev), dmaru->reg_base_addr, 754 scope->bus, path->device, path->function); 755 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) 756 if (tmp == NULL) { 757 dmaru->devices[i].bus = scope->bus; 758 dmaru->devices[i].devfn = PCI_DEVFN(path->device, 759 path->function); 760 rcu_assign_pointer(dmaru->devices[i].dev, 761 get_device(&adev->dev)); 762 return; 763 } 764 BUG_ON(i >= dmaru->devices_cnt); 765 } 766 } 767 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", 768 device_number, dev_name(&adev->dev)); 769 } 770 771 static int __init dmar_acpi_dev_scope_init(void) 772 { 773 struct acpi_dmar_andd *andd; 774 775 if (dmar_tbl == NULL) 776 return -ENODEV; 777 778 for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar); 779 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length; 780 andd = ((void *)andd) + andd->header.length) { 781 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) { 782 acpi_handle h; 783 struct acpi_device *adev; 784 785 if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT, 786 andd->device_name, 787 &h))) { 788 pr_err("Failed to find handle for ACPI object %s\n", 789 andd->device_name); 790 continue; 791 } 792 adev = acpi_fetch_acpi_dev(h); 793 if (!adev) { 794 pr_err("Failed to get device for ACPI object %s\n", 795 andd->device_name); 796 continue; 797 } 798 dmar_acpi_insert_dev_scope(andd->device_number, adev); 799 } 800 } 801 return 0; 802 } 803 804 int __init dmar_dev_scope_init(void) 805 { 806 struct pci_dev *dev = NULL; 807 struct dmar_pci_notify_info *info; 808 809 if (dmar_dev_scope_status != 1) 810 return dmar_dev_scope_status; 811 812 if (list_empty(&dmar_drhd_units)) { 813 dmar_dev_scope_status = -ENODEV; 814 } else { 815 dmar_dev_scope_status = 0; 816 817 dmar_acpi_dev_scope_init(); 818 819 for_each_pci_dev(dev) { 820 if (dev->is_virtfn) 821 continue; 822 823 info = dmar_alloc_pci_notify_info(dev, 824 BUS_NOTIFY_ADD_DEVICE); 825 if (!info) { 826 pci_dev_put(dev); 827 return dmar_dev_scope_status; 828 } else { 829 dmar_pci_bus_add_dev(info); 830 dmar_free_pci_notify_info(info); 831 } 832 } 833 } 834 835 return dmar_dev_scope_status; 836 } 837 838 void __init dmar_register_bus_notifier(void) 839 { 840 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb); 841 } 842 843 844 int __init dmar_table_init(void) 845 { 846 static int dmar_table_initialized; 847 int ret; 848 849 if (dmar_table_initialized == 0) { 850 ret = parse_dmar_table(); 851 if (ret < 0) { 852 if (ret != -ENODEV) 853 pr_info("Parse DMAR table failure.\n"); 854 } else if (list_empty(&dmar_drhd_units)) { 855 pr_info("No DMAR devices found\n"); 856 ret = -ENODEV; 857 } 858 859 if (ret < 0) 860 dmar_table_initialized = ret; 861 else 862 dmar_table_initialized = 1; 863 } 864 865 return dmar_table_initialized < 0 ? dmar_table_initialized : 0; 866 } 867 868 static void warn_invalid_dmar(u64 addr, const char *message) 869 { 870 pr_warn_once(FW_BUG 871 "Your BIOS is broken; DMAR reported at address %llx%s!\n" 872 "BIOS vendor: %s; Ver: %s; Product Version: %s\n", 873 addr, message, 874 dmi_get_system_info(DMI_BIOS_VENDOR), 875 dmi_get_system_info(DMI_BIOS_VERSION), 876 dmi_get_system_info(DMI_PRODUCT_VERSION)); 877 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 878 } 879 880 static int __ref 881 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg) 882 { 883 struct acpi_dmar_hardware_unit *drhd; 884 void __iomem *addr; 885 u64 cap, ecap; 886 887 drhd = (void *)entry; 888 if (!drhd->address) { 889 warn_invalid_dmar(0, ""); 890 return -EINVAL; 891 } 892 893 if (arg) 894 addr = ioremap(drhd->address, VTD_PAGE_SIZE); 895 else 896 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); 897 if (!addr) { 898 pr_warn("Can't validate DRHD address: %llx\n", drhd->address); 899 return -EINVAL; 900 } 901 902 cap = dmar_readq(addr + DMAR_CAP_REG); 903 ecap = dmar_readq(addr + DMAR_ECAP_REG); 904 905 if (arg) 906 iounmap(addr); 907 else 908 early_iounmap(addr, VTD_PAGE_SIZE); 909 910 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { 911 warn_invalid_dmar(drhd->address, " returns all ones"); 912 return -EINVAL; 913 } 914 915 return 0; 916 } 917 918 void __init detect_intel_iommu(void) 919 { 920 int ret; 921 struct dmar_res_callback validate_drhd_cb = { 922 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd, 923 .ignore_unhandled = true, 924 }; 925 926 down_write(&dmar_global_lock); 927 ret = dmar_table_detect(); 928 if (!ret) 929 ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl, 930 &validate_drhd_cb); 931 if (!ret && !no_iommu && !iommu_detected && 932 (!dmar_disabled || dmar_platform_optin())) { 933 iommu_detected = 1; 934 /* Make sure ACS will be enabled */ 935 pci_request_acs(); 936 } 937 938 #ifdef CONFIG_X86 939 if (!ret) { 940 x86_init.iommu.iommu_init = intel_iommu_init; 941 x86_platform.iommu_shutdown = intel_iommu_shutdown; 942 } 943 944 #endif 945 946 if (dmar_tbl) { 947 acpi_put_table(dmar_tbl); 948 dmar_tbl = NULL; 949 } 950 up_write(&dmar_global_lock); 951 } 952 953 static void unmap_iommu(struct intel_iommu *iommu) 954 { 955 iounmap(iommu->reg); 956 release_mem_region(iommu->reg_phys, iommu->reg_size); 957 } 958 959 /** 960 * map_iommu: map the iommu's registers 961 * @iommu: the iommu to map 962 * @drhd: DMA remapping hardware definition structure 963 * 964 * Memory map the iommu's registers. Start w/ a single page, and 965 * possibly expand if that turns out to be insufficent. 966 */ 967 static int map_iommu(struct intel_iommu *iommu, struct dmar_drhd_unit *drhd) 968 { 969 u64 phys_addr = drhd->reg_base_addr; 970 int map_size, err=0; 971 972 iommu->reg_phys = phys_addr; 973 iommu->reg_size = drhd->reg_size; 974 975 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { 976 pr_err("Can't reserve memory\n"); 977 err = -EBUSY; 978 goto out; 979 } 980 981 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); 982 if (!iommu->reg) { 983 pr_err("Can't map the region\n"); 984 err = -ENOMEM; 985 goto release; 986 } 987 988 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); 989 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); 990 991 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { 992 err = -EINVAL; 993 warn_invalid_dmar(phys_addr, " returns all ones"); 994 goto unmap; 995 } 996 if (ecap_vcs(iommu->ecap)) 997 iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG); 998 999 /* the registers might be more than one page */ 1000 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), 1001 cap_max_fault_reg_offset(iommu->cap)); 1002 map_size = VTD_PAGE_ALIGN(map_size); 1003 if (map_size > iommu->reg_size) { 1004 iounmap(iommu->reg); 1005 release_mem_region(iommu->reg_phys, iommu->reg_size); 1006 iommu->reg_size = map_size; 1007 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, 1008 iommu->name)) { 1009 pr_err("Can't reserve memory\n"); 1010 err = -EBUSY; 1011 goto out; 1012 } 1013 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); 1014 if (!iommu->reg) { 1015 pr_err("Can't map the region\n"); 1016 err = -ENOMEM; 1017 goto release; 1018 } 1019 } 1020 1021 if (cap_ecmds(iommu->cap)) { 1022 int i; 1023 1024 for (i = 0; i < DMA_MAX_NUM_ECMDCAP; i++) { 1025 iommu->ecmdcap[i] = dmar_readq(iommu->reg + DMAR_ECCAP_REG + 1026 i * DMA_ECMD_REG_STEP); 1027 } 1028 } 1029 1030 err = 0; 1031 goto out; 1032 1033 unmap: 1034 iounmap(iommu->reg); 1035 release: 1036 release_mem_region(iommu->reg_phys, iommu->reg_size); 1037 out: 1038 return err; 1039 } 1040 1041 static int alloc_iommu(struct dmar_drhd_unit *drhd) 1042 { 1043 struct intel_iommu *iommu; 1044 u32 ver, sts; 1045 int agaw = -1; 1046 int msagaw = -1; 1047 int err; 1048 1049 if (!drhd->reg_base_addr) { 1050 warn_invalid_dmar(0, ""); 1051 return -EINVAL; 1052 } 1053 1054 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); 1055 if (!iommu) 1056 return -ENOMEM; 1057 1058 iommu->seq_id = ida_alloc_range(&dmar_seq_ids, 0, 1059 DMAR_UNITS_SUPPORTED - 1, GFP_KERNEL); 1060 if (iommu->seq_id < 0) { 1061 pr_err("Failed to allocate seq_id\n"); 1062 err = iommu->seq_id; 1063 goto error; 1064 } 1065 sprintf(iommu->name, "dmar%d", iommu->seq_id); 1066 1067 err = map_iommu(iommu, drhd); 1068 if (err) { 1069 pr_err("Failed to map %s\n", iommu->name); 1070 goto error_free_seq_id; 1071 } 1072 1073 err = -EINVAL; 1074 if (cap_sagaw(iommu->cap) == 0) { 1075 pr_info("%s: No supported address widths. Not attempting DMA translation.\n", 1076 iommu->name); 1077 drhd->ignored = 1; 1078 } 1079 1080 if (!drhd->ignored) { 1081 agaw = iommu_calculate_agaw(iommu); 1082 if (agaw < 0) { 1083 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", 1084 iommu->seq_id); 1085 drhd->ignored = 1; 1086 } 1087 } 1088 if (!drhd->ignored) { 1089 msagaw = iommu_calculate_max_sagaw(iommu); 1090 if (msagaw < 0) { 1091 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", 1092 iommu->seq_id); 1093 drhd->ignored = 1; 1094 agaw = -1; 1095 } 1096 } 1097 iommu->agaw = agaw; 1098 iommu->msagaw = msagaw; 1099 iommu->segment = drhd->segment; 1100 1101 iommu->node = NUMA_NO_NODE; 1102 1103 ver = readl(iommu->reg + DMAR_VER_REG); 1104 pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", 1105 iommu->name, 1106 (unsigned long long)drhd->reg_base_addr, 1107 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), 1108 (unsigned long long)iommu->cap, 1109 (unsigned long long)iommu->ecap); 1110 1111 /* Reflect status in gcmd */ 1112 sts = readl(iommu->reg + DMAR_GSTS_REG); 1113 if (sts & DMA_GSTS_IRES) 1114 iommu->gcmd |= DMA_GCMD_IRE; 1115 if (sts & DMA_GSTS_TES) 1116 iommu->gcmd |= DMA_GCMD_TE; 1117 if (sts & DMA_GSTS_QIES) 1118 iommu->gcmd |= DMA_GCMD_QIE; 1119 1120 if (alloc_iommu_pmu(iommu)) 1121 pr_debug("Cannot alloc PMU for iommu (seq_id = %d)\n", iommu->seq_id); 1122 1123 raw_spin_lock_init(&iommu->register_lock); 1124 1125 /* 1126 * A value of N in PSS field of eCap register indicates hardware 1127 * supports PASID field of N+1 bits. 1128 */ 1129 if (pasid_supported(iommu)) 1130 iommu->iommu.max_pasids = 2UL << ecap_pss(iommu->ecap); 1131 1132 /* 1133 * This is only for hotplug; at boot time intel_iommu_enabled won't 1134 * be set yet. When intel_iommu_init() runs, it registers the units 1135 * present at boot time, then sets intel_iommu_enabled. 1136 */ 1137 if (intel_iommu_enabled && !drhd->ignored) { 1138 err = iommu_device_sysfs_add(&iommu->iommu, NULL, 1139 intel_iommu_groups, 1140 "%s", iommu->name); 1141 if (err) 1142 goto err_unmap; 1143 1144 err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); 1145 if (err) 1146 goto err_sysfs; 1147 1148 iommu_pmu_register(iommu); 1149 } 1150 1151 drhd->iommu = iommu; 1152 iommu->drhd = drhd; 1153 1154 return 0; 1155 1156 err_sysfs: 1157 iommu_device_sysfs_remove(&iommu->iommu); 1158 err_unmap: 1159 free_iommu_pmu(iommu); 1160 unmap_iommu(iommu); 1161 error_free_seq_id: 1162 ida_free(&dmar_seq_ids, iommu->seq_id); 1163 error: 1164 kfree(iommu); 1165 return err; 1166 } 1167 1168 static void free_iommu(struct intel_iommu *iommu) 1169 { 1170 if (intel_iommu_enabled && !iommu->drhd->ignored) { 1171 iommu_pmu_unregister(iommu); 1172 iommu_device_unregister(&iommu->iommu); 1173 iommu_device_sysfs_remove(&iommu->iommu); 1174 } 1175 1176 free_iommu_pmu(iommu); 1177 1178 if (iommu->irq) { 1179 if (iommu->pr_irq) { 1180 free_irq(iommu->pr_irq, iommu); 1181 dmar_free_hwirq(iommu->pr_irq); 1182 iommu->pr_irq = 0; 1183 } 1184 free_irq(iommu->irq, iommu); 1185 dmar_free_hwirq(iommu->irq); 1186 iommu->irq = 0; 1187 } 1188 1189 if (iommu->qi) { 1190 free_page((unsigned long)iommu->qi->desc); 1191 kfree(iommu->qi->desc_status); 1192 kfree(iommu->qi); 1193 } 1194 1195 if (iommu->reg) 1196 unmap_iommu(iommu); 1197 1198 ida_free(&dmar_seq_ids, iommu->seq_id); 1199 kfree(iommu); 1200 } 1201 1202 /* 1203 * Reclaim all the submitted descriptors which have completed its work. 1204 */ 1205 static inline void reclaim_free_desc(struct q_inval *qi) 1206 { 1207 while (qi->desc_status[qi->free_tail] == QI_DONE || 1208 qi->desc_status[qi->free_tail] == QI_ABORT) { 1209 qi->desc_status[qi->free_tail] = QI_FREE; 1210 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; 1211 qi->free_cnt++; 1212 } 1213 } 1214 1215 static const char *qi_type_string(u8 type) 1216 { 1217 switch (type) { 1218 case QI_CC_TYPE: 1219 return "Context-cache Invalidation"; 1220 case QI_IOTLB_TYPE: 1221 return "IOTLB Invalidation"; 1222 case QI_DIOTLB_TYPE: 1223 return "Device-TLB Invalidation"; 1224 case QI_IEC_TYPE: 1225 return "Interrupt Entry Cache Invalidation"; 1226 case QI_IWD_TYPE: 1227 return "Invalidation Wait"; 1228 case QI_EIOTLB_TYPE: 1229 return "PASID-based IOTLB Invalidation"; 1230 case QI_PC_TYPE: 1231 return "PASID-cache Invalidation"; 1232 case QI_DEIOTLB_TYPE: 1233 return "PASID-based Device-TLB Invalidation"; 1234 case QI_PGRP_RESP_TYPE: 1235 return "Page Group Response"; 1236 default: 1237 return "UNKNOWN"; 1238 } 1239 } 1240 1241 static void qi_dump_fault(struct intel_iommu *iommu, u32 fault) 1242 { 1243 unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG); 1244 u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG); 1245 struct qi_desc *desc = iommu->qi->desc + head; 1246 1247 if (fault & DMA_FSTS_IQE) 1248 pr_err("VT-d detected Invalidation Queue Error: Reason %llx", 1249 DMAR_IQER_REG_IQEI(iqe_err)); 1250 if (fault & DMA_FSTS_ITE) 1251 pr_err("VT-d detected Invalidation Time-out Error: SID %llx", 1252 DMAR_IQER_REG_ITESID(iqe_err)); 1253 if (fault & DMA_FSTS_ICE) 1254 pr_err("VT-d detected Invalidation Completion Error: SID %llx", 1255 DMAR_IQER_REG_ICESID(iqe_err)); 1256 1257 pr_err("QI HEAD: %s qw0 = 0x%llx, qw1 = 0x%llx\n", 1258 qi_type_string(desc->qw0 & 0xf), 1259 (unsigned long long)desc->qw0, 1260 (unsigned long long)desc->qw1); 1261 1262 head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH; 1263 head <<= qi_shift(iommu); 1264 desc = iommu->qi->desc + head; 1265 1266 pr_err("QI PRIOR: %s qw0 = 0x%llx, qw1 = 0x%llx\n", 1267 qi_type_string(desc->qw0 & 0xf), 1268 (unsigned long long)desc->qw0, 1269 (unsigned long long)desc->qw1); 1270 } 1271 1272 static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index) 1273 { 1274 u32 fault; 1275 int head, tail; 1276 struct q_inval *qi = iommu->qi; 1277 int shift = qi_shift(iommu); 1278 1279 if (qi->desc_status[wait_index] == QI_ABORT) 1280 return -EAGAIN; 1281 1282 fault = readl(iommu->reg + DMAR_FSTS_REG); 1283 if (fault & (DMA_FSTS_IQE | DMA_FSTS_ITE | DMA_FSTS_ICE)) 1284 qi_dump_fault(iommu, fault); 1285 1286 /* 1287 * If IQE happens, the head points to the descriptor associated 1288 * with the error. No new descriptors are fetched until the IQE 1289 * is cleared. 1290 */ 1291 if (fault & DMA_FSTS_IQE) { 1292 head = readl(iommu->reg + DMAR_IQH_REG); 1293 if ((head >> shift) == index) { 1294 struct qi_desc *desc = qi->desc + head; 1295 1296 /* 1297 * desc->qw2 and desc->qw3 are either reserved or 1298 * used by software as private data. We won't print 1299 * out these two qw's for security consideration. 1300 */ 1301 memcpy(desc, qi->desc + (wait_index << shift), 1302 1 << shift); 1303 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); 1304 pr_info("Invalidation Queue Error (IQE) cleared\n"); 1305 return -EINVAL; 1306 } 1307 } 1308 1309 /* 1310 * If ITE happens, all pending wait_desc commands are aborted. 1311 * No new descriptors are fetched until the ITE is cleared. 1312 */ 1313 if (fault & DMA_FSTS_ITE) { 1314 head = readl(iommu->reg + DMAR_IQH_REG); 1315 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; 1316 head |= 1; 1317 tail = readl(iommu->reg + DMAR_IQT_REG); 1318 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; 1319 1320 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); 1321 pr_info("Invalidation Time-out Error (ITE) cleared\n"); 1322 1323 do { 1324 if (qi->desc_status[head] == QI_IN_USE) 1325 qi->desc_status[head] = QI_ABORT; 1326 head = (head - 2 + QI_LENGTH) % QI_LENGTH; 1327 } while (head != tail); 1328 1329 if (qi->desc_status[wait_index] == QI_ABORT) 1330 return -EAGAIN; 1331 } 1332 1333 if (fault & DMA_FSTS_ICE) { 1334 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); 1335 pr_info("Invalidation Completion Error (ICE) cleared\n"); 1336 } 1337 1338 return 0; 1339 } 1340 1341 /* 1342 * Function to submit invalidation descriptors of all types to the queued 1343 * invalidation interface(QI). Multiple descriptors can be submitted at a 1344 * time, a wait descriptor will be appended to each submission to ensure 1345 * hardware has completed the invalidation before return. Wait descriptors 1346 * can be part of the submission but it will not be polled for completion. 1347 */ 1348 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, 1349 unsigned int count, unsigned long options) 1350 { 1351 struct q_inval *qi = iommu->qi; 1352 s64 devtlb_start_ktime = 0; 1353 s64 iotlb_start_ktime = 0; 1354 s64 iec_start_ktime = 0; 1355 struct qi_desc wait_desc; 1356 int wait_index, index; 1357 unsigned long flags; 1358 int offset, shift; 1359 int rc, i; 1360 u64 type; 1361 1362 if (!qi) 1363 return 0; 1364 1365 type = desc->qw0 & GENMASK_ULL(3, 0); 1366 1367 if ((type == QI_IOTLB_TYPE || type == QI_EIOTLB_TYPE) && 1368 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IOTLB)) 1369 iotlb_start_ktime = ktime_to_ns(ktime_get()); 1370 1371 if ((type == QI_DIOTLB_TYPE || type == QI_DEIOTLB_TYPE) && 1372 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_DEVTLB)) 1373 devtlb_start_ktime = ktime_to_ns(ktime_get()); 1374 1375 if (type == QI_IEC_TYPE && 1376 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IEC)) 1377 iec_start_ktime = ktime_to_ns(ktime_get()); 1378 1379 restart: 1380 rc = 0; 1381 1382 raw_spin_lock_irqsave(&qi->q_lock, flags); 1383 /* 1384 * Check if we have enough empty slots in the queue to submit, 1385 * the calculation is based on: 1386 * # of desc + 1 wait desc + 1 space between head and tail 1387 */ 1388 while (qi->free_cnt < count + 2) { 1389 raw_spin_unlock_irqrestore(&qi->q_lock, flags); 1390 cpu_relax(); 1391 raw_spin_lock_irqsave(&qi->q_lock, flags); 1392 } 1393 1394 index = qi->free_head; 1395 wait_index = (index + count) % QI_LENGTH; 1396 shift = qi_shift(iommu); 1397 1398 for (i = 0; i < count; i++) { 1399 offset = ((index + i) % QI_LENGTH) << shift; 1400 memcpy(qi->desc + offset, &desc[i], 1 << shift); 1401 qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE; 1402 trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1, 1403 desc[i].qw2, desc[i].qw3); 1404 } 1405 qi->desc_status[wait_index] = QI_IN_USE; 1406 1407 wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) | 1408 QI_IWD_STATUS_WRITE | QI_IWD_TYPE; 1409 if (options & QI_OPT_WAIT_DRAIN) 1410 wait_desc.qw0 |= QI_IWD_PRQ_DRAIN; 1411 wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]); 1412 wait_desc.qw2 = 0; 1413 wait_desc.qw3 = 0; 1414 1415 offset = wait_index << shift; 1416 memcpy(qi->desc + offset, &wait_desc, 1 << shift); 1417 1418 qi->free_head = (qi->free_head + count + 1) % QI_LENGTH; 1419 qi->free_cnt -= count + 1; 1420 1421 /* 1422 * update the HW tail register indicating the presence of 1423 * new descriptors. 1424 */ 1425 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); 1426 1427 while (qi->desc_status[wait_index] != QI_DONE) { 1428 /* 1429 * We will leave the interrupts disabled, to prevent interrupt 1430 * context to queue another cmd while a cmd is already submitted 1431 * and waiting for completion on this cpu. This is to avoid 1432 * a deadlock where the interrupt context can wait indefinitely 1433 * for free slots in the queue. 1434 */ 1435 rc = qi_check_fault(iommu, index, wait_index); 1436 if (rc) 1437 break; 1438 1439 raw_spin_unlock(&qi->q_lock); 1440 cpu_relax(); 1441 raw_spin_lock(&qi->q_lock); 1442 } 1443 1444 for (i = 0; i < count; i++) 1445 qi->desc_status[(index + i) % QI_LENGTH] = QI_DONE; 1446 1447 reclaim_free_desc(qi); 1448 raw_spin_unlock_irqrestore(&qi->q_lock, flags); 1449 1450 if (rc == -EAGAIN) 1451 goto restart; 1452 1453 if (iotlb_start_ktime) 1454 dmar_latency_update(iommu, DMAR_LATENCY_INV_IOTLB, 1455 ktime_to_ns(ktime_get()) - iotlb_start_ktime); 1456 1457 if (devtlb_start_ktime) 1458 dmar_latency_update(iommu, DMAR_LATENCY_INV_DEVTLB, 1459 ktime_to_ns(ktime_get()) - devtlb_start_ktime); 1460 1461 if (iec_start_ktime) 1462 dmar_latency_update(iommu, DMAR_LATENCY_INV_IEC, 1463 ktime_to_ns(ktime_get()) - iec_start_ktime); 1464 1465 return rc; 1466 } 1467 1468 /* 1469 * Flush the global interrupt entry cache. 1470 */ 1471 void qi_global_iec(struct intel_iommu *iommu) 1472 { 1473 struct qi_desc desc; 1474 1475 desc.qw0 = QI_IEC_TYPE; 1476 desc.qw1 = 0; 1477 desc.qw2 = 0; 1478 desc.qw3 = 0; 1479 1480 /* should never fail */ 1481 qi_submit_sync(iommu, &desc, 1, 0); 1482 } 1483 1484 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, 1485 u64 type) 1486 { 1487 struct qi_desc desc; 1488 1489 desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did) 1490 | QI_CC_GRAN(type) | QI_CC_TYPE; 1491 desc.qw1 = 0; 1492 desc.qw2 = 0; 1493 desc.qw3 = 0; 1494 1495 qi_submit_sync(iommu, &desc, 1, 0); 1496 } 1497 1498 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, 1499 unsigned int size_order, u64 type) 1500 { 1501 u8 dw = 0, dr = 0; 1502 1503 struct qi_desc desc; 1504 int ih = 0; 1505 1506 if (cap_write_drain(iommu->cap)) 1507 dw = 1; 1508 1509 if (cap_read_drain(iommu->cap)) 1510 dr = 1; 1511 1512 desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw) 1513 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE; 1514 desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih) 1515 | QI_IOTLB_AM(size_order); 1516 desc.qw2 = 0; 1517 desc.qw3 = 0; 1518 1519 qi_submit_sync(iommu, &desc, 1, 0); 1520 } 1521 1522 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, 1523 u16 qdep, u64 addr, unsigned mask) 1524 { 1525 struct qi_desc desc; 1526 1527 if (mask) { 1528 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; 1529 desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE; 1530 } else 1531 desc.qw1 = QI_DEV_IOTLB_ADDR(addr); 1532 1533 if (qdep >= QI_DEV_IOTLB_MAX_INVS) 1534 qdep = 0; 1535 1536 desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) | 1537 QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid); 1538 desc.qw2 = 0; 1539 desc.qw3 = 0; 1540 1541 qi_submit_sync(iommu, &desc, 1, 0); 1542 } 1543 1544 /* PASID-based IOTLB invalidation */ 1545 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, 1546 unsigned long npages, bool ih) 1547 { 1548 struct qi_desc desc = {.qw2 = 0, .qw3 = 0}; 1549 1550 /* 1551 * npages == -1 means a PASID-selective invalidation, otherwise, 1552 * a positive value for Page-selective-within-PASID invalidation. 1553 * 0 is not a valid input. 1554 */ 1555 if (WARN_ON(!npages)) { 1556 pr_err("Invalid input npages = %ld\n", npages); 1557 return; 1558 } 1559 1560 if (npages == -1) { 1561 desc.qw0 = QI_EIOTLB_PASID(pasid) | 1562 QI_EIOTLB_DID(did) | 1563 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | 1564 QI_EIOTLB_TYPE; 1565 desc.qw1 = 0; 1566 } else { 1567 int mask = ilog2(__roundup_pow_of_two(npages)); 1568 unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask)); 1569 1570 if (WARN_ON_ONCE(!IS_ALIGNED(addr, align))) 1571 addr = ALIGN_DOWN(addr, align); 1572 1573 desc.qw0 = QI_EIOTLB_PASID(pasid) | 1574 QI_EIOTLB_DID(did) | 1575 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | 1576 QI_EIOTLB_TYPE; 1577 desc.qw1 = QI_EIOTLB_ADDR(addr) | 1578 QI_EIOTLB_IH(ih) | 1579 QI_EIOTLB_AM(mask); 1580 } 1581 1582 qi_submit_sync(iommu, &desc, 1, 0); 1583 } 1584 1585 /* PASID-based device IOTLB Invalidate */ 1586 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, 1587 u32 pasid, u16 qdep, u64 addr, unsigned int size_order) 1588 { 1589 unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1); 1590 struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; 1591 1592 desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) | 1593 QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE | 1594 QI_DEV_IOTLB_PFSID(pfsid); 1595 1596 /* 1597 * If S bit is 0, we only flush a single page. If S bit is set, 1598 * The least significant zero bit indicates the invalidation address 1599 * range. VT-d spec 6.5.2.6. 1600 * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB. 1601 * size order = 0 is PAGE_SIZE 4KB 1602 * Max Invs Pending (MIP) is set to 0 for now until we have DIT in 1603 * ECAP. 1604 */ 1605 if (!IS_ALIGNED(addr, VTD_PAGE_SIZE << size_order)) 1606 pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n", 1607 addr, size_order); 1608 1609 /* Take page address */ 1610 desc.qw1 = QI_DEV_EIOTLB_ADDR(addr); 1611 1612 if (size_order) { 1613 /* 1614 * Existing 0s in address below size_order may be the least 1615 * significant bit, we must set them to 1s to avoid having 1616 * smaller size than desired. 1617 */ 1618 desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1, 1619 VTD_PAGE_SHIFT); 1620 /* Clear size_order bit to indicate size */ 1621 desc.qw1 &= ~mask; 1622 /* Set the S bit to indicate flushing more than 1 page */ 1623 desc.qw1 |= QI_DEV_EIOTLB_SIZE; 1624 } 1625 1626 qi_submit_sync(iommu, &desc, 1, 0); 1627 } 1628 1629 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, 1630 u64 granu, u32 pasid) 1631 { 1632 struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; 1633 1634 desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) | 1635 QI_PC_GRAN(granu) | QI_PC_TYPE; 1636 qi_submit_sync(iommu, &desc, 1, 0); 1637 } 1638 1639 /* 1640 * Disable Queued Invalidation interface. 1641 */ 1642 void dmar_disable_qi(struct intel_iommu *iommu) 1643 { 1644 unsigned long flags; 1645 u32 sts; 1646 cycles_t start_time = get_cycles(); 1647 1648 if (!ecap_qis(iommu->ecap)) 1649 return; 1650 1651 raw_spin_lock_irqsave(&iommu->register_lock, flags); 1652 1653 sts = readl(iommu->reg + DMAR_GSTS_REG); 1654 if (!(sts & DMA_GSTS_QIES)) 1655 goto end; 1656 1657 /* 1658 * Give a chance to HW to complete the pending invalidation requests. 1659 */ 1660 while ((readl(iommu->reg + DMAR_IQT_REG) != 1661 readl(iommu->reg + DMAR_IQH_REG)) && 1662 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) 1663 cpu_relax(); 1664 1665 iommu->gcmd &= ~DMA_GCMD_QIE; 1666 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); 1667 1668 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, 1669 !(sts & DMA_GSTS_QIES), sts); 1670 end: 1671 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); 1672 } 1673 1674 /* 1675 * Enable queued invalidation. 1676 */ 1677 static void __dmar_enable_qi(struct intel_iommu *iommu) 1678 { 1679 u32 sts; 1680 unsigned long flags; 1681 struct q_inval *qi = iommu->qi; 1682 u64 val = virt_to_phys(qi->desc); 1683 1684 qi->free_head = qi->free_tail = 0; 1685 qi->free_cnt = QI_LENGTH; 1686 1687 /* 1688 * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability 1689 * is present. 1690 */ 1691 if (ecap_smts(iommu->ecap)) 1692 val |= (1 << 11) | 1; 1693 1694 raw_spin_lock_irqsave(&iommu->register_lock, flags); 1695 1696 /* write zero to the tail reg */ 1697 writel(0, iommu->reg + DMAR_IQT_REG); 1698 1699 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); 1700 1701 iommu->gcmd |= DMA_GCMD_QIE; 1702 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); 1703 1704 /* Make sure hardware complete it */ 1705 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); 1706 1707 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); 1708 } 1709 1710 /* 1711 * Enable Queued Invalidation interface. This is a must to support 1712 * interrupt-remapping. Also used by DMA-remapping, which replaces 1713 * register based IOTLB invalidation. 1714 */ 1715 int dmar_enable_qi(struct intel_iommu *iommu) 1716 { 1717 struct q_inval *qi; 1718 struct page *desc_page; 1719 1720 if (!ecap_qis(iommu->ecap)) 1721 return -ENOENT; 1722 1723 /* 1724 * queued invalidation is already setup and enabled. 1725 */ 1726 if (iommu->qi) 1727 return 0; 1728 1729 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); 1730 if (!iommu->qi) 1731 return -ENOMEM; 1732 1733 qi = iommu->qi; 1734 1735 /* 1736 * Need two pages to accommodate 256 descriptors of 256 bits each 1737 * if the remapping hardware supports scalable mode translation. 1738 */ 1739 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 1740 !!ecap_smts(iommu->ecap)); 1741 if (!desc_page) { 1742 kfree(qi); 1743 iommu->qi = NULL; 1744 return -ENOMEM; 1745 } 1746 1747 qi->desc = page_address(desc_page); 1748 1749 qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC); 1750 if (!qi->desc_status) { 1751 free_page((unsigned long) qi->desc); 1752 kfree(qi); 1753 iommu->qi = NULL; 1754 return -ENOMEM; 1755 } 1756 1757 raw_spin_lock_init(&qi->q_lock); 1758 1759 __dmar_enable_qi(iommu); 1760 1761 return 0; 1762 } 1763 1764 /* iommu interrupt handling. Most stuff are MSI-like. */ 1765 1766 enum faulttype { 1767 DMA_REMAP, 1768 INTR_REMAP, 1769 UNKNOWN, 1770 }; 1771 1772 static const char *dma_remap_fault_reasons[] = 1773 { 1774 "Software", 1775 "Present bit in root entry is clear", 1776 "Present bit in context entry is clear", 1777 "Invalid context entry", 1778 "Access beyond MGAW", 1779 "PTE Write access is not set", 1780 "PTE Read access is not set", 1781 "Next page table ptr is invalid", 1782 "Root table address invalid", 1783 "Context table ptr is invalid", 1784 "non-zero reserved fields in RTP", 1785 "non-zero reserved fields in CTP", 1786 "non-zero reserved fields in PTE", 1787 "PCE for translation request specifies blocking", 1788 }; 1789 1790 static const char * const dma_remap_sm_fault_reasons[] = { 1791 "SM: Invalid Root Table Address", 1792 "SM: TTM 0 for request with PASID", 1793 "SM: TTM 0 for page group request", 1794 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */ 1795 "SM: Error attempting to access Root Entry", 1796 "SM: Present bit in Root Entry is clear", 1797 "SM: Non-zero reserved field set in Root Entry", 1798 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */ 1799 "SM: Error attempting to access Context Entry", 1800 "SM: Present bit in Context Entry is clear", 1801 "SM: Non-zero reserved field set in the Context Entry", 1802 "SM: Invalid Context Entry", 1803 "SM: DTE field in Context Entry is clear", 1804 "SM: PASID Enable field in Context Entry is clear", 1805 "SM: PASID is larger than the max in Context Entry", 1806 "SM: PRE field in Context-Entry is clear", 1807 "SM: RID_PASID field error in Context-Entry", 1808 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */ 1809 "SM: Error attempting to access the PASID Directory Entry", 1810 "SM: Present bit in Directory Entry is clear", 1811 "SM: Non-zero reserved field set in PASID Directory Entry", 1812 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */ 1813 "SM: Error attempting to access PASID Table Entry", 1814 "SM: Present bit in PASID Table Entry is clear", 1815 "SM: Non-zero reserved field set in PASID Table Entry", 1816 "SM: Invalid Scalable-Mode PASID Table Entry", 1817 "SM: ERE field is clear in PASID Table Entry", 1818 "SM: SRE field is clear in PASID Table Entry", 1819 "Unknown", "Unknown",/* 0x5E-0x5F */ 1820 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */ 1821 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */ 1822 "SM: Error attempting to access first-level paging entry", 1823 "SM: Present bit in first-level paging entry is clear", 1824 "SM: Non-zero reserved field set in first-level paging entry", 1825 "SM: Error attempting to access FL-PML4 entry", 1826 "SM: First-level entry address beyond MGAW in Nested translation", 1827 "SM: Read permission error in FL-PML4 entry in Nested translation", 1828 "SM: Read permission error in first-level paging entry in Nested translation", 1829 "SM: Write permission error in first-level paging entry in Nested translation", 1830 "SM: Error attempting to access second-level paging entry", 1831 "SM: Read/Write permission error in second-level paging entry", 1832 "SM: Non-zero reserved field set in second-level paging entry", 1833 "SM: Invalid second-level page table pointer", 1834 "SM: A/D bit update needed in second-level entry when set up in no snoop", 1835 "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */ 1836 "SM: Address in first-level translation is not canonical", 1837 "SM: U/S set 0 for first-level translation with user privilege", 1838 "SM: No execute permission for request with PASID and ER=1", 1839 "SM: Address beyond the DMA hardware max", 1840 "SM: Second-level entry address beyond the max", 1841 "SM: No write permission for Write/AtomicOp request", 1842 "SM: No read permission for Read/AtomicOp request", 1843 "SM: Invalid address-interrupt address", 1844 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */ 1845 "SM: A/D bit update needed in first-level entry when set up in no snoop", 1846 }; 1847 1848 static const char *irq_remap_fault_reasons[] = 1849 { 1850 "Detected reserved fields in the decoded interrupt-remapped request", 1851 "Interrupt index exceeded the interrupt-remapping table size", 1852 "Present field in the IRTE entry is clear", 1853 "Error accessing interrupt-remapping table pointed by IRTA_REG", 1854 "Detected reserved fields in the IRTE entry", 1855 "Blocked a compatibility format interrupt request", 1856 "Blocked an interrupt request due to source-id verification failure", 1857 }; 1858 1859 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type) 1860 { 1861 if (fault_reason >= 0x20 && (fault_reason - 0x20 < 1862 ARRAY_SIZE(irq_remap_fault_reasons))) { 1863 *fault_type = INTR_REMAP; 1864 return irq_remap_fault_reasons[fault_reason - 0x20]; 1865 } else if (fault_reason >= 0x30 && (fault_reason - 0x30 < 1866 ARRAY_SIZE(dma_remap_sm_fault_reasons))) { 1867 *fault_type = DMA_REMAP; 1868 return dma_remap_sm_fault_reasons[fault_reason - 0x30]; 1869 } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) { 1870 *fault_type = DMA_REMAP; 1871 return dma_remap_fault_reasons[fault_reason]; 1872 } else { 1873 *fault_type = UNKNOWN; 1874 return "Unknown"; 1875 } 1876 } 1877 1878 1879 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq) 1880 { 1881 if (iommu->irq == irq) 1882 return DMAR_FECTL_REG; 1883 else if (iommu->pr_irq == irq) 1884 return DMAR_PECTL_REG; 1885 else if (iommu->perf_irq == irq) 1886 return DMAR_PERFINTRCTL_REG; 1887 else 1888 BUG(); 1889 } 1890 1891 void dmar_msi_unmask(struct irq_data *data) 1892 { 1893 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); 1894 int reg = dmar_msi_reg(iommu, data->irq); 1895 unsigned long flag; 1896 1897 /* unmask it */ 1898 raw_spin_lock_irqsave(&iommu->register_lock, flag); 1899 writel(0, iommu->reg + reg); 1900 /* Read a reg to force flush the post write */ 1901 readl(iommu->reg + reg); 1902 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); 1903 } 1904 1905 void dmar_msi_mask(struct irq_data *data) 1906 { 1907 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); 1908 int reg = dmar_msi_reg(iommu, data->irq); 1909 unsigned long flag; 1910 1911 /* mask it */ 1912 raw_spin_lock_irqsave(&iommu->register_lock, flag); 1913 writel(DMA_FECTL_IM, iommu->reg + reg); 1914 /* Read a reg to force flush the post write */ 1915 readl(iommu->reg + reg); 1916 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); 1917 } 1918 1919 void dmar_msi_write(int irq, struct msi_msg *msg) 1920 { 1921 struct intel_iommu *iommu = irq_get_handler_data(irq); 1922 int reg = dmar_msi_reg(iommu, irq); 1923 unsigned long flag; 1924 1925 raw_spin_lock_irqsave(&iommu->register_lock, flag); 1926 writel(msg->data, iommu->reg + reg + 4); 1927 writel(msg->address_lo, iommu->reg + reg + 8); 1928 writel(msg->address_hi, iommu->reg + reg + 12); 1929 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); 1930 } 1931 1932 void dmar_msi_read(int irq, struct msi_msg *msg) 1933 { 1934 struct intel_iommu *iommu = irq_get_handler_data(irq); 1935 int reg = dmar_msi_reg(iommu, irq); 1936 unsigned long flag; 1937 1938 raw_spin_lock_irqsave(&iommu->register_lock, flag); 1939 msg->data = readl(iommu->reg + reg + 4); 1940 msg->address_lo = readl(iommu->reg + reg + 8); 1941 msg->address_hi = readl(iommu->reg + reg + 12); 1942 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); 1943 } 1944 1945 static int dmar_fault_do_one(struct intel_iommu *iommu, int type, 1946 u8 fault_reason, u32 pasid, u16 source_id, 1947 unsigned long long addr) 1948 { 1949 const char *reason; 1950 int fault_type; 1951 1952 reason = dmar_get_fault_reason(fault_reason, &fault_type); 1953 1954 if (fault_type == INTR_REMAP) { 1955 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index 0x%llx [fault reason 0x%02x] %s\n", 1956 source_id >> 8, PCI_SLOT(source_id & 0xFF), 1957 PCI_FUNC(source_id & 0xFF), addr >> 48, 1958 fault_reason, reason); 1959 1960 return 0; 1961 } 1962 1963 if (pasid == INVALID_IOASID) 1964 pr_err("[%s NO_PASID] Request device [%02x:%02x.%d] fault addr 0x%llx [fault reason 0x%02x] %s\n", 1965 type ? "DMA Read" : "DMA Write", 1966 source_id >> 8, PCI_SLOT(source_id & 0xFF), 1967 PCI_FUNC(source_id & 0xFF), addr, 1968 fault_reason, reason); 1969 else 1970 pr_err("[%s PASID 0x%x] Request device [%02x:%02x.%d] fault addr 0x%llx [fault reason 0x%02x] %s\n", 1971 type ? "DMA Read" : "DMA Write", pasid, 1972 source_id >> 8, PCI_SLOT(source_id & 0xFF), 1973 PCI_FUNC(source_id & 0xFF), addr, 1974 fault_reason, reason); 1975 1976 dmar_fault_dump_ptes(iommu, source_id, addr, pasid); 1977 1978 return 0; 1979 } 1980 1981 #define PRIMARY_FAULT_REG_LEN (16) 1982 irqreturn_t dmar_fault(int irq, void *dev_id) 1983 { 1984 struct intel_iommu *iommu = dev_id; 1985 int reg, fault_index; 1986 u32 fault_status; 1987 unsigned long flag; 1988 static DEFINE_RATELIMIT_STATE(rs, 1989 DEFAULT_RATELIMIT_INTERVAL, 1990 DEFAULT_RATELIMIT_BURST); 1991 1992 raw_spin_lock_irqsave(&iommu->register_lock, flag); 1993 fault_status = readl(iommu->reg + DMAR_FSTS_REG); 1994 if (fault_status && __ratelimit(&rs)) 1995 pr_err("DRHD: handling fault status reg %x\n", fault_status); 1996 1997 /* TBD: ignore advanced fault log currently */ 1998 if (!(fault_status & DMA_FSTS_PPF)) 1999 goto unlock_exit; 2000 2001 fault_index = dma_fsts_fault_record_index(fault_status); 2002 reg = cap_fault_reg_offset(iommu->cap); 2003 while (1) { 2004 /* Disable printing, simply clear the fault when ratelimited */ 2005 bool ratelimited = !__ratelimit(&rs); 2006 u8 fault_reason; 2007 u16 source_id; 2008 u64 guest_addr; 2009 u32 pasid; 2010 int type; 2011 u32 data; 2012 bool pasid_present; 2013 2014 /* highest 32 bits */ 2015 data = readl(iommu->reg + reg + 2016 fault_index * PRIMARY_FAULT_REG_LEN + 12); 2017 if (!(data & DMA_FRCD_F)) 2018 break; 2019 2020 if (!ratelimited) { 2021 fault_reason = dma_frcd_fault_reason(data); 2022 type = dma_frcd_type(data); 2023 2024 pasid = dma_frcd_pasid_value(data); 2025 data = readl(iommu->reg + reg + 2026 fault_index * PRIMARY_FAULT_REG_LEN + 8); 2027 source_id = dma_frcd_source_id(data); 2028 2029 pasid_present = dma_frcd_pasid_present(data); 2030 guest_addr = dmar_readq(iommu->reg + reg + 2031 fault_index * PRIMARY_FAULT_REG_LEN); 2032 guest_addr = dma_frcd_page_addr(guest_addr); 2033 } 2034 2035 /* clear the fault */ 2036 writel(DMA_FRCD_F, iommu->reg + reg + 2037 fault_index * PRIMARY_FAULT_REG_LEN + 12); 2038 2039 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); 2040 2041 if (!ratelimited) 2042 /* Using pasid -1 if pasid is not present */ 2043 dmar_fault_do_one(iommu, type, fault_reason, 2044 pasid_present ? pasid : INVALID_IOASID, 2045 source_id, guest_addr); 2046 2047 fault_index++; 2048 if (fault_index >= cap_num_fault_regs(iommu->cap)) 2049 fault_index = 0; 2050 raw_spin_lock_irqsave(&iommu->register_lock, flag); 2051 } 2052 2053 writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO, 2054 iommu->reg + DMAR_FSTS_REG); 2055 2056 unlock_exit: 2057 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); 2058 return IRQ_HANDLED; 2059 } 2060 2061 int dmar_set_interrupt(struct intel_iommu *iommu) 2062 { 2063 int irq, ret; 2064 2065 /* 2066 * Check if the fault interrupt is already initialized. 2067 */ 2068 if (iommu->irq) 2069 return 0; 2070 2071 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); 2072 if (irq > 0) { 2073 iommu->irq = irq; 2074 } else { 2075 pr_err("No free IRQ vectors\n"); 2076 return -EINVAL; 2077 } 2078 2079 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); 2080 if (ret) 2081 pr_err("Can't request irq\n"); 2082 return ret; 2083 } 2084 2085 int __init enable_drhd_fault_handling(void) 2086 { 2087 struct dmar_drhd_unit *drhd; 2088 struct intel_iommu *iommu; 2089 2090 /* 2091 * Enable fault control interrupt. 2092 */ 2093 for_each_iommu(iommu, drhd) { 2094 u32 fault_status; 2095 int ret = dmar_set_interrupt(iommu); 2096 2097 if (ret) { 2098 pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n", 2099 (unsigned long long)drhd->reg_base_addr, ret); 2100 return -1; 2101 } 2102 2103 /* 2104 * Clear any previous faults. 2105 */ 2106 dmar_fault(iommu->irq, iommu); 2107 fault_status = readl(iommu->reg + DMAR_FSTS_REG); 2108 writel(fault_status, iommu->reg + DMAR_FSTS_REG); 2109 } 2110 2111 return 0; 2112 } 2113 2114 /* 2115 * Re-enable Queued Invalidation interface. 2116 */ 2117 int dmar_reenable_qi(struct intel_iommu *iommu) 2118 { 2119 if (!ecap_qis(iommu->ecap)) 2120 return -ENOENT; 2121 2122 if (!iommu->qi) 2123 return -ENOENT; 2124 2125 /* 2126 * First disable queued invalidation. 2127 */ 2128 dmar_disable_qi(iommu); 2129 /* 2130 * Then enable queued invalidation again. Since there is no pending 2131 * invalidation requests now, it's safe to re-enable queued 2132 * invalidation. 2133 */ 2134 __dmar_enable_qi(iommu); 2135 2136 return 0; 2137 } 2138 2139 /* 2140 * Check interrupt remapping support in DMAR table description. 2141 */ 2142 int __init dmar_ir_support(void) 2143 { 2144 struct acpi_table_dmar *dmar; 2145 dmar = (struct acpi_table_dmar *)dmar_tbl; 2146 if (!dmar) 2147 return 0; 2148 return dmar->flags & 0x1; 2149 } 2150 2151 /* Check whether DMAR units are in use */ 2152 static inline bool dmar_in_use(void) 2153 { 2154 return irq_remapping_enabled || intel_iommu_enabled; 2155 } 2156 2157 static int __init dmar_free_unused_resources(void) 2158 { 2159 struct dmar_drhd_unit *dmaru, *dmaru_n; 2160 2161 if (dmar_in_use()) 2162 return 0; 2163 2164 if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units)) 2165 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb); 2166 2167 down_write(&dmar_global_lock); 2168 list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) { 2169 list_del(&dmaru->list); 2170 dmar_free_drhd(dmaru); 2171 } 2172 up_write(&dmar_global_lock); 2173 2174 return 0; 2175 } 2176 2177 late_initcall(dmar_free_unused_resources); 2178 2179 /* 2180 * DMAR Hotplug Support 2181 * For more details, please refer to Intel(R) Virtualization Technology 2182 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8 2183 * "Remapping Hardware Unit Hot Plug". 2184 */ 2185 static guid_t dmar_hp_guid = 2186 GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B, 2187 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF); 2188 2189 /* 2190 * Currently there's only one revision and BIOS will not check the revision id, 2191 * so use 0 for safety. 2192 */ 2193 #define DMAR_DSM_REV_ID 0 2194 #define DMAR_DSM_FUNC_DRHD 1 2195 #define DMAR_DSM_FUNC_ATSR 2 2196 #define DMAR_DSM_FUNC_RHSA 3 2197 #define DMAR_DSM_FUNC_SATC 4 2198 2199 static inline bool dmar_detect_dsm(acpi_handle handle, int func) 2200 { 2201 return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func); 2202 } 2203 2204 static int dmar_walk_dsm_resource(acpi_handle handle, int func, 2205 dmar_res_handler_t handler, void *arg) 2206 { 2207 int ret = -ENODEV; 2208 union acpi_object *obj; 2209 struct acpi_dmar_header *start; 2210 struct dmar_res_callback callback; 2211 static int res_type[] = { 2212 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT, 2213 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS, 2214 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY, 2215 [DMAR_DSM_FUNC_SATC] = ACPI_DMAR_TYPE_SATC, 2216 }; 2217 2218 if (!dmar_detect_dsm(handle, func)) 2219 return 0; 2220 2221 obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 2222 func, NULL, ACPI_TYPE_BUFFER); 2223 if (!obj) 2224 return -ENODEV; 2225 2226 memset(&callback, 0, sizeof(callback)); 2227 callback.cb[res_type[func]] = handler; 2228 callback.arg[res_type[func]] = arg; 2229 start = (struct acpi_dmar_header *)obj->buffer.pointer; 2230 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback); 2231 2232 ACPI_FREE(obj); 2233 2234 return ret; 2235 } 2236 2237 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg) 2238 { 2239 int ret; 2240 struct dmar_drhd_unit *dmaru; 2241 2242 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); 2243 if (!dmaru) 2244 return -ENODEV; 2245 2246 ret = dmar_ir_hotplug(dmaru, true); 2247 if (ret == 0) 2248 ret = dmar_iommu_hotplug(dmaru, true); 2249 2250 return ret; 2251 } 2252 2253 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg) 2254 { 2255 int i, ret; 2256 struct device *dev; 2257 struct dmar_drhd_unit *dmaru; 2258 2259 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); 2260 if (!dmaru) 2261 return 0; 2262 2263 /* 2264 * All PCI devices managed by this unit should have been destroyed. 2265 */ 2266 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) { 2267 for_each_active_dev_scope(dmaru->devices, 2268 dmaru->devices_cnt, i, dev) 2269 return -EBUSY; 2270 } 2271 2272 ret = dmar_ir_hotplug(dmaru, false); 2273 if (ret == 0) 2274 ret = dmar_iommu_hotplug(dmaru, false); 2275 2276 return ret; 2277 } 2278 2279 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg) 2280 { 2281 struct dmar_drhd_unit *dmaru; 2282 2283 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); 2284 if (dmaru) { 2285 list_del_rcu(&dmaru->list); 2286 synchronize_rcu(); 2287 dmar_free_drhd(dmaru); 2288 } 2289 2290 return 0; 2291 } 2292 2293 static int dmar_hotplug_insert(acpi_handle handle) 2294 { 2295 int ret; 2296 int drhd_count = 0; 2297 2298 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, 2299 &dmar_validate_one_drhd, (void *)1); 2300 if (ret) 2301 goto out; 2302 2303 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, 2304 &dmar_parse_one_drhd, (void *)&drhd_count); 2305 if (ret == 0 && drhd_count == 0) { 2306 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n"); 2307 goto out; 2308 } else if (ret) { 2309 goto release_drhd; 2310 } 2311 2312 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA, 2313 &dmar_parse_one_rhsa, NULL); 2314 if (ret) 2315 goto release_drhd; 2316 2317 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, 2318 &dmar_parse_one_atsr, NULL); 2319 if (ret) 2320 goto release_atsr; 2321 2322 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, 2323 &dmar_hp_add_drhd, NULL); 2324 if (!ret) 2325 return 0; 2326 2327 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, 2328 &dmar_hp_remove_drhd, NULL); 2329 release_atsr: 2330 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, 2331 &dmar_release_one_atsr, NULL); 2332 release_drhd: 2333 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, 2334 &dmar_hp_release_drhd, NULL); 2335 out: 2336 return ret; 2337 } 2338 2339 static int dmar_hotplug_remove(acpi_handle handle) 2340 { 2341 int ret; 2342 2343 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, 2344 &dmar_check_one_atsr, NULL); 2345 if (ret) 2346 return ret; 2347 2348 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, 2349 &dmar_hp_remove_drhd, NULL); 2350 if (ret == 0) { 2351 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, 2352 &dmar_release_one_atsr, NULL)); 2353 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, 2354 &dmar_hp_release_drhd, NULL)); 2355 } else { 2356 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, 2357 &dmar_hp_add_drhd, NULL); 2358 } 2359 2360 return ret; 2361 } 2362 2363 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl, 2364 void *context, void **retval) 2365 { 2366 acpi_handle *phdl = retval; 2367 2368 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { 2369 *phdl = handle; 2370 return AE_CTRL_TERMINATE; 2371 } 2372 2373 return AE_OK; 2374 } 2375 2376 static int dmar_device_hotplug(acpi_handle handle, bool insert) 2377 { 2378 int ret; 2379 acpi_handle tmp = NULL; 2380 acpi_status status; 2381 2382 if (!dmar_in_use()) 2383 return 0; 2384 2385 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { 2386 tmp = handle; 2387 } else { 2388 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 2389 ACPI_UINT32_MAX, 2390 dmar_get_dsm_handle, 2391 NULL, NULL, &tmp); 2392 if (ACPI_FAILURE(status)) { 2393 pr_warn("Failed to locate _DSM method.\n"); 2394 return -ENXIO; 2395 } 2396 } 2397 if (tmp == NULL) 2398 return 0; 2399 2400 down_write(&dmar_global_lock); 2401 if (insert) 2402 ret = dmar_hotplug_insert(tmp); 2403 else 2404 ret = dmar_hotplug_remove(tmp); 2405 up_write(&dmar_global_lock); 2406 2407 return ret; 2408 } 2409 2410 int dmar_device_add(acpi_handle handle) 2411 { 2412 return dmar_device_hotplug(handle, true); 2413 } 2414 2415 int dmar_device_remove(acpi_handle handle) 2416 { 2417 return dmar_device_hotplug(handle, false); 2418 } 2419 2420 /* 2421 * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table 2422 * 2423 * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in 2424 * the ACPI DMAR table. This means that the platform boot firmware has made 2425 * sure no device can issue DMA outside of RMRR regions. 2426 */ 2427 bool dmar_platform_optin(void) 2428 { 2429 struct acpi_table_dmar *dmar; 2430 acpi_status status; 2431 bool ret; 2432 2433 status = acpi_get_table(ACPI_SIG_DMAR, 0, 2434 (struct acpi_table_header **)&dmar); 2435 if (ACPI_FAILURE(status)) 2436 return false; 2437 2438 ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN); 2439 acpi_put_table((struct acpi_table_header *)dmar); 2440 2441 return ret; 2442 } 2443 EXPORT_SYMBOL_GPL(dmar_platform_optin); 2444