1a6199bb5SShawn Guo // SPDX-License-Identifier: GPL-2.0-only 2a6199bb5SShawn Guo /* 3a6199bb5SShawn Guo * Copyright (c) 2021, Linaro Limited 4a6199bb5SShawn Guo * Copyright (c) 2010-2020, The Linux Foundation. All rights reserved. 5a6199bb5SShawn Guo */ 6a6199bb5SShawn Guo 7a6199bb5SShawn Guo #include <linux/delay.h> 8a6199bb5SShawn Guo #include <linux/err.h> 9a6199bb5SShawn Guo #include <linux/init.h> 10a6199bb5SShawn Guo #include <linux/interrupt.h> 11a6199bb5SShawn Guo #include <linux/io.h> 12a6199bb5SShawn Guo #include <linux/irqchip.h> 13a6199bb5SShawn Guo #include <linux/irqdomain.h> 14a6199bb5SShawn Guo #include <linux/mailbox_client.h> 15a6199bb5SShawn Guo #include <linux/module.h> 16a6199bb5SShawn Guo #include <linux/of.h> 17a6199bb5SShawn Guo #include <linux/of_device.h> 18a6199bb5SShawn Guo #include <linux/platform_device.h> 19a6199bb5SShawn Guo #include <linux/pm_domain.h> 20a6199bb5SShawn Guo #include <linux/slab.h> 21a6199bb5SShawn Guo #include <linux/soc/qcom/irq.h> 22a6199bb5SShawn Guo #include <linux/spinlock.h> 23a6199bb5SShawn Guo 24a6199bb5SShawn Guo /* 25a6199bb5SShawn Guo * This is the driver for Qualcomm MPM (MSM Power Manager) interrupt controller, 26a6199bb5SShawn Guo * which is commonly found on Qualcomm SoCs built on the RPM architecture. 27a6199bb5SShawn Guo * Sitting in always-on domain, MPM monitors the wakeup interrupts when SoC is 28a6199bb5SShawn Guo * asleep, and wakes up the AP when one of those interrupts occurs. This driver 29a6199bb5SShawn Guo * doesn't directly access physical MPM registers though. Instead, the access 30a6199bb5SShawn Guo * is bridged via a piece of internal memory (SRAM) that is accessible to both 31a6199bb5SShawn Guo * AP and RPM. This piece of memory is called 'vMPM' in the driver. 32a6199bb5SShawn Guo * 33a6199bb5SShawn Guo * When SoC is awake, the vMPM is owned by AP and the register setup by this 34a6199bb5SShawn Guo * driver all happens on vMPM. When AP is about to get power collapsed, the 35a6199bb5SShawn Guo * driver sends a mailbox notification to RPM, which will take over the vMPM 36a6199bb5SShawn Guo * ownership and dump vMPM into physical MPM registers. On wakeup, AP is woken 37a6199bb5SShawn Guo * up by a MPM pin/interrupt, and RPM will copy STATUS registers into vMPM. 38a6199bb5SShawn Guo * Then AP start owning vMPM again. 39a6199bb5SShawn Guo * 40a6199bb5SShawn Guo * vMPM register map: 41a6199bb5SShawn Guo * 42a6199bb5SShawn Guo * 31 0 43a6199bb5SShawn Guo * +--------------------------------+ 44a6199bb5SShawn Guo * | TIMER0 | 0x00 45a6199bb5SShawn Guo * +--------------------------------+ 46a6199bb5SShawn Guo * | TIMER1 | 0x04 47a6199bb5SShawn Guo * +--------------------------------+ 48a6199bb5SShawn Guo * | ENABLE0 | 0x08 49a6199bb5SShawn Guo * +--------------------------------+ 50a6199bb5SShawn Guo * | ... | ... 51a6199bb5SShawn Guo * +--------------------------------+ 52a6199bb5SShawn Guo * | ENABLEn | 53a6199bb5SShawn Guo * +--------------------------------+ 54a6199bb5SShawn Guo * | FALLING_EDGE0 | 55a6199bb5SShawn Guo * +--------------------------------+ 56a6199bb5SShawn Guo * | ... | 57a6199bb5SShawn Guo * +--------------------------------+ 58a6199bb5SShawn Guo * | STATUSn | 59a6199bb5SShawn Guo * +--------------------------------+ 60a6199bb5SShawn Guo * 61a6199bb5SShawn Guo * n = DIV_ROUND_UP(pin_cnt, 32) 62a6199bb5SShawn Guo * 63a6199bb5SShawn Guo */ 64a6199bb5SShawn Guo 65a6199bb5SShawn Guo #define MPM_REG_ENABLE 0 66a6199bb5SShawn Guo #define MPM_REG_FALLING_EDGE 1 67a6199bb5SShawn Guo #define MPM_REG_RISING_EDGE 2 68a6199bb5SShawn Guo #define MPM_REG_POLARITY 3 69a6199bb5SShawn Guo #define MPM_REG_STATUS 4 70a6199bb5SShawn Guo 71a6199bb5SShawn Guo /* MPM pin map to GIC hwirq */ 72a6199bb5SShawn Guo struct mpm_gic_map { 73a6199bb5SShawn Guo int pin; 74a6199bb5SShawn Guo irq_hw_number_t hwirq; 75a6199bb5SShawn Guo }; 76a6199bb5SShawn Guo 77a6199bb5SShawn Guo struct qcom_mpm_priv { 78a6199bb5SShawn Guo void __iomem *base; 79a6199bb5SShawn Guo raw_spinlock_t lock; 80a6199bb5SShawn Guo struct mbox_client mbox_client; 81a6199bb5SShawn Guo struct mbox_chan *mbox_chan; 82a6199bb5SShawn Guo struct mpm_gic_map *maps; 83a6199bb5SShawn Guo unsigned int map_cnt; 84a6199bb5SShawn Guo unsigned int reg_stride; 85a6199bb5SShawn Guo struct irq_domain *domain; 86a6199bb5SShawn Guo struct generic_pm_domain genpd; 87a6199bb5SShawn Guo }; 88a6199bb5SShawn Guo 89a6199bb5SShawn Guo static u32 qcom_mpm_read(struct qcom_mpm_priv *priv, unsigned int reg, 90a6199bb5SShawn Guo unsigned int index) 91a6199bb5SShawn Guo { 92a6199bb5SShawn Guo unsigned int offset = (reg * priv->reg_stride + index + 2) * 4; 93a6199bb5SShawn Guo 94a6199bb5SShawn Guo return readl_relaxed(priv->base + offset); 95a6199bb5SShawn Guo } 96a6199bb5SShawn Guo 97a6199bb5SShawn Guo static void qcom_mpm_write(struct qcom_mpm_priv *priv, unsigned int reg, 98a6199bb5SShawn Guo unsigned int index, u32 val) 99a6199bb5SShawn Guo { 100a6199bb5SShawn Guo unsigned int offset = (reg * priv->reg_stride + index + 2) * 4; 101a6199bb5SShawn Guo 102a6199bb5SShawn Guo writel_relaxed(val, priv->base + offset); 103a6199bb5SShawn Guo 104a6199bb5SShawn Guo /* Ensure the write is completed */ 105a6199bb5SShawn Guo wmb(); 106a6199bb5SShawn Guo } 107a6199bb5SShawn Guo 108a6199bb5SShawn Guo static void qcom_mpm_enable_irq(struct irq_data *d, bool en) 109a6199bb5SShawn Guo { 110a6199bb5SShawn Guo struct qcom_mpm_priv *priv = d->chip_data; 111a6199bb5SShawn Guo int pin = d->hwirq; 112a6199bb5SShawn Guo unsigned int index = pin / 32; 113a6199bb5SShawn Guo unsigned int shift = pin % 32; 114a6199bb5SShawn Guo unsigned long flags, val; 115a6199bb5SShawn Guo 116a6199bb5SShawn Guo raw_spin_lock_irqsave(&priv->lock, flags); 117a6199bb5SShawn Guo 118a6199bb5SShawn Guo val = qcom_mpm_read(priv, MPM_REG_ENABLE, index); 119a6199bb5SShawn Guo __assign_bit(shift, &val, en); 120a6199bb5SShawn Guo qcom_mpm_write(priv, MPM_REG_ENABLE, index, val); 121a6199bb5SShawn Guo 122a6199bb5SShawn Guo raw_spin_unlock_irqrestore(&priv->lock, flags); 123a6199bb5SShawn Guo } 124a6199bb5SShawn Guo 125a6199bb5SShawn Guo static void qcom_mpm_mask(struct irq_data *d) 126a6199bb5SShawn Guo { 127a6199bb5SShawn Guo qcom_mpm_enable_irq(d, false); 128a6199bb5SShawn Guo 129a6199bb5SShawn Guo if (d->parent_data) 130a6199bb5SShawn Guo irq_chip_mask_parent(d); 131a6199bb5SShawn Guo } 132a6199bb5SShawn Guo 133a6199bb5SShawn Guo static void qcom_mpm_unmask(struct irq_data *d) 134a6199bb5SShawn Guo { 135a6199bb5SShawn Guo qcom_mpm_enable_irq(d, true); 136a6199bb5SShawn Guo 137a6199bb5SShawn Guo if (d->parent_data) 138a6199bb5SShawn Guo irq_chip_unmask_parent(d); 139a6199bb5SShawn Guo } 140a6199bb5SShawn Guo 141a6199bb5SShawn Guo static void mpm_set_type(struct qcom_mpm_priv *priv, bool set, unsigned int reg, 142a6199bb5SShawn Guo unsigned int index, unsigned int shift) 143a6199bb5SShawn Guo { 144a6199bb5SShawn Guo unsigned long flags, val; 145a6199bb5SShawn Guo 146a6199bb5SShawn Guo raw_spin_lock_irqsave(&priv->lock, flags); 147a6199bb5SShawn Guo 148a6199bb5SShawn Guo val = qcom_mpm_read(priv, reg, index); 149a6199bb5SShawn Guo __assign_bit(shift, &val, set); 150a6199bb5SShawn Guo qcom_mpm_write(priv, reg, index, val); 151a6199bb5SShawn Guo 152a6199bb5SShawn Guo raw_spin_unlock_irqrestore(&priv->lock, flags); 153a6199bb5SShawn Guo } 154a6199bb5SShawn Guo 155a6199bb5SShawn Guo static int qcom_mpm_set_type(struct irq_data *d, unsigned int type) 156a6199bb5SShawn Guo { 157a6199bb5SShawn Guo struct qcom_mpm_priv *priv = d->chip_data; 158a6199bb5SShawn Guo int pin = d->hwirq; 159a6199bb5SShawn Guo unsigned int index = pin / 32; 160a6199bb5SShawn Guo unsigned int shift = pin % 32; 161a6199bb5SShawn Guo 162a6199bb5SShawn Guo if (type & IRQ_TYPE_EDGE_RISING) 163a6199bb5SShawn Guo mpm_set_type(priv, true, MPM_REG_RISING_EDGE, index, shift); 164a6199bb5SShawn Guo else 165a6199bb5SShawn Guo mpm_set_type(priv, false, MPM_REG_RISING_EDGE, index, shift); 166a6199bb5SShawn Guo 167a6199bb5SShawn Guo if (type & IRQ_TYPE_EDGE_FALLING) 168a6199bb5SShawn Guo mpm_set_type(priv, true, MPM_REG_FALLING_EDGE, index, shift); 169a6199bb5SShawn Guo else 170a6199bb5SShawn Guo mpm_set_type(priv, false, MPM_REG_FALLING_EDGE, index, shift); 171a6199bb5SShawn Guo 172a6199bb5SShawn Guo if (type & IRQ_TYPE_LEVEL_HIGH) 173a6199bb5SShawn Guo mpm_set_type(priv, true, MPM_REG_POLARITY, index, shift); 174a6199bb5SShawn Guo else 175a6199bb5SShawn Guo mpm_set_type(priv, false, MPM_REG_POLARITY, index, shift); 176a6199bb5SShawn Guo 177a6199bb5SShawn Guo if (!d->parent_data) 178a6199bb5SShawn Guo return 0; 179a6199bb5SShawn Guo 180a6199bb5SShawn Guo if (type & IRQ_TYPE_EDGE_BOTH) 181a6199bb5SShawn Guo type = IRQ_TYPE_EDGE_RISING; 182a6199bb5SShawn Guo 183a6199bb5SShawn Guo if (type & IRQ_TYPE_LEVEL_MASK) 184a6199bb5SShawn Guo type = IRQ_TYPE_LEVEL_HIGH; 185a6199bb5SShawn Guo 186a6199bb5SShawn Guo return irq_chip_set_type_parent(d, type); 187a6199bb5SShawn Guo } 188a6199bb5SShawn Guo 189a6199bb5SShawn Guo static struct irq_chip qcom_mpm_chip = { 190a6199bb5SShawn Guo .name = "mpm", 191a6199bb5SShawn Guo .irq_eoi = irq_chip_eoi_parent, 192a6199bb5SShawn Guo .irq_mask = qcom_mpm_mask, 193a6199bb5SShawn Guo .irq_unmask = qcom_mpm_unmask, 194a6199bb5SShawn Guo .irq_retrigger = irq_chip_retrigger_hierarchy, 195a6199bb5SShawn Guo .irq_set_type = qcom_mpm_set_type, 196a6199bb5SShawn Guo .irq_set_affinity = irq_chip_set_affinity_parent, 197a6199bb5SShawn Guo .flags = IRQCHIP_MASK_ON_SUSPEND | 198a6199bb5SShawn Guo IRQCHIP_SKIP_SET_WAKE, 199a6199bb5SShawn Guo }; 200a6199bb5SShawn Guo 201a6199bb5SShawn Guo static struct mpm_gic_map *get_mpm_gic_map(struct qcom_mpm_priv *priv, int pin) 202a6199bb5SShawn Guo { 203a6199bb5SShawn Guo struct mpm_gic_map *maps = priv->maps; 204a6199bb5SShawn Guo int i; 205a6199bb5SShawn Guo 206a6199bb5SShawn Guo for (i = 0; i < priv->map_cnt; i++) { 207a6199bb5SShawn Guo if (maps[i].pin == pin) 208a6199bb5SShawn Guo return &maps[i]; 209a6199bb5SShawn Guo } 210a6199bb5SShawn Guo 211a6199bb5SShawn Guo return NULL; 212a6199bb5SShawn Guo } 213a6199bb5SShawn Guo 214a6199bb5SShawn Guo static int qcom_mpm_alloc(struct irq_domain *domain, unsigned int virq, 215a6199bb5SShawn Guo unsigned int nr_irqs, void *data) 216a6199bb5SShawn Guo { 217a6199bb5SShawn Guo struct qcom_mpm_priv *priv = domain->host_data; 218a6199bb5SShawn Guo struct irq_fwspec *fwspec = data; 219a6199bb5SShawn Guo struct irq_fwspec parent_fwspec; 220a6199bb5SShawn Guo struct mpm_gic_map *map; 221a6199bb5SShawn Guo irq_hw_number_t pin; 222a6199bb5SShawn Guo unsigned int type; 223a6199bb5SShawn Guo int ret; 224a6199bb5SShawn Guo 225a6199bb5SShawn Guo ret = irq_domain_translate_twocell(domain, fwspec, &pin, &type); 226a6199bb5SShawn Guo if (ret) 227a6199bb5SShawn Guo return ret; 228a6199bb5SShawn Guo 229a6199bb5SShawn Guo ret = irq_domain_set_hwirq_and_chip(domain, virq, pin, 230a6199bb5SShawn Guo &qcom_mpm_chip, priv); 231a6199bb5SShawn Guo if (ret) 232a6199bb5SShawn Guo return ret; 233a6199bb5SShawn Guo 234a6199bb5SShawn Guo map = get_mpm_gic_map(priv, pin); 235a6199bb5SShawn Guo if (map == NULL) 236a6199bb5SShawn Guo return irq_domain_disconnect_hierarchy(domain->parent, virq); 237a6199bb5SShawn Guo 238a6199bb5SShawn Guo if (type & IRQ_TYPE_EDGE_BOTH) 239a6199bb5SShawn Guo type = IRQ_TYPE_EDGE_RISING; 240a6199bb5SShawn Guo 241a6199bb5SShawn Guo if (type & IRQ_TYPE_LEVEL_MASK) 242a6199bb5SShawn Guo type = IRQ_TYPE_LEVEL_HIGH; 243a6199bb5SShawn Guo 244a6199bb5SShawn Guo parent_fwspec.fwnode = domain->parent->fwnode; 245a6199bb5SShawn Guo parent_fwspec.param_count = 3; 246a6199bb5SShawn Guo parent_fwspec.param[0] = 0; 247a6199bb5SShawn Guo parent_fwspec.param[1] = map->hwirq; 248a6199bb5SShawn Guo parent_fwspec.param[2] = type; 249a6199bb5SShawn Guo 250a6199bb5SShawn Guo return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 251a6199bb5SShawn Guo &parent_fwspec); 252a6199bb5SShawn Guo } 253a6199bb5SShawn Guo 254a6199bb5SShawn Guo static const struct irq_domain_ops qcom_mpm_ops = { 255a6199bb5SShawn Guo .alloc = qcom_mpm_alloc, 256a6199bb5SShawn Guo .free = irq_domain_free_irqs_common, 257a6199bb5SShawn Guo .translate = irq_domain_translate_twocell, 258a6199bb5SShawn Guo }; 259a6199bb5SShawn Guo 260a6199bb5SShawn Guo /* Triggered by RPM when system resumes from deep sleep */ 261a6199bb5SShawn Guo static irqreturn_t qcom_mpm_handler(int irq, void *dev_id) 262a6199bb5SShawn Guo { 263a6199bb5SShawn Guo struct qcom_mpm_priv *priv = dev_id; 264a6199bb5SShawn Guo unsigned long enable, pending; 265a6199bb5SShawn Guo irqreturn_t ret = IRQ_NONE; 266a6199bb5SShawn Guo unsigned long flags; 267a6199bb5SShawn Guo int i, j; 268a6199bb5SShawn Guo 269a6199bb5SShawn Guo for (i = 0; i < priv->reg_stride; i++) { 270a6199bb5SShawn Guo raw_spin_lock_irqsave(&priv->lock, flags); 271a6199bb5SShawn Guo enable = qcom_mpm_read(priv, MPM_REG_ENABLE, i); 272a6199bb5SShawn Guo pending = qcom_mpm_read(priv, MPM_REG_STATUS, i); 273a6199bb5SShawn Guo pending &= enable; 274a6199bb5SShawn Guo raw_spin_unlock_irqrestore(&priv->lock, flags); 275a6199bb5SShawn Guo 276a6199bb5SShawn Guo for_each_set_bit(j, &pending, 32) { 277a6199bb5SShawn Guo unsigned int pin = 32 * i + j; 278a6199bb5SShawn Guo struct irq_desc *desc = irq_resolve_mapping(priv->domain, pin); 279a6199bb5SShawn Guo struct irq_data *d = &desc->irq_data; 280a6199bb5SShawn Guo 281a6199bb5SShawn Guo if (!irqd_is_level_type(d)) 282a6199bb5SShawn Guo irq_set_irqchip_state(d->irq, 283a6199bb5SShawn Guo IRQCHIP_STATE_PENDING, true); 284a6199bb5SShawn Guo ret = IRQ_HANDLED; 285a6199bb5SShawn Guo } 286a6199bb5SShawn Guo } 287a6199bb5SShawn Guo 288a6199bb5SShawn Guo return ret; 289a6199bb5SShawn Guo } 290a6199bb5SShawn Guo 291a6199bb5SShawn Guo static int mpm_pd_power_off(struct generic_pm_domain *genpd) 292a6199bb5SShawn Guo { 293a6199bb5SShawn Guo struct qcom_mpm_priv *priv = container_of(genpd, struct qcom_mpm_priv, 294a6199bb5SShawn Guo genpd); 295a6199bb5SShawn Guo int i, ret; 296a6199bb5SShawn Guo 297a6199bb5SShawn Guo for (i = 0; i < priv->reg_stride; i++) 298a6199bb5SShawn Guo qcom_mpm_write(priv, MPM_REG_STATUS, i, 0); 299a6199bb5SShawn Guo 300a6199bb5SShawn Guo /* Notify RPM to write vMPM into HW */ 301a6199bb5SShawn Guo ret = mbox_send_message(priv->mbox_chan, NULL); 302a6199bb5SShawn Guo if (ret < 0) 303a6199bb5SShawn Guo return ret; 304a6199bb5SShawn Guo 305a6199bb5SShawn Guo return 0; 306a6199bb5SShawn Guo } 307a6199bb5SShawn Guo 308a6199bb5SShawn Guo static bool gic_hwirq_is_mapped(struct mpm_gic_map *maps, int cnt, u32 hwirq) 309a6199bb5SShawn Guo { 310a6199bb5SShawn Guo int i; 311a6199bb5SShawn Guo 312a6199bb5SShawn Guo for (i = 0; i < cnt; i++) 313a6199bb5SShawn Guo if (maps[i].hwirq == hwirq) 314a6199bb5SShawn Guo return true; 315a6199bb5SShawn Guo 316a6199bb5SShawn Guo return false; 317a6199bb5SShawn Guo } 318a6199bb5SShawn Guo 319a6199bb5SShawn Guo static int qcom_mpm_init(struct device_node *np, struct device_node *parent) 320a6199bb5SShawn Guo { 321a6199bb5SShawn Guo struct platform_device *pdev = of_find_device_by_node(np); 322a6199bb5SShawn Guo struct device *dev = &pdev->dev; 323a6199bb5SShawn Guo struct irq_domain *parent_domain; 324a6199bb5SShawn Guo struct generic_pm_domain *genpd; 325a6199bb5SShawn Guo struct qcom_mpm_priv *priv; 326a6199bb5SShawn Guo unsigned int pin_cnt; 327a6199bb5SShawn Guo int i, irq; 328a6199bb5SShawn Guo int ret; 329a6199bb5SShawn Guo 330a6199bb5SShawn Guo priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 331a6199bb5SShawn Guo if (!priv) 332a6199bb5SShawn Guo return -ENOMEM; 333a6199bb5SShawn Guo 334a6199bb5SShawn Guo ret = of_property_read_u32(np, "qcom,mpm-pin-count", &pin_cnt); 335a6199bb5SShawn Guo if (ret) { 336a6199bb5SShawn Guo dev_err(dev, "failed to read qcom,mpm-pin-count: %d\n", ret); 337a6199bb5SShawn Guo return ret; 338a6199bb5SShawn Guo } 339a6199bb5SShawn Guo 340a6199bb5SShawn Guo priv->reg_stride = DIV_ROUND_UP(pin_cnt, 32); 341a6199bb5SShawn Guo 342a6199bb5SShawn Guo ret = of_property_count_u32_elems(np, "qcom,mpm-pin-map"); 343a6199bb5SShawn Guo if (ret < 0) { 344a6199bb5SShawn Guo dev_err(dev, "failed to read qcom,mpm-pin-map: %d\n", ret); 345a6199bb5SShawn Guo return ret; 346a6199bb5SShawn Guo } 347a6199bb5SShawn Guo 348a6199bb5SShawn Guo if (ret % 2) { 349a6199bb5SShawn Guo dev_err(dev, "invalid qcom,mpm-pin-map\n"); 350a6199bb5SShawn Guo return -EINVAL; 351a6199bb5SShawn Guo } 352a6199bb5SShawn Guo 353a6199bb5SShawn Guo priv->map_cnt = ret / 2; 354a6199bb5SShawn Guo priv->maps = devm_kcalloc(dev, priv->map_cnt, sizeof(*priv->maps), 355a6199bb5SShawn Guo GFP_KERNEL); 356a6199bb5SShawn Guo if (!priv->maps) 357a6199bb5SShawn Guo return -ENOMEM; 358a6199bb5SShawn Guo 359a6199bb5SShawn Guo for (i = 0; i < priv->map_cnt; i++) { 360a6199bb5SShawn Guo u32 pin, hwirq; 361a6199bb5SShawn Guo 362a6199bb5SShawn Guo of_property_read_u32_index(np, "qcom,mpm-pin-map", i * 2, &pin); 363a6199bb5SShawn Guo of_property_read_u32_index(np, "qcom,mpm-pin-map", i * 2 + 1, &hwirq); 364a6199bb5SShawn Guo 365a6199bb5SShawn Guo if (gic_hwirq_is_mapped(priv->maps, i, hwirq)) { 366a6199bb5SShawn Guo dev_warn(dev, "failed to map pin %d as GIC hwirq %d is already mapped\n", 367a6199bb5SShawn Guo pin, hwirq); 368a6199bb5SShawn Guo continue; 369a6199bb5SShawn Guo } 370a6199bb5SShawn Guo 371a6199bb5SShawn Guo priv->maps[i].pin = pin; 372a6199bb5SShawn Guo priv->maps[i].hwirq = hwirq; 373a6199bb5SShawn Guo } 374a6199bb5SShawn Guo 375a6199bb5SShawn Guo raw_spin_lock_init(&priv->lock); 376a6199bb5SShawn Guo 377a6199bb5SShawn Guo priv->base = devm_platform_ioremap_resource(pdev, 0); 378*76ff614aSYang Yingliang if (IS_ERR(priv->base)) 379a6199bb5SShawn Guo return PTR_ERR(priv->base); 380a6199bb5SShawn Guo 381a6199bb5SShawn Guo for (i = 0; i < priv->reg_stride; i++) { 382a6199bb5SShawn Guo qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0); 383a6199bb5SShawn Guo qcom_mpm_write(priv, MPM_REG_FALLING_EDGE, i, 0); 384a6199bb5SShawn Guo qcom_mpm_write(priv, MPM_REG_RISING_EDGE, i, 0); 385a6199bb5SShawn Guo qcom_mpm_write(priv, MPM_REG_POLARITY, i, 0); 386a6199bb5SShawn Guo qcom_mpm_write(priv, MPM_REG_STATUS, i, 0); 387a6199bb5SShawn Guo } 388a6199bb5SShawn Guo 389a6199bb5SShawn Guo irq = platform_get_irq(pdev, 0); 390a6199bb5SShawn Guo if (irq < 0) 391a6199bb5SShawn Guo return irq; 392a6199bb5SShawn Guo 393a6199bb5SShawn Guo genpd = &priv->genpd; 394a6199bb5SShawn Guo genpd->flags = GENPD_FLAG_IRQ_SAFE; 395a6199bb5SShawn Guo genpd->power_off = mpm_pd_power_off; 396a6199bb5SShawn Guo 397a6199bb5SShawn Guo genpd->name = devm_kasprintf(dev, GFP_KERNEL, "%s", dev_name(dev)); 398a6199bb5SShawn Guo if (!genpd->name) 399a6199bb5SShawn Guo return -ENOMEM; 400a6199bb5SShawn Guo 401a6199bb5SShawn Guo ret = pm_genpd_init(genpd, NULL, false); 402a6199bb5SShawn Guo if (ret) { 403a6199bb5SShawn Guo dev_err(dev, "failed to init genpd: %d\n", ret); 404a6199bb5SShawn Guo return ret; 405a6199bb5SShawn Guo } 406a6199bb5SShawn Guo 407a6199bb5SShawn Guo ret = of_genpd_add_provider_simple(np, genpd); 408a6199bb5SShawn Guo if (ret) { 409a6199bb5SShawn Guo dev_err(dev, "failed to add genpd provider: %d\n", ret); 410a6199bb5SShawn Guo goto remove_genpd; 411a6199bb5SShawn Guo } 412a6199bb5SShawn Guo 413a6199bb5SShawn Guo priv->mbox_client.dev = dev; 414a6199bb5SShawn Guo priv->mbox_chan = mbox_request_channel(&priv->mbox_client, 0); 415a6199bb5SShawn Guo if (IS_ERR(priv->mbox_chan)) { 416a6199bb5SShawn Guo ret = PTR_ERR(priv->mbox_chan); 417a6199bb5SShawn Guo dev_err(dev, "failed to acquire IPC channel: %d\n", ret); 418a6199bb5SShawn Guo return ret; 419a6199bb5SShawn Guo } 420a6199bb5SShawn Guo 421a6199bb5SShawn Guo parent_domain = irq_find_host(parent); 422a6199bb5SShawn Guo if (!parent_domain) { 423a6199bb5SShawn Guo dev_err(dev, "failed to find MPM parent domain\n"); 424a6199bb5SShawn Guo ret = -ENXIO; 425a6199bb5SShawn Guo goto free_mbox; 426a6199bb5SShawn Guo } 427a6199bb5SShawn Guo 428a6199bb5SShawn Guo priv->domain = irq_domain_create_hierarchy(parent_domain, 429a6199bb5SShawn Guo IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP, pin_cnt, 430a6199bb5SShawn Guo of_node_to_fwnode(np), &qcom_mpm_ops, priv); 431a6199bb5SShawn Guo if (!priv->domain) { 432a6199bb5SShawn Guo dev_err(dev, "failed to create MPM domain\n"); 433a6199bb5SShawn Guo ret = -ENOMEM; 434a6199bb5SShawn Guo goto free_mbox; 435a6199bb5SShawn Guo } 436a6199bb5SShawn Guo 437a6199bb5SShawn Guo irq_domain_update_bus_token(priv->domain, DOMAIN_BUS_WAKEUP); 438a6199bb5SShawn Guo 439a6199bb5SShawn Guo ret = devm_request_irq(dev, irq, qcom_mpm_handler, IRQF_NO_SUSPEND, 440a6199bb5SShawn Guo "qcom_mpm", priv); 441a6199bb5SShawn Guo if (ret) { 442a6199bb5SShawn Guo dev_err(dev, "failed to request irq: %d\n", ret); 443a6199bb5SShawn Guo goto remove_domain; 444a6199bb5SShawn Guo } 445a6199bb5SShawn Guo 446a6199bb5SShawn Guo return 0; 447a6199bb5SShawn Guo 448a6199bb5SShawn Guo remove_domain: 449a6199bb5SShawn Guo irq_domain_remove(priv->domain); 450a6199bb5SShawn Guo free_mbox: 451a6199bb5SShawn Guo mbox_free_channel(priv->mbox_chan); 452a6199bb5SShawn Guo remove_genpd: 453a6199bb5SShawn Guo pm_genpd_remove(genpd); 454a6199bb5SShawn Guo return ret; 455a6199bb5SShawn Guo } 456a6199bb5SShawn Guo 457a6199bb5SShawn Guo IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_mpm) 458a6199bb5SShawn Guo IRQCHIP_MATCH("qcom,mpm", qcom_mpm_init) 459a6199bb5SShawn Guo IRQCHIP_PLATFORM_DRIVER_END(qcom_mpm) 460a6199bb5SShawn Guo MODULE_DESCRIPTION("Qualcomm Technologies, Inc. MSM Power Manager"); 461a6199bb5SShawn Guo MODULE_LICENSE("GPL v2"); 462