1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Support for the Broadcom BCM3510 ATSC demodulator (1st generation Air2PC)
4  *
5  *  Copyright (C) 2001-5, B2C2 inc.
6  *
7  *  GPL/Linux driver written by Patrick Boettcher <patrick.boettcher@posteo.de>
8  */
9 #ifndef __BCM3510_PRIV_H__
10 #define __BCM3510_PRIV_H__
11 
12 #define PACKED __attribute__((packed))
13 
14 #undef err
15 #define err(format, arg...)  printk(KERN_ERR     "bcm3510: " format "\n" , ## arg)
16 #undef info
17 #define info(format, arg...) printk(KERN_INFO    "bcm3510: " format "\n" , ## arg)
18 #undef warn
19 #define warn(format, arg...) printk(KERN_WARNING "bcm3510: " format "\n" , ## arg)
20 
21 
22 #define PANASONIC_FIRST_IF_BASE_IN_KHz  1407500
23 #define BCM3510_SYMBOL_RATE             5381000
24 
25 typedef union {
26 	u8 raw;
27 
28 	struct {
29 		u8 CTL   :8;
30 	} TSTCTL_2e;
31 
32 	u8 LDCERC_4e;
33 	u8 LDUERC_4f;
34 	u8 LD_BER0_65;
35 	u8 LD_BER1_66;
36 	u8 LD_BER2_67;
37 	u8 LD_BER3_68;
38 
39 	struct {
40 		u8 RESET :1;
41 		u8 IDLE  :1;
42 		u8 STOP  :1;
43 		u8 HIRQ0 :1;
44 		u8 HIRQ1 :1;
45 		u8 na0   :1;
46 		u8 HABAV :1;
47 		u8 na1   :1;
48 	} HCTL1_a0;
49 
50 	struct {
51 		u8 na0    :1;
52 		u8 IDLMSK :1;
53 		u8 STMSK  :1;
54 		u8 I0MSK  :1;
55 		u8 I1MSK  :1;
56 		u8 na1    :1;
57 		u8 HABMSK :1;
58 		u8 na2    :1;
59 	} HCTLMSK_a1;
60 
61 	struct {
62 		u8 RESET  :1;
63 		u8 IDLE   :1;
64 		u8 STOP   :1;
65 		u8 RUN    :1;
66 		u8 HABAV  :1;
67 		u8 MEMAV  :1;
68 		u8 ALDONE :1;
69 		u8 REIRQ  :1;
70 	} APSTAT1_a2;
71 
72 	struct {
73 		u8 RSTMSK :1;
74 		u8 IMSK   :1;
75 		u8 SMSK   :1;
76 		u8 RMSK   :1;
77 		u8 HABMSK :1;
78 		u8 MAVMSK :1;
79 		u8 ALDMSK :1;
80 		u8 REMSK  :1;
81 	} APMSK1_a3;
82 
83 	u8 APSTAT2_a4;
84 	u8 APMSK2_a5;
85 
86 	struct {
87 		u8 HABADR :7;
88 		u8 na     :1;
89 	} HABADR_a6;
90 
91 	u8 HABDATA_a7;
92 
93 	struct {
94 		u8 HABR   :1;
95 		u8 LDHABR :1;
96 		u8 APMSK  :1;
97 		u8 HMSK   :1;
98 		u8 LDMSK  :1;
99 		u8 na     :3;
100 	} HABSTAT_a8;
101 
102 	u8 MADRH_a9;
103 	u8 MADRL_aa;
104 	u8 MDATA_ab;
105 
106 	struct {
107 #define JDEC_WAIT_AT_RAM      0x7
108 #define JDEC_EEPROM_LOAD_WAIT 0x4
109 		u8 JDEC   :3;
110 		u8 na     :5;
111 	} JDEC_ca;
112 
113 	struct {
114 		u8 REV   :4;
115 		u8 LAYER :4;
116 	} REVID_e0;
117 
118 	struct {
119 		u8 unk0   :1;
120 		u8 CNTCTL :1;
121 		u8 BITCNT :1;
122 		u8 unk1   :1;
123 		u8 RESYNC :1;
124 		u8 unk2   :3;
125 	} BERCTL_fa;
126 
127 	struct {
128 		u8 CSEL0  :1;
129 		u8 CLKED0 :1;
130 		u8 CSEL1  :1;
131 		u8 CLKED1 :1;
132 		u8 CLKLEV :1;
133 		u8 SPIVAR :1;
134 		u8 na     :2;
135 	} TUNSET_fc;
136 
137 	struct {
138 		u8 CLK    :1;
139 		u8 DATA   :1;
140 		u8 CS0    :1;
141 		u8 CS1    :1;
142 		u8 AGCSEL :1;
143 		u8 na0    :1;
144 		u8 TUNSEL :1;
145 		u8 na1    :1;
146 	} TUNCTL_fd;
147 
148 	u8 TUNSEL0_fe;
149 	u8 TUNSEL1_ff;
150 
151 } bcm3510_register_value;
152 
153 /* HAB commands */
154 
155 /* version */
156 #define CMD_GET_VERSION_INFO   0x3D
157 #define MSGID_GET_VERSION_INFO 0x15
158 struct bcm3510_hab_cmd_get_version_info {
159 	u8 microcode_version;
160 	u8 script_version;
161 	u8 config_version;
162 	u8 demod_version;
163 } PACKED;
164 
165 #define BCM3510_DEF_MICROCODE_VERSION 0x0E
166 #define BCM3510_DEF_SCRIPT_VERSION    0x06
167 #define BCM3510_DEF_CONFIG_VERSION    0x01
168 #define BCM3510_DEF_DEMOD_VERSION     0xB1
169 
170 /* acquire */
171 #define CMD_ACQUIRE            0x38
172 
173 #define MSGID_EXT_TUNER_ACQUIRE 0x0A
174 struct bcm3510_hab_cmd_ext_acquire {
175 	struct {
176 		u8 MODE      :4;
177 		u8 BW        :1;
178 		u8 FA        :1;
179 		u8 NTSCSWEEP :1;
180 		u8 OFFSET    :1;
181 	} PACKED ACQUIRE0; /* control_byte */
182 
183 	struct {
184 		u8 IF_FREQ  :3;
185 		u8 zero0    :1;
186 		u8 SYM_RATE :3;
187 		u8 zero1    :1;
188 	} PACKED ACQUIRE1; /* sym_if */
189 
190 	u8 IF_OFFSET0;   /* IF_Offset_10hz */
191 	u8 IF_OFFSET1;
192 	u8 SYM_OFFSET0;  /* SymbolRateOffset */
193 	u8 SYM_OFFSET1;
194 	u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */
195 	u8 NTSC_OFFSET1;
196 } PACKED;
197 
198 #define MSGID_INT_TUNER_ACQUIRE 0x0B
199 struct bcm3510_hab_cmd_int_acquire {
200 	struct {
201 		u8 MODE      :4;
202 		u8 BW        :1;
203 		u8 FA        :1;
204 		u8 NTSCSWEEP :1;
205 		u8 OFFSET    :1;
206 	} PACKED ACQUIRE0; /* control_byte */
207 
208 	struct {
209 		u8 IF_FREQ  :3;
210 		u8 zero0    :1;
211 		u8 SYM_RATE :3;
212 		u8 zero1    :1;
213 	} PACKED ACQUIRE1; /* sym_if */
214 
215 	u8 TUNER_FREQ0;
216 	u8 TUNER_FREQ1;
217 	u8 TUNER_FREQ2;
218 	u8 TUNER_FREQ3;
219 	u8 IF_OFFSET0;   /* IF_Offset_10hz */
220 	u8 IF_OFFSET1;
221 	u8 SYM_OFFSET0;  /* SymbolRateOffset */
222 	u8 SYM_OFFSET1;
223 	u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */
224 	u8 NTSC_OFFSET1;
225 } PACKED;
226 
227 /* modes */
228 #define BCM3510_QAM16           =   0x01
229 #define BCM3510_QAM32           =   0x02
230 #define BCM3510_QAM64           =   0x03
231 #define BCM3510_QAM128          =   0x04
232 #define BCM3510_QAM256          =   0x05
233 #define BCM3510_8VSB            =   0x0B
234 #define BCM3510_16VSB           =   0x0D
235 
236 /* IF_FREQS */
237 #define BCM3510_IF_TERRESTRIAL 0x0
238 #define BCM3510_IF_CABLE       0x1
239 #define BCM3510_IF_USE_CMD     0x7
240 
241 /* SYM_RATE */
242 #define BCM3510_SR_8VSB        0x0 /* 5381119 s/sec */
243 #define BCM3510_SR_256QAM      0x1 /* 5360537 s/sec */
244 #define BCM3510_SR_16QAM       0x2 /* 5056971 s/sec */
245 #define BCM3510_SR_MISC        0x3 /* 5000000 s/sec */
246 #define BCM3510_SR_USE_CMD     0x7
247 
248 /* special symbol rate */
249 #define CMD_SET_VALUE_NOT_LISTED  0x2d
250 #define MSGID_SET_SYMBOL_RATE_NOT_LISTED 0x0c
251 struct bcm3510_hab_cmd_set_sr_not_listed {
252 	u8 HOST_SYM_RATE0;
253 	u8 HOST_SYM_RATE1;
254 	u8 HOST_SYM_RATE2;
255 	u8 HOST_SYM_RATE3;
256 } PACKED;
257 
258 /* special IF */
259 #define MSGID_SET_IF_FREQ_NOT_LISTED 0x0d
260 struct bcm3510_hab_cmd_set_if_freq_not_listed {
261 	u8 HOST_IF_FREQ0;
262 	u8 HOST_IF_FREQ1;
263 	u8 HOST_IF_FREQ2;
264 	u8 HOST_IF_FREQ3;
265 } PACKED;
266 
267 /* auto reacquire */
268 #define CMD_AUTO_PARAM       0x2a
269 #define MSGID_AUTO_REACQUIRE 0x0e
270 struct bcm3510_hab_cmd_auto_reacquire {
271 	u8 ACQ    :1; /* on/off*/
272 	u8 unused :7;
273 } PACKED;
274 
275 #define MSGID_SET_RF_AGC_SEL 0x12
276 struct bcm3510_hab_cmd_set_agc {
277 	u8 LVL    :1;
278 	u8 unused :6;
279 	u8 SEL    :1;
280 } PACKED;
281 
282 #define MSGID_SET_AUTO_INVERSION 0x14
283 struct bcm3510_hab_cmd_auto_inversion {
284 	u8 AI     :1;
285 	u8 unused :7;
286 } PACKED;
287 
288 
289 /* bert control */
290 #define CMD_STATE_CONTROL  0x12
291 #define MSGID_BERT_CONTROL 0x0e
292 #define MSGID_BERT_SET     0xfa
293 struct bcm3510_hab_cmd_bert_control {
294 	u8 BE     :1;
295 	u8 unused :7;
296 } PACKED;
297 
298 #define MSGID_TRI_STATE 0x2e
299 struct bcm3510_hab_cmd_tri_state {
300 	u8 RE :1; /* a/d ram port pins */
301 	u8 PE :1; /* baud clock pin */
302 	u8 AC :1; /* a/d clock pin */
303 	u8 BE :1; /* baud clock pin */
304 	u8 unused :4;
305 } PACKED;
306 
307 
308 /* tune */
309 #define CMD_TUNE   0x38
310 #define MSGID_TUNE 0x16
311 struct bcm3510_hab_cmd_tune_ctrl_data_pair {
312 	struct {
313 #define BITS_8 0x07
314 #define BITS_7 0x06
315 #define BITS_6 0x05
316 #define BITS_5 0x04
317 #define BITS_4 0x03
318 #define BITS_3 0x02
319 #define BITS_2 0x01
320 #define BITS_1 0x00
321 		u8 size    :3;
322 		u8 unk     :2;
323 		u8 clk_off :1;
324 		u8 cs0     :1;
325 		u8 cs1     :1;
326 
327 	} PACKED ctrl;
328 
329 	u8 data;
330 } PACKED;
331 
332 struct bcm3510_hab_cmd_tune {
333 	u8 length;
334 	u8 clock_width;
335 	u8 misc;
336 	u8 TUNCTL_state;
337 
338 	struct bcm3510_hab_cmd_tune_ctrl_data_pair ctl_dat[16];
339 } PACKED;
340 
341 #define CMD_STATUS    0x38
342 #define MSGID_STATUS1 0x08
343 struct bcm3510_hab_cmd_status1 {
344 	struct {
345 		u8 EQ_MODE       :4;
346 		u8 reserved      :2;
347 		u8 QRE           :1; /* if QSE and the spectrum is inversed */
348 		u8 QSE           :1; /* automatic spectral inversion */
349 	} PACKED STATUS0;
350 
351 	struct {
352 		u8 RECEIVER_LOCK :1;
353 		u8 FEC_LOCK      :1;
354 		u8 OUT_PLL_LOCK  :1;
355 		u8 reserved      :5;
356 	} PACKED STATUS1;
357 
358 	struct {
359 		u8 reserved      :2;
360 		u8 BW            :1;
361 		u8 NTE           :1; /* NTSC filter sweep enabled */
362 		u8 AQI           :1; /* currently acquiring */
363 		u8 FA            :1; /* fast acquisition */
364 		u8 ARI           :1; /* auto reacquire */
365 		u8 TI            :1; /* programming the tuner */
366 	} PACKED STATUS2;
367 	u8 STATUS3;
368 	u8 SNR_EST0;
369 	u8 SNR_EST1;
370 	u8 TUNER_FREQ0;
371 	u8 TUNER_FREQ1;
372 	u8 TUNER_FREQ2;
373 	u8 TUNER_FREQ3;
374 	u8 SYM_RATE0;
375 	u8 SYM_RATE1;
376 	u8 SYM_RATE2;
377 	u8 SYM_RATE3;
378 	u8 SYM_OFFSET0;
379 	u8 SYM_OFFSET1;
380 	u8 SYM_ERROR0;
381 	u8 SYM_ERROR1;
382 	u8 IF_FREQ0;
383 	u8 IF_FREQ1;
384 	u8 IF_FREQ2;
385 	u8 IF_FREQ3;
386 	u8 IF_OFFSET0;
387 	u8 IF_OFFSET1;
388 	u8 IF_ERROR0;
389 	u8 IF_ERROR1;
390 	u8 NTSC_FILTER0;
391 	u8 NTSC_FILTER1;
392 	u8 NTSC_FILTER2;
393 	u8 NTSC_FILTER3;
394 	u8 NTSC_OFFSET0;
395 	u8 NTSC_OFFSET1;
396 	u8 NTSC_ERROR0;
397 	u8 NTSC_ERROR1;
398 	u8 INT_AGC_LEVEL0;
399 	u8 INT_AGC_LEVEL1;
400 	u8 EXT_AGC_LEVEL0;
401 	u8 EXT_AGC_LEVEL1;
402 } PACKED;
403 
404 #define MSGID_STATUS2 0x14
405 struct bcm3510_hab_cmd_status2 {
406 	struct {
407 		u8 EQ_MODE  :4;
408 		u8 reserved :2;
409 		u8 QRE      :1;
410 		u8 QSR      :1;
411 	} PACKED STATUS0;
412 	struct {
413 		u8 RL       :1;
414 		u8 FL       :1;
415 		u8 OL       :1;
416 		u8 reserved :5;
417 	} PACKED STATUS1;
418 	u8 SYMBOL_RATE0;
419 	u8 SYMBOL_RATE1;
420 	u8 SYMBOL_RATE2;
421 	u8 SYMBOL_RATE3;
422 	u8 LDCERC0;
423 	u8 LDCERC1;
424 	u8 LDCERC2;
425 	u8 LDCERC3;
426 	u8 LDUERC0;
427 	u8 LDUERC1;
428 	u8 LDUERC2;
429 	u8 LDUERC3;
430 	u8 LDBER0;
431 	u8 LDBER1;
432 	u8 LDBER2;
433 	u8 LDBER3;
434 	struct {
435 		u8 MODE_TYPE :4; /* acquire mode 0 */
436 		u8 reservd   :4;
437 	} MODE_TYPE;
438 	u8 SNR_EST0;
439 	u8 SNR_EST1;
440 	u8 SIGNAL;
441 } PACKED;
442 
443 #define CMD_SET_RF_BW_NOT_LISTED   0x3f
444 #define MSGID_SET_RF_BW_NOT_LISTED 0x11
445 /* TODO */
446 
447 #endif
448