1 /*
2   Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
3   All rights reserved.
4 
5   Redistribution and use in source and binary forms, with or without
6   modification, are permitted provided that the following conditions are met:
7 
8   * Redistributions of source code must retain the above copyright notice,
9     this list of conditions and the following disclaimer.
10   * Redistributions in binary form must reproduce the above copyright notice,
11     this list of conditions and the following disclaimer in the documentation
12 	and/or other materials provided with the distribution.
13   * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14     nor the names of its contributors may be used to endorse or promote
15 	products derived from this software without specific prior written
16 	permission.
17 
18   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28   POSSIBILITY OF SUCH DAMAGE.
29 */
30 
31 /*
32  ***********************************************************************************************************************
33  * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE
34  *
35  * Filename:        drxj_map.h
36  * Generated on:    Mon Jan 18 12:09:24 2010
37  * Generated by:    IDF:x 1.3.0
38  * Generated from:  reg_map
39  * Output start:    [entry point]
40  *
41  * filename         last modified               re-use
42  * -----------------------------------------------------
43  * reg_map.1.tmp    Mon Jan 18 12:09:24 2010    -
44  *
45  */
46 
47 #ifndef __DRXJ_MAP__H__
48 #define __DRXJ_MAP__H__ INCLUDED
49 
50 #ifdef _REGISTERTABLE_
51 #include <registertable.h>
52 	extern register_table_t drxj_map[];
53 	extern register_table_info_t drxj_map_info[];
54 #endif
55 
56 #define ATV_COMM_EXEC__A                                                    0xC00000
57 #define ATV_COMM_EXEC__W                                                    2
58 #define ATV_COMM_EXEC__M                                                    0x3
59 #define ATV_COMM_EXEC__PRE                                                  0x0
60 #define   ATV_COMM_EXEC_STOP                                                0x0
61 #define   ATV_COMM_EXEC_ACTIVE                                              0x1
62 #define   ATV_COMM_EXEC_HOLD                                                0x2
63 
64 #define ATV_COMM_STATE__A                                                   0xC00001
65 #define ATV_COMM_STATE__W                                                   16
66 #define ATV_COMM_STATE__M                                                   0xFFFF
67 #define ATV_COMM_STATE__PRE                                                 0x0
68 #define ATV_COMM_MB__A                                                      0xC00002
69 #define ATV_COMM_MB__W                                                      16
70 #define ATV_COMM_MB__M                                                      0xFFFF
71 #define ATV_COMM_MB__PRE                                                    0x0
72 #define ATV_COMM_INT_REQ__A                                                 0xC00003
73 #define ATV_COMM_INT_REQ__W                                                 16
74 #define ATV_COMM_INT_REQ__M                                                 0xFFFF
75 #define ATV_COMM_INT_REQ__PRE                                               0x0
76 #define   ATV_COMM_INT_REQ_COMM_INT_REQ__B                                  0
77 #define   ATV_COMM_INT_REQ_COMM_INT_REQ__W                                  1
78 #define   ATV_COMM_INT_REQ_COMM_INT_REQ__M                                  0x1
79 #define   ATV_COMM_INT_REQ_COMM_INT_REQ__PRE                                0x0
80 
81 #define ATV_COMM_INT_STA__A                                                 0xC00005
82 #define ATV_COMM_INT_STA__W                                                 16
83 #define ATV_COMM_INT_STA__M                                                 0xFFFF
84 #define ATV_COMM_INT_STA__PRE                                               0x0
85 #define ATV_COMM_INT_MSK__A                                                 0xC00006
86 #define ATV_COMM_INT_MSK__W                                                 16
87 #define ATV_COMM_INT_MSK__M                                                 0xFFFF
88 #define ATV_COMM_INT_MSK__PRE                                               0x0
89 #define ATV_COMM_INT_STM__A                                                 0xC00007
90 #define ATV_COMM_INT_STM__W                                                 16
91 #define ATV_COMM_INT_STM__M                                                 0xFFFF
92 #define ATV_COMM_INT_STM__PRE                                               0x0
93 
94 #define ATV_COMM_KEY__A                                                     0xC0000F
95 #define ATV_COMM_KEY__W                                                     16
96 #define ATV_COMM_KEY__M                                                     0xFFFF
97 #define ATV_COMM_KEY__PRE                                                   0x0
98 #define   ATV_COMM_KEY_KEY                                                  0xFABA
99 #define   ATV_COMM_KEY_MIN                                                  0x0
100 #define   ATV_COMM_KEY_MAX                                                  0xFFFF
101 
102 #define ATV_TOP_COMM_EXEC__A                                                0xC10000
103 #define ATV_TOP_COMM_EXEC__W                                                2
104 #define ATV_TOP_COMM_EXEC__M                                                0x3
105 #define ATV_TOP_COMM_EXEC__PRE                                              0x0
106 #define   ATV_TOP_COMM_EXEC_STOP                                            0x0
107 #define   ATV_TOP_COMM_EXEC_ACTIVE                                          0x1
108 #define   ATV_TOP_COMM_EXEC_HOLD                                            0x2
109 
110 #define ATV_TOP_COMM_STATE__A                                               0xC10001
111 #define ATV_TOP_COMM_STATE__W                                               16
112 #define ATV_TOP_COMM_STATE__M                                               0xFFFF
113 #define ATV_TOP_COMM_STATE__PRE                                             0x0
114 #define   ATV_TOP_COMM_STATE_STATE__B                                       0
115 #define   ATV_TOP_COMM_STATE_STATE__W                                       16
116 #define   ATV_TOP_COMM_STATE_STATE__M                                       0xFFFF
117 #define   ATV_TOP_COMM_STATE_STATE__PRE                                     0x0
118 
119 #define ATV_TOP_COMM_MB__A                                                  0xC10002
120 #define ATV_TOP_COMM_MB__W                                                  16
121 #define ATV_TOP_COMM_MB__M                                                  0xFFFF
122 #define ATV_TOP_COMM_MB__PRE                                                0x0
123 #define   ATV_TOP_COMM_MB_CTL__B                                            0
124 #define   ATV_TOP_COMM_MB_CTL__W                                            1
125 #define   ATV_TOP_COMM_MB_CTL__M                                            0x1
126 #define   ATV_TOP_COMM_MB_CTL__PRE                                          0x0
127 #define   ATV_TOP_COMM_MB_OBS__B                                            1
128 #define   ATV_TOP_COMM_MB_OBS__W                                            1
129 #define   ATV_TOP_COMM_MB_OBS__M                                            0x2
130 #define   ATV_TOP_COMM_MB_OBS__PRE                                          0x0
131 
132 #define   ATV_TOP_COMM_MB_MUX_CTRL__B                                       2
133 #define   ATV_TOP_COMM_MB_MUX_CTRL__W                                       4
134 #define   ATV_TOP_COMM_MB_MUX_CTRL__M                                       0x3C
135 #define   ATV_TOP_COMM_MB_MUX_CTRL__PRE                                     0x0
136 #define     ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S                                 0x0
137 #define     ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN                               0x4
138 #define     ATV_TOP_COMM_MB_MUX_CTRL_CORR_O                                 0x8
139 #define     ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O                               0xC
140 #define     ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ                              0x10
141 #define     ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O                                0x14
142 #define     ATV_TOP_COMM_MB_MUX_CTRL_SIF_O                                  0x18
143 #define     ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O                              0x1C
144 #define     ATV_TOP_COMM_MB_MUX_CTRL_POST_S                                 0x20
145 
146 #define   ATV_TOP_COMM_MB_MUX_OBS__B                                        6
147 #define   ATV_TOP_COMM_MB_MUX_OBS__W                                        4
148 #define   ATV_TOP_COMM_MB_MUX_OBS__M                                        0x3C0
149 #define   ATV_TOP_COMM_MB_MUX_OBS__PRE                                      0x0
150 #define     ATV_TOP_COMM_MB_MUX_OBS_PEAK_S                                  0x0
151 #define     ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN                                0x40
152 #define     ATV_TOP_COMM_MB_MUX_OBS_CORR_O                                  0x80
153 #define     ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O                                0xC0
154 #define     ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ                               0x100
155 #define     ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O                                 0x140
156 #define     ATV_TOP_COMM_MB_MUX_OBS_SIF_O                                   0x180
157 #define     ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O                               0x1C0
158 #define     ATV_TOP_COMM_MB_MUX_OBS_POST_S                                  0x200
159 
160 #define ATV_TOP_COMM_INT_REQ__A                                             0xC10003
161 #define ATV_TOP_COMM_INT_REQ__W                                             16
162 #define ATV_TOP_COMM_INT_REQ__M                                             0xFFFF
163 #define ATV_TOP_COMM_INT_REQ__PRE                                           0x0
164 #define ATV_TOP_COMM_INT_STA__A                                             0xC10005
165 #define ATV_TOP_COMM_INT_STA__W                                             16
166 #define ATV_TOP_COMM_INT_STA__M                                             0xFFFF
167 #define ATV_TOP_COMM_INT_STA__PRE                                           0x0
168 
169 #define   ATV_TOP_COMM_INT_STA_FAGC_STA__B                                  0
170 #define   ATV_TOP_COMM_INT_STA_FAGC_STA__W                                  1
171 #define   ATV_TOP_COMM_INT_STA_FAGC_STA__M                                  0x1
172 #define   ATV_TOP_COMM_INT_STA_FAGC_STA__PRE                                0x0
173 
174 #define   ATV_TOP_COMM_INT_STA_OVM_STA__B                                   1
175 #define   ATV_TOP_COMM_INT_STA_OVM_STA__W                                   1
176 #define   ATV_TOP_COMM_INT_STA_OVM_STA__M                                   0x2
177 #define   ATV_TOP_COMM_INT_STA_OVM_STA__PRE                                 0x0
178 
179 #define   ATV_TOP_COMM_INT_STA_AMPTH_STA__B                                 2
180 #define   ATV_TOP_COMM_INT_STA_AMPTH_STA__W                                 1
181 #define   ATV_TOP_COMM_INT_STA_AMPTH_STA__M                                 0x4
182 #define   ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE                               0x0
183 
184 #define ATV_TOP_COMM_INT_MSK__A                                             0xC10006
185 #define ATV_TOP_COMM_INT_MSK__W                                             16
186 #define ATV_TOP_COMM_INT_MSK__M                                             0xFFFF
187 #define ATV_TOP_COMM_INT_MSK__PRE                                           0x0
188 
189 #define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__B                                  0
190 #define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__W                                  1
191 #define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__M                                  0x1
192 #define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE                                0x0
193 
194 #define   ATV_TOP_COMM_INT_MSK_OVM_MSK__B                                   1
195 #define   ATV_TOP_COMM_INT_MSK_OVM_MSK__W                                   1
196 #define   ATV_TOP_COMM_INT_MSK_OVM_MSK__M                                   0x2
197 #define   ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE                                 0x0
198 
199 #define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B                                 2
200 #define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W                                 1
201 #define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M                                 0x4
202 #define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE                               0x0
203 
204 #define ATV_TOP_COMM_INT_STM__A                                             0xC10007
205 #define ATV_TOP_COMM_INT_STM__W                                             16
206 #define ATV_TOP_COMM_INT_STM__M                                             0xFFFF
207 #define ATV_TOP_COMM_INT_STM__PRE                                           0x0
208 
209 #define   ATV_TOP_COMM_INT_STM_FAGC_STM__B                                  0
210 #define   ATV_TOP_COMM_INT_STM_FAGC_STM__W                                  1
211 #define   ATV_TOP_COMM_INT_STM_FAGC_STM__M                                  0x1
212 #define   ATV_TOP_COMM_INT_STM_FAGC_STM__PRE                                0x0
213 
214 #define   ATV_TOP_COMM_INT_STM_OVM_STM__B                                   1
215 #define   ATV_TOP_COMM_INT_STM_OVM_STM__W                                   1
216 #define   ATV_TOP_COMM_INT_STM_OVM_STM__M                                   0x2
217 #define   ATV_TOP_COMM_INT_STM_OVM_STM__PRE                                 0x0
218 
219 #define   ATV_TOP_COMM_INT_STM_AMPTH_STM__B                                 2
220 #define   ATV_TOP_COMM_INT_STM_AMPTH_STM__W                                 1
221 #define   ATV_TOP_COMM_INT_STM_AMPTH_STM__M                                 0x4
222 #define   ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE                               0x0
223 
224 #define ATV_TOP_COMM_KEY__A                                                 0xC1000F
225 #define ATV_TOP_COMM_KEY__W                                                 16
226 #define ATV_TOP_COMM_KEY__M                                                 0xFFFF
227 #define ATV_TOP_COMM_KEY__PRE                                               0x0
228 
229 #define   ATV_TOP_COMM_KEY_KEY__B                                           0
230 #define   ATV_TOP_COMM_KEY_KEY__W                                           16
231 #define   ATV_TOP_COMM_KEY_KEY__M                                           0xFFFF
232 #define   ATV_TOP_COMM_KEY_KEY__PRE                                         0x0
233 #define     ATV_TOP_COMM_KEY_KEY_KEY                                        0xFABA
234 #define     ATV_TOP_COMM_KEY_KEY_MIN                                        0x0
235 #define     ATV_TOP_COMM_KEY_KEY_MAX                                        0xFFFF
236 
237 #define ATV_TOP_CR_AMP_TH__A                                                0xC10010
238 #define ATV_TOP_CR_AMP_TH__W                                                8
239 #define ATV_TOP_CR_AMP_TH__M                                                0xFF
240 #define ATV_TOP_CR_AMP_TH__PRE                                              0x8
241 #define   ATV_TOP_CR_AMP_TH_MN                                              0x8
242 
243 #define ATV_TOP_CR_CONT__A                                                  0xC10011
244 #define ATV_TOP_CR_CONT__W                                                  9
245 #define ATV_TOP_CR_CONT__M                                                  0x1FF
246 #define ATV_TOP_CR_CONT__PRE                                                0x9C
247 
248 #define   ATV_TOP_CR_CONT_CR_P__B                                           0
249 #define   ATV_TOP_CR_CONT_CR_P__W                                           3
250 #define   ATV_TOP_CR_CONT_CR_P__M                                           0x7
251 #define   ATV_TOP_CR_CONT_CR_P__PRE                                         0x4
252 #define     ATV_TOP_CR_CONT_CR_P_MN                                         0x4
253 #define     ATV_TOP_CR_CONT_CR_P_FM                                         0x0
254 
255 #define   ATV_TOP_CR_CONT_CR_D__B                                           3
256 #define   ATV_TOP_CR_CONT_CR_D__W                                           3
257 #define   ATV_TOP_CR_CONT_CR_D__M                                           0x38
258 #define   ATV_TOP_CR_CONT_CR_D__PRE                                         0x18
259 #define     ATV_TOP_CR_CONT_CR_D_MN                                         0x18
260 #define     ATV_TOP_CR_CONT_CR_D_FM                                         0x0
261 
262 #define   ATV_TOP_CR_CONT_CR_I__B                                           6
263 #define   ATV_TOP_CR_CONT_CR_I__W                                           3
264 #define   ATV_TOP_CR_CONT_CR_I__M                                           0x1C0
265 #define   ATV_TOP_CR_CONT_CR_I__PRE                                         0x80
266 #define     ATV_TOP_CR_CONT_CR_I_MN                                         0x80
267 #define     ATV_TOP_CR_CONT_CR_I_FM                                         0x0
268 
269 #define ATV_TOP_CR_OVM_TH__A                                                0xC10012
270 #define ATV_TOP_CR_OVM_TH__W                                                8
271 #define ATV_TOP_CR_OVM_TH__M                                                0xFF
272 #define ATV_TOP_CR_OVM_TH__PRE                                              0xA0
273 #define   ATV_TOP_CR_OVM_TH_MN                                              0xA0
274 #define   ATV_TOP_CR_OVM_TH_FM                                              0x0
275 
276 #define ATV_TOP_NOISE_TH__A                                                 0xC10013
277 #define ATV_TOP_NOISE_TH__W                                                 4
278 #define ATV_TOP_NOISE_TH__M                                                 0xF
279 #define ATV_TOP_NOISE_TH__PRE                                               0x8
280 #define   ATV_TOP_NOISE_TH_MN                                               0x8
281 
282 #define ATV_TOP_EQU0__A                                                     0xC10014
283 #define ATV_TOP_EQU0__W                                                     9
284 #define ATV_TOP_EQU0__M                                                     0x1FF
285 #define ATV_TOP_EQU0__PRE                                                   0x1FB
286 
287 #define   ATV_TOP_EQU0_EQU_C0__B                                            0
288 #define   ATV_TOP_EQU0_EQU_C0__W                                            9
289 #define   ATV_TOP_EQU0_EQU_C0__M                                            0x1FF
290 #define   ATV_TOP_EQU0_EQU_C0__PRE                                          0x1FB
291 #define     ATV_TOP_EQU0_EQU_C0_MN                                          0xFB
292 
293 #define ATV_TOP_EQU1__A                                                     0xC10015
294 #define ATV_TOP_EQU1__W                                                     9
295 #define ATV_TOP_EQU1__M                                                     0x1FF
296 #define ATV_TOP_EQU1__PRE                                                   0x1CE
297 
298 #define   ATV_TOP_EQU1_EQU_C1__B                                            0
299 #define   ATV_TOP_EQU1_EQU_C1__W                                            9
300 #define   ATV_TOP_EQU1_EQU_C1__M                                            0x1FF
301 #define   ATV_TOP_EQU1_EQU_C1__PRE                                          0x1CE
302 #define     ATV_TOP_EQU1_EQU_C1_MN                                          0xCE
303 
304 #define ATV_TOP_EQU2__A                                                     0xC10016
305 #define ATV_TOP_EQU2__W                                                     9
306 #define ATV_TOP_EQU2__M                                                     0x1FF
307 #define ATV_TOP_EQU2__PRE                                                   0xD2
308 
309 #define   ATV_TOP_EQU2_EQU_C2__B                                            0
310 #define   ATV_TOP_EQU2_EQU_C2__W                                            9
311 #define   ATV_TOP_EQU2_EQU_C2__M                                            0x1FF
312 #define   ATV_TOP_EQU2_EQU_C2__PRE                                          0xD2
313 #define     ATV_TOP_EQU2_EQU_C2_MN                                          0xD2
314 
315 #define ATV_TOP_EQU3__A                                                     0xC10017
316 #define ATV_TOP_EQU3__W                                                     9
317 #define ATV_TOP_EQU3__M                                                     0x1FF
318 #define ATV_TOP_EQU3__PRE                                                   0x160
319 
320 #define   ATV_TOP_EQU3_EQU_C3__B                                            0
321 #define   ATV_TOP_EQU3_EQU_C3__W                                            9
322 #define   ATV_TOP_EQU3_EQU_C3__M                                            0x1FF
323 #define   ATV_TOP_EQU3_EQU_C3__PRE                                          0x160
324 #define     ATV_TOP_EQU3_EQU_C3_MN                                          0x60
325 
326 #define ATV_TOP_ROT_MODE__A                                                 0xC10018
327 #define ATV_TOP_ROT_MODE__W                                                 1
328 #define ATV_TOP_ROT_MODE__M                                                 0x1
329 #define ATV_TOP_ROT_MODE__PRE                                               0x0
330 #define   ATV_TOP_ROT_MODE_AMPTH_DEPEND                                     0x0
331 #define   ATV_TOP_ROT_MODE_ALWAYS                                           0x1
332 
333 #define ATV_TOP_MOD_CONTROL__A                                              0xC10019
334 #define ATV_TOP_MOD_CONTROL__W                                              12
335 #define ATV_TOP_MOD_CONTROL__M                                              0xFFF
336 #define ATV_TOP_MOD_CONTROL__PRE                                            0x5B1
337 
338 #define   ATV_TOP_MOD_CONTROL_MOD_IR__B                                     0
339 #define   ATV_TOP_MOD_CONTROL_MOD_IR__W                                     3
340 #define   ATV_TOP_MOD_CONTROL_MOD_IR__M                                     0x7
341 #define   ATV_TOP_MOD_CONTROL_MOD_IR__PRE                                   0x1
342 #define     ATV_TOP_MOD_CONTROL_MOD_IR_MN                                   0x1
343 #define     ATV_TOP_MOD_CONTROL_MOD_IR_FM                                   0x0
344 
345 #define   ATV_TOP_MOD_CONTROL_MOD_IF__B                                     3
346 #define   ATV_TOP_MOD_CONTROL_MOD_IF__W                                     4
347 #define   ATV_TOP_MOD_CONTROL_MOD_IF__M                                     0x78
348 #define   ATV_TOP_MOD_CONTROL_MOD_IF__PRE                                   0x30
349 #define     ATV_TOP_MOD_CONTROL_MOD_IF_MN                                   0x30
350 #define     ATV_TOP_MOD_CONTROL_MOD_IF_FM                                   0x0
351 
352 #define   ATV_TOP_MOD_CONTROL_MOD_MODE__B                                   7
353 #define   ATV_TOP_MOD_CONTROL_MOD_MODE__W                                   1
354 #define   ATV_TOP_MOD_CONTROL_MOD_MODE__M                                   0x80
355 #define   ATV_TOP_MOD_CONTROL_MOD_MODE__PRE                                 0x80
356 #define     ATV_TOP_MOD_CONTROL_MOD_MODE_RISE                               0x0
357 #define     ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL                          0x80
358 
359 #define   ATV_TOP_MOD_CONTROL_MOD_TH__B                                     8
360 #define   ATV_TOP_MOD_CONTROL_MOD_TH__W                                     4
361 #define   ATV_TOP_MOD_CONTROL_MOD_TH__M                                     0xF00
362 #define   ATV_TOP_MOD_CONTROL_MOD_TH__PRE                                   0x500
363 #define     ATV_TOP_MOD_CONTROL_MOD_TH_MN                                   0x500
364 #define     ATV_TOP_MOD_CONTROL_MOD_TH_FM                                   0x0
365 
366 #define ATV_TOP_STD__A                                                      0xC1001A
367 #define ATV_TOP_STD__W                                                      2
368 #define ATV_TOP_STD__M                                                      0x3
369 #define ATV_TOP_STD__PRE                                                    0x0
370 
371 #define   ATV_TOP_STD_MODE__B                                               0
372 #define   ATV_TOP_STD_MODE__W                                               1
373 #define   ATV_TOP_STD_MODE__M                                               0x1
374 #define   ATV_TOP_STD_MODE__PRE                                             0x0
375 #define     ATV_TOP_STD_MODE_MN                                             0x0
376 #define     ATV_TOP_STD_MODE_FM                                             0x1
377 
378 #define   ATV_TOP_STD_VID_POL__B                                            1
379 #define   ATV_TOP_STD_VID_POL__W                                            1
380 #define   ATV_TOP_STD_VID_POL__M                                            0x2
381 #define   ATV_TOP_STD_VID_POL__PRE                                          0x0
382 #define     ATV_TOP_STD_VID_POL_NEG                                         0x0
383 #define     ATV_TOP_STD_VID_POL_POS                                         0x2
384 
385 #define ATV_TOP_VID_AMP__A                                                  0xC1001B
386 #define ATV_TOP_VID_AMP__W                                                  12
387 #define ATV_TOP_VID_AMP__M                                                  0xFFF
388 #define ATV_TOP_VID_AMP__PRE                                                0x380
389 #define   ATV_TOP_VID_AMP_MN                                                0x380
390 #define   ATV_TOP_VID_AMP_FM                                                0x0
391 
392 #define ATV_TOP_VID_PEAK__A                                                 0xC1001C
393 #define ATV_TOP_VID_PEAK__W                                                 5
394 #define ATV_TOP_VID_PEAK__M                                                 0x1F
395 #define ATV_TOP_VID_PEAK__PRE                                               0x1
396 
397 #define ATV_TOP_FAGC_TH__A                                                  0xC1001D
398 #define ATV_TOP_FAGC_TH__W                                                  11
399 #define ATV_TOP_FAGC_TH__M                                                  0x7FF
400 #define ATV_TOP_FAGC_TH__PRE                                                0x2B2
401 #define   ATV_TOP_FAGC_TH_MN                                                0x2B2
402 
403 #define ATV_TOP_SYNC_SLICE__A                                               0xC1001E
404 #define ATV_TOP_SYNC_SLICE__W                                               11
405 #define ATV_TOP_SYNC_SLICE__M                                               0x7FF
406 #define ATV_TOP_SYNC_SLICE__PRE                                             0x243
407 #define   ATV_TOP_SYNC_SLICE_MN                                             0x243
408 
409 #define ATV_TOP_SIF_GAIN__A                                                 0xC1001F
410 #define ATV_TOP_SIF_GAIN__W                                                 11
411 #define ATV_TOP_SIF_GAIN__M                                                 0x7FF
412 #define ATV_TOP_SIF_GAIN__PRE                                               0x0
413 
414 #define ATV_TOP_SIF_TP__A                                                   0xC10020
415 #define ATV_TOP_SIF_TP__W                                                   6
416 #define ATV_TOP_SIF_TP__M                                                   0x3F
417 #define ATV_TOP_SIF_TP__PRE                                                 0x0
418 
419 #define ATV_TOP_MOD_ACCU__A                                                 0xC10021
420 #define ATV_TOP_MOD_ACCU__W                                                 10
421 #define ATV_TOP_MOD_ACCU__M                                                 0x3FF
422 #define ATV_TOP_MOD_ACCU__PRE                                               0x0
423 
424 #define ATV_TOP_CR_FREQ__A                                                  0xC10022
425 #define ATV_TOP_CR_FREQ__W                                                  8
426 #define ATV_TOP_CR_FREQ__M                                                  0xFF
427 #define ATV_TOP_CR_FREQ__PRE                                                0x0
428 
429 #define ATV_TOP_CR_PHAD__A                                                  0xC10023
430 #define ATV_TOP_CR_PHAD__W                                                  12
431 #define ATV_TOP_CR_PHAD__M                                                  0xFFF
432 #define ATV_TOP_CR_PHAD__PRE                                                0x0
433 
434 #define ATV_TOP_AF_SIF_ATT__A                                               0xC10024
435 #define ATV_TOP_AF_SIF_ATT__W                                               2
436 #define ATV_TOP_AF_SIF_ATT__M                                               0x3
437 #define ATV_TOP_AF_SIF_ATT__PRE                                             0x0
438 #define   ATV_TOP_AF_SIF_ATT_0DB                                            0x0
439 #define   ATV_TOP_AF_SIF_ATT_M3DB                                           0x1
440 #define   ATV_TOP_AF_SIF_ATT_M6DB                                           0x2
441 #define   ATV_TOP_AF_SIF_ATT_M9DB                                           0x3
442 
443 #define ATV_TOP_STDBY__A                                                    0xC10025
444 #define ATV_TOP_STDBY__W                                                    2
445 #define ATV_TOP_STDBY__M                                                    0x3
446 #define ATV_TOP_STDBY__PRE                                                  0x1
447 
448 #define   ATV_TOP_STDBY_SIF_STDBY__B                                        0
449 #define   ATV_TOP_STDBY_SIF_STDBY__W                                        1
450 #define   ATV_TOP_STDBY_SIF_STDBY__M                                        0x1
451 #define   ATV_TOP_STDBY_SIF_STDBY__PRE                                      0x1
452 #define     ATV_TOP_STDBY_SIF_STDBY_ACTIVE                                  0x0
453 #define     ATV_TOP_STDBY_SIF_STDBY_STANDBY                                 0x1
454 
455 #define   ATV_TOP_STDBY_CVBS_STDBY__B                                       1
456 #define   ATV_TOP_STDBY_CVBS_STDBY__W                                       1
457 #define   ATV_TOP_STDBY_CVBS_STDBY__M                                       0x2
458 #define   ATV_TOP_STDBY_CVBS_STDBY__PRE                                     0x0
459 #define     ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE                              0x0
460 #define     ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY                             0x2
461 #define     ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE                              0x2
462 #define     ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY                             0x0
463 
464 #define ATV_TOP_OVERRIDE_SFR__A                                             0xC10026
465 #define ATV_TOP_OVERRIDE_SFR__W                                             1
466 #define ATV_TOP_OVERRIDE_SFR__M                                             0x1
467 #define ATV_TOP_OVERRIDE_SFR__PRE                                           0x0
468 #define   ATV_TOP_OVERRIDE_SFR_ACTIVE                                       0x0
469 #define   ATV_TOP_OVERRIDE_SFR_OVERRIDE                                     0x1
470 
471 #define ATV_TOP_SFR_VID_GAIN__A                                             0xC10027
472 #define ATV_TOP_SFR_VID_GAIN__W                                             16
473 #define ATV_TOP_SFR_VID_GAIN__M                                             0xFFFF
474 #define ATV_TOP_SFR_VID_GAIN__PRE                                           0x0
475 
476 #define ATV_TOP_SFR_AGC_RES__A                                              0xC10028
477 #define ATV_TOP_SFR_AGC_RES__W                                              5
478 #define ATV_TOP_SFR_AGC_RES__M                                              0x1F
479 #define ATV_TOP_SFR_AGC_RES__PRE                                            0x0
480 
481 #define ATV_TOP_OVM_COMP__A                                                 0xC10029
482 #define ATV_TOP_OVM_COMP__W                                                 12
483 #define ATV_TOP_OVM_COMP__M                                                 0xFFF
484 #define ATV_TOP_OVM_COMP__PRE                                               0x0
485 #define ATV_TOP_OUT_CONF__A                                                 0xC1002A
486 #define ATV_TOP_OUT_CONF__W                                                 5
487 #define ATV_TOP_OUT_CONF__M                                                 0x1F
488 #define ATV_TOP_OUT_CONF__PRE                                               0x0
489 
490 #define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B                                 0
491 #define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W                                 1
492 #define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M                                 0x1
493 #define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE                               0x0
494 #define     ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED                         0x0
495 #define     ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED                           0x1
496 
497 #define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B                                  1
498 #define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W                                  1
499 #define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M                                  0x2
500 #define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE                                0x0
501 #define     ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED                          0x0
502 #define     ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED                            0x2
503 
504 #define   ATV_TOP_OUT_CONF_SIF20_SIGN__B                                    2
505 #define   ATV_TOP_OUT_CONF_SIF20_SIGN__W                                    1
506 #define   ATV_TOP_OUT_CONF_SIF20_SIGN__M                                    0x4
507 #define   ATV_TOP_OUT_CONF_SIF20_SIGN__PRE                                  0x0
508 #define     ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED                            0x0
509 #define     ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED                              0x4
510 
511 #define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__B                                   3
512 #define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__W                                   1
513 #define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__M                                   0x8
514 #define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE                                 0x0
515 #define     ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL                             0x0
516 #define     ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED                        0x8
517 
518 #define   ATV_TOP_OUT_CONF_SIF_DAC_BR__B                                    4
519 #define   ATV_TOP_OUT_CONF_SIF_DAC_BR__W                                    1
520 #define   ATV_TOP_OUT_CONF_SIF_DAC_BR__M                                    0x10
521 #define   ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE                                  0x0
522 #define     ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL                              0x0
523 #define     ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED                         0x10
524 
525 #define ATV_AFT_COMM_EXEC__A                                                0xFF0000
526 #define ATV_AFT_COMM_EXEC__W                                                2
527 #define ATV_AFT_COMM_EXEC__M                                                0x3
528 #define ATV_AFT_COMM_EXEC__PRE                                              0x0
529 #define   ATV_AFT_COMM_EXEC_STOP                                            0x0
530 #define   ATV_AFT_COMM_EXEC_ACTIVE                                          0x1
531 #define   ATV_AFT_COMM_EXEC_HOLD                                            0x2
532 
533 #define ATV_AFT_TST__A                                                      0xFF0010
534 #define ATV_AFT_TST__W                                                      4
535 #define ATV_AFT_TST__M                                                      0xF
536 #define ATV_AFT_TST__PRE                                                    0x0
537 
538 #define AUD_COMM_EXEC__A                                                    0x1000000
539 #define AUD_COMM_EXEC__W                                                    2
540 #define AUD_COMM_EXEC__M                                                    0x3
541 #define AUD_COMM_EXEC__PRE                                                  0x0
542 #define   AUD_COMM_EXEC_STOP                                                0x0
543 #define   AUD_COMM_EXEC_ACTIVE                                              0x1
544 
545 #define AUD_COMM_MB__A                                                      0x1000002
546 #define AUD_COMM_MB__W                                                      16
547 #define AUD_COMM_MB__M                                                      0xFFFF
548 #define AUD_COMM_MB__PRE                                                    0x0
549 
550 #define AUD_TOP_COMM_EXEC__A                                                0x1010000
551 #define AUD_TOP_COMM_EXEC__W                                                2
552 #define AUD_TOP_COMM_EXEC__M                                                0x3
553 #define AUD_TOP_COMM_EXEC__PRE                                              0x0
554 #define   AUD_TOP_COMM_EXEC_STOP                                            0x0
555 #define   AUD_TOP_COMM_EXEC_ACTIVE                                          0x1
556 
557 #define AUD_TOP_COMM_MB__A                                                  0x1010002
558 #define AUD_TOP_COMM_MB__W                                                  16
559 #define AUD_TOP_COMM_MB__M                                                  0xFFFF
560 #define AUD_TOP_COMM_MB__PRE                                                0x0
561 
562 #define   AUD_TOP_COMM_MB_CTL__B                                            0
563 #define   AUD_TOP_COMM_MB_CTL__W                                            1
564 #define   AUD_TOP_COMM_MB_CTL__M                                            0x1
565 #define   AUD_TOP_COMM_MB_CTL__PRE                                          0x0
566 #define     AUD_TOP_COMM_MB_CTL_CTR_OFF                                     0x0
567 #define     AUD_TOP_COMM_MB_CTL_CTR_ON                                      0x1
568 
569 #define   AUD_TOP_COMM_MB_OBS__B                                            1
570 #define   AUD_TOP_COMM_MB_OBS__W                                            1
571 #define   AUD_TOP_COMM_MB_OBS__M                                            0x2
572 #define   AUD_TOP_COMM_MB_OBS__PRE                                          0x0
573 #define     AUD_TOP_COMM_MB_OBS_OBS_OFF                                     0x0
574 #define     AUD_TOP_COMM_MB_OBS_OBS_ON                                      0x2
575 
576 #define   AUD_TOP_COMM_MB_MUX_CTRL__B                                       2
577 #define   AUD_TOP_COMM_MB_MUX_CTRL__W                                       4
578 #define   AUD_TOP_COMM_MB_MUX_CTRL__M                                       0x3C
579 #define   AUD_TOP_COMM_MB_MUX_CTRL__PRE                                     0x0
580 #define     AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO                              0x0
581 #define     AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS                              0x4
582 #define     AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC                              0x8
583 #define     AUD_TOP_COMM_MB_MUX_CTRL_SAOUT                                  0xC
584 #define     AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ                             0x10
585 
586 #define   AUD_TOP_COMM_MB_MUX_OBS__B                                        6
587 #define   AUD_TOP_COMM_MB_MUX_OBS__W                                        4
588 #define   AUD_TOP_COMM_MB_MUX_OBS__M                                        0x3C0
589 #define   AUD_TOP_COMM_MB_MUX_OBS__PRE                                      0x0
590 #define     AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO                               0x0
591 #define     AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS                               0x40
592 #define     AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC                               0x80
593 #define     AUD_TOP_COMM_MB_MUX_OBS_SAOUT                                   0xC0
594 #define     AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ                              0x100
595 
596 #define AUD_TOP_TR_MDE__A                                                   0x1010010
597 #define AUD_TOP_TR_MDE__W                                                   5
598 #define AUD_TOP_TR_MDE__M                                                   0x1F
599 #define AUD_TOP_TR_MDE__PRE                                                 0x18
600 
601 #define   AUD_TOP_TR_MDE_FIFO_SIZE__B                                       0
602 #define   AUD_TOP_TR_MDE_FIFO_SIZE__W                                       4
603 #define   AUD_TOP_TR_MDE_FIFO_SIZE__M                                       0xF
604 #define   AUD_TOP_TR_MDE_FIFO_SIZE__PRE                                     0x8
605 
606 #define   AUD_TOP_TR_MDE_RD_LOCK__B                                         4
607 #define   AUD_TOP_TR_MDE_RD_LOCK__W                                         1
608 #define   AUD_TOP_TR_MDE_RD_LOCK__M                                         0x10
609 #define   AUD_TOP_TR_MDE_RD_LOCK__PRE                                       0x10
610 #define     AUD_TOP_TR_MDE_RD_LOCK_NORMAL                                   0x0
611 #define     AUD_TOP_TR_MDE_RD_LOCK_LOCK                                     0x10
612 
613 #define AUD_TOP_TR_CTR__A                                                   0x1010011
614 #define AUD_TOP_TR_CTR__W                                                   4
615 #define AUD_TOP_TR_CTR__M                                                   0xF
616 #define AUD_TOP_TR_CTR__PRE                                                 0x0
617 
618 #define   AUD_TOP_TR_CTR_FIFO_RD_RDY__B                                     0
619 #define   AUD_TOP_TR_CTR_FIFO_RD_RDY__W                                     1
620 #define   AUD_TOP_TR_CTR_FIFO_RD_RDY__M                                     0x1
621 #define   AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE                                   0x0
622 #define     AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY                            0x0
623 #define     AUD_TOP_TR_CTR_FIFO_RD_RDY_READY                                0x1
624 
625 #define   AUD_TOP_TR_CTR_FIFO_EMPTY__B                                      1
626 #define   AUD_TOP_TR_CTR_FIFO_EMPTY__W                                      1
627 #define   AUD_TOP_TR_CTR_FIFO_EMPTY__M                                      0x2
628 #define   AUD_TOP_TR_CTR_FIFO_EMPTY__PRE                                    0x0
629 #define     AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY                             0x0
630 #define     AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY                                 0x2
631 
632 #define   AUD_TOP_TR_CTR_FIFO_LOCK__B                                       2
633 #define   AUD_TOP_TR_CTR_FIFO_LOCK__W                                       1
634 #define   AUD_TOP_TR_CTR_FIFO_LOCK__M                                       0x4
635 #define   AUD_TOP_TR_CTR_FIFO_LOCK__PRE                                     0x0
636 #define     AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED                               0x0
637 #define     AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED                                 0x4
638 
639 #define   AUD_TOP_TR_CTR_FIFO_FULL__B                                       3
640 #define   AUD_TOP_TR_CTR_FIFO_FULL__W                                       1
641 #define   AUD_TOP_TR_CTR_FIFO_FULL__M                                       0x8
642 #define   AUD_TOP_TR_CTR_FIFO_FULL__PRE                                     0x0
643 #define     AUD_TOP_TR_CTR_FIFO_FULL_EMPTY                                  0x0
644 #define     AUD_TOP_TR_CTR_FIFO_FULL_FULL                                   0x8
645 
646 #define AUD_TOP_TR_RD_REG__A                                                0x1010012
647 #define AUD_TOP_TR_RD_REG__W                                                16
648 #define AUD_TOP_TR_RD_REG__M                                                0xFFFF
649 #define AUD_TOP_TR_RD_REG__PRE                                              0x0
650 
651 #define   AUD_TOP_TR_RD_REG_RESULT__B                                       0
652 #define   AUD_TOP_TR_RD_REG_RESULT__W                                       16
653 #define   AUD_TOP_TR_RD_REG_RESULT__M                                       0xFFFF
654 #define   AUD_TOP_TR_RD_REG_RESULT__PRE                                     0x0
655 
656 #define AUD_TOP_TR_TIMER__A                                                 0x1010013
657 #define AUD_TOP_TR_TIMER__W                                                 16
658 #define AUD_TOP_TR_TIMER__M                                                 0xFFFF
659 #define AUD_TOP_TR_TIMER__PRE                                               0x0
660 
661 #define   AUD_TOP_TR_TIMER_CYCLES__B                                        0
662 #define   AUD_TOP_TR_TIMER_CYCLES__W                                        16
663 #define   AUD_TOP_TR_TIMER_CYCLES__M                                        0xFFFF
664 #define   AUD_TOP_TR_TIMER_CYCLES__PRE                                      0x0
665 
666 #define AUD_TOP_DEMOD_TBO_SEL__A                                            0x1010014
667 #define AUD_TOP_DEMOD_TBO_SEL__W                                            5
668 #define AUD_TOP_DEMOD_TBO_SEL__M                                            0x1F
669 #define AUD_TOP_DEMOD_TBO_SEL__PRE                                          0x0
670 
671 #define AUD_DEM_WR_MODUS__A                                                 0x1030030
672 #define AUD_DEM_WR_MODUS__W                                                 16
673 #define AUD_DEM_WR_MODUS__M                                                 0xFFFF
674 #define AUD_DEM_WR_MODUS__PRE                                               0x0
675 
676 #define   AUD_DEM_WR_MODUS_MOD_ASS__B                                       0
677 #define   AUD_DEM_WR_MODUS_MOD_ASS__W                                       1
678 #define   AUD_DEM_WR_MODUS_MOD_ASS__M                                       0x1
679 #define   AUD_DEM_WR_MODUS_MOD_ASS__PRE                                     0x0
680 #define     AUD_DEM_WR_MODUS_MOD_ASS_OFF                                    0x0
681 #define     AUD_DEM_WR_MODUS_MOD_ASS_ON                                     0x1
682 
683 #define   AUD_DEM_WR_MODUS_MOD_STATINTERR__B                                1
684 #define   AUD_DEM_WR_MODUS_MOD_STATINTERR__W                                1
685 #define   AUD_DEM_WR_MODUS_MOD_STATINTERR__M                                0x2
686 #define   AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE                              0x0
687 #define     AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE                         0x0
688 #define     AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE                          0x2
689 
690 #define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B                               2
691 #define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W                               1
692 #define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M                               0x4
693 #define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE                             0x0
694 #define     AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED                        0x0
695 #define     AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED                       0x4
696 
697 #define   AUD_DEM_WR_MODUS_MOD_HDEV_A__B                                    8
698 #define   AUD_DEM_WR_MODUS_MOD_HDEV_A__W                                    1
699 #define   AUD_DEM_WR_MODUS_MOD_HDEV_A__M                                    0x100
700 #define   AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE                                  0x0
701 #define     AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL                              0x0
702 #define     AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION                      0x100
703 
704 #define   AUD_DEM_WR_MODUS_MOD_CM_A__B                                      9
705 #define   AUD_DEM_WR_MODUS_MOD_CM_A__W                                      1
706 #define   AUD_DEM_WR_MODUS_MOD_CM_A__M                                      0x200
707 #define   AUD_DEM_WR_MODUS_MOD_CM_A__PRE                                    0x0
708 #define     AUD_DEM_WR_MODUS_MOD_CM_A_MUTE                                  0x0
709 #define     AUD_DEM_WR_MODUS_MOD_CM_A_NOISE                                 0x200
710 
711 #define   AUD_DEM_WR_MODUS_MOD_CM_B__B                                      10
712 #define   AUD_DEM_WR_MODUS_MOD_CM_B__W                                      1
713 #define   AUD_DEM_WR_MODUS_MOD_CM_B__M                                      0x400
714 #define   AUD_DEM_WR_MODUS_MOD_CM_B__PRE                                    0x0
715 #define     AUD_DEM_WR_MODUS_MOD_CM_B_MUTE                                  0x0
716 #define     AUD_DEM_WR_MODUS_MOD_CM_B_NOISE                                 0x400
717 
718 #define   AUD_DEM_WR_MODUS_MOD_FMRADIO__B                                   11
719 #define   AUD_DEM_WR_MODUS_MOD_FMRADIO__W                                   1
720 #define   AUD_DEM_WR_MODUS_MOD_FMRADIO__M                                   0x800
721 #define   AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE                                 0x0
722 #define     AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U                             0x0
723 #define     AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U                             0x800
724 
725 #define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__B                                    12
726 #define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__W                                    1
727 #define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__M                                    0x1000
728 #define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE                                  0x0
729 #define     AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM                               0x0
730 #define     AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K                                 0x1000
731 
732 #define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__B                                    13
733 #define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__W                                    2
734 #define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__M                                    0x6000
735 #define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE                                  0x0
736 #define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA                             0x0
737 #define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC                              0x2000
738 #define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ                              0x4000
739 #define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA                              0x6000
740 
741 #define   AUD_DEM_WR_MODUS_MOD_BTSC__B                                      15
742 #define   AUD_DEM_WR_MODUS_MOD_BTSC__W                                      1
743 #define   AUD_DEM_WR_MODUS_MOD_BTSC__M                                      0x8000
744 #define   AUD_DEM_WR_MODUS_MOD_BTSC__PRE                                    0x0
745 #define     AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO                           0x0
746 #define     AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP                              0x8000
747 
748 #define AUD_DEM_WR_STANDARD_SEL__A                                          0x1030020
749 #define AUD_DEM_WR_STANDARD_SEL__W                                          16
750 #define AUD_DEM_WR_STANDARD_SEL__M                                          0xFFFF
751 #define AUD_DEM_WR_STANDARD_SEL__PRE                                        0x0
752 
753 #define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__B                                0
754 #define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__W                                12
755 #define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__M                                0xFFF
756 #define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE                              0x0
757 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO                            0x1
758 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA                         0x2
759 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM                           0x3
760 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1                            0x4
761 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2                            0x5
762 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3                            0x7
763 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM                     0x8
764 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM                      0x9
765 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM                      0xA
766 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM                    0xB
767 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO                     0x20
768 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP                        0x21
769 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J                           0x30
770 #define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO                        0x40
771 
772 #define AUD_DEM_RD_STANDARD_RES__A                                          0x102007E
773 #define AUD_DEM_RD_STANDARD_RES__W                                          16
774 #define AUD_DEM_RD_STANDARD_RES__M                                          0xFFFF
775 #define AUD_DEM_RD_STANDARD_RES__PRE                                        0x0
776 
777 #define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__B                             0
778 #define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__W                             16
779 #define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__M                             0xFFFF
780 #define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE                           0x0
781 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD            0x0
782 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM       0x2
783 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM          0x3
784 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM         0x4
785 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM         0x5
786 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM         0x7
787 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM                 0x8
788 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM                   0x9
789 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM                   0xA
790 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM                 0xB
791 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO                  0x20
792 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP                0x21
793 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J                   0x30
794 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO                     0x40
795 #define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE       0x7FF
796 
797 #define AUD_DEM_RD_STATUS__A                                                0x1020200
798 #define AUD_DEM_RD_STATUS__W                                                16
799 #define AUD_DEM_RD_STATUS__M                                                0xFFFF
800 #define AUD_DEM_RD_STATUS__PRE                                              0x0
801 
802 #define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__B                                 0
803 #define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__W                                 1
804 #define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__M                                 0x1
805 #define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE                               0x0
806 #define     AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA                      0x0
807 #define     AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA                     0x1
808 
809 #define   AUD_DEM_RD_STATUS_STAT_CARR_A__B                                  1
810 #define   AUD_DEM_RD_STATUS_STAT_CARR_A__W                                  1
811 #define   AUD_DEM_RD_STATUS_STAT_CARR_A__M                                  0x2
812 #define   AUD_DEM_RD_STATUS_STAT_CARR_A__PRE                                0x0
813 #define     AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED                          0x0
814 #define     AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED                      0x2
815 
816 #define   AUD_DEM_RD_STATUS_STAT_CARR_B__B                                  2
817 #define   AUD_DEM_RD_STATUS_STAT_CARR_B__W                                  1
818 #define   AUD_DEM_RD_STATUS_STAT_CARR_B__M                                  0x4
819 #define   AUD_DEM_RD_STATUS_STAT_CARR_B__PRE                                0x0
820 #define     AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED                          0x0
821 #define     AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED                      0x4
822 
823 #define   AUD_DEM_RD_STATUS_STAT_NICAM__B                                   5
824 #define   AUD_DEM_RD_STATUS_STAT_NICAM__W                                   1
825 #define   AUD_DEM_RD_STATUS_STAT_NICAM__M                                   0x20
826 #define   AUD_DEM_RD_STATUS_STAT_NICAM__PRE                                 0x0
827 #define     AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM                           0x0
828 #define     AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED                     0x20
829 
830 #define   AUD_DEM_RD_STATUS_STAT_STEREO__B                                  6
831 #define   AUD_DEM_RD_STATUS_STAT_STEREO__W                                  1
832 #define   AUD_DEM_RD_STATUS_STAT_STEREO__M                                  0x40
833 #define   AUD_DEM_RD_STATUS_STAT_STEREO__PRE                                0x0
834 #define     AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO                         0x0
835 #define     AUD_DEM_RD_STATUS_STAT_STEREO_STEREO                            0x40
836 
837 #define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B                              7
838 #define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W                              1
839 #define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M                              0x80
840 #define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE                            0x0
841 #define     AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM     0x0
842 #define     AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM   0x80
843 
844 #define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B                              8
845 #define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W                              1
846 #define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M                              0x100
847 #define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE                            0x0
848 #define     AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP                        0x0
849 #define     AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP                           0x100
850 
851 #define   AUD_DEM_RD_STATUS_BAD_NICAM__B                                    9
852 #define   AUD_DEM_RD_STATUS_BAD_NICAM__W                                    1
853 #define   AUD_DEM_RD_STATUS_BAD_NICAM__M                                    0x200
854 #define   AUD_DEM_RD_STATUS_BAD_NICAM__PRE                                  0x0
855 #define     AUD_DEM_RD_STATUS_BAD_NICAM_OK                                  0x0
856 #define     AUD_DEM_RD_STATUS_BAD_NICAM_BAD                                 0x200
857 
858 #define AUD_DEM_RD_RDS_ARRAY_CNT__A                                         0x102020F
859 #define AUD_DEM_RD_RDS_ARRAY_CNT__W                                         12
860 #define AUD_DEM_RD_RDS_ARRAY_CNT__M                                         0xFFF
861 #define AUD_DEM_RD_RDS_ARRAY_CNT__PRE                                       0x0
862 
863 #define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B                          0
864 #define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W                          12
865 #define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M                          0xFFF
866 #define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE                        0x0
867 #define     AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID        0xFFF
868 
869 #define AUD_DEM_RD_RDS_DATA__A                                              0x1020210
870 #define AUD_DEM_RD_RDS_DATA__W                                              12
871 #define AUD_DEM_RD_RDS_DATA__M                                              0xFFF
872 #define AUD_DEM_RD_RDS_DATA__PRE                                            0x0
873 
874 #define AUD_DSP_WR_FM_PRESC__A                                              0x105000E
875 #define AUD_DSP_WR_FM_PRESC__W                                              16
876 #define AUD_DSP_WR_FM_PRESC__M                                              0xFFFF
877 #define AUD_DSP_WR_FM_PRESC__PRE                                            0x0
878 
879 #define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B                                8
880 #define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W                                8
881 #define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M                                0xFF00
882 #define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE                              0x0
883 #define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION             0x7F00
884 #define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION             0x4800
885 #define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION             0x3000
886 #define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION            0x2400
887 #define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION            0x1800
888 #define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION            0x1300
889 #define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION            0x900
890 
891 #define AUD_DSP_WR_NICAM_PRESC__A                                           0x1050010
892 #define AUD_DSP_WR_NICAM_PRESC__W                                           16
893 #define AUD_DSP_WR_NICAM_PRESC__M                                           0xFFFF
894 #define AUD_DSP_WR_NICAM_PRESC__PRE                                         0x0
895 #define AUD_DSP_WR_VOLUME__A                                                0x1050000
896 #define AUD_DSP_WR_VOLUME__W                                                16
897 #define AUD_DSP_WR_VOLUME__M                                                0xFFFF
898 #define AUD_DSP_WR_VOLUME__PRE                                              0x0
899 
900 #define   AUD_DSP_WR_VOLUME_VOL_MAIN__B                                     8
901 #define   AUD_DSP_WR_VOLUME_VOL_MAIN__W                                     8
902 #define   AUD_DSP_WR_VOLUME_VOL_MAIN__M                                     0xFF00
903 #define   AUD_DSP_WR_VOLUME_VOL_MAIN__PRE                                   0x0
904 
905 #define AUD_DSP_WR_SRC_I2S_MATR__A                                          0x1050038
906 #define AUD_DSP_WR_SRC_I2S_MATR__W                                          16
907 #define AUD_DSP_WR_SRC_I2S_MATR__M                                          0xFFFF
908 #define AUD_DSP_WR_SRC_I2S_MATR__PRE                                        0x0
909 
910 #define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B                                8
911 #define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W                                8
912 #define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M                                0xFF00
913 #define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE                              0x0
914 #define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO                            0x0
915 #define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB                       0x100
916 #define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A                        0x300
917 #define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B                        0x400
918 
919 #define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B                                0
920 #define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W                                8
921 #define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M                                0xFF
922 #define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE                              0x0
923 #define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A                         0x0
924 #define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B                         0x10
925 #define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO                          0x20
926 #define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO                            0x30
927 
928 #define AUD_DSP_WR_AVC__A                                                   0x1050029
929 #define AUD_DSP_WR_AVC__W                                                   16
930 #define AUD_DSP_WR_AVC__M                                                   0xFFFF
931 #define AUD_DSP_WR_AVC__PRE                                                 0x0
932 
933 #define   AUD_DSP_WR_AVC_AVC_ON__B                                          14
934 #define   AUD_DSP_WR_AVC_AVC_ON__W                                          2
935 #define   AUD_DSP_WR_AVC_AVC_ON__M                                          0xC000
936 #define   AUD_DSP_WR_AVC_AVC_ON__PRE                                        0x0
937 #define     AUD_DSP_WR_AVC_AVC_ON_OFF                                       0x0
938 #define     AUD_DSP_WR_AVC_AVC_ON_ON                                        0xC000
939 
940 #define   AUD_DSP_WR_AVC_AVC_DECAY__B                                       8
941 #define   AUD_DSP_WR_AVC_AVC_DECAY__W                                       4
942 #define   AUD_DSP_WR_AVC_AVC_DECAY__M                                       0xF00
943 #define   AUD_DSP_WR_AVC_AVC_DECAY__PRE                                     0x0
944 #define     AUD_DSP_WR_AVC_AVC_DECAY_8_SEC                                  0x800
945 #define     AUD_DSP_WR_AVC_AVC_DECAY_4_SEC                                  0x400
946 #define     AUD_DSP_WR_AVC_AVC_DECAY_2_SEC                                  0x200
947 #define     AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC                                0x100
948 
949 #define   AUD_DSP_WR_AVC_AVC_REF_LEV__B                                     4
950 #define   AUD_DSP_WR_AVC_AVC_REF_LEV__W                                     4
951 #define   AUD_DSP_WR_AVC_AVC_REF_LEV__M                                     0xF0
952 #define   AUD_DSP_WR_AVC_AVC_REF_LEV__PRE                                   0x0
953 
954 #define   AUD_DSP_WR_AVC_AVC_MAX_ATT__B                                     2
955 #define   AUD_DSP_WR_AVC_AVC_MAX_ATT__W                                     2
956 #define   AUD_DSP_WR_AVC_AVC_MAX_ATT__M                                     0xC
957 #define   AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE                                   0x0
958 #define     AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB                                 0x0
959 #define     AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB                                 0x4
960 #define     AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB                                 0x8
961 
962 #define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__B                                    0
963 #define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__W                                    2
964 #define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__M                                    0x3
965 #define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE                                  0x0
966 #define     AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB                                 0x0
967 #define     AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB                                0x1
968 #define     AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB                                 0x3
969 
970 #define AUD_DSP_WR_QPEAK__A                                                 0x105000C
971 #define AUD_DSP_WR_QPEAK__W                                                 16
972 #define AUD_DSP_WR_QPEAK__M                                                 0xFFFF
973 #define AUD_DSP_WR_QPEAK__PRE                                               0x0
974 
975 #define   AUD_DSP_WR_QPEAK_SRC_QP__B                                        8
976 #define   AUD_DSP_WR_QPEAK_SRC_QP__W                                        8
977 #define   AUD_DSP_WR_QPEAK_SRC_QP__M                                        0xFF00
978 #define   AUD_DSP_WR_QPEAK_SRC_QP__PRE                                      0x0
979 #define     AUD_DSP_WR_QPEAK_SRC_QP_MONO                                    0x0
980 #define     AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB                               0x100
981 #define     AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A                                0x300
982 #define     AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B                                0x400
983 
984 #define   AUD_DSP_WR_QPEAK_MAT_QP__B                                        0
985 #define   AUD_DSP_WR_QPEAK_MAT_QP__W                                        8
986 #define   AUD_DSP_WR_QPEAK_MAT_QP__M                                        0xFF
987 #define   AUD_DSP_WR_QPEAK_MAT_QP__PRE                                      0x0
988 #define     AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A                                 0x0
989 #define     AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B                                 0x10
990 #define     AUD_DSP_WR_QPEAK_MAT_QP_STEREO                                  0x20
991 #define     AUD_DSP_WR_QPEAK_MAT_QP_MONO                                    0x30
992 
993 #define AUD_DSP_RD_QPEAK_L__A                                               0x1040019
994 #define AUD_DSP_RD_QPEAK_L__W                                               16
995 #define AUD_DSP_RD_QPEAK_L__M                                               0xFFFF
996 #define AUD_DSP_RD_QPEAK_L__PRE                                             0x0
997 
998 #define AUD_DSP_RD_QPEAK_R__A                                               0x104001A
999 #define AUD_DSP_RD_QPEAK_R__W                                               16
1000 #define AUD_DSP_RD_QPEAK_R__M                                               0xFFFF
1001 #define AUD_DSP_RD_QPEAK_R__PRE                                             0x0
1002 
1003 #define AUD_DSP_WR_BEEPER__A                                                0x1050014
1004 #define AUD_DSP_WR_BEEPER__W                                                16
1005 #define AUD_DSP_WR_BEEPER__M                                                0xFFFF
1006 #define AUD_DSP_WR_BEEPER__PRE                                              0x0
1007 
1008 #define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__B                                  8
1009 #define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__W                                  7
1010 #define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__M                                  0x7F00
1011 #define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE                                0x0
1012 
1013 #define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B                               0
1014 #define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W                               7
1015 #define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M                               0x7F
1016 #define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE                             0x0
1017 
1018 #define AUD_DEM_WR_I2S_CONFIG2__A                                           0x1030050
1019 #define AUD_DEM_WR_I2S_CONFIG2__W                                           16
1020 #define AUD_DEM_WR_I2S_CONFIG2__M                                           0xFFFF
1021 #define AUD_DEM_WR_I2S_CONFIG2__PRE                                         0x0
1022 
1023 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B                              6
1024 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W                              1
1025 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M                              0x40
1026 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE                            0x0
1027 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL                        0x0
1028 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED                      0x40
1029 
1030 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B                              4
1031 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W                              1
1032 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M                              0x10
1033 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE                            0x0
1034 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE                       0x0
1035 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE                        0x10
1036 
1037 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B                             3
1038 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W                             1
1039 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M                             0x8
1040 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE                           0x0
1041 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER                       0x0
1042 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE                        0x8
1043 
1044 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B                              2
1045 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W                              1
1046 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M                              0x4
1047 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE                            0x0
1048 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW                      0x0
1049 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH                     0x4
1050 
1051 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B                             1
1052 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W                             1
1053 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M                             0x2
1054 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE                           0x0
1055 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY                     0x0
1056 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY                        0x2
1057 
1058 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B                            0
1059 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W                            1
1060 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M                            0x1
1061 #define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE                          0x0
1062 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32                      0x0
1063 #define     AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16                      0x1
1064 
1065 #define AUD_DSP_WR_I2S_OUT_FS__A                                            0x105002A
1066 #define AUD_DSP_WR_I2S_OUT_FS__W                                            16
1067 #define AUD_DSP_WR_I2S_OUT_FS__M                                            0xFFFF
1068 #define AUD_DSP_WR_I2S_OUT_FS__PRE                                          0x0
1069 
1070 #define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B                                   0
1071 #define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W                                   16
1072 #define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M                                   0xFFFF
1073 #define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE                                 0x0
1074 
1075 #define AUD_DSP_WR_AV_SYNC__A                                               0x105002B
1076 #define AUD_DSP_WR_AV_SYNC__W                                               16
1077 #define AUD_DSP_WR_AV_SYNC__M                                               0xFFFF
1078 #define AUD_DSP_WR_AV_SYNC__PRE                                             0x0
1079 
1080 #define   AUD_DSP_WR_AV_SYNC_AV_ON__B                                       15
1081 #define   AUD_DSP_WR_AV_SYNC_AV_ON__W                                       1
1082 #define   AUD_DSP_WR_AV_SYNC_AV_ON__M                                       0x8000
1083 #define   AUD_DSP_WR_AV_SYNC_AV_ON__PRE                                     0x0
1084 #define     AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE                                0x0
1085 #define     AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE                                 0x8000
1086 
1087 #define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B                                14
1088 #define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W                                1
1089 #define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M                                0x4000
1090 #define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE                              0x0
1091 #define     AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME                      0x0
1092 #define     AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC                            0x4000
1093 
1094 #define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B                                  0
1095 #define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W                                  2
1096 #define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M                                  0x3
1097 #define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE                                0x0
1098 #define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO                              0x0
1099 #define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM                         0x1
1100 #define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC                              0x2
1101 #define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME                        0x3
1102 
1103 #define AUD_DSP_RD_STATUS2__A                                               0x104007B
1104 #define AUD_DSP_RD_STATUS2__W                                               16
1105 #define AUD_DSP_RD_STATUS2__M                                               0xFFFF
1106 #define AUD_DSP_RD_STATUS2__PRE                                             0x0
1107 
1108 #define   AUD_DSP_RD_STATUS2_AV_ACTIVE__B                                   15
1109 #define   AUD_DSP_RD_STATUS2_AV_ACTIVE__W                                   1
1110 #define   AUD_DSP_RD_STATUS2_AV_ACTIVE__M                                   0x8000
1111 #define   AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE                                 0x0
1112 #define     AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC                            0x0
1113 #define     AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE                        0x8000
1114 
1115 #define AUD_DSP_RD_XDFP_FW__A                                               0x104001D
1116 #define AUD_DSP_RD_XDFP_FW__W                                               16
1117 #define AUD_DSP_RD_XDFP_FW__M                                               0xFFFF
1118 #define AUD_DSP_RD_XDFP_FW__PRE                                             0x344
1119 
1120 #define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B                                  0
1121 #define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W                                  16
1122 #define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M                                  0xFFFF
1123 #define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE                                0x344
1124 
1125 #define AUD_DSP_RD_XFP_FW__A                                                0x10404B8
1126 #define AUD_DSP_RD_XFP_FW__W                                                16
1127 #define AUD_DSP_RD_XFP_FW__M                                                0xFFFF
1128 #define AUD_DSP_RD_XFP_FW__PRE                                              0x42
1129 
1130 #define   AUD_DSP_RD_XFP_FW_FP_FW_REV__B                                    0
1131 #define   AUD_DSP_RD_XFP_FW_FP_FW_REV__W                                    16
1132 #define   AUD_DSP_RD_XFP_FW_FP_FW_REV__M                                    0xFFFF
1133 #define   AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE                                  0x42
1134 
1135 #define AUD_DEM_WR_DCO_B_HI__A                                              0x103009B
1136 #define AUD_DEM_WR_DCO_B_HI__W                                              16
1137 #define AUD_DEM_WR_DCO_B_HI__M                                              0xFFFF
1138 #define AUD_DEM_WR_DCO_B_HI__PRE                                            0x0
1139 
1140 #define AUD_DEM_WR_DCO_B_LO__A                                              0x1030093
1141 #define AUD_DEM_WR_DCO_B_LO__W                                              16
1142 #define AUD_DEM_WR_DCO_B_LO__M                                              0xFFFF
1143 #define AUD_DEM_WR_DCO_B_LO__PRE                                            0x0
1144 
1145 #define AUD_DEM_WR_DCO_A_HI__A                                              0x10300AB
1146 #define AUD_DEM_WR_DCO_A_HI__W                                              16
1147 #define AUD_DEM_WR_DCO_A_HI__M                                              0xFFFF
1148 #define AUD_DEM_WR_DCO_A_HI__PRE                                            0x0
1149 
1150 #define AUD_DEM_WR_DCO_A_LO__A                                              0x10300A3
1151 #define AUD_DEM_WR_DCO_A_LO__W                                              16
1152 #define AUD_DEM_WR_DCO_A_LO__M                                              0xFFFF
1153 #define AUD_DEM_WR_DCO_A_LO__PRE                                            0x0
1154 #define AUD_DEM_WR_NICAM_THRSHLD__A                                         0x1030021
1155 #define AUD_DEM_WR_NICAM_THRSHLD__W                                         16
1156 #define AUD_DEM_WR_NICAM_THRSHLD__M                                         0xFFFF
1157 #define AUD_DEM_WR_NICAM_THRSHLD__PRE                                       0x2BC
1158 
1159 #define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B                            0
1160 #define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W                            12
1161 #define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M                            0xFFF
1162 #define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE                          0x2BC
1163 
1164 #define AUD_DEM_WR_A2_THRSHLD__A                                            0x1030022
1165 #define AUD_DEM_WR_A2_THRSHLD__W                                            16
1166 #define AUD_DEM_WR_A2_THRSHLD__M                                            0xFFFF
1167 #define AUD_DEM_WR_A2_THRSHLD__PRE                                          0x190
1168 
1169 #define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__B                                  0
1170 #define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__W                                  12
1171 #define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__M                                  0xFFF
1172 #define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE                                0x190
1173 
1174 #define AUD_DEM_WR_BTSC_THRSHLD__A                                          0x1030023
1175 #define AUD_DEM_WR_BTSC_THRSHLD__W                                          16
1176 #define AUD_DEM_WR_BTSC_THRSHLD__M                                          0xFFFF
1177 #define AUD_DEM_WR_BTSC_THRSHLD__PRE                                        0xC
1178 
1179 #define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B                              0
1180 #define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W                              12
1181 #define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M                              0xFFF
1182 #define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE                            0xC
1183 
1184 #define AUD_DEM_WR_CM_A_THRSHLD__A                                          0x1030024
1185 #define AUD_DEM_WR_CM_A_THRSHLD__W                                          16
1186 #define AUD_DEM_WR_CM_A_THRSHLD__M                                          0xFFFF
1187 #define AUD_DEM_WR_CM_A_THRSHLD__PRE                                        0x2A
1188 
1189 #define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B                              0
1190 #define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W                              12
1191 #define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M                              0xFFF
1192 #define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE                            0x2A
1193 
1194 #define AUD_DEM_WR_CM_B_THRSHLD__A                                          0x1030025
1195 #define AUD_DEM_WR_CM_B_THRSHLD__W                                          16
1196 #define AUD_DEM_WR_CM_B_THRSHLD__M                                          0xFFFF
1197 #define AUD_DEM_WR_CM_B_THRSHLD__PRE                                        0x2A
1198 
1199 #define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B                              0
1200 #define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W                              12
1201 #define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M                              0xFFF
1202 #define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE                            0x2A
1203 
1204 #define AUD_DEM_RD_NIC_C_AD_BITS__A                                         0x1020023
1205 #define AUD_DEM_RD_NIC_C_AD_BITS__W                                         16
1206 #define AUD_DEM_RD_NIC_C_AD_BITS__M                                         0xFFFF
1207 #define AUD_DEM_RD_NIC_C_AD_BITS__PRE                                       0x0
1208 
1209 #define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B                            0
1210 #define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W                            1
1211 #define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M                            0x1
1212 #define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE                          0x0
1213 #define     AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED                  0x0
1214 #define     AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED                      0x1
1215 
1216 #define   AUD_DEM_RD_NIC_C_AD_BITS_C__B                                     1
1217 #define   AUD_DEM_RD_NIC_C_AD_BITS_C__W                                     4
1218 #define   AUD_DEM_RD_NIC_C_AD_BITS_C__M                                     0x1E
1219 #define   AUD_DEM_RD_NIC_C_AD_BITS_C__PRE                                   0x0
1220 
1221 #define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B                            5
1222 #define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W                            3
1223 #define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M                            0xE0
1224 #define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE                          0x0
1225 
1226 #define AUD_DEM_RD_NIC_ADD_BITS_HI__A                                       0x1020038
1227 #define AUD_DEM_RD_NIC_ADD_BITS_HI__W                                       16
1228 #define AUD_DEM_RD_NIC_ADD_BITS_HI__M                                       0xFFFF
1229 #define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE                                     0x0
1230 
1231 #define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B                          0
1232 #define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W                          8
1233 #define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M                          0xFF
1234 #define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE                        0x0
1235 
1236 #define AUD_DEM_RD_NIC_CIB__A                                               0x1020038
1237 #define AUD_DEM_RD_NIC_CIB__W                                               16
1238 #define AUD_DEM_RD_NIC_CIB__M                                               0xFFFF
1239 #define AUD_DEM_RD_NIC_CIB__PRE                                             0x0
1240 
1241 #define   AUD_DEM_RD_NIC_CIB_CIB2__B                                        0
1242 #define   AUD_DEM_RD_NIC_CIB_CIB2__W                                        1
1243 #define   AUD_DEM_RD_NIC_CIB_CIB2__M                                        0x1
1244 #define   AUD_DEM_RD_NIC_CIB_CIB2__PRE                                      0x0
1245 
1246 #define   AUD_DEM_RD_NIC_CIB_CIB1__B                                        1
1247 #define   AUD_DEM_RD_NIC_CIB_CIB1__W                                        1
1248 #define   AUD_DEM_RD_NIC_CIB_CIB1__M                                        0x2
1249 #define   AUD_DEM_RD_NIC_CIB_CIB1__PRE                                      0x0
1250 
1251 #define AUD_DEM_RD_NIC_ERROR_RATE__A                                        0x1020057
1252 #define AUD_DEM_RD_NIC_ERROR_RATE__W                                        16
1253 #define AUD_DEM_RD_NIC_ERROR_RATE__M                                        0xFFFF
1254 #define AUD_DEM_RD_NIC_ERROR_RATE__PRE                                      0x0
1255 
1256 #define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B                           0
1257 #define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W                           12
1258 #define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M                           0xFFF
1259 #define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE                         0x0
1260 
1261 #define AUD_DEM_WR_FM_DEEMPH__A                                             0x103000F
1262 #define AUD_DEM_WR_FM_DEEMPH__W                                             16
1263 #define AUD_DEM_WR_FM_DEEMPH__M                                             0xFFFF
1264 #define AUD_DEM_WR_FM_DEEMPH__PRE                                           0x0
1265 #define   AUD_DEM_WR_FM_DEEMPH_50US                                         0x0
1266 #define   AUD_DEM_WR_FM_DEEMPH_75US                                         0x1
1267 #define   AUD_DEM_WR_FM_DEEMPH_OFF                                          0x3F
1268 
1269 #define AUD_DEM_WR_FM_MATRIX__A                                             0x103006F
1270 #define AUD_DEM_WR_FM_MATRIX__W                                             16
1271 #define AUD_DEM_WR_FM_MATRIX__M                                             0xFFFF
1272 #define AUD_DEM_WR_FM_MATRIX__PRE                                           0x0
1273 #define   AUD_DEM_WR_FM_MATRIX_NO_MATRIX                                    0x0
1274 #define   AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX                                0x1
1275 #define   AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX                                0x2
1276 #define   AUD_DEM_WR_FM_MATRIX_SOUND_A                                      0x3
1277 #define   AUD_DEM_WR_FM_MATRIX_SOUND_B                                      0x4
1278 
1279 #define AUD_DSP_RD_FM_IDENT_VALUE__A                                        0x1040018
1280 #define AUD_DSP_RD_FM_IDENT_VALUE__W                                        16
1281 #define AUD_DSP_RD_FM_IDENT_VALUE__M                                        0xFFFF
1282 #define AUD_DSP_RD_FM_IDENT_VALUE__PRE                                      0x0
1283 
1284 #define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B                             8
1285 #define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W                             8
1286 #define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M                             0xFF00
1287 #define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE                           0x0
1288 
1289 #define AUD_DSP_RD_FM_DC_LEVEL_A__A                                         0x104001B
1290 #define AUD_DSP_RD_FM_DC_LEVEL_A__W                                         16
1291 #define AUD_DSP_RD_FM_DC_LEVEL_A__M                                         0xFFFF
1292 #define AUD_DSP_RD_FM_DC_LEVEL_A__PRE                                       0x0
1293 
1294 #define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B                           0
1295 #define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W                           16
1296 #define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M                           0xFFFF
1297 #define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE                         0x0
1298 
1299 #define AUD_DSP_RD_FM_DC_LEVEL_B__A                                         0x104001C
1300 #define AUD_DSP_RD_FM_DC_LEVEL_B__W                                         16
1301 #define AUD_DSP_RD_FM_DC_LEVEL_B__M                                         0xFFFF
1302 #define AUD_DSP_RD_FM_DC_LEVEL_B__PRE                                       0x0
1303 
1304 #define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B                           0
1305 #define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W                           16
1306 #define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M                           0xFFFF
1307 #define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE                         0x0
1308 
1309 #define AUD_DEM_WR_FM_DC_NOTCH_SW__A                                        0x1030017
1310 #define AUD_DEM_WR_FM_DC_NOTCH_SW__W                                        16
1311 #define AUD_DEM_WR_FM_DC_NOTCH_SW__M                                        0xFFFF
1312 #define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE                                      0x0
1313 
1314 #define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B                          0
1315 #define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W                          16
1316 #define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M                          0xFFFF
1317 #define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE                        0x0
1318 #define     AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON                        0x0
1319 #define     AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF                       0x3F
1320 
1321 #define AUD_DSP_WR_SYNC_OUT__A                                              0x1050026
1322 #define AUD_DSP_WR_SYNC_OUT__W                                              16
1323 #define AUD_DSP_WR_SYNC_OUT__M                                              0xFFFF
1324 #define AUD_DSP_WR_SYNC_OUT__PRE                                            0x0
1325 #define   AUD_DSP_WR_SYNC_OUT_OFF                                           0x0
1326 #define   AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS                                   0x1
1327 
1328 #define AUD_XFP_DRAM_1K__A                                                  0x1060000
1329 #define AUD_XFP_DRAM_1K__W                                                  16
1330 #define AUD_XFP_DRAM_1K__M                                                  0xFFFF
1331 #define AUD_XFP_DRAM_1K__PRE                                                0x0
1332 #define   AUD_XFP_DRAM_1K_D__B                                              0
1333 #define   AUD_XFP_DRAM_1K_D__W                                              16
1334 #define   AUD_XFP_DRAM_1K_D__M                                              0xFFFF
1335 #define   AUD_XFP_DRAM_1K_D__PRE                                            0x0
1336 
1337 #define AUD_XFP_PRAM_4K__A                                                  0x1070000
1338 #define AUD_XFP_PRAM_4K__W                                                  16
1339 #define AUD_XFP_PRAM_4K__M                                                  0xFFFF
1340 #define AUD_XFP_PRAM_4K__PRE                                                0x0
1341 #define   AUD_XFP_PRAM_4K_D__B                                              0
1342 #define   AUD_XFP_PRAM_4K_D__W                                              16
1343 #define   AUD_XFP_PRAM_4K_D__M                                              0xFFFF
1344 #define   AUD_XFP_PRAM_4K_D__PRE                                            0x0
1345 
1346 #define AUD_XDFP_DRAM_1K__A                                                 0x1080000
1347 #define AUD_XDFP_DRAM_1K__W                                                 16
1348 #define AUD_XDFP_DRAM_1K__M                                                 0xFFFF
1349 #define AUD_XDFP_DRAM_1K__PRE                                               0x0
1350 #define   AUD_XDFP_DRAM_1K_D__B                                             0
1351 #define   AUD_XDFP_DRAM_1K_D__W                                             16
1352 #define   AUD_XDFP_DRAM_1K_D__M                                             0xFFFF
1353 #define   AUD_XDFP_DRAM_1K_D__PRE                                           0x0
1354 
1355 #define AUD_XDFP_PRAM_4K__A                                                 0x1090000
1356 #define AUD_XDFP_PRAM_4K__W                                                 16
1357 #define AUD_XDFP_PRAM_4K__M                                                 0xFFFF
1358 #define AUD_XDFP_PRAM_4K__PRE                                               0x0
1359 #define   AUD_XDFP_PRAM_4K_D__B                                             0
1360 #define   AUD_XDFP_PRAM_4K_D__W                                             16
1361 #define   AUD_XDFP_PRAM_4K_D__M                                             0xFFFF
1362 #define   AUD_XDFP_PRAM_4K_D__PRE                                           0x0
1363 
1364 #define FEC_COMM_EXEC__A                                                    0x2400000
1365 #define FEC_COMM_EXEC__W                                                    2
1366 #define FEC_COMM_EXEC__M                                                    0x3
1367 #define FEC_COMM_EXEC__PRE                                                  0x0
1368 #define   FEC_COMM_EXEC_STOP                                                0x0
1369 #define   FEC_COMM_EXEC_ACTIVE                                              0x1
1370 #define   FEC_COMM_EXEC_HOLD                                                0x2
1371 
1372 #define FEC_COMM_MB__A                                                      0x2400002
1373 #define FEC_COMM_MB__W                                                      16
1374 #define FEC_COMM_MB__M                                                      0xFFFF
1375 #define FEC_COMM_MB__PRE                                                    0x0
1376 #define FEC_COMM_INT_REQ__A                                                 0x2400003
1377 #define FEC_COMM_INT_REQ__W                                                 16
1378 #define FEC_COMM_INT_REQ__M                                                 0xFFFF
1379 #define FEC_COMM_INT_REQ__PRE                                               0x0
1380 #define   FEC_COMM_INT_REQ_OC_REQ__B                                        0
1381 #define   FEC_COMM_INT_REQ_OC_REQ__W                                        1
1382 #define   FEC_COMM_INT_REQ_OC_REQ__M                                        0x1
1383 #define   FEC_COMM_INT_REQ_OC_REQ__PRE                                      0x0
1384 #define   FEC_COMM_INT_REQ_RS_REQ__B                                        1
1385 #define   FEC_COMM_INT_REQ_RS_REQ__W                                        1
1386 #define   FEC_COMM_INT_REQ_RS_REQ__M                                        0x2
1387 #define   FEC_COMM_INT_REQ_RS_REQ__PRE                                      0x0
1388 #define   FEC_COMM_INT_REQ_DI_REQ__B                                        2
1389 #define   FEC_COMM_INT_REQ_DI_REQ__W                                        1
1390 #define   FEC_COMM_INT_REQ_DI_REQ__M                                        0x4
1391 #define   FEC_COMM_INT_REQ_DI_REQ__PRE                                      0x0
1392 
1393 #define FEC_COMM_INT_STA__A                                                 0x2400005
1394 #define FEC_COMM_INT_STA__W                                                 16
1395 #define FEC_COMM_INT_STA__M                                                 0xFFFF
1396 #define FEC_COMM_INT_STA__PRE                                               0x0
1397 #define FEC_COMM_INT_MSK__A                                                 0x2400006
1398 #define FEC_COMM_INT_MSK__W                                                 16
1399 #define FEC_COMM_INT_MSK__M                                                 0xFFFF
1400 #define FEC_COMM_INT_MSK__PRE                                               0x0
1401 #define FEC_COMM_INT_STM__A                                                 0x2400007
1402 #define FEC_COMM_INT_STM__W                                                 16
1403 #define FEC_COMM_INT_STM__M                                                 0xFFFF
1404 #define FEC_COMM_INT_STM__PRE                                               0x0
1405 
1406 #define FEC_TOP_COMM_EXEC__A                                                0x2410000
1407 #define FEC_TOP_COMM_EXEC__W                                                2
1408 #define FEC_TOP_COMM_EXEC__M                                                0x3
1409 #define FEC_TOP_COMM_EXEC__PRE                                              0x0
1410 #define   FEC_TOP_COMM_EXEC_STOP                                            0x0
1411 #define   FEC_TOP_COMM_EXEC_ACTIVE                                          0x1
1412 #define   FEC_TOP_COMM_EXEC_HOLD                                            0x2
1413 
1414 #define FEC_TOP_ANNEX__A                                                    0x2410010
1415 #define FEC_TOP_ANNEX__W                                                    2
1416 #define FEC_TOP_ANNEX__M                                                    0x3
1417 #define FEC_TOP_ANNEX__PRE                                                  0x0
1418 #define   FEC_TOP_ANNEX_A                                                   0x0
1419 #define   FEC_TOP_ANNEX_B                                                   0x1
1420 #define   FEC_TOP_ANNEX_C                                                   0x2
1421 #define   FEC_TOP_ANNEX_D                                                   0x3
1422 
1423 #define FEC_DI_COMM_EXEC__A                                                 0x2420000
1424 #define FEC_DI_COMM_EXEC__W                                                 2
1425 #define FEC_DI_COMM_EXEC__M                                                 0x3
1426 #define FEC_DI_COMM_EXEC__PRE                                               0x0
1427 #define   FEC_DI_COMM_EXEC_STOP                                             0x0
1428 #define   FEC_DI_COMM_EXEC_ACTIVE                                           0x1
1429 #define   FEC_DI_COMM_EXEC_HOLD                                             0x2
1430 
1431 #define FEC_DI_COMM_MB__A                                                   0x2420002
1432 #define FEC_DI_COMM_MB__W                                                   2
1433 #define FEC_DI_COMM_MB__M                                                   0x3
1434 #define FEC_DI_COMM_MB__PRE                                                 0x0
1435 #define   FEC_DI_COMM_MB_CTL__B                                             0
1436 #define   FEC_DI_COMM_MB_CTL__W                                             1
1437 #define   FEC_DI_COMM_MB_CTL__M                                             0x1
1438 #define   FEC_DI_COMM_MB_CTL__PRE                                           0x0
1439 #define     FEC_DI_COMM_MB_CTL_OFF                                          0x0
1440 #define     FEC_DI_COMM_MB_CTL_ON                                           0x1
1441 #define   FEC_DI_COMM_MB_OBS__B                                             1
1442 #define   FEC_DI_COMM_MB_OBS__W                                             1
1443 #define   FEC_DI_COMM_MB_OBS__M                                             0x2
1444 #define   FEC_DI_COMM_MB_OBS__PRE                                           0x0
1445 #define     FEC_DI_COMM_MB_OBS_OFF                                          0x0
1446 #define     FEC_DI_COMM_MB_OBS_ON                                           0x2
1447 
1448 #define FEC_DI_COMM_INT_REQ__A                                              0x2420003
1449 #define FEC_DI_COMM_INT_REQ__W                                              1
1450 #define FEC_DI_COMM_INT_REQ__M                                              0x1
1451 #define FEC_DI_COMM_INT_REQ__PRE                                            0x0
1452 #define FEC_DI_COMM_INT_STA__A                                              0x2420005
1453 #define FEC_DI_COMM_INT_STA__W                                              2
1454 #define FEC_DI_COMM_INT_STA__M                                              0x3
1455 #define FEC_DI_COMM_INT_STA__PRE                                            0x0
1456 
1457 #define   FEC_DI_COMM_INT_STA_STAT_INT__B                                   0
1458 #define   FEC_DI_COMM_INT_STA_STAT_INT__W                                   1
1459 #define   FEC_DI_COMM_INT_STA_STAT_INT__M                                   0x1
1460 #define   FEC_DI_COMM_INT_STA_STAT_INT__PRE                                 0x0
1461 
1462 #define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__B                                1
1463 #define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__W                                1
1464 #define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__M                                0x2
1465 #define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE                              0x0
1466 
1467 #define FEC_DI_COMM_INT_MSK__A                                              0x2420006
1468 #define FEC_DI_COMM_INT_MSK__W                                              2
1469 #define FEC_DI_COMM_INT_MSK__M                                              0x3
1470 #define FEC_DI_COMM_INT_MSK__PRE                                            0x0
1471 #define   FEC_DI_COMM_INT_MSK_STAT_INT__B                                   0
1472 #define   FEC_DI_COMM_INT_MSK_STAT_INT__W                                   1
1473 #define   FEC_DI_COMM_INT_MSK_STAT_INT__M                                   0x1
1474 #define   FEC_DI_COMM_INT_MSK_STAT_INT__PRE                                 0x0
1475 #define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B                                1
1476 #define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W                                1
1477 #define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M                                0x2
1478 #define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE                              0x0
1479 
1480 #define FEC_DI_COMM_INT_STM__A                                              0x2420007
1481 #define FEC_DI_COMM_INT_STM__W                                              2
1482 #define FEC_DI_COMM_INT_STM__M                                              0x3
1483 #define FEC_DI_COMM_INT_STM__PRE                                            0x0
1484 #define   FEC_DI_COMM_INT_STM_STAT_INT__B                                   0
1485 #define   FEC_DI_COMM_INT_STM_STAT_INT__W                                   1
1486 #define   FEC_DI_COMM_INT_STM_STAT_INT__M                                   0x1
1487 #define   FEC_DI_COMM_INT_STM_STAT_INT__PRE                                 0x0
1488 #define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__B                                1
1489 #define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__W                                1
1490 #define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__M                                0x2
1491 #define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE                              0x0
1492 
1493 #define FEC_DI_STATUS__A                                                    0x2420010
1494 #define FEC_DI_STATUS__W                                                    1
1495 #define FEC_DI_STATUS__M                                                    0x1
1496 #define FEC_DI_STATUS__PRE                                                  0x0
1497 #define FEC_DI_MODE__A                                                      0x2420011
1498 #define FEC_DI_MODE__W                                                      3
1499 #define FEC_DI_MODE__M                                                      0x7
1500 #define FEC_DI_MODE__PRE                                                    0x0
1501 
1502 #define   FEC_DI_MODE_NO_SYNC__B                                            0
1503 #define   FEC_DI_MODE_NO_SYNC__W                                            1
1504 #define   FEC_DI_MODE_NO_SYNC__M                                            0x1
1505 #define   FEC_DI_MODE_NO_SYNC__PRE                                          0x0
1506 
1507 #define   FEC_DI_MODE_IGNORE_LOST_SYNC__B                                   1
1508 #define   FEC_DI_MODE_IGNORE_LOST_SYNC__W                                   1
1509 #define   FEC_DI_MODE_IGNORE_LOST_SYNC__M                                   0x2
1510 #define   FEC_DI_MODE_IGNORE_LOST_SYNC__PRE                                 0x0
1511 
1512 #define   FEC_DI_MODE_IGNORE_TIMEOUT__B                                     2
1513 #define   FEC_DI_MODE_IGNORE_TIMEOUT__W                                     1
1514 #define   FEC_DI_MODE_IGNORE_TIMEOUT__M                                     0x4
1515 #define   FEC_DI_MODE_IGNORE_TIMEOUT__PRE                                   0x0
1516 
1517 #define FEC_DI_CONTROL_WORD__A                                              0x2420012
1518 #define FEC_DI_CONTROL_WORD__W                                              4
1519 #define FEC_DI_CONTROL_WORD__M                                              0xF
1520 #define FEC_DI_CONTROL_WORD__PRE                                            0x0
1521 
1522 #define FEC_DI_RESTART__A                                                   0x2420013
1523 #define FEC_DI_RESTART__W                                                   1
1524 #define FEC_DI_RESTART__M                                                   0x1
1525 #define FEC_DI_RESTART__PRE                                                 0x0
1526 
1527 #define FEC_DI_TIMEOUT_LO__A                                                0x2420014
1528 #define FEC_DI_TIMEOUT_LO__W                                                16
1529 #define FEC_DI_TIMEOUT_LO__M                                                0xFFFF
1530 #define FEC_DI_TIMEOUT_LO__PRE                                              0x0
1531 
1532 #define FEC_DI_TIMEOUT_HI__A                                                0x2420015
1533 #define FEC_DI_TIMEOUT_HI__W                                                8
1534 #define FEC_DI_TIMEOUT_HI__M                                                0xFF
1535 #define FEC_DI_TIMEOUT_HI__PRE                                              0xA
1536 
1537 #define FEC_RS_COMM_EXEC__A                                                 0x2430000
1538 #define FEC_RS_COMM_EXEC__W                                                 2
1539 #define FEC_RS_COMM_EXEC__M                                                 0x3
1540 #define FEC_RS_COMM_EXEC__PRE                                               0x0
1541 #define   FEC_RS_COMM_EXEC_STOP                                             0x0
1542 #define   FEC_RS_COMM_EXEC_ACTIVE                                           0x1
1543 #define   FEC_RS_COMM_EXEC_HOLD                                             0x2
1544 
1545 #define FEC_RS_COMM_MB__A                                                   0x2430002
1546 #define FEC_RS_COMM_MB__W                                                   2
1547 #define FEC_RS_COMM_MB__M                                                   0x3
1548 #define FEC_RS_COMM_MB__PRE                                                 0x0
1549 #define   FEC_RS_COMM_MB_CTL__B                                             0
1550 #define   FEC_RS_COMM_MB_CTL__W                                             1
1551 #define   FEC_RS_COMM_MB_CTL__M                                             0x1
1552 #define   FEC_RS_COMM_MB_CTL__PRE                                           0x0
1553 #define     FEC_RS_COMM_MB_CTL_OFF                                          0x0
1554 #define     FEC_RS_COMM_MB_CTL_ON                                           0x1
1555 #define   FEC_RS_COMM_MB_OBS__B                                             1
1556 #define   FEC_RS_COMM_MB_OBS__W                                             1
1557 #define   FEC_RS_COMM_MB_OBS__M                                             0x2
1558 #define   FEC_RS_COMM_MB_OBS__PRE                                           0x0
1559 #define     FEC_RS_COMM_MB_OBS_OFF                                          0x0
1560 #define     FEC_RS_COMM_MB_OBS_ON                                           0x2
1561 
1562 #define FEC_RS_COMM_INT_REQ__A                                              0x2430003
1563 #define FEC_RS_COMM_INT_REQ__W                                              1
1564 #define FEC_RS_COMM_INT_REQ__M                                              0x1
1565 #define FEC_RS_COMM_INT_REQ__PRE                                            0x0
1566 #define FEC_RS_COMM_INT_STA__A                                              0x2430005
1567 #define FEC_RS_COMM_INT_STA__W                                              2
1568 #define FEC_RS_COMM_INT_STA__M                                              0x3
1569 #define FEC_RS_COMM_INT_STA__PRE                                            0x0
1570 
1571 #define   FEC_RS_COMM_INT_STA_FAILURE_INT__B                                0
1572 #define   FEC_RS_COMM_INT_STA_FAILURE_INT__W                                1
1573 #define   FEC_RS_COMM_INT_STA_FAILURE_INT__M                                0x1
1574 #define   FEC_RS_COMM_INT_STA_FAILURE_INT__PRE                              0x0
1575 
1576 #define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B                            1
1577 #define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W                            1
1578 #define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M                            0x2
1579 #define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE                          0x0
1580 
1581 #define FEC_RS_COMM_INT_MSK__A                                              0x2430006
1582 #define FEC_RS_COMM_INT_MSK__W                                              2
1583 #define FEC_RS_COMM_INT_MSK__M                                              0x3
1584 #define FEC_RS_COMM_INT_MSK__PRE                                            0x0
1585 #define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__B                                0
1586 #define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__W                                1
1587 #define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__M                                0x1
1588 #define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE                              0x0
1589 #define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B                            1
1590 #define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W                            1
1591 #define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M                            0x2
1592 #define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE                          0x0
1593 
1594 #define FEC_RS_COMM_INT_STM__A                                              0x2430007
1595 #define FEC_RS_COMM_INT_STM__W                                              2
1596 #define FEC_RS_COMM_INT_STM__M                                              0x3
1597 #define FEC_RS_COMM_INT_STM__PRE                                            0x0
1598 #define   FEC_RS_COMM_INT_STM_FAILURE_MSK__B                                0
1599 #define   FEC_RS_COMM_INT_STM_FAILURE_MSK__W                                1
1600 #define   FEC_RS_COMM_INT_STM_FAILURE_MSK__M                                0x1
1601 #define   FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE                              0x0
1602 #define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B                            1
1603 #define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W                            1
1604 #define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M                            0x2
1605 #define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE                          0x0
1606 
1607 #define FEC_RS_STATUS__A                                                    0x2430010
1608 #define FEC_RS_STATUS__W                                                    1
1609 #define FEC_RS_STATUS__M                                                    0x1
1610 #define FEC_RS_STATUS__PRE                                                  0x0
1611 #define FEC_RS_MODE__A                                                      0x2430011
1612 #define FEC_RS_MODE__W                                                      1
1613 #define FEC_RS_MODE__M                                                      0x1
1614 #define FEC_RS_MODE__PRE                                                    0x0
1615 
1616 #define   FEC_RS_MODE_BYPASS__B                                             0
1617 #define   FEC_RS_MODE_BYPASS__W                                             1
1618 #define   FEC_RS_MODE_BYPASS__M                                             0x1
1619 #define   FEC_RS_MODE_BYPASS__PRE                                           0x0
1620 
1621 #define FEC_RS_MEASUREMENT_PERIOD__A                                        0x2430012
1622 #define FEC_RS_MEASUREMENT_PERIOD__W                                        16
1623 #define FEC_RS_MEASUREMENT_PERIOD__M                                        0xFFFF
1624 #define FEC_RS_MEASUREMENT_PERIOD__PRE                                      0x1171
1625 
1626 #define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__B                               0
1627 #define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__W                               16
1628 #define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__M                               0xFFFF
1629 #define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE                             0x1171
1630 
1631 #define FEC_RS_MEASUREMENT_PRESCALE__A                                      0x2430013
1632 #define FEC_RS_MEASUREMENT_PRESCALE__W                                      16
1633 #define FEC_RS_MEASUREMENT_PRESCALE__M                                      0xFFFF
1634 #define FEC_RS_MEASUREMENT_PRESCALE__PRE                                    0x1
1635 
1636 #define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B                           0
1637 #define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W                           16
1638 #define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M                           0xFFFF
1639 #define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE                         0x1
1640 
1641 #define FEC_RS_NR_BIT_ERRORS__A                                             0x2430014
1642 #define FEC_RS_NR_BIT_ERRORS__W                                             16
1643 #define FEC_RS_NR_BIT_ERRORS__M                                             0xFFFF
1644 #define FEC_RS_NR_BIT_ERRORS__PRE                                           0xFFFF
1645 
1646 #define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B                                0
1647 #define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W                                12
1648 #define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M                                0xFFF
1649 #define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE                              0xFFF
1650 
1651 #define   FEC_RS_NR_BIT_ERRORS_EXP__B                                       12
1652 #define   FEC_RS_NR_BIT_ERRORS_EXP__W                                       4
1653 #define   FEC_RS_NR_BIT_ERRORS_EXP__M                                       0xF000
1654 #define   FEC_RS_NR_BIT_ERRORS_EXP__PRE                                     0xF000
1655 
1656 #define FEC_RS_NR_SYMBOL_ERRORS__A                                          0x2430015
1657 #define FEC_RS_NR_SYMBOL_ERRORS__W                                          16
1658 #define FEC_RS_NR_SYMBOL_ERRORS__M                                          0xFFFF
1659 #define FEC_RS_NR_SYMBOL_ERRORS__PRE                                        0xFFFF
1660 
1661 #define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B                             0
1662 #define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W                             12
1663 #define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M                             0xFFF
1664 #define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE                           0xFFF
1665 
1666 #define   FEC_RS_NR_SYMBOL_ERRORS_EXP__B                                    12
1667 #define   FEC_RS_NR_SYMBOL_ERRORS_EXP__W                                    4
1668 #define   FEC_RS_NR_SYMBOL_ERRORS_EXP__M                                    0xF000
1669 #define   FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE                                  0xF000
1670 
1671 #define FEC_RS_NR_PACKET_ERRORS__A                                          0x2430016
1672 #define FEC_RS_NR_PACKET_ERRORS__W                                          16
1673 #define FEC_RS_NR_PACKET_ERRORS__M                                          0xFFFF
1674 #define FEC_RS_NR_PACKET_ERRORS__PRE                                        0xFFFF
1675 
1676 #define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B                             0
1677 #define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W                             12
1678 #define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M                             0xFFF
1679 #define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE                           0xFFF
1680 
1681 #define   FEC_RS_NR_PACKET_ERRORS_EXP__B                                    12
1682 #define   FEC_RS_NR_PACKET_ERRORS_EXP__W                                    4
1683 #define   FEC_RS_NR_PACKET_ERRORS_EXP__M                                    0xF000
1684 #define   FEC_RS_NR_PACKET_ERRORS_EXP__PRE                                  0xF000
1685 
1686 #define FEC_RS_NR_FAILURES__A                                               0x2430017
1687 #define FEC_RS_NR_FAILURES__W                                               16
1688 #define FEC_RS_NR_FAILURES__M                                               0xFFFF
1689 #define FEC_RS_NR_FAILURES__PRE                                             0x0
1690 
1691 #define   FEC_RS_NR_FAILURES_FIXED_MANT__B                                  0
1692 #define   FEC_RS_NR_FAILURES_FIXED_MANT__W                                  12
1693 #define   FEC_RS_NR_FAILURES_FIXED_MANT__M                                  0xFFF
1694 #define   FEC_RS_NR_FAILURES_FIXED_MANT__PRE                                0x0
1695 
1696 #define   FEC_RS_NR_FAILURES_EXP__B                                         12
1697 #define   FEC_RS_NR_FAILURES_EXP__W                                         4
1698 #define   FEC_RS_NR_FAILURES_EXP__M                                         0xF000
1699 #define   FEC_RS_NR_FAILURES_EXP__PRE                                       0x0
1700 
1701 #define FEC_OC_COMM_EXEC__A                                                 0x2440000
1702 #define FEC_OC_COMM_EXEC__W                                                 2
1703 #define FEC_OC_COMM_EXEC__M                                                 0x3
1704 #define FEC_OC_COMM_EXEC__PRE                                               0x0
1705 #define   FEC_OC_COMM_EXEC_STOP                                             0x0
1706 #define   FEC_OC_COMM_EXEC_ACTIVE                                           0x1
1707 #define   FEC_OC_COMM_EXEC_HOLD                                             0x2
1708 
1709 #define FEC_OC_COMM_MB__A                                                   0x2440002
1710 #define FEC_OC_COMM_MB__W                                                   2
1711 #define FEC_OC_COMM_MB__M                                                   0x3
1712 #define FEC_OC_COMM_MB__PRE                                                 0x0
1713 #define   FEC_OC_COMM_MB_CTL__B                                             0
1714 #define   FEC_OC_COMM_MB_CTL__W                                             1
1715 #define   FEC_OC_COMM_MB_CTL__M                                             0x1
1716 #define   FEC_OC_COMM_MB_CTL__PRE                                           0x0
1717 #define     FEC_OC_COMM_MB_CTL_OFF                                          0x0
1718 #define     FEC_OC_COMM_MB_CTL_ON                                           0x1
1719 #define   FEC_OC_COMM_MB_OBS__B                                             1
1720 #define   FEC_OC_COMM_MB_OBS__W                                             1
1721 #define   FEC_OC_COMM_MB_OBS__M                                             0x2
1722 #define   FEC_OC_COMM_MB_OBS__PRE                                           0x0
1723 #define     FEC_OC_COMM_MB_OBS_OFF                                          0x0
1724 #define     FEC_OC_COMM_MB_OBS_ON                                           0x2
1725 
1726 #define FEC_OC_COMM_INT_REQ__A                                              0x2440003
1727 #define FEC_OC_COMM_INT_REQ__W                                              1
1728 #define FEC_OC_COMM_INT_REQ__M                                              0x1
1729 #define FEC_OC_COMM_INT_REQ__PRE                                            0x0
1730 #define FEC_OC_COMM_INT_STA__A                                              0x2440005
1731 #define FEC_OC_COMM_INT_STA__W                                              8
1732 #define FEC_OC_COMM_INT_STA__M                                              0xFF
1733 #define FEC_OC_COMM_INT_STA__PRE                                            0x0
1734 
1735 #define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B                               0
1736 #define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W                               1
1737 #define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M                               0x1
1738 #define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE                             0x0
1739 
1740 #define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B                               1
1741 #define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W                               1
1742 #define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M                               0x2
1743 #define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE                             0x0
1744 
1745 #define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__B                               2
1746 #define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__W                               1
1747 #define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__M                               0x4
1748 #define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE                             0x0
1749 
1750 #define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__B                                3
1751 #define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__W                                1
1752 #define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__M                                0x8
1753 #define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE                              0x0
1754 
1755 #define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B                              4
1756 #define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W                              1
1757 #define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M                              0x10
1758 #define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE                            0x0
1759 
1760 #define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B                             5
1761 #define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W                             1
1762 #define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M                             0x20
1763 #define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE                           0x0
1764 
1765 #define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B                                6
1766 #define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W                                1
1767 #define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M                                0x40
1768 #define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE                              0x0
1769 
1770 #define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__B                               7
1771 #define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__W                               1
1772 #define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__M                               0x80
1773 #define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE                             0x0
1774 
1775 #define FEC_OC_COMM_INT_MSK__A                                              0x2440006
1776 #define FEC_OC_COMM_INT_MSK__W                                              8
1777 #define FEC_OC_COMM_INT_MSK__M                                              0xFF
1778 #define FEC_OC_COMM_INT_MSK__PRE                                            0x0
1779 #define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B                               0
1780 #define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W                               1
1781 #define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M                               0x1
1782 #define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE                             0x0
1783 #define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B                               1
1784 #define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W                               1
1785 #define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M                               0x2
1786 #define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE                             0x0
1787 #define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B                               2
1788 #define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W                               1
1789 #define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M                               0x4
1790 #define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE                             0x0
1791 #define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B                                3
1792 #define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W                                1
1793 #define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M                                0x8
1794 #define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE                              0x0
1795 #define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B                              4
1796 #define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W                              1
1797 #define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M                              0x10
1798 #define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE                            0x0
1799 #define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B                             5
1800 #define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W                             1
1801 #define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M                             0x20
1802 #define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE                           0x0
1803 #define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B                                6
1804 #define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W                                1
1805 #define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M                                0x40
1806 #define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE                              0x0
1807 #define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B                               7
1808 #define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W                               1
1809 #define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M                               0x80
1810 #define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE                             0x0
1811 
1812 #define FEC_OC_COMM_INT_STM__A                                              0x2440007
1813 #define FEC_OC_COMM_INT_STM__W                                              8
1814 #define FEC_OC_COMM_INT_STM__M                                              0xFF
1815 #define FEC_OC_COMM_INT_STM__PRE                                            0x0
1816 #define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B                               0
1817 #define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W                               1
1818 #define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M                               0x1
1819 #define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE                             0x0
1820 #define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B                               1
1821 #define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W                               1
1822 #define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M                               0x2
1823 #define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE                             0x0
1824 #define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B                               2
1825 #define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W                               1
1826 #define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M                               0x4
1827 #define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE                             0x0
1828 #define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B                                3
1829 #define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W                                1
1830 #define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M                                0x8
1831 #define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE                              0x0
1832 #define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B                              4
1833 #define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W                              1
1834 #define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M                              0x10
1835 #define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE                            0x0
1836 #define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B                             5
1837 #define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W                             1
1838 #define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M                             0x20
1839 #define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE                           0x0
1840 #define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B                                6
1841 #define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W                                1
1842 #define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M                                0x40
1843 #define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE                              0x0
1844 #define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B                               7
1845 #define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W                               1
1846 #define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M                               0x80
1847 #define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE                             0x0
1848 
1849 #define FEC_OC_STATUS__A                                                    0x2440010
1850 #define FEC_OC_STATUS__W                                                    5
1851 #define FEC_OC_STATUS__M                                                    0x1F
1852 #define FEC_OC_STATUS__PRE                                                  0x0
1853 
1854 #define   FEC_OC_STATUS_DPR_STATUS__B                                       0
1855 #define   FEC_OC_STATUS_DPR_STATUS__W                                       1
1856 #define   FEC_OC_STATUS_DPR_STATUS__M                                       0x1
1857 #define   FEC_OC_STATUS_DPR_STATUS__PRE                                     0x0
1858 
1859 #define   FEC_OC_STATUS_SNC_STATUS__B                                       1
1860 #define   FEC_OC_STATUS_SNC_STATUS__W                                       2
1861 #define   FEC_OC_STATUS_SNC_STATUS__M                                       0x6
1862 #define   FEC_OC_STATUS_SNC_STATUS__PRE                                     0x0
1863 
1864 #define   FEC_OC_STATUS_FIFO_FULL__B                                        3
1865 #define   FEC_OC_STATUS_FIFO_FULL__W                                        1
1866 #define   FEC_OC_STATUS_FIFO_FULL__M                                        0x8
1867 #define   FEC_OC_STATUS_FIFO_FULL__PRE                                      0x0
1868 
1869 #define   FEC_OC_STATUS_FIFO_EMPTY__B                                       4
1870 #define   FEC_OC_STATUS_FIFO_EMPTY__W                                       1
1871 #define   FEC_OC_STATUS_FIFO_EMPTY__M                                       0x10
1872 #define   FEC_OC_STATUS_FIFO_EMPTY__PRE                                     0x0
1873 
1874 #define FEC_OC_MODE__A                                                      0x2440011
1875 #define FEC_OC_MODE__W                                                      4
1876 #define FEC_OC_MODE__M                                                      0xF
1877 #define FEC_OC_MODE__PRE                                                    0x0
1878 
1879 #define   FEC_OC_MODE_PARITY__B                                             0
1880 #define   FEC_OC_MODE_PARITY__W                                             1
1881 #define   FEC_OC_MODE_PARITY__M                                             0x1
1882 #define   FEC_OC_MODE_PARITY__PRE                                           0x0
1883 
1884 #define   FEC_OC_MODE_TRANSPARENT__B                                        1
1885 #define   FEC_OC_MODE_TRANSPARENT__W                                        1
1886 #define   FEC_OC_MODE_TRANSPARENT__M                                        0x2
1887 #define   FEC_OC_MODE_TRANSPARENT__PRE                                      0x0
1888 
1889 #define   FEC_OC_MODE_CLEAR__B                                              2
1890 #define   FEC_OC_MODE_CLEAR__W                                              1
1891 #define   FEC_OC_MODE_CLEAR__M                                              0x4
1892 #define   FEC_OC_MODE_CLEAR__PRE                                            0x0
1893 
1894 #define   FEC_OC_MODE_RETAIN_FRAMING__B                                     3
1895 #define   FEC_OC_MODE_RETAIN_FRAMING__W                                     1
1896 #define   FEC_OC_MODE_RETAIN_FRAMING__M                                     0x8
1897 #define   FEC_OC_MODE_RETAIN_FRAMING__PRE                                   0x0
1898 
1899 #define FEC_OC_DPR_MODE__A                                                  0x2440012
1900 #define FEC_OC_DPR_MODE__W                                                  2
1901 #define FEC_OC_DPR_MODE__M                                                  0x3
1902 #define FEC_OC_DPR_MODE__PRE                                                0x0
1903 
1904 #define   FEC_OC_DPR_MODE_ERR_DISABLE__B                                    0
1905 #define   FEC_OC_DPR_MODE_ERR_DISABLE__W                                    1
1906 #define   FEC_OC_DPR_MODE_ERR_DISABLE__M                                    0x1
1907 #define   FEC_OC_DPR_MODE_ERR_DISABLE__PRE                                  0x0
1908 
1909 #define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__B                                  1
1910 #define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__W                                  1
1911 #define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__M                                  0x2
1912 #define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE                                0x0
1913 
1914 #define FEC_OC_DPR_UNLOCK__A                                                0x2440013
1915 #define FEC_OC_DPR_UNLOCK__W                                                1
1916 #define FEC_OC_DPR_UNLOCK__M                                                0x1
1917 #define FEC_OC_DPR_UNLOCK__PRE                                              0x0
1918 #define FEC_OC_DTO_MODE__A                                                  0x2440014
1919 #define FEC_OC_DTO_MODE__W                                                  3
1920 #define FEC_OC_DTO_MODE__M                                                  0x7
1921 #define FEC_OC_DTO_MODE__PRE                                                0x0
1922 
1923 #define   FEC_OC_DTO_MODE_DYNAMIC__B                                        0
1924 #define   FEC_OC_DTO_MODE_DYNAMIC__W                                        1
1925 #define   FEC_OC_DTO_MODE_DYNAMIC__M                                        0x1
1926 #define   FEC_OC_DTO_MODE_DYNAMIC__PRE                                      0x0
1927 
1928 #define   FEC_OC_DTO_MODE_DUTY_CYCLE__B                                     1
1929 #define   FEC_OC_DTO_MODE_DUTY_CYCLE__W                                     1
1930 #define   FEC_OC_DTO_MODE_DUTY_CYCLE__M                                     0x2
1931 #define   FEC_OC_DTO_MODE_DUTY_CYCLE__PRE                                   0x0
1932 
1933 #define   FEC_OC_DTO_MODE_OFFSET_ENABLE__B                                  2
1934 #define   FEC_OC_DTO_MODE_OFFSET_ENABLE__W                                  1
1935 #define   FEC_OC_DTO_MODE_OFFSET_ENABLE__M                                  0x4
1936 #define   FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE                                0x0
1937 
1938 #define FEC_OC_DTO_PERIOD__A                                                0x2440015
1939 #define FEC_OC_DTO_PERIOD__W                                                8
1940 #define FEC_OC_DTO_PERIOD__M                                                0xFF
1941 #define FEC_OC_DTO_PERIOD__PRE                                              0x0
1942 #define FEC_OC_DTO_RATE_LO__A                                               0x2440016
1943 #define FEC_OC_DTO_RATE_LO__W                                               16
1944 #define FEC_OC_DTO_RATE_LO__M                                               0xFFFF
1945 #define FEC_OC_DTO_RATE_LO__PRE                                             0x0
1946 
1947 #define   FEC_OC_DTO_RATE_LO_RATE_LO__B                                     0
1948 #define   FEC_OC_DTO_RATE_LO_RATE_LO__W                                     16
1949 #define   FEC_OC_DTO_RATE_LO_RATE_LO__M                                     0xFFFF
1950 #define   FEC_OC_DTO_RATE_LO_RATE_LO__PRE                                   0x0
1951 
1952 #define FEC_OC_DTO_RATE_HI__A                                               0x2440017
1953 #define FEC_OC_DTO_RATE_HI__W                                               10
1954 #define FEC_OC_DTO_RATE_HI__M                                               0x3FF
1955 #define FEC_OC_DTO_RATE_HI__PRE                                             0xC0
1956 
1957 #define   FEC_OC_DTO_RATE_HI_RATE_HI__B                                     0
1958 #define   FEC_OC_DTO_RATE_HI_RATE_HI__W                                     10
1959 #define   FEC_OC_DTO_RATE_HI_RATE_HI__M                                     0x3FF
1960 #define   FEC_OC_DTO_RATE_HI_RATE_HI__PRE                                   0xC0
1961 
1962 #define FEC_OC_DTO_BURST_LEN__A                                             0x2440018
1963 #define FEC_OC_DTO_BURST_LEN__W                                             8
1964 #define FEC_OC_DTO_BURST_LEN__M                                             0xFF
1965 #define FEC_OC_DTO_BURST_LEN__PRE                                           0xBC
1966 
1967 #define   FEC_OC_DTO_BURST_LEN_BURST_LEN__B                                 0
1968 #define   FEC_OC_DTO_BURST_LEN_BURST_LEN__W                                 8
1969 #define   FEC_OC_DTO_BURST_LEN_BURST_LEN__M                                 0xFF
1970 #define   FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE                               0xBC
1971 
1972 #define FEC_OC_FCT_MODE__A                                                  0x244001A
1973 #define FEC_OC_FCT_MODE__W                                                  2
1974 #define FEC_OC_FCT_MODE__M                                                  0x3
1975 #define FEC_OC_FCT_MODE__PRE                                                0x0
1976 
1977 #define   FEC_OC_FCT_MODE_RAT_ENA__B                                        0
1978 #define   FEC_OC_FCT_MODE_RAT_ENA__W                                        1
1979 #define   FEC_OC_FCT_MODE_RAT_ENA__M                                        0x1
1980 #define   FEC_OC_FCT_MODE_RAT_ENA__PRE                                      0x0
1981 
1982 #define   FEC_OC_FCT_MODE_VIRT_ENA__B                                       1
1983 #define   FEC_OC_FCT_MODE_VIRT_ENA__W                                       1
1984 #define   FEC_OC_FCT_MODE_VIRT_ENA__M                                       0x2
1985 #define   FEC_OC_FCT_MODE_VIRT_ENA__PRE                                     0x0
1986 
1987 #define FEC_OC_FCT_USAGE__A                                                 0x244001B
1988 #define FEC_OC_FCT_USAGE__W                                                 3
1989 #define FEC_OC_FCT_USAGE__M                                                 0x7
1990 #define FEC_OC_FCT_USAGE__PRE                                               0x2
1991 
1992 #define   FEC_OC_FCT_USAGE_USAGE__B                                         0
1993 #define   FEC_OC_FCT_USAGE_USAGE__W                                         3
1994 #define   FEC_OC_FCT_USAGE_USAGE__M                                         0x7
1995 #define   FEC_OC_FCT_USAGE_USAGE__PRE                                       0x2
1996 
1997 #define FEC_OC_FCT_OCCUPATION__A                                            0x244001C
1998 #define FEC_OC_FCT_OCCUPATION__W                                            12
1999 #define FEC_OC_FCT_OCCUPATION__M                                            0xFFF
2000 #define FEC_OC_FCT_OCCUPATION__PRE                                          0x0
2001 
2002 #define   FEC_OC_FCT_OCCUPATION_OCCUPATION__B                               0
2003 #define   FEC_OC_FCT_OCCUPATION_OCCUPATION__W                               12
2004 #define   FEC_OC_FCT_OCCUPATION_OCCUPATION__M                               0xFFF
2005 #define   FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE                             0x0
2006 
2007 #define FEC_OC_TMD_MODE__A                                                  0x244001E
2008 #define FEC_OC_TMD_MODE__W                                                  3
2009 #define FEC_OC_TMD_MODE__M                                                  0x7
2010 #define FEC_OC_TMD_MODE__PRE                                                0x4
2011 
2012 #define   FEC_OC_TMD_MODE_MODE__B                                           0
2013 #define   FEC_OC_TMD_MODE_MODE__W                                           3
2014 #define   FEC_OC_TMD_MODE_MODE__M                                           0x7
2015 #define   FEC_OC_TMD_MODE_MODE__PRE                                         0x4
2016 
2017 #define FEC_OC_TMD_COUNT__A                                                 0x244001F
2018 #define FEC_OC_TMD_COUNT__W                                                 10
2019 #define FEC_OC_TMD_COUNT__M                                                 0x3FF
2020 #define FEC_OC_TMD_COUNT__PRE                                               0x1F4
2021 
2022 #define   FEC_OC_TMD_COUNT_COUNT__B                                         0
2023 #define   FEC_OC_TMD_COUNT_COUNT__W                                         10
2024 #define   FEC_OC_TMD_COUNT_COUNT__M                                         0x3FF
2025 #define   FEC_OC_TMD_COUNT_COUNT__PRE                                       0x1F4
2026 
2027 #define FEC_OC_TMD_HI_MARGIN__A                                             0x2440020
2028 #define FEC_OC_TMD_HI_MARGIN__W                                             11
2029 #define FEC_OC_TMD_HI_MARGIN__M                                             0x7FF
2030 #define FEC_OC_TMD_HI_MARGIN__PRE                                           0x200
2031 
2032 #define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B                                 0
2033 #define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W                                 11
2034 #define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M                                 0x7FF
2035 #define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE                               0x200
2036 
2037 #define FEC_OC_TMD_LO_MARGIN__A                                             0x2440021
2038 #define FEC_OC_TMD_LO_MARGIN__W                                             11
2039 #define FEC_OC_TMD_LO_MARGIN__M                                             0x7FF
2040 #define FEC_OC_TMD_LO_MARGIN__PRE                                           0x100
2041 
2042 #define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B                                 0
2043 #define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W                                 11
2044 #define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M                                 0x7FF
2045 #define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE                               0x100
2046 
2047 #define FEC_OC_TMD_CTL_UPD_RATE__A                                          0x2440022
2048 #define FEC_OC_TMD_CTL_UPD_RATE__W                                          4
2049 #define FEC_OC_TMD_CTL_UPD_RATE__M                                          0xF
2050 #define FEC_OC_TMD_CTL_UPD_RATE__PRE                                        0x1
2051 
2052 #define   FEC_OC_TMD_CTL_UPD_RATE_RATE__B                                   0
2053 #define   FEC_OC_TMD_CTL_UPD_RATE_RATE__W                                   4
2054 #define   FEC_OC_TMD_CTL_UPD_RATE_RATE__M                                   0xF
2055 #define   FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE                                 0x1
2056 
2057 #define FEC_OC_TMD_INT_UPD_RATE__A                                          0x2440023
2058 #define FEC_OC_TMD_INT_UPD_RATE__W                                          4
2059 #define FEC_OC_TMD_INT_UPD_RATE__M                                          0xF
2060 #define FEC_OC_TMD_INT_UPD_RATE__PRE                                        0x4
2061 
2062 #define   FEC_OC_TMD_INT_UPD_RATE_RATE__B                                   0
2063 #define   FEC_OC_TMD_INT_UPD_RATE_RATE__W                                   4
2064 #define   FEC_OC_TMD_INT_UPD_RATE_RATE__M                                   0xF
2065 #define   FEC_OC_TMD_INT_UPD_RATE_RATE__PRE                                 0x4
2066 
2067 #define FEC_OC_AVR_PARM_A__A                                                0x2440026
2068 #define FEC_OC_AVR_PARM_A__W                                                4
2069 #define FEC_OC_AVR_PARM_A__M                                                0xF
2070 #define FEC_OC_AVR_PARM_A__PRE                                              0x6
2071 
2072 #define   FEC_OC_AVR_PARM_A_PARM__B                                         0
2073 #define   FEC_OC_AVR_PARM_A_PARM__W                                         4
2074 #define   FEC_OC_AVR_PARM_A_PARM__M                                         0xF
2075 #define   FEC_OC_AVR_PARM_A_PARM__PRE                                       0x6
2076 
2077 #define FEC_OC_AVR_PARM_B__A                                                0x2440027
2078 #define FEC_OC_AVR_PARM_B__W                                                4
2079 #define FEC_OC_AVR_PARM_B__M                                                0xF
2080 #define FEC_OC_AVR_PARM_B__PRE                                              0x4
2081 
2082 #define   FEC_OC_AVR_PARM_B_PARM__B                                         0
2083 #define   FEC_OC_AVR_PARM_B_PARM__W                                         4
2084 #define   FEC_OC_AVR_PARM_B_PARM__M                                         0xF
2085 #define   FEC_OC_AVR_PARM_B_PARM__PRE                                       0x4
2086 
2087 #define FEC_OC_AVR_AVG_LO__A                                                0x2440028
2088 #define FEC_OC_AVR_AVG_LO__W                                                16
2089 #define FEC_OC_AVR_AVG_LO__M                                                0xFFFF
2090 #define FEC_OC_AVR_AVG_LO__PRE                                              0x0
2091 
2092 #define   FEC_OC_AVR_AVG_LO_AVG_LO__B                                       0
2093 #define   FEC_OC_AVR_AVG_LO_AVG_LO__W                                       16
2094 #define   FEC_OC_AVR_AVG_LO_AVG_LO__M                                       0xFFFF
2095 #define   FEC_OC_AVR_AVG_LO_AVG_LO__PRE                                     0x0
2096 
2097 #define FEC_OC_AVR_AVG_HI__A                                                0x2440029
2098 #define FEC_OC_AVR_AVG_HI__W                                                6
2099 #define FEC_OC_AVR_AVG_HI__M                                                0x3F
2100 #define FEC_OC_AVR_AVG_HI__PRE                                              0x0
2101 
2102 #define   FEC_OC_AVR_AVG_HI_AVG_HI__B                                       0
2103 #define   FEC_OC_AVR_AVG_HI_AVG_HI__W                                       6
2104 #define   FEC_OC_AVR_AVG_HI_AVG_HI__M                                       0x3F
2105 #define   FEC_OC_AVR_AVG_HI_AVG_HI__PRE                                     0x0
2106 
2107 #define FEC_OC_RCN_MODE__A                                                  0x244002C
2108 #define FEC_OC_RCN_MODE__W                                                  5
2109 #define FEC_OC_RCN_MODE__M                                                  0x1F
2110 #define FEC_OC_RCN_MODE__PRE                                                0x1F
2111 
2112 #define   FEC_OC_RCN_MODE_MODE__B                                           0
2113 #define   FEC_OC_RCN_MODE_MODE__W                                           5
2114 #define   FEC_OC_RCN_MODE_MODE__M                                           0x1F
2115 #define   FEC_OC_RCN_MODE_MODE__PRE                                         0x1F
2116 
2117 #define FEC_OC_RCN_OCC_SETTLE__A                                            0x244002D
2118 #define FEC_OC_RCN_OCC_SETTLE__W                                            11
2119 #define FEC_OC_RCN_OCC_SETTLE__M                                            0x7FF
2120 #define FEC_OC_RCN_OCC_SETTLE__PRE                                          0x180
2121 
2122 #define   FEC_OC_RCN_OCC_SETTLE_LEVEL__B                                    0
2123 #define   FEC_OC_RCN_OCC_SETTLE_LEVEL__W                                    11
2124 #define   FEC_OC_RCN_OCC_SETTLE_LEVEL__M                                    0x7FF
2125 #define   FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE                                  0x180
2126 
2127 #define FEC_OC_RCN_GAIN__A                                                  0x244002E
2128 #define FEC_OC_RCN_GAIN__W                                                  4
2129 #define FEC_OC_RCN_GAIN__M                                                  0xF
2130 #define FEC_OC_RCN_GAIN__PRE                                                0xC
2131 
2132 #define   FEC_OC_RCN_GAIN_GAIN__B                                           0
2133 #define   FEC_OC_RCN_GAIN_GAIN__W                                           4
2134 #define   FEC_OC_RCN_GAIN_GAIN__M                                           0xF
2135 #define   FEC_OC_RCN_GAIN_GAIN__PRE                                         0xC
2136 
2137 #define FEC_OC_RCN_CTL_RATE_LO__A                                           0x2440030
2138 #define FEC_OC_RCN_CTL_RATE_LO__W                                           16
2139 #define FEC_OC_RCN_CTL_RATE_LO__M                                           0xFFFF
2140 #define FEC_OC_RCN_CTL_RATE_LO__PRE                                         0x0
2141 
2142 #define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B                                  0
2143 #define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W                                  16
2144 #define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M                                  0xFFFF
2145 #define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE                                0x0
2146 
2147 #define FEC_OC_RCN_CTL_RATE_HI__A                                           0x2440031
2148 #define FEC_OC_RCN_CTL_RATE_HI__W                                           8
2149 #define FEC_OC_RCN_CTL_RATE_HI__M                                           0xFF
2150 #define FEC_OC_RCN_CTL_RATE_HI__PRE                                         0xC0
2151 
2152 #define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B                                  0
2153 #define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W                                  8
2154 #define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M                                  0xFF
2155 #define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE                                0xC0
2156 
2157 #define FEC_OC_RCN_CTL_STEP_LO__A                                           0x2440032
2158 #define FEC_OC_RCN_CTL_STEP_LO__W                                           16
2159 #define FEC_OC_RCN_CTL_STEP_LO__M                                           0xFFFF
2160 #define FEC_OC_RCN_CTL_STEP_LO__PRE                                         0x0
2161 
2162 #define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B                                  0
2163 #define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W                                  16
2164 #define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M                                  0xFFFF
2165 #define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE                                0x0
2166 
2167 #define FEC_OC_RCN_CTL_STEP_HI__A                                           0x2440033
2168 #define FEC_OC_RCN_CTL_STEP_HI__W                                           8
2169 #define FEC_OC_RCN_CTL_STEP_HI__M                                           0xFF
2170 #define FEC_OC_RCN_CTL_STEP_HI__PRE                                         0x8
2171 
2172 #define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B                                  0
2173 #define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W                                  8
2174 #define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M                                  0xFF
2175 #define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE                                0x8
2176 
2177 #define FEC_OC_RCN_DTO_OFS_LO__A                                            0x2440034
2178 #define FEC_OC_RCN_DTO_OFS_LO__W                                            16
2179 #define FEC_OC_RCN_DTO_OFS_LO__M                                            0xFFFF
2180 #define FEC_OC_RCN_DTO_OFS_LO__PRE                                          0x0
2181 
2182 #define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B                                   0
2183 #define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W                                   16
2184 #define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M                                   0xFFFF
2185 #define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE                                 0x0
2186 
2187 #define FEC_OC_RCN_DTO_OFS_HI__A                                            0x2440035
2188 #define FEC_OC_RCN_DTO_OFS_HI__W                                            8
2189 #define FEC_OC_RCN_DTO_OFS_HI__M                                            0xFF
2190 #define FEC_OC_RCN_DTO_OFS_HI__PRE                                          0x0
2191 
2192 #define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B                                   0
2193 #define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W                                   8
2194 #define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M                                   0xFF
2195 #define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE                                 0x0
2196 
2197 #define FEC_OC_RCN_DTO_RATE_LO__A                                           0x2440036
2198 #define FEC_OC_RCN_DTO_RATE_LO__W                                           16
2199 #define FEC_OC_RCN_DTO_RATE_LO__M                                           0xFFFF
2200 #define FEC_OC_RCN_DTO_RATE_LO__PRE                                         0x0
2201 
2202 #define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B                                  0
2203 #define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W                                  16
2204 #define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M                                  0xFFFF
2205 #define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE                                0x0
2206 
2207 #define FEC_OC_RCN_DTO_RATE_HI__A                                           0x2440037
2208 #define FEC_OC_RCN_DTO_RATE_HI__W                                           8
2209 #define FEC_OC_RCN_DTO_RATE_HI__M                                           0xFF
2210 #define FEC_OC_RCN_DTO_RATE_HI__PRE                                         0x0
2211 
2212 #define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B                                  0
2213 #define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W                                  8
2214 #define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M                                  0xFF
2215 #define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE                                0x0
2216 
2217 #define FEC_OC_RCN_RATE_CLIP_LO__A                                          0x2440038
2218 #define FEC_OC_RCN_RATE_CLIP_LO__W                                          16
2219 #define FEC_OC_RCN_RATE_CLIP_LO__M                                          0xFFFF
2220 #define FEC_OC_RCN_RATE_CLIP_LO__PRE                                        0x0
2221 
2222 #define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B                                0
2223 #define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W                                16
2224 #define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M                                0xFFFF
2225 #define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE                              0x0
2226 
2227 #define FEC_OC_RCN_RATE_CLIP_HI__A                                          0x2440039
2228 #define FEC_OC_RCN_RATE_CLIP_HI__W                                          8
2229 #define FEC_OC_RCN_RATE_CLIP_HI__M                                          0xFF
2230 #define FEC_OC_RCN_RATE_CLIP_HI__PRE                                        0xF0
2231 
2232 #define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B                                0
2233 #define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W                                8
2234 #define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M                                0xFF
2235 #define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE                              0xF0
2236 
2237 #define FEC_OC_RCN_DYN_RATE_LO__A                                           0x244003A
2238 #define FEC_OC_RCN_DYN_RATE_LO__W                                           16
2239 #define FEC_OC_RCN_DYN_RATE_LO__M                                           0xFFFF
2240 #define FEC_OC_RCN_DYN_RATE_LO__PRE                                         0x0
2241 
2242 #define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B                                 0
2243 #define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W                                 16
2244 #define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M                                 0xFFFF
2245 #define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE                               0x0
2246 
2247 #define FEC_OC_RCN_DYN_RATE_HI__A                                           0x244003B
2248 #define FEC_OC_RCN_DYN_RATE_HI__W                                           8
2249 #define FEC_OC_RCN_DYN_RATE_HI__M                                           0xFF
2250 #define FEC_OC_RCN_DYN_RATE_HI__PRE                                         0x0
2251 
2252 #define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B                                 0
2253 #define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W                                 8
2254 #define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M                                 0xFF
2255 #define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE                               0x0
2256 
2257 #define FEC_OC_SNC_MODE__A                                                  0x2440040
2258 #define FEC_OC_SNC_MODE__W                                                  4
2259 #define FEC_OC_SNC_MODE__M                                                  0xF
2260 #define FEC_OC_SNC_MODE__PRE                                                0x0
2261 
2262 #define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__B                                  0
2263 #define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__W                                  1
2264 #define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__M                                  0x1
2265 #define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE                                0x0
2266 
2267 #define   FEC_OC_SNC_MODE_ERROR_CTL__B                                      1
2268 #define   FEC_OC_SNC_MODE_ERROR_CTL__W                                      2
2269 #define   FEC_OC_SNC_MODE_ERROR_CTL__M                                      0x6
2270 #define   FEC_OC_SNC_MODE_ERROR_CTL__PRE                                    0x0
2271 
2272 #define   FEC_OC_SNC_MODE_CORR_DISABLE__B                                   3
2273 #define   FEC_OC_SNC_MODE_CORR_DISABLE__W                                   1
2274 #define   FEC_OC_SNC_MODE_CORR_DISABLE__M                                   0x8
2275 #define   FEC_OC_SNC_MODE_CORR_DISABLE__PRE                                 0x0
2276 
2277 #define FEC_OC_SNC_LWM__A                                                   0x2440041
2278 #define FEC_OC_SNC_LWM__W                                                   4
2279 #define FEC_OC_SNC_LWM__M                                                   0xF
2280 #define FEC_OC_SNC_LWM__PRE                                                 0x3
2281 
2282 #define   FEC_OC_SNC_LWM_MARK__B                                            0
2283 #define   FEC_OC_SNC_LWM_MARK__W                                            4
2284 #define   FEC_OC_SNC_LWM_MARK__M                                            0xF
2285 #define   FEC_OC_SNC_LWM_MARK__PRE                                          0x3
2286 
2287 #define FEC_OC_SNC_HWM__A                                                   0x2440042
2288 #define FEC_OC_SNC_HWM__W                                                   4
2289 #define FEC_OC_SNC_HWM__M                                                   0xF
2290 #define FEC_OC_SNC_HWM__PRE                                                 0x5
2291 
2292 #define   FEC_OC_SNC_HWM_MARK__B                                            0
2293 #define   FEC_OC_SNC_HWM_MARK__W                                            4
2294 #define   FEC_OC_SNC_HWM_MARK__M                                            0xF
2295 #define   FEC_OC_SNC_HWM_MARK__PRE                                          0x5
2296 
2297 #define FEC_OC_SNC_UNLOCK__A                                                0x2440043
2298 #define FEC_OC_SNC_UNLOCK__W                                                1
2299 #define FEC_OC_SNC_UNLOCK__M                                                0x1
2300 #define FEC_OC_SNC_UNLOCK__PRE                                              0x0
2301 
2302 #define   FEC_OC_SNC_UNLOCK_RESTART__B                                      0
2303 #define   FEC_OC_SNC_UNLOCK_RESTART__W                                      1
2304 #define   FEC_OC_SNC_UNLOCK_RESTART__M                                      0x1
2305 #define   FEC_OC_SNC_UNLOCK_RESTART__PRE                                    0x0
2306 
2307 #define FEC_OC_SNC_LOCK_COUNT__A                                            0x2440044
2308 #define FEC_OC_SNC_LOCK_COUNT__W                                            12
2309 #define FEC_OC_SNC_LOCK_COUNT__M                                            0xFFF
2310 #define FEC_OC_SNC_LOCK_COUNT__PRE                                          0x0
2311 
2312 #define   FEC_OC_SNC_LOCK_COUNT_COUNT__B                                    0
2313 #define   FEC_OC_SNC_LOCK_COUNT_COUNT__W                                    12
2314 #define   FEC_OC_SNC_LOCK_COUNT_COUNT__M                                    0xFFF
2315 #define   FEC_OC_SNC_LOCK_COUNT_COUNT__PRE                                  0x0
2316 
2317 #define FEC_OC_SNC_FAIL_COUNT__A                                            0x2440045
2318 #define FEC_OC_SNC_FAIL_COUNT__W                                            12
2319 #define FEC_OC_SNC_FAIL_COUNT__M                                            0xFFF
2320 #define FEC_OC_SNC_FAIL_COUNT__PRE                                          0x0
2321 
2322 #define   FEC_OC_SNC_FAIL_COUNT_COUNT__B                                    0
2323 #define   FEC_OC_SNC_FAIL_COUNT_COUNT__W                                    12
2324 #define   FEC_OC_SNC_FAIL_COUNT_COUNT__M                                    0xFFF
2325 #define   FEC_OC_SNC_FAIL_COUNT_COUNT__PRE                                  0x0
2326 
2327 #define FEC_OC_SNC_FAIL_PERIOD__A                                           0x2440046
2328 #define FEC_OC_SNC_FAIL_PERIOD__W                                           16
2329 #define FEC_OC_SNC_FAIL_PERIOD__M                                           0xFFFF
2330 #define FEC_OC_SNC_FAIL_PERIOD__PRE                                         0x1171
2331 
2332 #define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__B                                  0
2333 #define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__W                                  16
2334 #define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__M                                  0xFFFF
2335 #define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE                                0x1171
2336 
2337 #define FEC_OC_EMS_MODE__A                                                  0x2440047
2338 #define FEC_OC_EMS_MODE__W                                                  2
2339 #define FEC_OC_EMS_MODE__M                                                  0x3
2340 #define FEC_OC_EMS_MODE__PRE                                                0x0
2341 
2342 #define   FEC_OC_EMS_MODE_MODE__B                                           0
2343 #define   FEC_OC_EMS_MODE_MODE__W                                           2
2344 #define   FEC_OC_EMS_MODE_MODE__M                                           0x3
2345 #define   FEC_OC_EMS_MODE_MODE__PRE                                         0x0
2346 
2347 #define FEC_OC_IPR_MODE__A                                                  0x2440048
2348 #define FEC_OC_IPR_MODE__W                                                  12
2349 #define FEC_OC_IPR_MODE__M                                                  0xFFF
2350 #define FEC_OC_IPR_MODE__PRE                                                0x0
2351 
2352 #define   FEC_OC_IPR_MODE_SERIAL__B                                         0
2353 #define   FEC_OC_IPR_MODE_SERIAL__W                                         1
2354 #define   FEC_OC_IPR_MODE_SERIAL__M                                         0x1
2355 #define   FEC_OC_IPR_MODE_SERIAL__PRE                                       0x0
2356 
2357 #define   FEC_OC_IPR_MODE_REVERSE_ORDER__B                                  1
2358 #define   FEC_OC_IPR_MODE_REVERSE_ORDER__W                                  1
2359 #define   FEC_OC_IPR_MODE_REVERSE_ORDER__M                                  0x2
2360 #define   FEC_OC_IPR_MODE_REVERSE_ORDER__PRE                                0x0
2361 
2362 #define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B                               2
2363 #define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W                               1
2364 #define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M                               0x4
2365 #define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE                             0x0
2366 
2367 #define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__B                                   3
2368 #define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__W                                   1
2369 #define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__M                                   0x8
2370 #define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE                                 0x0
2371 
2372 #define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__B                                   4
2373 #define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__W                                   1
2374 #define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__M                                   0x10
2375 #define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE                                 0x0
2376 
2377 #define   FEC_OC_IPR_MODE_MERR_DIS_PAR__B                                   5
2378 #define   FEC_OC_IPR_MODE_MERR_DIS_PAR__W                                   1
2379 #define   FEC_OC_IPR_MODE_MERR_DIS_PAR__M                                   0x20
2380 #define   FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE                                 0x0
2381 
2382 #define   FEC_OC_IPR_MODE_MD_DIS_PAR__B                                     6
2383 #define   FEC_OC_IPR_MODE_MD_DIS_PAR__W                                     1
2384 #define   FEC_OC_IPR_MODE_MD_DIS_PAR__M                                     0x40
2385 #define   FEC_OC_IPR_MODE_MD_DIS_PAR__PRE                                   0x0
2386 
2387 #define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__B                                   7
2388 #define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__W                                   1
2389 #define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__M                                   0x80
2390 #define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE                                 0x0
2391 
2392 #define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__B                                   8
2393 #define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__W                                   1
2394 #define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__M                                   0x100
2395 #define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE                                 0x0
2396 
2397 #define   FEC_OC_IPR_MODE_MERR_DIS_ERR__B                                   9
2398 #define   FEC_OC_IPR_MODE_MERR_DIS_ERR__W                                   1
2399 #define   FEC_OC_IPR_MODE_MERR_DIS_ERR__M                                   0x200
2400 #define   FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE                                 0x0
2401 
2402 #define   FEC_OC_IPR_MODE_MD_DIS_ERR__B                                     10
2403 #define   FEC_OC_IPR_MODE_MD_DIS_ERR__W                                     1
2404 #define   FEC_OC_IPR_MODE_MD_DIS_ERR__M                                     0x400
2405 #define   FEC_OC_IPR_MODE_MD_DIS_ERR__PRE                                   0x0
2406 
2407 #define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B                                  11
2408 #define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W                                  1
2409 #define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M                                  0x800
2410 #define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE                                0x0
2411 
2412 #define FEC_OC_IPR_INVERT__A                                                0x2440049
2413 #define FEC_OC_IPR_INVERT__W                                                12
2414 #define FEC_OC_IPR_INVERT__M                                                0xFFF
2415 #define FEC_OC_IPR_INVERT__PRE                                              0x0
2416 
2417 #define   FEC_OC_IPR_INVERT_MD0__B                                          0
2418 #define   FEC_OC_IPR_INVERT_MD0__W                                          1
2419 #define   FEC_OC_IPR_INVERT_MD0__M                                          0x1
2420 #define   FEC_OC_IPR_INVERT_MD0__PRE                                        0x0
2421 
2422 #define   FEC_OC_IPR_INVERT_MD1__B                                          1
2423 #define   FEC_OC_IPR_INVERT_MD1__W                                          1
2424 #define   FEC_OC_IPR_INVERT_MD1__M                                          0x2
2425 #define   FEC_OC_IPR_INVERT_MD1__PRE                                        0x0
2426 
2427 #define   FEC_OC_IPR_INVERT_MD2__B                                          2
2428 #define   FEC_OC_IPR_INVERT_MD2__W                                          1
2429 #define   FEC_OC_IPR_INVERT_MD2__M                                          0x4
2430 #define   FEC_OC_IPR_INVERT_MD2__PRE                                        0x0
2431 
2432 #define   FEC_OC_IPR_INVERT_MD3__B                                          3
2433 #define   FEC_OC_IPR_INVERT_MD3__W                                          1
2434 #define   FEC_OC_IPR_INVERT_MD3__M                                          0x8
2435 #define   FEC_OC_IPR_INVERT_MD3__PRE                                        0x0
2436 
2437 #define   FEC_OC_IPR_INVERT_MD4__B                                          4
2438 #define   FEC_OC_IPR_INVERT_MD4__W                                          1
2439 #define   FEC_OC_IPR_INVERT_MD4__M                                          0x10
2440 #define   FEC_OC_IPR_INVERT_MD4__PRE                                        0x0
2441 
2442 #define   FEC_OC_IPR_INVERT_MD5__B                                          5
2443 #define   FEC_OC_IPR_INVERT_MD5__W                                          1
2444 #define   FEC_OC_IPR_INVERT_MD5__M                                          0x20
2445 #define   FEC_OC_IPR_INVERT_MD5__PRE                                        0x0
2446 
2447 #define   FEC_OC_IPR_INVERT_MD6__B                                          6
2448 #define   FEC_OC_IPR_INVERT_MD6__W                                          1
2449 #define   FEC_OC_IPR_INVERT_MD6__M                                          0x40
2450 #define   FEC_OC_IPR_INVERT_MD6__PRE                                        0x0
2451 
2452 #define   FEC_OC_IPR_INVERT_MD7__B                                          7
2453 #define   FEC_OC_IPR_INVERT_MD7__W                                          1
2454 #define   FEC_OC_IPR_INVERT_MD7__M                                          0x80
2455 #define   FEC_OC_IPR_INVERT_MD7__PRE                                        0x0
2456 
2457 #define   FEC_OC_IPR_INVERT_MERR__B                                         8
2458 #define   FEC_OC_IPR_INVERT_MERR__W                                         1
2459 #define   FEC_OC_IPR_INVERT_MERR__M                                         0x100
2460 #define   FEC_OC_IPR_INVERT_MERR__PRE                                       0x0
2461 
2462 #define   FEC_OC_IPR_INVERT_MSTRT__B                                        9
2463 #define   FEC_OC_IPR_INVERT_MSTRT__W                                        1
2464 #define   FEC_OC_IPR_INVERT_MSTRT__M                                        0x200
2465 #define   FEC_OC_IPR_INVERT_MSTRT__PRE                                      0x0
2466 
2467 #define   FEC_OC_IPR_INVERT_MVAL__B                                         10
2468 #define   FEC_OC_IPR_INVERT_MVAL__W                                         1
2469 #define   FEC_OC_IPR_INVERT_MVAL__M                                         0x400
2470 #define   FEC_OC_IPR_INVERT_MVAL__PRE                                       0x0
2471 
2472 #define   FEC_OC_IPR_INVERT_MCLK__B                                         11
2473 #define   FEC_OC_IPR_INVERT_MCLK__W                                         1
2474 #define   FEC_OC_IPR_INVERT_MCLK__M                                         0x800
2475 #define   FEC_OC_IPR_INVERT_MCLK__PRE                                       0x0
2476 
2477 #define FEC_OC_OCR_MODE__A                                                  0x2440050
2478 #define FEC_OC_OCR_MODE__W                                                  4
2479 #define FEC_OC_OCR_MODE__M                                                  0xF
2480 #define FEC_OC_OCR_MODE__PRE                                                0x0
2481 
2482 #define   FEC_OC_OCR_MODE_MB_SELECT__B                                      0
2483 #define   FEC_OC_OCR_MODE_MB_SELECT__W                                      1
2484 #define   FEC_OC_OCR_MODE_MB_SELECT__M                                      0x1
2485 #define   FEC_OC_OCR_MODE_MB_SELECT__PRE                                    0x0
2486 
2487 #define   FEC_OC_OCR_MODE_GRAB_ENABLE__B                                    1
2488 #define   FEC_OC_OCR_MODE_GRAB_ENABLE__W                                    1
2489 #define   FEC_OC_OCR_MODE_GRAB_ENABLE__M                                    0x2
2490 #define   FEC_OC_OCR_MODE_GRAB_ENABLE__PRE                                  0x0
2491 
2492 #define   FEC_OC_OCR_MODE_GRAB_SELECT__B                                    2
2493 #define   FEC_OC_OCR_MODE_GRAB_SELECT__W                                    1
2494 #define   FEC_OC_OCR_MODE_GRAB_SELECT__M                                    0x4
2495 #define   FEC_OC_OCR_MODE_GRAB_SELECT__PRE                                  0x0
2496 
2497 #define   FEC_OC_OCR_MODE_GRAB_COUNTED__B                                   3
2498 #define   FEC_OC_OCR_MODE_GRAB_COUNTED__W                                   1
2499 #define   FEC_OC_OCR_MODE_GRAB_COUNTED__M                                   0x8
2500 #define   FEC_OC_OCR_MODE_GRAB_COUNTED__PRE                                 0x0
2501 
2502 #define FEC_OC_OCR_RATE__A                                                  0x2440051
2503 #define FEC_OC_OCR_RATE__W                                                  4
2504 #define FEC_OC_OCR_RATE__M                                                  0xF
2505 #define FEC_OC_OCR_RATE__PRE                                                0x0
2506 
2507 #define   FEC_OC_OCR_RATE_RATE__B                                           0
2508 #define   FEC_OC_OCR_RATE_RATE__W                                           4
2509 #define   FEC_OC_OCR_RATE_RATE__M                                           0xF
2510 #define   FEC_OC_OCR_RATE_RATE__PRE                                         0x0
2511 
2512 #define FEC_OC_OCR_INVERT__A                                                0x2440052
2513 #define FEC_OC_OCR_INVERT__W                                                12
2514 #define FEC_OC_OCR_INVERT__M                                                0xFFF
2515 #define FEC_OC_OCR_INVERT__PRE                                              0x800
2516 
2517 #define   FEC_OC_OCR_INVERT_INVERT__B                                       0
2518 #define   FEC_OC_OCR_INVERT_INVERT__W                                       12
2519 #define   FEC_OC_OCR_INVERT_INVERT__M                                       0xFFF
2520 #define   FEC_OC_OCR_INVERT_INVERT__PRE                                     0x800
2521 
2522 #define FEC_OC_OCR_GRAB_COUNT__A                                            0x2440053
2523 #define FEC_OC_OCR_GRAB_COUNT__W                                            16
2524 #define FEC_OC_OCR_GRAB_COUNT__M                                            0xFFFF
2525 #define FEC_OC_OCR_GRAB_COUNT__PRE                                          0x0
2526 
2527 #define   FEC_OC_OCR_GRAB_COUNT_COUNT__B                                    0
2528 #define   FEC_OC_OCR_GRAB_COUNT_COUNT__W                                    16
2529 #define   FEC_OC_OCR_GRAB_COUNT_COUNT__M                                    0xFFFF
2530 #define   FEC_OC_OCR_GRAB_COUNT_COUNT__PRE                                  0x0
2531 
2532 #define FEC_OC_OCR_GRAB_SYNC__A                                             0x2440054
2533 #define FEC_OC_OCR_GRAB_SYNC__W                                             8
2534 #define FEC_OC_OCR_GRAB_SYNC__M                                             0xFF
2535 #define FEC_OC_OCR_GRAB_SYNC__PRE                                           0x0
2536 
2537 #define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B                                  0
2538 #define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W                                  3
2539 #define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M                                  0x7
2540 #define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE                                0x0
2541 
2542 #define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B                                   3
2543 #define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W                                   4
2544 #define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M                                   0x78
2545 #define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE                                 0x0
2546 
2547 #define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B                                 7
2548 #define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W                                 1
2549 #define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M                                 0x80
2550 #define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE                               0x0
2551 
2552 #define FEC_OC_OCR_GRAB_RD0__A                                              0x2440055
2553 #define FEC_OC_OCR_GRAB_RD0__W                                              10
2554 #define FEC_OC_OCR_GRAB_RD0__M                                              0x3FF
2555 #define FEC_OC_OCR_GRAB_RD0__PRE                                            0x0
2556 
2557 #define   FEC_OC_OCR_GRAB_RD0_DATA__B                                       0
2558 #define   FEC_OC_OCR_GRAB_RD0_DATA__W                                       10
2559 #define   FEC_OC_OCR_GRAB_RD0_DATA__M                                       0x3FF
2560 #define   FEC_OC_OCR_GRAB_RD0_DATA__PRE                                     0x0
2561 
2562 #define FEC_OC_OCR_GRAB_RD1__A                                              0x2440056
2563 #define FEC_OC_OCR_GRAB_RD1__W                                              10
2564 #define FEC_OC_OCR_GRAB_RD1__M                                              0x3FF
2565 #define FEC_OC_OCR_GRAB_RD1__PRE                                            0x0
2566 
2567 #define   FEC_OC_OCR_GRAB_RD1_DATA__B                                       0
2568 #define   FEC_OC_OCR_GRAB_RD1_DATA__W                                       10
2569 #define   FEC_OC_OCR_GRAB_RD1_DATA__M                                       0x3FF
2570 #define   FEC_OC_OCR_GRAB_RD1_DATA__PRE                                     0x0
2571 
2572 #define FEC_OC_OCR_GRAB_RD2__A                                              0x2440057
2573 #define FEC_OC_OCR_GRAB_RD2__W                                              10
2574 #define FEC_OC_OCR_GRAB_RD2__M                                              0x3FF
2575 #define FEC_OC_OCR_GRAB_RD2__PRE                                            0x0
2576 
2577 #define   FEC_OC_OCR_GRAB_RD2_DATA__B                                       0
2578 #define   FEC_OC_OCR_GRAB_RD2_DATA__W                                       10
2579 #define   FEC_OC_OCR_GRAB_RD2_DATA__M                                       0x3FF
2580 #define   FEC_OC_OCR_GRAB_RD2_DATA__PRE                                     0x0
2581 
2582 #define FEC_OC_OCR_GRAB_RD3__A                                              0x2440058
2583 #define FEC_OC_OCR_GRAB_RD3__W                                              10
2584 #define FEC_OC_OCR_GRAB_RD3__M                                              0x3FF
2585 #define FEC_OC_OCR_GRAB_RD3__PRE                                            0x0
2586 
2587 #define   FEC_OC_OCR_GRAB_RD3_DATA__B                                       0
2588 #define   FEC_OC_OCR_GRAB_RD3_DATA__W                                       10
2589 #define   FEC_OC_OCR_GRAB_RD3_DATA__M                                       0x3FF
2590 #define   FEC_OC_OCR_GRAB_RD3_DATA__PRE                                     0x0
2591 
2592 #define FEC_OC_OCR_GRAB_RD4__A                                              0x2440059
2593 #define FEC_OC_OCR_GRAB_RD4__W                                              10
2594 #define FEC_OC_OCR_GRAB_RD4__M                                              0x3FF
2595 #define FEC_OC_OCR_GRAB_RD4__PRE                                            0x0
2596 
2597 #define   FEC_OC_OCR_GRAB_RD4_DATA__B                                       0
2598 #define   FEC_OC_OCR_GRAB_RD4_DATA__W                                       10
2599 #define   FEC_OC_OCR_GRAB_RD4_DATA__M                                       0x3FF
2600 #define   FEC_OC_OCR_GRAB_RD4_DATA__PRE                                     0x0
2601 
2602 #define FEC_OC_OCR_GRAB_RD5__A                                              0x244005A
2603 #define FEC_OC_OCR_GRAB_RD5__W                                              10
2604 #define FEC_OC_OCR_GRAB_RD5__M                                              0x3FF
2605 #define FEC_OC_OCR_GRAB_RD5__PRE                                            0x0
2606 
2607 #define   FEC_OC_OCR_GRAB_RD5_DATA__B                                       0
2608 #define   FEC_OC_OCR_GRAB_RD5_DATA__W                                       10
2609 #define   FEC_OC_OCR_GRAB_RD5_DATA__M                                       0x3FF
2610 #define   FEC_OC_OCR_GRAB_RD5_DATA__PRE                                     0x0
2611 
2612 #define FEC_DI_RAM__A                                                       0x2450000
2613 
2614 #define FEC_RS_RAM__A                                                       0x2460000
2615 
2616 #define FEC_OC_RAM__A                                                       0x2470000
2617 
2618 #define IQM_COMM_EXEC__A                                                    0x1800000
2619 #define IQM_COMM_EXEC__W                                                    2
2620 #define IQM_COMM_EXEC__M                                                    0x3
2621 #define IQM_COMM_EXEC__PRE                                                  0x0
2622 #define   IQM_COMM_EXEC_STOP                                                0x0
2623 #define   IQM_COMM_EXEC_ACTIVE                                              0x1
2624 #define   IQM_COMM_EXEC_HOLD                                                0x2
2625 
2626 #define IQM_COMM_MB__A                                                      0x1800002
2627 #define IQM_COMM_MB__W                                                      16
2628 #define IQM_COMM_MB__M                                                      0xFFFF
2629 #define IQM_COMM_MB__PRE                                                    0x0
2630 #define IQM_COMM_INT_REQ__A                                                 0x1800003
2631 #define IQM_COMM_INT_REQ__W                                                 2
2632 #define IQM_COMM_INT_REQ__M                                                 0x3
2633 #define IQM_COMM_INT_REQ__PRE                                               0x0
2634 
2635 #define   IQM_COMM_INT_REQ_AF_REQ__B                                        0
2636 #define   IQM_COMM_INT_REQ_AF_REQ__W                                        1
2637 #define   IQM_COMM_INT_REQ_AF_REQ__M                                        0x1
2638 #define   IQM_COMM_INT_REQ_AF_REQ__PRE                                      0x0
2639 
2640 #define   IQM_COMM_INT_REQ_CF_REQ__B                                        1
2641 #define   IQM_COMM_INT_REQ_CF_REQ__W                                        1
2642 #define   IQM_COMM_INT_REQ_CF_REQ__M                                        0x2
2643 #define   IQM_COMM_INT_REQ_CF_REQ__PRE                                      0x0
2644 
2645 #define IQM_COMM_INT_STA__A                                                 0x1800005
2646 #define IQM_COMM_INT_STA__W                                                 16
2647 #define IQM_COMM_INT_STA__M                                                 0xFFFF
2648 #define IQM_COMM_INT_STA__PRE                                               0x0
2649 #define IQM_COMM_INT_MSK__A                                                 0x1800006
2650 #define IQM_COMM_INT_MSK__W                                                 16
2651 #define IQM_COMM_INT_MSK__M                                                 0xFFFF
2652 #define IQM_COMM_INT_MSK__PRE                                               0x0
2653 #define IQM_COMM_INT_STM__A                                                 0x1800007
2654 #define IQM_COMM_INT_STM__W                                                 16
2655 #define IQM_COMM_INT_STM__M                                                 0xFFFF
2656 #define IQM_COMM_INT_STM__PRE                                               0x0
2657 
2658 #define IQM_FS_COMM_EXEC__A                                                 0x1820000
2659 #define IQM_FS_COMM_EXEC__W                                                 2
2660 #define IQM_FS_COMM_EXEC__M                                                 0x3
2661 #define IQM_FS_COMM_EXEC__PRE                                               0x0
2662 #define   IQM_FS_COMM_EXEC_STOP                                             0x0
2663 #define   IQM_FS_COMM_EXEC_ACTIVE                                           0x1
2664 #define   IQM_FS_COMM_EXEC_HOLD                                             0x2
2665 
2666 #define IQM_FS_COMM_MB__A                                                   0x1820002
2667 #define IQM_FS_COMM_MB__W                                                   2
2668 #define IQM_FS_COMM_MB__M                                                   0x3
2669 #define IQM_FS_COMM_MB__PRE                                                 0x0
2670 #define   IQM_FS_COMM_MB_CTL__B                                             0
2671 #define   IQM_FS_COMM_MB_CTL__W                                             1
2672 #define   IQM_FS_COMM_MB_CTL__M                                             0x1
2673 #define   IQM_FS_COMM_MB_CTL__PRE                                           0x0
2674 #define     IQM_FS_COMM_MB_CTL_CTL_OFF                                      0x0
2675 #define     IQM_FS_COMM_MB_CTL_CTL_ON                                       0x1
2676 #define   IQM_FS_COMM_MB_OBS__B                                             1
2677 #define   IQM_FS_COMM_MB_OBS__W                                             1
2678 #define   IQM_FS_COMM_MB_OBS__M                                             0x2
2679 #define   IQM_FS_COMM_MB_OBS__PRE                                           0x0
2680 #define     IQM_FS_COMM_MB_OBS_OBS_OFF                                      0x0
2681 #define     IQM_FS_COMM_MB_OBS_OBS_ON                                       0x2
2682 
2683 #define IQM_FS_RATE_OFS_LO__A                                               0x1820010
2684 #define IQM_FS_RATE_OFS_LO__W                                               16
2685 #define IQM_FS_RATE_OFS_LO__M                                               0xFFFF
2686 #define IQM_FS_RATE_OFS_LO__PRE                                             0x0
2687 #define IQM_FS_RATE_OFS_HI__A                                               0x1820011
2688 #define IQM_FS_RATE_OFS_HI__W                                               12
2689 #define IQM_FS_RATE_OFS_HI__M                                               0xFFF
2690 #define IQM_FS_RATE_OFS_HI__PRE                                             0x0
2691 #define IQM_FS_RATE_LO__A                                                   0x1820012
2692 #define IQM_FS_RATE_LO__W                                                   16
2693 #define IQM_FS_RATE_LO__M                                                   0xFFFF
2694 #define IQM_FS_RATE_LO__PRE                                                 0x0
2695 #define IQM_FS_RATE_HI__A                                                   0x1820013
2696 #define IQM_FS_RATE_HI__W                                                   12
2697 #define IQM_FS_RATE_HI__M                                                   0xFFF
2698 #define IQM_FS_RATE_HI__PRE                                                 0x0
2699 
2700 #define IQM_FS_ADJ_SEL__A                                                   0x1820014
2701 #define IQM_FS_ADJ_SEL__W                                                   2
2702 #define IQM_FS_ADJ_SEL__M                                                   0x3
2703 #define IQM_FS_ADJ_SEL__PRE                                                 0x0
2704 #define   IQM_FS_ADJ_SEL_OFF                                                0x0
2705 #define   IQM_FS_ADJ_SEL_QAM                                                0x1
2706 #define   IQM_FS_ADJ_SEL_VSB                                                0x2
2707 
2708 #define IQM_FD_COMM_EXEC__A                                                 0x1830000
2709 #define IQM_FD_COMM_EXEC__W                                                 2
2710 #define IQM_FD_COMM_EXEC__M                                                 0x3
2711 #define IQM_FD_COMM_EXEC__PRE                                               0x0
2712 #define   IQM_FD_COMM_EXEC_STOP                                             0x0
2713 #define   IQM_FD_COMM_EXEC_ACTIVE                                           0x1
2714 #define   IQM_FD_COMM_EXEC_HOLD                                             0x2
2715 
2716 #define IQM_FD_COMM_MB__A                                                   0x1830002
2717 #define IQM_FD_COMM_MB__W                                                   2
2718 #define IQM_FD_COMM_MB__M                                                   0x3
2719 #define IQM_FD_COMM_MB__PRE                                                 0x0
2720 #define   IQM_FD_COMM_MB_CTL__B                                             0
2721 #define   IQM_FD_COMM_MB_CTL__W                                             1
2722 #define   IQM_FD_COMM_MB_CTL__M                                             0x1
2723 #define   IQM_FD_COMM_MB_CTL__PRE                                           0x0
2724 #define     IQM_FD_COMM_MB_CTL_CTL_OFF                                      0x0
2725 #define     IQM_FD_COMM_MB_CTL_CTL_ON                                       0x1
2726 #define   IQM_FD_COMM_MB_OBS__B                                             1
2727 #define   IQM_FD_COMM_MB_OBS__W                                             1
2728 #define   IQM_FD_COMM_MB_OBS__M                                             0x2
2729 #define   IQM_FD_COMM_MB_OBS__PRE                                           0x0
2730 #define     IQM_FD_COMM_MB_OBS_OBS_OFF                                      0x0
2731 #define     IQM_FD_COMM_MB_OBS_OBS_ON                                       0x2
2732 
2733 #define IQM_RC_COMM_EXEC__A                                                 0x1840000
2734 #define IQM_RC_COMM_EXEC__W                                                 2
2735 #define IQM_RC_COMM_EXEC__M                                                 0x3
2736 #define IQM_RC_COMM_EXEC__PRE                                               0x0
2737 #define   IQM_RC_COMM_EXEC_STOP                                             0x0
2738 #define   IQM_RC_COMM_EXEC_ACTIVE                                           0x1
2739 #define   IQM_RC_COMM_EXEC_HOLD                                             0x2
2740 
2741 #define IQM_RC_COMM_MB__A                                                   0x1840002
2742 #define IQM_RC_COMM_MB__W                                                   2
2743 #define IQM_RC_COMM_MB__M                                                   0x3
2744 #define IQM_RC_COMM_MB__PRE                                                 0x0
2745 #define   IQM_RC_COMM_MB_CTL__B                                             0
2746 #define   IQM_RC_COMM_MB_CTL__W                                             1
2747 #define   IQM_RC_COMM_MB_CTL__M                                             0x1
2748 #define   IQM_RC_COMM_MB_CTL__PRE                                           0x0
2749 #define     IQM_RC_COMM_MB_CTL_CTL_OFF                                      0x0
2750 #define     IQM_RC_COMM_MB_CTL_CTL_ON                                       0x1
2751 #define   IQM_RC_COMM_MB_OBS__B                                             1
2752 #define   IQM_RC_COMM_MB_OBS__W                                             1
2753 #define   IQM_RC_COMM_MB_OBS__M                                             0x2
2754 #define   IQM_RC_COMM_MB_OBS__PRE                                           0x0
2755 #define     IQM_RC_COMM_MB_OBS_OBS_OFF                                      0x0
2756 #define     IQM_RC_COMM_MB_OBS_OBS_ON                                       0x2
2757 
2758 #define IQM_RC_RATE_OFS_LO__A                                               0x1840010
2759 #define IQM_RC_RATE_OFS_LO__W                                               16
2760 #define IQM_RC_RATE_OFS_LO__M                                               0xFFFF
2761 #define IQM_RC_RATE_OFS_LO__PRE                                             0x0
2762 #define IQM_RC_RATE_OFS_HI__A                                               0x1840011
2763 #define IQM_RC_RATE_OFS_HI__W                                               8
2764 #define IQM_RC_RATE_OFS_HI__M                                               0xFF
2765 #define IQM_RC_RATE_OFS_HI__PRE                                             0x0
2766 #define IQM_RC_RATE_LO__A                                                   0x1840012
2767 #define IQM_RC_RATE_LO__W                                                   16
2768 #define IQM_RC_RATE_LO__M                                                   0xFFFF
2769 #define IQM_RC_RATE_LO__PRE                                                 0x0
2770 #define IQM_RC_RATE_HI__A                                                   0x1840013
2771 #define IQM_RC_RATE_HI__W                                                   8
2772 #define IQM_RC_RATE_HI__M                                                   0xFF
2773 #define IQM_RC_RATE_HI__PRE                                                 0x0
2774 
2775 #define IQM_RC_ADJ_SEL__A                                                   0x1840014
2776 #define IQM_RC_ADJ_SEL__W                                                   2
2777 #define IQM_RC_ADJ_SEL__M                                                   0x3
2778 #define IQM_RC_ADJ_SEL__PRE                                                 0x0
2779 #define   IQM_RC_ADJ_SEL_OFF                                                0x0
2780 #define   IQM_RC_ADJ_SEL_QAM                                                0x1
2781 #define   IQM_RC_ADJ_SEL_VSB                                                0x2
2782 
2783 #define IQM_RC_CROUT_ENA__A                                                 0x1840015
2784 #define IQM_RC_CROUT_ENA__W                                                 1
2785 #define IQM_RC_CROUT_ENA__M                                                 0x1
2786 #define IQM_RC_CROUT_ENA__PRE                                               0x0
2787 
2788 #define   IQM_RC_CROUT_ENA_ENA__B                                           0
2789 #define   IQM_RC_CROUT_ENA_ENA__W                                           1
2790 #define   IQM_RC_CROUT_ENA_ENA__M                                           0x1
2791 #define   IQM_RC_CROUT_ENA_ENA__PRE                                         0x0
2792 
2793 #define IQM_RC_STRETCH__A                                                   0x1840016
2794 #define IQM_RC_STRETCH__W                                                   5
2795 #define IQM_RC_STRETCH__M                                                   0x1F
2796 #define IQM_RC_STRETCH__PRE                                                 0x0
2797 #define   IQM_RC_STRETCH_QAM_B_64                                           0x1E
2798 #define   IQM_RC_STRETCH_QAM_B_256                                          0x1C
2799 #define   IQM_RC_STRETCH_ATV                                                0xF
2800 
2801 #define IQM_RT_COMM_EXEC__A                                                 0x1850000
2802 #define IQM_RT_COMM_EXEC__W                                                 2
2803 #define IQM_RT_COMM_EXEC__M                                                 0x3
2804 #define IQM_RT_COMM_EXEC__PRE                                               0x0
2805 #define   IQM_RT_COMM_EXEC_STOP                                             0x0
2806 #define   IQM_RT_COMM_EXEC_ACTIVE                                           0x1
2807 #define   IQM_RT_COMM_EXEC_HOLD                                             0x2
2808 
2809 #define IQM_RT_COMM_MB__A                                                   0x1850002
2810 #define IQM_RT_COMM_MB__W                                                   2
2811 #define IQM_RT_COMM_MB__M                                                   0x3
2812 #define IQM_RT_COMM_MB__PRE                                                 0x0
2813 #define   IQM_RT_COMM_MB_CTL__B                                             0
2814 #define   IQM_RT_COMM_MB_CTL__W                                             1
2815 #define   IQM_RT_COMM_MB_CTL__M                                             0x1
2816 #define   IQM_RT_COMM_MB_CTL__PRE                                           0x0
2817 #define     IQM_RT_COMM_MB_CTL_CTL_OFF                                      0x0
2818 #define     IQM_RT_COMM_MB_CTL_CTL_ON                                       0x1
2819 #define   IQM_RT_COMM_MB_OBS__B                                             1
2820 #define   IQM_RT_COMM_MB_OBS__W                                             1
2821 #define   IQM_RT_COMM_MB_OBS__M                                             0x2
2822 #define   IQM_RT_COMM_MB_OBS__PRE                                           0x0
2823 #define     IQM_RT_COMM_MB_OBS_OBS_OFF                                      0x0
2824 #define     IQM_RT_COMM_MB_OBS_OBS_ON                                       0x2
2825 
2826 #define IQM_RT_ACTIVE__A                                                    0x1850010
2827 #define IQM_RT_ACTIVE__W                                                    2
2828 #define IQM_RT_ACTIVE__M                                                    0x3
2829 #define IQM_RT_ACTIVE__PRE                                                  0x0
2830 
2831 #define   IQM_RT_ACTIVE_ACTIVE_RT__B                                        0
2832 #define   IQM_RT_ACTIVE_ACTIVE_RT__W                                        1
2833 #define   IQM_RT_ACTIVE_ACTIVE_RT__M                                        0x1
2834 #define   IQM_RT_ACTIVE_ACTIVE_RT__PRE                                      0x0
2835 #define     IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF                             0x0
2836 #define     IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON                              0x1
2837 
2838 #define   IQM_RT_ACTIVE_ACTIVE_CR__B                                        1
2839 #define   IQM_RT_ACTIVE_ACTIVE_CR__W                                        1
2840 #define   IQM_RT_ACTIVE_ACTIVE_CR__M                                        0x2
2841 #define   IQM_RT_ACTIVE_ACTIVE_CR__PRE                                      0x0
2842 #define     IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF                              0x0
2843 #define     IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON                               0x2
2844 
2845 #define IQM_RT_LO_INCR__A                                                   0x1850011
2846 #define IQM_RT_LO_INCR__W                                                   12
2847 #define IQM_RT_LO_INCR__M                                                   0xFFF
2848 #define IQM_RT_LO_INCR__PRE                                                 0x588
2849 #define   IQM_RT_LO_INCR_FM                                                 0x0
2850 #define   IQM_RT_LO_INCR_MN                                                 0x588
2851 
2852 #define IQM_RT_ROT_BP__A                                                    0x1850012
2853 #define IQM_RT_ROT_BP__W                                                    2
2854 #define IQM_RT_ROT_BP__M                                                    0x3
2855 #define IQM_RT_ROT_BP__PRE                                                  0x0
2856 
2857 #define   IQM_RT_ROT_BP_ROT_OFF__B                                          0
2858 #define   IQM_RT_ROT_BP_ROT_OFF__W                                          1
2859 #define   IQM_RT_ROT_BP_ROT_OFF__M                                          0x1
2860 #define   IQM_RT_ROT_BP_ROT_OFF__PRE                                        0x0
2861 #define     IQM_RT_ROT_BP_ROT_OFF_ACTIVE                                    0x0
2862 #define     IQM_RT_ROT_BP_ROT_OFF_OFF                                       0x1
2863 
2864 #define   IQM_RT_ROT_BP_ROT_BPF__B                                          1
2865 #define   IQM_RT_ROT_BP_ROT_BPF__W                                          1
2866 #define   IQM_RT_ROT_BP_ROT_BPF__M                                          0x2
2867 #define   IQM_RT_ROT_BP_ROT_BPF__PRE                                        0x0
2868 
2869 #define IQM_RT_LP_BP__A                                                     0x1850013
2870 #define IQM_RT_LP_BP__W                                                     1
2871 #define IQM_RT_LP_BP__M                                                     0x1
2872 #define IQM_RT_LP_BP__PRE                                                   0x0
2873 
2874 #define IQM_RT_DELAY__A                                                     0x1850014
2875 #define IQM_RT_DELAY__W                                                     7
2876 #define IQM_RT_DELAY__M                                                     0x7F
2877 #define IQM_RT_DELAY__PRE                                                   0x45
2878 
2879 #define IQM_CF_COMM_EXEC__A                                                 0x1860000
2880 #define IQM_CF_COMM_EXEC__W                                                 2
2881 #define IQM_CF_COMM_EXEC__M                                                 0x3
2882 #define IQM_CF_COMM_EXEC__PRE                                               0x0
2883 #define   IQM_CF_COMM_EXEC_STOP                                             0x0
2884 #define   IQM_CF_COMM_EXEC_ACTIVE                                           0x1
2885 #define   IQM_CF_COMM_EXEC_HOLD                                             0x2
2886 
2887 #define IQM_CF_COMM_MB__A                                                   0x1860002
2888 #define IQM_CF_COMM_MB__W                                                   2
2889 #define IQM_CF_COMM_MB__M                                                   0x3
2890 #define IQM_CF_COMM_MB__PRE                                                 0x0
2891 #define   IQM_CF_COMM_MB_CTL__B                                             0
2892 #define   IQM_CF_COMM_MB_CTL__W                                             1
2893 #define   IQM_CF_COMM_MB_CTL__M                                             0x1
2894 #define   IQM_CF_COMM_MB_CTL__PRE                                           0x0
2895 #define     IQM_CF_COMM_MB_CTL_CTL_OFF                                      0x0
2896 #define     IQM_CF_COMM_MB_CTL_CTL_ON                                       0x1
2897 #define   IQM_CF_COMM_MB_OBS__B                                             1
2898 #define   IQM_CF_COMM_MB_OBS__W                                             1
2899 #define   IQM_CF_COMM_MB_OBS__M                                             0x2
2900 #define   IQM_CF_COMM_MB_OBS__PRE                                           0x0
2901 #define     IQM_CF_COMM_MB_OBS_OBS_OFF                                      0x0
2902 #define     IQM_CF_COMM_MB_OBS_OBS_ON                                       0x2
2903 
2904 #define IQM_CF_COMM_INT_REQ__A                                              0x1860003
2905 #define IQM_CF_COMM_INT_REQ__W                                              1
2906 #define IQM_CF_COMM_INT_REQ__M                                              0x1
2907 #define IQM_CF_COMM_INT_REQ__PRE                                            0x0
2908 #define IQM_CF_COMM_INT_STA__A                                              0x1860005
2909 #define IQM_CF_COMM_INT_STA__W                                              1
2910 #define IQM_CF_COMM_INT_STA__M                                              0x1
2911 #define IQM_CF_COMM_INT_STA__PRE                                            0x0
2912 #define   IQM_CF_COMM_INT_STA_PM__B                                         0
2913 #define   IQM_CF_COMM_INT_STA_PM__W                                         1
2914 #define   IQM_CF_COMM_INT_STA_PM__M                                         0x1
2915 #define   IQM_CF_COMM_INT_STA_PM__PRE                                       0x0
2916 
2917 #define IQM_CF_COMM_INT_MSK__A                                              0x1860006
2918 #define IQM_CF_COMM_INT_MSK__W                                              1
2919 #define IQM_CF_COMM_INT_MSK__M                                              0x1
2920 #define IQM_CF_COMM_INT_MSK__PRE                                            0x0
2921 #define   IQM_CF_COMM_INT_MSK_PM__B                                         0
2922 #define   IQM_CF_COMM_INT_MSK_PM__W                                         1
2923 #define   IQM_CF_COMM_INT_MSK_PM__M                                         0x1
2924 #define   IQM_CF_COMM_INT_MSK_PM__PRE                                       0x0
2925 
2926 #define IQM_CF_COMM_INT_STM__A                                              0x1860007
2927 #define IQM_CF_COMM_INT_STM__W                                              1
2928 #define IQM_CF_COMM_INT_STM__M                                              0x1
2929 #define IQM_CF_COMM_INT_STM__PRE                                            0x0
2930 #define   IQM_CF_COMM_INT_STM_PM__B                                         0
2931 #define   IQM_CF_COMM_INT_STM_PM__W                                         1
2932 #define   IQM_CF_COMM_INT_STM_PM__M                                         0x1
2933 #define   IQM_CF_COMM_INT_STM_PM__PRE                                       0x0
2934 
2935 #define IQM_CF_SYMMETRIC__A                                                 0x1860010
2936 #define IQM_CF_SYMMETRIC__W                                                 2
2937 #define IQM_CF_SYMMETRIC__M                                                 0x3
2938 #define IQM_CF_SYMMETRIC__PRE                                               0x0
2939 
2940 #define   IQM_CF_SYMMETRIC_RE__B                                            0
2941 #define   IQM_CF_SYMMETRIC_RE__W                                            1
2942 #define   IQM_CF_SYMMETRIC_RE__M                                            0x1
2943 #define   IQM_CF_SYMMETRIC_RE__PRE                                          0x0
2944 
2945 #define   IQM_CF_SYMMETRIC_IM__B                                            1
2946 #define   IQM_CF_SYMMETRIC_IM__W                                            1
2947 #define   IQM_CF_SYMMETRIC_IM__M                                            0x2
2948 #define   IQM_CF_SYMMETRIC_IM__PRE                                          0x0
2949 
2950 #define IQM_CF_MIDTAP__A                                                    0x1860011
2951 #define IQM_CF_MIDTAP__W                                                    2
2952 #define IQM_CF_MIDTAP__M                                                    0x3
2953 #define IQM_CF_MIDTAP__PRE                                                  0x3
2954 
2955 #define   IQM_CF_MIDTAP_RE__B                                               0
2956 #define   IQM_CF_MIDTAP_RE__W                                               1
2957 #define   IQM_CF_MIDTAP_RE__M                                               0x1
2958 #define   IQM_CF_MIDTAP_RE__PRE                                             0x1
2959 
2960 #define   IQM_CF_MIDTAP_IM__B                                               1
2961 #define   IQM_CF_MIDTAP_IM__W                                               1
2962 #define   IQM_CF_MIDTAP_IM__M                                               0x2
2963 #define   IQM_CF_MIDTAP_IM__PRE                                             0x2
2964 
2965 #define IQM_CF_OUT_ENA__A                                                   0x1860012
2966 #define IQM_CF_OUT_ENA__W                                                   3
2967 #define IQM_CF_OUT_ENA__M                                                   0x7
2968 #define IQM_CF_OUT_ENA__PRE                                                 0x0
2969 
2970 #define   IQM_CF_OUT_ENA_ATV__B                                             0
2971 #define   IQM_CF_OUT_ENA_ATV__W                                             1
2972 #define   IQM_CF_OUT_ENA_ATV__M                                             0x1
2973 #define   IQM_CF_OUT_ENA_ATV__PRE                                           0x0
2974 
2975 #define   IQM_CF_OUT_ENA_QAM__B                                             1
2976 #define   IQM_CF_OUT_ENA_QAM__W                                             1
2977 #define   IQM_CF_OUT_ENA_QAM__M                                             0x2
2978 #define   IQM_CF_OUT_ENA_QAM__PRE                                           0x0
2979 
2980 #define   IQM_CF_OUT_ENA_VSB__B                                             2
2981 #define   IQM_CF_OUT_ENA_VSB__W                                             1
2982 #define   IQM_CF_OUT_ENA_VSB__M                                             0x4
2983 #define   IQM_CF_OUT_ENA_VSB__PRE                                           0x0
2984 
2985 #define IQM_CF_ADJ_SEL__A                                                   0x1860013
2986 #define IQM_CF_ADJ_SEL__W                                                   2
2987 #define IQM_CF_ADJ_SEL__M                                                   0x3
2988 #define IQM_CF_ADJ_SEL__PRE                                                 0x0
2989 #define IQM_CF_SCALE__A                                                     0x1860014
2990 #define IQM_CF_SCALE__W                                                     14
2991 #define IQM_CF_SCALE__M                                                     0x3FFF
2992 #define IQM_CF_SCALE__PRE                                                   0x400
2993 
2994 #define IQM_CF_SCALE_SH__A                                                  0x1860015
2995 #define IQM_CF_SCALE_SH__W                                                  2
2996 #define IQM_CF_SCALE_SH__M                                                  0x3
2997 #define IQM_CF_SCALE_SH__PRE                                                0x0
2998 
2999 #define IQM_CF_AMP__A                                                       0x1860016
3000 #define IQM_CF_AMP__W                                                       14
3001 #define IQM_CF_AMP__M                                                       0x3FFF
3002 #define IQM_CF_AMP__PRE                                                     0x0
3003 
3004 #define IQM_CF_POW_MEAS_LEN__A                                              0x1860017
3005 #define IQM_CF_POW_MEAS_LEN__W                                              3
3006 #define IQM_CF_POW_MEAS_LEN__M                                              0x7
3007 #define IQM_CF_POW_MEAS_LEN__PRE                                            0x2
3008 #define   IQM_CF_POW_MEAS_LEN_QAM_B_64                                      0x1
3009 #define   IQM_CF_POW_MEAS_LEN_QAM_B_256                                     0x1
3010 
3011 #define IQM_CF_POW__A                                                       0x1860018
3012 #define IQM_CF_POW__W                                                       16
3013 #define IQM_CF_POW__M                                                       0xFFFF
3014 #define IQM_CF_POW__PRE                                                     0x2
3015 #define IQM_CF_TAP_RE0__A                                                   0x1860020
3016 #define IQM_CF_TAP_RE0__W                                                   7
3017 #define IQM_CF_TAP_RE0__M                                                   0x7F
3018 #define IQM_CF_TAP_RE0__PRE                                                 0x2
3019 #define IQM_CF_TAP_RE1__A                                                   0x1860021
3020 #define IQM_CF_TAP_RE1__W                                                   7
3021 #define IQM_CF_TAP_RE1__M                                                   0x7F
3022 #define IQM_CF_TAP_RE1__PRE                                                 0x2
3023 #define IQM_CF_TAP_RE2__A                                                   0x1860022
3024 #define IQM_CF_TAP_RE2__W                                                   7
3025 #define IQM_CF_TAP_RE2__M                                                   0x7F
3026 #define IQM_CF_TAP_RE2__PRE                                                 0x2
3027 #define IQM_CF_TAP_RE3__A                                                   0x1860023
3028 #define IQM_CF_TAP_RE3__W                                                   7
3029 #define IQM_CF_TAP_RE3__M                                                   0x7F
3030 #define IQM_CF_TAP_RE3__PRE                                                 0x2
3031 #define IQM_CF_TAP_RE4__A                                                   0x1860024
3032 #define IQM_CF_TAP_RE4__W                                                   7
3033 #define IQM_CF_TAP_RE4__M                                                   0x7F
3034 #define IQM_CF_TAP_RE4__PRE                                                 0x2
3035 #define IQM_CF_TAP_RE5__A                                                   0x1860025
3036 #define IQM_CF_TAP_RE5__W                                                   7
3037 #define IQM_CF_TAP_RE5__M                                                   0x7F
3038 #define IQM_CF_TAP_RE5__PRE                                                 0x2
3039 #define IQM_CF_TAP_RE6__A                                                   0x1860026
3040 #define IQM_CF_TAP_RE6__W                                                   7
3041 #define IQM_CF_TAP_RE6__M                                                   0x7F
3042 #define IQM_CF_TAP_RE6__PRE                                                 0x2
3043 #define IQM_CF_TAP_RE7__A                                                   0x1860027
3044 #define IQM_CF_TAP_RE7__W                                                   9
3045 #define IQM_CF_TAP_RE7__M                                                   0x1FF
3046 #define IQM_CF_TAP_RE7__PRE                                                 0x2
3047 #define IQM_CF_TAP_RE8__A                                                   0x1860028
3048 #define IQM_CF_TAP_RE8__W                                                   9
3049 #define IQM_CF_TAP_RE8__M                                                   0x1FF
3050 #define IQM_CF_TAP_RE8__PRE                                                 0x2
3051 #define IQM_CF_TAP_RE9__A                                                   0x1860029
3052 #define IQM_CF_TAP_RE9__W                                                   9
3053 #define IQM_CF_TAP_RE9__M                                                   0x1FF
3054 #define IQM_CF_TAP_RE9__PRE                                                 0x2
3055 #define IQM_CF_TAP_RE10__A                                                  0x186002A
3056 #define IQM_CF_TAP_RE10__W                                                  9
3057 #define IQM_CF_TAP_RE10__M                                                  0x1FF
3058 #define IQM_CF_TAP_RE10__PRE                                                0x2
3059 #define IQM_CF_TAP_RE11__A                                                  0x186002B
3060 #define IQM_CF_TAP_RE11__W                                                  9
3061 #define IQM_CF_TAP_RE11__M                                                  0x1FF
3062 #define IQM_CF_TAP_RE11__PRE                                                0x2
3063 #define IQM_CF_TAP_RE12__A                                                  0x186002C
3064 #define IQM_CF_TAP_RE12__W                                                  9
3065 #define IQM_CF_TAP_RE12__M                                                  0x1FF
3066 #define IQM_CF_TAP_RE12__PRE                                                0x2
3067 #define IQM_CF_TAP_RE13__A                                                  0x186002D
3068 #define IQM_CF_TAP_RE13__W                                                  9
3069 #define IQM_CF_TAP_RE13__M                                                  0x1FF
3070 #define IQM_CF_TAP_RE13__PRE                                                0x2
3071 #define IQM_CF_TAP_RE14__A                                                  0x186002E
3072 #define IQM_CF_TAP_RE14__W                                                  9
3073 #define IQM_CF_TAP_RE14__M                                                  0x1FF
3074 #define IQM_CF_TAP_RE14__PRE                                                0x2
3075 #define IQM_CF_TAP_RE15__A                                                  0x186002F
3076 #define IQM_CF_TAP_RE15__W                                                  9
3077 #define IQM_CF_TAP_RE15__M                                                  0x1FF
3078 #define IQM_CF_TAP_RE15__PRE                                                0x2
3079 #define IQM_CF_TAP_RE16__A                                                  0x1860030
3080 #define IQM_CF_TAP_RE16__W                                                  9
3081 #define IQM_CF_TAP_RE16__M                                                  0x1FF
3082 #define IQM_CF_TAP_RE16__PRE                                                0x2
3083 #define IQM_CF_TAP_RE17__A                                                  0x1860031
3084 #define IQM_CF_TAP_RE17__W                                                  9
3085 #define IQM_CF_TAP_RE17__M                                                  0x1FF
3086 #define IQM_CF_TAP_RE17__PRE                                                0x2
3087 #define IQM_CF_TAP_RE18__A                                                  0x1860032
3088 #define IQM_CF_TAP_RE18__W                                                  9
3089 #define IQM_CF_TAP_RE18__M                                                  0x1FF
3090 #define IQM_CF_TAP_RE18__PRE                                                0x2
3091 #define IQM_CF_TAP_RE19__A                                                  0x1860033
3092 #define IQM_CF_TAP_RE19__W                                                  9
3093 #define IQM_CF_TAP_RE19__M                                                  0x1FF
3094 #define IQM_CF_TAP_RE19__PRE                                                0x2
3095 #define IQM_CF_TAP_RE20__A                                                  0x1860034
3096 #define IQM_CF_TAP_RE20__W                                                  9
3097 #define IQM_CF_TAP_RE20__M                                                  0x1FF
3098 #define IQM_CF_TAP_RE20__PRE                                                0x2
3099 #define IQM_CF_TAP_RE21__A                                                  0x1860035
3100 #define IQM_CF_TAP_RE21__W                                                  11
3101 #define IQM_CF_TAP_RE21__M                                                  0x7FF
3102 #define IQM_CF_TAP_RE21__PRE                                                0x2
3103 #define IQM_CF_TAP_RE22__A                                                  0x1860036
3104 #define IQM_CF_TAP_RE22__W                                                  11
3105 #define IQM_CF_TAP_RE22__M                                                  0x7FF
3106 #define IQM_CF_TAP_RE22__PRE                                                0x2
3107 #define IQM_CF_TAP_RE23__A                                                  0x1860037
3108 #define IQM_CF_TAP_RE23__W                                                  11
3109 #define IQM_CF_TAP_RE23__M                                                  0x7FF
3110 #define IQM_CF_TAP_RE23__PRE                                                0x2
3111 #define IQM_CF_TAP_RE24__A                                                  0x1860038
3112 #define IQM_CF_TAP_RE24__W                                                  11
3113 #define IQM_CF_TAP_RE24__M                                                  0x7FF
3114 #define IQM_CF_TAP_RE24__PRE                                                0x2
3115 #define IQM_CF_TAP_RE25__A                                                  0x1860039
3116 #define IQM_CF_TAP_RE25__W                                                  11
3117 #define IQM_CF_TAP_RE25__M                                                  0x7FF
3118 #define IQM_CF_TAP_RE25__PRE                                                0x2
3119 #define IQM_CF_TAP_RE26__A                                                  0x186003A
3120 #define IQM_CF_TAP_RE26__W                                                  11
3121 #define IQM_CF_TAP_RE26__M                                                  0x7FF
3122 #define IQM_CF_TAP_RE26__PRE                                                0x2
3123 #define IQM_CF_TAP_RE27__A                                                  0x186003B
3124 #define IQM_CF_TAP_RE27__W                                                  11
3125 #define IQM_CF_TAP_RE27__M                                                  0x7FF
3126 #define IQM_CF_TAP_RE27__PRE                                                0x2
3127 #define IQM_CF_TAP_IM0__A                                                   0x1860040
3128 #define IQM_CF_TAP_IM0__W                                                   7
3129 #define IQM_CF_TAP_IM0__M                                                   0x7F
3130 #define IQM_CF_TAP_IM0__PRE                                                 0x2
3131 #define IQM_CF_TAP_IM1__A                                                   0x1860041
3132 #define IQM_CF_TAP_IM1__W                                                   7
3133 #define IQM_CF_TAP_IM1__M                                                   0x7F
3134 #define IQM_CF_TAP_IM1__PRE                                                 0x2
3135 #define IQM_CF_TAP_IM2__A                                                   0x1860042
3136 #define IQM_CF_TAP_IM2__W                                                   7
3137 #define IQM_CF_TAP_IM2__M                                                   0x7F
3138 #define IQM_CF_TAP_IM2__PRE                                                 0x2
3139 #define IQM_CF_TAP_IM3__A                                                   0x1860043
3140 #define IQM_CF_TAP_IM3__W                                                   7
3141 #define IQM_CF_TAP_IM3__M                                                   0x7F
3142 #define IQM_CF_TAP_IM3__PRE                                                 0x2
3143 #define IQM_CF_TAP_IM4__A                                                   0x1860044
3144 #define IQM_CF_TAP_IM4__W                                                   7
3145 #define IQM_CF_TAP_IM4__M                                                   0x7F
3146 #define IQM_CF_TAP_IM4__PRE                                                 0x2
3147 #define IQM_CF_TAP_IM5__A                                                   0x1860045
3148 #define IQM_CF_TAP_IM5__W                                                   7
3149 #define IQM_CF_TAP_IM5__M                                                   0x7F
3150 #define IQM_CF_TAP_IM5__PRE                                                 0x2
3151 #define IQM_CF_TAP_IM6__A                                                   0x1860046
3152 #define IQM_CF_TAP_IM6__W                                                   7
3153 #define IQM_CF_TAP_IM6__M                                                   0x7F
3154 #define IQM_CF_TAP_IM6__PRE                                                 0x2
3155 #define IQM_CF_TAP_IM7__A                                                   0x1860047
3156 #define IQM_CF_TAP_IM7__W                                                   9
3157 #define IQM_CF_TAP_IM7__M                                                   0x1FF
3158 #define IQM_CF_TAP_IM7__PRE                                                 0x2
3159 #define IQM_CF_TAP_IM8__A                                                   0x1860048
3160 #define IQM_CF_TAP_IM8__W                                                   9
3161 #define IQM_CF_TAP_IM8__M                                                   0x1FF
3162 #define IQM_CF_TAP_IM8__PRE                                                 0x2
3163 #define IQM_CF_TAP_IM9__A                                                   0x1860049
3164 #define IQM_CF_TAP_IM9__W                                                   9
3165 #define IQM_CF_TAP_IM9__M                                                   0x1FF
3166 #define IQM_CF_TAP_IM9__PRE                                                 0x2
3167 #define IQM_CF_TAP_IM10__A                                                  0x186004A
3168 #define IQM_CF_TAP_IM10__W                                                  9
3169 #define IQM_CF_TAP_IM10__M                                                  0x1FF
3170 #define IQM_CF_TAP_IM10__PRE                                                0x2
3171 #define IQM_CF_TAP_IM11__A                                                  0x186004B
3172 #define IQM_CF_TAP_IM11__W                                                  9
3173 #define IQM_CF_TAP_IM11__M                                                  0x1FF
3174 #define IQM_CF_TAP_IM11__PRE                                                0x2
3175 #define IQM_CF_TAP_IM12__A                                                  0x186004C
3176 #define IQM_CF_TAP_IM12__W                                                  9
3177 #define IQM_CF_TAP_IM12__M                                                  0x1FF
3178 #define IQM_CF_TAP_IM12__PRE                                                0x2
3179 #define IQM_CF_TAP_IM13__A                                                  0x186004D
3180 #define IQM_CF_TAP_IM13__W                                                  9
3181 #define IQM_CF_TAP_IM13__M                                                  0x1FF
3182 #define IQM_CF_TAP_IM13__PRE                                                0x2
3183 #define IQM_CF_TAP_IM14__A                                                  0x186004E
3184 #define IQM_CF_TAP_IM14__W                                                  9
3185 #define IQM_CF_TAP_IM14__M                                                  0x1FF
3186 #define IQM_CF_TAP_IM14__PRE                                                0x2
3187 #define IQM_CF_TAP_IM15__A                                                  0x186004F
3188 #define IQM_CF_TAP_IM15__W                                                  9
3189 #define IQM_CF_TAP_IM15__M                                                  0x1FF
3190 #define IQM_CF_TAP_IM15__PRE                                                0x2
3191 #define IQM_CF_TAP_IM16__A                                                  0x1860050
3192 #define IQM_CF_TAP_IM16__W                                                  9
3193 #define IQM_CF_TAP_IM16__M                                                  0x1FF
3194 #define IQM_CF_TAP_IM16__PRE                                                0x2
3195 #define IQM_CF_TAP_IM17__A                                                  0x1860051
3196 #define IQM_CF_TAP_IM17__W                                                  9
3197 #define IQM_CF_TAP_IM17__M                                                  0x1FF
3198 #define IQM_CF_TAP_IM17__PRE                                                0x2
3199 #define IQM_CF_TAP_IM18__A                                                  0x1860052
3200 #define IQM_CF_TAP_IM18__W                                                  9
3201 #define IQM_CF_TAP_IM18__M                                                  0x1FF
3202 #define IQM_CF_TAP_IM18__PRE                                                0x2
3203 #define IQM_CF_TAP_IM19__A                                                  0x1860053
3204 #define IQM_CF_TAP_IM19__W                                                  9
3205 #define IQM_CF_TAP_IM19__M                                                  0x1FF
3206 #define IQM_CF_TAP_IM19__PRE                                                0x2
3207 #define IQM_CF_TAP_IM20__A                                                  0x1860054
3208 #define IQM_CF_TAP_IM20__W                                                  9
3209 #define IQM_CF_TAP_IM20__M                                                  0x1FF
3210 #define IQM_CF_TAP_IM20__PRE                                                0x2
3211 #define IQM_CF_TAP_IM21__A                                                  0x1860055
3212 #define IQM_CF_TAP_IM21__W                                                  11
3213 #define IQM_CF_TAP_IM21__M                                                  0x7FF
3214 #define IQM_CF_TAP_IM21__PRE                                                0x2
3215 #define IQM_CF_TAP_IM22__A                                                  0x1860056
3216 #define IQM_CF_TAP_IM22__W                                                  11
3217 #define IQM_CF_TAP_IM22__M                                                  0x7FF
3218 #define IQM_CF_TAP_IM22__PRE                                                0x2
3219 #define IQM_CF_TAP_IM23__A                                                  0x1860057
3220 #define IQM_CF_TAP_IM23__W                                                  11
3221 #define IQM_CF_TAP_IM23__M                                                  0x7FF
3222 #define IQM_CF_TAP_IM23__PRE                                                0x2
3223 #define IQM_CF_TAP_IM24__A                                                  0x1860058
3224 #define IQM_CF_TAP_IM24__W                                                  11
3225 #define IQM_CF_TAP_IM24__M                                                  0x7FF
3226 #define IQM_CF_TAP_IM24__PRE                                                0x2
3227 #define IQM_CF_TAP_IM25__A                                                  0x1860059
3228 #define IQM_CF_TAP_IM25__W                                                  11
3229 #define IQM_CF_TAP_IM25__M                                                  0x7FF
3230 #define IQM_CF_TAP_IM25__PRE                                                0x2
3231 #define IQM_CF_TAP_IM26__A                                                  0x186005A
3232 #define IQM_CF_TAP_IM26__W                                                  11
3233 #define IQM_CF_TAP_IM26__M                                                  0x7FF
3234 #define IQM_CF_TAP_IM26__PRE                                                0x2
3235 #define IQM_CF_TAP_IM27__A                                                  0x186005B
3236 #define IQM_CF_TAP_IM27__W                                                  11
3237 #define IQM_CF_TAP_IM27__M                                                  0x7FF
3238 #define IQM_CF_TAP_IM27__PRE                                                0x2
3239 
3240 #define IQM_AF_COMM_EXEC__A                                                 0x1870000
3241 #define IQM_AF_COMM_EXEC__W                                                 2
3242 #define IQM_AF_COMM_EXEC__M                                                 0x3
3243 #define IQM_AF_COMM_EXEC__PRE                                               0x0
3244 #define   IQM_AF_COMM_EXEC_STOP                                             0x0
3245 #define   IQM_AF_COMM_EXEC_ACTIVE                                           0x1
3246 #define   IQM_AF_COMM_EXEC_HOLD                                             0x2
3247 
3248 #define IQM_AF_COMM_MB__A                                                   0x1870002
3249 #define IQM_AF_COMM_MB__W                                                   8
3250 #define IQM_AF_COMM_MB__M                                                   0xFF
3251 #define IQM_AF_COMM_MB__PRE                                                 0x0
3252 #define   IQM_AF_COMM_MB_CTL__B                                             0
3253 #define   IQM_AF_COMM_MB_CTL__W                                             1
3254 #define   IQM_AF_COMM_MB_CTL__M                                             0x1
3255 #define   IQM_AF_COMM_MB_CTL__PRE                                           0x0
3256 #define     IQM_AF_COMM_MB_CTL_CTL_OFF                                      0x0
3257 #define     IQM_AF_COMM_MB_CTL_CTL_ON                                       0x1
3258 #define   IQM_AF_COMM_MB_OBS__B                                             1
3259 #define   IQM_AF_COMM_MB_OBS__W                                             1
3260 #define   IQM_AF_COMM_MB_OBS__M                                             0x2
3261 #define   IQM_AF_COMM_MB_OBS__PRE                                           0x0
3262 #define     IQM_AF_COMM_MB_OBS_OBS_OFF                                      0x0
3263 #define     IQM_AF_COMM_MB_OBS_OBS_ON                                       0x2
3264 #define   IQM_AF_COMM_MB_MUX_CTRL__B                                        2
3265 #define   IQM_AF_COMM_MB_MUX_CTRL__W                                        3
3266 #define   IQM_AF_COMM_MB_MUX_CTRL__M                                        0x1C
3267 #define   IQM_AF_COMM_MB_MUX_CTRL__PRE                                      0x0
3268 #define     IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT                           0x0
3269 #define     IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT                             0x4
3270 #define     IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT                          0x8
3271 #define     IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT                           0xC
3272 #define     IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT                           0x10
3273 #define   IQM_AF_COMM_MB_MUX_OBS__B                                         5
3274 #define   IQM_AF_COMM_MB_MUX_OBS__W                                         3
3275 #define   IQM_AF_COMM_MB_MUX_OBS__M                                         0xE0
3276 #define   IQM_AF_COMM_MB_MUX_OBS__PRE                                       0x0
3277 #define     IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT                            0x0
3278 #define     IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT                              0x20
3279 #define     IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT                           0x40
3280 #define     IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT                            0x60
3281 #define     IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT                            0x80
3282 
3283 #define IQM_AF_COMM_INT_REQ__A                                              0x1870003
3284 #define IQM_AF_COMM_INT_REQ__W                                              1
3285 #define IQM_AF_COMM_INT_REQ__M                                              0x1
3286 #define IQM_AF_COMM_INT_REQ__PRE                                            0x0
3287 #define IQM_AF_COMM_INT_STA__A                                              0x1870005
3288 #define IQM_AF_COMM_INT_STA__W                                              2
3289 #define IQM_AF_COMM_INT_STA__M                                              0x3
3290 #define IQM_AF_COMM_INT_STA__PRE                                            0x0
3291 #define   IQM_AF_COMM_INT_STA_CLP_INT_STA__B                                0
3292 #define   IQM_AF_COMM_INT_STA_CLP_INT_STA__W                                1
3293 #define   IQM_AF_COMM_INT_STA_CLP_INT_STA__M                                0x1
3294 #define   IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE                              0x0
3295 #define   IQM_AF_COMM_INT_STA_SNS_INT_STA__B                                1
3296 #define   IQM_AF_COMM_INT_STA_SNS_INT_STA__W                                1
3297 #define   IQM_AF_COMM_INT_STA_SNS_INT_STA__M                                0x2
3298 #define   IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE                              0x0
3299 
3300 #define IQM_AF_COMM_INT_MSK__A                                              0x1870006
3301 #define IQM_AF_COMM_INT_MSK__W                                              2
3302 #define IQM_AF_COMM_INT_MSK__M                                              0x3
3303 #define IQM_AF_COMM_INT_MSK__PRE                                            0x0
3304 #define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B                                0
3305 #define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W                                1
3306 #define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M                                0x1
3307 #define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE                              0x0
3308 #define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B                                1
3309 #define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W                                1
3310 #define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M                                0x2
3311 #define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE                              0x0
3312 
3313 #define IQM_AF_COMM_INT_STM__A                                              0x1870007
3314 #define IQM_AF_COMM_INT_STM__W                                              2
3315 #define IQM_AF_COMM_INT_STM__M                                              0x3
3316 #define IQM_AF_COMM_INT_STM__PRE                                            0x0
3317 #define   IQM_AF_COMM_INT_STM_CLP_INT_STA__B                                0
3318 #define   IQM_AF_COMM_INT_STM_CLP_INT_STA__W                                1
3319 #define   IQM_AF_COMM_INT_STM_CLP_INT_STA__M                                0x1
3320 #define   IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE                              0x0
3321 #define   IQM_AF_COMM_INT_STM_SNS_INT_STA__B                                1
3322 #define   IQM_AF_COMM_INT_STM_SNS_INT_STA__W                                1
3323 #define   IQM_AF_COMM_INT_STM_SNS_INT_STA__M                                0x2
3324 #define   IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE                              0x0
3325 
3326 #define IQM_AF_FDB_SEL__A                                                   0x1870010
3327 #define IQM_AF_FDB_SEL__W                                                   1
3328 #define IQM_AF_FDB_SEL__M                                                   0x1
3329 #define IQM_AF_FDB_SEL__PRE                                                 0x0
3330 
3331 #define IQM_AF_INVEXT__A                                                    0x1870011
3332 #define IQM_AF_INVEXT__W                                                    1
3333 #define IQM_AF_INVEXT__M                                                    0x1
3334 #define IQM_AF_INVEXT__PRE                                                  0x0
3335 #define IQM_AF_CLKNEG__A                                                    0x1870012
3336 #define IQM_AF_CLKNEG__W                                                    2
3337 #define IQM_AF_CLKNEG__M                                                    0x3
3338 #define IQM_AF_CLKNEG__PRE                                                  0x0
3339 
3340 #define   IQM_AF_CLKNEG_CLKNEGPEAK__B                                       0
3341 #define   IQM_AF_CLKNEG_CLKNEGPEAK__W                                       1
3342 #define   IQM_AF_CLKNEG_CLKNEGPEAK__M                                       0x1
3343 #define   IQM_AF_CLKNEG_CLKNEGPEAK__PRE                                     0x0
3344 #define     IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS                       0x0
3345 #define     IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG                       0x1
3346 
3347 #define   IQM_AF_CLKNEG_CLKNEGDATA__B                                       1
3348 #define   IQM_AF_CLKNEG_CLKNEGDATA__W                                       1
3349 #define   IQM_AF_CLKNEG_CLKNEGDATA__M                                       0x2
3350 #define   IQM_AF_CLKNEG_CLKNEGDATA__PRE                                     0x0
3351 #define     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS                       0x0
3352 #define     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG                       0x2
3353 
3354 #define IQM_AF_MON_IN_MUX__A                                                0x1870013
3355 #define IQM_AF_MON_IN_MUX__W                                                2
3356 #define IQM_AF_MON_IN_MUX__M                                                0x3
3357 #define IQM_AF_MON_IN_MUX__PRE                                              0x0
3358 
3359 #define IQM_AF_MON_IN5__A                                                   0x1870014
3360 #define IQM_AF_MON_IN5__W                                                   10
3361 #define IQM_AF_MON_IN5__M                                                   0x3FF
3362 #define IQM_AF_MON_IN5__PRE                                                 0x0
3363 
3364 #define IQM_AF_MON_IN4__A                                                   0x1870015
3365 #define IQM_AF_MON_IN4__W                                                   10
3366 #define IQM_AF_MON_IN4__M                                                   0x3FF
3367 #define IQM_AF_MON_IN4__PRE                                                 0x0
3368 
3369 #define IQM_AF_MON_IN3__A                                                   0x1870016
3370 #define IQM_AF_MON_IN3__W                                                   10
3371 #define IQM_AF_MON_IN3__M                                                   0x3FF
3372 #define IQM_AF_MON_IN3__PRE                                                 0x0
3373 
3374 #define IQM_AF_MON_IN2__A                                                   0x1870017
3375 #define IQM_AF_MON_IN2__W                                                   10
3376 #define IQM_AF_MON_IN2__M                                                   0x3FF
3377 #define IQM_AF_MON_IN2__PRE                                                 0x0
3378 
3379 #define IQM_AF_MON_IN1__A                                                   0x1870018
3380 #define IQM_AF_MON_IN1__W                                                   10
3381 #define IQM_AF_MON_IN1__M                                                   0x3FF
3382 #define IQM_AF_MON_IN1__PRE                                                 0x0
3383 
3384 #define IQM_AF_MON_IN0__A                                                   0x1870019
3385 #define IQM_AF_MON_IN0__W                                                   10
3386 #define IQM_AF_MON_IN0__M                                                   0x3FF
3387 #define IQM_AF_MON_IN0__PRE                                                 0x0
3388 
3389 #define IQM_AF_MON_IN_VAL__A                                                0x187001A
3390 #define IQM_AF_MON_IN_VAL__W                                                1
3391 #define IQM_AF_MON_IN_VAL__M                                                0x1
3392 #define IQM_AF_MON_IN_VAL__PRE                                              0x0
3393 
3394 #define IQM_AF_START_LOCK__A                                                0x187001B
3395 #define IQM_AF_START_LOCK__W                                                1
3396 #define IQM_AF_START_LOCK__M                                                0x1
3397 #define IQM_AF_START_LOCK__PRE                                              0x0
3398 
3399 #define IQM_AF_PHASE0__A                                                    0x187001C
3400 #define IQM_AF_PHASE0__W                                                    7
3401 #define IQM_AF_PHASE0__M                                                    0x7F
3402 #define IQM_AF_PHASE0__PRE                                                  0x0
3403 
3404 #define IQM_AF_PHASE1__A                                                    0x187001D
3405 #define IQM_AF_PHASE1__W                                                    7
3406 #define IQM_AF_PHASE1__M                                                    0x7F
3407 #define IQM_AF_PHASE1__PRE                                                  0x0
3408 
3409 #define IQM_AF_PHASE2__A                                                    0x187001E
3410 #define IQM_AF_PHASE2__W                                                    7
3411 #define IQM_AF_PHASE2__M                                                    0x7F
3412 #define IQM_AF_PHASE2__PRE                                                  0x0
3413 
3414 #define IQM_AF_SCU_PHASE__A                                                 0x187001F
3415 #define IQM_AF_SCU_PHASE__W                                                 2
3416 #define IQM_AF_SCU_PHASE__M                                                 0x3
3417 #define IQM_AF_SCU_PHASE__PRE                                               0x0
3418 
3419 #define IQM_AF_SYNC_SEL__A                                                  0x1870020
3420 #define IQM_AF_SYNC_SEL__W                                                  2
3421 #define IQM_AF_SYNC_SEL__M                                                  0x3
3422 #define IQM_AF_SYNC_SEL__PRE                                                0x0
3423 #define IQM_AF_ADC_CONF__A                                                  0x1870021
3424 #define IQM_AF_ADC_CONF__W                                                  4
3425 #define IQM_AF_ADC_CONF__M                                                  0xF
3426 #define IQM_AF_ADC_CONF__PRE                                                0x0
3427 
3428 #define   IQM_AF_ADC_CONF_ADC_SIGN__B                                       0
3429 #define   IQM_AF_ADC_CONF_ADC_SIGN__W                                       1
3430 #define   IQM_AF_ADC_CONF_ADC_SIGN__M                                       0x1
3431 #define   IQM_AF_ADC_CONF_ADC_SIGN__PRE                                     0x0
3432 #define     IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED                             0x0
3433 #define     IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED                           0x1
3434 
3435 #define   IQM_AF_ADC_CONF_BITREVERSE_ADC__B                                 1
3436 #define   IQM_AF_ADC_CONF_BITREVERSE_ADC__W                                 1
3437 #define   IQM_AF_ADC_CONF_BITREVERSE_ADC__M                                 0x2
3438 #define   IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE                               0x0
3439 #define     IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL                       0x0
3440 #define     IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED                  0x2
3441 
3442 #define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__B                                2
3443 #define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__W                                1
3444 #define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__M                                0x4
3445 #define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE                              0x0
3446 #define     IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL                0x0
3447 #define     IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED           0x4
3448 
3449 #define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__B                                3
3450 #define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__W                                1
3451 #define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__M                                0x8
3452 #define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE                              0x0
3453 #define     IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL                0x0
3454 #define     IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED           0x8
3455 
3456 #define IQM_AF_CLP_CLIP__A                                                  0x1870022
3457 #define IQM_AF_CLP_CLIP__W                                                  16
3458 #define IQM_AF_CLP_CLIP__M                                                  0xFFFF
3459 #define IQM_AF_CLP_CLIP__PRE                                                0x0
3460 
3461 #define IQM_AF_CLP_LEN__A                                                   0x1870023
3462 #define IQM_AF_CLP_LEN__W                                                   16
3463 #define IQM_AF_CLP_LEN__M                                                   0xFFFF
3464 #define IQM_AF_CLP_LEN__PRE                                                 0x0
3465 #define   IQM_AF_CLP_LEN_QAM_B_64                                           0x400
3466 #define   IQM_AF_CLP_LEN_QAM_B_256                                          0x400
3467 #define   IQM_AF_CLP_LEN_ATV                                                0x0
3468 
3469 #define IQM_AF_CLP_TH__A                                                    0x1870024
3470 #define IQM_AF_CLP_TH__W                                                    9
3471 #define IQM_AF_CLP_TH__M                                                    0x1FF
3472 #define IQM_AF_CLP_TH__PRE                                                  0x0
3473 #define   IQM_AF_CLP_TH_QAM_B_64                                            0x80
3474 #define   IQM_AF_CLP_TH_QAM_B_256                                           0x80
3475 #define   IQM_AF_CLP_TH_ATV                                                 0x1C0
3476 
3477 #define IQM_AF_DCF_BYPASS__A                                                0x1870025
3478 #define IQM_AF_DCF_BYPASS__W                                                1
3479 #define IQM_AF_DCF_BYPASS__M                                                0x1
3480 #define IQM_AF_DCF_BYPASS__PRE                                              0x0
3481 #define   IQM_AF_DCF_BYPASS_ACTIVE                                          0x0
3482 #define   IQM_AF_DCF_BYPASS_BYPASS                                          0x1
3483 
3484 #define IQM_AF_SNS_LEN__A                                                   0x1870026
3485 #define IQM_AF_SNS_LEN__W                                                   16
3486 #define IQM_AF_SNS_LEN__M                                                   0xFFFF
3487 #define IQM_AF_SNS_LEN__PRE                                                 0x0
3488 #define   IQM_AF_SNS_LEN_QAM_B_64                                           0x400
3489 #define   IQM_AF_SNS_LEN_QAM_B_256                                          0x400
3490 #define   IQM_AF_SNS_LEN_ATV                                                0x0
3491 
3492 #define IQM_AF_SNS_SENSE__A                                                 0x1870027
3493 #define IQM_AF_SNS_SENSE__W                                                 16
3494 #define IQM_AF_SNS_SENSE__M                                                 0xFFFF
3495 #define IQM_AF_SNS_SENSE__PRE                                               0x0
3496 
3497 #define IQM_AF_AGC_IF__A                                                    0x1870028
3498 #define IQM_AF_AGC_IF__W                                                    15
3499 #define IQM_AF_AGC_IF__M                                                    0x7FFF
3500 #define IQM_AF_AGC_IF__PRE                                                  0x0
3501 
3502 #define IQM_AF_AGC_RF__A                                                    0x1870029
3503 #define IQM_AF_AGC_RF__W                                                    15
3504 #define IQM_AF_AGC_RF__M                                                    0x7FFF
3505 #define IQM_AF_AGC_RF__PRE                                                  0x0
3506 
3507 #define IQM_AF_PGA_GAIN__A                                                  0x187002A
3508 #define IQM_AF_PGA_GAIN__W                                                  4
3509 #define IQM_AF_PGA_GAIN__M                                                  0xF
3510 #define IQM_AF_PGA_GAIN__PRE                                                0x0
3511 
3512 #define IQM_AF_PDREF__A                                                     0x187002B
3513 #define IQM_AF_PDREF__W                                                     5
3514 #define IQM_AF_PDREF__M                                                     0x1F
3515 #define IQM_AF_PDREF__PRE                                                   0x0
3516 #define   IQM_AF_PDREF_QAM_B_64                                             0xF
3517 #define   IQM_AF_PDREF_QAM_B_256                                            0xF
3518 #define   IQM_AF_PDREF_ATV                                                  0xF
3519 
3520 #define IQM_AF_STDBY__A                                                     0x187002C
3521 #define IQM_AF_STDBY__W                                                     6
3522 #define IQM_AF_STDBY__M                                                     0x3F
3523 #define IQM_AF_STDBY__PRE                                                   0x0
3524 
3525 #define   IQM_AF_STDBY_STDBY_BIAS__B                                        0
3526 #define   IQM_AF_STDBY_STDBY_BIAS__W                                        1
3527 #define   IQM_AF_STDBY_STDBY_BIAS__M                                        0x1
3528 #define   IQM_AF_STDBY_STDBY_BIAS__PRE                                      0x0
3529 #define     IQM_AF_STDBY_STDBY_BIAS_ACTIVE                                  0x0
3530 #define     IQM_AF_STDBY_STDBY_BIAS_STANDBY                                 0x1
3531 
3532 #define   IQM_AF_STDBY_STDBY_ADC__B                                         1
3533 #define   IQM_AF_STDBY_STDBY_ADC__W                                         1
3534 #define   IQM_AF_STDBY_STDBY_ADC__M                                         0x2
3535 #define   IQM_AF_STDBY_STDBY_ADC__PRE                                       0x0
3536 #define     IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE                                0x0
3537 #define     IQM_AF_STDBY_STDBY_ADC_A1_STANDBY                               0x2
3538 #define     IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE                                0x2
3539 #define     IQM_AF_STDBY_STDBY_ADC_A2_STANDBY                               0x0
3540 
3541 #define   IQM_AF_STDBY_STDBY_AMP__B                                         2
3542 #define   IQM_AF_STDBY_STDBY_AMP__W                                         1
3543 #define   IQM_AF_STDBY_STDBY_AMP__M                                         0x4
3544 #define   IQM_AF_STDBY_STDBY_AMP__PRE                                       0x0
3545 #define     IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE                                0x0
3546 #define     IQM_AF_STDBY_STDBY_AMP_A1_STANDBY                               0x4
3547 #define     IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE                                0x4
3548 #define     IQM_AF_STDBY_STDBY_AMP_A2_STANDBY                               0x0
3549 
3550 #define   IQM_AF_STDBY_STDBY_PD__B                                          3
3551 #define   IQM_AF_STDBY_STDBY_PD__W                                          1
3552 #define   IQM_AF_STDBY_STDBY_PD__M                                          0x8
3553 #define   IQM_AF_STDBY_STDBY_PD__PRE                                        0x0
3554 #define     IQM_AF_STDBY_STDBY_PD_A1_ACTIVE                                 0x0
3555 #define     IQM_AF_STDBY_STDBY_PD_A1_STANDBY                                0x8
3556 #define     IQM_AF_STDBY_STDBY_PD_A2_ACTIVE                                 0x8
3557 #define     IQM_AF_STDBY_STDBY_PD_A2_STANDBY                                0x0
3558 
3559 #define   IQM_AF_STDBY_STDBY_TAGC_IF__B                                     4
3560 #define   IQM_AF_STDBY_STDBY_TAGC_IF__W                                     1
3561 #define   IQM_AF_STDBY_STDBY_TAGC_IF__M                                     0x10
3562 #define   IQM_AF_STDBY_STDBY_TAGC_IF__PRE                                   0x0
3563 #define     IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE                            0x0
3564 #define     IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY                           0x10
3565 #define     IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE                            0x10
3566 #define     IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY                           0x0
3567 
3568 #define   IQM_AF_STDBY_STDBY_TAGC_RF__B                                     5
3569 #define   IQM_AF_STDBY_STDBY_TAGC_RF__W                                     1
3570 #define   IQM_AF_STDBY_STDBY_TAGC_RF__M                                     0x20
3571 #define   IQM_AF_STDBY_STDBY_TAGC_RF__PRE                                   0x0
3572 #define     IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE                            0x0
3573 #define     IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY                           0x20
3574 #define     IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE                            0x20
3575 #define     IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY                           0x0
3576 
3577 #define IQM_AF_AMUX__A                                                      0x187002D
3578 #define IQM_AF_AMUX__W                                                      2
3579 #define IQM_AF_AMUX__M                                                      0x3
3580 #define IQM_AF_AMUX__PRE                                                    0x0
3581 
3582 #define IQM_AF_TST_AFEMAIN__A                                               0x187002E
3583 #define IQM_AF_TST_AFEMAIN__W                                               8
3584 #define IQM_AF_TST_AFEMAIN__M                                               0xFF
3585 #define IQM_AF_TST_AFEMAIN__PRE                                             0x0
3586 
3587 #define IQM_RT_RAM__A                                                       0x1880000
3588 
3589 #define   IQM_RT_RAM_DLY__B                                                 0
3590 #define   IQM_RT_RAM_DLY__W                                                 13
3591 #define   IQM_RT_RAM_DLY__M                                                 0x1FFF
3592 #define   IQM_RT_RAM_DLY__PRE                                               0x0
3593 
3594 #define ORX_COMM_EXEC__A                                                    0x2000000
3595 #define ORX_COMM_EXEC__W                                                    2
3596 #define ORX_COMM_EXEC__M                                                    0x3
3597 #define ORX_COMM_EXEC__PRE                                                  0x0
3598 #define   ORX_COMM_EXEC_STOP                                                0x0
3599 #define   ORX_COMM_EXEC_ACTIVE                                              0x1
3600 #define   ORX_COMM_EXEC_HOLD                                                0x2
3601 
3602 #define ORX_COMM_STATE__A                                                   0x2000001
3603 #define ORX_COMM_STATE__W                                                   16
3604 #define ORX_COMM_STATE__M                                                   0xFFFF
3605 #define ORX_COMM_STATE__PRE                                                 0x0
3606 #define ORX_COMM_MB__A                                                      0x2000002
3607 #define ORX_COMM_MB__W                                                      16
3608 #define ORX_COMM_MB__M                                                      0xFFFF
3609 #define ORX_COMM_MB__PRE                                                    0x0
3610 #define ORX_COMM_INT_REQ__A                                                 0x2000003
3611 #define ORX_COMM_INT_REQ__W                                                 16
3612 #define ORX_COMM_INT_REQ__M                                                 0xFFFF
3613 #define ORX_COMM_INT_REQ__PRE                                               0x0
3614 #define   ORX_COMM_INT_REQ_EQU_REQ__B                                       0
3615 #define   ORX_COMM_INT_REQ_EQU_REQ__W                                       1
3616 #define   ORX_COMM_INT_REQ_EQU_REQ__M                                       0x1
3617 #define   ORX_COMM_INT_REQ_EQU_REQ__PRE                                     0x0
3618 #define   ORX_COMM_INT_REQ_DDC_REQ__B                                       1
3619 #define   ORX_COMM_INT_REQ_DDC_REQ__W                                       1
3620 #define   ORX_COMM_INT_REQ_DDC_REQ__M                                       0x2
3621 #define   ORX_COMM_INT_REQ_DDC_REQ__PRE                                     0x0
3622 #define   ORX_COMM_INT_REQ_FWP_REQ__B                                       2
3623 #define   ORX_COMM_INT_REQ_FWP_REQ__W                                       1
3624 #define   ORX_COMM_INT_REQ_FWP_REQ__M                                       0x4
3625 #define   ORX_COMM_INT_REQ_FWP_REQ__PRE                                     0x0
3626 #define   ORX_COMM_INT_REQ_CON_REQ__B                                       3
3627 #define   ORX_COMM_INT_REQ_CON_REQ__W                                       1
3628 #define   ORX_COMM_INT_REQ_CON_REQ__M                                       0x8
3629 #define   ORX_COMM_INT_REQ_CON_REQ__PRE                                     0x0
3630 #define   ORX_COMM_INT_REQ_NSU_REQ__B                                       4
3631 #define   ORX_COMM_INT_REQ_NSU_REQ__W                                       1
3632 #define   ORX_COMM_INT_REQ_NSU_REQ__M                                       0x10
3633 #define   ORX_COMM_INT_REQ_NSU_REQ__PRE                                     0x0
3634 
3635 #define ORX_COMM_INT_STA__A                                                 0x2000005
3636 #define ORX_COMM_INT_STA__W                                                 16
3637 #define ORX_COMM_INT_STA__M                                                 0xFFFF
3638 #define ORX_COMM_INT_STA__PRE                                               0x0
3639 #define ORX_COMM_INT_MSK__A                                                 0x2000006
3640 #define ORX_COMM_INT_MSK__W                                                 16
3641 #define ORX_COMM_INT_MSK__M                                                 0xFFFF
3642 #define ORX_COMM_INT_MSK__PRE                                               0x0
3643 #define ORX_COMM_INT_STM__A                                                 0x2000007
3644 #define ORX_COMM_INT_STM__W                                                 16
3645 #define ORX_COMM_INT_STM__M                                                 0xFFFF
3646 #define ORX_COMM_INT_STM__PRE                                               0x0
3647 
3648 #define ORX_TOP_COMM_EXEC__A                                                0x2010000
3649 #define ORX_TOP_COMM_EXEC__W                                                2
3650 #define ORX_TOP_COMM_EXEC__M                                                0x3
3651 #define ORX_TOP_COMM_EXEC__PRE                                              0x0
3652 #define   ORX_TOP_COMM_EXEC_STOP                                            0x0
3653 #define   ORX_TOP_COMM_EXEC_ACTIVE                                          0x1
3654 #define   ORX_TOP_COMM_EXEC_HOLD                                            0x2
3655 
3656 #define ORX_TOP_COMM_KEY__A                                                 0x201000F
3657 #define ORX_TOP_COMM_KEY__W                                                 16
3658 #define ORX_TOP_COMM_KEY__M                                                 0xFFFF
3659 #define ORX_TOP_COMM_KEY__PRE                                               0x0
3660 #define   ORX_TOP_COMM_KEY_KEY                                              0xFABA
3661 
3662 #define ORX_TOP_MDE_W__A                                                    0x2010010
3663 #define ORX_TOP_MDE_W__W                                                    2
3664 #define ORX_TOP_MDE_W__M                                                    0x3
3665 #define ORX_TOP_MDE_W__PRE                                                  0x2
3666 #define   ORX_TOP_MDE_W_RATE_1544KBPS                                       0x0
3667 #define   ORX_TOP_MDE_W_RATE_3088KBPS                                       0x1
3668 #define   ORX_TOP_MDE_W_RATE_2048KBPS_SQRT                                  0x2
3669 #define   ORX_TOP_MDE_W_RATE_2048KBPS_RO                                    0x3
3670 
3671 #define ORX_TOP_AIF_CTRL_W__A                                               0x2010011
3672 #define ORX_TOP_AIF_CTRL_W__W                                               3
3673 #define ORX_TOP_AIF_CTRL_W__M                                               0x7
3674 #define ORX_TOP_AIF_CTRL_W__PRE                                             0x0
3675 #define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B                                0
3676 #define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W                                1
3677 #define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M                                0x1
3678 #define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE                              0x0
3679 #define     ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE       0x0
3680 #define     ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE       0x1
3681 #define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B                                 1
3682 #define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W                                 1
3683 #define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M                                 0x2
3684 #define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE                               0x0
3685 #define     ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC            0x0
3686 #define     ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC           0x2
3687 #define   ORX_TOP_AIF_CTRL_W_INV_MSB__B                                     2
3688 #define   ORX_TOP_AIF_CTRL_W_INV_MSB__W                                     1
3689 #define   ORX_TOP_AIF_CTRL_W_INV_MSB__M                                     0x4
3690 #define   ORX_TOP_AIF_CTRL_W_INV_MSB__PRE                                   0x0
3691 #define     ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC                 0x0
3692 #define     ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC                    0x4
3693 
3694 #define ORX_FWP_COMM_EXEC__A                                                0x2020000
3695 #define ORX_FWP_COMM_EXEC__W                                                2
3696 #define ORX_FWP_COMM_EXEC__M                                                0x3
3697 #define ORX_FWP_COMM_EXEC__PRE                                              0x0
3698 #define   ORX_FWP_COMM_EXEC_STOP                                            0x0
3699 #define   ORX_FWP_COMM_EXEC_ACTIVE                                          0x1
3700 #define   ORX_FWP_COMM_EXEC_HOLD                                            0x2
3701 
3702 #define ORX_FWP_COMM_MB__A                                                  0x2020002
3703 #define ORX_FWP_COMM_MB__W                                                  8
3704 #define ORX_FWP_COMM_MB__M                                                  0xFF
3705 #define ORX_FWP_COMM_MB__PRE                                                0x0
3706 #define   ORX_FWP_COMM_MB_CTL__B                                            0
3707 #define   ORX_FWP_COMM_MB_CTL__W                                            1
3708 #define   ORX_FWP_COMM_MB_CTL__M                                            0x1
3709 #define   ORX_FWP_COMM_MB_CTL__PRE                                          0x0
3710 #define     ORX_FWP_COMM_MB_CTL_OFF                                         0x0
3711 #define     ORX_FWP_COMM_MB_CTL_ON                                          0x1
3712 #define   ORX_FWP_COMM_MB_OBS__B                                            1
3713 #define   ORX_FWP_COMM_MB_OBS__W                                            1
3714 #define   ORX_FWP_COMM_MB_OBS__M                                            0x2
3715 #define   ORX_FWP_COMM_MB_OBS__PRE                                          0x0
3716 #define     ORX_FWP_COMM_MB_OBS_OFF                                         0x0
3717 #define     ORX_FWP_COMM_MB_OBS_ON                                          0x2
3718 
3719 #define   ORX_FWP_COMM_MB_CTL_MUX__B                                        2
3720 #define   ORX_FWP_COMM_MB_CTL_MUX__W                                        3
3721 #define   ORX_FWP_COMM_MB_CTL_MUX__M                                        0x1C
3722 #define   ORX_FWP_COMM_MB_CTL_MUX__PRE                                      0x0
3723 
3724 #define   ORX_FWP_COMM_MB_OBS_MUX__B                                        5
3725 #define   ORX_FWP_COMM_MB_OBS_MUX__W                                        3
3726 #define   ORX_FWP_COMM_MB_OBS_MUX__M                                        0xE0
3727 #define   ORX_FWP_COMM_MB_OBS_MUX__PRE                                      0x0
3728 
3729 #define ORX_FWP_AAG_LEN_W__A                                                0x2020010
3730 #define ORX_FWP_AAG_LEN_W__W                                                16
3731 #define ORX_FWP_AAG_LEN_W__M                                                0xFFFF
3732 #define ORX_FWP_AAG_LEN_W__PRE                                              0x800
3733 
3734 #define ORX_FWP_AAG_THR_W__A                                                0x2020011
3735 #define ORX_FWP_AAG_THR_W__W                                                8
3736 #define ORX_FWP_AAG_THR_W__M                                                0xFF
3737 #define ORX_FWP_AAG_THR_W__PRE                                              0x50
3738 
3739 #define ORX_FWP_AAG_THR_CNT_R__A                                            0x2020012
3740 #define ORX_FWP_AAG_THR_CNT_R__W                                            16
3741 #define ORX_FWP_AAG_THR_CNT_R__M                                            0xFFFF
3742 #define ORX_FWP_AAG_THR_CNT_R__PRE                                          0x0
3743 
3744 #define ORX_FWP_AAG_SNS_CNT_R__A                                            0x2020013
3745 #define ORX_FWP_AAG_SNS_CNT_R__W                                            16
3746 #define ORX_FWP_AAG_SNS_CNT_R__M                                            0xFFFF
3747 #define ORX_FWP_AAG_SNS_CNT_R__PRE                                          0x0
3748 
3749 #define ORX_FWP_PFI_A_W__A                                                  0x2020014
3750 #define ORX_FWP_PFI_A_W__W                                                  8
3751 #define ORX_FWP_PFI_A_W__M                                                  0xFF
3752 #define ORX_FWP_PFI_A_W__PRE                                                0xB0
3753 #define   ORX_FWP_PFI_A_W_RATE_2048KBPS                                     0xB0
3754 #define   ORX_FWP_PFI_A_W_RATE_1544KBPS                                     0xA4
3755 #define   ORX_FWP_PFI_A_W_RATE_3088KBPS                                     0xC0
3756 
3757 #define ORX_FWP_PFI_B_W__A                                                  0x2020015
3758 #define ORX_FWP_PFI_B_W__W                                                  8
3759 #define ORX_FWP_PFI_B_W__M                                                  0xFF
3760 #define ORX_FWP_PFI_B_W__PRE                                                0x9E
3761 #define   ORX_FWP_PFI_B_W_RATE_2048KBPS                                     0x9E
3762 #define   ORX_FWP_PFI_B_W_RATE_1544KBPS                                     0x94
3763 #define   ORX_FWP_PFI_B_W_RATE_3088KBPS                                     0xB0
3764 
3765 #define ORX_FWP_PFI_C_W__A                                                  0x2020016
3766 #define ORX_FWP_PFI_C_W__W                                                  8
3767 #define ORX_FWP_PFI_C_W__M                                                  0xFF
3768 #define ORX_FWP_PFI_C_W__PRE                                                0x5C
3769 #define   ORX_FWP_PFI_C_W_RATE_2048KBPS                                     0x5C
3770 #define   ORX_FWP_PFI_C_W_RATE_1544KBPS                                     0x64
3771 #define   ORX_FWP_PFI_C_W_RATE_3088KBPS                                     0x50
3772 
3773 #define ORX_FWP_KR1_AMP_R__A                                                0x2020017
3774 #define ORX_FWP_KR1_AMP_R__W                                                9
3775 #define ORX_FWP_KR1_AMP_R__M                                                0x1FF
3776 #define ORX_FWP_KR1_AMP_R__PRE                                              0x0
3777 
3778 #define ORX_FWP_KR1_LDT_W__A                                                0x2020018
3779 #define ORX_FWP_KR1_LDT_W__W                                                3
3780 #define ORX_FWP_KR1_LDT_W__M                                                0x7
3781 #define ORX_FWP_KR1_LDT_W__PRE                                              0x2
3782 #define ORX_FWP_SRC_DGN_W__A                                                0x2020019
3783 #define ORX_FWP_SRC_DGN_W__W                                                16
3784 #define ORX_FWP_SRC_DGN_W__M                                                0xFFFF
3785 #define ORX_FWP_SRC_DGN_W__PRE                                              0x1FF
3786 
3787 #define   ORX_FWP_SRC_DGN_W_MANT__B                                         0
3788 #define   ORX_FWP_SRC_DGN_W_MANT__W                                         9
3789 #define   ORX_FWP_SRC_DGN_W_MANT__M                                         0x1FF
3790 #define   ORX_FWP_SRC_DGN_W_MANT__PRE                                       0x1FF
3791 
3792 #define   ORX_FWP_SRC_DGN_W_EXP__B                                          12
3793 #define   ORX_FWP_SRC_DGN_W_EXP__W                                          4
3794 #define   ORX_FWP_SRC_DGN_W_EXP__M                                          0xF000
3795 #define   ORX_FWP_SRC_DGN_W_EXP__PRE                                        0x0
3796 
3797 #define ORX_FWP_NYQ_ADR_W__A                                                0x202001A
3798 #define ORX_FWP_NYQ_ADR_W__W                                                5
3799 #define ORX_FWP_NYQ_ADR_W__M                                                0x1F
3800 #define ORX_FWP_NYQ_ADR_W__PRE                                              0x1F
3801 
3802 #define ORX_FWP_NYQ_COF_RW__A                                               0x202001B
3803 #define ORX_FWP_NYQ_COF_RW__W                                               10
3804 #define ORX_FWP_NYQ_COF_RW__M                                               0x3FF
3805 #define ORX_FWP_NYQ_COF_RW__PRE                                             0x0
3806 
3807 #define ORX_FWP_IQM_FRQ_W__A                                                0x202001C
3808 #define ORX_FWP_IQM_FRQ_W__W                                                16
3809 #define ORX_FWP_IQM_FRQ_W__M                                                0xFFFF
3810 #define ORX_FWP_IQM_FRQ_W__PRE                                              0x4301
3811 
3812 #define ORX_EQU_COMM_EXEC__A                                                0x2030000
3813 #define ORX_EQU_COMM_EXEC__W                                                2
3814 #define ORX_EQU_COMM_EXEC__M                                                0x3
3815 #define ORX_EQU_COMM_EXEC__PRE                                              0x0
3816 #define   ORX_EQU_COMM_EXEC_STOP                                            0x0
3817 #define   ORX_EQU_COMM_EXEC_ACTIVE                                          0x1
3818 #define   ORX_EQU_COMM_EXEC_HOLD                                            0x2
3819 
3820 #define ORX_EQU_COMM_MB__A                                                  0x2030002
3821 #define ORX_EQU_COMM_MB__W                                                  8
3822 #define ORX_EQU_COMM_MB__M                                                  0xFF
3823 #define ORX_EQU_COMM_MB__PRE                                                0x0
3824 #define   ORX_EQU_COMM_MB_CTL__B                                            0
3825 #define   ORX_EQU_COMM_MB_CTL__W                                            1
3826 #define   ORX_EQU_COMM_MB_CTL__M                                            0x1
3827 #define   ORX_EQU_COMM_MB_CTL__PRE                                          0x0
3828 #define     ORX_EQU_COMM_MB_CTL_OFF                                         0x0
3829 #define     ORX_EQU_COMM_MB_CTL_ON                                          0x1
3830 #define   ORX_EQU_COMM_MB_OBS__B                                            1
3831 #define   ORX_EQU_COMM_MB_OBS__W                                            1
3832 #define   ORX_EQU_COMM_MB_OBS__M                                            0x2
3833 #define   ORX_EQU_COMM_MB_OBS__PRE                                          0x0
3834 #define     ORX_EQU_COMM_MB_OBS_OFF                                         0x0
3835 #define     ORX_EQU_COMM_MB_OBS_ON                                          0x2
3836 
3837 #define   ORX_EQU_COMM_MB_CTL_MUX__B                                        2
3838 #define   ORX_EQU_COMM_MB_CTL_MUX__W                                        3
3839 #define   ORX_EQU_COMM_MB_CTL_MUX__M                                        0x1C
3840 #define   ORX_EQU_COMM_MB_CTL_MUX__PRE                                      0x0
3841 
3842 #define   ORX_EQU_COMM_MB_OBS_MUX__B                                        5
3843 #define   ORX_EQU_COMM_MB_OBS_MUX__W                                        3
3844 #define   ORX_EQU_COMM_MB_OBS_MUX__M                                        0xE0
3845 #define   ORX_EQU_COMM_MB_OBS_MUX__PRE                                      0x0
3846 
3847 #define ORX_EQU_COMM_INT_REQ__A                                             0x2030003
3848 #define ORX_EQU_COMM_INT_REQ__W                                             1
3849 #define ORX_EQU_COMM_INT_REQ__M                                             0x1
3850 #define ORX_EQU_COMM_INT_REQ__PRE                                           0x0
3851 #define ORX_EQU_COMM_INT_STA__A                                             0x2030005
3852 #define ORX_EQU_COMM_INT_STA__W                                             2
3853 #define ORX_EQU_COMM_INT_STA__M                                             0x3
3854 #define ORX_EQU_COMM_INT_STA__PRE                                           0x0
3855 
3856 #define   ORX_EQU_COMM_INT_STA_FFF_READ__B                                  0
3857 #define   ORX_EQU_COMM_INT_STA_FFF_READ__W                                  1
3858 #define   ORX_EQU_COMM_INT_STA_FFF_READ__M                                  0x1
3859 #define   ORX_EQU_COMM_INT_STA_FFF_READ__PRE                                0x0
3860 
3861 #define   ORX_EQU_COMM_INT_STA_FBF_READ__B                                  1
3862 #define   ORX_EQU_COMM_INT_STA_FBF_READ__W                                  1
3863 #define   ORX_EQU_COMM_INT_STA_FBF_READ__M                                  0x2
3864 #define   ORX_EQU_COMM_INT_STA_FBF_READ__PRE                                0x0
3865 
3866 #define ORX_EQU_COMM_INT_MSK__A                                             0x2030006
3867 #define ORX_EQU_COMM_INT_MSK__W                                             2
3868 #define ORX_EQU_COMM_INT_MSK__M                                             0x3
3869 #define ORX_EQU_COMM_INT_MSK__PRE                                           0x0
3870 #define   ORX_EQU_COMM_INT_MSK_FFF_READ__B                                  0
3871 #define   ORX_EQU_COMM_INT_MSK_FFF_READ__W                                  1
3872 #define   ORX_EQU_COMM_INT_MSK_FFF_READ__M                                  0x1
3873 #define   ORX_EQU_COMM_INT_MSK_FFF_READ__PRE                                0x0
3874 #define   ORX_EQU_COMM_INT_MSK_FBF_READ__B                                  1
3875 #define   ORX_EQU_COMM_INT_MSK_FBF_READ__W                                  1
3876 #define   ORX_EQU_COMM_INT_MSK_FBF_READ__M                                  0x2
3877 #define   ORX_EQU_COMM_INT_MSK_FBF_READ__PRE                                0x0
3878 
3879 #define ORX_EQU_COMM_INT_STM__A                                             0x2030007
3880 #define ORX_EQU_COMM_INT_STM__W                                             2
3881 #define ORX_EQU_COMM_INT_STM__M                                             0x3
3882 #define ORX_EQU_COMM_INT_STM__PRE                                           0x0
3883 #define   ORX_EQU_COMM_INT_STM_FFF_READ__B                                  0
3884 #define   ORX_EQU_COMM_INT_STM_FFF_READ__W                                  1
3885 #define   ORX_EQU_COMM_INT_STM_FFF_READ__M                                  0x1
3886 #define   ORX_EQU_COMM_INT_STM_FFF_READ__PRE                                0x0
3887 #define   ORX_EQU_COMM_INT_STM_FBF_READ__B                                  1
3888 #define   ORX_EQU_COMM_INT_STM_FBF_READ__W                                  1
3889 #define   ORX_EQU_COMM_INT_STM_FBF_READ__M                                  0x2
3890 #define   ORX_EQU_COMM_INT_STM_FBF_READ__PRE                                0x0
3891 
3892 #define ORX_EQU_FFF_SCL_W__A                                                0x2030010
3893 #define ORX_EQU_FFF_SCL_W__W                                                1
3894 #define ORX_EQU_FFF_SCL_W__M                                                0x1
3895 #define ORX_EQU_FFF_SCL_W__PRE                                              0x0
3896 #define   ORX_EQU_FFF_SCL_W_SCALE_GAIN_1                                    0x0
3897 #define   ORX_EQU_FFF_SCL_W_SCALE_GAIN_2                                    0x1
3898 
3899 #define ORX_EQU_FFF_UPD_W__A                                                0x2030011
3900 #define ORX_EQU_FFF_UPD_W__W                                                1
3901 #define ORX_EQU_FFF_UPD_W__M                                                0x1
3902 #define ORX_EQU_FFF_UPD_W__PRE                                              0x0
3903 #define   ORX_EQU_FFF_UPD_W_NO_UPDATE                                       0x0
3904 #define   ORX_EQU_FFF_UPD_W_LMS_UPDATE                                      0x1
3905 
3906 #define ORX_EQU_FFF_STP_W__A                                                0x2030012
3907 #define ORX_EQU_FFF_STP_W__W                                                3
3908 #define ORX_EQU_FFF_STP_W__M                                                0x7
3909 #define ORX_EQU_FFF_STP_W__PRE                                              0x2
3910 
3911 #define ORX_EQU_FFF_LEA_W__A                                                0x2030013
3912 #define ORX_EQU_FFF_LEA_W__W                                                4
3913 #define ORX_EQU_FFF_LEA_W__M                                                0xF
3914 #define ORX_EQU_FFF_LEA_W__PRE                                              0x4
3915 
3916 #define ORX_EQU_FFF_RWT_W__A                                                0x2030014
3917 #define ORX_EQU_FFF_RWT_W__W                                                2
3918 #define ORX_EQU_FFF_RWT_W__M                                                0x3
3919 #define ORX_EQU_FFF_RWT_W__PRE                                              0x0
3920 
3921 #define ORX_EQU_FFF_C0RE_RW__A                                              0x2030015
3922 #define ORX_EQU_FFF_C0RE_RW__W                                              12
3923 #define ORX_EQU_FFF_C0RE_RW__M                                              0xFFF
3924 #define ORX_EQU_FFF_C0RE_RW__PRE                                            0x0
3925 
3926 #define ORX_EQU_FFF_C0IM_RW__A                                              0x2030016
3927 #define ORX_EQU_FFF_C0IM_RW__W                                              12
3928 #define ORX_EQU_FFF_C0IM_RW__M                                              0xFFF
3929 #define ORX_EQU_FFF_C0IM_RW__PRE                                            0x0
3930 
3931 #define ORX_EQU_FFF_C1RE_RW__A                                              0x2030017
3932 #define ORX_EQU_FFF_C1RE_RW__W                                              12
3933 #define ORX_EQU_FFF_C1RE_RW__M                                              0xFFF
3934 #define ORX_EQU_FFF_C1RE_RW__PRE                                            0x0
3935 
3936 #define ORX_EQU_FFF_C1IM_RW__A                                              0x2030018
3937 #define ORX_EQU_FFF_C1IM_RW__W                                              12
3938 #define ORX_EQU_FFF_C1IM_RW__M                                              0xFFF
3939 #define ORX_EQU_FFF_C1IM_RW__PRE                                            0x0
3940 
3941 #define ORX_EQU_FFF_C2RE_RW__A                                              0x2030019
3942 #define ORX_EQU_FFF_C2RE_RW__W                                              12
3943 #define ORX_EQU_FFF_C2RE_RW__M                                              0xFFF
3944 #define ORX_EQU_FFF_C2RE_RW__PRE                                            0x0
3945 
3946 #define ORX_EQU_FFF_C2IM_RW__A                                              0x203001A
3947 #define ORX_EQU_FFF_C2IM_RW__W                                              12
3948 #define ORX_EQU_FFF_C2IM_RW__M                                              0xFFF
3949 #define ORX_EQU_FFF_C2IM_RW__PRE                                            0x0
3950 
3951 #define ORX_EQU_FFF_C3RE_RW__A                                              0x203001B
3952 #define ORX_EQU_FFF_C3RE_RW__W                                              12
3953 #define ORX_EQU_FFF_C3RE_RW__M                                              0xFFF
3954 #define ORX_EQU_FFF_C3RE_RW__PRE                                            0x0
3955 
3956 #define ORX_EQU_FFF_C3IM_RW__A                                              0x203001C
3957 #define ORX_EQU_FFF_C3IM_RW__W                                              12
3958 #define ORX_EQU_FFF_C3IM_RW__M                                              0xFFF
3959 #define ORX_EQU_FFF_C3IM_RW__PRE                                            0x0
3960 
3961 #define ORX_EQU_FFF_C4RE_RW__A                                              0x203001D
3962 #define ORX_EQU_FFF_C4RE_RW__W                                              12
3963 #define ORX_EQU_FFF_C4RE_RW__M                                              0xFFF
3964 #define ORX_EQU_FFF_C4RE_RW__PRE                                            0x400
3965 
3966 #define ORX_EQU_FFF_C4IM_RW__A                                              0x203001E
3967 #define ORX_EQU_FFF_C4IM_RW__W                                              12
3968 #define ORX_EQU_FFF_C4IM_RW__M                                              0xFFF
3969 #define ORX_EQU_FFF_C4IM_RW__PRE                                            0x0
3970 
3971 #define ORX_EQU_FFF_C5RE_RW__A                                              0x203001F
3972 #define ORX_EQU_FFF_C5RE_RW__W                                              12
3973 #define ORX_EQU_FFF_C5RE_RW__M                                              0xFFF
3974 #define ORX_EQU_FFF_C5RE_RW__PRE                                            0x0
3975 
3976 #define ORX_EQU_FFF_C5IM_RW__A                                              0x2030020
3977 #define ORX_EQU_FFF_C5IM_RW__W                                              12
3978 #define ORX_EQU_FFF_C5IM_RW__M                                              0xFFF
3979 #define ORX_EQU_FFF_C5IM_RW__PRE                                            0x0
3980 
3981 #define ORX_EQU_FFF_C6RE_RW__A                                              0x2030021
3982 #define ORX_EQU_FFF_C6RE_RW__W                                              12
3983 #define ORX_EQU_FFF_C6RE_RW__M                                              0xFFF
3984 #define ORX_EQU_FFF_C6RE_RW__PRE                                            0x0
3985 
3986 #define ORX_EQU_FFF_C6IM_RW__A                                              0x2030022
3987 #define ORX_EQU_FFF_C6IM_RW__W                                              12
3988 #define ORX_EQU_FFF_C6IM_RW__M                                              0xFFF
3989 #define ORX_EQU_FFF_C6IM_RW__PRE                                            0x0
3990 
3991 #define ORX_EQU_FFF_C7RE_RW__A                                              0x2030023
3992 #define ORX_EQU_FFF_C7RE_RW__W                                              12
3993 #define ORX_EQU_FFF_C7RE_RW__M                                              0xFFF
3994 #define ORX_EQU_FFF_C7RE_RW__PRE                                            0x0
3995 
3996 #define ORX_EQU_FFF_C7IM_RW__A                                              0x2030024
3997 #define ORX_EQU_FFF_C7IM_RW__W                                              12
3998 #define ORX_EQU_FFF_C7IM_RW__M                                              0xFFF
3999 #define ORX_EQU_FFF_C7IM_RW__PRE                                            0x0
4000 
4001 #define ORX_EQU_FFF_C8RE_RW__A                                              0x2030025
4002 #define ORX_EQU_FFF_C8RE_RW__W                                              12
4003 #define ORX_EQU_FFF_C8RE_RW__M                                              0xFFF
4004 #define ORX_EQU_FFF_C8RE_RW__PRE                                            0x0
4005 
4006 #define ORX_EQU_FFF_C8IM_RW__A                                              0x2030026
4007 #define ORX_EQU_FFF_C8IM_RW__W                                              12
4008 #define ORX_EQU_FFF_C8IM_RW__M                                              0xFFF
4009 #define ORX_EQU_FFF_C8IM_RW__PRE                                            0x0
4010 
4011 #define ORX_EQU_FFF_C9RE_RW__A                                              0x2030027
4012 #define ORX_EQU_FFF_C9RE_RW__W                                              12
4013 #define ORX_EQU_FFF_C9RE_RW__M                                              0xFFF
4014 #define ORX_EQU_FFF_C9RE_RW__PRE                                            0x0
4015 
4016 #define ORX_EQU_FFF_C9IM_RW__A                                              0x2030028
4017 #define ORX_EQU_FFF_C9IM_RW__W                                              12
4018 #define ORX_EQU_FFF_C9IM_RW__M                                              0xFFF
4019 #define ORX_EQU_FFF_C9IM_RW__PRE                                            0x0
4020 
4021 #define ORX_EQU_FFF_C10RE_RW__A                                             0x2030029
4022 #define ORX_EQU_FFF_C10RE_RW__W                                             12
4023 #define ORX_EQU_FFF_C10RE_RW__M                                             0xFFF
4024 #define ORX_EQU_FFF_C10RE_RW__PRE                                           0x0
4025 
4026 #define ORX_EQU_FFF_C10IM_RW__A                                             0x203002A
4027 #define ORX_EQU_FFF_C10IM_RW__W                                             12
4028 #define ORX_EQU_FFF_C10IM_RW__M                                             0xFFF
4029 #define ORX_EQU_FFF_C10IM_RW__PRE                                           0x0
4030 
4031 #define ORX_EQU_MXB_SEL_W__A                                                0x203002B
4032 #define ORX_EQU_MXB_SEL_W__W                                                1
4033 #define ORX_EQU_MXB_SEL_W__M                                                0x1
4034 #define ORX_EQU_MXB_SEL_W__PRE                                              0x0
4035 #define   ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS                               0x0
4036 #define   ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS                                 0x1
4037 
4038 #define ORX_EQU_FBF_UPD_W__A                                                0x203002C
4039 #define ORX_EQU_FBF_UPD_W__W                                                1
4040 #define ORX_EQU_FBF_UPD_W__M                                                0x1
4041 #define ORX_EQU_FBF_UPD_W__PRE                                              0x0
4042 #define   ORX_EQU_FBF_UPD_W_NO_UPDATE                                       0x0
4043 #define   ORX_EQU_FBF_UPD_W_LMS_UPDATE                                      0x1
4044 
4045 #define ORX_EQU_FBF_STP_W__A                                                0x203002D
4046 #define ORX_EQU_FBF_STP_W__W                                                3
4047 #define ORX_EQU_FBF_STP_W__M                                                0x7
4048 #define ORX_EQU_FBF_STP_W__PRE                                              0x2
4049 
4050 #define ORX_EQU_FBF_LEA_W__A                                                0x203002E
4051 #define ORX_EQU_FBF_LEA_W__W                                                4
4052 #define ORX_EQU_FBF_LEA_W__M                                                0xF
4053 #define ORX_EQU_FBF_LEA_W__PRE                                              0x4
4054 
4055 #define ORX_EQU_FBF_RWT_W__A                                                0x203002F
4056 #define ORX_EQU_FBF_RWT_W__W                                                2
4057 #define ORX_EQU_FBF_RWT_W__M                                                0x3
4058 #define ORX_EQU_FBF_RWT_W__PRE                                              0x0
4059 
4060 #define ORX_EQU_FBF_C0RE_RW__A                                              0x2030030
4061 #define ORX_EQU_FBF_C0RE_RW__W                                              12
4062 #define ORX_EQU_FBF_C0RE_RW__M                                              0xFFF
4063 #define ORX_EQU_FBF_C0RE_RW__PRE                                            0x0
4064 
4065 #define ORX_EQU_FBF_C0IM_RW__A                                              0x2030031
4066 #define ORX_EQU_FBF_C0IM_RW__W                                              12
4067 #define ORX_EQU_FBF_C0IM_RW__M                                              0xFFF
4068 #define ORX_EQU_FBF_C0IM_RW__PRE                                            0x0
4069 
4070 #define ORX_EQU_FBF_C1RE_RW__A                                              0x2030032
4071 #define ORX_EQU_FBF_C1RE_RW__W                                              12
4072 #define ORX_EQU_FBF_C1RE_RW__M                                              0xFFF
4073 #define ORX_EQU_FBF_C1RE_RW__PRE                                            0x0
4074 
4075 #define ORX_EQU_FBF_C1IM_RW__A                                              0x2030033
4076 #define ORX_EQU_FBF_C1IM_RW__W                                              12
4077 #define ORX_EQU_FBF_C1IM_RW__M                                              0xFFF
4078 #define ORX_EQU_FBF_C1IM_RW__PRE                                            0x0
4079 
4080 #define ORX_EQU_FBF_C2RE_RW__A                                              0x2030034
4081 #define ORX_EQU_FBF_C2RE_RW__W                                              12
4082 #define ORX_EQU_FBF_C2RE_RW__M                                              0xFFF
4083 #define ORX_EQU_FBF_C2RE_RW__PRE                                            0x0
4084 
4085 #define ORX_EQU_FBF_C2IM_RW__A                                              0x2030035
4086 #define ORX_EQU_FBF_C2IM_RW__W                                              12
4087 #define ORX_EQU_FBF_C2IM_RW__M                                              0xFFF
4088 #define ORX_EQU_FBF_C2IM_RW__PRE                                            0x0
4089 
4090 #define ORX_EQU_FBF_C3RE_RW__A                                              0x2030036
4091 #define ORX_EQU_FBF_C3RE_RW__W                                              12
4092 #define ORX_EQU_FBF_C3RE_RW__M                                              0xFFF
4093 #define ORX_EQU_FBF_C3RE_RW__PRE                                            0x0
4094 
4095 #define ORX_EQU_FBF_C3IM_RW__A                                              0x2030037
4096 #define ORX_EQU_FBF_C3IM_RW__W                                              12
4097 #define ORX_EQU_FBF_C3IM_RW__M                                              0xFFF
4098 #define ORX_EQU_FBF_C3IM_RW__PRE                                            0x0
4099 
4100 #define ORX_EQU_FBF_C4RE_RW__A                                              0x2030038
4101 #define ORX_EQU_FBF_C4RE_RW__W                                              12
4102 #define ORX_EQU_FBF_C4RE_RW__M                                              0xFFF
4103 #define ORX_EQU_FBF_C4RE_RW__PRE                                            0x0
4104 
4105 #define ORX_EQU_FBF_C4IM_RW__A                                              0x2030039
4106 #define ORX_EQU_FBF_C4IM_RW__W                                              12
4107 #define ORX_EQU_FBF_C4IM_RW__M                                              0xFFF
4108 #define ORX_EQU_FBF_C4IM_RW__PRE                                            0x0
4109 
4110 #define ORX_EQU_FBF_C5RE_RW__A                                              0x203003A
4111 #define ORX_EQU_FBF_C5RE_RW__W                                              12
4112 #define ORX_EQU_FBF_C5RE_RW__M                                              0xFFF
4113 #define ORX_EQU_FBF_C5RE_RW__PRE                                            0x0
4114 
4115 #define ORX_EQU_FBF_C5IM_RW__A                                              0x203003B
4116 #define ORX_EQU_FBF_C5IM_RW__W                                              12
4117 #define ORX_EQU_FBF_C5IM_RW__M                                              0xFFF
4118 #define ORX_EQU_FBF_C5IM_RW__PRE                                            0x0
4119 
4120 #define ORX_EQU_ERR_SEL_W__A                                                0x203003C
4121 #define ORX_EQU_ERR_SEL_W__W                                                1
4122 #define ORX_EQU_ERR_SEL_W__M                                                0x1
4123 #define ORX_EQU_ERR_SEL_W__PRE                                              0x0
4124 #define   ORX_EQU_ERR_SEL_W_CMA_ERROR                                       0x0
4125 #define   ORX_EQU_ERR_SEL_W_DDA_ERROR                                       0x1
4126 
4127 #define ORX_EQU_ERR_TIS_W__A                                                0x203003D
4128 #define ORX_EQU_ERR_TIS_W__W                                                1
4129 #define ORX_EQU_ERR_TIS_W__M                                                0x1
4130 #define ORX_EQU_ERR_TIS_W__PRE                                              0x0
4131 #define   ORX_EQU_ERR_TIS_W_CMA_SIGNALS                                     0x0
4132 #define   ORX_EQU_ERR_TIS_W_DDA_SIGNALS                                     0x1
4133 
4134 #define ORX_EQU_ERR_EDI_R__A                                                0x203003E
4135 #define ORX_EQU_ERR_EDI_R__W                                                5
4136 #define ORX_EQU_ERR_EDI_R__M                                                0x1F
4137 #define ORX_EQU_ERR_EDI_R__PRE                                              0xF
4138 
4139 #define ORX_EQU_ERR_EDQ_R__A                                                0x203003F
4140 #define ORX_EQU_ERR_EDQ_R__W                                                5
4141 #define ORX_EQU_ERR_EDQ_R__M                                                0x1F
4142 #define ORX_EQU_ERR_EDQ_R__PRE                                              0xF
4143 
4144 #define ORX_EQU_ERR_ECI_R__A                                                0x2030040
4145 #define ORX_EQU_ERR_ECI_R__W                                                5
4146 #define ORX_EQU_ERR_ECI_R__M                                                0x1F
4147 #define ORX_EQU_ERR_ECI_R__PRE                                              0xF
4148 
4149 #define ORX_EQU_ERR_ECQ_R__A                                                0x2030041
4150 #define ORX_EQU_ERR_ECQ_R__W                                                5
4151 #define ORX_EQU_ERR_ECQ_R__M                                                0x1F
4152 #define ORX_EQU_ERR_ECQ_R__PRE                                              0xF
4153 
4154 #define ORX_EQU_MER_MER_R__A                                                0x2030042
4155 #define ORX_EQU_MER_MER_R__W                                                6
4156 #define ORX_EQU_MER_MER_R__M                                                0x3F
4157 #define ORX_EQU_MER_MER_R__PRE                                              0x3F
4158 
4159 #define ORX_EQU_MER_LDT_W__A                                                0x2030043
4160 #define ORX_EQU_MER_LDT_W__W                                                3
4161 #define ORX_EQU_MER_LDT_W__M                                                0x7
4162 #define ORX_EQU_MER_LDT_W__PRE                                              0x4
4163 
4164 #define ORX_EQU_SYN_LEN_W__A                                                0x2030044
4165 #define ORX_EQU_SYN_LEN_W__W                                                16
4166 #define ORX_EQU_SYN_LEN_W__M                                                0xFFFF
4167 #define ORX_EQU_SYN_LEN_W__PRE                                              0x0
4168 
4169 #define ORX_DDC_COMM_EXEC__A                                                0x2040000
4170 #define ORX_DDC_COMM_EXEC__W                                                2
4171 #define ORX_DDC_COMM_EXEC__M                                                0x3
4172 #define ORX_DDC_COMM_EXEC__PRE                                              0x0
4173 #define   ORX_DDC_COMM_EXEC_STOP                                            0x0
4174 #define   ORX_DDC_COMM_EXEC_ACTIVE                                          0x1
4175 #define   ORX_DDC_COMM_EXEC_HOLD                                            0x2
4176 
4177 #define ORX_DDC_COMM_MB__A                                                  0x2040002
4178 #define ORX_DDC_COMM_MB__W                                                  6
4179 #define ORX_DDC_COMM_MB__M                                                  0x3F
4180 #define ORX_DDC_COMM_MB__PRE                                                0x0
4181 #define   ORX_DDC_COMM_MB_CTL__B                                            0
4182 #define   ORX_DDC_COMM_MB_CTL__W                                            1
4183 #define   ORX_DDC_COMM_MB_CTL__M                                            0x1
4184 #define   ORX_DDC_COMM_MB_CTL__PRE                                          0x0
4185 #define     ORX_DDC_COMM_MB_CTL_OFF                                         0x0
4186 #define     ORX_DDC_COMM_MB_CTL_ON                                          0x1
4187 #define   ORX_DDC_COMM_MB_OBS__B                                            1
4188 #define   ORX_DDC_COMM_MB_OBS__W                                            1
4189 #define   ORX_DDC_COMM_MB_OBS__M                                            0x2
4190 #define   ORX_DDC_COMM_MB_OBS__PRE                                          0x0
4191 #define     ORX_DDC_COMM_MB_OBS_OFF                                         0x0
4192 #define     ORX_DDC_COMM_MB_OBS_ON                                          0x2
4193 
4194 #define   ORX_DDC_COMM_MB_CTL_MUX__B                                        2
4195 #define   ORX_DDC_COMM_MB_CTL_MUX__W                                        2
4196 #define   ORX_DDC_COMM_MB_CTL_MUX__M                                        0xC
4197 #define   ORX_DDC_COMM_MB_CTL_MUX__PRE                                      0x0
4198 
4199 #define   ORX_DDC_COMM_MB_OBS_MUX__B                                        4
4200 #define   ORX_DDC_COMM_MB_OBS_MUX__W                                        2
4201 #define   ORX_DDC_COMM_MB_OBS_MUX__M                                        0x30
4202 #define   ORX_DDC_COMM_MB_OBS_MUX__PRE                                      0x0
4203 
4204 #define ORX_DDC_COMM_INT_REQ__A                                             0x2040003
4205 #define ORX_DDC_COMM_INT_REQ__W                                             1
4206 #define ORX_DDC_COMM_INT_REQ__M                                             0x1
4207 #define ORX_DDC_COMM_INT_REQ__PRE                                           0x0
4208 #define ORX_DDC_COMM_INT_STA__A                                             0x2040005
4209 #define ORX_DDC_COMM_INT_STA__W                                             1
4210 #define ORX_DDC_COMM_INT_STA__M                                             0x1
4211 #define ORX_DDC_COMM_INT_STA__PRE                                           0x0
4212 #define ORX_DDC_COMM_INT_MSK__A                                             0x2040006
4213 #define ORX_DDC_COMM_INT_MSK__W                                             1
4214 #define ORX_DDC_COMM_INT_MSK__M                                             0x1
4215 #define ORX_DDC_COMM_INT_MSK__PRE                                           0x0
4216 #define ORX_DDC_COMM_INT_STM__A                                             0x2040007
4217 #define ORX_DDC_COMM_INT_STM__W                                             1
4218 #define ORX_DDC_COMM_INT_STM__M                                             0x1
4219 #define ORX_DDC_COMM_INT_STM__PRE                                           0x0
4220 #define ORX_DDC_DEC_MAP_W__A                                                0x2040010
4221 #define ORX_DDC_DEC_MAP_W__W                                                9
4222 #define ORX_DDC_DEC_MAP_W__M                                                0x1FF
4223 #define ORX_DDC_DEC_MAP_W__PRE                                              0x178
4224 
4225 #define   ORX_DDC_DEC_MAP_W_QUADR0__B                                       0
4226 #define   ORX_DDC_DEC_MAP_W_QUADR0__W                                       2
4227 #define   ORX_DDC_DEC_MAP_W_QUADR0__M                                       0x3
4228 #define   ORX_DDC_DEC_MAP_W_QUADR0__PRE                                     0x0
4229 #define     ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_DEFAULT                         0x0
4230 #define     ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE                       0x0
4231 
4232 #define   ORX_DDC_DEC_MAP_W_QUADR1__B                                       2
4233 #define   ORX_DDC_DEC_MAP_W_QUADR1__W                                       2
4234 #define   ORX_DDC_DEC_MAP_W_QUADR1__M                                       0xC
4235 #define   ORX_DDC_DEC_MAP_W_QUADR1__PRE                                     0x8
4236 #define     ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT                         0x8
4237 #define     ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE                       0x4
4238 
4239 #define   ORX_DDC_DEC_MAP_W_QUADR2__B                                       4
4240 #define   ORX_DDC_DEC_MAP_W_QUADR2__W                                       2
4241 #define   ORX_DDC_DEC_MAP_W_QUADR2__M                                       0x30
4242 #define   ORX_DDC_DEC_MAP_W_QUADR2__PRE                                     0x30
4243 #define     ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT                         0x30
4244 #define     ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE                       0x30
4245 
4246 #define   ORX_DDC_DEC_MAP_W_QUADR3__B                                       6
4247 #define   ORX_DDC_DEC_MAP_W_QUADR3__W                                       2
4248 #define   ORX_DDC_DEC_MAP_W_QUADR3__M                                       0xC0
4249 #define   ORX_DDC_DEC_MAP_W_QUADR3__PRE                                     0x40
4250 #define     ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT                         0x40
4251 #define     ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE                       0x80
4252 #define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__B                                   8
4253 #define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__W                                   1
4254 #define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__M                                   0x100
4255 #define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__PRE                                 0x100
4256 #define     ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING                  0x0
4257 #define     ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING                      0x100
4258 
4259 #define ORX_DDC_OFO_SET_W__A                                                0x2040011
4260 #define ORX_DDC_OFO_SET_W__W                                                16
4261 #define ORX_DDC_OFO_SET_W__M                                                0xFFFF
4262 #define ORX_DDC_OFO_SET_W__PRE                                              0x1402
4263 
4264 #define   ORX_DDC_OFO_SET_W_PHASE__B                                        0
4265 #define   ORX_DDC_OFO_SET_W_PHASE__W                                        7
4266 #define   ORX_DDC_OFO_SET_W_PHASE__M                                        0x7F
4267 #define   ORX_DDC_OFO_SET_W_PHASE__PRE                                      0x2
4268 
4269 #define   ORX_DDC_OFO_SET_W_CRXHITIME__B                                    7
4270 #define   ORX_DDC_OFO_SET_W_CRXHITIME__W                                    7
4271 #define   ORX_DDC_OFO_SET_W_CRXHITIME__M                                    0x3F80
4272 #define   ORX_DDC_OFO_SET_W_CRXHITIME__PRE                                  0x1400
4273 
4274 #define   ORX_DDC_OFO_SET_W_CRXINV__B                                       14
4275 #define   ORX_DDC_OFO_SET_W_CRXINV__W                                       1
4276 #define   ORX_DDC_OFO_SET_W_CRXINV__M                                       0x4000
4277 #define   ORX_DDC_OFO_SET_W_CRXINV__PRE                                     0x0
4278 
4279 #define   ORX_DDC_OFO_SET_W_DISABLE__B                                      15
4280 #define   ORX_DDC_OFO_SET_W_DISABLE__W                                      1
4281 #define   ORX_DDC_OFO_SET_W_DISABLE__M                                      0x8000
4282 #define   ORX_DDC_OFO_SET_W_DISABLE__PRE                                    0x0
4283 
4284 #define ORX_CON_COMM_EXEC__A                                                0x2050000
4285 #define ORX_CON_COMM_EXEC__W                                                2
4286 #define ORX_CON_COMM_EXEC__M                                                0x3
4287 #define ORX_CON_COMM_EXEC__PRE                                              0x0
4288 #define   ORX_CON_COMM_EXEC_STOP                                            0x0
4289 #define   ORX_CON_COMM_EXEC_ACTIVE                                          0x1
4290 #define   ORX_CON_COMM_EXEC_HOLD                                            0x2
4291 
4292 #define ORX_CON_LDT_W__A                                                    0x2050010
4293 #define ORX_CON_LDT_W__W                                                    3
4294 #define ORX_CON_LDT_W__M                                                    0x7
4295 #define ORX_CON_LDT_W__PRE                                                  0x3
4296 
4297 #define   ORX_CON_LDT_W_CON_LDT_W__B                                        0
4298 #define   ORX_CON_LDT_W_CON_LDT_W__W                                        3
4299 #define   ORX_CON_LDT_W_CON_LDT_W__M                                        0x7
4300 #define   ORX_CON_LDT_W_CON_LDT_W__PRE                                      0x3
4301 
4302 #define ORX_CON_RST_W__A                                                    0x2050011
4303 #define ORX_CON_RST_W__W                                                    4
4304 #define ORX_CON_RST_W__M                                                    0xF
4305 #define ORX_CON_RST_W__PRE                                                  0x0
4306 
4307 #define   ORX_CON_RST_W_CPH__B                                              0
4308 #define   ORX_CON_RST_W_CPH__W                                              1
4309 #define   ORX_CON_RST_W_CPH__M                                              0x1
4310 #define   ORX_CON_RST_W_CPH__PRE                                            0x0
4311 
4312 #define   ORX_CON_RST_W_CTI__B                                              1
4313 #define   ORX_CON_RST_W_CTI__W                                              1
4314 #define   ORX_CON_RST_W_CTI__M                                              0x2
4315 #define   ORX_CON_RST_W_CTI__PRE                                            0x0
4316 
4317 #define   ORX_CON_RST_W_KRN__B                                              2
4318 #define   ORX_CON_RST_W_KRN__W                                              1
4319 #define   ORX_CON_RST_W_KRN__M                                              0x4
4320 #define   ORX_CON_RST_W_KRN__PRE                                            0x0
4321 
4322 #define   ORX_CON_RST_W_KRP__B                                              3
4323 #define   ORX_CON_RST_W_KRP__W                                              1
4324 #define   ORX_CON_RST_W_KRP__M                                              0x8
4325 #define   ORX_CON_RST_W_KRP__PRE                                            0x0
4326 
4327 #define ORX_CON_CPH_PHI_R__A                                                0x2050012
4328 #define ORX_CON_CPH_PHI_R__W                                                16
4329 #define ORX_CON_CPH_PHI_R__M                                                0xFFFF
4330 #define ORX_CON_CPH_PHI_R__PRE                                              0x0
4331 
4332 #define ORX_CON_CPH_FRQ_R__A                                                0x2050013
4333 #define ORX_CON_CPH_FRQ_R__W                                                16
4334 #define ORX_CON_CPH_FRQ_R__M                                                0xFFFF
4335 #define ORX_CON_CPH_FRQ_R__PRE                                              0x0
4336 
4337 #define ORX_CON_CPH_AMP_R__A                                                0x2050014
4338 #define ORX_CON_CPH_AMP_R__W                                                16
4339 #define ORX_CON_CPH_AMP_R__M                                                0xFFFF
4340 #define ORX_CON_CPH_AMP_R__PRE                                              0x0
4341 
4342 #define ORX_CON_CPH_KDF_W__A                                                0x2050015
4343 #define ORX_CON_CPH_KDF_W__W                                                4
4344 #define ORX_CON_CPH_KDF_W__M                                                0xF
4345 #define ORX_CON_CPH_KDF_W__PRE                                              0x0
4346 
4347 #define ORX_CON_CPH_KPF_W__A                                                0x2050016
4348 #define ORX_CON_CPH_KPF_W__W                                                4
4349 #define ORX_CON_CPH_KPF_W__M                                                0xF
4350 #define ORX_CON_CPH_KPF_W__PRE                                              0x0
4351 
4352 #define ORX_CON_CPH_KIF_W__A                                                0x2050017
4353 #define ORX_CON_CPH_KIF_W__W                                                4
4354 #define ORX_CON_CPH_KIF_W__M                                                0xF
4355 #define ORX_CON_CPH_KIF_W__PRE                                              0x0
4356 #define ORX_CON_CPH_APT_W__A                                                0x2050018
4357 #define ORX_CON_CPH_APT_W__W                                                16
4358 #define ORX_CON_CPH_APT_W__M                                                0xFFFF
4359 #define ORX_CON_CPH_APT_W__PRE                                              0x804
4360 
4361 #define   ORX_CON_CPH_APT_W_PTH__B                                          0
4362 #define   ORX_CON_CPH_APT_W_PTH__W                                          8
4363 #define   ORX_CON_CPH_APT_W_PTH__M                                          0xFF
4364 #define   ORX_CON_CPH_APT_W_PTH__PRE                                        0x4
4365 
4366 #define   ORX_CON_CPH_APT_W_ATH__B                                          8
4367 #define   ORX_CON_CPH_APT_W_ATH__W                                          8
4368 #define   ORX_CON_CPH_APT_W_ATH__M                                          0xFF00
4369 #define   ORX_CON_CPH_APT_W_ATH__PRE                                        0x800
4370 
4371 #define ORX_CON_CPH_WLC_W__A                                                0x2050019
4372 #define ORX_CON_CPH_WLC_W__W                                                8
4373 #define ORX_CON_CPH_WLC_W__M                                                0xFF
4374 #define ORX_CON_CPH_WLC_W__PRE                                              0x81
4375 
4376 #define   ORX_CON_CPH_WLC_W_LATC__B                                         0
4377 #define   ORX_CON_CPH_WLC_W_LATC__W                                         4
4378 #define   ORX_CON_CPH_WLC_W_LATC__M                                         0xF
4379 #define   ORX_CON_CPH_WLC_W_LATC__PRE                                       0x1
4380 
4381 #define   ORX_CON_CPH_WLC_W_WLIM__B                                         4
4382 #define   ORX_CON_CPH_WLC_W_WLIM__W                                         4
4383 #define   ORX_CON_CPH_WLC_W_WLIM__M                                         0xF0
4384 #define   ORX_CON_CPH_WLC_W_WLIM__PRE                                       0x80
4385 
4386 #define ORX_CON_CPH_DLY_W__A                                                0x205001A
4387 #define ORX_CON_CPH_DLY_W__W                                                3
4388 #define ORX_CON_CPH_DLY_W__M                                                0x7
4389 #define ORX_CON_CPH_DLY_W__PRE                                              0x4
4390 
4391 #define ORX_CON_CPH_TCL_W__A                                                0x205001B
4392 #define ORX_CON_CPH_TCL_W__W                                                3
4393 #define ORX_CON_CPH_TCL_W__M                                                0x7
4394 #define ORX_CON_CPH_TCL_W__PRE                                              0x3
4395 
4396 #define ORX_CON_KRP_AMP_R__A                                                0x205001C
4397 #define ORX_CON_KRP_AMP_R__W                                                9
4398 #define ORX_CON_KRP_AMP_R__M                                                0x1FF
4399 #define ORX_CON_KRP_AMP_R__PRE                                              0x0
4400 
4401 #define ORX_CON_KRN_AMP_R__A                                                0x205001D
4402 #define ORX_CON_KRN_AMP_R__W                                                9
4403 #define ORX_CON_KRN_AMP_R__M                                                0x1FF
4404 #define ORX_CON_KRN_AMP_R__PRE                                              0x0
4405 
4406 #define ORX_CON_CTI_DTI_R__A                                                0x205001E
4407 #define ORX_CON_CTI_DTI_R__W                                                16
4408 #define ORX_CON_CTI_DTI_R__M                                                0xFFFF
4409 #define ORX_CON_CTI_DTI_R__PRE                                              0x0
4410 
4411 #define ORX_CON_CTI_KDT_W__A                                                0x205001F
4412 #define ORX_CON_CTI_KDT_W__W                                                4
4413 #define ORX_CON_CTI_KDT_W__M                                                0xF
4414 #define ORX_CON_CTI_KDT_W__PRE                                              0x4
4415 
4416 #define ORX_CON_CTI_KPT_W__A                                                0x2050020
4417 #define ORX_CON_CTI_KPT_W__W                                                4
4418 #define ORX_CON_CTI_KPT_W__M                                                0xF
4419 #define ORX_CON_CTI_KPT_W__PRE                                              0x3
4420 
4421 #define ORX_CON_CTI_KIT_W__A                                                0x2050021
4422 #define ORX_CON_CTI_KIT_W__W                                                4
4423 #define ORX_CON_CTI_KIT_W__M                                                0xF
4424 #define ORX_CON_CTI_KIT_W__PRE                                              0xB
4425 
4426 #define ORX_CON_CTI_TAT_W__A                                                0x2050022
4427 #define ORX_CON_CTI_TAT_W__W                                                4
4428 #define ORX_CON_CTI_TAT_W__M                                                0xF
4429 #define ORX_CON_CTI_TAT_W__PRE                                              0x3
4430 
4431 #define ORX_NSU_COMM_EXEC__A                                                0x2060000
4432 #define ORX_NSU_COMM_EXEC__W                                                2
4433 #define ORX_NSU_COMM_EXEC__M                                                0x3
4434 #define ORX_NSU_COMM_EXEC__PRE                                              0x0
4435 #define   ORX_NSU_COMM_EXEC_STOP                                            0x0
4436 #define   ORX_NSU_COMM_EXEC_ACTIVE                                          0x1
4437 #define   ORX_NSU_COMM_EXEC_HOLD                                            0x2
4438 
4439 #define ORX_NSU_AOX_STDBY_W__A                                              0x2060010
4440 #define ORX_NSU_AOX_STDBY_W__W                                              8
4441 #define ORX_NSU_AOX_STDBY_W__M                                              0xFF
4442 #define ORX_NSU_AOX_STDBY_W__PRE                                            0x0
4443 
4444 #define   ORX_NSU_AOX_STDBY_W_STDBYADC__B                                   0
4445 #define   ORX_NSU_AOX_STDBY_W_STDBYADC__W                                   1
4446 #define   ORX_NSU_AOX_STDBY_W_STDBYADC__M                                   0x1
4447 #define   ORX_NSU_AOX_STDBY_W_STDBYADC__PRE                                 0x0
4448 #define     ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON                              0x0
4449 #define     ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF                             0x1
4450 #define     ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF                             0x0
4451 #define     ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON                              0x1
4452 
4453 #define   ORX_NSU_AOX_STDBY_W_STDBYAMP__B                                   1
4454 #define   ORX_NSU_AOX_STDBY_W_STDBYAMP__W                                   1
4455 #define   ORX_NSU_AOX_STDBY_W_STDBYAMP__M                                   0x2
4456 #define   ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE                                 0x0
4457 #define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON                              0x0
4458 #define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF                             0x2
4459 #define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF                             0x0
4460 #define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON                              0x2
4461 
4462 #define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__B                                  2
4463 #define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__W                                  1
4464 #define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__M                                  0x4
4465 #define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE                                0x0
4466 #define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON                             0x0
4467 #define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF                            0x4
4468 #define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF                            0x0
4469 #define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON                             0x4
4470 
4471 #define   ORX_NSU_AOX_STDBY_W_STDBYPLL__B                                   3
4472 #define   ORX_NSU_AOX_STDBY_W_STDBYPLL__W                                   1
4473 #define   ORX_NSU_AOX_STDBY_W_STDBYPLL__M                                   0x8
4474 #define   ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE                                 0x0
4475 #define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON                              0x0
4476 #define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF                             0x8
4477 #define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF                             0x0
4478 #define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON                              0x8
4479 
4480 #define   ORX_NSU_AOX_STDBY_W_STDBYPD__B                                    4
4481 #define   ORX_NSU_AOX_STDBY_W_STDBYPD__W                                    1
4482 #define   ORX_NSU_AOX_STDBY_W_STDBYPD__M                                    0x10
4483 #define   ORX_NSU_AOX_STDBY_W_STDBYPD__PRE                                  0x0
4484 #define     ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON                               0x0
4485 #define     ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF                              0x10
4486 #define     ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF                              0x0
4487 #define     ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON                               0x10
4488 
4489 #define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B                               5
4490 #define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W                               1
4491 #define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M                               0x20
4492 #define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE                             0x0
4493 #define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON                          0x0
4494 #define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF                         0x20
4495 #define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF                         0x0
4496 #define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON                          0x20
4497 
4498 #define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B                               6
4499 #define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W                               1
4500 #define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M                               0x40
4501 #define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE                             0x0
4502 #define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON                          0x0
4503 #define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF                         0x40
4504 #define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF                         0x0
4505 #define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON                          0x40
4506 
4507 #define   ORX_NSU_AOX_STDBY_W_STDBYFLT__B                                   7
4508 #define   ORX_NSU_AOX_STDBY_W_STDBYFLT__W                                   1
4509 #define   ORX_NSU_AOX_STDBY_W_STDBYFLT__M                                   0x80
4510 #define   ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE                                 0x0
4511 #define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON                              0x0
4512 #define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF                             0x80
4513 #define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF                             0x0
4514 #define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON                              0x80
4515 
4516 #define ORX_NSU_AOX_LOFRQ_W__A                                              0x2060011
4517 #define ORX_NSU_AOX_LOFRQ_W__W                                              16
4518 #define ORX_NSU_AOX_LOFRQ_W__M                                              0xFFFF
4519 #define ORX_NSU_AOX_LOFRQ_W__PRE                                            0x0
4520 #define ORX_NSU_AOX_LOMDE_W__A                                              0x2060012
4521 #define ORX_NSU_AOX_LOMDE_W__W                                              16
4522 #define ORX_NSU_AOX_LOMDE_W__M                                              0xFFFF
4523 #define ORX_NSU_AOX_LOMDE_W__PRE                                            0x0
4524 
4525 #define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B                              0
4526 #define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W                              8
4527 #define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M                              0xFF
4528 #define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE                            0x0
4529 
4530 #define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__B                                  13
4531 #define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__W                                  1
4532 #define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__M                                  0x2000
4533 #define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE                                0x0
4534 
4535 #define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__B                                    14
4536 #define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__W                                    2
4537 #define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__M                                    0xC000
4538 #define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE                                  0x0
4539 
4540 #define ORX_NSU_AOX_LOPOW_W__A                                              0x2060013
4541 #define ORX_NSU_AOX_LOPOW_W__W                                              2
4542 #define ORX_NSU_AOX_LOPOW_W__M                                              0x3
4543 #define ORX_NSU_AOX_LOPOW_W__PRE                                            0x0
4544 #define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB                                0x0
4545 #define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB                                0x1
4546 #define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB                               0x2
4547 #define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB                               0x3
4548 
4549 #define ORX_NSU_AOX_STHR_W__A                                               0x2060014
4550 #define ORX_NSU_AOX_STHR_W__W                                               5
4551 #define ORX_NSU_AOX_STHR_W__M                                               0x1F
4552 #define ORX_NSU_AOX_STHR_W__PRE                                             0x0
4553 
4554 #define ORX_NSU_TUN_RFGAIN_W__A                                             0x2060015
4555 #define ORX_NSU_TUN_RFGAIN_W__W                                             15
4556 #define ORX_NSU_TUN_RFGAIN_W__M                                             0x7FFF
4557 #define ORX_NSU_TUN_RFGAIN_W__PRE                                           0x0
4558 
4559 #define ORX_NSU_TUN_IFGAIN_W__A                                             0x2060016
4560 #define ORX_NSU_TUN_IFGAIN_W__W                                             15
4561 #define ORX_NSU_TUN_IFGAIN_W__M                                             0x7FFF
4562 #define ORX_NSU_TUN_IFGAIN_W__PRE                                           0x0
4563 
4564 #define ORX_NSU_TUN_BPF_W__A                                                0x2060017
4565 #define ORX_NSU_TUN_BPF_W__W                                                15
4566 #define ORX_NSU_TUN_BPF_W__M                                                0x7FFF
4567 #define ORX_NSU_TUN_BPF_W__PRE                                              0x1F9
4568 #define ORX_NSU_NSS_BITSWAP_W__A                                            0x2060018
4569 #define ORX_NSU_NSS_BITSWAP_W__W                                            3
4570 #define ORX_NSU_NSS_BITSWAP_W__M                                            0x7
4571 #define ORX_NSU_NSS_BITSWAP_W__PRE                                          0x0
4572 
4573 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B                           0
4574 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W                           1
4575 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M                           0x1
4576 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE                         0x0
4577 
4578 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B                           1
4579 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W                           1
4580 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M                           0x2
4581 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE                         0x0
4582 
4583 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B                           2
4584 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W                           1
4585 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M                           0x4
4586 #define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE                         0x0
4587 
4588 #define ORX_TST_COMM_EXEC__A                                                0x23F0000
4589 #define ORX_TST_COMM_EXEC__W                                                2
4590 #define ORX_TST_COMM_EXEC__M                                                0x3
4591 #define ORX_TST_COMM_EXEC__PRE                                              0x0
4592 #define   ORX_TST_COMM_EXEC_STOP                                            0x0
4593 #define   ORX_TST_COMM_EXEC_ACTIVE                                          0x1
4594 #define   ORX_TST_COMM_EXEC_HOLD                                            0x2
4595 
4596 #define ORX_TST_AOX_TST_W__A                                                0x23F0010
4597 #define ORX_TST_AOX_TST_W__W                                                8
4598 #define ORX_TST_AOX_TST_W__M                                                0xFF
4599 #define ORX_TST_AOX_TST_W__PRE                                              0x0
4600 
4601 #define QAM_COMM_EXEC__A                                                    0x1400000
4602 #define QAM_COMM_EXEC__W                                                    2
4603 #define QAM_COMM_EXEC__M                                                    0x3
4604 #define QAM_COMM_EXEC__PRE                                                  0x0
4605 #define   QAM_COMM_EXEC_STOP                                                0x0
4606 #define   QAM_COMM_EXEC_ACTIVE                                              0x1
4607 #define   QAM_COMM_EXEC_HOLD                                                0x2
4608 
4609 #define QAM_COMM_MB__A                                                      0x1400002
4610 #define QAM_COMM_MB__W                                                      16
4611 #define QAM_COMM_MB__M                                                      0xFFFF
4612 #define QAM_COMM_MB__PRE                                                    0x0
4613 #define QAM_COMM_INT_REQ__A                                                 0x1400003
4614 #define QAM_COMM_INT_REQ__W                                                 16
4615 #define QAM_COMM_INT_REQ__M                                                 0xFFFF
4616 #define QAM_COMM_INT_REQ__PRE                                               0x0
4617 
4618 #define   QAM_COMM_INT_REQ_SL_REQ__B                                        0
4619 #define   QAM_COMM_INT_REQ_SL_REQ__W                                        1
4620 #define   QAM_COMM_INT_REQ_SL_REQ__M                                        0x1
4621 #define   QAM_COMM_INT_REQ_SL_REQ__PRE                                      0x0
4622 
4623 #define   QAM_COMM_INT_REQ_LC_REQ__B                                        1
4624 #define   QAM_COMM_INT_REQ_LC_REQ__W                                        1
4625 #define   QAM_COMM_INT_REQ_LC_REQ__M                                        0x2
4626 #define   QAM_COMM_INT_REQ_LC_REQ__PRE                                      0x0
4627 
4628 #define   QAM_COMM_INT_REQ_VD_REQ__B                                        2
4629 #define   QAM_COMM_INT_REQ_VD_REQ__W                                        1
4630 #define   QAM_COMM_INT_REQ_VD_REQ__M                                        0x4
4631 #define   QAM_COMM_INT_REQ_VD_REQ__PRE                                      0x0
4632 
4633 #define   QAM_COMM_INT_REQ_SY_REQ__B                                        3
4634 #define   QAM_COMM_INT_REQ_SY_REQ__W                                        1
4635 #define   QAM_COMM_INT_REQ_SY_REQ__M                                        0x8
4636 #define   QAM_COMM_INT_REQ_SY_REQ__PRE                                      0x0
4637 
4638 #define QAM_COMM_INT_STA__A                                                 0x1400005
4639 #define QAM_COMM_INT_STA__W                                                 16
4640 #define QAM_COMM_INT_STA__M                                                 0xFFFF
4641 #define QAM_COMM_INT_STA__PRE                                               0x0
4642 #define QAM_COMM_INT_MSK__A                                                 0x1400006
4643 #define QAM_COMM_INT_MSK__W                                                 16
4644 #define QAM_COMM_INT_MSK__M                                                 0xFFFF
4645 #define QAM_COMM_INT_MSK__PRE                                               0x0
4646 #define QAM_COMM_INT_STM__A                                                 0x1400007
4647 #define QAM_COMM_INT_STM__W                                                 16
4648 #define QAM_COMM_INT_STM__M                                                 0xFFFF
4649 #define QAM_COMM_INT_STM__PRE                                               0x0
4650 
4651 #define QAM_TOP_COMM_EXEC__A                                                0x1410000
4652 #define QAM_TOP_COMM_EXEC__W                                                2
4653 #define QAM_TOP_COMM_EXEC__M                                                0x3
4654 #define QAM_TOP_COMM_EXEC__PRE                                              0x0
4655 #define   QAM_TOP_COMM_EXEC_STOP                                            0x0
4656 #define   QAM_TOP_COMM_EXEC_ACTIVE                                          0x1
4657 #define   QAM_TOP_COMM_EXEC_HOLD                                            0x2
4658 
4659 #define QAM_TOP_ANNEX__A                                                    0x1410010
4660 #define QAM_TOP_ANNEX__W                                                    2
4661 #define QAM_TOP_ANNEX__M                                                    0x3
4662 #define QAM_TOP_ANNEX__PRE                                                  0x1
4663 #define   QAM_TOP_ANNEX_A                                                   0x0
4664 #define   QAM_TOP_ANNEX_B                                                   0x1
4665 #define   QAM_TOP_ANNEX_C                                                   0x2
4666 #define   QAM_TOP_ANNEX_D                                                   0x3
4667 
4668 #define QAM_TOP_CONSTELLATION__A                                            0x1410011
4669 #define QAM_TOP_CONSTELLATION__W                                            3
4670 #define QAM_TOP_CONSTELLATION__M                                            0x7
4671 #define QAM_TOP_CONSTELLATION__PRE                                          0x5
4672 #define   QAM_TOP_CONSTELLATION_NONE                                        0x0
4673 #define   QAM_TOP_CONSTELLATION_QPSK                                        0x1
4674 #define   QAM_TOP_CONSTELLATION_QAM8                                        0x2
4675 #define   QAM_TOP_CONSTELLATION_QAM16                                       0x3
4676 #define   QAM_TOP_CONSTELLATION_QAM32                                       0x4
4677 #define   QAM_TOP_CONSTELLATION_QAM64                                       0x5
4678 #define   QAM_TOP_CONSTELLATION_QAM128                                      0x6
4679 #define   QAM_TOP_CONSTELLATION_QAM256                                      0x7
4680 
4681 #define QAM_FQ_COMM_EXEC__A                                                 0x1420000
4682 #define QAM_FQ_COMM_EXEC__W                                                 2
4683 #define QAM_FQ_COMM_EXEC__M                                                 0x3
4684 #define QAM_FQ_COMM_EXEC__PRE                                               0x0
4685 #define   QAM_FQ_COMM_EXEC_STOP                                             0x0
4686 #define   QAM_FQ_COMM_EXEC_ACTIVE                                           0x1
4687 #define   QAM_FQ_COMM_EXEC_HOLD                                             0x2
4688 
4689 #define QAM_FQ_MODE__A                                                      0x1420010
4690 #define QAM_FQ_MODE__W                                                      3
4691 #define QAM_FQ_MODE__M                                                      0x7
4692 #define QAM_FQ_MODE__PRE                                                    0x0
4693 
4694 #define   QAM_FQ_MODE_TAPRESET__B                                           0
4695 #define   QAM_FQ_MODE_TAPRESET__W                                           1
4696 #define   QAM_FQ_MODE_TAPRESET__M                                           0x1
4697 #define   QAM_FQ_MODE_TAPRESET__PRE                                         0x0
4698 #define     QAM_FQ_MODE_TAPRESET_RST                                        0x1
4699 
4700 #define   QAM_FQ_MODE_TAPLMS__B                                             1
4701 #define   QAM_FQ_MODE_TAPLMS__W                                             1
4702 #define   QAM_FQ_MODE_TAPLMS__M                                             0x2
4703 #define   QAM_FQ_MODE_TAPLMS__PRE                                           0x0
4704 #define     QAM_FQ_MODE_TAPLMS_UPD                                          0x2
4705 
4706 #define   QAM_FQ_MODE_TAPDRAIN__B                                           2
4707 #define   QAM_FQ_MODE_TAPDRAIN__W                                           1
4708 #define   QAM_FQ_MODE_TAPDRAIN__M                                           0x4
4709 #define   QAM_FQ_MODE_TAPDRAIN__PRE                                         0x0
4710 #define     QAM_FQ_MODE_TAPDRAIN_DRAIN                                      0x4
4711 
4712 #define QAM_FQ_MU_FACTOR__A                                                 0x1420011
4713 #define QAM_FQ_MU_FACTOR__W                                                 3
4714 #define QAM_FQ_MU_FACTOR__M                                                 0x7
4715 #define QAM_FQ_MU_FACTOR__PRE                                               0x0
4716 
4717 #define QAM_FQ_LA_FACTOR__A                                                 0x1420012
4718 #define QAM_FQ_LA_FACTOR__W                                                 4
4719 #define QAM_FQ_LA_FACTOR__M                                                 0xF
4720 #define QAM_FQ_LA_FACTOR__PRE                                               0xC
4721 #define QAM_FQ_CENTTAP_IDX__A                                               0x1420016
4722 #define QAM_FQ_CENTTAP_IDX__W                                               5
4723 #define QAM_FQ_CENTTAP_IDX__M                                               0x1F
4724 #define QAM_FQ_CENTTAP_IDX__PRE                                             0x13
4725 
4726 #define   QAM_FQ_CENTTAP_IDX_IDX__B                                         0
4727 #define   QAM_FQ_CENTTAP_IDX_IDX__W                                         5
4728 #define   QAM_FQ_CENTTAP_IDX_IDX__M                                         0x1F
4729 #define   QAM_FQ_CENTTAP_IDX_IDX__PRE                                       0x13
4730 
4731 #define QAM_FQ_CENTTAP_VALUE__A                                             0x1420017
4732 #define QAM_FQ_CENTTAP_VALUE__W                                             12
4733 #define QAM_FQ_CENTTAP_VALUE__M                                             0xFFF
4734 #define QAM_FQ_CENTTAP_VALUE__PRE                                           0x600
4735 
4736 #define   QAM_FQ_CENTTAP_VALUE_TAP__B                                       0
4737 #define   QAM_FQ_CENTTAP_VALUE_TAP__W                                       12
4738 #define   QAM_FQ_CENTTAP_VALUE_TAP__M                                       0xFFF
4739 #define   QAM_FQ_CENTTAP_VALUE_TAP__PRE                                     0x600
4740 
4741 #define QAM_FQ_TAP_RE_EL0__A                                                0x1420020
4742 #define QAM_FQ_TAP_RE_EL0__W                                                12
4743 #define QAM_FQ_TAP_RE_EL0__M                                                0xFFF
4744 #define QAM_FQ_TAP_RE_EL0__PRE                                              0x2
4745 
4746 #define   QAM_FQ_TAP_RE_EL0_TAP__B                                          0
4747 #define   QAM_FQ_TAP_RE_EL0_TAP__W                                          12
4748 #define   QAM_FQ_TAP_RE_EL0_TAP__M                                          0xFFF
4749 #define   QAM_FQ_TAP_RE_EL0_TAP__PRE                                        0x2
4750 
4751 #define QAM_FQ_TAP_IM_EL0__A                                                0x1420021
4752 #define QAM_FQ_TAP_IM_EL0__W                                                12
4753 #define QAM_FQ_TAP_IM_EL0__M                                                0xFFF
4754 #define QAM_FQ_TAP_IM_EL0__PRE                                              0x2
4755 
4756 #define   QAM_FQ_TAP_IM_EL0_TAP__B                                          0
4757 #define   QAM_FQ_TAP_IM_EL0_TAP__W                                          12
4758 #define   QAM_FQ_TAP_IM_EL0_TAP__M                                          0xFFF
4759 #define   QAM_FQ_TAP_IM_EL0_TAP__PRE                                        0x2
4760 
4761 #define QAM_FQ_TAP_RE_EL1__A                                                0x1420022
4762 #define QAM_FQ_TAP_RE_EL1__W                                                12
4763 #define QAM_FQ_TAP_RE_EL1__M                                                0xFFF
4764 #define QAM_FQ_TAP_RE_EL1__PRE                                              0x2
4765 
4766 #define   QAM_FQ_TAP_RE_EL1_TAP__B                                          0
4767 #define   QAM_FQ_TAP_RE_EL1_TAP__W                                          12
4768 #define   QAM_FQ_TAP_RE_EL1_TAP__M                                          0xFFF
4769 #define   QAM_FQ_TAP_RE_EL1_TAP__PRE                                        0x2
4770 
4771 #define QAM_FQ_TAP_IM_EL1__A                                                0x1420023
4772 #define QAM_FQ_TAP_IM_EL1__W                                                12
4773 #define QAM_FQ_TAP_IM_EL1__M                                                0xFFF
4774 #define QAM_FQ_TAP_IM_EL1__PRE                                              0x2
4775 
4776 #define   QAM_FQ_TAP_IM_EL1_TAP__B                                          0
4777 #define   QAM_FQ_TAP_IM_EL1_TAP__W                                          12
4778 #define   QAM_FQ_TAP_IM_EL1_TAP__M                                          0xFFF
4779 #define   QAM_FQ_TAP_IM_EL1_TAP__PRE                                        0x2
4780 
4781 #define QAM_FQ_TAP_RE_EL2__A                                                0x1420024
4782 #define QAM_FQ_TAP_RE_EL2__W                                                12
4783 #define QAM_FQ_TAP_RE_EL2__M                                                0xFFF
4784 #define QAM_FQ_TAP_RE_EL2__PRE                                              0x2
4785 
4786 #define   QAM_FQ_TAP_RE_EL2_TAP__B                                          0
4787 #define   QAM_FQ_TAP_RE_EL2_TAP__W                                          12
4788 #define   QAM_FQ_TAP_RE_EL2_TAP__M                                          0xFFF
4789 #define   QAM_FQ_TAP_RE_EL2_TAP__PRE                                        0x2
4790 
4791 #define QAM_FQ_TAP_IM_EL2__A                                                0x1420025
4792 #define QAM_FQ_TAP_IM_EL2__W                                                12
4793 #define QAM_FQ_TAP_IM_EL2__M                                                0xFFF
4794 #define QAM_FQ_TAP_IM_EL2__PRE                                              0x2
4795 
4796 #define   QAM_FQ_TAP_IM_EL2_TAP__B                                          0
4797 #define   QAM_FQ_TAP_IM_EL2_TAP__W                                          12
4798 #define   QAM_FQ_TAP_IM_EL2_TAP__M                                          0xFFF
4799 #define   QAM_FQ_TAP_IM_EL2_TAP__PRE                                        0x2
4800 
4801 #define QAM_FQ_TAP_RE_EL3__A                                                0x1420026
4802 #define QAM_FQ_TAP_RE_EL3__W                                                12
4803 #define QAM_FQ_TAP_RE_EL3__M                                                0xFFF
4804 #define QAM_FQ_TAP_RE_EL3__PRE                                              0x2
4805 
4806 #define   QAM_FQ_TAP_RE_EL3_TAP__B                                          0
4807 #define   QAM_FQ_TAP_RE_EL3_TAP__W                                          12
4808 #define   QAM_FQ_TAP_RE_EL3_TAP__M                                          0xFFF
4809 #define   QAM_FQ_TAP_RE_EL3_TAP__PRE                                        0x2
4810 
4811 #define QAM_FQ_TAP_IM_EL3__A                                                0x1420027
4812 #define QAM_FQ_TAP_IM_EL3__W                                                12
4813 #define QAM_FQ_TAP_IM_EL3__M                                                0xFFF
4814 #define QAM_FQ_TAP_IM_EL3__PRE                                              0x2
4815 
4816 #define   QAM_FQ_TAP_IM_EL3_TAP__B                                          0
4817 #define   QAM_FQ_TAP_IM_EL3_TAP__W                                          12
4818 #define   QAM_FQ_TAP_IM_EL3_TAP__M                                          0xFFF
4819 #define   QAM_FQ_TAP_IM_EL3_TAP__PRE                                        0x2
4820 
4821 #define QAM_FQ_TAP_RE_EL4__A                                                0x1420028
4822 #define QAM_FQ_TAP_RE_EL4__W                                                12
4823 #define QAM_FQ_TAP_RE_EL4__M                                                0xFFF
4824 #define QAM_FQ_TAP_RE_EL4__PRE                                              0x2
4825 
4826 #define   QAM_FQ_TAP_RE_EL4_TAP__B                                          0
4827 #define   QAM_FQ_TAP_RE_EL4_TAP__W                                          12
4828 #define   QAM_FQ_TAP_RE_EL4_TAP__M                                          0xFFF
4829 #define   QAM_FQ_TAP_RE_EL4_TAP__PRE                                        0x2
4830 
4831 #define QAM_FQ_TAP_IM_EL4__A                                                0x1420029
4832 #define QAM_FQ_TAP_IM_EL4__W                                                12
4833 #define QAM_FQ_TAP_IM_EL4__M                                                0xFFF
4834 #define QAM_FQ_TAP_IM_EL4__PRE                                              0x2
4835 
4836 #define   QAM_FQ_TAP_IM_EL4_TAP__B                                          0
4837 #define   QAM_FQ_TAP_IM_EL4_TAP__W                                          12
4838 #define   QAM_FQ_TAP_IM_EL4_TAP__M                                          0xFFF
4839 #define   QAM_FQ_TAP_IM_EL4_TAP__PRE                                        0x2
4840 
4841 #define QAM_FQ_TAP_RE_EL5__A                                                0x142002A
4842 #define QAM_FQ_TAP_RE_EL5__W                                                12
4843 #define QAM_FQ_TAP_RE_EL5__M                                                0xFFF
4844 #define QAM_FQ_TAP_RE_EL5__PRE                                              0x2
4845 
4846 #define   QAM_FQ_TAP_RE_EL5_TAP__B                                          0
4847 #define   QAM_FQ_TAP_RE_EL5_TAP__W                                          12
4848 #define   QAM_FQ_TAP_RE_EL5_TAP__M                                          0xFFF
4849 #define   QAM_FQ_TAP_RE_EL5_TAP__PRE                                        0x2
4850 
4851 #define QAM_FQ_TAP_IM_EL5__A                                                0x142002B
4852 #define QAM_FQ_TAP_IM_EL5__W                                                12
4853 #define QAM_FQ_TAP_IM_EL5__M                                                0xFFF
4854 #define QAM_FQ_TAP_IM_EL5__PRE                                              0x2
4855 
4856 #define   QAM_FQ_TAP_IM_EL5_TAP__B                                          0
4857 #define   QAM_FQ_TAP_IM_EL5_TAP__W                                          12
4858 #define   QAM_FQ_TAP_IM_EL5_TAP__M                                          0xFFF
4859 #define   QAM_FQ_TAP_IM_EL5_TAP__PRE                                        0x2
4860 
4861 #define QAM_FQ_TAP_RE_EL6__A                                                0x142002C
4862 #define QAM_FQ_TAP_RE_EL6__W                                                12
4863 #define QAM_FQ_TAP_RE_EL6__M                                                0xFFF
4864 #define QAM_FQ_TAP_RE_EL6__PRE                                              0x2
4865 
4866 #define   QAM_FQ_TAP_RE_EL6_TAP__B                                          0
4867 #define   QAM_FQ_TAP_RE_EL6_TAP__W                                          12
4868 #define   QAM_FQ_TAP_RE_EL6_TAP__M                                          0xFFF
4869 #define   QAM_FQ_TAP_RE_EL6_TAP__PRE                                        0x2
4870 
4871 #define QAM_FQ_TAP_IM_EL6__A                                                0x142002D
4872 #define QAM_FQ_TAP_IM_EL6__W                                                12
4873 #define QAM_FQ_TAP_IM_EL6__M                                                0xFFF
4874 #define QAM_FQ_TAP_IM_EL6__PRE                                              0x2
4875 
4876 #define   QAM_FQ_TAP_IM_EL6_TAP__B                                          0
4877 #define   QAM_FQ_TAP_IM_EL6_TAP__W                                          12
4878 #define   QAM_FQ_TAP_IM_EL6_TAP__M                                          0xFFF
4879 #define   QAM_FQ_TAP_IM_EL6_TAP__PRE                                        0x2
4880 
4881 #define QAM_FQ_TAP_RE_EL7__A                                                0x142002E
4882 #define QAM_FQ_TAP_RE_EL7__W                                                12
4883 #define QAM_FQ_TAP_RE_EL7__M                                                0xFFF
4884 #define QAM_FQ_TAP_RE_EL7__PRE                                              0x2
4885 
4886 #define   QAM_FQ_TAP_RE_EL7_TAP__B                                          0
4887 #define   QAM_FQ_TAP_RE_EL7_TAP__W                                          12
4888 #define   QAM_FQ_TAP_RE_EL7_TAP__M                                          0xFFF
4889 #define   QAM_FQ_TAP_RE_EL7_TAP__PRE                                        0x2
4890 
4891 #define QAM_FQ_TAP_IM_EL7__A                                                0x142002F
4892 #define QAM_FQ_TAP_IM_EL7__W                                                12
4893 #define QAM_FQ_TAP_IM_EL7__M                                                0xFFF
4894 #define QAM_FQ_TAP_IM_EL7__PRE                                              0x2
4895 
4896 #define   QAM_FQ_TAP_IM_EL7_TAP__B                                          0
4897 #define   QAM_FQ_TAP_IM_EL7_TAP__W                                          12
4898 #define   QAM_FQ_TAP_IM_EL7_TAP__M                                          0xFFF
4899 #define   QAM_FQ_TAP_IM_EL7_TAP__PRE                                        0x2
4900 
4901 #define QAM_FQ_TAP_RE_EL8__A                                                0x1420030
4902 #define QAM_FQ_TAP_RE_EL8__W                                                12
4903 #define QAM_FQ_TAP_RE_EL8__M                                                0xFFF
4904 #define QAM_FQ_TAP_RE_EL8__PRE                                              0x2
4905 
4906 #define   QAM_FQ_TAP_RE_EL8_TAP__B                                          0
4907 #define   QAM_FQ_TAP_RE_EL8_TAP__W                                          12
4908 #define   QAM_FQ_TAP_RE_EL8_TAP__M                                          0xFFF
4909 #define   QAM_FQ_TAP_RE_EL8_TAP__PRE                                        0x2
4910 
4911 #define QAM_FQ_TAP_IM_EL8__A                                                0x1420031
4912 #define QAM_FQ_TAP_IM_EL8__W                                                12
4913 #define QAM_FQ_TAP_IM_EL8__M                                                0xFFF
4914 #define QAM_FQ_TAP_IM_EL8__PRE                                              0x2
4915 
4916 #define   QAM_FQ_TAP_IM_EL8_TAP__B                                          0
4917 #define   QAM_FQ_TAP_IM_EL8_TAP__W                                          12
4918 #define   QAM_FQ_TAP_IM_EL8_TAP__M                                          0xFFF
4919 #define   QAM_FQ_TAP_IM_EL8_TAP__PRE                                        0x2
4920 
4921 #define QAM_FQ_TAP_RE_EL9__A                                                0x1420032
4922 #define QAM_FQ_TAP_RE_EL9__W                                                12
4923 #define QAM_FQ_TAP_RE_EL9__M                                                0xFFF
4924 #define QAM_FQ_TAP_RE_EL9__PRE                                              0x2
4925 
4926 #define   QAM_FQ_TAP_RE_EL9_TAP__B                                          0
4927 #define   QAM_FQ_TAP_RE_EL9_TAP__W                                          12
4928 #define   QAM_FQ_TAP_RE_EL9_TAP__M                                          0xFFF
4929 #define   QAM_FQ_TAP_RE_EL9_TAP__PRE                                        0x2
4930 
4931 #define QAM_FQ_TAP_IM_EL9__A                                                0x1420033
4932 #define QAM_FQ_TAP_IM_EL9__W                                                12
4933 #define QAM_FQ_TAP_IM_EL9__M                                                0xFFF
4934 #define QAM_FQ_TAP_IM_EL9__PRE                                              0x2
4935 
4936 #define   QAM_FQ_TAP_IM_EL9_TAP__B                                          0
4937 #define   QAM_FQ_TAP_IM_EL9_TAP__W                                          12
4938 #define   QAM_FQ_TAP_IM_EL9_TAP__M                                          0xFFF
4939 #define   QAM_FQ_TAP_IM_EL9_TAP__PRE                                        0x2
4940 
4941 #define QAM_FQ_TAP_RE_EL10__A                                               0x1420034
4942 #define QAM_FQ_TAP_RE_EL10__W                                               12
4943 #define QAM_FQ_TAP_RE_EL10__M                                               0xFFF
4944 #define QAM_FQ_TAP_RE_EL10__PRE                                             0x2
4945 
4946 #define   QAM_FQ_TAP_RE_EL10_TAP__B                                         0
4947 #define   QAM_FQ_TAP_RE_EL10_TAP__W                                         12
4948 #define   QAM_FQ_TAP_RE_EL10_TAP__M                                         0xFFF
4949 #define   QAM_FQ_TAP_RE_EL10_TAP__PRE                                       0x2
4950 
4951 #define QAM_FQ_TAP_IM_EL10__A                                               0x1420035
4952 #define QAM_FQ_TAP_IM_EL10__W                                               12
4953 #define QAM_FQ_TAP_IM_EL10__M                                               0xFFF
4954 #define QAM_FQ_TAP_IM_EL10__PRE                                             0x2
4955 
4956 #define   QAM_FQ_TAP_IM_EL10_TAP__B                                         0
4957 #define   QAM_FQ_TAP_IM_EL10_TAP__W                                         12
4958 #define   QAM_FQ_TAP_IM_EL10_TAP__M                                         0xFFF
4959 #define   QAM_FQ_TAP_IM_EL10_TAP__PRE                                       0x2
4960 
4961 #define QAM_FQ_TAP_RE_EL11__A                                               0x1420036
4962 #define QAM_FQ_TAP_RE_EL11__W                                               12
4963 #define QAM_FQ_TAP_RE_EL11__M                                               0xFFF
4964 #define QAM_FQ_TAP_RE_EL11__PRE                                             0x2
4965 
4966 #define   QAM_FQ_TAP_RE_EL11_TAP__B                                         0
4967 #define   QAM_FQ_TAP_RE_EL11_TAP__W                                         12
4968 #define   QAM_FQ_TAP_RE_EL11_TAP__M                                         0xFFF
4969 #define   QAM_FQ_TAP_RE_EL11_TAP__PRE                                       0x2
4970 
4971 #define QAM_FQ_TAP_IM_EL11__A                                               0x1420037
4972 #define QAM_FQ_TAP_IM_EL11__W                                               12
4973 #define QAM_FQ_TAP_IM_EL11__M                                               0xFFF
4974 #define QAM_FQ_TAP_IM_EL11__PRE                                             0x2
4975 
4976 #define   QAM_FQ_TAP_IM_EL11_TAP__B                                         0
4977 #define   QAM_FQ_TAP_IM_EL11_TAP__W                                         12
4978 #define   QAM_FQ_TAP_IM_EL11_TAP__M                                         0xFFF
4979 #define   QAM_FQ_TAP_IM_EL11_TAP__PRE                                       0x2
4980 
4981 #define QAM_FQ_TAP_RE_EL12__A                                               0x1420038
4982 #define QAM_FQ_TAP_RE_EL12__W                                               12
4983 #define QAM_FQ_TAP_RE_EL12__M                                               0xFFF
4984 #define QAM_FQ_TAP_RE_EL12__PRE                                             0x2
4985 
4986 #define   QAM_FQ_TAP_RE_EL12_TAP__B                                         0
4987 #define   QAM_FQ_TAP_RE_EL12_TAP__W                                         12
4988 #define   QAM_FQ_TAP_RE_EL12_TAP__M                                         0xFFF
4989 #define   QAM_FQ_TAP_RE_EL12_TAP__PRE                                       0x2
4990 
4991 #define QAM_FQ_TAP_IM_EL12__A                                               0x1420039
4992 #define QAM_FQ_TAP_IM_EL12__W                                               12
4993 #define QAM_FQ_TAP_IM_EL12__M                                               0xFFF
4994 #define QAM_FQ_TAP_IM_EL12__PRE                                             0x2
4995 
4996 #define   QAM_FQ_TAP_IM_EL12_TAP__B                                         0
4997 #define   QAM_FQ_TAP_IM_EL12_TAP__W                                         12
4998 #define   QAM_FQ_TAP_IM_EL12_TAP__M                                         0xFFF
4999 #define   QAM_FQ_TAP_IM_EL12_TAP__PRE                                       0x2
5000 
5001 #define QAM_FQ_TAP_RE_EL13__A                                               0x142003A
5002 #define QAM_FQ_TAP_RE_EL13__W                                               12
5003 #define QAM_FQ_TAP_RE_EL13__M                                               0xFFF
5004 #define QAM_FQ_TAP_RE_EL13__PRE                                             0x2
5005 
5006 #define   QAM_FQ_TAP_RE_EL13_TAP__B                                         0
5007 #define   QAM_FQ_TAP_RE_EL13_TAP__W                                         12
5008 #define   QAM_FQ_TAP_RE_EL13_TAP__M                                         0xFFF
5009 #define   QAM_FQ_TAP_RE_EL13_TAP__PRE                                       0x2
5010 
5011 #define QAM_FQ_TAP_IM_EL13__A                                               0x142003B
5012 #define QAM_FQ_TAP_IM_EL13__W                                               12
5013 #define QAM_FQ_TAP_IM_EL13__M                                               0xFFF
5014 #define QAM_FQ_TAP_IM_EL13__PRE                                             0x2
5015 
5016 #define   QAM_FQ_TAP_IM_EL13_TAP__B                                         0
5017 #define   QAM_FQ_TAP_IM_EL13_TAP__W                                         12
5018 #define   QAM_FQ_TAP_IM_EL13_TAP__M                                         0xFFF
5019 #define   QAM_FQ_TAP_IM_EL13_TAP__PRE                                       0x2
5020 
5021 #define QAM_FQ_TAP_RE_EL14__A                                               0x142003C
5022 #define QAM_FQ_TAP_RE_EL14__W                                               12
5023 #define QAM_FQ_TAP_RE_EL14__M                                               0xFFF
5024 #define QAM_FQ_TAP_RE_EL14__PRE                                             0x2
5025 
5026 #define   QAM_FQ_TAP_RE_EL14_TAP__B                                         0
5027 #define   QAM_FQ_TAP_RE_EL14_TAP__W                                         12
5028 #define   QAM_FQ_TAP_RE_EL14_TAP__M                                         0xFFF
5029 #define   QAM_FQ_TAP_RE_EL14_TAP__PRE                                       0x2
5030 
5031 #define QAM_FQ_TAP_IM_EL14__A                                               0x142003D
5032 #define QAM_FQ_TAP_IM_EL14__W                                               12
5033 #define QAM_FQ_TAP_IM_EL14__M                                               0xFFF
5034 #define QAM_FQ_TAP_IM_EL14__PRE                                             0x2
5035 
5036 #define   QAM_FQ_TAP_IM_EL14_TAP__B                                         0
5037 #define   QAM_FQ_TAP_IM_EL14_TAP__W                                         12
5038 #define   QAM_FQ_TAP_IM_EL14_TAP__M                                         0xFFF
5039 #define   QAM_FQ_TAP_IM_EL14_TAP__PRE                                       0x2
5040 
5041 #define QAM_FQ_TAP_RE_EL15__A                                               0x142003E
5042 #define QAM_FQ_TAP_RE_EL15__W                                               12
5043 #define QAM_FQ_TAP_RE_EL15__M                                               0xFFF
5044 #define QAM_FQ_TAP_RE_EL15__PRE                                             0x2
5045 
5046 #define   QAM_FQ_TAP_RE_EL15_TAP__B                                         0
5047 #define   QAM_FQ_TAP_RE_EL15_TAP__W                                         12
5048 #define   QAM_FQ_TAP_RE_EL15_TAP__M                                         0xFFF
5049 #define   QAM_FQ_TAP_RE_EL15_TAP__PRE                                       0x2
5050 
5051 #define QAM_FQ_TAP_IM_EL15__A                                               0x142003F
5052 #define QAM_FQ_TAP_IM_EL15__W                                               12
5053 #define QAM_FQ_TAP_IM_EL15__M                                               0xFFF
5054 #define QAM_FQ_TAP_IM_EL15__PRE                                             0x2
5055 
5056 #define   QAM_FQ_TAP_IM_EL15_TAP__B                                         0
5057 #define   QAM_FQ_TAP_IM_EL15_TAP__W                                         12
5058 #define   QAM_FQ_TAP_IM_EL15_TAP__M                                         0xFFF
5059 #define   QAM_FQ_TAP_IM_EL15_TAP__PRE                                       0x2
5060 
5061 #define QAM_FQ_TAP_RE_EL16__A                                               0x1420040
5062 #define QAM_FQ_TAP_RE_EL16__W                                               12
5063 #define QAM_FQ_TAP_RE_EL16__M                                               0xFFF
5064 #define QAM_FQ_TAP_RE_EL16__PRE                                             0x2
5065 
5066 #define   QAM_FQ_TAP_RE_EL16_TAP__B                                         0
5067 #define   QAM_FQ_TAP_RE_EL16_TAP__W                                         12
5068 #define   QAM_FQ_TAP_RE_EL16_TAP__M                                         0xFFF
5069 #define   QAM_FQ_TAP_RE_EL16_TAP__PRE                                       0x2
5070 
5071 #define QAM_FQ_TAP_IM_EL16__A                                               0x1420041
5072 #define QAM_FQ_TAP_IM_EL16__W                                               12
5073 #define QAM_FQ_TAP_IM_EL16__M                                               0xFFF
5074 #define QAM_FQ_TAP_IM_EL16__PRE                                             0x2
5075 
5076 #define   QAM_FQ_TAP_IM_EL16_TAP__B                                         0
5077 #define   QAM_FQ_TAP_IM_EL16_TAP__W                                         12
5078 #define   QAM_FQ_TAP_IM_EL16_TAP__M                                         0xFFF
5079 #define   QAM_FQ_TAP_IM_EL16_TAP__PRE                                       0x2
5080 
5081 #define QAM_FQ_TAP_RE_EL17__A                                               0x1420042
5082 #define QAM_FQ_TAP_RE_EL17__W                                               12
5083 #define QAM_FQ_TAP_RE_EL17__M                                               0xFFF
5084 #define QAM_FQ_TAP_RE_EL17__PRE                                             0x2
5085 
5086 #define   QAM_FQ_TAP_RE_EL17_TAP__B                                         0
5087 #define   QAM_FQ_TAP_RE_EL17_TAP__W                                         12
5088 #define   QAM_FQ_TAP_RE_EL17_TAP__M                                         0xFFF
5089 #define   QAM_FQ_TAP_RE_EL17_TAP__PRE                                       0x2
5090 
5091 #define QAM_FQ_TAP_IM_EL17__A                                               0x1420043
5092 #define QAM_FQ_TAP_IM_EL17__W                                               12
5093 #define QAM_FQ_TAP_IM_EL17__M                                               0xFFF
5094 #define QAM_FQ_TAP_IM_EL17__PRE                                             0x2
5095 
5096 #define   QAM_FQ_TAP_IM_EL17_TAP__B                                         0
5097 #define   QAM_FQ_TAP_IM_EL17_TAP__W                                         12
5098 #define   QAM_FQ_TAP_IM_EL17_TAP__M                                         0xFFF
5099 #define   QAM_FQ_TAP_IM_EL17_TAP__PRE                                       0x2
5100 
5101 #define QAM_FQ_TAP_RE_EL18__A                                               0x1420044
5102 #define QAM_FQ_TAP_RE_EL18__W                                               12
5103 #define QAM_FQ_TAP_RE_EL18__M                                               0xFFF
5104 #define QAM_FQ_TAP_RE_EL18__PRE                                             0x2
5105 
5106 #define   QAM_FQ_TAP_RE_EL18_TAP__B                                         0
5107 #define   QAM_FQ_TAP_RE_EL18_TAP__W                                         12
5108 #define   QAM_FQ_TAP_RE_EL18_TAP__M                                         0xFFF
5109 #define   QAM_FQ_TAP_RE_EL18_TAP__PRE                                       0x2
5110 
5111 #define QAM_FQ_TAP_IM_EL18__A                                               0x1420045
5112 #define QAM_FQ_TAP_IM_EL18__W                                               12
5113 #define QAM_FQ_TAP_IM_EL18__M                                               0xFFF
5114 #define QAM_FQ_TAP_IM_EL18__PRE                                             0x2
5115 
5116 #define   QAM_FQ_TAP_IM_EL18_TAP__B                                         0
5117 #define   QAM_FQ_TAP_IM_EL18_TAP__W                                         12
5118 #define   QAM_FQ_TAP_IM_EL18_TAP__M                                         0xFFF
5119 #define   QAM_FQ_TAP_IM_EL18_TAP__PRE                                       0x2
5120 
5121 #define QAM_FQ_TAP_RE_EL19__A                                               0x1420046
5122 #define QAM_FQ_TAP_RE_EL19__W                                               12
5123 #define QAM_FQ_TAP_RE_EL19__M                                               0xFFF
5124 #define QAM_FQ_TAP_RE_EL19__PRE                                             0x600
5125 
5126 #define   QAM_FQ_TAP_RE_EL19_TAP__B                                         0
5127 #define   QAM_FQ_TAP_RE_EL19_TAP__W                                         12
5128 #define   QAM_FQ_TAP_RE_EL19_TAP__M                                         0xFFF
5129 #define   QAM_FQ_TAP_RE_EL19_TAP__PRE                                       0x600
5130 
5131 #define QAM_FQ_TAP_IM_EL19__A                                               0x1420047
5132 #define QAM_FQ_TAP_IM_EL19__W                                               12
5133 #define QAM_FQ_TAP_IM_EL19__M                                               0xFFF
5134 #define QAM_FQ_TAP_IM_EL19__PRE                                             0x2
5135 
5136 #define   QAM_FQ_TAP_IM_EL19_TAP__B                                         0
5137 #define   QAM_FQ_TAP_IM_EL19_TAP__W                                         12
5138 #define   QAM_FQ_TAP_IM_EL19_TAP__M                                         0xFFF
5139 #define   QAM_FQ_TAP_IM_EL19_TAP__PRE                                       0x2
5140 
5141 #define QAM_FQ_TAP_RE_EL20__A                                               0x1420048
5142 #define QAM_FQ_TAP_RE_EL20__W                                               12
5143 #define QAM_FQ_TAP_RE_EL20__M                                               0xFFF
5144 #define QAM_FQ_TAP_RE_EL20__PRE                                             0x2
5145 
5146 #define   QAM_FQ_TAP_RE_EL20_TAP__B                                         0
5147 #define   QAM_FQ_TAP_RE_EL20_TAP__W                                         12
5148 #define   QAM_FQ_TAP_RE_EL20_TAP__M                                         0xFFF
5149 #define   QAM_FQ_TAP_RE_EL20_TAP__PRE                                       0x2
5150 
5151 #define QAM_FQ_TAP_IM_EL20__A                                               0x1420049
5152 #define QAM_FQ_TAP_IM_EL20__W                                               12
5153 #define QAM_FQ_TAP_IM_EL20__M                                               0xFFF
5154 #define QAM_FQ_TAP_IM_EL20__PRE                                             0x2
5155 
5156 #define   QAM_FQ_TAP_IM_EL20_TAP__B                                         0
5157 #define   QAM_FQ_TAP_IM_EL20_TAP__W                                         12
5158 #define   QAM_FQ_TAP_IM_EL20_TAP__M                                         0xFFF
5159 #define   QAM_FQ_TAP_IM_EL20_TAP__PRE                                       0x2
5160 
5161 #define QAM_FQ_TAP_RE_EL21__A                                               0x142004A
5162 #define QAM_FQ_TAP_RE_EL21__W                                               12
5163 #define QAM_FQ_TAP_RE_EL21__M                                               0xFFF
5164 #define QAM_FQ_TAP_RE_EL21__PRE                                             0x2
5165 
5166 #define   QAM_FQ_TAP_RE_EL21_TAP__B                                         0
5167 #define   QAM_FQ_TAP_RE_EL21_TAP__W                                         12
5168 #define   QAM_FQ_TAP_RE_EL21_TAP__M                                         0xFFF
5169 #define   QAM_FQ_TAP_RE_EL21_TAP__PRE                                       0x2
5170 
5171 #define QAM_FQ_TAP_IM_EL21__A                                               0x142004B
5172 #define QAM_FQ_TAP_IM_EL21__W                                               12
5173 #define QAM_FQ_TAP_IM_EL21__M                                               0xFFF
5174 #define QAM_FQ_TAP_IM_EL21__PRE                                             0x2
5175 
5176 #define   QAM_FQ_TAP_IM_EL21_TAP__B                                         0
5177 #define   QAM_FQ_TAP_IM_EL21_TAP__W                                         12
5178 #define   QAM_FQ_TAP_IM_EL21_TAP__M                                         0xFFF
5179 #define   QAM_FQ_TAP_IM_EL21_TAP__PRE                                       0x2
5180 
5181 #define QAM_FQ_TAP_RE_EL22__A                                               0x142004C
5182 #define QAM_FQ_TAP_RE_EL22__W                                               12
5183 #define QAM_FQ_TAP_RE_EL22__M                                               0xFFF
5184 #define QAM_FQ_TAP_RE_EL22__PRE                                             0x2
5185 
5186 #define   QAM_FQ_TAP_RE_EL22_TAP__B                                         0
5187 #define   QAM_FQ_TAP_RE_EL22_TAP__W                                         12
5188 #define   QAM_FQ_TAP_RE_EL22_TAP__M                                         0xFFF
5189 #define   QAM_FQ_TAP_RE_EL22_TAP__PRE                                       0x2
5190 
5191 #define QAM_FQ_TAP_IM_EL22__A                                               0x142004D
5192 #define QAM_FQ_TAP_IM_EL22__W                                               12
5193 #define QAM_FQ_TAP_IM_EL22__M                                               0xFFF
5194 #define QAM_FQ_TAP_IM_EL22__PRE                                             0x2
5195 
5196 #define   QAM_FQ_TAP_IM_EL22_TAP__B                                         0
5197 #define   QAM_FQ_TAP_IM_EL22_TAP__W                                         12
5198 #define   QAM_FQ_TAP_IM_EL22_TAP__M                                         0xFFF
5199 #define   QAM_FQ_TAP_IM_EL22_TAP__PRE                                       0x2
5200 
5201 #define QAM_FQ_TAP_RE_EL23__A                                               0x142004E
5202 #define QAM_FQ_TAP_RE_EL23__W                                               12
5203 #define QAM_FQ_TAP_RE_EL23__M                                               0xFFF
5204 #define QAM_FQ_TAP_RE_EL23__PRE                                             0x2
5205 
5206 #define   QAM_FQ_TAP_RE_EL23_TAP__B                                         0
5207 #define   QAM_FQ_TAP_RE_EL23_TAP__W                                         12
5208 #define   QAM_FQ_TAP_RE_EL23_TAP__M                                         0xFFF
5209 #define   QAM_FQ_TAP_RE_EL23_TAP__PRE                                       0x2
5210 
5211 #define QAM_FQ_TAP_IM_EL23__A                                               0x142004F
5212 #define QAM_FQ_TAP_IM_EL23__W                                               12
5213 #define QAM_FQ_TAP_IM_EL23__M                                               0xFFF
5214 #define QAM_FQ_TAP_IM_EL23__PRE                                             0x2
5215 
5216 #define   QAM_FQ_TAP_IM_EL23_TAP__B                                         0
5217 #define   QAM_FQ_TAP_IM_EL23_TAP__W                                         12
5218 #define   QAM_FQ_TAP_IM_EL23_TAP__M                                         0xFFF
5219 #define   QAM_FQ_TAP_IM_EL23_TAP__PRE                                       0x2
5220 
5221 #define QAM_SL_COMM_EXEC__A                                                 0x1430000
5222 #define QAM_SL_COMM_EXEC__W                                                 2
5223 #define QAM_SL_COMM_EXEC__M                                                 0x3
5224 #define QAM_SL_COMM_EXEC__PRE                                               0x0
5225 #define   QAM_SL_COMM_EXEC_STOP                                             0x0
5226 #define   QAM_SL_COMM_EXEC_ACTIVE                                           0x1
5227 #define   QAM_SL_COMM_EXEC_HOLD                                             0x2
5228 
5229 #define QAM_SL_COMM_MB__A                                                   0x1430002
5230 #define QAM_SL_COMM_MB__W                                                   4
5231 #define QAM_SL_COMM_MB__M                                                   0xF
5232 #define QAM_SL_COMM_MB__PRE                                                 0x0
5233 #define   QAM_SL_COMM_MB_CTL__B                                             0
5234 #define   QAM_SL_COMM_MB_CTL__W                                             1
5235 #define   QAM_SL_COMM_MB_CTL__M                                             0x1
5236 #define   QAM_SL_COMM_MB_CTL__PRE                                           0x0
5237 #define     QAM_SL_COMM_MB_CTL_OFF                                          0x0
5238 #define     QAM_SL_COMM_MB_CTL_ON                                           0x1
5239 #define   QAM_SL_COMM_MB_OBS__B                                             1
5240 #define   QAM_SL_COMM_MB_OBS__W                                             1
5241 #define   QAM_SL_COMM_MB_OBS__M                                             0x2
5242 #define   QAM_SL_COMM_MB_OBS__PRE                                           0x0
5243 #define     QAM_SL_COMM_MB_OBS_OFF                                          0x0
5244 #define     QAM_SL_COMM_MB_OBS_ON                                           0x2
5245 #define   QAM_SL_COMM_MB_MUX_OBS__B                                         2
5246 #define   QAM_SL_COMM_MB_MUX_OBS__W                                         2
5247 #define   QAM_SL_COMM_MB_MUX_OBS__M                                         0xC
5248 #define   QAM_SL_COMM_MB_MUX_OBS__PRE                                       0x0
5249 #define     QAM_SL_COMM_MB_MUX_OBS_CONST_CORR                               0x0
5250 #define     QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O                               0x4
5251 #define     QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O                               0x8
5252 #define     QAM_SL_COMM_MB_MUX_OBS_VDEC_O                                   0xC
5253 
5254 #define QAM_SL_COMM_INT_REQ__A                                              0x1430003
5255 #define QAM_SL_COMM_INT_REQ__W                                              1
5256 #define QAM_SL_COMM_INT_REQ__M                                              0x1
5257 #define QAM_SL_COMM_INT_REQ__PRE                                            0x0
5258 #define QAM_SL_COMM_INT_STA__A                                              0x1430005
5259 #define QAM_SL_COMM_INT_STA__W                                              2
5260 #define QAM_SL_COMM_INT_STA__M                                              0x3
5261 #define QAM_SL_COMM_INT_STA__PRE                                            0x0
5262 
5263 #define   QAM_SL_COMM_INT_STA_MED_ERR_INT__B                                0
5264 #define   QAM_SL_COMM_INT_STA_MED_ERR_INT__W                                1
5265 #define   QAM_SL_COMM_INT_STA_MED_ERR_INT__M                                0x1
5266 #define   QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE                              0x0
5267 
5268 #define   QAM_SL_COMM_INT_STA_MER_INT__B                                    1
5269 #define   QAM_SL_COMM_INT_STA_MER_INT__W                                    1
5270 #define   QAM_SL_COMM_INT_STA_MER_INT__M                                    0x2
5271 #define   QAM_SL_COMM_INT_STA_MER_INT__PRE                                  0x0
5272 
5273 #define QAM_SL_COMM_INT_MSK__A                                              0x1430006
5274 #define QAM_SL_COMM_INT_MSK__W                                              2
5275 #define QAM_SL_COMM_INT_MSK__M                                              0x3
5276 #define QAM_SL_COMM_INT_MSK__PRE                                            0x0
5277 #define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B                                0
5278 #define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W                                1
5279 #define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M                                0x1
5280 #define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE                              0x0
5281 #define   QAM_SL_COMM_INT_MSK_MER_MSK__B                                    1
5282 #define   QAM_SL_COMM_INT_MSK_MER_MSK__W                                    1
5283 #define   QAM_SL_COMM_INT_MSK_MER_MSK__M                                    0x2
5284 #define   QAM_SL_COMM_INT_MSK_MER_MSK__PRE                                  0x0
5285 
5286 #define QAM_SL_COMM_INT_STM__A                                              0x1430007
5287 #define QAM_SL_COMM_INT_STM__W                                              2
5288 #define QAM_SL_COMM_INT_STM__M                                              0x3
5289 #define QAM_SL_COMM_INT_STM__PRE                                            0x0
5290 #define   QAM_SL_COMM_INT_STM_MED_ERR_STM__B                                0
5291 #define   QAM_SL_COMM_INT_STM_MED_ERR_STM__W                                1
5292 #define   QAM_SL_COMM_INT_STM_MED_ERR_STM__M                                0x1
5293 #define   QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE                              0x0
5294 #define   QAM_SL_COMM_INT_STM_MER_STM__B                                    1
5295 #define   QAM_SL_COMM_INT_STM_MER_STM__W                                    1
5296 #define   QAM_SL_COMM_INT_STM_MER_STM__M                                    0x2
5297 #define   QAM_SL_COMM_INT_STM_MER_STM__PRE                                  0x0
5298 
5299 #define QAM_SL_MODE__A                                                      0x1430010
5300 #define QAM_SL_MODE__W                                                      11
5301 #define QAM_SL_MODE__M                                                      0x7FF
5302 #define QAM_SL_MODE__PRE                                                    0x0
5303 
5304 #define   QAM_SL_MODE_SLICER4LC__B                                          0
5305 #define   QAM_SL_MODE_SLICER4LC__W                                          2
5306 #define   QAM_SL_MODE_SLICER4LC__M                                          0x3
5307 #define   QAM_SL_MODE_SLICER4LC__PRE                                        0x0
5308 #define     QAM_SL_MODE_SLICER4LC_RECT                                      0x0
5309 #define     QAM_SL_MODE_SLICER4LC_ONET                                      0x1
5310 #define     QAM_SL_MODE_SLICER4LC_RAD                                       0x2
5311 
5312 #define   QAM_SL_MODE_SLICER4DQ__B                                          2
5313 #define   QAM_SL_MODE_SLICER4DQ__W                                          2
5314 #define   QAM_SL_MODE_SLICER4DQ__M                                          0xC
5315 #define   QAM_SL_MODE_SLICER4DQ__PRE                                        0x0
5316 #define     QAM_SL_MODE_SLICER4DQ_RECT                                      0x0
5317 #define     QAM_SL_MODE_SLICER4DQ_ONET                                      0x4
5318 #define     QAM_SL_MODE_SLICER4DQ_RAD                                       0x8
5319 
5320 #define   QAM_SL_MODE_SLICER4VD__B                                          4
5321 #define   QAM_SL_MODE_SLICER4VD__W                                          2
5322 #define   QAM_SL_MODE_SLICER4VD__M                                          0x30
5323 #define   QAM_SL_MODE_SLICER4VD__PRE                                        0x0
5324 #define     QAM_SL_MODE_SLICER4VD_RECT                                      0x0
5325 #define     QAM_SL_MODE_SLICER4VD_ONET                                      0x10
5326 #define     QAM_SL_MODE_SLICER4VD_RAD                                       0x20
5327 
5328 #define   QAM_SL_MODE_ROT_DIS__B                                            6
5329 #define   QAM_SL_MODE_ROT_DIS__W                                            1
5330 #define   QAM_SL_MODE_ROT_DIS__M                                            0x40
5331 #define   QAM_SL_MODE_ROT_DIS__PRE                                          0x0
5332 
5333 #define   QAM_SL_MODE_DQROT_DIS__B                                          7
5334 #define   QAM_SL_MODE_DQROT_DIS__W                                          1
5335 #define   QAM_SL_MODE_DQROT_DIS__M                                          0x80
5336 #define   QAM_SL_MODE_DQROT_DIS__PRE                                        0x0
5337 
5338 #define   QAM_SL_MODE_DFE_DIS__B                                            8
5339 #define   QAM_SL_MODE_DFE_DIS__W                                            1
5340 #define   QAM_SL_MODE_DFE_DIS__M                                            0x100
5341 #define   QAM_SL_MODE_DFE_DIS__PRE                                          0x0
5342 
5343 #define   QAM_SL_MODE_RADIUS_MIX__B                                         9
5344 #define   QAM_SL_MODE_RADIUS_MIX__W                                         1
5345 #define   QAM_SL_MODE_RADIUS_MIX__M                                         0x200
5346 #define   QAM_SL_MODE_RADIUS_MIX__PRE                                       0x0
5347 
5348 #define   QAM_SL_MODE_TILT_COMP__B                                          10
5349 #define   QAM_SL_MODE_TILT_COMP__W                                          1
5350 #define   QAM_SL_MODE_TILT_COMP__M                                          0x400
5351 #define   QAM_SL_MODE_TILT_COMP__PRE                                        0x0
5352 
5353 #define QAM_SL_K_FACTOR__A                                                  0x1430011
5354 #define QAM_SL_K_FACTOR__W                                                  4
5355 #define QAM_SL_K_FACTOR__M                                                  0xF
5356 #define QAM_SL_K_FACTOR__PRE                                                0x0
5357 #define QAM_SL_MEDIAN__A                                                    0x1430012
5358 #define QAM_SL_MEDIAN__W                                                    14
5359 #define QAM_SL_MEDIAN__M                                                    0x3FFF
5360 #define QAM_SL_MEDIAN__PRE                                                  0x0
5361 
5362 #define   QAM_SL_MEDIAN_LENGTH__B                                           0
5363 #define   QAM_SL_MEDIAN_LENGTH__W                                           2
5364 #define   QAM_SL_MEDIAN_LENGTH__M                                           0x3
5365 #define   QAM_SL_MEDIAN_LENGTH__PRE                                         0x0
5366 
5367 #define   QAM_SL_MEDIAN_CORRECT__B                                          2
5368 #define   QAM_SL_MEDIAN_CORRECT__W                                          4
5369 #define   QAM_SL_MEDIAN_CORRECT__M                                          0x3C
5370 #define   QAM_SL_MEDIAN_CORRECT__PRE                                        0x0
5371 
5372 #define   QAM_SL_MEDIAN_TOLERANCE__B                                        6
5373 #define   QAM_SL_MEDIAN_TOLERANCE__W                                        7
5374 #define   QAM_SL_MEDIAN_TOLERANCE__M                                        0x1FC0
5375 #define   QAM_SL_MEDIAN_TOLERANCE__PRE                                      0x0
5376 
5377 #define   QAM_SL_MEDIAN_FAST__B                                             13
5378 #define   QAM_SL_MEDIAN_FAST__W                                             1
5379 #define   QAM_SL_MEDIAN_FAST__M                                             0x2000
5380 #define   QAM_SL_MEDIAN_FAST__PRE                                           0x0
5381 
5382 #define QAM_SL_ALPHA__A                                                     0x1430013
5383 #define QAM_SL_ALPHA__W                                                     3
5384 #define QAM_SL_ALPHA__M                                                     0x7
5385 #define QAM_SL_ALPHA__PRE                                                   0x0
5386 
5387 #define QAM_SL_PHASELIMIT__A                                                0x1430014
5388 #define QAM_SL_PHASELIMIT__W                                                9
5389 #define QAM_SL_PHASELIMIT__M                                                0x1FF
5390 #define QAM_SL_PHASELIMIT__PRE                                              0x0
5391 #define QAM_SL_MTA_LENGTH__A                                                0x1430015
5392 #define QAM_SL_MTA_LENGTH__W                                                2
5393 #define QAM_SL_MTA_LENGTH__M                                                0x3
5394 #define QAM_SL_MTA_LENGTH__PRE                                              0x1
5395 
5396 #define   QAM_SL_MTA_LENGTH_LENGTH__B                                       0
5397 #define   QAM_SL_MTA_LENGTH_LENGTH__W                                       2
5398 #define   QAM_SL_MTA_LENGTH_LENGTH__M                                       0x3
5399 #define   QAM_SL_MTA_LENGTH_LENGTH__PRE                                     0x1
5400 
5401 #define QAM_SL_MEDIAN_ERROR__A                                              0x1430016
5402 #define QAM_SL_MEDIAN_ERROR__W                                              10
5403 #define QAM_SL_MEDIAN_ERROR__M                                              0x3FF
5404 #define QAM_SL_MEDIAN_ERROR__PRE                                            0x0
5405 
5406 #define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B                                 0
5407 #define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W                                 10
5408 #define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M                                 0x3FF
5409 #define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE                               0x0
5410 
5411 #define QAM_SL_ERR_POWER__A                                                 0x1430017
5412 #define QAM_SL_ERR_POWER__W                                                 16
5413 #define QAM_SL_ERR_POWER__M                                                 0xFFFF
5414 #define QAM_SL_ERR_POWER__PRE                                               0x0
5415 
5416 #define QAM_DQ_COMM_EXEC__A                                                 0x1440000
5417 #define QAM_DQ_COMM_EXEC__W                                                 2
5418 #define QAM_DQ_COMM_EXEC__M                                                 0x3
5419 #define QAM_DQ_COMM_EXEC__PRE                                               0x0
5420 #define   QAM_DQ_COMM_EXEC_STOP                                             0x0
5421 #define   QAM_DQ_COMM_EXEC_ACTIVE                                           0x1
5422 #define   QAM_DQ_COMM_EXEC_HOLD                                             0x2
5423 
5424 #define QAM_DQ_MODE__A                                                      0x1440010
5425 #define QAM_DQ_MODE__W                                                      5
5426 #define QAM_DQ_MODE__M                                                      0x1F
5427 #define QAM_DQ_MODE__PRE                                                    0x0
5428 
5429 #define   QAM_DQ_MODE_TAPRESET__B                                           0
5430 #define   QAM_DQ_MODE_TAPRESET__W                                           1
5431 #define   QAM_DQ_MODE_TAPRESET__M                                           0x1
5432 #define   QAM_DQ_MODE_TAPRESET__PRE                                         0x0
5433 #define     QAM_DQ_MODE_TAPRESET_RST                                        0x1
5434 
5435 #define   QAM_DQ_MODE_TAPLMS__B                                             1
5436 #define   QAM_DQ_MODE_TAPLMS__W                                             1
5437 #define   QAM_DQ_MODE_TAPLMS__M                                             0x2
5438 #define   QAM_DQ_MODE_TAPLMS__PRE                                           0x0
5439 #define     QAM_DQ_MODE_TAPLMS_UPD                                          0x2
5440 
5441 #define   QAM_DQ_MODE_TAPDRAIN__B                                           2
5442 #define   QAM_DQ_MODE_TAPDRAIN__W                                           1
5443 #define   QAM_DQ_MODE_TAPDRAIN__M                                           0x4
5444 #define   QAM_DQ_MODE_TAPDRAIN__PRE                                         0x0
5445 #define     QAM_DQ_MODE_TAPDRAIN_DRAIN                                      0x4
5446 
5447 #define   QAM_DQ_MODE_FB__B                                                 3
5448 #define   QAM_DQ_MODE_FB__W                                                 2
5449 #define   QAM_DQ_MODE_FB__M                                                 0x18
5450 #define   QAM_DQ_MODE_FB__PRE                                               0x0
5451 #define     QAM_DQ_MODE_FB_CMA                                              0x0
5452 #define     QAM_DQ_MODE_FB_RADIUS                                           0x8
5453 #define     QAM_DQ_MODE_FB_DFB                                              0x10
5454 #define     QAM_DQ_MODE_FB_TRELLIS                                          0x18
5455 
5456 #define QAM_DQ_MU_FACTOR__A                                                 0x1440011
5457 #define QAM_DQ_MU_FACTOR__W                                                 3
5458 #define QAM_DQ_MU_FACTOR__M                                                 0x7
5459 #define QAM_DQ_MU_FACTOR__PRE                                               0x0
5460 
5461 #define QAM_DQ_LA_FACTOR__A                                                 0x1440012
5462 #define QAM_DQ_LA_FACTOR__W                                                 4
5463 #define QAM_DQ_LA_FACTOR__M                                                 0xF
5464 #define QAM_DQ_LA_FACTOR__PRE                                               0xC
5465 
5466 #define QAM_DQ_CMA_RATIO__A                                                 0x1440013
5467 #define QAM_DQ_CMA_RATIO__W                                                 14
5468 #define QAM_DQ_CMA_RATIO__M                                                 0x3FFF
5469 #define QAM_DQ_CMA_RATIO__PRE                                               0x3CF9
5470 #define   QAM_DQ_CMA_RATIO_QPSK                                             0x2000
5471 #define   QAM_DQ_CMA_RATIO_QAM16                                            0x34CD
5472 #define   QAM_DQ_CMA_RATIO_QAM64                                            0x3A00
5473 #define   QAM_DQ_CMA_RATIO_QAM256                                           0x3B4D
5474 #define   QAM_DQ_CMA_RATIO_QAM1024                                          0x3BA0
5475 
5476 #define QAM_DQ_QUAL_RADSEL__A                                               0x1440014
5477 #define QAM_DQ_QUAL_RADSEL__W                                               3
5478 #define QAM_DQ_QUAL_RADSEL__M                                               0x7
5479 #define QAM_DQ_QUAL_RADSEL__PRE                                             0x0
5480 
5481 #define   QAM_DQ_QUAL_RADSEL_BIT__B                                         0
5482 #define   QAM_DQ_QUAL_RADSEL_BIT__W                                         3
5483 #define   QAM_DQ_QUAL_RADSEL_BIT__M                                         0x7
5484 #define   QAM_DQ_QUAL_RADSEL_BIT__PRE                                       0x0
5485 #define     QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS                              0x0
5486 #define     QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA                                 0x6
5487 
5488 #define QAM_DQ_QUAL_ENA__A                                                  0x1440015
5489 #define QAM_DQ_QUAL_ENA__W                                                  1
5490 #define QAM_DQ_QUAL_ENA__M                                                  0x1
5491 #define QAM_DQ_QUAL_ENA__PRE                                                0x0
5492 
5493 #define   QAM_DQ_QUAL_ENA_ENA__B                                            0
5494 #define   QAM_DQ_QUAL_ENA_ENA__W                                            1
5495 #define   QAM_DQ_QUAL_ENA_ENA__M                                            0x1
5496 #define   QAM_DQ_QUAL_ENA_ENA__PRE                                          0x0
5497 #define     QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING                              0x1
5498 
5499 #define QAM_DQ_QUAL_FUN0__A                                                 0x1440018
5500 #define QAM_DQ_QUAL_FUN0__W                                                 6
5501 #define QAM_DQ_QUAL_FUN0__M                                                 0x3F
5502 #define QAM_DQ_QUAL_FUN0__PRE                                               0x4
5503 
5504 #define   QAM_DQ_QUAL_FUN0_BIT__B                                           0
5505 #define   QAM_DQ_QUAL_FUN0_BIT__W                                           6
5506 #define   QAM_DQ_QUAL_FUN0_BIT__M                                           0x3F
5507 #define   QAM_DQ_QUAL_FUN0_BIT__PRE                                         0x4
5508 
5509 #define QAM_DQ_QUAL_FUN1__A                                                 0x1440019
5510 #define QAM_DQ_QUAL_FUN1__W                                                 6
5511 #define QAM_DQ_QUAL_FUN1__M                                                 0x3F
5512 #define QAM_DQ_QUAL_FUN1__PRE                                               0x4
5513 
5514 #define   QAM_DQ_QUAL_FUN1_BIT__B                                           0
5515 #define   QAM_DQ_QUAL_FUN1_BIT__W                                           6
5516 #define   QAM_DQ_QUAL_FUN1_BIT__M                                           0x3F
5517 #define   QAM_DQ_QUAL_FUN1_BIT__PRE                                         0x4
5518 
5519 #define QAM_DQ_QUAL_FUN2__A                                                 0x144001A
5520 #define QAM_DQ_QUAL_FUN2__W                                                 6
5521 #define QAM_DQ_QUAL_FUN2__M                                                 0x3F
5522 #define QAM_DQ_QUAL_FUN2__PRE                                               0x4
5523 
5524 #define   QAM_DQ_QUAL_FUN2_BIT__B                                           0
5525 #define   QAM_DQ_QUAL_FUN2_BIT__W                                           6
5526 #define   QAM_DQ_QUAL_FUN2_BIT__M                                           0x3F
5527 #define   QAM_DQ_QUAL_FUN2_BIT__PRE                                         0x4
5528 
5529 #define QAM_DQ_QUAL_FUN3__A                                                 0x144001B
5530 #define QAM_DQ_QUAL_FUN3__W                                                 6
5531 #define QAM_DQ_QUAL_FUN3__M                                                 0x3F
5532 #define QAM_DQ_QUAL_FUN3__PRE                                               0x4
5533 
5534 #define   QAM_DQ_QUAL_FUN3_BIT__B                                           0
5535 #define   QAM_DQ_QUAL_FUN3_BIT__W                                           6
5536 #define   QAM_DQ_QUAL_FUN3_BIT__M                                           0x3F
5537 #define   QAM_DQ_QUAL_FUN3_BIT__PRE                                         0x4
5538 
5539 #define QAM_DQ_QUAL_FUN4__A                                                 0x144001C
5540 #define QAM_DQ_QUAL_FUN4__W                                                 6
5541 #define QAM_DQ_QUAL_FUN4__M                                                 0x3F
5542 #define QAM_DQ_QUAL_FUN4__PRE                                               0x6
5543 
5544 #define   QAM_DQ_QUAL_FUN4_BIT__B                                           0
5545 #define   QAM_DQ_QUAL_FUN4_BIT__W                                           6
5546 #define   QAM_DQ_QUAL_FUN4_BIT__M                                           0x3F
5547 #define   QAM_DQ_QUAL_FUN4_BIT__PRE                                         0x6
5548 
5549 #define QAM_DQ_QUAL_FUN5__A                                                 0x144001D
5550 #define QAM_DQ_QUAL_FUN5__W                                                 6
5551 #define QAM_DQ_QUAL_FUN5__M                                                 0x3F
5552 #define QAM_DQ_QUAL_FUN5__PRE                                               0x6
5553 
5554 #define   QAM_DQ_QUAL_FUN5_BIT__B                                           0
5555 #define   QAM_DQ_QUAL_FUN5_BIT__W                                           6
5556 #define   QAM_DQ_QUAL_FUN5_BIT__M                                           0x3F
5557 #define   QAM_DQ_QUAL_FUN5_BIT__PRE                                         0x6
5558 
5559 #define QAM_DQ_RAW_LIM__A                                                   0x144001E
5560 #define QAM_DQ_RAW_LIM__W                                                   5
5561 #define QAM_DQ_RAW_LIM__M                                                   0x1F
5562 #define QAM_DQ_RAW_LIM__PRE                                                 0x1F
5563 
5564 #define   QAM_DQ_RAW_LIM_BIT__B                                             0
5565 #define   QAM_DQ_RAW_LIM_BIT__W                                             5
5566 #define   QAM_DQ_RAW_LIM_BIT__M                                             0x1F
5567 #define   QAM_DQ_RAW_LIM_BIT__PRE                                           0x1F
5568 
5569 #define QAM_DQ_TAP_RE_EL0__A                                                0x1440020
5570 #define QAM_DQ_TAP_RE_EL0__W                                                12
5571 #define QAM_DQ_TAP_RE_EL0__M                                                0xFFF
5572 #define QAM_DQ_TAP_RE_EL0__PRE                                              0x2
5573 
5574 #define   QAM_DQ_TAP_RE_EL0_TAP__B                                          0
5575 #define   QAM_DQ_TAP_RE_EL0_TAP__W                                          12
5576 #define   QAM_DQ_TAP_RE_EL0_TAP__M                                          0xFFF
5577 #define   QAM_DQ_TAP_RE_EL0_TAP__PRE                                        0x2
5578 
5579 #define QAM_DQ_TAP_IM_EL0__A                                                0x1440021
5580 #define QAM_DQ_TAP_IM_EL0__W                                                12
5581 #define QAM_DQ_TAP_IM_EL0__M                                                0xFFF
5582 #define QAM_DQ_TAP_IM_EL0__PRE                                              0x2
5583 
5584 #define   QAM_DQ_TAP_IM_EL0_TAP__B                                          0
5585 #define   QAM_DQ_TAP_IM_EL0_TAP__W                                          12
5586 #define   QAM_DQ_TAP_IM_EL0_TAP__M                                          0xFFF
5587 #define   QAM_DQ_TAP_IM_EL0_TAP__PRE                                        0x2
5588 
5589 #define QAM_DQ_TAP_RE_EL1__A                                                0x1440022
5590 #define QAM_DQ_TAP_RE_EL1__W                                                12
5591 #define QAM_DQ_TAP_RE_EL1__M                                                0xFFF
5592 #define QAM_DQ_TAP_RE_EL1__PRE                                              0x2
5593 
5594 #define   QAM_DQ_TAP_RE_EL1_TAP__B                                          0
5595 #define   QAM_DQ_TAP_RE_EL1_TAP__W                                          12
5596 #define   QAM_DQ_TAP_RE_EL1_TAP__M                                          0xFFF
5597 #define   QAM_DQ_TAP_RE_EL1_TAP__PRE                                        0x2
5598 
5599 #define QAM_DQ_TAP_IM_EL1__A                                                0x1440023
5600 #define QAM_DQ_TAP_IM_EL1__W                                                12
5601 #define QAM_DQ_TAP_IM_EL1__M                                                0xFFF
5602 #define QAM_DQ_TAP_IM_EL1__PRE                                              0x2
5603 
5604 #define   QAM_DQ_TAP_IM_EL1_TAP__B                                          0
5605 #define   QAM_DQ_TAP_IM_EL1_TAP__W                                          12
5606 #define   QAM_DQ_TAP_IM_EL1_TAP__M                                          0xFFF
5607 #define   QAM_DQ_TAP_IM_EL1_TAP__PRE                                        0x2
5608 
5609 #define QAM_DQ_TAP_RE_EL2__A                                                0x1440024
5610 #define QAM_DQ_TAP_RE_EL2__W                                                12
5611 #define QAM_DQ_TAP_RE_EL2__M                                                0xFFF
5612 #define QAM_DQ_TAP_RE_EL2__PRE                                              0x2
5613 
5614 #define   QAM_DQ_TAP_RE_EL2_TAP__B                                          0
5615 #define   QAM_DQ_TAP_RE_EL2_TAP__W                                          12
5616 #define   QAM_DQ_TAP_RE_EL2_TAP__M                                          0xFFF
5617 #define   QAM_DQ_TAP_RE_EL2_TAP__PRE                                        0x2
5618 
5619 #define QAM_DQ_TAP_IM_EL2__A                                                0x1440025
5620 #define QAM_DQ_TAP_IM_EL2__W                                                12
5621 #define QAM_DQ_TAP_IM_EL2__M                                                0xFFF
5622 #define QAM_DQ_TAP_IM_EL2__PRE                                              0x2
5623 
5624 #define   QAM_DQ_TAP_IM_EL2_TAP__B                                          0
5625 #define   QAM_DQ_TAP_IM_EL2_TAP__W                                          12
5626 #define   QAM_DQ_TAP_IM_EL2_TAP__M                                          0xFFF
5627 #define   QAM_DQ_TAP_IM_EL2_TAP__PRE                                        0x2
5628 
5629 #define QAM_DQ_TAP_RE_EL3__A                                                0x1440026
5630 #define QAM_DQ_TAP_RE_EL3__W                                                12
5631 #define QAM_DQ_TAP_RE_EL3__M                                                0xFFF
5632 #define QAM_DQ_TAP_RE_EL3__PRE                                              0x2
5633 
5634 #define   QAM_DQ_TAP_RE_EL3_TAP__B                                          0
5635 #define   QAM_DQ_TAP_RE_EL3_TAP__W                                          12
5636 #define   QAM_DQ_TAP_RE_EL3_TAP__M                                          0xFFF
5637 #define   QAM_DQ_TAP_RE_EL3_TAP__PRE                                        0x2
5638 
5639 #define QAM_DQ_TAP_IM_EL3__A                                                0x1440027
5640 #define QAM_DQ_TAP_IM_EL3__W                                                12
5641 #define QAM_DQ_TAP_IM_EL3__M                                                0xFFF
5642 #define QAM_DQ_TAP_IM_EL3__PRE                                              0x2
5643 
5644 #define   QAM_DQ_TAP_IM_EL3_TAP__B                                          0
5645 #define   QAM_DQ_TAP_IM_EL3_TAP__W                                          12
5646 #define   QAM_DQ_TAP_IM_EL3_TAP__M                                          0xFFF
5647 #define   QAM_DQ_TAP_IM_EL3_TAP__PRE                                        0x2
5648 
5649 #define QAM_DQ_TAP_RE_EL4__A                                                0x1440028
5650 #define QAM_DQ_TAP_RE_EL4__W                                                12
5651 #define QAM_DQ_TAP_RE_EL4__M                                                0xFFF
5652 #define QAM_DQ_TAP_RE_EL4__PRE                                              0x2
5653 
5654 #define   QAM_DQ_TAP_RE_EL4_TAP__B                                          0
5655 #define   QAM_DQ_TAP_RE_EL4_TAP__W                                          12
5656 #define   QAM_DQ_TAP_RE_EL4_TAP__M                                          0xFFF
5657 #define   QAM_DQ_TAP_RE_EL4_TAP__PRE                                        0x2
5658 
5659 #define QAM_DQ_TAP_IM_EL4__A                                                0x1440029
5660 #define QAM_DQ_TAP_IM_EL4__W                                                12
5661 #define QAM_DQ_TAP_IM_EL4__M                                                0xFFF
5662 #define QAM_DQ_TAP_IM_EL4__PRE                                              0x2
5663 
5664 #define   QAM_DQ_TAP_IM_EL4_TAP__B                                          0
5665 #define   QAM_DQ_TAP_IM_EL4_TAP__W                                          12
5666 #define   QAM_DQ_TAP_IM_EL4_TAP__M                                          0xFFF
5667 #define   QAM_DQ_TAP_IM_EL4_TAP__PRE                                        0x2
5668 
5669 #define QAM_DQ_TAP_RE_EL5__A                                                0x144002A
5670 #define QAM_DQ_TAP_RE_EL5__W                                                12
5671 #define QAM_DQ_TAP_RE_EL5__M                                                0xFFF
5672 #define QAM_DQ_TAP_RE_EL5__PRE                                              0x2
5673 
5674 #define   QAM_DQ_TAP_RE_EL5_TAP__B                                          0
5675 #define   QAM_DQ_TAP_RE_EL5_TAP__W                                          12
5676 #define   QAM_DQ_TAP_RE_EL5_TAP__M                                          0xFFF
5677 #define   QAM_DQ_TAP_RE_EL5_TAP__PRE                                        0x2
5678 
5679 #define QAM_DQ_TAP_IM_EL5__A                                                0x144002B
5680 #define QAM_DQ_TAP_IM_EL5__W                                                12
5681 #define QAM_DQ_TAP_IM_EL5__M                                                0xFFF
5682 #define QAM_DQ_TAP_IM_EL5__PRE                                              0x2
5683 
5684 #define   QAM_DQ_TAP_IM_EL5_TAP__B                                          0
5685 #define   QAM_DQ_TAP_IM_EL5_TAP__W                                          12
5686 #define   QAM_DQ_TAP_IM_EL5_TAP__M                                          0xFFF
5687 #define   QAM_DQ_TAP_IM_EL5_TAP__PRE                                        0x2
5688 
5689 #define QAM_DQ_TAP_RE_EL6__A                                                0x144002C
5690 #define QAM_DQ_TAP_RE_EL6__W                                                12
5691 #define QAM_DQ_TAP_RE_EL6__M                                                0xFFF
5692 #define QAM_DQ_TAP_RE_EL6__PRE                                              0x2
5693 
5694 #define   QAM_DQ_TAP_RE_EL6_TAP__B                                          0
5695 #define   QAM_DQ_TAP_RE_EL6_TAP__W                                          12
5696 #define   QAM_DQ_TAP_RE_EL6_TAP__M                                          0xFFF
5697 #define   QAM_DQ_TAP_RE_EL6_TAP__PRE                                        0x2
5698 
5699 #define QAM_DQ_TAP_IM_EL6__A                                                0x144002D
5700 #define QAM_DQ_TAP_IM_EL6__W                                                12
5701 #define QAM_DQ_TAP_IM_EL6__M                                                0xFFF
5702 #define QAM_DQ_TAP_IM_EL6__PRE                                              0x2
5703 
5704 #define   QAM_DQ_TAP_IM_EL6_TAP__B                                          0
5705 #define   QAM_DQ_TAP_IM_EL6_TAP__W                                          12
5706 #define   QAM_DQ_TAP_IM_EL6_TAP__M                                          0xFFF
5707 #define   QAM_DQ_TAP_IM_EL6_TAP__PRE                                        0x2
5708 
5709 #define QAM_DQ_TAP_RE_EL7__A                                                0x144002E
5710 #define QAM_DQ_TAP_RE_EL7__W                                                12
5711 #define QAM_DQ_TAP_RE_EL7__M                                                0xFFF
5712 #define QAM_DQ_TAP_RE_EL7__PRE                                              0x2
5713 
5714 #define   QAM_DQ_TAP_RE_EL7_TAP__B                                          0
5715 #define   QAM_DQ_TAP_RE_EL7_TAP__W                                          12
5716 #define   QAM_DQ_TAP_RE_EL7_TAP__M                                          0xFFF
5717 #define   QAM_DQ_TAP_RE_EL7_TAP__PRE                                        0x2
5718 
5719 #define QAM_DQ_TAP_IM_EL7__A                                                0x144002F
5720 #define QAM_DQ_TAP_IM_EL7__W                                                12
5721 #define QAM_DQ_TAP_IM_EL7__M                                                0xFFF
5722 #define QAM_DQ_TAP_IM_EL7__PRE                                              0x2
5723 
5724 #define   QAM_DQ_TAP_IM_EL7_TAP__B                                          0
5725 #define   QAM_DQ_TAP_IM_EL7_TAP__W                                          12
5726 #define   QAM_DQ_TAP_IM_EL7_TAP__M                                          0xFFF
5727 #define   QAM_DQ_TAP_IM_EL7_TAP__PRE                                        0x2
5728 
5729 #define QAM_DQ_TAP_RE_EL8__A                                                0x1440030
5730 #define QAM_DQ_TAP_RE_EL8__W                                                12
5731 #define QAM_DQ_TAP_RE_EL8__M                                                0xFFF
5732 #define QAM_DQ_TAP_RE_EL8__PRE                                              0x2
5733 
5734 #define   QAM_DQ_TAP_RE_EL8_TAP__B                                          0
5735 #define   QAM_DQ_TAP_RE_EL8_TAP__W                                          12
5736 #define   QAM_DQ_TAP_RE_EL8_TAP__M                                          0xFFF
5737 #define   QAM_DQ_TAP_RE_EL8_TAP__PRE                                        0x2
5738 
5739 #define QAM_DQ_TAP_IM_EL8__A                                                0x1440031
5740 #define QAM_DQ_TAP_IM_EL8__W                                                12
5741 #define QAM_DQ_TAP_IM_EL8__M                                                0xFFF
5742 #define QAM_DQ_TAP_IM_EL8__PRE                                              0x2
5743 
5744 #define   QAM_DQ_TAP_IM_EL8_TAP__B                                          0
5745 #define   QAM_DQ_TAP_IM_EL8_TAP__W                                          12
5746 #define   QAM_DQ_TAP_IM_EL8_TAP__M                                          0xFFF
5747 #define   QAM_DQ_TAP_IM_EL8_TAP__PRE                                        0x2
5748 
5749 #define QAM_DQ_TAP_RE_EL9__A                                                0x1440032
5750 #define QAM_DQ_TAP_RE_EL9__W                                                12
5751 #define QAM_DQ_TAP_RE_EL9__M                                                0xFFF
5752 #define QAM_DQ_TAP_RE_EL9__PRE                                              0x2
5753 
5754 #define   QAM_DQ_TAP_RE_EL9_TAP__B                                          0
5755 #define   QAM_DQ_TAP_RE_EL9_TAP__W                                          12
5756 #define   QAM_DQ_TAP_RE_EL9_TAP__M                                          0xFFF
5757 #define   QAM_DQ_TAP_RE_EL9_TAP__PRE                                        0x2
5758 
5759 #define QAM_DQ_TAP_IM_EL9__A                                                0x1440033
5760 #define QAM_DQ_TAP_IM_EL9__W                                                12
5761 #define QAM_DQ_TAP_IM_EL9__M                                                0xFFF
5762 #define QAM_DQ_TAP_IM_EL9__PRE                                              0x2
5763 
5764 #define   QAM_DQ_TAP_IM_EL9_TAP__B                                          0
5765 #define   QAM_DQ_TAP_IM_EL9_TAP__W                                          12
5766 #define   QAM_DQ_TAP_IM_EL9_TAP__M                                          0xFFF
5767 #define   QAM_DQ_TAP_IM_EL9_TAP__PRE                                        0x2
5768 
5769 #define QAM_DQ_TAP_RE_EL10__A                                               0x1440034
5770 #define QAM_DQ_TAP_RE_EL10__W                                               12
5771 #define QAM_DQ_TAP_RE_EL10__M                                               0xFFF
5772 #define QAM_DQ_TAP_RE_EL10__PRE                                             0x2
5773 
5774 #define   QAM_DQ_TAP_RE_EL10_TAP__B                                         0
5775 #define   QAM_DQ_TAP_RE_EL10_TAP__W                                         12
5776 #define   QAM_DQ_TAP_RE_EL10_TAP__M                                         0xFFF
5777 #define   QAM_DQ_TAP_RE_EL10_TAP__PRE                                       0x2
5778 
5779 #define QAM_DQ_TAP_IM_EL10__A                                               0x1440035
5780 #define QAM_DQ_TAP_IM_EL10__W                                               12
5781 #define QAM_DQ_TAP_IM_EL10__M                                               0xFFF
5782 #define QAM_DQ_TAP_IM_EL10__PRE                                             0x2
5783 
5784 #define   QAM_DQ_TAP_IM_EL10_TAP__B                                         0
5785 #define   QAM_DQ_TAP_IM_EL10_TAP__W                                         12
5786 #define   QAM_DQ_TAP_IM_EL10_TAP__M                                         0xFFF
5787 #define   QAM_DQ_TAP_IM_EL10_TAP__PRE                                       0x2
5788 
5789 #define QAM_DQ_TAP_RE_EL11__A                                               0x1440036
5790 #define QAM_DQ_TAP_RE_EL11__W                                               12
5791 #define QAM_DQ_TAP_RE_EL11__M                                               0xFFF
5792 #define QAM_DQ_TAP_RE_EL11__PRE                                             0x2
5793 
5794 #define   QAM_DQ_TAP_RE_EL11_TAP__B                                         0
5795 #define   QAM_DQ_TAP_RE_EL11_TAP__W                                         12
5796 #define   QAM_DQ_TAP_RE_EL11_TAP__M                                         0xFFF
5797 #define   QAM_DQ_TAP_RE_EL11_TAP__PRE                                       0x2
5798 
5799 #define QAM_DQ_TAP_IM_EL11__A                                               0x1440037
5800 #define QAM_DQ_TAP_IM_EL11__W                                               12
5801 #define QAM_DQ_TAP_IM_EL11__M                                               0xFFF
5802 #define QAM_DQ_TAP_IM_EL11__PRE                                             0x2
5803 
5804 #define   QAM_DQ_TAP_IM_EL11_TAP__B                                         0
5805 #define   QAM_DQ_TAP_IM_EL11_TAP__W                                         12
5806 #define   QAM_DQ_TAP_IM_EL11_TAP__M                                         0xFFF
5807 #define   QAM_DQ_TAP_IM_EL11_TAP__PRE                                       0x2
5808 
5809 #define QAM_DQ_TAP_RE_EL12__A                                               0x1440038
5810 #define QAM_DQ_TAP_RE_EL12__W                                               12
5811 #define QAM_DQ_TAP_RE_EL12__M                                               0xFFF
5812 #define QAM_DQ_TAP_RE_EL12__PRE                                             0x2
5813 
5814 #define   QAM_DQ_TAP_RE_EL12_TAP__B                                         0
5815 #define   QAM_DQ_TAP_RE_EL12_TAP__W                                         12
5816 #define   QAM_DQ_TAP_RE_EL12_TAP__M                                         0xFFF
5817 #define   QAM_DQ_TAP_RE_EL12_TAP__PRE                                       0x2
5818 
5819 #define QAM_DQ_TAP_IM_EL12__A                                               0x1440039
5820 #define QAM_DQ_TAP_IM_EL12__W                                               12
5821 #define QAM_DQ_TAP_IM_EL12__M                                               0xFFF
5822 #define QAM_DQ_TAP_IM_EL12__PRE                                             0x2
5823 
5824 #define   QAM_DQ_TAP_IM_EL12_TAP__B                                         0
5825 #define   QAM_DQ_TAP_IM_EL12_TAP__W                                         12
5826 #define   QAM_DQ_TAP_IM_EL12_TAP__M                                         0xFFF
5827 #define   QAM_DQ_TAP_IM_EL12_TAP__PRE                                       0x2
5828 
5829 #define QAM_DQ_TAP_RE_EL13__A                                               0x144003A
5830 #define QAM_DQ_TAP_RE_EL13__W                                               12
5831 #define QAM_DQ_TAP_RE_EL13__M                                               0xFFF
5832 #define QAM_DQ_TAP_RE_EL13__PRE                                             0x2
5833 
5834 #define   QAM_DQ_TAP_RE_EL13_TAP__B                                         0
5835 #define   QAM_DQ_TAP_RE_EL13_TAP__W                                         12
5836 #define   QAM_DQ_TAP_RE_EL13_TAP__M                                         0xFFF
5837 #define   QAM_DQ_TAP_RE_EL13_TAP__PRE                                       0x2
5838 
5839 #define QAM_DQ_TAP_IM_EL13__A                                               0x144003B
5840 #define QAM_DQ_TAP_IM_EL13__W                                               12
5841 #define QAM_DQ_TAP_IM_EL13__M                                               0xFFF
5842 #define QAM_DQ_TAP_IM_EL13__PRE                                             0x2
5843 
5844 #define   QAM_DQ_TAP_IM_EL13_TAP__B                                         0
5845 #define   QAM_DQ_TAP_IM_EL13_TAP__W                                         12
5846 #define   QAM_DQ_TAP_IM_EL13_TAP__M                                         0xFFF
5847 #define   QAM_DQ_TAP_IM_EL13_TAP__PRE                                       0x2
5848 
5849 #define QAM_DQ_TAP_RE_EL14__A                                               0x144003C
5850 #define QAM_DQ_TAP_RE_EL14__W                                               12
5851 #define QAM_DQ_TAP_RE_EL14__M                                               0xFFF
5852 #define QAM_DQ_TAP_RE_EL14__PRE                                             0x2
5853 
5854 #define   QAM_DQ_TAP_RE_EL14_TAP__B                                         0
5855 #define   QAM_DQ_TAP_RE_EL14_TAP__W                                         12
5856 #define   QAM_DQ_TAP_RE_EL14_TAP__M                                         0xFFF
5857 #define   QAM_DQ_TAP_RE_EL14_TAP__PRE                                       0x2
5858 
5859 #define QAM_DQ_TAP_IM_EL14__A                                               0x144003D
5860 #define QAM_DQ_TAP_IM_EL14__W                                               12
5861 #define QAM_DQ_TAP_IM_EL14__M                                               0xFFF
5862 #define QAM_DQ_TAP_IM_EL14__PRE                                             0x2
5863 
5864 #define   QAM_DQ_TAP_IM_EL14_TAP__B                                         0
5865 #define   QAM_DQ_TAP_IM_EL14_TAP__W                                         12
5866 #define   QAM_DQ_TAP_IM_EL14_TAP__M                                         0xFFF
5867 #define   QAM_DQ_TAP_IM_EL14_TAP__PRE                                       0x2
5868 
5869 #define QAM_DQ_TAP_RE_EL15__A                                               0x144003E
5870 #define QAM_DQ_TAP_RE_EL15__W                                               12
5871 #define QAM_DQ_TAP_RE_EL15__M                                               0xFFF
5872 #define QAM_DQ_TAP_RE_EL15__PRE                                             0x2
5873 
5874 #define   QAM_DQ_TAP_RE_EL15_TAP__B                                         0
5875 #define   QAM_DQ_TAP_RE_EL15_TAP__W                                         12
5876 #define   QAM_DQ_TAP_RE_EL15_TAP__M                                         0xFFF
5877 #define   QAM_DQ_TAP_RE_EL15_TAP__PRE                                       0x2
5878 
5879 #define QAM_DQ_TAP_IM_EL15__A                                               0x144003F
5880 #define QAM_DQ_TAP_IM_EL15__W                                               12
5881 #define QAM_DQ_TAP_IM_EL15__M                                               0xFFF
5882 #define QAM_DQ_TAP_IM_EL15__PRE                                             0x2
5883 
5884 #define   QAM_DQ_TAP_IM_EL15_TAP__B                                         0
5885 #define   QAM_DQ_TAP_IM_EL15_TAP__W                                         12
5886 #define   QAM_DQ_TAP_IM_EL15_TAP__M                                         0xFFF
5887 #define   QAM_DQ_TAP_IM_EL15_TAP__PRE                                       0x2
5888 
5889 #define QAM_DQ_TAP_RE_EL16__A                                               0x1440040
5890 #define QAM_DQ_TAP_RE_EL16__W                                               12
5891 #define QAM_DQ_TAP_RE_EL16__M                                               0xFFF
5892 #define QAM_DQ_TAP_RE_EL16__PRE                                             0x2
5893 
5894 #define   QAM_DQ_TAP_RE_EL16_TAP__B                                         0
5895 #define   QAM_DQ_TAP_RE_EL16_TAP__W                                         12
5896 #define   QAM_DQ_TAP_RE_EL16_TAP__M                                         0xFFF
5897 #define   QAM_DQ_TAP_RE_EL16_TAP__PRE                                       0x2
5898 
5899 #define QAM_DQ_TAP_IM_EL16__A                                               0x1440041
5900 #define QAM_DQ_TAP_IM_EL16__W                                               12
5901 #define QAM_DQ_TAP_IM_EL16__M                                               0xFFF
5902 #define QAM_DQ_TAP_IM_EL16__PRE                                             0x2
5903 
5904 #define   QAM_DQ_TAP_IM_EL16_TAP__B                                         0
5905 #define   QAM_DQ_TAP_IM_EL16_TAP__W                                         12
5906 #define   QAM_DQ_TAP_IM_EL16_TAP__M                                         0xFFF
5907 #define   QAM_DQ_TAP_IM_EL16_TAP__PRE                                       0x2
5908 
5909 #define QAM_DQ_TAP_RE_EL17__A                                               0x1440042
5910 #define QAM_DQ_TAP_RE_EL17__W                                               12
5911 #define QAM_DQ_TAP_RE_EL17__M                                               0xFFF
5912 #define QAM_DQ_TAP_RE_EL17__PRE                                             0x2
5913 
5914 #define   QAM_DQ_TAP_RE_EL17_TAP__B                                         0
5915 #define   QAM_DQ_TAP_RE_EL17_TAP__W                                         12
5916 #define   QAM_DQ_TAP_RE_EL17_TAP__M                                         0xFFF
5917 #define   QAM_DQ_TAP_RE_EL17_TAP__PRE                                       0x2
5918 
5919 #define QAM_DQ_TAP_IM_EL17__A                                               0x1440043
5920 #define QAM_DQ_TAP_IM_EL17__W                                               12
5921 #define QAM_DQ_TAP_IM_EL17__M                                               0xFFF
5922 #define QAM_DQ_TAP_IM_EL17__PRE                                             0x2
5923 
5924 #define   QAM_DQ_TAP_IM_EL17_TAP__B                                         0
5925 #define   QAM_DQ_TAP_IM_EL17_TAP__W                                         12
5926 #define   QAM_DQ_TAP_IM_EL17_TAP__M                                         0xFFF
5927 #define   QAM_DQ_TAP_IM_EL17_TAP__PRE                                       0x2
5928 
5929 #define QAM_DQ_TAP_RE_EL18__A                                               0x1440044
5930 #define QAM_DQ_TAP_RE_EL18__W                                               12
5931 #define QAM_DQ_TAP_RE_EL18__M                                               0xFFF
5932 #define QAM_DQ_TAP_RE_EL18__PRE                                             0x2
5933 
5934 #define   QAM_DQ_TAP_RE_EL18_TAP__B                                         0
5935 #define   QAM_DQ_TAP_RE_EL18_TAP__W                                         12
5936 #define   QAM_DQ_TAP_RE_EL18_TAP__M                                         0xFFF
5937 #define   QAM_DQ_TAP_RE_EL18_TAP__PRE                                       0x2
5938 
5939 #define QAM_DQ_TAP_IM_EL18__A                                               0x1440045
5940 #define QAM_DQ_TAP_IM_EL18__W                                               12
5941 #define QAM_DQ_TAP_IM_EL18__M                                               0xFFF
5942 #define QAM_DQ_TAP_IM_EL18__PRE                                             0x2
5943 
5944 #define   QAM_DQ_TAP_IM_EL18_TAP__B                                         0
5945 #define   QAM_DQ_TAP_IM_EL18_TAP__W                                         12
5946 #define   QAM_DQ_TAP_IM_EL18_TAP__M                                         0xFFF
5947 #define   QAM_DQ_TAP_IM_EL18_TAP__PRE                                       0x2
5948 
5949 #define QAM_DQ_TAP_RE_EL19__A                                               0x1440046
5950 #define QAM_DQ_TAP_RE_EL19__W                                               12
5951 #define QAM_DQ_TAP_RE_EL19__M                                               0xFFF
5952 #define QAM_DQ_TAP_RE_EL19__PRE                                             0x2
5953 
5954 #define   QAM_DQ_TAP_RE_EL19_TAP__B                                         0
5955 #define   QAM_DQ_TAP_RE_EL19_TAP__W                                         12
5956 #define   QAM_DQ_TAP_RE_EL19_TAP__M                                         0xFFF
5957 #define   QAM_DQ_TAP_RE_EL19_TAP__PRE                                       0x2
5958 
5959 #define QAM_DQ_TAP_IM_EL19__A                                               0x1440047
5960 #define QAM_DQ_TAP_IM_EL19__W                                               12
5961 #define QAM_DQ_TAP_IM_EL19__M                                               0xFFF
5962 #define QAM_DQ_TAP_IM_EL19__PRE                                             0x2
5963 
5964 #define   QAM_DQ_TAP_IM_EL19_TAP__B                                         0
5965 #define   QAM_DQ_TAP_IM_EL19_TAP__W                                         12
5966 #define   QAM_DQ_TAP_IM_EL19_TAP__M                                         0xFFF
5967 #define   QAM_DQ_TAP_IM_EL19_TAP__PRE                                       0x2
5968 
5969 #define QAM_DQ_TAP_RE_EL20__A                                               0x1440048
5970 #define QAM_DQ_TAP_RE_EL20__W                                               12
5971 #define QAM_DQ_TAP_RE_EL20__M                                               0xFFF
5972 #define QAM_DQ_TAP_RE_EL20__PRE                                             0x2
5973 
5974 #define   QAM_DQ_TAP_RE_EL20_TAP__B                                         0
5975 #define   QAM_DQ_TAP_RE_EL20_TAP__W                                         12
5976 #define   QAM_DQ_TAP_RE_EL20_TAP__M                                         0xFFF
5977 #define   QAM_DQ_TAP_RE_EL20_TAP__PRE                                       0x2
5978 
5979 #define QAM_DQ_TAP_IM_EL20__A                                               0x1440049
5980 #define QAM_DQ_TAP_IM_EL20__W                                               12
5981 #define QAM_DQ_TAP_IM_EL20__M                                               0xFFF
5982 #define QAM_DQ_TAP_IM_EL20__PRE                                             0x2
5983 
5984 #define   QAM_DQ_TAP_IM_EL20_TAP__B                                         0
5985 #define   QAM_DQ_TAP_IM_EL20_TAP__W                                         12
5986 #define   QAM_DQ_TAP_IM_EL20_TAP__M                                         0xFFF
5987 #define   QAM_DQ_TAP_IM_EL20_TAP__PRE                                       0x2
5988 
5989 #define QAM_DQ_TAP_RE_EL21__A                                               0x144004A
5990 #define QAM_DQ_TAP_RE_EL21__W                                               12
5991 #define QAM_DQ_TAP_RE_EL21__M                                               0xFFF
5992 #define QAM_DQ_TAP_RE_EL21__PRE                                             0x2
5993 
5994 #define   QAM_DQ_TAP_RE_EL21_TAP__B                                         0
5995 #define   QAM_DQ_TAP_RE_EL21_TAP__W                                         12
5996 #define   QAM_DQ_TAP_RE_EL21_TAP__M                                         0xFFF
5997 #define   QAM_DQ_TAP_RE_EL21_TAP__PRE                                       0x2
5998 
5999 #define QAM_DQ_TAP_IM_EL21__A                                               0x144004B
6000 #define QAM_DQ_TAP_IM_EL21__W                                               12
6001 #define QAM_DQ_TAP_IM_EL21__M                                               0xFFF
6002 #define QAM_DQ_TAP_IM_EL21__PRE                                             0x2
6003 
6004 #define   QAM_DQ_TAP_IM_EL21_TAP__B                                         0
6005 #define   QAM_DQ_TAP_IM_EL21_TAP__W                                         12
6006 #define   QAM_DQ_TAP_IM_EL21_TAP__M                                         0xFFF
6007 #define   QAM_DQ_TAP_IM_EL21_TAP__PRE                                       0x2
6008 
6009 #define QAM_DQ_TAP_RE_EL22__A                                               0x144004C
6010 #define QAM_DQ_TAP_RE_EL22__W                                               12
6011 #define QAM_DQ_TAP_RE_EL22__M                                               0xFFF
6012 #define QAM_DQ_TAP_RE_EL22__PRE                                             0x2
6013 
6014 #define   QAM_DQ_TAP_RE_EL22_TAP__B                                         0
6015 #define   QAM_DQ_TAP_RE_EL22_TAP__W                                         12
6016 #define   QAM_DQ_TAP_RE_EL22_TAP__M                                         0xFFF
6017 #define   QAM_DQ_TAP_RE_EL22_TAP__PRE                                       0x2
6018 
6019 #define QAM_DQ_TAP_IM_EL22__A                                               0x144004D
6020 #define QAM_DQ_TAP_IM_EL22__W                                               12
6021 #define QAM_DQ_TAP_IM_EL22__M                                               0xFFF
6022 #define QAM_DQ_TAP_IM_EL22__PRE                                             0x2
6023 
6024 #define   QAM_DQ_TAP_IM_EL22_TAP__B                                         0
6025 #define   QAM_DQ_TAP_IM_EL22_TAP__W                                         12
6026 #define   QAM_DQ_TAP_IM_EL22_TAP__M                                         0xFFF
6027 #define   QAM_DQ_TAP_IM_EL22_TAP__PRE                                       0x2
6028 
6029 #define QAM_DQ_TAP_RE_EL23__A                                               0x144004E
6030 #define QAM_DQ_TAP_RE_EL23__W                                               12
6031 #define QAM_DQ_TAP_RE_EL23__M                                               0xFFF
6032 #define QAM_DQ_TAP_RE_EL23__PRE                                             0x2
6033 
6034 #define   QAM_DQ_TAP_RE_EL23_TAP__B                                         0
6035 #define   QAM_DQ_TAP_RE_EL23_TAP__W                                         12
6036 #define   QAM_DQ_TAP_RE_EL23_TAP__M                                         0xFFF
6037 #define   QAM_DQ_TAP_RE_EL23_TAP__PRE                                       0x2
6038 
6039 #define QAM_DQ_TAP_IM_EL23__A                                               0x144004F
6040 #define QAM_DQ_TAP_IM_EL23__W                                               12
6041 #define QAM_DQ_TAP_IM_EL23__M                                               0xFFF
6042 #define QAM_DQ_TAP_IM_EL23__PRE                                             0x2
6043 
6044 #define   QAM_DQ_TAP_IM_EL23_TAP__B                                         0
6045 #define   QAM_DQ_TAP_IM_EL23_TAP__W                                         12
6046 #define   QAM_DQ_TAP_IM_EL23_TAP__M                                         0xFFF
6047 #define   QAM_DQ_TAP_IM_EL23_TAP__PRE                                       0x2
6048 
6049 #define QAM_DQ_TAP_RE_EL24__A                                               0x1440050
6050 #define QAM_DQ_TAP_RE_EL24__W                                               12
6051 #define QAM_DQ_TAP_RE_EL24__M                                               0xFFF
6052 #define QAM_DQ_TAP_RE_EL24__PRE                                             0x2
6053 
6054 #define   QAM_DQ_TAP_RE_EL24_TAP__B                                         0
6055 #define   QAM_DQ_TAP_RE_EL24_TAP__W                                         12
6056 #define   QAM_DQ_TAP_RE_EL24_TAP__M                                         0xFFF
6057 #define   QAM_DQ_TAP_RE_EL24_TAP__PRE                                       0x2
6058 
6059 #define QAM_DQ_TAP_IM_EL24__A                                               0x1440051
6060 #define QAM_DQ_TAP_IM_EL24__W                                               12
6061 #define QAM_DQ_TAP_IM_EL24__M                                               0xFFF
6062 #define QAM_DQ_TAP_IM_EL24__PRE                                             0x2
6063 
6064 #define   QAM_DQ_TAP_IM_EL24_TAP__B                                         0
6065 #define   QAM_DQ_TAP_IM_EL24_TAP__W                                         12
6066 #define   QAM_DQ_TAP_IM_EL24_TAP__M                                         0xFFF
6067 #define   QAM_DQ_TAP_IM_EL24_TAP__PRE                                       0x2
6068 
6069 #define QAM_DQ_TAP_RE_EL25__A                                               0x1440052
6070 #define QAM_DQ_TAP_RE_EL25__W                                               12
6071 #define QAM_DQ_TAP_RE_EL25__M                                               0xFFF
6072 #define QAM_DQ_TAP_RE_EL25__PRE                                             0x2
6073 
6074 #define   QAM_DQ_TAP_RE_EL25_TAP__B                                         0
6075 #define   QAM_DQ_TAP_RE_EL25_TAP__W                                         12
6076 #define   QAM_DQ_TAP_RE_EL25_TAP__M                                         0xFFF
6077 #define   QAM_DQ_TAP_RE_EL25_TAP__PRE                                       0x2
6078 
6079 #define QAM_DQ_TAP_IM_EL25__A                                               0x1440053
6080 #define QAM_DQ_TAP_IM_EL25__W                                               12
6081 #define QAM_DQ_TAP_IM_EL25__M                                               0xFFF
6082 #define QAM_DQ_TAP_IM_EL25__PRE                                             0x2
6083 
6084 #define   QAM_DQ_TAP_IM_EL25_TAP__B                                         0
6085 #define   QAM_DQ_TAP_IM_EL25_TAP__W                                         12
6086 #define   QAM_DQ_TAP_IM_EL25_TAP__M                                         0xFFF
6087 #define   QAM_DQ_TAP_IM_EL25_TAP__PRE                                       0x2
6088 
6089 #define QAM_DQ_TAP_RE_EL26__A                                               0x1440054
6090 #define QAM_DQ_TAP_RE_EL26__W                                               12
6091 #define QAM_DQ_TAP_RE_EL26__M                                               0xFFF
6092 #define QAM_DQ_TAP_RE_EL26__PRE                                             0x2
6093 
6094 #define   QAM_DQ_TAP_RE_EL26_TAP__B                                         0
6095 #define   QAM_DQ_TAP_RE_EL26_TAP__W                                         12
6096 #define   QAM_DQ_TAP_RE_EL26_TAP__M                                         0xFFF
6097 #define   QAM_DQ_TAP_RE_EL26_TAP__PRE                                       0x2
6098 
6099 #define QAM_DQ_TAP_IM_EL26__A                                               0x1440055
6100 #define QAM_DQ_TAP_IM_EL26__W                                               12
6101 #define QAM_DQ_TAP_IM_EL26__M                                               0xFFF
6102 #define QAM_DQ_TAP_IM_EL26__PRE                                             0x2
6103 
6104 #define   QAM_DQ_TAP_IM_EL26_TAP__B                                         0
6105 #define   QAM_DQ_TAP_IM_EL26_TAP__W                                         12
6106 #define   QAM_DQ_TAP_IM_EL26_TAP__M                                         0xFFF
6107 #define   QAM_DQ_TAP_IM_EL26_TAP__PRE                                       0x2
6108 
6109 #define QAM_DQ_TAP_RE_EL27__A                                               0x1440056
6110 #define QAM_DQ_TAP_RE_EL27__W                                               12
6111 #define QAM_DQ_TAP_RE_EL27__M                                               0xFFF
6112 #define QAM_DQ_TAP_RE_EL27__PRE                                             0x2
6113 
6114 #define   QAM_DQ_TAP_RE_EL27_TAP__B                                         0
6115 #define   QAM_DQ_TAP_RE_EL27_TAP__W                                         12
6116 #define   QAM_DQ_TAP_RE_EL27_TAP__M                                         0xFFF
6117 #define   QAM_DQ_TAP_RE_EL27_TAP__PRE                                       0x2
6118 
6119 #define QAM_DQ_TAP_IM_EL27__A                                               0x1440057
6120 #define QAM_DQ_TAP_IM_EL27__W                                               12
6121 #define QAM_DQ_TAP_IM_EL27__M                                               0xFFF
6122 #define QAM_DQ_TAP_IM_EL27__PRE                                             0x2
6123 
6124 #define   QAM_DQ_TAP_IM_EL27_TAP__B                                         0
6125 #define   QAM_DQ_TAP_IM_EL27_TAP__W                                         12
6126 #define   QAM_DQ_TAP_IM_EL27_TAP__M                                         0xFFF
6127 #define   QAM_DQ_TAP_IM_EL27_TAP__PRE                                       0x2
6128 
6129 #define QAM_LC_COMM_EXEC__A                                                 0x1450000
6130 #define QAM_LC_COMM_EXEC__W                                                 2
6131 #define QAM_LC_COMM_EXEC__M                                                 0x3
6132 #define QAM_LC_COMM_EXEC__PRE                                               0x0
6133 #define   QAM_LC_COMM_EXEC_STOP                                             0x0
6134 #define   QAM_LC_COMM_EXEC_ACTIVE                                           0x1
6135 #define   QAM_LC_COMM_EXEC_HOLD                                             0x2
6136 
6137 #define QAM_LC_COMM_MB__A                                                   0x1450002
6138 #define QAM_LC_COMM_MB__W                                                   2
6139 #define QAM_LC_COMM_MB__M                                                   0x3
6140 #define QAM_LC_COMM_MB__PRE                                                 0x0
6141 #define   QAM_LC_COMM_MB_CTL__B                                             0
6142 #define   QAM_LC_COMM_MB_CTL__W                                             1
6143 #define   QAM_LC_COMM_MB_CTL__M                                             0x1
6144 #define   QAM_LC_COMM_MB_CTL__PRE                                           0x0
6145 #define     QAM_LC_COMM_MB_CTL_OFF                                          0x0
6146 #define     QAM_LC_COMM_MB_CTL_ON                                           0x1
6147 #define   QAM_LC_COMM_MB_OBS__B                                             1
6148 #define   QAM_LC_COMM_MB_OBS__W                                             1
6149 #define   QAM_LC_COMM_MB_OBS__M                                             0x2
6150 #define   QAM_LC_COMM_MB_OBS__PRE                                           0x0
6151 #define     QAM_LC_COMM_MB_OBS_OFF                                          0x0
6152 #define     QAM_LC_COMM_MB_OBS_ON                                           0x2
6153 
6154 #define QAM_LC_COMM_INT_REQ__A                                              0x1450003
6155 #define QAM_LC_COMM_INT_REQ__W                                              1
6156 #define QAM_LC_COMM_INT_REQ__M                                              0x1
6157 #define QAM_LC_COMM_INT_REQ__PRE                                            0x0
6158 #define QAM_LC_COMM_INT_STA__A                                              0x1450005
6159 #define QAM_LC_COMM_INT_STA__W                                              3
6160 #define QAM_LC_COMM_INT_STA__M                                              0x7
6161 #define QAM_LC_COMM_INT_STA__PRE                                            0x0
6162 
6163 #define   QAM_LC_COMM_INT_STA_READY__B                                      0
6164 #define   QAM_LC_COMM_INT_STA_READY__W                                      1
6165 #define   QAM_LC_COMM_INT_STA_READY__M                                      0x1
6166 #define   QAM_LC_COMM_INT_STA_READY__PRE                                    0x0
6167 
6168 #define   QAM_LC_COMM_INT_STA_OVERFLOW__B                                   1
6169 #define   QAM_LC_COMM_INT_STA_OVERFLOW__W                                   1
6170 #define   QAM_LC_COMM_INT_STA_OVERFLOW__M                                   0x2
6171 #define   QAM_LC_COMM_INT_STA_OVERFLOW__PRE                                 0x0
6172 
6173 #define   QAM_LC_COMM_INT_STA_FREQ_WRAP__B                                  2
6174 #define   QAM_LC_COMM_INT_STA_FREQ_WRAP__W                                  1
6175 #define   QAM_LC_COMM_INT_STA_FREQ_WRAP__M                                  0x4
6176 #define   QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE                                0x0
6177 
6178 #define QAM_LC_COMM_INT_MSK__A                                              0x1450006
6179 #define QAM_LC_COMM_INT_MSK__W                                              3
6180 #define QAM_LC_COMM_INT_MSK__M                                              0x7
6181 #define QAM_LC_COMM_INT_MSK__PRE                                            0x0
6182 #define   QAM_LC_COMM_INT_MSK_READY__B                                      0
6183 #define   QAM_LC_COMM_INT_MSK_READY__W                                      1
6184 #define   QAM_LC_COMM_INT_MSK_READY__M                                      0x1
6185 #define   QAM_LC_COMM_INT_MSK_READY__PRE                                    0x0
6186 #define   QAM_LC_COMM_INT_MSK_OVERFLOW__B                                   1
6187 #define   QAM_LC_COMM_INT_MSK_OVERFLOW__W                                   1
6188 #define   QAM_LC_COMM_INT_MSK_OVERFLOW__M                                   0x2
6189 #define   QAM_LC_COMM_INT_MSK_OVERFLOW__PRE                                 0x0
6190 #define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__B                                  2
6191 #define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__W                                  1
6192 #define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__M                                  0x4
6193 #define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE                                0x0
6194 
6195 #define QAM_LC_COMM_INT_STM__A                                              0x1450007
6196 #define QAM_LC_COMM_INT_STM__W                                              3
6197 #define QAM_LC_COMM_INT_STM__M                                              0x7
6198 #define QAM_LC_COMM_INT_STM__PRE                                            0x0
6199 #define   QAM_LC_COMM_INT_STM_READY__B                                      0
6200 #define   QAM_LC_COMM_INT_STM_READY__W                                      1
6201 #define   QAM_LC_COMM_INT_STM_READY__M                                      0x1
6202 #define   QAM_LC_COMM_INT_STM_READY__PRE                                    0x0
6203 #define   QAM_LC_COMM_INT_STM_OVERFLOW__B                                   1
6204 #define   QAM_LC_COMM_INT_STM_OVERFLOW__W                                   1
6205 #define   QAM_LC_COMM_INT_STM_OVERFLOW__M                                   0x2
6206 #define   QAM_LC_COMM_INT_STM_OVERFLOW__PRE                                 0x0
6207 #define   QAM_LC_COMM_INT_STM_FREQ_WRAP__B                                  2
6208 #define   QAM_LC_COMM_INT_STM_FREQ_WRAP__W                                  1
6209 #define   QAM_LC_COMM_INT_STM_FREQ_WRAP__M                                  0x4
6210 #define   QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE                                0x0
6211 
6212 #define QAM_LC_MODE__A                                                      0x1450010
6213 #define QAM_LC_MODE__W                                                      3
6214 #define QAM_LC_MODE__M                                                      0x7
6215 #define QAM_LC_MODE__PRE                                                    0x7
6216 
6217 #define   QAM_LC_MODE_ENABLE_A__B                                           0
6218 #define   QAM_LC_MODE_ENABLE_A__W                                           1
6219 #define   QAM_LC_MODE_ENABLE_A__M                                           0x1
6220 #define   QAM_LC_MODE_ENABLE_A__PRE                                         0x1
6221 
6222 #define   QAM_LC_MODE_ENABLE_F__B                                           1
6223 #define   QAM_LC_MODE_ENABLE_F__W                                           1
6224 #define   QAM_LC_MODE_ENABLE_F__M                                           0x2
6225 #define   QAM_LC_MODE_ENABLE_F__PRE                                         0x2
6226 
6227 #define   QAM_LC_MODE_ENABLE_R__B                                           2
6228 #define   QAM_LC_MODE_ENABLE_R__W                                           1
6229 #define   QAM_LC_MODE_ENABLE_R__M                                           0x4
6230 #define   QAM_LC_MODE_ENABLE_R__PRE                                         0x4
6231 
6232 #define QAM_LC_CA__A                                                        0x1450011
6233 #define QAM_LC_CA__W                                                        6
6234 #define QAM_LC_CA__M                                                        0x3F
6235 #define QAM_LC_CA__PRE                                                      0x28
6236 
6237 #define   QAM_LC_CA_COEF__B                                                 0
6238 #define   QAM_LC_CA_COEF__W                                                 6
6239 #define   QAM_LC_CA_COEF__M                                                 0x3F
6240 #define   QAM_LC_CA_COEF__PRE                                               0x28
6241 
6242 #define QAM_LC_CF__A                                                        0x1450012
6243 #define QAM_LC_CF__W                                                        8
6244 #define QAM_LC_CF__M                                                        0xFF
6245 #define QAM_LC_CF__PRE                                                      0x8C
6246 
6247 #define   QAM_LC_CF_COEF__B                                                 0
6248 #define   QAM_LC_CF_COEF__W                                                 8
6249 #define   QAM_LC_CF_COEF__M                                                 0xFF
6250 #define   QAM_LC_CF_COEF__PRE                                               0x8C
6251 
6252 #define QAM_LC_CF1__A                                                       0x1450013
6253 #define QAM_LC_CF1__W                                                       8
6254 #define QAM_LC_CF1__M                                                       0xFF
6255 #define QAM_LC_CF1__PRE                                                     0x1E
6256 
6257 #define   QAM_LC_CF1_COEF__B                                                0
6258 #define   QAM_LC_CF1_COEF__W                                                8
6259 #define   QAM_LC_CF1_COEF__M                                                0xFF
6260 #define   QAM_LC_CF1_COEF__PRE                                              0x1E
6261 
6262 #define QAM_LC_CP__A                                                        0x1450014
6263 #define QAM_LC_CP__W                                                        8
6264 #define QAM_LC_CP__M                                                        0xFF
6265 #define QAM_LC_CP__PRE                                                      0x78
6266 
6267 #define   QAM_LC_CP_COEF__B                                                 0
6268 #define   QAM_LC_CP_COEF__W                                                 8
6269 #define   QAM_LC_CP_COEF__M                                                 0xFF
6270 #define   QAM_LC_CP_COEF__PRE                                               0x78
6271 
6272 #define QAM_LC_CI__A                                                        0x1450015
6273 #define QAM_LC_CI__W                                                        8
6274 #define QAM_LC_CI__M                                                        0xFF
6275 #define QAM_LC_CI__PRE                                                      0x46
6276 
6277 #define   QAM_LC_CI_COEF__B                                                 0
6278 #define   QAM_LC_CI_COEF__W                                                 8
6279 #define   QAM_LC_CI_COEF__M                                                 0xFF
6280 #define   QAM_LC_CI_COEF__PRE                                               0x46
6281 
6282 #define QAM_LC_EP__A                                                        0x1450016
6283 #define QAM_LC_EP__W                                                        6
6284 #define QAM_LC_EP__M                                                        0x3F
6285 #define QAM_LC_EP__PRE                                                      0x0
6286 
6287 #define   QAM_LC_EP_COEF__B                                                 0
6288 #define   QAM_LC_EP_COEF__W                                                 6
6289 #define   QAM_LC_EP_COEF__M                                                 0x3F
6290 #define   QAM_LC_EP_COEF__PRE                                               0x0
6291 
6292 #define QAM_LC_EI__A                                                        0x1450017
6293 #define QAM_LC_EI__W                                                        6
6294 #define QAM_LC_EI__M                                                        0x3F
6295 #define QAM_LC_EI__PRE                                                      0x0
6296 
6297 #define   QAM_LC_EI_COEF__B                                                 0
6298 #define   QAM_LC_EI_COEF__W                                                 6
6299 #define   QAM_LC_EI_COEF__M                                                 0x3F
6300 #define   QAM_LC_EI_COEF__PRE                                               0x0
6301 
6302 #define QAM_LC_QUAL_TAB0__A                                                 0x1450018
6303 #define QAM_LC_QUAL_TAB0__W                                                 5
6304 #define QAM_LC_QUAL_TAB0__M                                                 0x1F
6305 #define QAM_LC_QUAL_TAB0__PRE                                               0x1
6306 
6307 #define   QAM_LC_QUAL_TAB0_VALUE__B                                         0
6308 #define   QAM_LC_QUAL_TAB0_VALUE__W                                         5
6309 #define   QAM_LC_QUAL_TAB0_VALUE__M                                         0x1F
6310 #define   QAM_LC_QUAL_TAB0_VALUE__PRE                                       0x1
6311 
6312 #define QAM_LC_QUAL_TAB1__A                                                 0x1450019
6313 #define QAM_LC_QUAL_TAB1__W                                                 5
6314 #define QAM_LC_QUAL_TAB1__M                                                 0x1F
6315 #define QAM_LC_QUAL_TAB1__PRE                                               0x1
6316 
6317 #define   QAM_LC_QUAL_TAB1_VALUE__B                                         0
6318 #define   QAM_LC_QUAL_TAB1_VALUE__W                                         5
6319 #define   QAM_LC_QUAL_TAB1_VALUE__M                                         0x1F
6320 #define   QAM_LC_QUAL_TAB1_VALUE__PRE                                       0x1
6321 
6322 #define QAM_LC_QUAL_TAB2__A                                                 0x145001A
6323 #define QAM_LC_QUAL_TAB2__W                                                 5
6324 #define QAM_LC_QUAL_TAB2__M                                                 0x1F
6325 #define QAM_LC_QUAL_TAB2__PRE                                               0x1
6326 
6327 #define   QAM_LC_QUAL_TAB2_VALUE__B                                         0
6328 #define   QAM_LC_QUAL_TAB2_VALUE__W                                         5
6329 #define   QAM_LC_QUAL_TAB2_VALUE__M                                         0x1F
6330 #define   QAM_LC_QUAL_TAB2_VALUE__PRE                                       0x1
6331 
6332 #define QAM_LC_QUAL_TAB3__A                                                 0x145001B
6333 #define QAM_LC_QUAL_TAB3__W                                                 5
6334 #define QAM_LC_QUAL_TAB3__M                                                 0x1F
6335 #define QAM_LC_QUAL_TAB3__PRE                                               0x1
6336 
6337 #define   QAM_LC_QUAL_TAB3_VALUE__B                                         0
6338 #define   QAM_LC_QUAL_TAB3_VALUE__W                                         5
6339 #define   QAM_LC_QUAL_TAB3_VALUE__M                                         0x1F
6340 #define   QAM_LC_QUAL_TAB3_VALUE__PRE                                       0x1
6341 
6342 #define QAM_LC_QUAL_TAB4__A                                                 0x145001C
6343 #define QAM_LC_QUAL_TAB4__W                                                 5
6344 #define QAM_LC_QUAL_TAB4__M                                                 0x1F
6345 #define QAM_LC_QUAL_TAB4__PRE                                               0x1
6346 
6347 #define   QAM_LC_QUAL_TAB4_VALUE__B                                         0
6348 #define   QAM_LC_QUAL_TAB4_VALUE__W                                         5
6349 #define   QAM_LC_QUAL_TAB4_VALUE__M                                         0x1F
6350 #define   QAM_LC_QUAL_TAB4_VALUE__PRE                                       0x1
6351 
6352 #define QAM_LC_QUAL_TAB5__A                                                 0x145001D
6353 #define QAM_LC_QUAL_TAB5__W                                                 5
6354 #define QAM_LC_QUAL_TAB5__M                                                 0x1F
6355 #define QAM_LC_QUAL_TAB5__PRE                                               0x1
6356 
6357 #define   QAM_LC_QUAL_TAB5_VALUE__B                                         0
6358 #define   QAM_LC_QUAL_TAB5_VALUE__W                                         5
6359 #define   QAM_LC_QUAL_TAB5_VALUE__M                                         0x1F
6360 #define   QAM_LC_QUAL_TAB5_VALUE__PRE                                       0x1
6361 
6362 #define QAM_LC_QUAL_TAB6__A                                                 0x145001E
6363 #define QAM_LC_QUAL_TAB6__W                                                 5
6364 #define QAM_LC_QUAL_TAB6__M                                                 0x1F
6365 #define QAM_LC_QUAL_TAB6__PRE                                               0x1
6366 
6367 #define   QAM_LC_QUAL_TAB6_VALUE__B                                         0
6368 #define   QAM_LC_QUAL_TAB6_VALUE__W                                         5
6369 #define   QAM_LC_QUAL_TAB6_VALUE__M                                         0x1F
6370 #define   QAM_LC_QUAL_TAB6_VALUE__PRE                                       0x1
6371 
6372 #define QAM_LC_QUAL_TAB8__A                                                 0x145001F
6373 #define QAM_LC_QUAL_TAB8__W                                                 5
6374 #define QAM_LC_QUAL_TAB8__M                                                 0x1F
6375 #define QAM_LC_QUAL_TAB8__PRE                                               0x1
6376 
6377 #define   QAM_LC_QUAL_TAB8_VALUE__B                                         0
6378 #define   QAM_LC_QUAL_TAB8_VALUE__W                                         5
6379 #define   QAM_LC_QUAL_TAB8_VALUE__M                                         0x1F
6380 #define   QAM_LC_QUAL_TAB8_VALUE__PRE                                       0x1
6381 
6382 #define QAM_LC_QUAL_TAB9__A                                                 0x1450020
6383 #define QAM_LC_QUAL_TAB9__W                                                 5
6384 #define QAM_LC_QUAL_TAB9__M                                                 0x1F
6385 #define QAM_LC_QUAL_TAB9__PRE                                               0x1
6386 
6387 #define   QAM_LC_QUAL_TAB9_VALUE__B                                         0
6388 #define   QAM_LC_QUAL_TAB9_VALUE__W                                         5
6389 #define   QAM_LC_QUAL_TAB9_VALUE__M                                         0x1F
6390 #define   QAM_LC_QUAL_TAB9_VALUE__PRE                                       0x1
6391 
6392 #define QAM_LC_QUAL_TAB10__A                                                0x1450021
6393 #define QAM_LC_QUAL_TAB10__W                                                5
6394 #define QAM_LC_QUAL_TAB10__M                                                0x1F
6395 #define QAM_LC_QUAL_TAB10__PRE                                              0x1
6396 
6397 #define   QAM_LC_QUAL_TAB10_VALUE__B                                        0
6398 #define   QAM_LC_QUAL_TAB10_VALUE__W                                        5
6399 #define   QAM_LC_QUAL_TAB10_VALUE__M                                        0x1F
6400 #define   QAM_LC_QUAL_TAB10_VALUE__PRE                                      0x1
6401 
6402 #define QAM_LC_QUAL_TAB12__A                                                0x1450022
6403 #define QAM_LC_QUAL_TAB12__W                                                5
6404 #define QAM_LC_QUAL_TAB12__M                                                0x1F
6405 #define QAM_LC_QUAL_TAB12__PRE                                              0x1
6406 
6407 #define   QAM_LC_QUAL_TAB12_VALUE__B                                        0
6408 #define   QAM_LC_QUAL_TAB12_VALUE__W                                        5
6409 #define   QAM_LC_QUAL_TAB12_VALUE__M                                        0x1F
6410 #define   QAM_LC_QUAL_TAB12_VALUE__PRE                                      0x1
6411 
6412 #define QAM_LC_QUAL_TAB15__A                                                0x1450023
6413 #define QAM_LC_QUAL_TAB15__W                                                5
6414 #define QAM_LC_QUAL_TAB15__M                                                0x1F
6415 #define QAM_LC_QUAL_TAB15__PRE                                              0x1
6416 
6417 #define   QAM_LC_QUAL_TAB15_VALUE__B                                        0
6418 #define   QAM_LC_QUAL_TAB15_VALUE__W                                        5
6419 #define   QAM_LC_QUAL_TAB15_VALUE__M                                        0x1F
6420 #define   QAM_LC_QUAL_TAB15_VALUE__PRE                                      0x1
6421 
6422 #define QAM_LC_QUAL_TAB16__A                                                0x1450024
6423 #define QAM_LC_QUAL_TAB16__W                                                5
6424 #define QAM_LC_QUAL_TAB16__M                                                0x1F
6425 #define QAM_LC_QUAL_TAB16__PRE                                              0x1
6426 
6427 #define   QAM_LC_QUAL_TAB16_VALUE__B                                        0
6428 #define   QAM_LC_QUAL_TAB16_VALUE__W                                        5
6429 #define   QAM_LC_QUAL_TAB16_VALUE__M                                        0x1F
6430 #define   QAM_LC_QUAL_TAB16_VALUE__PRE                                      0x1
6431 
6432 #define QAM_LC_QUAL_TAB20__A                                                0x1450025
6433 #define QAM_LC_QUAL_TAB20__W                                                5
6434 #define QAM_LC_QUAL_TAB20__M                                                0x1F
6435 #define QAM_LC_QUAL_TAB20__PRE                                              0x1
6436 
6437 #define   QAM_LC_QUAL_TAB20_VALUE__B                                        0
6438 #define   QAM_LC_QUAL_TAB20_VALUE__W                                        5
6439 #define   QAM_LC_QUAL_TAB20_VALUE__M                                        0x1F
6440 #define   QAM_LC_QUAL_TAB20_VALUE__PRE                                      0x1
6441 
6442 #define QAM_LC_QUAL_TAB25__A                                                0x1450026
6443 #define QAM_LC_QUAL_TAB25__W                                                5
6444 #define QAM_LC_QUAL_TAB25__M                                                0x1F
6445 #define QAM_LC_QUAL_TAB25__PRE                                              0x1
6446 
6447 #define   QAM_LC_QUAL_TAB25_VALUE__B                                        0
6448 #define   QAM_LC_QUAL_TAB25_VALUE__W                                        5
6449 #define   QAM_LC_QUAL_TAB25_VALUE__M                                        0x1F
6450 #define   QAM_LC_QUAL_TAB25_VALUE__PRE                                      0x1
6451 
6452 #define QAM_LC_EQ_TIMING__A                                                 0x1450027
6453 #define QAM_LC_EQ_TIMING__W                                                 10
6454 #define QAM_LC_EQ_TIMING__M                                                 0x3FF
6455 #define QAM_LC_EQ_TIMING__PRE                                               0x0
6456 
6457 #define   QAM_LC_EQ_TIMING_OFFS__B                                          0
6458 #define   QAM_LC_EQ_TIMING_OFFS__W                                          10
6459 #define   QAM_LC_EQ_TIMING_OFFS__M                                          0x3FF
6460 #define   QAM_LC_EQ_TIMING_OFFS__PRE                                        0x0
6461 
6462 #define QAM_LC_LPF_FACTORP__A                                               0x1450028
6463 #define QAM_LC_LPF_FACTORP__W                                               3
6464 #define QAM_LC_LPF_FACTORP__M                                               0x7
6465 #define QAM_LC_LPF_FACTORP__PRE                                             0x3
6466 
6467 #define   QAM_LC_LPF_FACTORP_FACTOR__B                                      0
6468 #define   QAM_LC_LPF_FACTORP_FACTOR__W                                      3
6469 #define   QAM_LC_LPF_FACTORP_FACTOR__M                                      0x7
6470 #define   QAM_LC_LPF_FACTORP_FACTOR__PRE                                    0x3
6471 
6472 #define QAM_LC_LPF_FACTORI__A                                               0x1450029
6473 #define QAM_LC_LPF_FACTORI__W                                               3
6474 #define QAM_LC_LPF_FACTORI__M                                               0x7
6475 #define QAM_LC_LPF_FACTORI__PRE                                             0x3
6476 
6477 #define   QAM_LC_LPF_FACTORI_FACTOR__B                                      0
6478 #define   QAM_LC_LPF_FACTORI_FACTOR__W                                      3
6479 #define   QAM_LC_LPF_FACTORI_FACTOR__M                                      0x7
6480 #define   QAM_LC_LPF_FACTORI_FACTOR__PRE                                    0x3
6481 
6482 #define QAM_LC_RATE_LIMIT__A                                                0x145002A
6483 #define QAM_LC_RATE_LIMIT__W                                                2
6484 #define QAM_LC_RATE_LIMIT__M                                                0x3
6485 #define QAM_LC_RATE_LIMIT__PRE                                              0x3
6486 
6487 #define   QAM_LC_RATE_LIMIT_LIMIT__B                                        0
6488 #define   QAM_LC_RATE_LIMIT_LIMIT__W                                        2
6489 #define   QAM_LC_RATE_LIMIT_LIMIT__M                                        0x3
6490 #define   QAM_LC_RATE_LIMIT_LIMIT__PRE                                      0x3
6491 
6492 #define QAM_LC_SYMBOL_FREQ__A                                               0x145002B
6493 #define QAM_LC_SYMBOL_FREQ__W                                               10
6494 #define QAM_LC_SYMBOL_FREQ__M                                               0x3FF
6495 #define QAM_LC_SYMBOL_FREQ__PRE                                             0x199
6496 
6497 #define   QAM_LC_SYMBOL_FREQ_FREQ__B                                        0
6498 #define   QAM_LC_SYMBOL_FREQ_FREQ__W                                        10
6499 #define   QAM_LC_SYMBOL_FREQ_FREQ__M                                        0x3FF
6500 #define   QAM_LC_SYMBOL_FREQ_FREQ__PRE                                      0x199
6501 #define     QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_64                                0x197
6502 #define     QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256                               0x1B2
6503 
6504 #define QAM_LC_MTA_LENGTH__A                                                0x145002C
6505 #define QAM_LC_MTA_LENGTH__W                                                2
6506 #define QAM_LC_MTA_LENGTH__M                                                0x3
6507 #define QAM_LC_MTA_LENGTH__PRE                                              0x2
6508 
6509 #define   QAM_LC_MTA_LENGTH_LENGTH__B                                       0
6510 #define   QAM_LC_MTA_LENGTH_LENGTH__W                                       2
6511 #define   QAM_LC_MTA_LENGTH_LENGTH__M                                       0x3
6512 #define   QAM_LC_MTA_LENGTH_LENGTH__PRE                                     0x2
6513 
6514 #define QAM_LC_AMP_ACCU__A                                                  0x145002D
6515 #define QAM_LC_AMP_ACCU__W                                                  14
6516 #define QAM_LC_AMP_ACCU__M                                                  0x3FFF
6517 #define QAM_LC_AMP_ACCU__PRE                                                0x600
6518 
6519 #define   QAM_LC_AMP_ACCU_ACCU__B                                           0
6520 #define   QAM_LC_AMP_ACCU_ACCU__W                                           14
6521 #define   QAM_LC_AMP_ACCU_ACCU__M                                           0x3FFF
6522 #define   QAM_LC_AMP_ACCU_ACCU__PRE                                         0x600
6523 
6524 #define QAM_LC_FREQ_ACCU__A                                                 0x145002E
6525 #define QAM_LC_FREQ_ACCU__W                                                 10
6526 #define QAM_LC_FREQ_ACCU__M                                                 0x3FF
6527 #define QAM_LC_FREQ_ACCU__PRE                                               0x0
6528 
6529 #define   QAM_LC_FREQ_ACCU_ACCU__B                                          0
6530 #define   QAM_LC_FREQ_ACCU_ACCU__W                                          10
6531 #define   QAM_LC_FREQ_ACCU_ACCU__M                                          0x3FF
6532 #define   QAM_LC_FREQ_ACCU_ACCU__PRE                                        0x0
6533 
6534 #define QAM_LC_RATE_ACCU__A                                                 0x145002F
6535 #define QAM_LC_RATE_ACCU__W                                                 10
6536 #define QAM_LC_RATE_ACCU__M                                                 0x3FF
6537 #define QAM_LC_RATE_ACCU__PRE                                               0x0
6538 
6539 #define   QAM_LC_RATE_ACCU_ACCU__B                                          0
6540 #define   QAM_LC_RATE_ACCU_ACCU__W                                          10
6541 #define   QAM_LC_RATE_ACCU_ACCU__M                                          0x3FF
6542 #define   QAM_LC_RATE_ACCU_ACCU__PRE                                        0x0
6543 
6544 #define QAM_LC_AMPLITUDE__A                                                 0x1450030
6545 #define QAM_LC_AMPLITUDE__W                                                 10
6546 #define QAM_LC_AMPLITUDE__M                                                 0x3FF
6547 #define QAM_LC_AMPLITUDE__PRE                                               0x0
6548 
6549 #define   QAM_LC_AMPLITUDE_SIZE__B                                          0
6550 #define   QAM_LC_AMPLITUDE_SIZE__W                                          10
6551 #define   QAM_LC_AMPLITUDE_SIZE__M                                          0x3FF
6552 #define   QAM_LC_AMPLITUDE_SIZE__PRE                                        0x0
6553 
6554 #define QAM_LC_RAD_ERROR__A                                                 0x1450031
6555 #define QAM_LC_RAD_ERROR__W                                                 10
6556 #define QAM_LC_RAD_ERROR__M                                                 0x3FF
6557 #define QAM_LC_RAD_ERROR__PRE                                               0x0
6558 
6559 #define   QAM_LC_RAD_ERROR_SIZE__B                                          0
6560 #define   QAM_LC_RAD_ERROR_SIZE__W                                          10
6561 #define   QAM_LC_RAD_ERROR_SIZE__M                                          0x3FF
6562 #define   QAM_LC_RAD_ERROR_SIZE__PRE                                        0x0
6563 
6564 #define QAM_LC_FREQ_OFFS__A                                                 0x1450032
6565 #define QAM_LC_FREQ_OFFS__W                                                 10
6566 #define QAM_LC_FREQ_OFFS__M                                                 0x3FF
6567 #define QAM_LC_FREQ_OFFS__PRE                                               0x0
6568 
6569 #define   QAM_LC_FREQ_OFFS_OFFS__B                                          0
6570 #define   QAM_LC_FREQ_OFFS_OFFS__W                                          10
6571 #define   QAM_LC_FREQ_OFFS_OFFS__M                                          0x3FF
6572 #define   QAM_LC_FREQ_OFFS_OFFS__PRE                                        0x0
6573 
6574 #define QAM_LC_PHASE_ERROR__A                                               0x1450033
6575 #define QAM_LC_PHASE_ERROR__W                                               10
6576 #define QAM_LC_PHASE_ERROR__M                                               0x3FF
6577 #define QAM_LC_PHASE_ERROR__PRE                                             0x0
6578 
6579 #define   QAM_LC_PHASE_ERROR_SIZE__B                                        0
6580 #define   QAM_LC_PHASE_ERROR_SIZE__W                                        10
6581 #define   QAM_LC_PHASE_ERROR_SIZE__M                                        0x3FF
6582 #define   QAM_LC_PHASE_ERROR_SIZE__PRE                                      0x0
6583 
6584 #define QAM_VD_COMM_EXEC__A                                                 0x1460000
6585 #define QAM_VD_COMM_EXEC__W                                                 2
6586 #define QAM_VD_COMM_EXEC__M                                                 0x3
6587 #define QAM_VD_COMM_EXEC__PRE                                               0x0
6588 #define   QAM_VD_COMM_EXEC_STOP                                             0x0
6589 #define   QAM_VD_COMM_EXEC_ACTIVE                                           0x1
6590 #define   QAM_VD_COMM_EXEC_HOLD                                             0x2
6591 
6592 #define QAM_VD_COMM_MB__A                                                   0x1460002
6593 #define QAM_VD_COMM_MB__W                                                   2
6594 #define QAM_VD_COMM_MB__M                                                   0x3
6595 #define QAM_VD_COMM_MB__PRE                                                 0x0
6596 #define   QAM_VD_COMM_MB_CTL__B                                             0
6597 #define   QAM_VD_COMM_MB_CTL__W                                             1
6598 #define   QAM_VD_COMM_MB_CTL__M                                             0x1
6599 #define   QAM_VD_COMM_MB_CTL__PRE                                           0x0
6600 #define     QAM_VD_COMM_MB_CTL_OFF                                          0x0
6601 #define     QAM_VD_COMM_MB_CTL_ON                                           0x1
6602 #define   QAM_VD_COMM_MB_OBS__B                                             1
6603 #define   QAM_VD_COMM_MB_OBS__W                                             1
6604 #define   QAM_VD_COMM_MB_OBS__M                                             0x2
6605 #define   QAM_VD_COMM_MB_OBS__PRE                                           0x0
6606 #define     QAM_VD_COMM_MB_OBS_OFF                                          0x0
6607 #define     QAM_VD_COMM_MB_OBS_ON                                           0x2
6608 
6609 #define QAM_VD_COMM_INT_REQ__A                                              0x1460003
6610 #define QAM_VD_COMM_INT_REQ__W                                              1
6611 #define QAM_VD_COMM_INT_REQ__M                                              0x1
6612 #define QAM_VD_COMM_INT_REQ__PRE                                            0x0
6613 #define QAM_VD_COMM_INT_STA__A                                              0x1460005
6614 #define QAM_VD_COMM_INT_STA__W                                              2
6615 #define QAM_VD_COMM_INT_STA__M                                              0x3
6616 #define QAM_VD_COMM_INT_STA__PRE                                            0x0
6617 
6618 #define   QAM_VD_COMM_INT_STA_LOCK_INT__B                                   0
6619 #define   QAM_VD_COMM_INT_STA_LOCK_INT__W                                   1
6620 #define   QAM_VD_COMM_INT_STA_LOCK_INT__M                                   0x1
6621 #define   QAM_VD_COMM_INT_STA_LOCK_INT__PRE                                 0x0
6622 
6623 #define   QAM_VD_COMM_INT_STA_PERIOD_INT__B                                 1
6624 #define   QAM_VD_COMM_INT_STA_PERIOD_INT__W                                 1
6625 #define   QAM_VD_COMM_INT_STA_PERIOD_INT__M                                 0x2
6626 #define   QAM_VD_COMM_INT_STA_PERIOD_INT__PRE                               0x0
6627 
6628 #define QAM_VD_COMM_INT_MSK__A                                              0x1460006
6629 #define QAM_VD_COMM_INT_MSK__W                                              2
6630 #define QAM_VD_COMM_INT_MSK__M                                              0x3
6631 #define QAM_VD_COMM_INT_MSK__PRE                                            0x0
6632 #define   QAM_VD_COMM_INT_MSK_LOCK_INT__B                                   0
6633 #define   QAM_VD_COMM_INT_MSK_LOCK_INT__W                                   1
6634 #define   QAM_VD_COMM_INT_MSK_LOCK_INT__M                                   0x1
6635 #define   QAM_VD_COMM_INT_MSK_LOCK_INT__PRE                                 0x0
6636 #define   QAM_VD_COMM_INT_MSK_PERIOD_INT__B                                 1
6637 #define   QAM_VD_COMM_INT_MSK_PERIOD_INT__W                                 1
6638 #define   QAM_VD_COMM_INT_MSK_PERIOD_INT__M                                 0x2
6639 #define   QAM_VD_COMM_INT_MSK_PERIOD_INT__PRE                               0x0
6640 
6641 #define QAM_VD_COMM_INT_STM__A                                              0x1460007
6642 #define QAM_VD_COMM_INT_STM__W                                              2
6643 #define QAM_VD_COMM_INT_STM__M                                              0x3
6644 #define QAM_VD_COMM_INT_STM__PRE                                            0x0
6645 #define   QAM_VD_COMM_INT_STM_LOCK_INT__B                                   0
6646 #define   QAM_VD_COMM_INT_STM_LOCK_INT__W                                   1
6647 #define   QAM_VD_COMM_INT_STM_LOCK_INT__M                                   0x1
6648 #define   QAM_VD_COMM_INT_STM_LOCK_INT__PRE                                 0x0
6649 #define   QAM_VD_COMM_INT_STM_PERIOD_INT__B                                 1
6650 #define   QAM_VD_COMM_INT_STM_PERIOD_INT__W                                 1
6651 #define   QAM_VD_COMM_INT_STM_PERIOD_INT__M                                 0x2
6652 #define   QAM_VD_COMM_INT_STM_PERIOD_INT__PRE                               0x0
6653 
6654 #define QAM_VD_STATUS__A                                                    0x1460010
6655 #define QAM_VD_STATUS__W                                                    1
6656 #define QAM_VD_STATUS__M                                                    0x1
6657 #define QAM_VD_STATUS__PRE                                                  0x0
6658 
6659 #define   QAM_VD_STATUS_LOCK__B                                             0
6660 #define   QAM_VD_STATUS_LOCK__W                                             1
6661 #define   QAM_VD_STATUS_LOCK__M                                             0x1
6662 #define   QAM_VD_STATUS_LOCK__PRE                                           0x0
6663 
6664 #define QAM_VD_UNLOCK_CONTROL__A                                            0x1460011
6665 #define QAM_VD_UNLOCK_CONTROL__W                                            1
6666 #define QAM_VD_UNLOCK_CONTROL__M                                            0x1
6667 #define QAM_VD_UNLOCK_CONTROL__PRE                                          0x0
6668 
6669 #define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__B                              0
6670 #define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__W                              1
6671 #define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__M                              0x1
6672 #define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__PRE                            0x0
6673 
6674 #define QAM_VD_MIN_VOTING_ROUNDS__A                                         0x1460012
6675 #define QAM_VD_MIN_VOTING_ROUNDS__W                                         6
6676 #define QAM_VD_MIN_VOTING_ROUNDS__M                                         0x3F
6677 #define QAM_VD_MIN_VOTING_ROUNDS__PRE                                       0x10
6678 
6679 #define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__B                                0
6680 #define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__W                                6
6681 #define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__M                                0x3F
6682 #define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__PRE                              0x10
6683 
6684 #define QAM_VD_MAX_VOTING_ROUNDS__A                                         0x1460013
6685 #define QAM_VD_MAX_VOTING_ROUNDS__W                                         6
6686 #define QAM_VD_MAX_VOTING_ROUNDS__M                                         0x3F
6687 #define QAM_VD_MAX_VOTING_ROUNDS__PRE                                       0x10
6688 
6689 #define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__B                                0
6690 #define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__W                                6
6691 #define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__M                                0x3F
6692 #define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__PRE                              0x10
6693 
6694 #define QAM_VD_TRACEBACK_DEPTH__A                                           0x1460014
6695 #define QAM_VD_TRACEBACK_DEPTH__W                                           5
6696 #define QAM_VD_TRACEBACK_DEPTH__M                                           0x1F
6697 #define QAM_VD_TRACEBACK_DEPTH__PRE                                         0x10
6698 
6699 #define   QAM_VD_TRACEBACK_DEPTH_LENGTH__B                                  0
6700 #define   QAM_VD_TRACEBACK_DEPTH_LENGTH__W                                  5
6701 #define   QAM_VD_TRACEBACK_DEPTH_LENGTH__M                                  0x1F
6702 #define   QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE                                0x10
6703 
6704 #define QAM_VD_UNLOCK__A                                                    0x1460015
6705 #define QAM_VD_UNLOCK__W                                                    1
6706 #define QAM_VD_UNLOCK__M                                                    0x1
6707 #define QAM_VD_UNLOCK__PRE                                                  0x0
6708 #define QAM_VD_MEASUREMENT_PERIOD__A                                        0x1460016
6709 #define QAM_VD_MEASUREMENT_PERIOD__W                                        16
6710 #define QAM_VD_MEASUREMENT_PERIOD__M                                        0xFFFF
6711 #define QAM_VD_MEASUREMENT_PERIOD__PRE                                      0x8236
6712 
6713 #define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__B                               0
6714 #define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__W                               16
6715 #define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__M                               0xFFFF
6716 #define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__PRE                             0x8236
6717 
6718 #define QAM_VD_MEASUREMENT_PRESCALE__A                                      0x1460017
6719 #define QAM_VD_MEASUREMENT_PRESCALE__W                                      16
6720 #define QAM_VD_MEASUREMENT_PRESCALE__M                                      0xFFFF
6721 #define QAM_VD_MEASUREMENT_PRESCALE__PRE                                    0x4
6722 
6723 #define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__B                           0
6724 #define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__W                           16
6725 #define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__M                           0xFFFF
6726 #define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__PRE                         0x4
6727 
6728 #define QAM_VD_DELTA_PATH_METRIC__A                                         0x1460018
6729 #define QAM_VD_DELTA_PATH_METRIC__W                                         16
6730 #define QAM_VD_DELTA_PATH_METRIC__M                                         0xFFFF
6731 #define QAM_VD_DELTA_PATH_METRIC__PRE                                       0xFFFF
6732 
6733 #define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__B                            0
6734 #define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__W                            12
6735 #define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__M                            0xFFF
6736 #define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__PRE                          0xFFF
6737 
6738 #define   QAM_VD_DELTA_PATH_METRIC_EXP__B                                   12
6739 #define   QAM_VD_DELTA_PATH_METRIC_EXP__W                                   4
6740 #define   QAM_VD_DELTA_PATH_METRIC_EXP__M                                   0xF000
6741 #define   QAM_VD_DELTA_PATH_METRIC_EXP__PRE                                 0xF000
6742 
6743 #define QAM_VD_NR_QSYM_ERRORS__A                                            0x1460019
6744 #define QAM_VD_NR_QSYM_ERRORS__W                                            16
6745 #define QAM_VD_NR_QSYM_ERRORS__M                                            0xFFFF
6746 #define QAM_VD_NR_QSYM_ERRORS__PRE                                          0xFFFF
6747 
6748 #define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__B                               0
6749 #define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__W                               12
6750 #define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__M                               0xFFF
6751 #define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__PRE                             0xFFF
6752 
6753 #define   QAM_VD_NR_QSYM_ERRORS_EXP__B                                      12
6754 #define   QAM_VD_NR_QSYM_ERRORS_EXP__W                                      4
6755 #define   QAM_VD_NR_QSYM_ERRORS_EXP__M                                      0xF000
6756 #define   QAM_VD_NR_QSYM_ERRORS_EXP__PRE                                    0xF000
6757 
6758 #define QAM_VD_NR_SYMBOL_ERRORS__A                                          0x146001A
6759 #define QAM_VD_NR_SYMBOL_ERRORS__W                                          16
6760 #define QAM_VD_NR_SYMBOL_ERRORS__M                                          0xFFFF
6761 #define QAM_VD_NR_SYMBOL_ERRORS__PRE                                        0xFFFF
6762 
6763 #define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B                             0
6764 #define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__W                             12
6765 #define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M                             0xFFF
6766 #define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__PRE                           0xFFF
6767 
6768 #define   QAM_VD_NR_SYMBOL_ERRORS_EXP__B                                    12
6769 #define   QAM_VD_NR_SYMBOL_ERRORS_EXP__W                                    4
6770 #define   QAM_VD_NR_SYMBOL_ERRORS_EXP__M                                    0xF000
6771 #define   QAM_VD_NR_SYMBOL_ERRORS_EXP__PRE                                  0xF000
6772 
6773 #define QAM_VD_RELOCK_COUNT__A                                              0x146001B
6774 #define QAM_VD_RELOCK_COUNT__W                                              16
6775 #define QAM_VD_RELOCK_COUNT__M                                              0xFFFF
6776 #define QAM_VD_RELOCK_COUNT__PRE                                            0x0
6777 
6778 #define   QAM_VD_RELOCK_COUNT_COUNT__B                                      0
6779 #define   QAM_VD_RELOCK_COUNT_COUNT__W                                      8
6780 #define   QAM_VD_RELOCK_COUNT_COUNT__M                                      0xFF
6781 #define   QAM_VD_RELOCK_COUNT_COUNT__PRE                                    0x0
6782 
6783 #define QAM_SY_COMM_EXEC__A                                                 0x1470000
6784 #define QAM_SY_COMM_EXEC__W                                                 2
6785 #define QAM_SY_COMM_EXEC__M                                                 0x3
6786 #define QAM_SY_COMM_EXEC__PRE                                               0x0
6787 #define   QAM_SY_COMM_EXEC_STOP                                             0x0
6788 #define   QAM_SY_COMM_EXEC_ACTIVE                                           0x1
6789 #define   QAM_SY_COMM_EXEC_HOLD                                             0x2
6790 
6791 #define QAM_SY_COMM_MB__A                                                   0x1470002
6792 #define QAM_SY_COMM_MB__W                                                   2
6793 #define QAM_SY_COMM_MB__M                                                   0x3
6794 #define QAM_SY_COMM_MB__PRE                                                 0x0
6795 #define   QAM_SY_COMM_MB_CTL__B                                             0
6796 #define   QAM_SY_COMM_MB_CTL__W                                             1
6797 #define   QAM_SY_COMM_MB_CTL__M                                             0x1
6798 #define   QAM_SY_COMM_MB_CTL__PRE                                           0x0
6799 #define     QAM_SY_COMM_MB_CTL_OFF                                          0x0
6800 #define     QAM_SY_COMM_MB_CTL_ON                                           0x1
6801 #define   QAM_SY_COMM_MB_OBS__B                                             1
6802 #define   QAM_SY_COMM_MB_OBS__W                                             1
6803 #define   QAM_SY_COMM_MB_OBS__M                                             0x2
6804 #define   QAM_SY_COMM_MB_OBS__PRE                                           0x0
6805 #define     QAM_SY_COMM_MB_OBS_OFF                                          0x0
6806 #define     QAM_SY_COMM_MB_OBS_ON                                           0x2
6807 
6808 #define QAM_SY_COMM_INT_REQ__A                                              0x1470003
6809 #define QAM_SY_COMM_INT_REQ__W                                              1
6810 #define QAM_SY_COMM_INT_REQ__M                                              0x1
6811 #define QAM_SY_COMM_INT_REQ__PRE                                            0x0
6812 #define QAM_SY_COMM_INT_STA__A                                              0x1470005
6813 #define QAM_SY_COMM_INT_STA__W                                              4
6814 #define QAM_SY_COMM_INT_STA__M                                              0xF
6815 #define QAM_SY_COMM_INT_STA__PRE                                            0x0
6816 
6817 #define   QAM_SY_COMM_INT_STA_LOCK_INT__B                                   0
6818 #define   QAM_SY_COMM_INT_STA_LOCK_INT__W                                   1
6819 #define   QAM_SY_COMM_INT_STA_LOCK_INT__M                                   0x1
6820 #define   QAM_SY_COMM_INT_STA_LOCK_INT__PRE                                 0x0
6821 
6822 #define   QAM_SY_COMM_INT_STA_UNLOCK_INT__B                                 1
6823 #define   QAM_SY_COMM_INT_STA_UNLOCK_INT__W                                 1
6824 #define   QAM_SY_COMM_INT_STA_UNLOCK_INT__M                                 0x2
6825 #define   QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE                               0x0
6826 
6827 #define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__B                                2
6828 #define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__W                                1
6829 #define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__M                                0x4
6830 #define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE                              0x0
6831 
6832 #define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__B                               3
6833 #define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__W                               1
6834 #define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__M                               0x8
6835 #define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE                             0x0
6836 
6837 #define QAM_SY_COMM_INT_MSK__A                                              0x1470006
6838 #define QAM_SY_COMM_INT_MSK__W                                              4
6839 #define QAM_SY_COMM_INT_MSK__M                                              0xF
6840 #define QAM_SY_COMM_INT_MSK__PRE                                            0x0
6841 #define   QAM_SY_COMM_INT_MSK_LOCK_MSK__B                                   0
6842 #define   QAM_SY_COMM_INT_MSK_LOCK_MSK__W                                   1
6843 #define   QAM_SY_COMM_INT_MSK_LOCK_MSK__M                                   0x1
6844 #define   QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE                                 0x0
6845 #define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B                                 1
6846 #define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W                                 1
6847 #define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M                                 0x2
6848 #define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE                               0x0
6849 #define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B                                2
6850 #define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W                                1
6851 #define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M                                0x4
6852 #define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE                              0x0
6853 #define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B                               3
6854 #define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W                               1
6855 #define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M                               0x8
6856 #define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE                             0x0
6857 
6858 #define QAM_SY_COMM_INT_STM__A                                              0x1470007
6859 #define QAM_SY_COMM_INT_STM__W                                              4
6860 #define QAM_SY_COMM_INT_STM__M                                              0xF
6861 #define QAM_SY_COMM_INT_STM__PRE                                            0x0
6862 #define   QAM_SY_COMM_INT_STM_LOCK_MSK__B                                   0
6863 #define   QAM_SY_COMM_INT_STM_LOCK_MSK__W                                   1
6864 #define   QAM_SY_COMM_INT_STM_LOCK_MSK__M                                   0x1
6865 #define   QAM_SY_COMM_INT_STM_LOCK_MSK__PRE                                 0x0
6866 #define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__B                                 1
6867 #define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__W                                 1
6868 #define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__M                                 0x2
6869 #define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE                               0x0
6870 #define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B                                2
6871 #define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W                                1
6872 #define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M                                0x4
6873 #define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE                              0x0
6874 #define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B                               3
6875 #define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W                               1
6876 #define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M                               0x8
6877 #define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE                             0x0
6878 
6879 #define QAM_SY_STATUS__A                                                    0x1470010
6880 #define QAM_SY_STATUS__W                                                    2
6881 #define QAM_SY_STATUS__M                                                    0x3
6882 #define QAM_SY_STATUS__PRE                                                  0x0
6883 
6884 #define   QAM_SY_STATUS_SYNC_STATE__B                                       0
6885 #define   QAM_SY_STATUS_SYNC_STATE__W                                       2
6886 #define   QAM_SY_STATUS_SYNC_STATE__M                                       0x3
6887 #define   QAM_SY_STATUS_SYNC_STATE__PRE                                     0x0
6888 
6889 #define QAM_SY_TIMEOUT__A                                                   0x1470011
6890 #define QAM_SY_TIMEOUT__W                                                   16
6891 #define QAM_SY_TIMEOUT__M                                                   0xFFFF
6892 #define QAM_SY_TIMEOUT__PRE                                                 0x3A98
6893 
6894 #define QAM_SY_SYNC_LWM__A                                                  0x1470012
6895 #define QAM_SY_SYNC_LWM__W                                                  4
6896 #define QAM_SY_SYNC_LWM__M                                                  0xF
6897 #define QAM_SY_SYNC_LWM__PRE                                                0x2
6898 
6899 #define QAM_SY_SYNC_AWM__A                                                  0x1470013
6900 #define QAM_SY_SYNC_AWM__W                                                  4
6901 #define QAM_SY_SYNC_AWM__M                                                  0xF
6902 #define QAM_SY_SYNC_AWM__PRE                                                0x3
6903 
6904 #define QAM_SY_SYNC_HWM__A                                                  0x1470014
6905 #define QAM_SY_SYNC_HWM__W                                                  4
6906 #define QAM_SY_SYNC_HWM__M                                                  0xF
6907 #define QAM_SY_SYNC_HWM__PRE                                                0x5
6908 
6909 #define QAM_SY_UNLOCK__A                                                    0x1470015
6910 #define QAM_SY_UNLOCK__W                                                    1
6911 #define QAM_SY_UNLOCK__M                                                    0x1
6912 #define QAM_SY_UNLOCK__PRE                                                  0x0
6913 #define QAM_SY_CONTROL_WORD__A                                              0x1470016
6914 #define QAM_SY_CONTROL_WORD__W                                              4
6915 #define QAM_SY_CONTROL_WORD__M                                              0xF
6916 #define QAM_SY_CONTROL_WORD__PRE                                            0x0
6917 
6918 #define   QAM_SY_CONTROL_WORD_CTRL_WORD__B                                  0
6919 #define   QAM_SY_CONTROL_WORD_CTRL_WORD__W                                  4
6920 #define   QAM_SY_CONTROL_WORD_CTRL_WORD__M                                  0xF
6921 #define   QAM_SY_CONTROL_WORD_CTRL_WORD__PRE                                0x0
6922 
6923 #define QAM_VD_ISS_RAM__A                                                   0x1480000
6924 
6925 #define QAM_VD_QSS_RAM__A                                                   0x1490000
6926 
6927 #define QAM_VD_SYM_RAM__A                                                   0x14A0000
6928 
6929 #define SCU_COMM_EXEC__A                                                    0x800000
6930 #define SCU_COMM_EXEC__W                                                    2
6931 #define SCU_COMM_EXEC__M                                                    0x3
6932 #define SCU_COMM_EXEC__PRE                                                  0x0
6933 #define   SCU_COMM_EXEC_STOP                                                0x0
6934 #define   SCU_COMM_EXEC_ACTIVE                                              0x1
6935 #define   SCU_COMM_EXEC_HOLD                                                0x2
6936 
6937 #define SCU_COMM_STATE__A                                                   0x800001
6938 #define SCU_COMM_STATE__W                                                   16
6939 #define SCU_COMM_STATE__M                                                   0xFFFF
6940 #define SCU_COMM_STATE__PRE                                                 0x0
6941 
6942 #define   SCU_COMM_STATE_COMM_STATE__B                                      0
6943 #define   SCU_COMM_STATE_COMM_STATE__W                                      16
6944 #define   SCU_COMM_STATE_COMM_STATE__M                                      0xFFFF
6945 #define   SCU_COMM_STATE_COMM_STATE__PRE                                    0x0
6946 
6947 #define SCU_TOP_COMM_EXEC__A                                                0x810000
6948 #define SCU_TOP_COMM_EXEC__W                                                2
6949 #define SCU_TOP_COMM_EXEC__M                                                0x3
6950 #define SCU_TOP_COMM_EXEC__PRE                                              0x0
6951 #define   SCU_TOP_COMM_EXEC_STOP                                            0x0
6952 #define   SCU_TOP_COMM_EXEC_ACTIVE                                          0x1
6953 #define   SCU_TOP_COMM_EXEC_HOLD                                            0x2
6954 
6955 #define SCU_TOP_COMM_STATE__A                                               0x810001
6956 #define SCU_TOP_COMM_STATE__W                                               16
6957 #define SCU_TOP_COMM_STATE__M                                               0xFFFF
6958 #define SCU_TOP_COMM_STATE__PRE                                             0x0
6959 #define SCU_TOP_MWAIT_CTR__A                                                0x810010
6960 #define SCU_TOP_MWAIT_CTR__W                                                2
6961 #define SCU_TOP_MWAIT_CTR__M                                                0x3
6962 #define SCU_TOP_MWAIT_CTR__PRE                                              0x0
6963 
6964 #define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__B                                    0
6965 #define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__W                                    1
6966 #define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__M                                    0x1
6967 #define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE                                  0x0
6968 #define     SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF                           0x0
6969 #define     SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON                            0x1
6970 
6971 #define   SCU_TOP_MWAIT_CTR_READY_DIS__B                                    1
6972 #define   SCU_TOP_MWAIT_CTR_READY_DIS__W                                    1
6973 #define   SCU_TOP_MWAIT_CTR_READY_DIS__M                                    0x2
6974 #define   SCU_TOP_MWAIT_CTR_READY_DIS__PRE                                  0x0
6975 #define     SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON                              0x0
6976 #define     SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF                             0x2
6977 
6978 #define SCU_LOW_RAM__A                                                      0x820000
6979 
6980 #define   SCU_LOW_RAM_LOW__B                                                0
6981 #define   SCU_LOW_RAM_LOW__W                                                16
6982 #define   SCU_LOW_RAM_LOW__M                                                0xFFFF
6983 #define   SCU_LOW_RAM_LOW__PRE                                              0x0
6984 
6985 #define SCU_HIGH_RAM__A                                                     0x830000
6986 
6987 #define   SCU_HIGH_RAM_HIGH__B                                              0
6988 #define   SCU_HIGH_RAM_HIGH__W                                              16
6989 #define   SCU_HIGH_RAM_HIGH__M                                              0xFFFF
6990 #define   SCU_HIGH_RAM_HIGH__PRE                                            0x0
6991 
6992 #define SCU_RAM_AGC_RF_MAX__A                                               0x831E96
6993 #define SCU_RAM_AGC_RF_MAX__W                                               15
6994 #define SCU_RAM_AGC_RF_MAX__M                                               0x7FFF
6995 #define SCU_RAM_AGC_RF_MAX__PRE                                             0x0
6996 
6997 #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A                                  0x831E97
6998 #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W                                  16
6999 #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M                                  0xFFFF
7000 #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE                                0x0
7001 
7002 #define SCU_RAM_AGC_KI_CYCCNT__A                                            0x831E98
7003 #define SCU_RAM_AGC_KI_CYCCNT__W                                            16
7004 #define SCU_RAM_AGC_KI_CYCCNT__M                                            0xFFFF
7005 #define SCU_RAM_AGC_KI_CYCCNT__PRE                                          0x0
7006 
7007 #define SCU_RAM_AGC_KI_CYCLEN__A                                            0x831E99
7008 #define SCU_RAM_AGC_KI_CYCLEN__W                                            16
7009 #define SCU_RAM_AGC_KI_CYCLEN__M                                            0xFFFF
7010 #define SCU_RAM_AGC_KI_CYCLEN__PRE                                          0x0
7011 
7012 #define SCU_RAM_AGC_SNS_CYCLEN__A                                           0x831E9A
7013 #define SCU_RAM_AGC_SNS_CYCLEN__W                                           16
7014 #define SCU_RAM_AGC_SNS_CYCLEN__M                                           0xFFFF
7015 #define SCU_RAM_AGC_SNS_CYCLEN__PRE                                         0x0
7016 
7017 #define SCU_RAM_AGC_RF_SNS_DEV_MAX__A                                       0x831E9B
7018 #define SCU_RAM_AGC_RF_SNS_DEV_MAX__W                                       16
7019 #define SCU_RAM_AGC_RF_SNS_DEV_MAX__M                                       0xFFFF
7020 #define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE                                     0x0
7021 
7022 #define SCU_RAM_AGC_RF_SNS_DEV_MIN__A                                       0x831E9C
7023 #define SCU_RAM_AGC_RF_SNS_DEV_MIN__W                                       16
7024 #define SCU_RAM_AGC_RF_SNS_DEV_MIN__M                                       0xFFFF
7025 #define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE                                     0x0
7026 #define SCU_RAM_AGC_KI__A                                                   0x831E9D
7027 #define SCU_RAM_AGC_KI__W                                                   15
7028 #define SCU_RAM_AGC_KI__M                                                   0x7FFF
7029 #define SCU_RAM_AGC_KI__PRE                                                 0x0
7030 
7031 #define   SCU_RAM_AGC_KI_DGAIN__B                                           0
7032 #define   SCU_RAM_AGC_KI_DGAIN__W                                           4
7033 #define   SCU_RAM_AGC_KI_DGAIN__M                                           0xF
7034 #define   SCU_RAM_AGC_KI_DGAIN__PRE                                         0x0
7035 
7036 #define   SCU_RAM_AGC_KI_RF__B                                              4
7037 #define   SCU_RAM_AGC_KI_RF__W                                              4
7038 #define   SCU_RAM_AGC_KI_RF__M                                              0xF0
7039 #define   SCU_RAM_AGC_KI_RF__PRE                                            0x0
7040 
7041 #define   SCU_RAM_AGC_KI_IF__B                                              8
7042 #define   SCU_RAM_AGC_KI_IF__W                                              4
7043 #define   SCU_RAM_AGC_KI_IF__M                                              0xF00
7044 #define   SCU_RAM_AGC_KI_IF__PRE                                            0x0
7045 
7046 #define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__B                                  12
7047 #define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__W                                  1
7048 #define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__M                                  0x1000
7049 #define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__PRE                                0x0
7050 
7051 #define   SCU_RAM_AGC_KI_INV_IF_POL__B                                      13
7052 #define   SCU_RAM_AGC_KI_INV_IF_POL__W                                      1
7053 #define   SCU_RAM_AGC_KI_INV_IF_POL__M                                      0x2000
7054 #define   SCU_RAM_AGC_KI_INV_IF_POL__PRE                                    0x0
7055 
7056 #define   SCU_RAM_AGC_KI_INV_RF_POL__B                                      14
7057 #define   SCU_RAM_AGC_KI_INV_RF_POL__W                                      1
7058 #define   SCU_RAM_AGC_KI_INV_RF_POL__M                                      0x4000
7059 #define   SCU_RAM_AGC_KI_INV_RF_POL__PRE                                    0x0
7060 
7061 #define SCU_RAM_AGC_KI_RED__A                                               0x831E9E
7062 #define SCU_RAM_AGC_KI_RED__W                                               6
7063 #define SCU_RAM_AGC_KI_RED__M                                               0x3F
7064 #define SCU_RAM_AGC_KI_RED__PRE                                             0x0
7065 
7066 #define   SCU_RAM_AGC_KI_RED_INNER_RED__B                                   0
7067 #define   SCU_RAM_AGC_KI_RED_INNER_RED__W                                   2
7068 #define   SCU_RAM_AGC_KI_RED_INNER_RED__M                                   0x3
7069 #define   SCU_RAM_AGC_KI_RED_INNER_RED__PRE                                 0x0
7070 
7071 #define   SCU_RAM_AGC_KI_RED_RAGC_RED__B                                    2
7072 #define   SCU_RAM_AGC_KI_RED_RAGC_RED__W                                    2
7073 #define   SCU_RAM_AGC_KI_RED_RAGC_RED__M                                    0xC
7074 #define   SCU_RAM_AGC_KI_RED_RAGC_RED__PRE                                  0x0
7075 
7076 #define   SCU_RAM_AGC_KI_RED_IAGC_RED__B                                    4
7077 #define   SCU_RAM_AGC_KI_RED_IAGC_RED__W                                    2
7078 #define   SCU_RAM_AGC_KI_RED_IAGC_RED__M                                    0x30
7079 #define   SCU_RAM_AGC_KI_RED_IAGC_RED__PRE                                  0x0
7080 
7081 #define SCU_RAM_AGC_KI_INNERGAIN_MIN__A                                     0x831E9F
7082 #define SCU_RAM_AGC_KI_INNERGAIN_MIN__W                                     16
7083 #define SCU_RAM_AGC_KI_INNERGAIN_MIN__M                                     0xFFFF
7084 #define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE                                   0x0
7085 
7086 #define SCU_RAM_AGC_KI_MINGAIN__A                                           0x831EA0
7087 #define SCU_RAM_AGC_KI_MINGAIN__W                                           16
7088 #define SCU_RAM_AGC_KI_MINGAIN__M                                           0xFFFF
7089 #define SCU_RAM_AGC_KI_MINGAIN__PRE                                         0x0
7090 
7091 #define SCU_RAM_AGC_KI_MAXGAIN__A                                           0x831EA1
7092 #define SCU_RAM_AGC_KI_MAXGAIN__W                                           16
7093 #define SCU_RAM_AGC_KI_MAXGAIN__M                                           0xFFFF
7094 #define SCU_RAM_AGC_KI_MAXGAIN__PRE                                         0x0
7095 
7096 #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A                                     0x831EA2
7097 #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W                                     16
7098 #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M                                     0xFFFF
7099 #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE                                   0x0
7100 #define SCU_RAM_AGC_KI_MIN__A                                               0x831EA3
7101 #define SCU_RAM_AGC_KI_MIN__W                                               12
7102 #define SCU_RAM_AGC_KI_MIN__M                                               0xFFF
7103 #define SCU_RAM_AGC_KI_MIN__PRE                                             0x0
7104 
7105 #define   SCU_RAM_AGC_KI_MIN_DGAIN__B                                       0
7106 #define   SCU_RAM_AGC_KI_MIN_DGAIN__W                                       4
7107 #define   SCU_RAM_AGC_KI_MIN_DGAIN__M                                       0xF
7108 #define   SCU_RAM_AGC_KI_MIN_DGAIN__PRE                                     0x0
7109 
7110 #define   SCU_RAM_AGC_KI_MIN_RF__B                                          4
7111 #define   SCU_RAM_AGC_KI_MIN_RF__W                                          4
7112 #define   SCU_RAM_AGC_KI_MIN_RF__M                                          0xF0
7113 #define   SCU_RAM_AGC_KI_MIN_RF__PRE                                        0x0
7114 
7115 #define   SCU_RAM_AGC_KI_MIN_IF__B                                          8
7116 #define   SCU_RAM_AGC_KI_MIN_IF__W                                          4
7117 #define   SCU_RAM_AGC_KI_MIN_IF__M                                          0xF00
7118 #define   SCU_RAM_AGC_KI_MIN_IF__PRE                                        0x0
7119 
7120 #define SCU_RAM_AGC_KI_MAX__A                                               0x831EA4
7121 #define SCU_RAM_AGC_KI_MAX__W                                               12
7122 #define SCU_RAM_AGC_KI_MAX__M                                               0xFFF
7123 #define SCU_RAM_AGC_KI_MAX__PRE                                             0x0
7124 
7125 #define   SCU_RAM_AGC_KI_MAX_DGAIN__B                                       0
7126 #define   SCU_RAM_AGC_KI_MAX_DGAIN__W                                       4
7127 #define   SCU_RAM_AGC_KI_MAX_DGAIN__M                                       0xF
7128 #define   SCU_RAM_AGC_KI_MAX_DGAIN__PRE                                     0x0
7129 
7130 #define   SCU_RAM_AGC_KI_MAX_RF__B                                          4
7131 #define   SCU_RAM_AGC_KI_MAX_RF__W                                          4
7132 #define   SCU_RAM_AGC_KI_MAX_RF__M                                          0xF0
7133 #define   SCU_RAM_AGC_KI_MAX_RF__PRE                                        0x0
7134 
7135 #define   SCU_RAM_AGC_KI_MAX_IF__B                                          8
7136 #define   SCU_RAM_AGC_KI_MAX_IF__W                                          4
7137 #define   SCU_RAM_AGC_KI_MAX_IF__M                                          0xF00
7138 #define   SCU_RAM_AGC_KI_MAX_IF__PRE                                        0x0
7139 
7140 #define SCU_RAM_AGC_CLP_SUM__A                                              0x831EA5
7141 #define SCU_RAM_AGC_CLP_SUM__W                                              16
7142 #define SCU_RAM_AGC_CLP_SUM__M                                              0xFFFF
7143 #define SCU_RAM_AGC_CLP_SUM__PRE                                            0x0
7144 
7145 #define SCU_RAM_AGC_CLP_SUM_MIN__A                                          0x831EA6
7146 #define SCU_RAM_AGC_CLP_SUM_MIN__W                                          16
7147 #define SCU_RAM_AGC_CLP_SUM_MIN__M                                          0xFFFF
7148 #define SCU_RAM_AGC_CLP_SUM_MIN__PRE                                        0x0
7149 
7150 #define SCU_RAM_AGC_CLP_SUM_MAX__A                                          0x831EA7
7151 #define SCU_RAM_AGC_CLP_SUM_MAX__W                                          16
7152 #define SCU_RAM_AGC_CLP_SUM_MAX__M                                          0xFFFF
7153 #define SCU_RAM_AGC_CLP_SUM_MAX__PRE                                        0x0
7154 
7155 #define SCU_RAM_AGC_CLP_CYCLEN__A                                           0x831EA8
7156 #define SCU_RAM_AGC_CLP_CYCLEN__W                                           16
7157 #define SCU_RAM_AGC_CLP_CYCLEN__M                                           0xFFFF
7158 #define SCU_RAM_AGC_CLP_CYCLEN__PRE                                         0x0
7159 
7160 #define SCU_RAM_AGC_CLP_CYCCNT__A                                           0x831EA9
7161 #define SCU_RAM_AGC_CLP_CYCCNT__W                                           16
7162 #define SCU_RAM_AGC_CLP_CYCCNT__M                                           0xFFFF
7163 #define SCU_RAM_AGC_CLP_CYCCNT__PRE                                         0x0
7164 
7165 #define SCU_RAM_AGC_CLP_DIR_TO__A                                           0x831EAA
7166 #define SCU_RAM_AGC_CLP_DIR_TO__W                                           8
7167 #define SCU_RAM_AGC_CLP_DIR_TO__M                                           0xFF
7168 #define SCU_RAM_AGC_CLP_DIR_TO__PRE                                         0x0
7169 
7170 #define SCU_RAM_AGC_CLP_DIR_WD__A                                           0x831EAB
7171 #define SCU_RAM_AGC_CLP_DIR_WD__W                                           8
7172 #define SCU_RAM_AGC_CLP_DIR_WD__M                                           0xFF
7173 #define SCU_RAM_AGC_CLP_DIR_WD__PRE                                         0x0
7174 
7175 #define SCU_RAM_AGC_CLP_DIR_STP__A                                          0x831EAC
7176 #define SCU_RAM_AGC_CLP_DIR_STP__W                                          16
7177 #define SCU_RAM_AGC_CLP_DIR_STP__M                                          0xFFFF
7178 #define SCU_RAM_AGC_CLP_DIR_STP__PRE                                        0x0
7179 
7180 #define SCU_RAM_AGC_SNS_SUM__A                                              0x831EAD
7181 #define SCU_RAM_AGC_SNS_SUM__W                                              16
7182 #define SCU_RAM_AGC_SNS_SUM__M                                              0xFFFF
7183 #define SCU_RAM_AGC_SNS_SUM__PRE                                            0x0
7184 
7185 #define SCU_RAM_AGC_SNS_SUM_MIN__A                                          0x831EAE
7186 #define SCU_RAM_AGC_SNS_SUM_MIN__W                                          16
7187 #define SCU_RAM_AGC_SNS_SUM_MIN__M                                          0xFFFF
7188 #define SCU_RAM_AGC_SNS_SUM_MIN__PRE                                        0x0
7189 
7190 #define SCU_RAM_AGC_SNS_SUM_MAX__A                                          0x831EAF
7191 #define SCU_RAM_AGC_SNS_SUM_MAX__W                                          16
7192 #define SCU_RAM_AGC_SNS_SUM_MAX__M                                          0xFFFF
7193 #define SCU_RAM_AGC_SNS_SUM_MAX__PRE                                        0x0
7194 
7195 #define SCU_RAM_AGC_SNS_CYCCNT__A                                           0x831EB0
7196 #define SCU_RAM_AGC_SNS_CYCCNT__W                                           16
7197 #define SCU_RAM_AGC_SNS_CYCCNT__M                                           0xFFFF
7198 #define SCU_RAM_AGC_SNS_CYCCNT__PRE                                         0x0
7199 
7200 #define SCU_RAM_AGC_SNS_DIR_TO__A                                           0x831EB1
7201 #define SCU_RAM_AGC_SNS_DIR_TO__W                                           8
7202 #define SCU_RAM_AGC_SNS_DIR_TO__M                                           0xFF
7203 #define SCU_RAM_AGC_SNS_DIR_TO__PRE                                         0x0
7204 
7205 #define SCU_RAM_AGC_SNS_DIR_WD__A                                           0x831EB2
7206 #define SCU_RAM_AGC_SNS_DIR_WD__W                                           8
7207 #define SCU_RAM_AGC_SNS_DIR_WD__M                                           0xFF
7208 #define SCU_RAM_AGC_SNS_DIR_WD__PRE                                         0x0
7209 
7210 #define SCU_RAM_AGC_SNS_DIR_STP__A                                          0x831EB3
7211 #define SCU_RAM_AGC_SNS_DIR_STP__W                                          16
7212 #define SCU_RAM_AGC_SNS_DIR_STP__M                                          0xFFFF
7213 #define SCU_RAM_AGC_SNS_DIR_STP__PRE                                        0x0
7214 
7215 #define SCU_RAM_AGC_INGAIN__A                                               0x831EB4
7216 #define SCU_RAM_AGC_INGAIN__W                                               16
7217 #define SCU_RAM_AGC_INGAIN__M                                               0xFFFF
7218 #define SCU_RAM_AGC_INGAIN__PRE                                             0x0
7219 
7220 #define SCU_RAM_AGC_INGAIN_TGT__A                                           0x831EB5
7221 #define SCU_RAM_AGC_INGAIN_TGT__W                                           15
7222 #define SCU_RAM_AGC_INGAIN_TGT__M                                           0x7FFF
7223 #define SCU_RAM_AGC_INGAIN_TGT__PRE                                         0x0
7224 
7225 #define SCU_RAM_AGC_INGAIN_TGT_MIN__A                                       0x831EB6
7226 #define SCU_RAM_AGC_INGAIN_TGT_MIN__W                                       15
7227 #define SCU_RAM_AGC_INGAIN_TGT_MIN__M                                       0x7FFF
7228 #define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE                                     0x0
7229 
7230 #define SCU_RAM_AGC_INGAIN_TGT_MAX__A                                       0x831EB7
7231 #define SCU_RAM_AGC_INGAIN_TGT_MAX__W                                       15
7232 #define SCU_RAM_AGC_INGAIN_TGT_MAX__M                                       0x7FFF
7233 #define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE                                     0x0
7234 
7235 #define SCU_RAM_AGC_IF_IACCU_HI__A                                          0x831EB8
7236 #define SCU_RAM_AGC_IF_IACCU_HI__W                                          16
7237 #define SCU_RAM_AGC_IF_IACCU_HI__M                                          0xFFFF
7238 #define SCU_RAM_AGC_IF_IACCU_HI__PRE                                        0x0
7239 
7240 #define SCU_RAM_AGC_IF_IACCU_LO__A                                          0x831EB9
7241 #define SCU_RAM_AGC_IF_IACCU_LO__W                                          8
7242 #define SCU_RAM_AGC_IF_IACCU_LO__M                                          0xFF
7243 #define SCU_RAM_AGC_IF_IACCU_LO__PRE                                        0x0
7244 
7245 #define SCU_RAM_AGC_IF_IACCU_HI_TGT__A                                      0x831EBA
7246 #define SCU_RAM_AGC_IF_IACCU_HI_TGT__W                                      15
7247 #define SCU_RAM_AGC_IF_IACCU_HI_TGT__M                                      0x7FFF
7248 #define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE                                    0x0
7249 
7250 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A                                  0x831EBB
7251 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W                                  15
7252 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M                                  0x7FFF
7253 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE                                0x0
7254 
7255 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A                                  0x831EBC
7256 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W                                  15
7257 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M                                  0x7FFF
7258 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE                                0x0
7259 
7260 #define SCU_RAM_AGC_RF_IACCU_HI__A                                          0x831EBD
7261 #define SCU_RAM_AGC_RF_IACCU_HI__W                                          16
7262 #define SCU_RAM_AGC_RF_IACCU_HI__M                                          0xFFFF
7263 #define SCU_RAM_AGC_RF_IACCU_HI__PRE                                        0x0
7264 
7265 #define SCU_RAM_AGC_RF_IACCU_LO__A                                          0x831EBE
7266 #define SCU_RAM_AGC_RF_IACCU_LO__W                                          8
7267 #define SCU_RAM_AGC_RF_IACCU_LO__M                                          0xFF
7268 #define SCU_RAM_AGC_RF_IACCU_LO__PRE                                        0x0
7269 
7270 #define SCU_RAM_AGC_RF_IACCU_HI_CO__A                                       0x831EBF
7271 #define SCU_RAM_AGC_RF_IACCU_HI_CO__W                                       16
7272 #define SCU_RAM_AGC_RF_IACCU_HI_CO__M                                       0xFFFF
7273 #define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE                                     0x0
7274 
7275 #define SCU_RAM_SP__A                                                       0x831EC0
7276 #define SCU_RAM_SP__W                                                       16
7277 #define SCU_RAM_SP__M                                                       0xFFFF
7278 #define SCU_RAM_SP__PRE                                                     0x0
7279 
7280 #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A                                  0x831EC1
7281 #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W                                  16
7282 #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M                                  0xFFFF
7283 #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE                                0x0
7284 
7285 #define SCU_RAM_AGC_KI_MIN_IFGAIN__A                                        0x831EC2
7286 #define SCU_RAM_AGC_KI_MIN_IFGAIN__W                                        16
7287 #define SCU_RAM_AGC_KI_MIN_IFGAIN__M                                        0xFFFF
7288 #define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE                                      0x0
7289 
7290 #define SCU_RAM_AGC_KI_MAX_IFGAIN__A                                        0x831EC3
7291 #define SCU_RAM_AGC_KI_MAX_IFGAIN__W                                        16
7292 #define SCU_RAM_AGC_KI_MAX_IFGAIN__M                                        0xFFFF
7293 #define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE                                      0x0
7294 
7295 #define SCU_RAM_FEC_MEAS_COUNT__A                                           0x831EC4
7296 #define SCU_RAM_FEC_MEAS_COUNT__W                                           16
7297 #define SCU_RAM_FEC_MEAS_COUNT__M                                           0xFFFF
7298 #define SCU_RAM_FEC_MEAS_COUNT__PRE                                         0x0
7299 
7300 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A                                0x831EC5
7301 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__W                                16
7302 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__M                                0xFFFF
7303 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__PRE                              0x0
7304 
7305 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__A                                0x831EC6
7306 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__W                                16
7307 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__M                                0xFFFF
7308 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__PRE                              0x0
7309 #define SCU_RAM_GPIO__A                                                     0x831EC7
7310 #define SCU_RAM_GPIO__W                                                     1
7311 #define SCU_RAM_GPIO__M                                                     0x1
7312 #define SCU_RAM_GPIO__PRE                                                   0x0
7313 
7314 #define   SCU_RAM_GPIO_HW_LOCK_IND__B                                       0
7315 #define   SCU_RAM_GPIO_HW_LOCK_IND__W                                       1
7316 #define   SCU_RAM_GPIO_HW_LOCK_IND__M                                       0x1
7317 #define   SCU_RAM_GPIO_HW_LOCK_IND__PRE                                     0x0
7318 #define     SCU_RAM_GPIO_HW_LOCK_IND_DISABLE                                0x0
7319 #define     SCU_RAM_GPIO_HW_LOCK_IND_ENABLE                                 0x1
7320 
7321 #define SCU_RAM_AGC_CLP_CTRL_MODE__A                                        0x831EC8
7322 #define SCU_RAM_AGC_CLP_CTRL_MODE__W                                        8
7323 #define SCU_RAM_AGC_CLP_CTRL_MODE__M                                        0xFF
7324 #define SCU_RAM_AGC_CLP_CTRL_MODE__PRE                                      0x0
7325 
7326 #define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B                           0
7327 #define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W                           1
7328 #define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M                           0x1
7329 #define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE                         0x0
7330 #define     SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_false                      0x0
7331 #define     SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_true                       0x1
7332 
7333 #define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B                          1
7334 #define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W                          1
7335 #define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M                          0x2
7336 #define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE                        0x0
7337 #define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE                0x0
7338 #define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE               0x2
7339 
7340 #define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B                         2
7341 #define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W                         1
7342 #define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M                         0x4
7343 #define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE                       0x0
7344 #define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE              0x0
7345 #define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE               0x4
7346 
7347 #define SCU_RAM_AGC_KI_MIN_RFGAIN__A                                        0x831EC9
7348 #define SCU_RAM_AGC_KI_MIN_RFGAIN__W                                        16
7349 #define SCU_RAM_AGC_KI_MIN_RFGAIN__M                                        0xFFFF
7350 #define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE                                      0x0
7351 
7352 #define SCU_RAM_AGC_KI_MAX_RFGAIN__A                                        0x831ECA
7353 #define SCU_RAM_AGC_KI_MAX_RFGAIN__W                                        16
7354 #define SCU_RAM_AGC_KI_MAX_RFGAIN__M                                        0xFFFF
7355 #define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE                                      0x0
7356 
7357 #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A                                   0x831ECB
7358 #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W                                   16
7359 #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M                                   0xFFFF
7360 #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE                                 0x0
7361 
7362 #define SCU_RAM_INHIBIT_1__A                                                0x831ECC
7363 #define SCU_RAM_INHIBIT_1__W                                                16
7364 #define SCU_RAM_INHIBIT_1__M                                                0xFFFF
7365 #define SCU_RAM_INHIBIT_1__PRE                                              0x0
7366 
7367 #define SCU_RAM_HTOL_BUF_0__A                                               0x831ECD
7368 #define SCU_RAM_HTOL_BUF_0__W                                               16
7369 #define SCU_RAM_HTOL_BUF_0__M                                               0xFFFF
7370 #define SCU_RAM_HTOL_BUF_0__PRE                                             0x0
7371 
7372 #define SCU_RAM_HTOL_BUF_1__A                                               0x831ECE
7373 #define SCU_RAM_HTOL_BUF_1__W                                               16
7374 #define SCU_RAM_HTOL_BUF_1__M                                               0xFFFF
7375 #define SCU_RAM_HTOL_BUF_1__PRE                                             0x0
7376 
7377 #define SCU_RAM_INHIBIT_2__A                                                0x831ECF
7378 #define SCU_RAM_INHIBIT_2__W                                                16
7379 #define SCU_RAM_INHIBIT_2__M                                                0xFFFF
7380 #define SCU_RAM_INHIBIT_2__PRE                                              0x0
7381 
7382 #define SCU_RAM_TR_SHORT_BUF_0__A                                           0x831ED0
7383 #define SCU_RAM_TR_SHORT_BUF_0__W                                           16
7384 #define SCU_RAM_TR_SHORT_BUF_0__M                                           0xFFFF
7385 #define SCU_RAM_TR_SHORT_BUF_0__PRE                                         0x0
7386 
7387 #define SCU_RAM_TR_SHORT_BUF_1__A                                           0x831ED1
7388 #define SCU_RAM_TR_SHORT_BUF_1__W                                           16
7389 #define SCU_RAM_TR_SHORT_BUF_1__M                                           0xFFFF
7390 #define SCU_RAM_TR_SHORT_BUF_1__PRE                                         0x0
7391 
7392 #define SCU_RAM_TR_LONG_BUF_0__A                                            0x831ED2
7393 #define SCU_RAM_TR_LONG_BUF_0__W                                            16
7394 #define SCU_RAM_TR_LONG_BUF_0__M                                            0xFFFF
7395 #define SCU_RAM_TR_LONG_BUF_0__PRE                                          0x0
7396 
7397 #define SCU_RAM_TR_LONG_BUF_1__A                                            0x831ED3
7398 #define SCU_RAM_TR_LONG_BUF_1__W                                            16
7399 #define SCU_RAM_TR_LONG_BUF_1__M                                            0xFFFF
7400 #define SCU_RAM_TR_LONG_BUF_1__PRE                                          0x0
7401 
7402 #define SCU_RAM_TR_LONG_BUF_2__A                                            0x831ED4
7403 #define SCU_RAM_TR_LONG_BUF_2__W                                            16
7404 #define SCU_RAM_TR_LONG_BUF_2__M                                            0xFFFF
7405 #define SCU_RAM_TR_LONG_BUF_2__PRE                                          0x0
7406 
7407 #define SCU_RAM_TR_LONG_BUF_3__A                                            0x831ED5
7408 #define SCU_RAM_TR_LONG_BUF_3__W                                            16
7409 #define SCU_RAM_TR_LONG_BUF_3__M                                            0xFFFF
7410 #define SCU_RAM_TR_LONG_BUF_3__PRE                                          0x0
7411 
7412 #define SCU_RAM_TR_LONG_BUF_4__A                                            0x831ED6
7413 #define SCU_RAM_TR_LONG_BUF_4__W                                            16
7414 #define SCU_RAM_TR_LONG_BUF_4__M                                            0xFFFF
7415 #define SCU_RAM_TR_LONG_BUF_4__PRE                                          0x0
7416 
7417 #define SCU_RAM_TR_LONG_BUF_5__A                                            0x831ED7
7418 #define SCU_RAM_TR_LONG_BUF_5__W                                            16
7419 #define SCU_RAM_TR_LONG_BUF_5__M                                            0xFFFF
7420 #define SCU_RAM_TR_LONG_BUF_5__PRE                                          0x0
7421 
7422 #define SCU_RAM_TR_LONG_BUF_6__A                                            0x831ED8
7423 #define SCU_RAM_TR_LONG_BUF_6__W                                            16
7424 #define SCU_RAM_TR_LONG_BUF_6__M                                            0xFFFF
7425 #define SCU_RAM_TR_LONG_BUF_6__PRE                                          0x0
7426 
7427 #define SCU_RAM_TR_LONG_BUF_7__A                                            0x831ED9
7428 #define SCU_RAM_TR_LONG_BUF_7__W                                            16
7429 #define SCU_RAM_TR_LONG_BUF_7__M                                            0xFFFF
7430 #define SCU_RAM_TR_LONG_BUF_7__PRE                                          0x0
7431 
7432 #define SCU_RAM_TR_LONG_BUF_8__A                                            0x831EDA
7433 #define SCU_RAM_TR_LONG_BUF_8__W                                            16
7434 #define SCU_RAM_TR_LONG_BUF_8__M                                            0xFFFF
7435 #define SCU_RAM_TR_LONG_BUF_8__PRE                                          0x0
7436 
7437 #define SCU_RAM_TR_LONG_BUF_9__A                                            0x831EDB
7438 #define SCU_RAM_TR_LONG_BUF_9__W                                            16
7439 #define SCU_RAM_TR_LONG_BUF_9__M                                            0xFFFF
7440 #define SCU_RAM_TR_LONG_BUF_9__PRE                                          0x0
7441 
7442 #define SCU_RAM_TR_LONG_BUF_10__A                                           0x831EDC
7443 #define SCU_RAM_TR_LONG_BUF_10__W                                           16
7444 #define SCU_RAM_TR_LONG_BUF_10__M                                           0xFFFF
7445 #define SCU_RAM_TR_LONG_BUF_10__PRE                                         0x0
7446 
7447 #define SCU_RAM_TR_LONG_BUF_11__A                                           0x831EDD
7448 #define SCU_RAM_TR_LONG_BUF_11__W                                           16
7449 #define SCU_RAM_TR_LONG_BUF_11__M                                           0xFFFF
7450 #define SCU_RAM_TR_LONG_BUF_11__PRE                                         0x0
7451 
7452 #define SCU_RAM_TR_LONG_BUF_12__A                                           0x831EDE
7453 #define SCU_RAM_TR_LONG_BUF_12__W                                           16
7454 #define SCU_RAM_TR_LONG_BUF_12__M                                           0xFFFF
7455 #define SCU_RAM_TR_LONG_BUF_12__PRE                                         0x0
7456 
7457 #define SCU_RAM_TR_LONG_BUF_13__A                                           0x831EDF
7458 #define SCU_RAM_TR_LONG_BUF_13__W                                           16
7459 #define SCU_RAM_TR_LONG_BUF_13__M                                           0xFFFF
7460 #define SCU_RAM_TR_LONG_BUF_13__PRE                                         0x0
7461 
7462 #define SCU_RAM_TR_LONG_BUF_14__A                                           0x831EE0
7463 #define SCU_RAM_TR_LONG_BUF_14__W                                           16
7464 #define SCU_RAM_TR_LONG_BUF_14__M                                           0xFFFF
7465 #define SCU_RAM_TR_LONG_BUF_14__PRE                                         0x0
7466 
7467 #define SCU_RAM_TR_LONG_BUF_15__A                                           0x831EE1
7468 #define SCU_RAM_TR_LONG_BUF_15__W                                           16
7469 #define SCU_RAM_TR_LONG_BUF_15__M                                           0xFFFF
7470 #define SCU_RAM_TR_LONG_BUF_15__PRE                                         0x0
7471 
7472 #define SCU_RAM_TR_LONG_BUF_16__A                                           0x831EE2
7473 #define SCU_RAM_TR_LONG_BUF_16__W                                           16
7474 #define SCU_RAM_TR_LONG_BUF_16__M                                           0xFFFF
7475 #define SCU_RAM_TR_LONG_BUF_16__PRE                                         0x0
7476 
7477 #define SCU_RAM_TR_LONG_BUF_17__A                                           0x831EE3
7478 #define SCU_RAM_TR_LONG_BUF_17__W                                           16
7479 #define SCU_RAM_TR_LONG_BUF_17__M                                           0xFFFF
7480 #define SCU_RAM_TR_LONG_BUF_17__PRE                                         0x0
7481 
7482 #define SCU_RAM_TR_LONG_BUF_18__A                                           0x831EE4
7483 #define SCU_RAM_TR_LONG_BUF_18__W                                           16
7484 #define SCU_RAM_TR_LONG_BUF_18__M                                           0xFFFF
7485 #define SCU_RAM_TR_LONG_BUF_18__PRE                                         0x0
7486 
7487 #define SCU_RAM_TR_LONG_BUF_19__A                                           0x831EE5
7488 #define SCU_RAM_TR_LONG_BUF_19__W                                           16
7489 #define SCU_RAM_TR_LONG_BUF_19__M                                           0xFFFF
7490 #define SCU_RAM_TR_LONG_BUF_19__PRE                                         0x0
7491 
7492 #define SCU_RAM_TR_LONG_BUF_20__A                                           0x831EE6
7493 #define SCU_RAM_TR_LONG_BUF_20__W                                           16
7494 #define SCU_RAM_TR_LONG_BUF_20__M                                           0xFFFF
7495 #define SCU_RAM_TR_LONG_BUF_20__PRE                                         0x0
7496 
7497 #define SCU_RAM_TR_LONG_BUF_21__A                                           0x831EE7
7498 #define SCU_RAM_TR_LONG_BUF_21__W                                           16
7499 #define SCU_RAM_TR_LONG_BUF_21__M                                           0xFFFF
7500 #define SCU_RAM_TR_LONG_BUF_21__PRE                                         0x0
7501 
7502 #define SCU_RAM_TR_LONG_BUF_22__A                                           0x831EE8
7503 #define SCU_RAM_TR_LONG_BUF_22__W                                           16
7504 #define SCU_RAM_TR_LONG_BUF_22__M                                           0xFFFF
7505 #define SCU_RAM_TR_LONG_BUF_22__PRE                                         0x0
7506 
7507 #define SCU_RAM_TR_LONG_BUF_23__A                                           0x831EE9
7508 #define SCU_RAM_TR_LONG_BUF_23__W                                           16
7509 #define SCU_RAM_TR_LONG_BUF_23__M                                           0xFFFF
7510 #define SCU_RAM_TR_LONG_BUF_23__PRE                                         0x0
7511 
7512 #define SCU_RAM_TR_LONG_BUF_24__A                                           0x831EEA
7513 #define SCU_RAM_TR_LONG_BUF_24__W                                           16
7514 #define SCU_RAM_TR_LONG_BUF_24__M                                           0xFFFF
7515 #define SCU_RAM_TR_LONG_BUF_24__PRE                                         0x0
7516 
7517 #define SCU_RAM_TR_LONG_BUF_25__A                                           0x831EEB
7518 #define SCU_RAM_TR_LONG_BUF_25__W                                           16
7519 #define SCU_RAM_TR_LONG_BUF_25__M                                           0xFFFF
7520 #define SCU_RAM_TR_LONG_BUF_25__PRE                                         0x0
7521 
7522 #define SCU_RAM_TR_LONG_BUF_26__A                                           0x831EEC
7523 #define SCU_RAM_TR_LONG_BUF_26__W                                           16
7524 #define SCU_RAM_TR_LONG_BUF_26__M                                           0xFFFF
7525 #define SCU_RAM_TR_LONG_BUF_26__PRE                                         0x0
7526 
7527 #define SCU_RAM_TR_LONG_BUF_27__A                                           0x831EED
7528 #define SCU_RAM_TR_LONG_BUF_27__W                                           16
7529 #define SCU_RAM_TR_LONG_BUF_27__M                                           0xFFFF
7530 #define SCU_RAM_TR_LONG_BUF_27__PRE                                         0x0
7531 
7532 #define SCU_RAM_TR_LONG_BUF_28__A                                           0x831EEE
7533 #define SCU_RAM_TR_LONG_BUF_28__W                                           16
7534 #define SCU_RAM_TR_LONG_BUF_28__M                                           0xFFFF
7535 #define SCU_RAM_TR_LONG_BUF_28__PRE                                         0x0
7536 
7537 #define SCU_RAM_TR_LONG_BUF_29__A                                           0x831EEF
7538 #define SCU_RAM_TR_LONG_BUF_29__W                                           16
7539 #define SCU_RAM_TR_LONG_BUF_29__M                                           0xFFFF
7540 #define SCU_RAM_TR_LONG_BUF_29__PRE                                         0x0
7541 
7542 #define SCU_RAM_TR_LONG_BUF_30__A                                           0x831EF0
7543 #define SCU_RAM_TR_LONG_BUF_30__W                                           16
7544 #define SCU_RAM_TR_LONG_BUF_30__M                                           0xFFFF
7545 #define SCU_RAM_TR_LONG_BUF_30__PRE                                         0x0
7546 
7547 #define SCU_RAM_TR_LONG_BUF_31__A                                           0x831EF1
7548 #define SCU_RAM_TR_LONG_BUF_31__W                                           16
7549 #define SCU_RAM_TR_LONG_BUF_31__M                                           0xFFFF
7550 #define SCU_RAM_TR_LONG_BUF_31__PRE                                         0x0
7551 #define SCU_RAM_ATV_AMS_MAX__A                                              0x831EF2
7552 #define SCU_RAM_ATV_AMS_MAX__W                                              11
7553 #define SCU_RAM_ATV_AMS_MAX__M                                              0x7FF
7554 #define SCU_RAM_ATV_AMS_MAX__PRE                                            0x0
7555 
7556 #define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__B                                    0
7557 #define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__W                                    11
7558 #define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__M                                    0x7FF
7559 #define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE                                  0x0
7560 
7561 #define SCU_RAM_ATV_AMS_MIN__A                                              0x831EF3
7562 #define SCU_RAM_ATV_AMS_MIN__W                                              11
7563 #define SCU_RAM_ATV_AMS_MIN__M                                              0x7FF
7564 #define SCU_RAM_ATV_AMS_MIN__PRE                                            0x0
7565 
7566 #define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__B                                    0
7567 #define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__W                                    11
7568 #define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__M                                    0x7FF
7569 #define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE                                  0x0
7570 
7571 #define SCU_RAM_ATV_FIELD_CNT__A                                            0x831EF4
7572 #define SCU_RAM_ATV_FIELD_CNT__W                                            9
7573 #define SCU_RAM_ATV_FIELD_CNT__M                                            0x1FF
7574 #define SCU_RAM_ATV_FIELD_CNT__PRE                                          0x0
7575 
7576 #define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B                                0
7577 #define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W                                9
7578 #define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M                                0x1FF
7579 #define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE                              0x0
7580 
7581 #define SCU_RAM_ATV_AAGC_FAST__A                                            0x831EF5
7582 #define SCU_RAM_ATV_AAGC_FAST__W                                            1
7583 #define SCU_RAM_ATV_AAGC_FAST__M                                            0x1
7584 #define SCU_RAM_ATV_AAGC_FAST__PRE                                          0x0
7585 
7586 #define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B                                0
7587 #define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W                                1
7588 #define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M                                0x1
7589 #define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE                              0x0
7590 #define     SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF                             0x0
7591 #define     SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON                              0x1
7592 
7593 #define SCU_RAM_ATV_AAGC_LP2__A                                             0x831EF6
7594 #define SCU_RAM_ATV_AAGC_LP2__W                                             16
7595 #define SCU_RAM_ATV_AAGC_LP2__M                                             0xFFFF
7596 #define SCU_RAM_ATV_AAGC_LP2__PRE                                           0x0
7597 
7598 #define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B                                  0
7599 #define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W                                  16
7600 #define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M                                  0xFFFF
7601 #define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE                                0x0
7602 
7603 #define SCU_RAM_ATV_BP_LVL__A                                               0x831EF7
7604 #define SCU_RAM_ATV_BP_LVL__W                                               11
7605 #define SCU_RAM_ATV_BP_LVL__M                                               0x7FF
7606 #define SCU_RAM_ATV_BP_LVL__PRE                                             0x0
7607 
7608 #define   SCU_RAM_ATV_BP_LVL_BP_LVL__B                                      0
7609 #define   SCU_RAM_ATV_BP_LVL_BP_LVL__W                                      11
7610 #define   SCU_RAM_ATV_BP_LVL_BP_LVL__M                                      0x7FF
7611 #define   SCU_RAM_ATV_BP_LVL_BP_LVL__PRE                                    0x0
7612 
7613 #define SCU_RAM_ATV_BP_RELY__A                                              0x831EF8
7614 #define SCU_RAM_ATV_BP_RELY__W                                              8
7615 #define SCU_RAM_ATV_BP_RELY__M                                              0xFF
7616 #define SCU_RAM_ATV_BP_RELY__PRE                                            0x0
7617 
7618 #define   SCU_RAM_ATV_BP_RELY_BP_RELY__B                                    0
7619 #define   SCU_RAM_ATV_BP_RELY_BP_RELY__W                                    8
7620 #define   SCU_RAM_ATV_BP_RELY_BP_RELY__M                                    0xFF
7621 #define   SCU_RAM_ATV_BP_RELY_BP_RELY__PRE                                  0x0
7622 
7623 #define SCU_RAM_ATV_BP_MTA__A                                               0x831EF9
7624 #define SCU_RAM_ATV_BP_MTA__W                                               14
7625 #define SCU_RAM_ATV_BP_MTA__M                                               0x3FFF
7626 #define SCU_RAM_ATV_BP_MTA__PRE                                             0x0
7627 
7628 #define   SCU_RAM_ATV_BP_MTA_BP_MTA__B                                      0
7629 #define   SCU_RAM_ATV_BP_MTA_BP_MTA__W                                      14
7630 #define   SCU_RAM_ATV_BP_MTA_BP_MTA__M                                      0x3FFF
7631 #define   SCU_RAM_ATV_BP_MTA_BP_MTA__PRE                                    0x0
7632 
7633 #define SCU_RAM_ATV_BP_REF__A                                               0x831EFA
7634 #define SCU_RAM_ATV_BP_REF__W                                               11
7635 #define SCU_RAM_ATV_BP_REF__M                                               0x7FF
7636 #define SCU_RAM_ATV_BP_REF__PRE                                             0x0
7637 
7638 #define   SCU_RAM_ATV_BP_REF_BP_REF__B                                      0
7639 #define   SCU_RAM_ATV_BP_REF_BP_REF__W                                      11
7640 #define   SCU_RAM_ATV_BP_REF_BP_REF__M                                      0x7FF
7641 #define   SCU_RAM_ATV_BP_REF_BP_REF__PRE                                    0x0
7642 
7643 #define SCU_RAM_ATV_BP_REF_MIN__A                                           0x831EFB
7644 #define SCU_RAM_ATV_BP_REF_MIN__W                                           11
7645 #define SCU_RAM_ATV_BP_REF_MIN__M                                           0x7FF
7646 #define SCU_RAM_ATV_BP_REF_MIN__PRE                                         0x0
7647 
7648 #define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B                              0
7649 #define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W                              11
7650 #define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M                              0x7FF
7651 #define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE                            0x0
7652 
7653 #define SCU_RAM_ATV_BP_REF_MAX__A                                           0x831EFC
7654 #define SCU_RAM_ATV_BP_REF_MAX__W                                           11
7655 #define SCU_RAM_ATV_BP_REF_MAX__M                                           0x7FF
7656 #define SCU_RAM_ATV_BP_REF_MAX__PRE                                         0x0
7657 
7658 #define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B                              0
7659 #define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W                              11
7660 #define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M                              0x7FF
7661 #define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE                            0x0
7662 
7663 #define SCU_RAM_ATV_BP_CNT__A                                               0x831EFD
7664 #define SCU_RAM_ATV_BP_CNT__W                                               8
7665 #define SCU_RAM_ATV_BP_CNT__M                                               0xFF
7666 #define SCU_RAM_ATV_BP_CNT__PRE                                             0x0
7667 
7668 #define   SCU_RAM_ATV_BP_CNT_BP_CNT__B                                      0
7669 #define   SCU_RAM_ATV_BP_CNT_BP_CNT__W                                      8
7670 #define   SCU_RAM_ATV_BP_CNT_BP_CNT__M                                      0xFF
7671 #define   SCU_RAM_ATV_BP_CNT_BP_CNT__PRE                                    0x0
7672 
7673 #define SCU_RAM_ATV_BP_XD_CNT__A                                            0x831EFE
7674 #define SCU_RAM_ATV_BP_XD_CNT__W                                            12
7675 #define SCU_RAM_ATV_BP_XD_CNT__M                                            0xFFF
7676 #define SCU_RAM_ATV_BP_XD_CNT__PRE                                          0x0
7677 
7678 #define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B                                0
7679 #define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W                                12
7680 #define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M                                0xFFF
7681 #define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE                              0x0
7682 
7683 #define SCU_RAM_ATV_PAGC_KI_MIN__A                                          0x831EFF
7684 #define SCU_RAM_ATV_PAGC_KI_MIN__W                                          12
7685 #define SCU_RAM_ATV_PAGC_KI_MIN__M                                          0xFFF
7686 #define SCU_RAM_ATV_PAGC_KI_MIN__PRE                                        0x0
7687 
7688 #define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B                            0
7689 #define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W                            12
7690 #define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M                            0xFFF
7691 #define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE                          0x0
7692 
7693 #define SCU_RAM_ATV_BPC_KI_MIN__A                                           0x831F00
7694 #define SCU_RAM_ATV_BPC_KI_MIN__W                                           12
7695 #define SCU_RAM_ATV_BPC_KI_MIN__M                                           0xFFF
7696 #define SCU_RAM_ATV_BPC_KI_MIN__PRE                                         0x0
7697 
7698 #define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B                              0
7699 #define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W                              12
7700 #define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M                              0xFFF
7701 #define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE                            0x0
7702 
7703 #define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A                                0x831F01
7704 #define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W                                16
7705 #define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M                                0xFFFF
7706 #define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__PRE                              0x0
7707 
7708 #define SCU_RAM_ORX_RF_RX_DATA_RATE__A                                      0x831F02
7709 #define SCU_RAM_ORX_RF_RX_DATA_RATE__W                                      8
7710 #define SCU_RAM_ORX_RF_RX_DATA_RATE__M                                      0xFF
7711 #define SCU_RAM_ORX_RF_RX_DATA_RATE__PRE                                    0x0
7712 #define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC                      0x0
7713 #define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC                      0x1
7714 #define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT                  0x40
7715 #define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT                  0x41
7716 #define   SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC                      0x80
7717 #define   SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC                      0x81
7718 #define   SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC                      0xC0
7719 #define   SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC                      0xC1
7720 
7721 #define SCU_RAM_ORX_SCU_STATE__A                                            0x831F03
7722 #define SCU_RAM_ORX_SCU_STATE__W                                            8
7723 #define SCU_RAM_ORX_SCU_STATE__M                                            0xFF
7724 #define SCU_RAM_ORX_SCU_STATE__PRE                                          0x0
7725 #define   SCU_RAM_ORX_SCU_STATE_RESET                                       0x0
7726 #define   SCU_RAM_ORX_SCU_STATE_AGN_HUNT                                    0x1
7727 #define   SCU_RAM_ORX_SCU_STATE_DGN_HUNT                                    0x2
7728 #define   SCU_RAM_ORX_SCU_STATE_AGC_HUNT                                    0x3
7729 #define   SCU_RAM_ORX_SCU_STATE_FRQ_HUNT                                    0x4
7730 #define   SCU_RAM_ORX_SCU_STATE_PHA_HUNT                                    0x8
7731 #define   SCU_RAM_ORX_SCU_STATE_TIM_HUNT                                    0x10
7732 #define   SCU_RAM_ORX_SCU_STATE_EQU_HUNT                                    0x20
7733 #define   SCU_RAM_ORX_SCU_STATE_EQT_HUNT                                    0x30
7734 #define   SCU_RAM_ORX_SCU_STATE_SYNC                                        0x40
7735 
7736 #define SCU_RAM_ORX_SCU_LOCK__A                                             0x831F04
7737 #define SCU_RAM_ORX_SCU_LOCK__W                                             16
7738 #define SCU_RAM_ORX_SCU_LOCK__M                                             0xFFFF
7739 #define SCU_RAM_ORX_SCU_LOCK__PRE                                           0x0
7740 
7741 #define SCU_RAM_ORX_TARGET_MODE__A                                          0x831F05
7742 #define SCU_RAM_ORX_TARGET_MODE__W                                          2
7743 #define SCU_RAM_ORX_TARGET_MODE__M                                          0x3
7744 #define SCU_RAM_ORX_TARGET_MODE__PRE                                        0x0
7745 #define   SCU_RAM_ORX_TARGET_MODE_1544KBPS                                  0x0
7746 #define   SCU_RAM_ORX_TARGET_MODE_3088KBPS                                  0x1
7747 #define   SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT                             0x2
7748 #define   SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO                               0x3
7749 
7750 #define SCU_RAM_ORX_MER_MIN_DB__A                                           0x831F06
7751 #define SCU_RAM_ORX_MER_MIN_DB__W                                           8
7752 #define SCU_RAM_ORX_MER_MIN_DB__M                                           0xFF
7753 #define SCU_RAM_ORX_MER_MIN_DB__PRE                                         0x0
7754 
7755 #define SCU_RAM_ORX_RF_GAIN__A                                              0x831F07
7756 #define SCU_RAM_ORX_RF_GAIN__W                                              16
7757 #define SCU_RAM_ORX_RF_GAIN__M                                              0xFFFF
7758 #define SCU_RAM_ORX_RF_GAIN__PRE                                            0x0
7759 
7760 #define SCU_RAM_ORX_RF_GAIN_MIN__A                                          0x831F08
7761 #define SCU_RAM_ORX_RF_GAIN_MIN__W                                          16
7762 #define SCU_RAM_ORX_RF_GAIN_MIN__M                                          0xFFFF
7763 #define SCU_RAM_ORX_RF_GAIN_MIN__PRE                                        0x0
7764 
7765 #define SCU_RAM_ORX_RF_GAIN_MAX__A                                          0x831F09
7766 #define SCU_RAM_ORX_RF_GAIN_MAX__W                                          16
7767 #define SCU_RAM_ORX_RF_GAIN_MAX__M                                          0xFFFF
7768 #define SCU_RAM_ORX_RF_GAIN_MAX__PRE                                        0x0
7769 
7770 #define SCU_RAM_ORX_IF_GAIN__A                                              0x831F0A
7771 #define SCU_RAM_ORX_IF_GAIN__W                                              16
7772 #define SCU_RAM_ORX_IF_GAIN__M                                              0xFFFF
7773 #define SCU_RAM_ORX_IF_GAIN__PRE                                            0x0
7774 
7775 #define SCU_RAM_ORX_IF_GAIN_MIN__A                                          0x831F0B
7776 #define SCU_RAM_ORX_IF_GAIN_MIN__W                                          16
7777 #define SCU_RAM_ORX_IF_GAIN_MIN__M                                          0xFFFF
7778 #define SCU_RAM_ORX_IF_GAIN_MIN__PRE                                        0x0
7779 
7780 #define SCU_RAM_ORX_IF_GAIN_MAX__A                                          0x831F0C
7781 #define SCU_RAM_ORX_IF_GAIN_MAX__W                                          16
7782 #define SCU_RAM_ORX_IF_GAIN_MAX__M                                          0xFFFF
7783 #define SCU_RAM_ORX_IF_GAIN_MAX__PRE                                        0x0
7784 
7785 #define SCU_RAM_ORX_AGN_HEADR__A                                            0x831F0D
7786 #define SCU_RAM_ORX_AGN_HEADR__W                                            16
7787 #define SCU_RAM_ORX_AGN_HEADR__M                                            0xFFFF
7788 #define SCU_RAM_ORX_AGN_HEADR__PRE                                          0x0
7789 
7790 #define SCU_RAM_ORX_AGN_HEADR_STP__A                                        0x831F0E
7791 #define SCU_RAM_ORX_AGN_HEADR_STP__W                                        8
7792 #define SCU_RAM_ORX_AGN_HEADR_STP__M                                        0xFF
7793 #define SCU_RAM_ORX_AGN_HEADR_STP__PRE                                      0x0
7794 
7795 #define SCU_RAM_ORX_AGN_KI__A                                               0x831F0F
7796 #define SCU_RAM_ORX_AGN_KI__W                                               8
7797 #define SCU_RAM_ORX_AGN_KI__M                                               0xFF
7798 #define SCU_RAM_ORX_AGN_KI__PRE                                             0x0
7799 
7800 #define SCU_RAM_ORX_AGN_LOCK_TH__A                                          0x831F10
7801 #define SCU_RAM_ORX_AGN_LOCK_TH__W                                          16
7802 #define SCU_RAM_ORX_AGN_LOCK_TH__M                                          0xFFFF
7803 #define SCU_RAM_ORX_AGN_LOCK_TH__PRE                                        0x0
7804 
7805 #define SCU_RAM_ORX_AGN_LOCK_WD__A                                          0x831F11
7806 #define SCU_RAM_ORX_AGN_LOCK_WD__W                                          16
7807 #define SCU_RAM_ORX_AGN_LOCK_WD__M                                          0xFFFF
7808 #define SCU_RAM_ORX_AGN_LOCK_WD__PRE                                        0x0
7809 
7810 #define SCU_RAM_ORX_AGN_ONLOCK_TTH__A                                       0x831F12
7811 #define SCU_RAM_ORX_AGN_ONLOCK_TTH__W                                       16
7812 #define SCU_RAM_ORX_AGN_ONLOCK_TTH__M                                       0xFFFF
7813 #define SCU_RAM_ORX_AGN_ONLOCK_TTH__PRE                                     0x0
7814 
7815 #define SCU_RAM_ORX_AGN_UNLOCK_TTH__A                                       0x831F13
7816 #define SCU_RAM_ORX_AGN_UNLOCK_TTH__W                                       16
7817 #define SCU_RAM_ORX_AGN_UNLOCK_TTH__M                                       0xFFFF
7818 #define SCU_RAM_ORX_AGN_UNLOCK_TTH__PRE                                     0x0
7819 
7820 #define SCU_RAM_ORX_AGN_LOCK_TOTH__A                                        0x831F14
7821 #define SCU_RAM_ORX_AGN_LOCK_TOTH__W                                        16
7822 #define SCU_RAM_ORX_AGN_LOCK_TOTH__M                                        0xFFFF
7823 #define SCU_RAM_ORX_AGN_LOCK_TOTH__PRE                                      0x0
7824 
7825 #define SCU_RAM_ORX_AGN_LOCK_MASK__A                                        0x831F15
7826 #define SCU_RAM_ORX_AGN_LOCK_MASK__W                                        8
7827 #define SCU_RAM_ORX_AGN_LOCK_MASK__M                                        0xFF
7828 #define SCU_RAM_ORX_AGN_LOCK_MASK__PRE                                      0x0
7829 
7830 #define SCU_RAM_ORX_DGN__A                                                  0x831F16
7831 #define SCU_RAM_ORX_DGN__W                                                  16
7832 #define SCU_RAM_ORX_DGN__M                                                  0xFFFF
7833 #define SCU_RAM_ORX_DGN__PRE                                                0x0
7834 
7835 #define SCU_RAM_ORX_DGN_MIN__A                                              0x831F17
7836 #define SCU_RAM_ORX_DGN_MIN__W                                              16
7837 #define SCU_RAM_ORX_DGN_MIN__M                                              0xFFFF
7838 #define SCU_RAM_ORX_DGN_MIN__PRE                                            0x0
7839 
7840 #define SCU_RAM_ORX_DGN_MAX__A                                              0x831F18
7841 #define SCU_RAM_ORX_DGN_MAX__W                                              16
7842 #define SCU_RAM_ORX_DGN_MAX__M                                              0xFFFF
7843 #define SCU_RAM_ORX_DGN_MAX__PRE                                            0x0
7844 
7845 #define SCU_RAM_ORX_DGN_AMP__A                                              0x831F19
7846 #define SCU_RAM_ORX_DGN_AMP__W                                              16
7847 #define SCU_RAM_ORX_DGN_AMP__M                                              0xFFFF
7848 #define SCU_RAM_ORX_DGN_AMP__PRE                                            0x0
7849 
7850 #define SCU_RAM_ORX_DGN_AMPTARGET__A                                        0x831F1A
7851 #define SCU_RAM_ORX_DGN_AMPTARGET__W                                        16
7852 #define SCU_RAM_ORX_DGN_AMPTARGET__M                                        0xFFFF
7853 #define SCU_RAM_ORX_DGN_AMPTARGET__PRE                                      0x0
7854 
7855 #define SCU_RAM_ORX_DGN_KI__A                                               0x831F1B
7856 #define SCU_RAM_ORX_DGN_KI__W                                               8
7857 #define SCU_RAM_ORX_DGN_KI__M                                               0xFF
7858 #define SCU_RAM_ORX_DGN_KI__PRE                                             0x0
7859 
7860 #define SCU_RAM_ORX_DGN_LOCK_TH__A                                          0x831F1C
7861 #define SCU_RAM_ORX_DGN_LOCK_TH__W                                          16
7862 #define SCU_RAM_ORX_DGN_LOCK_TH__M                                          0xFFFF
7863 #define SCU_RAM_ORX_DGN_LOCK_TH__PRE                                        0x0
7864 
7865 #define SCU_RAM_ORX_DGN_LOCK_WD__A                                          0x831F1D
7866 #define SCU_RAM_ORX_DGN_LOCK_WD__W                                          16
7867 #define SCU_RAM_ORX_DGN_LOCK_WD__M                                          0xFFFF
7868 #define SCU_RAM_ORX_DGN_LOCK_WD__PRE                                        0x0
7869 
7870 #define SCU_RAM_ORX_DGN_ONLOCK_TTH__A                                       0x831F1E
7871 #define SCU_RAM_ORX_DGN_ONLOCK_TTH__W                                       16
7872 #define SCU_RAM_ORX_DGN_ONLOCK_TTH__M                                       0xFFFF
7873 #define SCU_RAM_ORX_DGN_ONLOCK_TTH__PRE                                     0x0
7874 
7875 #define SCU_RAM_ORX_DGN_UNLOCK_TTH__A                                       0x831F1F
7876 #define SCU_RAM_ORX_DGN_UNLOCK_TTH__W                                       16
7877 #define SCU_RAM_ORX_DGN_UNLOCK_TTH__M                                       0xFFFF
7878 #define SCU_RAM_ORX_DGN_UNLOCK_TTH__PRE                                     0x0
7879 
7880 #define SCU_RAM_ORX_DGN_LOCK_TOTH__A                                        0x831F20
7881 #define SCU_RAM_ORX_DGN_LOCK_TOTH__W                                        16
7882 #define SCU_RAM_ORX_DGN_LOCK_TOTH__M                                        0xFFFF
7883 #define SCU_RAM_ORX_DGN_LOCK_TOTH__PRE                                      0x0
7884 
7885 #define SCU_RAM_ORX_DGN_LOCK_MASK__A                                        0x831F21
7886 #define SCU_RAM_ORX_DGN_LOCK_MASK__W                                        8
7887 #define SCU_RAM_ORX_DGN_LOCK_MASK__M                                        0xFF
7888 #define SCU_RAM_ORX_DGN_LOCK_MASK__PRE                                      0x0
7889 
7890 #define SCU_RAM_ORX_FREQ_GAIN_CORR__A                                       0x831F22
7891 #define SCU_RAM_ORX_FREQ_GAIN_CORR__W                                       8
7892 #define SCU_RAM_ORX_FREQ_GAIN_CORR__M                                       0xFF
7893 #define SCU_RAM_ORX_FREQ_GAIN_CORR__PRE                                     0x0
7894 #define   SCU_RAM_ORX_FREQ_GAIN_CORR_1544KBPS                               0x60
7895 #define   SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS                               0x80
7896 #define   SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS                               0xC0
7897 
7898 #define SCU_RAM_ORX_FRQ_OFFSET__A                                           0x831F23
7899 #define SCU_RAM_ORX_FRQ_OFFSET__W                                           16
7900 #define SCU_RAM_ORX_FRQ_OFFSET__M                                           0xFFFF
7901 #define SCU_RAM_ORX_FRQ_OFFSET__PRE                                         0x0
7902 
7903 #define SCU_RAM_ORX_FRQ_OFFSET_MAX__A                                       0x831F24
7904 #define SCU_RAM_ORX_FRQ_OFFSET_MAX__W                                       15
7905 #define SCU_RAM_ORX_FRQ_OFFSET_MAX__M                                       0x7FFF
7906 #define SCU_RAM_ORX_FRQ_OFFSET_MAX__PRE                                     0x0
7907 
7908 #define SCU_RAM_ORX_FRQ_KI__A                                               0x831F25
7909 #define SCU_RAM_ORX_FRQ_KI__W                                               8
7910 #define SCU_RAM_ORX_FRQ_KI__M                                               0xFF
7911 #define SCU_RAM_ORX_FRQ_KI__PRE                                             0x0
7912 
7913 #define SCU_RAM_ORX_FRQ_DIFF__A                                             0x831F26
7914 #define SCU_RAM_ORX_FRQ_DIFF__W                                             16
7915 #define SCU_RAM_ORX_FRQ_DIFF__M                                             0xFFFF
7916 #define SCU_RAM_ORX_FRQ_DIFF__PRE                                           0x0
7917 
7918 #define SCU_RAM_ORX_FRQ_LOCK_TH__A                                          0x831F27
7919 #define SCU_RAM_ORX_FRQ_LOCK_TH__W                                          16
7920 #define SCU_RAM_ORX_FRQ_LOCK_TH__M                                          0xFFFF
7921 #define SCU_RAM_ORX_FRQ_LOCK_TH__PRE                                        0x0
7922 
7923 #define SCU_RAM_ORX_FRQ_LOCK_WD__A                                          0x831F28
7924 #define SCU_RAM_ORX_FRQ_LOCK_WD__W                                          16
7925 #define SCU_RAM_ORX_FRQ_LOCK_WD__M                                          0xFFFF
7926 #define SCU_RAM_ORX_FRQ_LOCK_WD__PRE                                        0x0
7927 
7928 #define SCU_RAM_ORX_FRQ_ONLOCK_TTH__A                                       0x831F29
7929 #define SCU_RAM_ORX_FRQ_ONLOCK_TTH__W                                       16
7930 #define SCU_RAM_ORX_FRQ_ONLOCK_TTH__M                                       0xFFFF
7931 #define SCU_RAM_ORX_FRQ_ONLOCK_TTH__PRE                                     0x0
7932 
7933 #define SCU_RAM_ORX_FRQ_UNLOCK_TTH__A                                       0x831F2A
7934 #define SCU_RAM_ORX_FRQ_UNLOCK_TTH__W                                       16
7935 #define SCU_RAM_ORX_FRQ_UNLOCK_TTH__M                                       0xFFFF
7936 #define SCU_RAM_ORX_FRQ_UNLOCK_TTH__PRE                                     0x0
7937 
7938 #define SCU_RAM_ORX_FRQ_LOCK_TOTH__A                                        0x831F2B
7939 #define SCU_RAM_ORX_FRQ_LOCK_TOTH__W                                        16
7940 #define SCU_RAM_ORX_FRQ_LOCK_TOTH__M                                        0xFFFF
7941 #define SCU_RAM_ORX_FRQ_LOCK_TOTH__PRE                                      0x0
7942 
7943 #define SCU_RAM_ORX_FRQ_LOCK_MASK__A                                        0x831F2C
7944 #define SCU_RAM_ORX_FRQ_LOCK_MASK__W                                        8
7945 #define SCU_RAM_ORX_FRQ_LOCK_MASK__M                                        0xFF
7946 #define SCU_RAM_ORX_FRQ_LOCK_MASK__PRE                                      0x0
7947 
7948 #define SCU_RAM_ORX_PHA_DIFF__A                                             0x831F2D
7949 #define SCU_RAM_ORX_PHA_DIFF__W                                             16
7950 #define SCU_RAM_ORX_PHA_DIFF__M                                             0xFFFF
7951 #define SCU_RAM_ORX_PHA_DIFF__PRE                                           0x0
7952 
7953 #define SCU_RAM_ORX_PHA_LOCK_TH__A                                          0x831F2E
7954 #define SCU_RAM_ORX_PHA_LOCK_TH__W                                          16
7955 #define SCU_RAM_ORX_PHA_LOCK_TH__M                                          0xFFFF
7956 #define SCU_RAM_ORX_PHA_LOCK_TH__PRE                                        0x0
7957 
7958 #define SCU_RAM_ORX_PHA_LOCK_WD__A                                          0x831F2F
7959 #define SCU_RAM_ORX_PHA_LOCK_WD__W                                          16
7960 #define SCU_RAM_ORX_PHA_LOCK_WD__M                                          0xFFFF
7961 #define SCU_RAM_ORX_PHA_LOCK_WD__PRE                                        0x0
7962 
7963 #define SCU_RAM_ORX_PHA_ONLOCK_TTH__A                                       0x831F30
7964 #define SCU_RAM_ORX_PHA_ONLOCK_TTH__W                                       16
7965 #define SCU_RAM_ORX_PHA_ONLOCK_TTH__M                                       0xFFFF
7966 #define SCU_RAM_ORX_PHA_ONLOCK_TTH__PRE                                     0x0
7967 
7968 #define SCU_RAM_ORX_PHA_UNLOCK_TTH__A                                       0x831F31
7969 #define SCU_RAM_ORX_PHA_UNLOCK_TTH__W                                       16
7970 #define SCU_RAM_ORX_PHA_UNLOCK_TTH__M                                       0xFFFF
7971 #define SCU_RAM_ORX_PHA_UNLOCK_TTH__PRE                                     0x0
7972 
7973 #define SCU_RAM_ORX_PHA_LOCK_TOTH__A                                        0x831F32
7974 #define SCU_RAM_ORX_PHA_LOCK_TOTH__W                                        16
7975 #define SCU_RAM_ORX_PHA_LOCK_TOTH__M                                        0xFFFF
7976 #define SCU_RAM_ORX_PHA_LOCK_TOTH__PRE                                      0x0
7977 
7978 #define SCU_RAM_ORX_PHA_LOCK_MASK__A                                        0x831F33
7979 #define SCU_RAM_ORX_PHA_LOCK_MASK__W                                        8
7980 #define SCU_RAM_ORX_PHA_LOCK_MASK__M                                        0xFF
7981 #define SCU_RAM_ORX_PHA_LOCK_MASK__PRE                                      0x0
7982 
7983 #define SCU_RAM_ORX_TIM_OFFSET__A                                           0x831F34
7984 #define SCU_RAM_ORX_TIM_OFFSET__W                                           16
7985 #define SCU_RAM_ORX_TIM_OFFSET__M                                           0xFFFF
7986 #define SCU_RAM_ORX_TIM_OFFSET__PRE                                         0x0
7987 
7988 #define SCU_RAM_ORX_TIM_DIFF__A                                             0x831F35
7989 #define SCU_RAM_ORX_TIM_DIFF__W                                             16
7990 #define SCU_RAM_ORX_TIM_DIFF__M                                             0xFFFF
7991 #define SCU_RAM_ORX_TIM_DIFF__PRE                                           0x0
7992 
7993 #define SCU_RAM_ORX_TIM_LOCK_TH__A                                          0x831F36
7994 #define SCU_RAM_ORX_TIM_LOCK_TH__W                                          16
7995 #define SCU_RAM_ORX_TIM_LOCK_TH__M                                          0xFFFF
7996 #define SCU_RAM_ORX_TIM_LOCK_TH__PRE                                        0x0
7997 
7998 #define SCU_RAM_ORX_TIM_LOCK_WD__A                                          0x831F37
7999 #define SCU_RAM_ORX_TIM_LOCK_WD__W                                          16
8000 #define SCU_RAM_ORX_TIM_LOCK_WD__M                                          0xFFFF
8001 #define SCU_RAM_ORX_TIM_LOCK_WD__PRE                                        0x0
8002 
8003 #define SCU_RAM_ORX_TIM_ONLOCK_TTH__A                                       0x831F38
8004 #define SCU_RAM_ORX_TIM_ONLOCK_TTH__W                                       16
8005 #define SCU_RAM_ORX_TIM_ONLOCK_TTH__M                                       0xFFFF
8006 #define SCU_RAM_ORX_TIM_ONLOCK_TTH__PRE                                     0x0
8007 
8008 #define SCU_RAM_ORX_TIM_UNLOCK_TTH__A                                       0x831F39
8009 #define SCU_RAM_ORX_TIM_UNLOCK_TTH__W                                       16
8010 #define SCU_RAM_ORX_TIM_UNLOCK_TTH__M                                       0xFFFF
8011 #define SCU_RAM_ORX_TIM_UNLOCK_TTH__PRE                                     0x0
8012 
8013 #define SCU_RAM_ORX_TIM_LOCK_TOTH__A                                        0x831F3A
8014 #define SCU_RAM_ORX_TIM_LOCK_TOTH__W                                        16
8015 #define SCU_RAM_ORX_TIM_LOCK_TOTH__M                                        0xFFFF
8016 #define SCU_RAM_ORX_TIM_LOCK_TOTH__PRE                                      0x0
8017 
8018 #define SCU_RAM_ORX_TIM_LOCK_MASK__A                                        0x831F3B
8019 #define SCU_RAM_ORX_TIM_LOCK_MASK__W                                        8
8020 #define SCU_RAM_ORX_TIM_LOCK_MASK__M                                        0xFF
8021 #define SCU_RAM_ORX_TIM_LOCK_MASK__PRE                                      0x0
8022 
8023 #define SCU_RAM_ORX_EQU_DIFF__A                                             0x831F3C
8024 #define SCU_RAM_ORX_EQU_DIFF__W                                             16
8025 #define SCU_RAM_ORX_EQU_DIFF__M                                             0xFFFF
8026 #define SCU_RAM_ORX_EQU_DIFF__PRE                                           0x0
8027 
8028 #define SCU_RAM_ORX_EQU_LOCK_TH__A                                          0x831F3D
8029 #define SCU_RAM_ORX_EQU_LOCK_TH__W                                          16
8030 #define SCU_RAM_ORX_EQU_LOCK_TH__M                                          0xFFFF
8031 #define SCU_RAM_ORX_EQU_LOCK_TH__PRE                                        0x0
8032 
8033 #define SCU_RAM_ORX_EQU_LOCK_WD__A                                          0x831F3E
8034 #define SCU_RAM_ORX_EQU_LOCK_WD__W                                          16
8035 #define SCU_RAM_ORX_EQU_LOCK_WD__M                                          0xFFFF
8036 #define SCU_RAM_ORX_EQU_LOCK_WD__PRE                                        0x0
8037 
8038 #define SCU_RAM_ORX_EQU_ONLOCK_TTH__A                                       0x831F3F
8039 #define SCU_RAM_ORX_EQU_ONLOCK_TTH__W                                       16
8040 #define SCU_RAM_ORX_EQU_ONLOCK_TTH__M                                       0xFFFF
8041 #define SCU_RAM_ORX_EQU_ONLOCK_TTH__PRE                                     0x0
8042 
8043 #define SCU_RAM_ORX_EQU_UNLOCK_TTH__A                                       0x831F40
8044 #define SCU_RAM_ORX_EQU_UNLOCK_TTH__W                                       16
8045 #define SCU_RAM_ORX_EQU_UNLOCK_TTH__M                                       0xFFFF
8046 #define SCU_RAM_ORX_EQU_UNLOCK_TTH__PRE                                     0x0
8047 
8048 #define SCU_RAM_ORX_EQU_LOCK_TOTH__A                                        0x831F41
8049 #define SCU_RAM_ORX_EQU_LOCK_TOTH__W                                        16
8050 #define SCU_RAM_ORX_EQU_LOCK_TOTH__M                                        0xFFFF
8051 #define SCU_RAM_ORX_EQU_LOCK_TOTH__PRE                                      0x0
8052 
8053 #define SCU_RAM_ORX_EQU_LOCK_MASK__A                                        0x831F42
8054 #define SCU_RAM_ORX_EQU_LOCK_MASK__W                                        8
8055 #define SCU_RAM_ORX_EQU_LOCK_MASK__M                                        0xFF
8056 #define SCU_RAM_ORX_EQU_LOCK_MASK__PRE                                      0x0
8057 
8058 #define SCU_RAM_ORX_FLT_FRQ__A                                              0x831F43
8059 #define SCU_RAM_ORX_FLT_FRQ__W                                              16
8060 #define SCU_RAM_ORX_FLT_FRQ__M                                              0xFFFF
8061 #define SCU_RAM_ORX_FLT_FRQ__PRE                                            0x0
8062 #define SCU_RAM_ORX_RST_CPH__A                                              0x831F44
8063 #define SCU_RAM_ORX_RST_CPH__W                                              4
8064 #define SCU_RAM_ORX_RST_CPH__M                                              0xF
8065 #define SCU_RAM_ORX_RST_CPH__PRE                                            0x0
8066 
8067 #define   SCU_RAM_ORX_RST_CPH_RST_CPH__B                                    0
8068 #define   SCU_RAM_ORX_RST_CPH_RST_CPH__W                                    4
8069 #define   SCU_RAM_ORX_RST_CPH_RST_CPH__M                                    0xF
8070 #define   SCU_RAM_ORX_RST_CPH_RST_CPH__PRE                                  0x0
8071 
8072 #define SCU_RAM_ORX_RST_CTI__A                                              0x831F45
8073 #define SCU_RAM_ORX_RST_CTI__W                                              4
8074 #define SCU_RAM_ORX_RST_CTI__M                                              0xF
8075 #define SCU_RAM_ORX_RST_CTI__PRE                                            0x0
8076 
8077 #define   SCU_RAM_ORX_RST_CTI_RST_CTI__B                                    0
8078 #define   SCU_RAM_ORX_RST_CTI_RST_CTI__W                                    4
8079 #define   SCU_RAM_ORX_RST_CTI_RST_CTI__M                                    0xF
8080 #define   SCU_RAM_ORX_RST_CTI_RST_CTI__PRE                                  0x0
8081 
8082 #define SCU_RAM_ORX_RST_KRN__A                                              0x831F46
8083 #define SCU_RAM_ORX_RST_KRN__W                                              4
8084 #define SCU_RAM_ORX_RST_KRN__M                                              0xF
8085 #define SCU_RAM_ORX_RST_KRN__PRE                                            0x0
8086 
8087 #define   SCU_RAM_ORX_RST_KRN_RST_KRN__B                                    0
8088 #define   SCU_RAM_ORX_RST_KRN_RST_KRN__W                                    4
8089 #define   SCU_RAM_ORX_RST_KRN_RST_KRN__M                                    0xF
8090 #define   SCU_RAM_ORX_RST_KRN_RST_KRN__PRE                                  0x0
8091 
8092 #define SCU_RAM_ORX_RST_KRP__A                                              0x831F47
8093 #define SCU_RAM_ORX_RST_KRP__W                                              4
8094 #define SCU_RAM_ORX_RST_KRP__M                                              0xF
8095 #define SCU_RAM_ORX_RST_KRP__PRE                                            0x0
8096 
8097 #define   SCU_RAM_ORX_RST_KRP_RST_KRP__B                                    0
8098 #define   SCU_RAM_ORX_RST_KRP_RST_KRP__W                                    4
8099 #define   SCU_RAM_ORX_RST_KRP_RST_KRP__M                                    0xF
8100 #define   SCU_RAM_ORX_RST_KRP_RST_KRP__PRE                                  0x0
8101 
8102 #define SCU_RAM_ATV_STANDARD__A                                             0x831F48
8103 #define SCU_RAM_ATV_STANDARD__W                                             12
8104 #define SCU_RAM_ATV_STANDARD__M                                             0xFFF
8105 #define SCU_RAM_ATV_STANDARD__PRE                                           0x0
8106 
8107 #define   SCU_RAM_ATV_STANDARD_STANDARD__B                                  0
8108 #define   SCU_RAM_ATV_STANDARD_STANDARD__W                                  12
8109 #define   SCU_RAM_ATV_STANDARD_STANDARD__M                                  0xFFF
8110 #define   SCU_RAM_ATV_STANDARD_STANDARD__PRE                                0x0
8111 #define     SCU_RAM_ATV_STANDARD_STANDARD_MN                                0x2
8112 #define     SCU_RAM_ATV_STANDARD_STANDARD_B                                 0x103
8113 #define     SCU_RAM_ATV_STANDARD_STANDARD_G                                 0x3
8114 #define     SCU_RAM_ATV_STANDARD_STANDARD_DK                                0x4
8115 #define     SCU_RAM_ATV_STANDARD_STANDARD_L                                 0x9
8116 #define     SCU_RAM_ATV_STANDARD_STANDARD_LP                                0x109
8117 #define     SCU_RAM_ATV_STANDARD_STANDARD_I                                 0xA
8118 #define     SCU_RAM_ATV_STANDARD_STANDARD_FM                                0x40
8119 
8120 #define SCU_RAM_ATV_DETECT__A                                               0x831F49
8121 #define SCU_RAM_ATV_DETECT__W                                               1
8122 #define SCU_RAM_ATV_DETECT__M                                               0x1
8123 #define SCU_RAM_ATV_DETECT__PRE                                             0x0
8124 
8125 #define   SCU_RAM_ATV_DETECT_DETECT__B                                      0
8126 #define   SCU_RAM_ATV_DETECT_DETECT__W                                      1
8127 #define   SCU_RAM_ATV_DETECT_DETECT__M                                      0x1
8128 #define   SCU_RAM_ATV_DETECT_DETECT__PRE                                    0x0
8129 #define     SCU_RAM_ATV_DETECT_DETECT_false                                 0x0
8130 #define     SCU_RAM_ATV_DETECT_DETECT_true                                  0x1
8131 
8132 #define SCU_RAM_ATV_DETECT_TH__A                                            0x831F4A
8133 #define SCU_RAM_ATV_DETECT_TH__W                                            8
8134 #define SCU_RAM_ATV_DETECT_TH__M                                            0xFF
8135 #define SCU_RAM_ATV_DETECT_TH__PRE                                          0x0
8136 
8137 #define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__B                                0
8138 #define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__W                                8
8139 #define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__M                                0xFF
8140 #define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE                              0x0
8141 
8142 #define SCU_RAM_ATV_LOCK__A                                                 0x831F4B
8143 #define SCU_RAM_ATV_LOCK__W                                                 2
8144 #define SCU_RAM_ATV_LOCK__M                                                 0x3
8145 #define SCU_RAM_ATV_LOCK__PRE                                               0x0
8146 
8147 #define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B                                   0
8148 #define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W                                   1
8149 #define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M                                   0x1
8150 #define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE                                 0x0
8151 #define     SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK                            0x0
8152 #define     SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK                               0x1
8153 
8154 #define   SCU_RAM_ATV_LOCK_SYNC_FLAG__B                                     1
8155 #define   SCU_RAM_ATV_LOCK_SYNC_FLAG__W                                     1
8156 #define   SCU_RAM_ATV_LOCK_SYNC_FLAG__M                                     0x2
8157 #define   SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE                                   0x0
8158 #define     SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC                              0x0
8159 #define     SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC                                 0x2
8160 
8161 #define SCU_RAM_ATV_CR_LOCK__A                                              0x831F4C
8162 #define SCU_RAM_ATV_CR_LOCK__W                                              11
8163 #define SCU_RAM_ATV_CR_LOCK__M                                              0x7FF
8164 #define SCU_RAM_ATV_CR_LOCK__PRE                                            0x0
8165 
8166 #define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__B                                    0
8167 #define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__W                                    11
8168 #define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__M                                    0x7FF
8169 #define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE                                  0x0
8170 
8171 #define SCU_RAM_ATV_AGC_MODE__A                                             0x831F4D
8172 #define SCU_RAM_ATV_AGC_MODE__W                                             8
8173 #define SCU_RAM_ATV_AGC_MODE__M                                             0xFF
8174 #define SCU_RAM_ATV_AGC_MODE__PRE                                           0x0
8175 
8176 #define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B                                  2
8177 #define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W                                  1
8178 #define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M                                  0x4
8179 #define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE                                0x0
8180 #define     SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST                          0x0
8181 #define     SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW                          0x4
8182 
8183 #define   SCU_RAM_ATV_AGC_MODE_BP_EN__B                                     3
8184 #define   SCU_RAM_ATV_AGC_MODE_BP_EN__W                                     1
8185 #define   SCU_RAM_ATV_AGC_MODE_BP_EN__M                                     0x8
8186 #define   SCU_RAM_ATV_AGC_MODE_BP_EN__PRE                                   0x0
8187 #define     SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE                          0x0
8188 #define     SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE                           0x8
8189 
8190 #define   SCU_RAM_ATV_AGC_MODE_SIF_STD__B                                   4
8191 #define   SCU_RAM_ATV_AGC_MODE_SIF_STD__W                                   2
8192 #define   SCU_RAM_ATV_AGC_MODE_SIF_STD__M                                   0x30
8193 #define   SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE                                 0x0
8194 #define     SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF                        0x0
8195 #define     SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM                         0x10
8196 #define     SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM                         0x20
8197 
8198 #define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B                              6
8199 #define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W                              1
8200 #define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M                              0x40
8201 #define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE                            0x0
8202 #define     SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE                  0x0
8203 #define     SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE                   0x40
8204 
8205 #define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B                                 7
8206 #define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W                                 1
8207 #define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M                                 0x80
8208 #define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE                               0x0
8209 #define     SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE                       0x0
8210 #define     SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE                      0x80
8211 
8212 #define SCU_RAM_ATV_RSV_01__A                                               0x831F4E
8213 #define SCU_RAM_ATV_RSV_01__W                                               16
8214 #define SCU_RAM_ATV_RSV_01__M                                               0xFFFF
8215 #define SCU_RAM_ATV_RSV_01__PRE                                             0x0
8216 
8217 #define SCU_RAM_ATV_RSV_02__A                                               0x831F4F
8218 #define SCU_RAM_ATV_RSV_02__W                                               16
8219 #define SCU_RAM_ATV_RSV_02__M                                               0xFFFF
8220 #define SCU_RAM_ATV_RSV_02__PRE                                             0x0
8221 
8222 #define SCU_RAM_ATV_RSV_03__A                                               0x831F50
8223 #define SCU_RAM_ATV_RSV_03__W                                               16
8224 #define SCU_RAM_ATV_RSV_03__M                                               0xFFFF
8225 #define SCU_RAM_ATV_RSV_03__PRE                                             0x0
8226 
8227 #define SCU_RAM_ATV_RSV_04__A                                               0x831F51
8228 #define SCU_RAM_ATV_RSV_04__W                                               16
8229 #define SCU_RAM_ATV_RSV_04__M                                               0xFFFF
8230 #define SCU_RAM_ATV_RSV_04__PRE                                             0x0
8231 #define SCU_RAM_ATV_FAGC_TH_RED__A                                          0x831F52
8232 #define SCU_RAM_ATV_FAGC_TH_RED__W                                          8
8233 #define SCU_RAM_ATV_FAGC_TH_RED__M                                          0xFF
8234 #define SCU_RAM_ATV_FAGC_TH_RED__PRE                                        0x0
8235 
8236 #define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B                            0
8237 #define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W                            8
8238 #define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M                            0xFF
8239 #define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE                          0x0
8240 
8241 #define SCU_RAM_ATV_AMS_MAX_REF__A                                          0x831F53
8242 #define SCU_RAM_ATV_AMS_MAX_REF__W                                          11
8243 #define SCU_RAM_ATV_AMS_MAX_REF__M                                          0x7FF
8244 #define SCU_RAM_ATV_AMS_MAX_REF__PRE                                        0x0
8245 
8246 #define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B                            0
8247 #define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W                            11
8248 #define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M                            0x7FF
8249 #define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE                          0x0
8250 #define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN                       0x2BC
8251 #define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK                          0x2D0
8252 #define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I                           0x314
8253 #define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP                         0x28A
8254 
8255 #define SCU_RAM_ATV_ACT_AMX__A                                              0x831F54
8256 #define SCU_RAM_ATV_ACT_AMX__W                                              11
8257 #define SCU_RAM_ATV_ACT_AMX__M                                              0x7FF
8258 #define SCU_RAM_ATV_ACT_AMX__PRE                                            0x0
8259 
8260 #define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__B                                    0
8261 #define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__W                                    11
8262 #define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__M                                    0x7FF
8263 #define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE                                  0x0
8264 
8265 #define SCU_RAM_ATV_ACT_AMI__A                                              0x831F55
8266 #define SCU_RAM_ATV_ACT_AMI__W                                              11
8267 #define SCU_RAM_ATV_ACT_AMI__M                                              0x7FF
8268 #define SCU_RAM_ATV_ACT_AMI__PRE                                            0x0
8269 
8270 #define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__B                                    0
8271 #define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__W                                    11
8272 #define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__M                                    0x7FF
8273 #define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE                                  0x0
8274 
8275 #define SCU_RAM_ATV_RSV_05__A                                               0x831F56
8276 #define SCU_RAM_ATV_RSV_05__W                                               16
8277 #define SCU_RAM_ATV_RSV_05__M                                               0xFFFF
8278 #define SCU_RAM_ATV_RSV_05__PRE                                             0x0
8279 
8280 #define SCU_RAM_ATV_RSV_06__A                                               0x831F57
8281 #define SCU_RAM_ATV_RSV_06__W                                               16
8282 #define SCU_RAM_ATV_RSV_06__M                                               0xFFFF
8283 #define SCU_RAM_ATV_RSV_06__PRE                                             0x0
8284 
8285 #define SCU_RAM_ATV_RSV_07__A                                               0x831F58
8286 #define SCU_RAM_ATV_RSV_07__W                                               16
8287 #define SCU_RAM_ATV_RSV_07__M                                               0xFFFF
8288 #define SCU_RAM_ATV_RSV_07__PRE                                             0x0
8289 
8290 #define SCU_RAM_ATV_RSV_08__A                                               0x831F59
8291 #define SCU_RAM_ATV_RSV_08__W                                               16
8292 #define SCU_RAM_ATV_RSV_08__M                                               0xFFFF
8293 #define SCU_RAM_ATV_RSV_08__PRE                                             0x0
8294 
8295 #define SCU_RAM_ATV_RSV_09__A                                               0x831F5A
8296 #define SCU_RAM_ATV_RSV_09__W                                               16
8297 #define SCU_RAM_ATV_RSV_09__M                                               0xFFFF
8298 #define SCU_RAM_ATV_RSV_09__PRE                                             0x0
8299 
8300 #define SCU_RAM_ATV_RSV_10__A                                               0x831F5B
8301 #define SCU_RAM_ATV_RSV_10__W                                               16
8302 #define SCU_RAM_ATV_RSV_10__M                                               0xFFFF
8303 #define SCU_RAM_ATV_RSV_10__PRE                                             0x0
8304 
8305 #define SCU_RAM_ATV_RSV_11__A                                               0x831F5C
8306 #define SCU_RAM_ATV_RSV_11__W                                               16
8307 #define SCU_RAM_ATV_RSV_11__M                                               0xFFFF
8308 #define SCU_RAM_ATV_RSV_11__PRE                                             0x0
8309 
8310 #define SCU_RAM_ATV_RSV_12__A                                               0x831F5D
8311 #define SCU_RAM_ATV_RSV_12__W                                               16
8312 #define SCU_RAM_ATV_RSV_12__M                                               0xFFFF
8313 #define SCU_RAM_ATV_RSV_12__PRE                                             0x0
8314 #define SCU_RAM_ATV_VID_GAIN_HI__A                                          0x831F5E
8315 #define SCU_RAM_ATV_VID_GAIN_HI__W                                          16
8316 #define SCU_RAM_ATV_VID_GAIN_HI__M                                          0xFFFF
8317 #define SCU_RAM_ATV_VID_GAIN_HI__PRE                                        0x0
8318 
8319 #define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B                            0
8320 #define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W                            16
8321 #define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M                            0xFFFF
8322 #define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE                          0x0
8323 
8324 #define SCU_RAM_ATV_VID_GAIN_LO__A                                          0x831F5F
8325 #define SCU_RAM_ATV_VID_GAIN_LO__W                                          8
8326 #define SCU_RAM_ATV_VID_GAIN_LO__M                                          0xFF
8327 #define SCU_RAM_ATV_VID_GAIN_LO__PRE                                        0x0
8328 
8329 #define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B                            0
8330 #define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W                            8
8331 #define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M                            0xFF
8332 #define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE                          0x0
8333 
8334 #define SCU_RAM_ATV_RSV_13__A                                               0x831F60
8335 #define SCU_RAM_ATV_RSV_13__W                                               16
8336 #define SCU_RAM_ATV_RSV_13__M                                               0xFFFF
8337 #define SCU_RAM_ATV_RSV_13__PRE                                             0x0
8338 
8339 #define SCU_RAM_ATV_RSV_14__A                                               0x831F61
8340 #define SCU_RAM_ATV_RSV_14__W                                               16
8341 #define SCU_RAM_ATV_RSV_14__M                                               0xFFFF
8342 #define SCU_RAM_ATV_RSV_14__PRE                                             0x0
8343 
8344 #define SCU_RAM_ATV_RSV_15__A                                               0x831F62
8345 #define SCU_RAM_ATV_RSV_15__W                                               16
8346 #define SCU_RAM_ATV_RSV_15__M                                               0xFFFF
8347 #define SCU_RAM_ATV_RSV_15__PRE                                             0x0
8348 
8349 #define SCU_RAM_ATV_RSV_16__A                                               0x831F63
8350 #define SCU_RAM_ATV_RSV_16__W                                               16
8351 #define SCU_RAM_ATV_RSV_16__M                                               0xFFFF
8352 #define SCU_RAM_ATV_RSV_16__PRE                                             0x0
8353 #define SCU_RAM_ATV_AAGC_CNT__A                                             0x831F64
8354 #define SCU_RAM_ATV_AAGC_CNT__W                                             8
8355 #define SCU_RAM_ATV_AAGC_CNT__M                                             0xFF
8356 #define SCU_RAM_ATV_AAGC_CNT__PRE                                           0x0
8357 
8358 #define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B                                  0
8359 #define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W                                  8
8360 #define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M                                  0xFF
8361 #define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE                                0x0
8362 
8363 #define SCU_RAM_ATV_SIF_GAIN__A                                             0x831F65
8364 #define SCU_RAM_ATV_SIF_GAIN__W                                             11
8365 #define SCU_RAM_ATV_SIF_GAIN__M                                             0x7FF
8366 #define SCU_RAM_ATV_SIF_GAIN__PRE                                           0x0
8367 
8368 #define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B                                  0
8369 #define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W                                  11
8370 #define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M                                  0x7FF
8371 #define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE                                0x0
8372 
8373 #define SCU_RAM_ATV_RSV_17__A                                               0x831F66
8374 #define SCU_RAM_ATV_RSV_17__W                                               16
8375 #define SCU_RAM_ATV_RSV_17__M                                               0xFFFF
8376 #define SCU_RAM_ATV_RSV_17__PRE                                             0x0
8377 
8378 #define SCU_RAM_ATV_RSV_18__A                                               0x831F67
8379 #define SCU_RAM_ATV_RSV_18__W                                               16
8380 #define SCU_RAM_ATV_RSV_18__M                                               0xFFFF
8381 #define SCU_RAM_ATV_RSV_18__PRE                                             0x0
8382 
8383 #define SCU_RAM_ATV_RATE_OFS__A                                             0x831F68
8384 #define SCU_RAM_ATV_RATE_OFS__W                                             12
8385 #define SCU_RAM_ATV_RATE_OFS__M                                             0xFFF
8386 #define SCU_RAM_ATV_RATE_OFS__PRE                                           0x0
8387 
8388 #define SCU_RAM_ATV_LO_INCR__A                                              0x831F69
8389 #define SCU_RAM_ATV_LO_INCR__W                                              12
8390 #define SCU_RAM_ATV_LO_INCR__M                                              0xFFF
8391 #define SCU_RAM_ATV_LO_INCR__PRE                                            0x0
8392 
8393 #define SCU_RAM_ATV_IIR_CRIT__A                                             0x831F6A
8394 #define SCU_RAM_ATV_IIR_CRIT__W                                             12
8395 #define SCU_RAM_ATV_IIR_CRIT__M                                             0xFFF
8396 #define SCU_RAM_ATV_IIR_CRIT__PRE                                           0x0
8397 
8398 #define SCU_RAM_ATV_DEF_RATE_OFS__A                                         0x831F6B
8399 #define SCU_RAM_ATV_DEF_RATE_OFS__W                                         12
8400 #define SCU_RAM_ATV_DEF_RATE_OFS__M                                         0xFFF
8401 #define SCU_RAM_ATV_DEF_RATE_OFS__PRE                                       0x0
8402 
8403 #define SCU_RAM_ATV_DEF_LO_INCR__A                                          0x831F6C
8404 #define SCU_RAM_ATV_DEF_LO_INCR__W                                          12
8405 #define SCU_RAM_ATV_DEF_LO_INCR__M                                          0xFFF
8406 #define SCU_RAM_ATV_DEF_LO_INCR__PRE                                        0x0
8407 
8408 #define SCU_RAM_ATV_ENABLE_IIR_WA__A                                        0x831F6D
8409 #define SCU_RAM_ATV_ENABLE_IIR_WA__W                                        1
8410 #define SCU_RAM_ATV_ENABLE_IIR_WA__M                                        0x1
8411 #define SCU_RAM_ATV_ENABLE_IIR_WA__PRE                                      0x0
8412 
8413 #define SCU_RAM_ATV_MOD_CONTROL__A                                          0x831F6E
8414 #define SCU_RAM_ATV_MOD_CONTROL__W                                          12
8415 #define SCU_RAM_ATV_MOD_CONTROL__M                                          0xFFF
8416 #define SCU_RAM_ATV_MOD_CONTROL__PRE                                        0x0
8417 
8418 #define SCU_RAM_ATV_PAGC_KI_MAX__A                                          0x831F6F
8419 #define SCU_RAM_ATV_PAGC_KI_MAX__W                                          12
8420 #define SCU_RAM_ATV_PAGC_KI_MAX__M                                          0xFFF
8421 #define SCU_RAM_ATV_PAGC_KI_MAX__PRE                                        0x0
8422 
8423 #define SCU_RAM_ATV_BPC_KI_MAX__A                                           0x831F70
8424 #define SCU_RAM_ATV_BPC_KI_MAX__W                                           12
8425 #define SCU_RAM_ATV_BPC_KI_MAX__M                                           0xFFF
8426 #define SCU_RAM_ATV_BPC_KI_MAX__PRE                                         0x0
8427 
8428 #define SCU_RAM_ATV_NAGC_KI_MAX__A                                          0x831F71
8429 #define SCU_RAM_ATV_NAGC_KI_MAX__W                                          12
8430 #define SCU_RAM_ATV_NAGC_KI_MAX__M                                          0xFFF
8431 #define SCU_RAM_ATV_NAGC_KI_MAX__PRE                                        0x0
8432 #define SCU_RAM_ATV_NAGC_KI_MIN__A                                          0x831F72
8433 #define SCU_RAM_ATV_NAGC_KI_MIN__W                                          12
8434 #define SCU_RAM_ATV_NAGC_KI_MIN__M                                          0xFFF
8435 #define SCU_RAM_ATV_NAGC_KI_MIN__PRE                                        0x0
8436 
8437 #define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B                            0
8438 #define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W                            12
8439 #define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M                            0xFFF
8440 #define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE                          0x0
8441 
8442 #define SCU_RAM_ATV_KI_CHANGE_TH__A                                         0x831F73
8443 #define SCU_RAM_ATV_KI_CHANGE_TH__W                                         8
8444 #define SCU_RAM_ATV_KI_CHANGE_TH__M                                         0xFF
8445 #define SCU_RAM_ATV_KI_CHANGE_TH__PRE                                       0x0
8446 
8447 #define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B                          0
8448 #define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W                          8
8449 #define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M                          0xFF
8450 #define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE                        0x0
8451 #define     SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD                   0x14
8452 #define     SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD                   0x28
8453 
8454 #define SCU_RAM_QAM_PARAM_ANNEX__A                                          0x831F74
8455 #define SCU_RAM_QAM_PARAM_ANNEX__W                                          2
8456 #define SCU_RAM_QAM_PARAM_ANNEX__M                                          0x3
8457 #define SCU_RAM_QAM_PARAM_ANNEX__PRE                                        0x0
8458 
8459 #define   SCU_RAM_QAM_PARAM_ANNEX_BIT__B                                    0
8460 #define   SCU_RAM_QAM_PARAM_ANNEX_BIT__W                                    2
8461 #define   SCU_RAM_QAM_PARAM_ANNEX_BIT__M                                    0x3
8462 #define   SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE                                  0x0
8463 #define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A                             0x0
8464 #define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B                             0x1
8465 #define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C                             0x2
8466 #define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D                             0x3
8467 
8468 #define SCU_RAM_QAM_PARAM_CONSTELLATION__A                                  0x831F75
8469 #define SCU_RAM_QAM_PARAM_CONSTELLATION__W                                  3
8470 #define SCU_RAM_QAM_PARAM_CONSTELLATION__M                                  0x7
8471 #define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE                                0x0
8472 
8473 #define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B                            0
8474 #define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W                            3
8475 #define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M                            0x7
8476 #define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE                          0x0
8477 #define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN                     0x0
8478 #define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16                      0x3
8479 #define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32                      0x4
8480 #define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64                      0x5
8481 #define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128                     0x6
8482 #define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256                     0x7
8483 
8484 #define SCU_RAM_QAM_PARAM_INTERLEAVE__A                                     0x831F76
8485 #define SCU_RAM_QAM_PARAM_INTERLEAVE__W                                     8
8486 #define SCU_RAM_QAM_PARAM_INTERLEAVE__M                                     0xFF
8487 #define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE                                   0x0
8488 
8489 #define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B                               0
8490 #define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W                               8
8491 #define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M                               0xFF
8492 #define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE                             0x0
8493 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1                        0x0
8494 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2                     0x1
8495 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2                        0x2
8496 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2                         0x3
8497 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3                        0x4
8498 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4                         0x5
8499 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4                        0x6
8500 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8                         0x7
8501 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5                        0x8
8502 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16                         0x9
8503 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6                        0xA
8504 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7                        0xC
8505 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8                        0xE
8506 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17                        0x10
8507 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4                          0x11
8508 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN                        0xFE
8509 #define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO                           0xFF
8510 
8511 #define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A                                  0x831F77
8512 #define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W                                  16
8513 #define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M                                  0xFFFF
8514 #define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE                                0x0
8515 
8516 #define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B                            0
8517 #define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W                            16
8518 #define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M                            0xFFFF
8519 #define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE                          0x0
8520 
8521 #define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A                                  0x831F78
8522 #define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W                                  16
8523 #define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M                                  0xFFFF
8524 #define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE                                0x0
8525 
8526 #define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B                            0
8527 #define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W                            16
8528 #define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M                            0xFFFF
8529 #define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE                          0x0
8530 
8531 #define SCU_RAM_QAM_EQ_CENTERTAP__A                                         0x831F79
8532 #define SCU_RAM_QAM_EQ_CENTERTAP__W                                         16
8533 #define SCU_RAM_QAM_EQ_CENTERTAP__M                                         0xFFFF
8534 #define SCU_RAM_QAM_EQ_CENTERTAP__PRE                                       0x0
8535 
8536 #define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__B                                   0
8537 #define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__W                                   8
8538 #define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__M                                   0xFF
8539 #define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE                                 0x0
8540 
8541 #define SCU_RAM_QAM_WR_RSV_0__A                                             0x831F7A
8542 #define SCU_RAM_QAM_WR_RSV_0__W                                             16
8543 #define SCU_RAM_QAM_WR_RSV_0__M                                             0xFFFF
8544 #define SCU_RAM_QAM_WR_RSV_0__PRE                                           0x0
8545 
8546 #define   SCU_RAM_QAM_WR_RSV_0_BIT__B                                       0
8547 #define   SCU_RAM_QAM_WR_RSV_0_BIT__W                                       16
8548 #define   SCU_RAM_QAM_WR_RSV_0_BIT__M                                       0xFFFF
8549 #define   SCU_RAM_QAM_WR_RSV_0_BIT__PRE                                     0x0
8550 
8551 #define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A                                  0x831F7B
8552 #define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W                                  16
8553 #define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M                                  0xFFFF
8554 #define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE                                0x0
8555 
8556 #define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B                            0
8557 #define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W                            16
8558 #define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M                            0xFFFF
8559 #define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE                          0x0
8560 
8561 #define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A                                  0x831F7C
8562 #define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W                                  16
8563 #define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M                                  0xFFFF
8564 #define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE                                0x0
8565 
8566 #define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B                            0
8567 #define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W                            16
8568 #define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M                            0xFFFF
8569 #define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE                          0x0
8570 
8571 #define SCU_RAM_QAM_WR_RSV_5__A                                             0x831F7D
8572 #define SCU_RAM_QAM_WR_RSV_5__W                                             16
8573 #define SCU_RAM_QAM_WR_RSV_5__M                                             0xFFFF
8574 #define SCU_RAM_QAM_WR_RSV_5__PRE                                           0x0
8575 
8576 #define   SCU_RAM_QAM_WR_RSV_5_BIT__B                                       0
8577 #define   SCU_RAM_QAM_WR_RSV_5_BIT__W                                       16
8578 #define   SCU_RAM_QAM_WR_RSV_5_BIT__M                                       0xFFFF
8579 #define   SCU_RAM_QAM_WR_RSV_5_BIT__PRE                                     0x0
8580 
8581 #define SCU_RAM_QAM_WR_RSV_6__A                                             0x831F7E
8582 #define SCU_RAM_QAM_WR_RSV_6__W                                             16
8583 #define SCU_RAM_QAM_WR_RSV_6__M                                             0xFFFF
8584 #define SCU_RAM_QAM_WR_RSV_6__PRE                                           0x0
8585 
8586 #define   SCU_RAM_QAM_WR_RSV_6_BIT__B                                       0
8587 #define   SCU_RAM_QAM_WR_RSV_6_BIT__W                                       16
8588 #define   SCU_RAM_QAM_WR_RSV_6_BIT__M                                       0xFFFF
8589 #define   SCU_RAM_QAM_WR_RSV_6_BIT__PRE                                     0x0
8590 
8591 #define SCU_RAM_QAM_WR_RSV_7__A                                             0x831F7F
8592 #define SCU_RAM_QAM_WR_RSV_7__W                                             16
8593 #define SCU_RAM_QAM_WR_RSV_7__M                                             0xFFFF
8594 #define SCU_RAM_QAM_WR_RSV_7__PRE                                           0x0
8595 
8596 #define   SCU_RAM_QAM_WR_RSV_7_BIT__B                                       0
8597 #define   SCU_RAM_QAM_WR_RSV_7_BIT__W                                       16
8598 #define   SCU_RAM_QAM_WR_RSV_7_BIT__M                                       0xFFFF
8599 #define   SCU_RAM_QAM_WR_RSV_7_BIT__PRE                                     0x0
8600 
8601 #define SCU_RAM_QAM_WR_RSV_8__A                                             0x831F80
8602 #define SCU_RAM_QAM_WR_RSV_8__W                                             16
8603 #define SCU_RAM_QAM_WR_RSV_8__M                                             0xFFFF
8604 #define SCU_RAM_QAM_WR_RSV_8__PRE                                           0x0
8605 
8606 #define   SCU_RAM_QAM_WR_RSV_8_BIT__B                                       0
8607 #define   SCU_RAM_QAM_WR_RSV_8_BIT__W                                       16
8608 #define   SCU_RAM_QAM_WR_RSV_8_BIT__M                                       0xFFFF
8609 #define   SCU_RAM_QAM_WR_RSV_8_BIT__PRE                                     0x0
8610 
8611 #define SCU_RAM_QAM_WR_RSV_9__A                                             0x831F81
8612 #define SCU_RAM_QAM_WR_RSV_9__W                                             16
8613 #define SCU_RAM_QAM_WR_RSV_9__M                                             0xFFFF
8614 #define SCU_RAM_QAM_WR_RSV_9__PRE                                           0x0
8615 
8616 #define   SCU_RAM_QAM_WR_RSV_9_BIT__B                                       0
8617 #define   SCU_RAM_QAM_WR_RSV_9_BIT__W                                       16
8618 #define   SCU_RAM_QAM_WR_RSV_9_BIT__M                                       0xFFFF
8619 #define   SCU_RAM_QAM_WR_RSV_9_BIT__PRE                                     0x0
8620 
8621 #define SCU_RAM_QAM_WR_RSV_10__A                                            0x831F82
8622 #define SCU_RAM_QAM_WR_RSV_10__W                                            16
8623 #define SCU_RAM_QAM_WR_RSV_10__M                                            0xFFFF
8624 #define SCU_RAM_QAM_WR_RSV_10__PRE                                          0x0
8625 
8626 #define   SCU_RAM_QAM_WR_RSV_10_BIT__B                                      0
8627 #define   SCU_RAM_QAM_WR_RSV_10_BIT__W                                      16
8628 #define   SCU_RAM_QAM_WR_RSV_10_BIT__M                                      0xFFFF
8629 #define   SCU_RAM_QAM_WR_RSV_10_BIT__PRE                                    0x0
8630 
8631 #define SCU_RAM_QAM_FSM_FMHUM_TO__A                                         0x831F83
8632 #define SCU_RAM_QAM_FSM_FMHUM_TO__W                                         16
8633 #define SCU_RAM_QAM_FSM_FMHUM_TO__M                                         0xFFFF
8634 #define SCU_RAM_QAM_FSM_FMHUM_TO__PRE                                       0x0
8635 
8636 #define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B                                   0
8637 #define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W                                   16
8638 #define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M                                   0xFFFF
8639 #define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE                                 0x0
8640 #define     SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO                        0x0
8641 
8642 #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A                                   0x831F84
8643 #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W                                   16
8644 #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M                                   0xFFFF
8645 #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE                                 0x0
8646 
8647 #define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B                             0
8648 #define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W                             16
8649 #define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M                             0xFFFF
8650 #define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE                           0x0
8651 
8652 #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A                                  0x831F85
8653 #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W                                  16
8654 #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M                                  0xFFFF
8655 #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE                                0x0
8656 
8657 #define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B                            0
8658 #define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W                            16
8659 #define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M                            0xFFFF
8660 #define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE                          0x0
8661 
8662 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A                                    0x831F86
8663 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W                                    16
8664 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M                                    0xFFFF
8665 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE                                  0x0
8666 
8667 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B                              0
8668 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W                              16
8669 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M                              0xFFFF
8670 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE                            0x0
8671 
8672 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A                                    0x831F87
8673 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W                                    16
8674 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M                                    0xFFFF
8675 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE                                  0x0
8676 
8677 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B                              0
8678 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W                              16
8679 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M                              0xFFFF
8680 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE                            0x0
8681 
8682 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A                                    0x831F88
8683 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W                                    16
8684 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M                                    0xFFFF
8685 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE                                  0x0
8686 
8687 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B                              0
8688 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W                              16
8689 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M                              0xFFFF
8690 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE                            0x0
8691 
8692 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A                                    0x831F89
8693 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W                                    16
8694 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M                                    0xFFFF
8695 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE                                  0x0
8696 
8697 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B                              0
8698 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W                              16
8699 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M                              0xFFFF
8700 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE                            0x0
8701 
8702 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A                                    0x831F8A
8703 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W                                    16
8704 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M                                    0xFFFF
8705 #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE                                  0x0
8706 
8707 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B                              0
8708 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W                              16
8709 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M                              0xFFFF
8710 #define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE                            0x0
8711 
8712 #define SCU_RAM_QAM_FSM_STATE_TGT__A                                        0x831F8B
8713 #define SCU_RAM_QAM_FSM_STATE_TGT__W                                        4
8714 #define SCU_RAM_QAM_FSM_STATE_TGT__M                                        0xF
8715 #define SCU_RAM_QAM_FSM_STATE_TGT__PRE                                      0x0
8716 
8717 #define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__B                                  0
8718 #define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__W                                  4
8719 #define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__M                                  0xF
8720 #define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE                                0x0
8721 #define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP                       0x0
8722 #define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE                      0x1
8723 #define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ                      0x2
8724 #define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT                   0x3
8725 #define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE                     0x4
8726 #define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE                  0x5
8727 #define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING                          0x6
8728 #define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST                    0x7
8729 
8730 #define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A                                    0x831F8C
8731 #define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W                                    9
8732 #define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M                                    0x1FF
8733 #define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE                                  0x0
8734 
8735 #define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B                          0
8736 #define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W                          1
8737 #define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M                          0x1
8738 #define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE                        0x0
8739 
8740 #define SCU_RAM_QAM_FSM_ATH__A                                              0x831F8D
8741 #define SCU_RAM_QAM_FSM_ATH__W                                              16
8742 #define SCU_RAM_QAM_FSM_ATH__M                                              0xFFFF
8743 #define SCU_RAM_QAM_FSM_ATH__PRE                                            0x0
8744 
8745 #define   SCU_RAM_QAM_FSM_ATH_BIT__B                                        0
8746 #define   SCU_RAM_QAM_FSM_ATH_BIT__W                                        16
8747 #define   SCU_RAM_QAM_FSM_ATH_BIT__M                                        0xFFFF
8748 #define   SCU_RAM_QAM_FSM_ATH_BIT__PRE                                      0x0
8749 
8750 #define SCU_RAM_QAM_FSM_RTH__A                                              0x831F8E
8751 #define SCU_RAM_QAM_FSM_RTH__W                                              16
8752 #define SCU_RAM_QAM_FSM_RTH__M                                              0xFFFF
8753 #define SCU_RAM_QAM_FSM_RTH__PRE                                            0x0
8754 
8755 #define   SCU_RAM_QAM_FSM_RTH_BIT__B                                        0
8756 #define   SCU_RAM_QAM_FSM_RTH_BIT__W                                        16
8757 #define   SCU_RAM_QAM_FSM_RTH_BIT__M                                        0xFFFF
8758 #define   SCU_RAM_QAM_FSM_RTH_BIT__PRE                                      0x0
8759 #define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_16                                  0x8C
8760 #define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_32                                  0x50
8761 #define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_64                                  0x4E
8762 #define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_128                                 0x32
8763 #define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_256                                 0x2D
8764 
8765 #define SCU_RAM_QAM_FSM_FTH__A                                              0x831F8F
8766 #define SCU_RAM_QAM_FSM_FTH__W                                              16
8767 #define SCU_RAM_QAM_FSM_FTH__M                                              0xFFFF
8768 #define SCU_RAM_QAM_FSM_FTH__PRE                                            0x0
8769 
8770 #define   SCU_RAM_QAM_FSM_FTH_BIT__B                                        0
8771 #define   SCU_RAM_QAM_FSM_FTH_BIT__W                                        16
8772 #define   SCU_RAM_QAM_FSM_FTH_BIT__M                                        0xFFFF
8773 #define   SCU_RAM_QAM_FSM_FTH_BIT__PRE                                      0x0
8774 #define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_16                                  0x32
8775 #define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_32                                  0x1E
8776 #define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_64                                  0x1E
8777 #define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_128                                 0x14
8778 #define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_256                                 0x14
8779 
8780 #define SCU_RAM_QAM_FSM_PTH__A                                              0x831F90
8781 #define SCU_RAM_QAM_FSM_PTH__W                                              16
8782 #define SCU_RAM_QAM_FSM_PTH__M                                              0xFFFF
8783 #define SCU_RAM_QAM_FSM_PTH__PRE                                            0x0
8784 
8785 #define   SCU_RAM_QAM_FSM_PTH_BIT__B                                        0
8786 #define   SCU_RAM_QAM_FSM_PTH_BIT__W                                        16
8787 #define   SCU_RAM_QAM_FSM_PTH_BIT__M                                        0xFFFF
8788 #define   SCU_RAM_QAM_FSM_PTH_BIT__PRE                                      0x0
8789 #define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_16                                  0xC8
8790 #define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_32                                  0x96
8791 #define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_64                                  0x8C
8792 #define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_128                                 0x64
8793 #define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_256                                 0x64
8794 
8795 #define SCU_RAM_QAM_FSM_MTH__A                                              0x831F91
8796 #define SCU_RAM_QAM_FSM_MTH__W                                              16
8797 #define SCU_RAM_QAM_FSM_MTH__M                                              0xFFFF
8798 #define SCU_RAM_QAM_FSM_MTH__PRE                                            0x0
8799 
8800 #define   SCU_RAM_QAM_FSM_MTH_BIT__B                                        0
8801 #define   SCU_RAM_QAM_FSM_MTH_BIT__W                                        16
8802 #define   SCU_RAM_QAM_FSM_MTH_BIT__M                                        0xFFFF
8803 #define   SCU_RAM_QAM_FSM_MTH_BIT__PRE                                      0x0
8804 #define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_16                                  0x5A
8805 #define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_32                                  0x50
8806 #define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_64                                  0x46
8807 #define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_128                                 0x3C
8808 #define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_256                                 0x50
8809 
8810 #define SCU_RAM_QAM_FSM_CTH__A                                              0x831F92
8811 #define SCU_RAM_QAM_FSM_CTH__W                                              16
8812 #define SCU_RAM_QAM_FSM_CTH__M                                              0xFFFF
8813 #define SCU_RAM_QAM_FSM_CTH__PRE                                            0x0
8814 
8815 #define   SCU_RAM_QAM_FSM_CTH_BIT__B                                        0
8816 #define   SCU_RAM_QAM_FSM_CTH_BIT__W                                        16
8817 #define   SCU_RAM_QAM_FSM_CTH_BIT__M                                        0xFFFF
8818 #define   SCU_RAM_QAM_FSM_CTH_BIT__PRE                                      0x0
8819 #define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_16                                  0xA0
8820 #define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_32                                  0x8C
8821 #define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_64                                  0x8C
8822 #define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_128                                 0x8C
8823 #define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_256                                 0x8C
8824 
8825 #define SCU_RAM_QAM_FSM_QTH__A                                              0x831F93
8826 #define SCU_RAM_QAM_FSM_QTH__W                                              16
8827 #define SCU_RAM_QAM_FSM_QTH__M                                              0xFFFF
8828 #define SCU_RAM_QAM_FSM_QTH__PRE                                            0x0
8829 
8830 #define   SCU_RAM_QAM_FSM_QTH_BIT__B                                        0
8831 #define   SCU_RAM_QAM_FSM_QTH_BIT__W                                        16
8832 #define   SCU_RAM_QAM_FSM_QTH_BIT__M                                        0xFFFF
8833 #define   SCU_RAM_QAM_FSM_QTH_BIT__PRE                                      0x0
8834 #define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_16                                  0xE6
8835 #define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_32                                  0xAA
8836 #define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_64                                  0xC3
8837 #define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_128                                 0x8C
8838 #define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_256                                 0x96
8839 
8840 #define SCU_RAM_QAM_FSM_RATE_LIM__A                                         0x831F94
8841 #define SCU_RAM_QAM_FSM_RATE_LIM__W                                         16
8842 #define SCU_RAM_QAM_FSM_RATE_LIM__M                                         0xFFFF
8843 #define SCU_RAM_QAM_FSM_RATE_LIM__PRE                                       0x0
8844 
8845 #define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__B                                   0
8846 #define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__W                                   16
8847 #define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__M                                   0xFFFF
8848 #define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE                                 0x0
8849 #define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16                             0x46
8850 #define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32                             0x46
8851 #define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64                             0x46
8852 #define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128                            0x46
8853 #define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256                            0x46
8854 
8855 #define SCU_RAM_QAM_FSM_FREQ_LIM__A                                         0x831F95
8856 #define SCU_RAM_QAM_FSM_FREQ_LIM__W                                         16
8857 #define SCU_RAM_QAM_FSM_FREQ_LIM__M                                         0xFFFF
8858 #define SCU_RAM_QAM_FSM_FREQ_LIM__PRE                                       0x0
8859 
8860 #define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B                                   0
8861 #define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W                                   16
8862 #define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M                                   0xFFFF
8863 #define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE                                 0x0
8864 #define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16                             0x1E
8865 #define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32                             0x14
8866 #define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64                             0x28
8867 #define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128                            0x8
8868 #define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256                            0x28
8869 
8870 #define SCU_RAM_QAM_FSM_COUNT_LIM__A                                        0x831F96
8871 #define SCU_RAM_QAM_FSM_COUNT_LIM__W                                        16
8872 #define SCU_RAM_QAM_FSM_COUNT_LIM__M                                        0xFFFF
8873 #define SCU_RAM_QAM_FSM_COUNT_LIM__PRE                                      0x0
8874 
8875 #define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B                                  0
8876 #define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W                                  16
8877 #define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M                                  0xFFFF
8878 #define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE                                0x0
8879 #define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16                            0x4
8880 #define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32                            0x6
8881 #define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64                            0x6
8882 #define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128                           0x7
8883 #define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256                           0x6
8884 
8885 #define SCU_RAM_QAM_LC_CA_COARSE__A                                         0x831F97
8886 #define SCU_RAM_QAM_LC_CA_COARSE__W                                         16
8887 #define SCU_RAM_QAM_LC_CA_COARSE__M                                         0xFFFF
8888 #define SCU_RAM_QAM_LC_CA_COARSE__PRE                                       0x0
8889 
8890 #define   SCU_RAM_QAM_LC_CA_COARSE_BIT__B                                   0
8891 #define   SCU_RAM_QAM_LC_CA_COARSE_BIT__W                                   8
8892 #define   SCU_RAM_QAM_LC_CA_COARSE_BIT__M                                   0xFF
8893 #define   SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE                                 0x0
8894 
8895 #define SCU_RAM_QAM_LC_CA_MEDIUM__A                                         0x831F98
8896 #define SCU_RAM_QAM_LC_CA_MEDIUM__W                                         16
8897 #define SCU_RAM_QAM_LC_CA_MEDIUM__M                                         0xFFFF
8898 #define SCU_RAM_QAM_LC_CA_MEDIUM__PRE                                       0x0
8899 
8900 #define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B                                   0
8901 #define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W                                   8
8902 #define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M                                   0xFF
8903 #define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE                                 0x0
8904 
8905 #define SCU_RAM_QAM_LC_CA_FINE__A                                           0x831F99
8906 #define SCU_RAM_QAM_LC_CA_FINE__W                                           16
8907 #define SCU_RAM_QAM_LC_CA_FINE__M                                           0xFFFF
8908 #define SCU_RAM_QAM_LC_CA_FINE__PRE                                         0x0
8909 
8910 #define   SCU_RAM_QAM_LC_CA_FINE_BIT__B                                     0
8911 #define   SCU_RAM_QAM_LC_CA_FINE_BIT__W                                     8
8912 #define   SCU_RAM_QAM_LC_CA_FINE_BIT__M                                     0xFF
8913 #define   SCU_RAM_QAM_LC_CA_FINE_BIT__PRE                                   0x0
8914 
8915 #define SCU_RAM_QAM_LC_CP_COARSE__A                                         0x831F9A
8916 #define SCU_RAM_QAM_LC_CP_COARSE__W                                         16
8917 #define SCU_RAM_QAM_LC_CP_COARSE__M                                         0xFFFF
8918 #define SCU_RAM_QAM_LC_CP_COARSE__PRE                                       0x0
8919 
8920 #define   SCU_RAM_QAM_LC_CP_COARSE_BIT__B                                   0
8921 #define   SCU_RAM_QAM_LC_CP_COARSE_BIT__W                                   8
8922 #define   SCU_RAM_QAM_LC_CP_COARSE_BIT__M                                   0xFF
8923 #define   SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE                                 0x0
8924 
8925 #define SCU_RAM_QAM_LC_CP_MEDIUM__A                                         0x831F9B
8926 #define SCU_RAM_QAM_LC_CP_MEDIUM__W                                         16
8927 #define SCU_RAM_QAM_LC_CP_MEDIUM__M                                         0xFFFF
8928 #define SCU_RAM_QAM_LC_CP_MEDIUM__PRE                                       0x0
8929 
8930 #define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B                                   0
8931 #define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W                                   8
8932 #define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M                                   0xFF
8933 #define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE                                 0x0
8934 
8935 #define SCU_RAM_QAM_LC_CP_FINE__A                                           0x831F9C
8936 #define SCU_RAM_QAM_LC_CP_FINE__W                                           16
8937 #define SCU_RAM_QAM_LC_CP_FINE__M                                           0xFFFF
8938 #define SCU_RAM_QAM_LC_CP_FINE__PRE                                         0x0
8939 
8940 #define   SCU_RAM_QAM_LC_CP_FINE_BIT__B                                     0
8941 #define   SCU_RAM_QAM_LC_CP_FINE_BIT__W                                     8
8942 #define   SCU_RAM_QAM_LC_CP_FINE_BIT__M                                     0xFF
8943 #define   SCU_RAM_QAM_LC_CP_FINE_BIT__PRE                                   0x0
8944 
8945 #define SCU_RAM_QAM_LC_CI_COARSE__A                                         0x831F9D
8946 #define SCU_RAM_QAM_LC_CI_COARSE__W                                         16
8947 #define SCU_RAM_QAM_LC_CI_COARSE__M                                         0xFFFF
8948 #define SCU_RAM_QAM_LC_CI_COARSE__PRE                                       0x0
8949 
8950 #define   SCU_RAM_QAM_LC_CI_COARSE_BIT__B                                   0
8951 #define   SCU_RAM_QAM_LC_CI_COARSE_BIT__W                                   8
8952 #define   SCU_RAM_QAM_LC_CI_COARSE_BIT__M                                   0xFF
8953 #define   SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE                                 0x0
8954 
8955 #define SCU_RAM_QAM_LC_CI_MEDIUM__A                                         0x831F9E
8956 #define SCU_RAM_QAM_LC_CI_MEDIUM__W                                         16
8957 #define SCU_RAM_QAM_LC_CI_MEDIUM__M                                         0xFFFF
8958 #define SCU_RAM_QAM_LC_CI_MEDIUM__PRE                                       0x0
8959 
8960 #define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B                                   0
8961 #define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W                                   8
8962 #define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M                                   0xFF
8963 #define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE                                 0x0
8964 
8965 #define SCU_RAM_QAM_LC_CI_FINE__A                                           0x831F9F
8966 #define SCU_RAM_QAM_LC_CI_FINE__W                                           16
8967 #define SCU_RAM_QAM_LC_CI_FINE__M                                           0xFFFF
8968 #define SCU_RAM_QAM_LC_CI_FINE__PRE                                         0x0
8969 
8970 #define   SCU_RAM_QAM_LC_CI_FINE_BIT__B                                     0
8971 #define   SCU_RAM_QAM_LC_CI_FINE_BIT__W                                     8
8972 #define   SCU_RAM_QAM_LC_CI_FINE_BIT__M                                     0xFF
8973 #define   SCU_RAM_QAM_LC_CI_FINE_BIT__PRE                                   0x0
8974 
8975 #define SCU_RAM_QAM_LC_EP_COARSE__A                                         0x831FA0
8976 #define SCU_RAM_QAM_LC_EP_COARSE__W                                         16
8977 #define SCU_RAM_QAM_LC_EP_COARSE__M                                         0xFFFF
8978 #define SCU_RAM_QAM_LC_EP_COARSE__PRE                                       0x0
8979 
8980 #define   SCU_RAM_QAM_LC_EP_COARSE_BIT__B                                   0
8981 #define   SCU_RAM_QAM_LC_EP_COARSE_BIT__W                                   8
8982 #define   SCU_RAM_QAM_LC_EP_COARSE_BIT__M                                   0xFF
8983 #define   SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE                                 0x0
8984 
8985 #define SCU_RAM_QAM_LC_EP_MEDIUM__A                                         0x831FA1
8986 #define SCU_RAM_QAM_LC_EP_MEDIUM__W                                         16
8987 #define SCU_RAM_QAM_LC_EP_MEDIUM__M                                         0xFFFF
8988 #define SCU_RAM_QAM_LC_EP_MEDIUM__PRE                                       0x0
8989 
8990 #define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B                                   0
8991 #define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W                                   8
8992 #define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M                                   0xFF
8993 #define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE                                 0x0
8994 
8995 #define SCU_RAM_QAM_LC_EP_FINE__A                                           0x831FA2
8996 #define SCU_RAM_QAM_LC_EP_FINE__W                                           16
8997 #define SCU_RAM_QAM_LC_EP_FINE__M                                           0xFFFF
8998 #define SCU_RAM_QAM_LC_EP_FINE__PRE                                         0x0
8999 
9000 #define   SCU_RAM_QAM_LC_EP_FINE_BIT__B                                     0
9001 #define   SCU_RAM_QAM_LC_EP_FINE_BIT__W                                     8
9002 #define   SCU_RAM_QAM_LC_EP_FINE_BIT__M                                     0xFF
9003 #define   SCU_RAM_QAM_LC_EP_FINE_BIT__PRE                                   0x0
9004 
9005 #define SCU_RAM_QAM_LC_EI_COARSE__A                                         0x831FA3
9006 #define SCU_RAM_QAM_LC_EI_COARSE__W                                         16
9007 #define SCU_RAM_QAM_LC_EI_COARSE__M                                         0xFFFF
9008 #define SCU_RAM_QAM_LC_EI_COARSE__PRE                                       0x0
9009 
9010 #define   SCU_RAM_QAM_LC_EI_COARSE_BIT__B                                   0
9011 #define   SCU_RAM_QAM_LC_EI_COARSE_BIT__W                                   8
9012 #define   SCU_RAM_QAM_LC_EI_COARSE_BIT__M                                   0xFF
9013 #define   SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE                                 0x0
9014 
9015 #define SCU_RAM_QAM_LC_EI_MEDIUM__A                                         0x831FA4
9016 #define SCU_RAM_QAM_LC_EI_MEDIUM__W                                         16
9017 #define SCU_RAM_QAM_LC_EI_MEDIUM__M                                         0xFFFF
9018 #define SCU_RAM_QAM_LC_EI_MEDIUM__PRE                                       0x0
9019 
9020 #define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B                                   0
9021 #define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W                                   8
9022 #define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M                                   0xFF
9023 #define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE                                 0x0
9024 
9025 #define SCU_RAM_QAM_LC_EI_FINE__A                                           0x831FA5
9026 #define SCU_RAM_QAM_LC_EI_FINE__W                                           16
9027 #define SCU_RAM_QAM_LC_EI_FINE__M                                           0xFFFF
9028 #define SCU_RAM_QAM_LC_EI_FINE__PRE                                         0x0
9029 
9030 #define   SCU_RAM_QAM_LC_EI_FINE_BIT__B                                     0
9031 #define   SCU_RAM_QAM_LC_EI_FINE_BIT__W                                     8
9032 #define   SCU_RAM_QAM_LC_EI_FINE_BIT__M                                     0xFF
9033 #define   SCU_RAM_QAM_LC_EI_FINE_BIT__PRE                                   0x0
9034 
9035 #define SCU_RAM_QAM_LC_CF_COARSE__A                                         0x831FA6
9036 #define SCU_RAM_QAM_LC_CF_COARSE__W                                         16
9037 #define SCU_RAM_QAM_LC_CF_COARSE__M                                         0xFFFF
9038 #define SCU_RAM_QAM_LC_CF_COARSE__PRE                                       0x0
9039 
9040 #define   SCU_RAM_QAM_LC_CF_COARSE_BIT__B                                   0
9041 #define   SCU_RAM_QAM_LC_CF_COARSE_BIT__W                                   8
9042 #define   SCU_RAM_QAM_LC_CF_COARSE_BIT__M                                   0xFF
9043 #define   SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE                                 0x0
9044 
9045 #define SCU_RAM_QAM_LC_CF_MEDIUM__A                                         0x831FA7
9046 #define SCU_RAM_QAM_LC_CF_MEDIUM__W                                         16
9047 #define SCU_RAM_QAM_LC_CF_MEDIUM__M                                         0xFFFF
9048 #define SCU_RAM_QAM_LC_CF_MEDIUM__PRE                                       0x0
9049 
9050 #define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B                                   0
9051 #define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W                                   8
9052 #define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M                                   0xFF
9053 #define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE                                 0x0
9054 
9055 #define SCU_RAM_QAM_LC_CF_FINE__A                                           0x831FA8
9056 #define SCU_RAM_QAM_LC_CF_FINE__W                                           16
9057 #define SCU_RAM_QAM_LC_CF_FINE__M                                           0xFFFF
9058 #define SCU_RAM_QAM_LC_CF_FINE__PRE                                         0x0
9059 
9060 #define   SCU_RAM_QAM_LC_CF_FINE_BIT__B                                     0
9061 #define   SCU_RAM_QAM_LC_CF_FINE_BIT__W                                     8
9062 #define   SCU_RAM_QAM_LC_CF_FINE_BIT__M                                     0xFF
9063 #define   SCU_RAM_QAM_LC_CF_FINE_BIT__PRE                                   0x0
9064 
9065 #define SCU_RAM_QAM_LC_CF1_COARSE__A                                        0x831FA9
9066 #define SCU_RAM_QAM_LC_CF1_COARSE__W                                        16
9067 #define SCU_RAM_QAM_LC_CF1_COARSE__M                                        0xFFFF
9068 #define SCU_RAM_QAM_LC_CF1_COARSE__PRE                                      0x0
9069 
9070 #define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__B                                  0
9071 #define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__W                                  8
9072 #define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__M                                  0xFF
9073 #define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE                                0x0
9074 
9075 #define SCU_RAM_QAM_LC_CF1_MEDIUM__A                                        0x831FAA
9076 #define SCU_RAM_QAM_LC_CF1_MEDIUM__W                                        16
9077 #define SCU_RAM_QAM_LC_CF1_MEDIUM__M                                        0xFFFF
9078 #define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE                                      0x0
9079 
9080 #define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B                                  0
9081 #define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W                                  8
9082 #define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M                                  0xFF
9083 #define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE                                0x0
9084 
9085 #define SCU_RAM_QAM_LC_CF1_FINE__A                                          0x831FAB
9086 #define SCU_RAM_QAM_LC_CF1_FINE__W                                          16
9087 #define SCU_RAM_QAM_LC_CF1_FINE__M                                          0xFFFF
9088 #define SCU_RAM_QAM_LC_CF1_FINE__PRE                                        0x0
9089 
9090 #define   SCU_RAM_QAM_LC_CF1_FINE_BIT__B                                    0
9091 #define   SCU_RAM_QAM_LC_CF1_FINE_BIT__W                                    8
9092 #define   SCU_RAM_QAM_LC_CF1_FINE_BIT__M                                    0xFF
9093 #define   SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE                                  0x0
9094 
9095 #define SCU_RAM_QAM_SL_SIG_POWER__A                                         0x831FAC
9096 #define SCU_RAM_QAM_SL_SIG_POWER__W                                         16
9097 #define SCU_RAM_QAM_SL_SIG_POWER__M                                         0xFFFF
9098 #define SCU_RAM_QAM_SL_SIG_POWER__PRE                                       0x0
9099 
9100 #define   SCU_RAM_QAM_SL_SIG_POWER_BIT__B                                   0
9101 #define   SCU_RAM_QAM_SL_SIG_POWER_BIT__W                                   16
9102 #define   SCU_RAM_QAM_SL_SIG_POWER_BIT__M                                   0xFFFF
9103 #define   SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE                                 0x0
9104 
9105 #define SCU_RAM_QAM_EQ_CMA_RAD0__A                                          0x831FAD
9106 #define SCU_RAM_QAM_EQ_CMA_RAD0__W                                          14
9107 #define SCU_RAM_QAM_EQ_CMA_RAD0__M                                          0x3FFF
9108 #define SCU_RAM_QAM_EQ_CMA_RAD0__PRE                                        0x0
9109 
9110 #define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B                                    0
9111 #define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W                                    14
9112 #define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M                                    0x3FFF
9113 #define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE                                  0x0
9114 #define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16                              0x34CD
9115 #define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32                              0x1A33
9116 #define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64                              0x3418
9117 #define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128                             0x1814
9118 #define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256                             0x2CEE
9119 
9120 #define SCU_RAM_QAM_EQ_CMA_RAD1__A                                          0x831FAE
9121 #define SCU_RAM_QAM_EQ_CMA_RAD1__W                                          14
9122 #define SCU_RAM_QAM_EQ_CMA_RAD1__M                                          0x3FFF
9123 #define SCU_RAM_QAM_EQ_CMA_RAD1__PRE                                        0x0
9124 
9125 #define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B                                    0
9126 #define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W                                    14
9127 #define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M                                    0x3FFF
9128 #define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE                                  0x0
9129 #define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16                              0x34CD
9130 #define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32                              0x1A33
9131 #define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64                              0x314A
9132 #define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128                             0x19C6
9133 #define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256                             0x2F34
9134 
9135 #define SCU_RAM_QAM_EQ_CMA_RAD2__A                                          0x831FAF
9136 #define SCU_RAM_QAM_EQ_CMA_RAD2__W                                          14
9137 #define SCU_RAM_QAM_EQ_CMA_RAD2__M                                          0x3FFF
9138 #define SCU_RAM_QAM_EQ_CMA_RAD2__PRE                                        0x0
9139 
9140 #define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B                                    0
9141 #define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W                                    14
9142 #define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M                                    0x3FFF
9143 #define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE                                  0x0
9144 #define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16                              0x34CD
9145 #define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32                              0x1A33
9146 #define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64                              0x2ED4
9147 #define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128                             0x18FA
9148 #define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256                             0x30FF
9149 
9150 #define SCU_RAM_QAM_EQ_CMA_RAD3__A                                          0x831FB0
9151 #define SCU_RAM_QAM_EQ_CMA_RAD3__W                                          14
9152 #define SCU_RAM_QAM_EQ_CMA_RAD3__M                                          0x3FFF
9153 #define SCU_RAM_QAM_EQ_CMA_RAD3__PRE                                        0x0
9154 
9155 #define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B                                    0
9156 #define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W                                    14
9157 #define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M                                    0x3FFF
9158 #define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE                                  0x0
9159 #define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16                              0x34CD
9160 #define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32                              0x1A33
9161 #define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64                              0x35F1
9162 #define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128                             0x1909
9163 #define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256                             0x3283
9164 
9165 #define SCU_RAM_QAM_EQ_CMA_RAD4__A                                          0x831FB1
9166 #define SCU_RAM_QAM_EQ_CMA_RAD4__W                                          14
9167 #define SCU_RAM_QAM_EQ_CMA_RAD4__M                                          0x3FFF
9168 #define SCU_RAM_QAM_EQ_CMA_RAD4__PRE                                        0x0
9169 
9170 #define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B                                    0
9171 #define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W                                    14
9172 #define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M                                    0x3FFF
9173 #define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE                                  0x0
9174 #define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16                              0x34CD
9175 #define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32                              0x1A33
9176 #define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64                              0x35F1
9177 #define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128                             0x1A00
9178 #define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256                             0x353D
9179 
9180 #define SCU_RAM_QAM_EQ_CMA_RAD5__A                                          0x831FB2
9181 #define SCU_RAM_QAM_EQ_CMA_RAD5__W                                          14
9182 #define SCU_RAM_QAM_EQ_CMA_RAD5__M                                          0x3FFF
9183 #define SCU_RAM_QAM_EQ_CMA_RAD5__PRE                                        0x0
9184 
9185 #define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B                                    0
9186 #define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W                                    14
9187 #define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M                                    0x3FFF
9188 #define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE                                  0x0
9189 #define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16                              0x34CD
9190 #define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32                              0x1A33
9191 #define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64                              0x3CF9
9192 #define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128                             0x1C46
9193 #define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256                             0x3C19
9194 
9195 #define SCU_RAM_QAM_CTL_ENA__A                                              0x831FB3
9196 #define SCU_RAM_QAM_CTL_ENA__W                                              16
9197 #define SCU_RAM_QAM_CTL_ENA__M                                              0xFFFF
9198 #define SCU_RAM_QAM_CTL_ENA__PRE                                            0x0
9199 
9200 #define   SCU_RAM_QAM_CTL_ENA_AMP__B                                        0
9201 #define   SCU_RAM_QAM_CTL_ENA_AMP__W                                        1
9202 #define   SCU_RAM_QAM_CTL_ENA_AMP__M                                        0x1
9203 #define   SCU_RAM_QAM_CTL_ENA_AMP__PRE                                      0x0
9204 
9205 #define   SCU_RAM_QAM_CTL_ENA_ACQ__B                                        1
9206 #define   SCU_RAM_QAM_CTL_ENA_ACQ__W                                        1
9207 #define   SCU_RAM_QAM_CTL_ENA_ACQ__M                                        0x2
9208 #define   SCU_RAM_QAM_CTL_ENA_ACQ__PRE                                      0x0
9209 
9210 #define   SCU_RAM_QAM_CTL_ENA_EQU__B                                        2
9211 #define   SCU_RAM_QAM_CTL_ENA_EQU__W                                        1
9212 #define   SCU_RAM_QAM_CTL_ENA_EQU__M                                        0x4
9213 #define   SCU_RAM_QAM_CTL_ENA_EQU__PRE                                      0x0
9214 
9215 #define   SCU_RAM_QAM_CTL_ENA_SLC__B                                        3
9216 #define   SCU_RAM_QAM_CTL_ENA_SLC__W                                        1
9217 #define   SCU_RAM_QAM_CTL_ENA_SLC__M                                        0x8
9218 #define   SCU_RAM_QAM_CTL_ENA_SLC__PRE                                      0x0
9219 
9220 #define   SCU_RAM_QAM_CTL_ENA_LC__B                                         4
9221 #define   SCU_RAM_QAM_CTL_ENA_LC__W                                         1
9222 #define   SCU_RAM_QAM_CTL_ENA_LC__M                                         0x10
9223 #define   SCU_RAM_QAM_CTL_ENA_LC__PRE                                       0x0
9224 
9225 #define   SCU_RAM_QAM_CTL_ENA_AGC__B                                        5
9226 #define   SCU_RAM_QAM_CTL_ENA_AGC__W                                        1
9227 #define   SCU_RAM_QAM_CTL_ENA_AGC__M                                        0x20
9228 #define   SCU_RAM_QAM_CTL_ENA_AGC__PRE                                      0x0
9229 
9230 #define   SCU_RAM_QAM_CTL_ENA_FEC__B                                        6
9231 #define   SCU_RAM_QAM_CTL_ENA_FEC__W                                        1
9232 #define   SCU_RAM_QAM_CTL_ENA_FEC__M                                        0x40
9233 #define   SCU_RAM_QAM_CTL_ENA_FEC__PRE                                      0x0
9234 
9235 #define   SCU_RAM_QAM_CTL_ENA_AXIS__B                                       7
9236 #define   SCU_RAM_QAM_CTL_ENA_AXIS__W                                       1
9237 #define   SCU_RAM_QAM_CTL_ENA_AXIS__M                                       0x80
9238 #define   SCU_RAM_QAM_CTL_ENA_AXIS__PRE                                     0x0
9239 
9240 #define   SCU_RAM_QAM_CTL_ENA_FMHUM__B                                      8
9241 #define   SCU_RAM_QAM_CTL_ENA_FMHUM__W                                      1
9242 #define   SCU_RAM_QAM_CTL_ENA_FMHUM__M                                      0x100
9243 #define   SCU_RAM_QAM_CTL_ENA_FMHUM__PRE                                    0x0
9244 
9245 #define   SCU_RAM_QAM_CTL_ENA_EQTIME__B                                     9
9246 #define   SCU_RAM_QAM_CTL_ENA_EQTIME__W                                     1
9247 #define   SCU_RAM_QAM_CTL_ENA_EQTIME__M                                     0x200
9248 #define   SCU_RAM_QAM_CTL_ENA_EQTIME__PRE                                   0x0
9249 
9250 #define   SCU_RAM_QAM_CTL_ENA_EXTLCK__B                                     10
9251 #define   SCU_RAM_QAM_CTL_ENA_EXTLCK__W                                     1
9252 #define   SCU_RAM_QAM_CTL_ENA_EXTLCK__M                                     0x400
9253 #define   SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE                                   0x0
9254 
9255 #define SCU_RAM_QAM_WR_RSV_1__A                                             0x831FB4
9256 #define SCU_RAM_QAM_WR_RSV_1__W                                             16
9257 #define SCU_RAM_QAM_WR_RSV_1__M                                             0xFFFF
9258 #define SCU_RAM_QAM_WR_RSV_1__PRE                                           0x0
9259 
9260 #define   SCU_RAM_QAM_WR_RSV_1_BIT__B                                       0
9261 #define   SCU_RAM_QAM_WR_RSV_1_BIT__W                                       16
9262 #define   SCU_RAM_QAM_WR_RSV_1_BIT__M                                       0xFFFF
9263 #define   SCU_RAM_QAM_WR_RSV_1_BIT__PRE                                     0x0
9264 
9265 #define SCU_RAM_QAM_WR_RSV_2__A                                             0x831FB5
9266 #define SCU_RAM_QAM_WR_RSV_2__W                                             16
9267 #define SCU_RAM_QAM_WR_RSV_2__M                                             0xFFFF
9268 #define SCU_RAM_QAM_WR_RSV_2__PRE                                           0x0
9269 
9270 #define   SCU_RAM_QAM_WR_RSV_2_BIT__B                                       0
9271 #define   SCU_RAM_QAM_WR_RSV_2_BIT__W                                       16
9272 #define   SCU_RAM_QAM_WR_RSV_2_BIT__M                                       0xFFFF
9273 #define   SCU_RAM_QAM_WR_RSV_2_BIT__PRE                                     0x0
9274 
9275 #define SCU_RAM_QAM_WR_RSV_3__A                                             0x831FB6
9276 #define SCU_RAM_QAM_WR_RSV_3__W                                             16
9277 #define SCU_RAM_QAM_WR_RSV_3__M                                             0xFFFF
9278 #define SCU_RAM_QAM_WR_RSV_3__PRE                                           0x0
9279 
9280 #define   SCU_RAM_QAM_WR_RSV_3_BIT__B                                       0
9281 #define   SCU_RAM_QAM_WR_RSV_3_BIT__W                                       16
9282 #define   SCU_RAM_QAM_WR_RSV_3_BIT__M                                       0xFFFF
9283 #define   SCU_RAM_QAM_WR_RSV_3_BIT__PRE                                     0x0
9284 
9285 #define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A                                 0x831FB7
9286 #define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W                                 3
9287 #define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M                                 0x7
9288 #define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE                               0x0
9289 
9290 #define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B                           0
9291 #define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W                           3
9292 #define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M                           0x7
9293 #define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE                         0x0
9294 #define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN                    0x0
9295 #define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16                     0x3
9296 #define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32                     0x4
9297 #define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64                     0x5
9298 #define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128                    0x6
9299 #define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256                    0x7
9300 
9301 #define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A                                    0x831FB8
9302 #define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W                                    8
9303 #define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M                                    0xFF
9304 #define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE                                  0x0
9305 
9306 #define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B                              0
9307 #define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W                              8
9308 #define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M                              0xFF
9309 #define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE                            0x0
9310 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1                       0x0
9311 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2                    0x1
9312 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2                       0x2
9313 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2                        0x3
9314 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3                       0x4
9315 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4                        0x5
9316 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4                       0x6
9317 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8                        0x7
9318 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5                       0x8
9319 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16                        0x9
9320 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6                       0xA
9321 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7                       0xC
9322 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8                       0xE
9323 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17                       0x10
9324 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4                         0x11
9325 #define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN                       0xFE
9326 
9327 #define SCU_RAM_QAM_RD_RSV_4__A                                             0x831FB9
9328 #define SCU_RAM_QAM_RD_RSV_4__W                                             16
9329 #define SCU_RAM_QAM_RD_RSV_4__M                                             0xFFFF
9330 #define SCU_RAM_QAM_RD_RSV_4__PRE                                           0x0
9331 
9332 #define   SCU_RAM_QAM_RD_RSV_4_BIT__B                                       0
9333 #define   SCU_RAM_QAM_RD_RSV_4_BIT__W                                       16
9334 #define   SCU_RAM_QAM_RD_RSV_4_BIT__M                                       0xFFFF
9335 #define   SCU_RAM_QAM_RD_RSV_4_BIT__PRE                                     0x0
9336 
9337 #define SCU_RAM_QAM_LOCKED__A                                               0x831FBA
9338 #define SCU_RAM_QAM_LOCKED__W                                               16
9339 #define SCU_RAM_QAM_LOCKED__M                                               0xFFFF
9340 #define SCU_RAM_QAM_LOCKED__PRE                                             0x0
9341 
9342 #define   SCU_RAM_QAM_LOCKED_INTLEVEL__B                                    0
9343 #define   SCU_RAM_QAM_LOCKED_INTLEVEL__W                                    8
9344 #define   SCU_RAM_QAM_LOCKED_INTLEVEL__M                                    0xFF
9345 #define   SCU_RAM_QAM_LOCKED_INTLEVEL__PRE                                  0x0
9346 #define     SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED                          0x0
9347 #define     SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK                              0x1
9348 #define     SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK                             0x2
9349 #define     SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK                             0x3
9350 #define     SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK                          0x4
9351 #define     SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK                          0x5
9352 #define     SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK                            0x6
9353 #define     SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK                         0x7
9354 
9355 #define   SCU_RAM_QAM_LOCKED_LOCKED__B                                      8
9356 #define   SCU_RAM_QAM_LOCKED_LOCKED__W                                      8
9357 #define   SCU_RAM_QAM_LOCKED_LOCKED__M                                      0xFF00
9358 #define   SCU_RAM_QAM_LOCKED_LOCKED__PRE                                    0x0
9359 #define     SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED                            0x0
9360 #define     SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED                          0x4000
9361 #define     SCU_RAM_QAM_LOCKED_LOCKED_LOCKED                                0x8000
9362 #define     SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK                            0xC000
9363 
9364 #define SCU_RAM_QAM_EVENTS_OCC_HI__A                                        0x831FBB
9365 #define SCU_RAM_QAM_EVENTS_OCC_HI__W                                        16
9366 #define SCU_RAM_QAM_EVENTS_OCC_HI__M                                        0xFFFF
9367 #define SCU_RAM_QAM_EVENTS_OCC_HI__PRE                                      0x0
9368 
9369 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B                               0
9370 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W                               1
9371 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M                               0x1
9372 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE                             0x0
9373 
9374 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B                          1
9375 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W                          1
9376 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M                          0x2
9377 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE                        0x0
9378 
9379 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B                                 2
9380 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W                                 1
9381 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M                                 0x4
9382 #define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE                               0x0
9383 
9384 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B                           3
9385 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W                           1
9386 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M                           0x8
9387 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE                         0x0
9388 
9389 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B                          4
9390 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W                          1
9391 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M                          0x10
9392 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE                        0x0
9393 
9394 #define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B                              5
9395 #define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W                              1
9396 #define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M                              0x20
9397 #define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE                            0x0
9398 
9399 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B                            6
9400 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W                            1
9401 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M                            0x40
9402 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE                          0x0
9403 
9404 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B                           7
9405 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W                           1
9406 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M                           0x80
9407 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE                         0x0
9408 
9409 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B                              8
9410 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W                              1
9411 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M                              0x100
9412 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE                            0x0
9413 
9414 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B                            9
9415 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W                            1
9416 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M                            0x200
9417 #define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE                          0x0
9418 
9419 #define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B                              10
9420 #define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W                              1
9421 #define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M                              0x400
9422 #define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE                            0x0
9423 
9424 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B                              11
9425 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W                              1
9426 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M                              0x800
9427 #define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE                            0x0
9428 
9429 #define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B                                  12
9430 #define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W                                  4
9431 #define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M                                  0xF000
9432 #define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE                                0x0
9433 
9434 #define SCU_RAM_QAM_EVENTS_OCC_LO__A                                        0x831FBC
9435 #define SCU_RAM_QAM_EVENTS_OCC_LO__W                                        16
9436 #define SCU_RAM_QAM_EVENTS_OCC_LO__M                                        0xFFFF
9437 #define SCU_RAM_QAM_EVENTS_OCC_LO__PRE                                      0x0
9438 
9439 #define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B                                0
9440 #define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W                                1
9441 #define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M                                0x1
9442 #define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE                              0x0
9443 
9444 #define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B                                 1
9445 #define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W                                 1
9446 #define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M                                 0x2
9447 #define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE                               0x0
9448 
9449 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B                                2
9450 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W                                1
9451 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M                                0x4
9452 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE                              0x0
9453 
9454 #define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B                                3
9455 #define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W                                1
9456 #define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M                                0x8
9457 #define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE                              0x0
9458 
9459 #define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B                               4
9460 #define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W                               1
9461 #define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M                               0x10
9462 #define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE                             0x0
9463 
9464 #define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__B                                  5
9465 #define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__W                                  1
9466 #define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__M                                  0x20
9467 #define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE                                0x0
9468 
9469 #define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B                                 6
9470 #define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W                                 1
9471 #define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M                                 0x40
9472 #define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE                               0x0
9473 
9474 #define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B                             7
9475 #define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W                             1
9476 #define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M                             0x80
9477 #define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE                           0x0
9478 
9479 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__B                                  8
9480 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__W                                  1
9481 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__M                                  0x100
9482 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE                                0x0
9483 
9484 #define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B                           9
9485 #define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W                           1
9486 #define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M                           0x200
9487 #define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE                         0x0
9488 
9489 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B                           10
9490 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W                           1
9491 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M                           0x400
9492 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE                         0x0
9493 
9494 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B                          11
9495 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W                          1
9496 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M                          0x800
9497 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE                        0x0
9498 
9499 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B                          12
9500 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W                          1
9501 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M                          0x1000
9502 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE                        0x0
9503 
9504 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B                             13
9505 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W                             1
9506 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M                             0x2000
9507 #define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE                           0x0
9508 
9509 #define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B                           14
9510 #define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W                           1
9511 #define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M                           0x4000
9512 #define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE                         0x0
9513 
9514 #define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B                          15
9515 #define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W                          1
9516 #define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M                          0x8000
9517 #define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE                        0x0
9518 
9519 #define SCU_RAM_QAM_EVENTS_SCHED_HI__A                                      0x831FBD
9520 #define SCU_RAM_QAM_EVENTS_SCHED_HI__W                                      16
9521 #define SCU_RAM_QAM_EVENTS_SCHED_HI__M                                      0xFFFF
9522 #define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE                                    0x0
9523 
9524 #define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B                                0
9525 #define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W                                16
9526 #define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M                                0xFFFF
9527 #define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE                              0x0
9528 
9529 #define SCU_RAM_QAM_EVENTS_SCHED_LO__A                                      0x831FBE
9530 #define SCU_RAM_QAM_EVENTS_SCHED_LO__W                                      16
9531 #define SCU_RAM_QAM_EVENTS_SCHED_LO__M                                      0xFFFF
9532 #define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE                                    0x0
9533 
9534 #define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B                                0
9535 #define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W                                16
9536 #define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M                                0xFFFF
9537 #define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE                              0x0
9538 
9539 #define SCU_RAM_QAM_TASKLETS_SCHED__A                                       0x831FBF
9540 #define SCU_RAM_QAM_TASKLETS_SCHED__W                                       16
9541 #define SCU_RAM_QAM_TASKLETS_SCHED__M                                       0xFFFF
9542 #define SCU_RAM_QAM_TASKLETS_SCHED__PRE                                     0x0
9543 
9544 #define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__B                                 0
9545 #define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__W                                 16
9546 #define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__M                                 0xFFFF
9547 #define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE                               0x0
9548 
9549 #define SCU_RAM_QAM_TASKLETS_RUN__A                                         0x831FC0
9550 #define SCU_RAM_QAM_TASKLETS_RUN__W                                         16
9551 #define SCU_RAM_QAM_TASKLETS_RUN__M                                         0xFFFF
9552 #define SCU_RAM_QAM_TASKLETS_RUN__PRE                                       0x0
9553 
9554 #define   SCU_RAM_QAM_TASKLETS_RUN_BIT__B                                   0
9555 #define   SCU_RAM_QAM_TASKLETS_RUN_BIT__W                                   16
9556 #define   SCU_RAM_QAM_TASKLETS_RUN_BIT__M                                   0xFFFF
9557 #define   SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE                                 0x0
9558 
9559 #define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A                                 0x831FC1
9560 #define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W                                 16
9561 #define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M                                 0xFFFF
9562 #define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE                               0x0
9563 
9564 #define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B                           0
9565 #define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W                           16
9566 #define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M                           0xFFFF
9567 #define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE                         0x0
9568 
9569 #define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A                                 0x831FC2
9570 #define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W                                 16
9571 #define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M                                 0xFFFF
9572 #define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE                               0x0
9573 
9574 #define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B                           0
9575 #define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W                           16
9576 #define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M                           0xFFFF
9577 #define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE                         0x0
9578 
9579 #define SCU_RAM_QAM_RD_RSV_5__A                                             0x831FC3
9580 #define SCU_RAM_QAM_RD_RSV_5__W                                             16
9581 #define SCU_RAM_QAM_RD_RSV_5__M                                             0xFFFF
9582 #define SCU_RAM_QAM_RD_RSV_5__PRE                                           0x0
9583 
9584 #define   SCU_RAM_QAM_RD_RSV_5_BIT__B                                       0
9585 #define   SCU_RAM_QAM_RD_RSV_5_BIT__W                                       16
9586 #define   SCU_RAM_QAM_RD_RSV_5_BIT__M                                       0xFFFF
9587 #define   SCU_RAM_QAM_RD_RSV_5_BIT__PRE                                     0x0
9588 
9589 #define SCU_RAM_QAM_RD_RSV_6__A                                             0x831FC4
9590 #define SCU_RAM_QAM_RD_RSV_6__W                                             16
9591 #define SCU_RAM_QAM_RD_RSV_6__M                                             0xFFFF
9592 #define SCU_RAM_QAM_RD_RSV_6__PRE                                           0x0
9593 
9594 #define   SCU_RAM_QAM_RD_RSV_6_BIT__B                                       0
9595 #define   SCU_RAM_QAM_RD_RSV_6_BIT__W                                       16
9596 #define   SCU_RAM_QAM_RD_RSV_6_BIT__M                                       0xFFFF
9597 #define   SCU_RAM_QAM_RD_RSV_6_BIT__PRE                                     0x0
9598 
9599 #define SCU_RAM_QAM_RD_RSV_7__A                                             0x831FC5
9600 #define SCU_RAM_QAM_RD_RSV_7__W                                             16
9601 #define SCU_RAM_QAM_RD_RSV_7__M                                             0xFFFF
9602 #define SCU_RAM_QAM_RD_RSV_7__PRE                                           0x0
9603 
9604 #define   SCU_RAM_QAM_RD_RSV_7_BIT__B                                       0
9605 #define   SCU_RAM_QAM_RD_RSV_7_BIT__W                                       16
9606 #define   SCU_RAM_QAM_RD_RSV_7_BIT__M                                       0xFFFF
9607 #define   SCU_RAM_QAM_RD_RSV_7_BIT__PRE                                     0x0
9608 
9609 #define SCU_RAM_QAM_RD_RSV_8__A                                             0x831FC6
9610 #define SCU_RAM_QAM_RD_RSV_8__W                                             16
9611 #define SCU_RAM_QAM_RD_RSV_8__M                                             0xFFFF
9612 #define SCU_RAM_QAM_RD_RSV_8__PRE                                           0x0
9613 
9614 #define   SCU_RAM_QAM_RD_RSV_8_BIT__B                                       0
9615 #define   SCU_RAM_QAM_RD_RSV_8_BIT__W                                       16
9616 #define   SCU_RAM_QAM_RD_RSV_8_BIT__M                                       0xFFFF
9617 #define   SCU_RAM_QAM_RD_RSV_8_BIT__PRE                                     0x0
9618 
9619 #define SCU_RAM_QAM_RD_RSV_9__A                                             0x831FC7
9620 #define SCU_RAM_QAM_RD_RSV_9__W                                             16
9621 #define SCU_RAM_QAM_RD_RSV_9__M                                             0xFFFF
9622 #define SCU_RAM_QAM_RD_RSV_9__PRE                                           0x0
9623 
9624 #define   SCU_RAM_QAM_RD_RSV_9_BIT__B                                       0
9625 #define   SCU_RAM_QAM_RD_RSV_9_BIT__W                                       16
9626 #define   SCU_RAM_QAM_RD_RSV_9_BIT__M                                       0xFFFF
9627 #define   SCU_RAM_QAM_RD_RSV_9_BIT__PRE                                     0x0
9628 
9629 #define SCU_RAM_QAM_RD_RSV_10__A                                            0x831FC8
9630 #define SCU_RAM_QAM_RD_RSV_10__W                                            16
9631 #define SCU_RAM_QAM_RD_RSV_10__M                                            0xFFFF
9632 #define SCU_RAM_QAM_RD_RSV_10__PRE                                          0x0
9633 
9634 #define   SCU_RAM_QAM_RD_RSV_10_BIT__B                                      0
9635 #define   SCU_RAM_QAM_RD_RSV_10_BIT__W                                      16
9636 #define   SCU_RAM_QAM_RD_RSV_10_BIT__M                                      0xFFFF
9637 #define   SCU_RAM_QAM_RD_RSV_10_BIT__PRE                                    0x0
9638 
9639 #define SCU_RAM_QAM_AGC_TPOW_OFFS__A                                        0x831FC9
9640 #define SCU_RAM_QAM_AGC_TPOW_OFFS__W                                        16
9641 #define SCU_RAM_QAM_AGC_TPOW_OFFS__M                                        0xFFFF
9642 #define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE                                      0x0
9643 
9644 #define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B                                  0
9645 #define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W                                  16
9646 #define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M                                  0xFFFF
9647 #define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE                                0x0
9648 
9649 #define SCU_RAM_QAM_FSM_STATE__A                                            0x831FCA
9650 #define SCU_RAM_QAM_FSM_STATE__W                                            4
9651 #define SCU_RAM_QAM_FSM_STATE__M                                            0xF
9652 #define SCU_RAM_QAM_FSM_STATE__PRE                                          0x0
9653 
9654 #define   SCU_RAM_QAM_FSM_STATE_BIT__B                                      0
9655 #define   SCU_RAM_QAM_FSM_STATE_BIT__W                                      4
9656 #define   SCU_RAM_QAM_FSM_STATE_BIT__M                                      0xF
9657 #define   SCU_RAM_QAM_FSM_STATE_BIT__PRE                                    0x0
9658 #define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP                           0x0
9659 #define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE                          0x1
9660 #define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ                          0x2
9661 #define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT                       0x3
9662 #define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE                         0x4
9663 #define     SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE                      0x5
9664 #define     SCU_RAM_QAM_FSM_STATE_BIT_TRACKING                              0x6
9665 #define     SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST                        0x7
9666 
9667 #define SCU_RAM_QAM_FSM_STATE_NEW__A                                        0x831FCB
9668 #define SCU_RAM_QAM_FSM_STATE_NEW__W                                        4
9669 #define SCU_RAM_QAM_FSM_STATE_NEW__M                                        0xF
9670 #define SCU_RAM_QAM_FSM_STATE_NEW__PRE                                      0x0
9671 
9672 #define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__B                                  0
9673 #define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__W                                  4
9674 #define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__M                                  0xF
9675 #define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE                                0x0
9676 #define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP                       0x0
9677 #define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE                      0x1
9678 #define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ                      0x2
9679 #define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT                   0x3
9680 #define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE                     0x4
9681 #define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE                  0x5
9682 #define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING                          0x6
9683 #define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST                    0x7
9684 
9685 #define SCU_RAM_QAM_FSM_LOCK_FLAGS__A                                       0x831FCC
9686 #define SCU_RAM_QAM_FSM_LOCK_FLAGS__W                                       9
9687 #define SCU_RAM_QAM_FSM_LOCK_FLAGS__M                                       0x1FF
9688 #define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE                                     0x0
9689 
9690 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B                             0
9691 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W                             1
9692 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M                             0x1
9693 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE                           0x0
9694 
9695 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B                         1
9696 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W                         1
9697 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M                         0x2
9698 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE                       0x0
9699 
9700 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B                          2
9701 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W                          1
9702 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M                          0x4
9703 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE                        0x0
9704 
9705 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B                            3
9706 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W                            1
9707 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M                            0x8
9708 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE                          0x0
9709 
9710 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B                         4
9711 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W                         1
9712 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M                         0x10
9713 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE                       0x0
9714 
9715 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B                          5
9716 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W                          1
9717 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M                          0x20
9718 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE                        0x0
9719 
9720 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B                         6
9721 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W                         1
9722 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M                         0x40
9723 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE                       0x0
9724 
9725 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B                           7
9726 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W                           1
9727 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M                           0x80
9728 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE                         0x0
9729 
9730 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B                          8
9731 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W                          1
9732 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M                          0x100
9733 #define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE                        0x0
9734 
9735 #define SCU_RAM_QAM_FSM_RATE_VARIATION__A                                   0x831FCD
9736 #define SCU_RAM_QAM_FSM_RATE_VARIATION__W                                   16
9737 #define SCU_RAM_QAM_FSM_RATE_VARIATION__M                                   0xFFFF
9738 #define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE                                 0x0
9739 
9740 #define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B                             0
9741 #define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W                             16
9742 #define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M                             0xFFFF
9743 #define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE                           0x0
9744 
9745 #define SCU_RAM_QAM_FSM_FREQ_VARIATION__A                                   0x831FCE
9746 #define SCU_RAM_QAM_FSM_FREQ_VARIATION__W                                   16
9747 #define SCU_RAM_QAM_FSM_FREQ_VARIATION__M                                   0xFFFF
9748 #define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE                                 0x0
9749 
9750 #define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B                             0
9751 #define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W                             16
9752 #define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M                             0xFFFF
9753 #define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE                           0x0
9754 
9755 #define SCU_RAM_QAM_ERR_STATE__A                                            0x831FCF
9756 #define SCU_RAM_QAM_ERR_STATE__W                                            4
9757 #define SCU_RAM_QAM_ERR_STATE__M                                            0xF
9758 #define SCU_RAM_QAM_ERR_STATE__PRE                                          0x0
9759 
9760 #define   SCU_RAM_QAM_ERR_STATE_BIT__B                                      0
9761 #define   SCU_RAM_QAM_ERR_STATE_BIT__W                                      4
9762 #define   SCU_RAM_QAM_ERR_STATE_BIT__M                                      0xF
9763 #define   SCU_RAM_QAM_ERR_STATE_BIT__PRE                                    0x0
9764 #define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP                           0x0
9765 #define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE                          0x1
9766 #define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ                          0x2
9767 #define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT                       0x3
9768 #define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE                         0x4
9769 #define     SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE                      0x5
9770 #define     SCU_RAM_QAM_ERR_STATE_BIT_TRACKING                              0x6
9771 #define     SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST                        0x7
9772 
9773 #define SCU_RAM_QAM_ERR_LOCK_FLAGS__A                                       0x831FD0
9774 #define SCU_RAM_QAM_ERR_LOCK_FLAGS__W                                       9
9775 #define SCU_RAM_QAM_ERR_LOCK_FLAGS__M                                       0x1FF
9776 #define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE                                     0x0
9777 
9778 #define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B                             0
9779 #define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W                             1
9780 #define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M                             0x1
9781 #define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE                           0x0
9782 
9783 #define SCU_RAM_QAM_EQ_LOCK__A                                              0x831FD1
9784 #define SCU_RAM_QAM_EQ_LOCK__W                                              1
9785 #define SCU_RAM_QAM_EQ_LOCK__M                                              0x1
9786 #define SCU_RAM_QAM_EQ_LOCK__PRE                                            0x0
9787 
9788 #define   SCU_RAM_QAM_EQ_LOCK_BIT__B                                        0
9789 #define   SCU_RAM_QAM_EQ_LOCK_BIT__W                                        1
9790 #define   SCU_RAM_QAM_EQ_LOCK_BIT__M                                        0x1
9791 #define   SCU_RAM_QAM_EQ_LOCK_BIT__PRE                                      0x0
9792 
9793 #define SCU_RAM_QAM_EQ_STATE__A                                             0x831FD2
9794 #define SCU_RAM_QAM_EQ_STATE__W                                             16
9795 #define SCU_RAM_QAM_EQ_STATE__M                                             0xFFFF
9796 #define SCU_RAM_QAM_EQ_STATE__PRE                                           0x0
9797 
9798 #define   SCU_RAM_QAM_EQ_STATE_BIT__B                                       0
9799 #define   SCU_RAM_QAM_EQ_STATE_BIT__W                                       16
9800 #define   SCU_RAM_QAM_EQ_STATE_BIT__M                                       0xFFFF
9801 #define   SCU_RAM_QAM_EQ_STATE_BIT__PRE                                     0x0
9802 
9803 #define SCU_RAM_QAM_RD_RSV_0__A                                             0x831FD3
9804 #define SCU_RAM_QAM_RD_RSV_0__W                                             16
9805 #define SCU_RAM_QAM_RD_RSV_0__M                                             0xFFFF
9806 #define SCU_RAM_QAM_RD_RSV_0__PRE                                           0x0
9807 
9808 #define   SCU_RAM_QAM_RD_RSV_0_BIT__B                                       0
9809 #define   SCU_RAM_QAM_RD_RSV_0_BIT__W                                       16
9810 #define   SCU_RAM_QAM_RD_RSV_0_BIT__M                                       0xFFFF
9811 #define   SCU_RAM_QAM_RD_RSV_0_BIT__PRE                                     0x0
9812 
9813 #define SCU_RAM_QAM_RD_RSV_1__A                                             0x831FD4
9814 #define SCU_RAM_QAM_RD_RSV_1__W                                             16
9815 #define SCU_RAM_QAM_RD_RSV_1__M                                             0xFFFF
9816 #define SCU_RAM_QAM_RD_RSV_1__PRE                                           0x0
9817 
9818 #define   SCU_RAM_QAM_RD_RSV_1_BIT__B                                       0
9819 #define   SCU_RAM_QAM_RD_RSV_1_BIT__W                                       16
9820 #define   SCU_RAM_QAM_RD_RSV_1_BIT__M                                       0xFFFF
9821 #define   SCU_RAM_QAM_RD_RSV_1_BIT__PRE                                     0x0
9822 
9823 #define SCU_RAM_QAM_RD_RSV_2__A                                             0x831FD5
9824 #define SCU_RAM_QAM_RD_RSV_2__W                                             16
9825 #define SCU_RAM_QAM_RD_RSV_2__M                                             0xFFFF
9826 #define SCU_RAM_QAM_RD_RSV_2__PRE                                           0x0
9827 
9828 #define   SCU_RAM_QAM_RD_RSV_2_BIT__B                                       0
9829 #define   SCU_RAM_QAM_RD_RSV_2_BIT__W                                       16
9830 #define   SCU_RAM_QAM_RD_RSV_2_BIT__M                                       0xFFFF
9831 #define   SCU_RAM_QAM_RD_RSV_2_BIT__PRE                                     0x0
9832 
9833 #define SCU_RAM_QAM_RD_RSV_3__A                                             0x831FD6
9834 #define SCU_RAM_QAM_RD_RSV_3__W                                             16
9835 #define SCU_RAM_QAM_RD_RSV_3__M                                             0xFFFF
9836 #define SCU_RAM_QAM_RD_RSV_3__PRE                                           0x0
9837 
9838 #define   SCU_RAM_QAM_RD_RSV_3_BIT__B                                       0
9839 #define   SCU_RAM_QAM_RD_RSV_3_BIT__W                                       16
9840 #define   SCU_RAM_QAM_RD_RSV_3_BIT__M                                       0xFFFF
9841 #define   SCU_RAM_QAM_RD_RSV_3_BIT__PRE                                     0x0
9842 
9843 #define SCU_RAM_VSB_CTL_MODE__A                                             0x831FD7
9844 #define SCU_RAM_VSB_CTL_MODE__W                                             2
9845 #define SCU_RAM_VSB_CTL_MODE__M                                             0x3
9846 #define SCU_RAM_VSB_CTL_MODE__PRE                                           0x0
9847 
9848 #define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__B                          0
9849 #define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__W                          1
9850 #define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__M                          0x1
9851 #define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__PRE                        0x0
9852 #define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_OFF                       0x0
9853 #define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_ON                        0x1
9854 
9855 #define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__B                          1
9856 #define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__W                          1
9857 #define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__M                          0x2
9858 #define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__PRE                        0x0
9859 #define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF                       0x0
9860 #define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON                        0x2
9861 
9862 #define SCU_RAM_VSB_NOTCH_THRESHOLD__A                                      0x831FD8
9863 #define SCU_RAM_VSB_NOTCH_THRESHOLD__W                                      16
9864 #define SCU_RAM_VSB_NOTCH_THRESHOLD__M                                      0xFFFF
9865 #define SCU_RAM_VSB_NOTCH_THRESHOLD__PRE                                    0x0
9866 
9867 #define SCU_RAM_VSB_RSV_0__A                                                0x831FD9
9868 #define SCU_RAM_VSB_RSV_0__W                                                16
9869 #define SCU_RAM_VSB_RSV_0__M                                                0xFFFF
9870 #define SCU_RAM_VSB_RSV_0__PRE                                              0x0
9871 
9872 #define SCU_RAM_VSB_RSV_1__A                                                0x831FDA
9873 #define SCU_RAM_VSB_RSV_1__W                                                16
9874 #define SCU_RAM_VSB_RSV_1__M                                                0xFFFF
9875 #define SCU_RAM_VSB_RSV_1__PRE                                              0x0
9876 
9877 #define SCU_RAM_VSB_RSV_2__A                                                0x831FDB
9878 #define SCU_RAM_VSB_RSV_2__W                                                16
9879 #define SCU_RAM_VSB_RSV_2__M                                                0xFFFF
9880 #define SCU_RAM_VSB_RSV_2__PRE                                              0x0
9881 
9882 #define SCU_RAM_VSB_RSV_3__A                                                0x831FDC
9883 #define SCU_RAM_VSB_RSV_3__W                                                16
9884 #define SCU_RAM_VSB_RSV_3__M                                                0xFFFF
9885 #define SCU_RAM_VSB_RSV_3__PRE                                              0x0
9886 
9887 #define SCU_RAM_VSB_RSV_4__A                                                0x831FDD
9888 #define SCU_RAM_VSB_RSV_4__W                                                16
9889 #define SCU_RAM_VSB_RSV_4__M                                                0xFFFF
9890 #define SCU_RAM_VSB_RSV_4__PRE                                              0x0
9891 
9892 #define SCU_RAM_VSB_RSV_5__A                                                0x831FDE
9893 #define SCU_RAM_VSB_RSV_5__W                                                16
9894 #define SCU_RAM_VSB_RSV_5__M                                                0xFFFF
9895 #define SCU_RAM_VSB_RSV_5__PRE                                              0x0
9896 
9897 #define SCU_RAM_VSB_RSV_6__A                                                0x831FDF
9898 #define SCU_RAM_VSB_RSV_6__W                                                16
9899 #define SCU_RAM_VSB_RSV_6__M                                                0xFFFF
9900 #define SCU_RAM_VSB_RSV_6__PRE                                              0x0
9901 
9902 #define SCU_RAM_VSB_RSV_7__A                                                0x831FE0
9903 #define SCU_RAM_VSB_RSV_7__W                                                16
9904 #define SCU_RAM_VSB_RSV_7__M                                                0xFFFF
9905 #define SCU_RAM_VSB_RSV_7__PRE                                              0x0
9906 
9907 #define SCU_RAM_VSB_RSV_8__A                                                0x831FE1
9908 #define SCU_RAM_VSB_RSV_8__W                                                16
9909 #define SCU_RAM_VSB_RSV_8__M                                                0xFFFF
9910 #define SCU_RAM_VSB_RSV_8__PRE                                              0x0
9911 
9912 #define SCU_RAM_VSB_RSV_9__A                                                0x831FE2
9913 #define SCU_RAM_VSB_RSV_9__W                                                16
9914 #define SCU_RAM_VSB_RSV_9__M                                                0xFFFF
9915 #define SCU_RAM_VSB_RSV_9__PRE                                              0x0
9916 
9917 #define SCU_RAM_VSB_RSV_10__A                                               0x831FE3
9918 #define SCU_RAM_VSB_RSV_10__W                                               16
9919 #define SCU_RAM_VSB_RSV_10__M                                               0xFFFF
9920 #define SCU_RAM_VSB_RSV_10__PRE                                             0x0
9921 
9922 #define SCU_RAM_VSB_RSV_11__A                                               0x831FE4
9923 #define SCU_RAM_VSB_RSV_11__W                                               16
9924 #define SCU_RAM_VSB_RSV_11__M                                               0xFFFF
9925 #define SCU_RAM_VSB_RSV_11__PRE                                             0x0
9926 
9927 #define SCU_RAM_VSB_RSV_12__A                                               0x831FE5
9928 #define SCU_RAM_VSB_RSV_12__W                                               16
9929 #define SCU_RAM_VSB_RSV_12__M                                               0xFFFF
9930 #define SCU_RAM_VSB_RSV_12__PRE                                             0x0
9931 
9932 #define SCU_RAM_VSB_RSV_13__A                                               0x831FE6
9933 #define SCU_RAM_VSB_RSV_13__W                                               16
9934 #define SCU_RAM_VSB_RSV_13__M                                               0xFFFF
9935 #define SCU_RAM_VSB_RSV_13__PRE                                             0x0
9936 
9937 #define SCU_RAM_VSB_AGC_POW_TGT__A                                          0x831FE7
9938 #define SCU_RAM_VSB_AGC_POW_TGT__W                                          15
9939 #define SCU_RAM_VSB_AGC_POW_TGT__M                                          0x7FFF
9940 #define SCU_RAM_VSB_AGC_POW_TGT__PRE                                        0x0
9941 
9942 #define SCU_RAM_VSB_OUTER_LOOP_CYCLE__A                                     0x831FE8
9943 #define SCU_RAM_VSB_OUTER_LOOP_CYCLE__W                                     8
9944 #define SCU_RAM_VSB_OUTER_LOOP_CYCLE__M                                     0xFF
9945 #define SCU_RAM_VSB_OUTER_LOOP_CYCLE__PRE                                   0x0
9946 
9947 #define SCU_RAM_VSB_FIELD_NUMBER__A                                         0x831FE9
9948 #define SCU_RAM_VSB_FIELD_NUMBER__W                                         9
9949 #define SCU_RAM_VSB_FIELD_NUMBER__M                                         0x1FF
9950 #define SCU_RAM_VSB_FIELD_NUMBER__PRE                                       0x0
9951 
9952 #define SCU_RAM_VSB_SEGMENT_NUMBER__A                                       0x831FEA
9953 #define SCU_RAM_VSB_SEGMENT_NUMBER__W                                       10
9954 #define SCU_RAM_VSB_SEGMENT_NUMBER__M                                       0x3FF
9955 #define SCU_RAM_VSB_SEGMENT_NUMBER__PRE                                     0x0
9956 
9957 #define SCU_RAM_DRIVER_VER_HI__A                                            0x831FEB
9958 #define SCU_RAM_DRIVER_VER_HI__W                                            16
9959 #define SCU_RAM_DRIVER_VER_HI__M                                            0xFFFF
9960 #define SCU_RAM_DRIVER_VER_HI__PRE                                          0x0
9961 
9962 #define SCU_RAM_DRIVER_VER_LO__A                                            0x831FEC
9963 #define SCU_RAM_DRIVER_VER_LO__W                                            16
9964 #define SCU_RAM_DRIVER_VER_LO__M                                            0xFFFF
9965 #define SCU_RAM_DRIVER_VER_LO__PRE                                          0x0
9966 
9967 #define SCU_RAM_PARAM_15__A                                                 0x831FED
9968 #define SCU_RAM_PARAM_15__W                                                 16
9969 #define SCU_RAM_PARAM_15__M                                                 0xFFFF
9970 #define SCU_RAM_PARAM_15__PRE                                               0x0
9971 
9972 #define SCU_RAM_PARAM_14__A                                                 0x831FEE
9973 #define SCU_RAM_PARAM_14__W                                                 16
9974 #define SCU_RAM_PARAM_14__M                                                 0xFFFF
9975 #define SCU_RAM_PARAM_14__PRE                                               0x0
9976 
9977 #define SCU_RAM_PARAM_13__A                                                 0x831FEF
9978 #define SCU_RAM_PARAM_13__W                                                 16
9979 #define SCU_RAM_PARAM_13__M                                                 0xFFFF
9980 #define SCU_RAM_PARAM_13__PRE                                               0x0
9981 
9982 #define SCU_RAM_PARAM_12__A                                                 0x831FF0
9983 #define SCU_RAM_PARAM_12__W                                                 16
9984 #define SCU_RAM_PARAM_12__M                                                 0xFFFF
9985 #define SCU_RAM_PARAM_12__PRE                                               0x0
9986 
9987 #define SCU_RAM_PARAM_11__A                                                 0x831FF1
9988 #define SCU_RAM_PARAM_11__W                                                 16
9989 #define SCU_RAM_PARAM_11__M                                                 0xFFFF
9990 #define SCU_RAM_PARAM_11__PRE                                               0x0
9991 
9992 #define SCU_RAM_PARAM_10__A                                                 0x831FF2
9993 #define SCU_RAM_PARAM_10__W                                                 16
9994 #define SCU_RAM_PARAM_10__M                                                 0xFFFF
9995 #define SCU_RAM_PARAM_10__PRE                                               0x0
9996 
9997 #define SCU_RAM_PARAM_9__A                                                  0x831FF3
9998 #define SCU_RAM_PARAM_9__W                                                  16
9999 #define SCU_RAM_PARAM_9__M                                                  0xFFFF
10000 #define SCU_RAM_PARAM_9__PRE                                                0x0
10001 
10002 #define SCU_RAM_PARAM_8__A                                                  0x831FF4
10003 #define SCU_RAM_PARAM_8__W                                                  16
10004 #define SCU_RAM_PARAM_8__M                                                  0xFFFF
10005 #define SCU_RAM_PARAM_8__PRE                                                0x0
10006 
10007 #define SCU_RAM_PARAM_7__A                                                  0x831FF5
10008 #define SCU_RAM_PARAM_7__W                                                  16
10009 #define SCU_RAM_PARAM_7__M                                                  0xFFFF
10010 #define SCU_RAM_PARAM_7__PRE                                                0x0
10011 
10012 #define SCU_RAM_PARAM_6__A                                                  0x831FF6
10013 #define SCU_RAM_PARAM_6__W                                                  16
10014 #define SCU_RAM_PARAM_6__M                                                  0xFFFF
10015 #define SCU_RAM_PARAM_6__PRE                                                0x0
10016 
10017 #define SCU_RAM_PARAM_5__A                                                  0x831FF7
10018 #define SCU_RAM_PARAM_5__W                                                  16
10019 #define SCU_RAM_PARAM_5__M                                                  0xFFFF
10020 #define SCU_RAM_PARAM_5__PRE                                                0x0
10021 
10022 #define SCU_RAM_PARAM_4__A                                                  0x831FF8
10023 #define SCU_RAM_PARAM_4__W                                                  16
10024 #define SCU_RAM_PARAM_4__M                                                  0xFFFF
10025 #define SCU_RAM_PARAM_4__PRE                                                0x0
10026 
10027 #define SCU_RAM_PARAM_3__A                                                  0x831FF9
10028 #define SCU_RAM_PARAM_3__W                                                  16
10029 #define SCU_RAM_PARAM_3__M                                                  0xFFFF
10030 #define SCU_RAM_PARAM_3__PRE                                                0x0
10031 
10032 #define SCU_RAM_PARAM_2__A                                                  0x831FFA
10033 #define SCU_RAM_PARAM_2__W                                                  16
10034 #define SCU_RAM_PARAM_2__M                                                  0xFFFF
10035 #define SCU_RAM_PARAM_2__PRE                                                0x0
10036 
10037 #define SCU_RAM_PARAM_1__A                                                  0x831FFB
10038 #define SCU_RAM_PARAM_1__W                                                  16
10039 #define SCU_RAM_PARAM_1__M                                                  0xFFFF
10040 #define SCU_RAM_PARAM_1__PRE                                                0x0
10041 #define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED                     0x0
10042 #define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED                   0x4000
10043 #define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED                         0x8000
10044 #define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK                     0xC000
10045 
10046 #define SCU_RAM_PARAM_0__A                                                  0x831FFC
10047 #define SCU_RAM_PARAM_0__W                                                  16
10048 #define SCU_RAM_PARAM_0__M                                                  0xFFFF
10049 #define SCU_RAM_PARAM_0__PRE                                                0x0
10050 #define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD                      0x2
10051 #define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD                       0x103
10052 #define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD                       0x3
10053 #define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD                      0x4
10054 #define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD                       0x9
10055 #define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD                      0x109
10056 #define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD                       0xA
10057 #define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD                      0x40
10058 #define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A                          0x0
10059 #define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B                          0x1
10060 #define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C                          0x2
10061 #define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D                          0x3
10062 #define   SCU_RAM_PARAM_0_RESULT_OK                                         0x0
10063 #define   SCU_RAM_PARAM_0_RESULT_UNKCMD                                     0xFFFF
10064 #define   SCU_RAM_PARAM_0_RESULT_UNKSTD                                     0xFFFE
10065 #define   SCU_RAM_PARAM_0_RESULT_INVPAR                                     0xFFFD
10066 #define   SCU_RAM_PARAM_0_RESULT_SIZE                                       0xFFFC
10067 
10068 #define SCU_RAM_COMMAND__A                                                  0x831FFD
10069 #define SCU_RAM_COMMAND__W                                                  16
10070 #define SCU_RAM_COMMAND__M                                                  0xFFFF
10071 #define SCU_RAM_COMMAND__PRE                                                0x0
10072 #define   SCU_RAM_COMMAND_CMD_DEMOD_RESET                                   0x1
10073 #define   SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV                                 0x2
10074 #define   SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM                               0x3
10075 #define   SCU_RAM_COMMAND_CMD_DEMOD_START                                   0x4
10076 #define   SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK                                0x5
10077 #define   SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM                               0x6
10078 #define   SCU_RAM_COMMAND_CMD_DEMOD_HOLD                                    0x7
10079 #define   SCU_RAM_COMMAND_CMD_DEMOD_RESUME                                  0x8
10080 #define   SCU_RAM_COMMAND_CMD_DEMOD_STOP                                    0x9
10081 #define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE                          0x80
10082 #define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE                        0x81
10083 #define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL                            0x82
10084 #define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR                           0x83
10085 #define   SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE                            0x84
10086 #define   SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE                         0x85
10087 #define   SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS                            0x80
10088 #define   SCU_RAM_COMMAND_CMD_DEBUG_HTOL                                    0x81
10089 #define   SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER                       0x82
10090 #define   SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK                       0x83
10091 #define   SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK                        0x84
10092 #define   SCU_RAM_COMMAND_CMD_ADMIN_NOP                                     0xFF
10093 #define   SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION                             0xFE
10094 #define   SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION                        0xFD
10095 #define   SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS                         0xC0
10096 
10097 #define   SCU_RAM_COMMAND_STANDARD__B                                       8
10098 #define   SCU_RAM_COMMAND_STANDARD__W                                       8
10099 #define   SCU_RAM_COMMAND_STANDARD__M                                       0xFF00
10100 #define   SCU_RAM_COMMAND_STANDARD__PRE                                     0x0
10101 #define     SCU_RAM_COMMAND_STANDARD_ATV                                    0x100
10102 #define     SCU_RAM_COMMAND_STANDARD_QAM                                    0x200
10103 #define     SCU_RAM_COMMAND_STANDARD_VSB                                    0x300
10104 #define     SCU_RAM_COMMAND_STANDARD_OFDM                                   0x400
10105 #define     SCU_RAM_COMMAND_STANDARD_OOB                                    0x8000
10106 #define     SCU_RAM_COMMAND_STANDARD_TOP                                    0xFF00
10107 
10108 #define SCU_RAM_VERSION_HI__A                                               0x831FFE
10109 #define SCU_RAM_VERSION_HI__W                                               16
10110 #define SCU_RAM_VERSION_HI__M                                               0xFFFF
10111 #define SCU_RAM_VERSION_HI__PRE                                             0x0
10112 
10113 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__B                                12
10114 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__W                                4
10115 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__M                                0xF000
10116 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE                              0x0
10117 
10118 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__B                                8
10119 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__W                                4
10120 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__M                                0xF00
10121 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE                              0x0
10122 
10123 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__B                                4
10124 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__W                                4
10125 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__M                                0xF0
10126 #define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE                              0x0
10127 
10128 #define   SCU_RAM_VERSION_HI_VER_MINOR_N1__B                                0
10129 #define   SCU_RAM_VERSION_HI_VER_MINOR_N1__W                                4
10130 #define   SCU_RAM_VERSION_HI_VER_MINOR_N1__M                                0xF
10131 #define   SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE                              0x0
10132 
10133 #define SCU_RAM_VERSION_LO__A                                               0x831FFF
10134 #define SCU_RAM_VERSION_LO__W                                               16
10135 #define SCU_RAM_VERSION_LO__M                                               0xFFFF
10136 #define SCU_RAM_VERSION_LO__PRE                                             0x0
10137 
10138 #define   SCU_RAM_VERSION_LO_VER_PATCH_N4__B                                12
10139 #define   SCU_RAM_VERSION_LO_VER_PATCH_N4__W                                4
10140 #define   SCU_RAM_VERSION_LO_VER_PATCH_N4__M                                0xF000
10141 #define   SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE                              0x0
10142 
10143 #define   SCU_RAM_VERSION_LO_VER_PATCH_N3__B                                8
10144 #define   SCU_RAM_VERSION_LO_VER_PATCH_N3__W                                4
10145 #define   SCU_RAM_VERSION_LO_VER_PATCH_N3__M                                0xF00
10146 #define   SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE                              0x0
10147 
10148 #define   SCU_RAM_VERSION_LO_VER_PATCH_N2__B                                4
10149 #define   SCU_RAM_VERSION_LO_VER_PATCH_N2__W                                4
10150 #define   SCU_RAM_VERSION_LO_VER_PATCH_N2__M                                0xF0
10151 #define   SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE                              0x0
10152 
10153 #define   SCU_RAM_VERSION_LO_VER_PATCH_N1__B                                0
10154 #define   SCU_RAM_VERSION_LO_VER_PATCH_N1__W                                4
10155 #define   SCU_RAM_VERSION_LO_VER_PATCH_N1__M                                0xF
10156 #define   SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE                              0x0
10157 
10158 #define SIO_COMM_EXEC__A                                                    0x400000
10159 #define SIO_COMM_EXEC__W                                                    2
10160 #define SIO_COMM_EXEC__M                                                    0x3
10161 #define SIO_COMM_EXEC__PRE                                                  0x0
10162 #define   SIO_COMM_EXEC_STOP                                                0x0
10163 #define   SIO_COMM_EXEC_ACTIVE                                              0x1
10164 #define   SIO_COMM_EXEC_HOLD                                                0x2
10165 
10166 #define SIO_COMM_STATE__A                                                   0x400001
10167 #define SIO_COMM_STATE__W                                                   16
10168 #define SIO_COMM_STATE__M                                                   0xFFFF
10169 #define SIO_COMM_STATE__PRE                                                 0x0
10170 #define SIO_COMM_MB__A                                                      0x400002
10171 #define SIO_COMM_MB__W                                                      16
10172 #define SIO_COMM_MB__M                                                      0xFFFF
10173 #define SIO_COMM_MB__PRE                                                    0x0
10174 #define SIO_COMM_INT_REQ__A                                                 0x400003
10175 #define SIO_COMM_INT_REQ__W                                                 16
10176 #define SIO_COMM_INT_REQ__M                                                 0xFFFF
10177 #define SIO_COMM_INT_REQ__PRE                                               0x0
10178 
10179 #define   SIO_COMM_INT_REQ_HI_REQ__B                                        0
10180 #define   SIO_COMM_INT_REQ_HI_REQ__W                                        1
10181 #define   SIO_COMM_INT_REQ_HI_REQ__M                                        0x1
10182 #define   SIO_COMM_INT_REQ_HI_REQ__PRE                                      0x0
10183 
10184 #define   SIO_COMM_INT_REQ_SA_REQ__B                                        1
10185 #define   SIO_COMM_INT_REQ_SA_REQ__W                                        1
10186 #define   SIO_COMM_INT_REQ_SA_REQ__M                                        0x2
10187 #define   SIO_COMM_INT_REQ_SA_REQ__PRE                                      0x0
10188 
10189 #define SIO_COMM_INT_STA__A                                                 0x400005
10190 #define SIO_COMM_INT_STA__W                                                 16
10191 #define SIO_COMM_INT_STA__M                                                 0xFFFF
10192 #define SIO_COMM_INT_STA__PRE                                               0x0
10193 #define SIO_COMM_INT_MSK__A                                                 0x400006
10194 #define SIO_COMM_INT_MSK__W                                                 16
10195 #define SIO_COMM_INT_MSK__M                                                 0xFFFF
10196 #define SIO_COMM_INT_MSK__PRE                                               0x0
10197 #define SIO_COMM_INT_STM__A                                                 0x400007
10198 #define SIO_COMM_INT_STM__W                                                 16
10199 #define SIO_COMM_INT_STM__M                                                 0xFFFF
10200 #define SIO_COMM_INT_STM__PRE                                               0x0
10201 
10202 #define SIO_TOP_COMM_EXEC__A                                                0x410000
10203 #define SIO_TOP_COMM_EXEC__W                                                2
10204 #define SIO_TOP_COMM_EXEC__M                                                0x3
10205 #define SIO_TOP_COMM_EXEC__PRE                                              0x0
10206 #define   SIO_TOP_COMM_EXEC_STOP                                            0x0
10207 #define   SIO_TOP_COMM_EXEC_ACTIVE                                          0x1
10208 #define   SIO_TOP_COMM_EXEC_HOLD                                            0x2
10209 
10210 #define SIO_TOP_COMM_KEY__A                                                 0x41000F
10211 #define SIO_TOP_COMM_KEY__W                                                 16
10212 #define SIO_TOP_COMM_KEY__M                                                 0xFFFF
10213 #define SIO_TOP_COMM_KEY__PRE                                               0x0
10214 #define   SIO_TOP_COMM_KEY_KEY                                              0xFABA
10215 
10216 #define SIO_TOP_JTAGID_LO__A                                                0x410012
10217 #define SIO_TOP_JTAGID_LO__W                                                16
10218 #define SIO_TOP_JTAGID_LO__M                                                0xFFFF
10219 #define SIO_TOP_JTAGID_LO__PRE                                              0x0
10220 
10221 #define SIO_TOP_JTAGID_HI__A                                                0x410013
10222 #define SIO_TOP_JTAGID_HI__W                                                16
10223 #define SIO_TOP_JTAGID_HI__M                                                0xFFFF
10224 #define SIO_TOP_JTAGID_HI__PRE                                              0x0
10225 
10226 #define SIO_HI_RA_RAM_S0_FLG_SMM__A                                         0x420010
10227 #define SIO_HI_RA_RAM_S0_FLG_SMM__W                                         1
10228 #define SIO_HI_RA_RAM_S0_FLG_SMM__M                                         0x1
10229 #define SIO_HI_RA_RAM_S0_FLG_SMM__PRE                                       0x0
10230 
10231 #define SIO_HI_RA_RAM_S0_DEV_ID__A                                          0x420011
10232 #define SIO_HI_RA_RAM_S0_DEV_ID__W                                          7
10233 #define SIO_HI_RA_RAM_S0_DEV_ID__M                                          0x7F
10234 #define SIO_HI_RA_RAM_S0_DEV_ID__PRE                                        0x52
10235 
10236 #define SIO_HI_RA_RAM_S0_FLG_CRC__A                                         0x420012
10237 #define SIO_HI_RA_RAM_S0_FLG_CRC__W                                         1
10238 #define SIO_HI_RA_RAM_S0_FLG_CRC__M                                         0x1
10239 #define SIO_HI_RA_RAM_S0_FLG_CRC__PRE                                       0x0
10240 #define SIO_HI_RA_RAM_S0_FLG_ACC__A                                         0x420013
10241 #define SIO_HI_RA_RAM_S0_FLG_ACC__W                                         4
10242 #define SIO_HI_RA_RAM_S0_FLG_ACC__M                                         0xF
10243 #define SIO_HI_RA_RAM_S0_FLG_ACC__PRE                                       0x0
10244 
10245 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B                                0
10246 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W                                2
10247 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M                                0x3
10248 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE                              0x0
10249 
10250 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B                            2
10251 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W                            1
10252 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M                            0x4
10253 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE                          0x0
10254 
10255 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B                            3
10256 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W                            1
10257 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M                            0x8
10258 #define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE                          0x0
10259 
10260 #define SIO_HI_RA_RAM_S0_STATE__A                                           0x420014
10261 #define SIO_HI_RA_RAM_S0_STATE__W                                           1
10262 #define SIO_HI_RA_RAM_S0_STATE__M                                           0x1
10263 #define SIO_HI_RA_RAM_S0_STATE__PRE                                         0x0
10264 
10265 #define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B                              0
10266 #define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W                              1
10267 #define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M                              0x1
10268 #define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE                            0x0
10269 
10270 #define SIO_HI_RA_RAM_S0_BLK_BNK__A                                         0x420015
10271 #define SIO_HI_RA_RAM_S0_BLK_BNK__W                                         12
10272 #define SIO_HI_RA_RAM_S0_BLK_BNK__M                                         0xFFF
10273 #define SIO_HI_RA_RAM_S0_BLK_BNK__PRE                                       0x82
10274 
10275 #define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B                            0
10276 #define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W                            6
10277 #define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M                            0x3F
10278 #define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE                          0x2
10279 
10280 #define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B                            6
10281 #define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W                            6
10282 #define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M                            0xFC0
10283 #define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE                          0x80
10284 
10285 #define SIO_HI_RA_RAM_S0_ADDR__A                                            0x420016
10286 #define SIO_HI_RA_RAM_S0_ADDR__W                                            16
10287 #define SIO_HI_RA_RAM_S0_ADDR__M                                            0xFFFF
10288 #define SIO_HI_RA_RAM_S0_ADDR__PRE                                          0x0
10289 
10290 #define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B                              0
10291 #define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W                              16
10292 #define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M                              0xFFFF
10293 #define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE                            0x0
10294 
10295 #define SIO_HI_RA_RAM_S0_CRC__A                                             0x420017
10296 #define SIO_HI_RA_RAM_S0_CRC__W                                             16
10297 #define SIO_HI_RA_RAM_S0_CRC__M                                             0xFFFF
10298 #define SIO_HI_RA_RAM_S0_CRC__PRE                                           0x0
10299 
10300 #define SIO_HI_RA_RAM_S0_BUFFER__A                                          0x420018
10301 #define SIO_HI_RA_RAM_S0_BUFFER__W                                          16
10302 #define SIO_HI_RA_RAM_S0_BUFFER__M                                          0xFFFF
10303 #define SIO_HI_RA_RAM_S0_BUFFER__PRE                                        0x0
10304 
10305 #define SIO_HI_RA_RAM_S0_RMWBUF__A                                          0x420019
10306 #define SIO_HI_RA_RAM_S0_RMWBUF__W                                          16
10307 #define SIO_HI_RA_RAM_S0_RMWBUF__M                                          0xFFFF
10308 #define SIO_HI_RA_RAM_S0_RMWBUF__PRE                                        0x0
10309 
10310 #define SIO_HI_RA_RAM_S0_FLG_VB__A                                          0x42001A
10311 #define SIO_HI_RA_RAM_S0_FLG_VB__W                                          1
10312 #define SIO_HI_RA_RAM_S0_FLG_VB__M                                          0x1
10313 #define SIO_HI_RA_RAM_S0_FLG_VB__PRE                                        0x0
10314 
10315 #define SIO_HI_RA_RAM_S0_TEMP0__A                                           0x42001B
10316 #define SIO_HI_RA_RAM_S0_TEMP0__W                                           16
10317 #define SIO_HI_RA_RAM_S0_TEMP0__M                                           0xFFFF
10318 #define SIO_HI_RA_RAM_S0_TEMP0__PRE                                         0x0
10319 
10320 #define SIO_HI_RA_RAM_S0_TEMP1__A                                           0x42001C
10321 #define SIO_HI_RA_RAM_S0_TEMP1__W                                           16
10322 #define SIO_HI_RA_RAM_S0_TEMP1__M                                           0xFFFF
10323 #define SIO_HI_RA_RAM_S0_TEMP1__PRE                                         0x0
10324 
10325 #define SIO_HI_RA_RAM_S0_OFFSET__A                                          0x42001D
10326 #define SIO_HI_RA_RAM_S0_OFFSET__W                                          16
10327 #define SIO_HI_RA_RAM_S0_OFFSET__M                                          0xFFFF
10328 #define SIO_HI_RA_RAM_S0_OFFSET__PRE                                        0x0
10329 
10330 #define SIO_HI_RA_RAM_S1_FLG_SMM__A                                         0x420020
10331 #define SIO_HI_RA_RAM_S1_FLG_SMM__W                                         1
10332 #define SIO_HI_RA_RAM_S1_FLG_SMM__M                                         0x1
10333 #define SIO_HI_RA_RAM_S1_FLG_SMM__PRE                                       0x0
10334 
10335 #define SIO_HI_RA_RAM_S1_DEV_ID__A                                          0x420021
10336 #define SIO_HI_RA_RAM_S1_DEV_ID__W                                          7
10337 #define SIO_HI_RA_RAM_S1_DEV_ID__M                                          0x7F
10338 #define SIO_HI_RA_RAM_S1_DEV_ID__PRE                                        0x52
10339 
10340 #define SIO_HI_RA_RAM_S1_FLG_CRC__A                                         0x420022
10341 #define SIO_HI_RA_RAM_S1_FLG_CRC__W                                         1
10342 #define SIO_HI_RA_RAM_S1_FLG_CRC__M                                         0x1
10343 #define SIO_HI_RA_RAM_S1_FLG_CRC__PRE                                       0x0
10344 #define SIO_HI_RA_RAM_S1_FLG_ACC__A                                         0x420023
10345 #define SIO_HI_RA_RAM_S1_FLG_ACC__W                                         4
10346 #define SIO_HI_RA_RAM_S1_FLG_ACC__M                                         0xF
10347 #define SIO_HI_RA_RAM_S1_FLG_ACC__PRE                                       0x0
10348 
10349 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B                                0
10350 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W                                2
10351 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M                                0x3
10352 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE                              0x0
10353 
10354 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B                            2
10355 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W                            1
10356 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M                            0x4
10357 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE                          0x0
10358 
10359 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B                            3
10360 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W                            1
10361 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M                            0x8
10362 #define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE                          0x0
10363 
10364 #define SIO_HI_RA_RAM_S1_STATE__A                                           0x420024
10365 #define SIO_HI_RA_RAM_S1_STATE__W                                           1
10366 #define SIO_HI_RA_RAM_S1_STATE__M                                           0x1
10367 #define SIO_HI_RA_RAM_S1_STATE__PRE                                         0x0
10368 
10369 #define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B                              0
10370 #define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W                              1
10371 #define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M                              0x1
10372 #define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE                            0x0
10373 
10374 #define SIO_HI_RA_RAM_S1_BLK_BNK__A                                         0x420025
10375 #define SIO_HI_RA_RAM_S1_BLK_BNK__W                                         12
10376 #define SIO_HI_RA_RAM_S1_BLK_BNK__M                                         0xFFF
10377 #define SIO_HI_RA_RAM_S1_BLK_BNK__PRE                                       0x82
10378 
10379 #define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B                            0
10380 #define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W                            6
10381 #define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M                            0x3F
10382 #define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE                          0x2
10383 
10384 #define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B                            6
10385 #define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W                            6
10386 #define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M                            0xFC0
10387 #define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE                          0x80
10388 
10389 #define SIO_HI_RA_RAM_S1_ADDR__A                                            0x420026
10390 #define SIO_HI_RA_RAM_S1_ADDR__W                                            16
10391 #define SIO_HI_RA_RAM_S1_ADDR__M                                            0xFFFF
10392 #define SIO_HI_RA_RAM_S1_ADDR__PRE                                          0x0
10393 
10394 #define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B                              0
10395 #define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W                              16
10396 #define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M                              0xFFFF
10397 #define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE                            0x0
10398 
10399 #define SIO_HI_RA_RAM_S1_CRC__A                                             0x420027
10400 #define SIO_HI_RA_RAM_S1_CRC__W                                             16
10401 #define SIO_HI_RA_RAM_S1_CRC__M                                             0xFFFF
10402 #define SIO_HI_RA_RAM_S1_CRC__PRE                                           0x0
10403 
10404 #define SIO_HI_RA_RAM_S1_BUFFER__A                                          0x420028
10405 #define SIO_HI_RA_RAM_S1_BUFFER__W                                          16
10406 #define SIO_HI_RA_RAM_S1_BUFFER__M                                          0xFFFF
10407 #define SIO_HI_RA_RAM_S1_BUFFER__PRE                                        0x0
10408 
10409 #define SIO_HI_RA_RAM_S1_RMWBUF__A                                          0x420029
10410 #define SIO_HI_RA_RAM_S1_RMWBUF__W                                          16
10411 #define SIO_HI_RA_RAM_S1_RMWBUF__M                                          0xFFFF
10412 #define SIO_HI_RA_RAM_S1_RMWBUF__PRE                                        0x0
10413 
10414 #define SIO_HI_RA_RAM_S1_FLG_VB__A                                          0x42002A
10415 #define SIO_HI_RA_RAM_S1_FLG_VB__W                                          1
10416 #define SIO_HI_RA_RAM_S1_FLG_VB__M                                          0x1
10417 #define SIO_HI_RA_RAM_S1_FLG_VB__PRE                                        0x0
10418 
10419 #define SIO_HI_RA_RAM_S1_TEMP0__A                                           0x42002B
10420 #define SIO_HI_RA_RAM_S1_TEMP0__W                                           16
10421 #define SIO_HI_RA_RAM_S1_TEMP0__M                                           0xFFFF
10422 #define SIO_HI_RA_RAM_S1_TEMP0__PRE                                         0x0
10423 
10424 #define SIO_HI_RA_RAM_S1_TEMP1__A                                           0x42002C
10425 #define SIO_HI_RA_RAM_S1_TEMP1__W                                           16
10426 #define SIO_HI_RA_RAM_S1_TEMP1__M                                           0xFFFF
10427 #define SIO_HI_RA_RAM_S1_TEMP1__PRE                                         0x0
10428 
10429 #define SIO_HI_RA_RAM_S1_OFFSET__A                                          0x42002D
10430 #define SIO_HI_RA_RAM_S1_OFFSET__W                                          16
10431 #define SIO_HI_RA_RAM_S1_OFFSET__M                                          0xFFFF
10432 #define SIO_HI_RA_RAM_S1_OFFSET__PRE                                        0x0
10433 #define SIO_HI_RA_RAM_SEMA__A                                               0x420030
10434 #define SIO_HI_RA_RAM_SEMA__W                                               1
10435 #define SIO_HI_RA_RAM_SEMA__M                                               0x1
10436 #define SIO_HI_RA_RAM_SEMA__PRE                                             0x0
10437 #define   SIO_HI_RA_RAM_SEMA_FREE                                           0x0
10438 #define   SIO_HI_RA_RAM_SEMA_BUSY                                           0x1
10439 
10440 #define SIO_HI_RA_RAM_RES__A                                                0x420031
10441 #define SIO_HI_RA_RAM_RES__W                                                3
10442 #define SIO_HI_RA_RAM_RES__M                                                0x7
10443 #define SIO_HI_RA_RAM_RES__PRE                                              0x0
10444 #define   SIO_HI_RA_RAM_RES_OK                                              0x0
10445 #define   SIO_HI_RA_RAM_RES_ERROR                                           0x1
10446 #define   SIO_HI_RA_RAM_RES_I2C_START_FOUND                                 0x1
10447 #define   SIO_HI_RA_RAM_RES_I2C_STOP_FOUND                                  0x2
10448 #define   SIO_HI_RA_RAM_RES_I2C_ARB_LOST                                    0x3
10449 #define   SIO_HI_RA_RAM_RES_I2C_ERROR                                       0x4
10450 
10451 #define SIO_HI_RA_RAM_CMD__A                                                0x420032
10452 #define SIO_HI_RA_RAM_CMD__W                                                4
10453 #define SIO_HI_RA_RAM_CMD__M                                                0xF
10454 #define SIO_HI_RA_RAM_CMD__PRE                                              0x0
10455 #define   SIO_HI_RA_RAM_CMD_NULL                                            0x0
10456 #define   SIO_HI_RA_RAM_CMD_UIO                                             0x1
10457 #define   SIO_HI_RA_RAM_CMD_RESET                                           0x2
10458 #define   SIO_HI_RA_RAM_CMD_CONFIG                                          0x3
10459 #define   SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER                               0x4
10460 #define   SIO_HI_RA_RAM_CMD_I2C_TRANSMIT                                    0x5
10461 #define   SIO_HI_RA_RAM_CMD_EXEC                                            0x6
10462 #define   SIO_HI_RA_RAM_CMD_BRDCTRL                                         0x7
10463 #define   SIO_HI_RA_RAM_CMD_ATOMIC_COPY                                     0x8
10464 
10465 #define SIO_HI_RA_RAM_PAR_1__A                                              0x420033
10466 #define SIO_HI_RA_RAM_PAR_1__W                                              16
10467 #define SIO_HI_RA_RAM_PAR_1__M                                              0xFFFF
10468 #define SIO_HI_RA_RAM_PAR_1__PRE                                            0x0
10469 #define   SIO_HI_RA_RAM_PAR_1_PAR1__B                                       0
10470 #define   SIO_HI_RA_RAM_PAR_1_PAR1__W                                       16
10471 #define   SIO_HI_RA_RAM_PAR_1_PAR1__M                                       0xFFFF
10472 #define   SIO_HI_RA_RAM_PAR_1_PAR1__PRE                                     0x0
10473 #define     SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY                                0x3945
10474 
10475 #define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B                                0
10476 #define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W                                6
10477 #define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M                                0x3F
10478 #define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE                              0x0
10479 
10480 #define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B                                6
10481 #define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W                                6
10482 #define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M                                0xFC0
10483 #define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE                              0x0
10484 
10485 #define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B                                 0
10486 #define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W                                 1
10487 #define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M                                 0x1
10488 #define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE                               0x0
10489 
10490 #define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B                                  1
10491 #define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W                                  1
10492 #define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M                                  0x2
10493 #define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE                                0x0
10494 #define     SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE                           0x0
10495 #define     SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE                            0x2
10496 
10497 #define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B                                  0
10498 #define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W                                  10
10499 #define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M                                  0x3FF
10500 #define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE                                0x0
10501 
10502 #define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B                                0
10503 #define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W                                6
10504 #define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M                                0x3F
10505 #define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE                              0x0
10506 
10507 #define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B                                6
10508 #define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W                                6
10509 #define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M                                0xFC0
10510 #define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE                              0x0
10511 
10512 #define SIO_HI_RA_RAM_PAR_2__A                                              0x420034
10513 #define SIO_HI_RA_RAM_PAR_2__W                                              16
10514 #define SIO_HI_RA_RAM_PAR_2__M                                              0xFFFF
10515 #define SIO_HI_RA_RAM_PAR_2__PRE                                            0x0
10516 #define   SIO_HI_RA_RAM_PAR_2_PAR2__B                                       0
10517 #define   SIO_HI_RA_RAM_PAR_2_PAR2__W                                       16
10518 #define   SIO_HI_RA_RAM_PAR_2_PAR2__M                                       0xFFFF
10519 #define   SIO_HI_RA_RAM_PAR_2_PAR2__PRE                                     0x0
10520 
10521 #define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__B                                    0
10522 #define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__W                                    7
10523 #define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__M                                    0x7F
10524 #define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE                                  0x25
10525 
10526 #define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B                                0
10527 #define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W                                16
10528 #define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M                                0xFFFF
10529 #define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE                              0x0
10530 
10531 #define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B                                  0
10532 #define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W                                  16
10533 #define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M                                  0xFFFF
10534 #define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE                                0x0
10535 
10536 #define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__B                                    2
10537 #define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__W                                    1
10538 #define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__M                                    0x4
10539 #define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE                                  0x0
10540 #define     SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN                                0x0
10541 #define     SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED                              0x4
10542 
10543 #define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B                                0
10544 #define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W                                16
10545 #define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M                                0xFFFF
10546 #define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE                              0x0
10547 
10548 #define SIO_HI_RA_RAM_PAR_3__A                                              0x420035
10549 #define SIO_HI_RA_RAM_PAR_3__W                                              16
10550 #define SIO_HI_RA_RAM_PAR_3__M                                              0xFFFF
10551 #define SIO_HI_RA_RAM_PAR_3__PRE                                            0x0
10552 #define   SIO_HI_RA_RAM_PAR_3_PAR3__B                                       0
10553 #define   SIO_HI_RA_RAM_PAR_3_PAR3__W                                       16
10554 #define   SIO_HI_RA_RAM_PAR_3_PAR3__M                                       0xFFFF
10555 #define   SIO_HI_RA_RAM_PAR_3_PAR3__PRE                                     0x0
10556 
10557 #define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B                                0
10558 #define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W                                7
10559 #define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M                                0x7F
10560 #define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE                              0x3F
10561 
10562 #define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B                                7
10563 #define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W                                7
10564 #define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M                                0x3F80
10565 #define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE                              0x1F80
10566 
10567 #define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__B                                    0
10568 #define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__W                                    16
10569 #define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__M                                    0xFFFF
10570 #define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE                                  0x0
10571 
10572 #define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__B                                    0
10573 #define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__W                                    3
10574 #define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__M                                    0x7
10575 #define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE                                  0x0
10576 
10577 #define   SIO_HI_RA_RAM_PAR_3_ACP_RW__B                                     3
10578 #define   SIO_HI_RA_RAM_PAR_3_ACP_RW__W                                     1
10579 #define   SIO_HI_RA_RAM_PAR_3_ACP_RW__M                                     0x8
10580 #define   SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE                                   0x0
10581 #define     SIO_HI_RA_RAM_PAR_3_ACP_RW_READ                                 0x0
10582 #define     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE                                0x8
10583 
10584 #define SIO_HI_RA_RAM_PAR_4__A                                              0x420036
10585 #define SIO_HI_RA_RAM_PAR_4__W                                              16
10586 #define SIO_HI_RA_RAM_PAR_4__M                                              0xFFFF
10587 #define SIO_HI_RA_RAM_PAR_4__PRE                                            0x0
10588 #define   SIO_HI_RA_RAM_PAR_4_PAR4__B                                       0
10589 #define   SIO_HI_RA_RAM_PAR_4_PAR4__W                                       16
10590 #define   SIO_HI_RA_RAM_PAR_4_PAR4__M                                       0xFFFF
10591 #define   SIO_HI_RA_RAM_PAR_4_PAR4__PRE                                     0x0
10592 
10593 #define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__B                                    0
10594 #define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__W                                    8
10595 #define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__M                                    0xFF
10596 #define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE                                  0xC1
10597 
10598 #define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B                                0
10599 #define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W                                6
10600 #define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M                                0x3F
10601 #define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE                              0x0
10602 
10603 #define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B                                6
10604 #define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W                                6
10605 #define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M                                0xFC0
10606 #define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE                              0x0
10607 
10608 #define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B                                0
10609 #define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W                                6
10610 #define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M                                0x3F
10611 #define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE                              0x0
10612 
10613 #define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B                                6
10614 #define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W                                6
10615 #define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M                                0xFC0
10616 #define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE                              0x0
10617 
10618 #define SIO_HI_RA_RAM_PAR_5__A                                              0x420037
10619 #define SIO_HI_RA_RAM_PAR_5__W                                              16
10620 #define SIO_HI_RA_RAM_PAR_5__M                                              0xFFFF
10621 #define SIO_HI_RA_RAM_PAR_5__PRE                                            0x0
10622 #define   SIO_HI_RA_RAM_PAR_5_PAR5__B                                       0
10623 #define   SIO_HI_RA_RAM_PAR_5_PAR5__W                                       16
10624 #define   SIO_HI_RA_RAM_PAR_5_PAR5__M                                       0xFFFF
10625 #define   SIO_HI_RA_RAM_PAR_5_PAR5__PRE                                     0x0
10626 
10627 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B                                   0
10628 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W                                   1
10629 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M                                   0x1
10630 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE                                 0x0
10631 #define     SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE                           0x0
10632 #define     SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE                              0x1
10633 
10634 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B                                   1
10635 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W                                   1
10636 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M                                   0x2
10637 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE                                 0x0
10638 #define     SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE                           0x0
10639 #define     SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE                              0x2
10640 
10641 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B                                  3
10642 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W                                  1
10643 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M                                  0x8
10644 #define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE                                0x0
10645 #define     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE                             0x0
10646 #define     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ                               0x8
10647 
10648 #define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B                                  5
10649 #define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W                                  1
10650 #define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M                                  0x20
10651 #define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE                                0x0
10652 #define     SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE                           0x0
10653 #define     SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE                            0x20
10654 
10655 #define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B                                0
10656 #define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W                                16
10657 #define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M                                0xFFFF
10658 #define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE                              0x0
10659 
10660 #define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B                                0
10661 #define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W                                16
10662 #define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M                                0xFFFF
10663 #define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE                              0x0
10664 
10665 #define SIO_HI_RA_RAM_PAR_6__A                                              0x420038
10666 #define SIO_HI_RA_RAM_PAR_6__W                                              16
10667 #define SIO_HI_RA_RAM_PAR_6__M                                              0xFFFF
10668 #define SIO_HI_RA_RAM_PAR_6__PRE                                            0x95FF
10669 #define   SIO_HI_RA_RAM_PAR_6_PAR6__B                                       0
10670 #define   SIO_HI_RA_RAM_PAR_6_PAR6__W                                       16
10671 #define   SIO_HI_RA_RAM_PAR_6_PAR6__M                                       0xFFFF
10672 #define   SIO_HI_RA_RAM_PAR_6_PAR6__PRE                                     0x0
10673 
10674 #define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__B                                    0
10675 #define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__W                                    8
10676 #define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__M                                    0xFF
10677 #define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE                                  0xFF
10678 
10679 #define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__B                                    8
10680 #define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__W                                    8
10681 #define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__M                                    0xFF00
10682 #define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE                                  0x9500
10683 
10684 #define SIO_HI_RA_RAM_AB_TEMP__A                                            0x42006E
10685 #define SIO_HI_RA_RAM_AB_TEMP__W                                            16
10686 #define SIO_HI_RA_RAM_AB_TEMP__M                                            0xFFFF
10687 #define SIO_HI_RA_RAM_AB_TEMP__PRE                                          0x0
10688 
10689 #define SIO_HI_RA_RAM_I2C_CTL__A                                            0x42006F
10690 #define SIO_HI_RA_RAM_I2C_CTL__W                                            16
10691 #define SIO_HI_RA_RAM_I2C_CTL__M                                            0xFFFF
10692 #define SIO_HI_RA_RAM_I2C_CTL__PRE                                          0x0
10693 
10694 #define SIO_HI_RA_RAM_VB_ENTRY0__A                                          0x420070
10695 #define SIO_HI_RA_RAM_VB_ENTRY0__W                                          16
10696 #define SIO_HI_RA_RAM_VB_ENTRY0__M                                          0xFFFF
10697 #define SIO_HI_RA_RAM_VB_ENTRY0__PRE                                        0x0
10698 
10699 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B                             0
10700 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W                             4
10701 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M                             0xF
10702 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE                           0x0
10703 
10704 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B                             4
10705 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W                             4
10706 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M                             0xF0
10707 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE                           0x0
10708 
10709 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B                            8
10710 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W                            4
10711 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M                            0xF00
10712 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE                          0x0
10713 
10714 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B                            12
10715 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W                            4
10716 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M                            0xF000
10717 #define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE                          0x0
10718 
10719 #define SIO_HI_RA_RAM_VB_OFFSET0__A                                         0x420071
10720 #define SIO_HI_RA_RAM_VB_OFFSET0__W                                         16
10721 #define SIO_HI_RA_RAM_VB_OFFSET0__M                                         0xFFFF
10722 #define SIO_HI_RA_RAM_VB_OFFSET0__PRE                                       0x0
10723 
10724 #define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B                           0
10725 #define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W                           16
10726 #define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M                           0xFFFF
10727 #define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE                         0x0
10728 
10729 #define SIO_HI_RA_RAM_VB_ENTRY1__A                                          0x420072
10730 #define SIO_HI_RA_RAM_VB_ENTRY1__W                                          16
10731 #define SIO_HI_RA_RAM_VB_ENTRY1__M                                          0xFFFF
10732 #define SIO_HI_RA_RAM_VB_ENTRY1__PRE                                        0x0
10733 #define SIO_HI_RA_RAM_VB_OFFSET1__A                                         0x420073
10734 #define SIO_HI_RA_RAM_VB_OFFSET1__W                                         16
10735 #define SIO_HI_RA_RAM_VB_OFFSET1__M                                         0xFFFF
10736 #define SIO_HI_RA_RAM_VB_OFFSET1__PRE                                       0x0
10737 
10738 #define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B                            0
10739 #define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W                            16
10740 #define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M                            0xFFFF
10741 #define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE                          0x0
10742 
10743 #define SIO_HI_RA_RAM_VB_ENTRY2__A                                          0x420074
10744 #define SIO_HI_RA_RAM_VB_ENTRY2__W                                          16
10745 #define SIO_HI_RA_RAM_VB_ENTRY2__M                                          0xFFFF
10746 #define SIO_HI_RA_RAM_VB_ENTRY2__PRE                                        0x0
10747 #define SIO_HI_RA_RAM_VB_OFFSET2__A                                         0x420075
10748 #define SIO_HI_RA_RAM_VB_OFFSET2__W                                         16
10749 #define SIO_HI_RA_RAM_VB_OFFSET2__M                                         0xFFFF
10750 #define SIO_HI_RA_RAM_VB_OFFSET2__PRE                                       0x0
10751 
10752 #define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B                            0
10753 #define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W                            16
10754 #define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M                            0xFFFF
10755 #define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE                          0x0
10756 
10757 #define SIO_HI_RA_RAM_VB_ENTRY3__A                                          0x420076
10758 #define SIO_HI_RA_RAM_VB_ENTRY3__W                                          16
10759 #define SIO_HI_RA_RAM_VB_ENTRY3__M                                          0xFFFF
10760 #define SIO_HI_RA_RAM_VB_ENTRY3__PRE                                        0x0
10761 #define SIO_HI_RA_RAM_VB_OFFSET3__A                                         0x420077
10762 #define SIO_HI_RA_RAM_VB_OFFSET3__W                                         16
10763 #define SIO_HI_RA_RAM_VB_OFFSET3__M                                         0xFFFF
10764 #define SIO_HI_RA_RAM_VB_OFFSET3__PRE                                       0x0
10765 
10766 #define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B                            0
10767 #define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W                            16
10768 #define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M                            0xFFFF
10769 #define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE                          0x0
10770 
10771 #define SIO_HI_RA_RAM_VB_ENTRY4__A                                          0x420078
10772 #define SIO_HI_RA_RAM_VB_ENTRY4__W                                          16
10773 #define SIO_HI_RA_RAM_VB_ENTRY4__M                                          0xFFFF
10774 #define SIO_HI_RA_RAM_VB_ENTRY4__PRE                                        0x0
10775 #define SIO_HI_RA_RAM_VB_OFFSET4__A                                         0x420079
10776 #define SIO_HI_RA_RAM_VB_OFFSET4__W                                         16
10777 #define SIO_HI_RA_RAM_VB_OFFSET4__M                                         0xFFFF
10778 #define SIO_HI_RA_RAM_VB_OFFSET4__PRE                                       0x0
10779 
10780 #define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B                            0
10781 #define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W                            16
10782 #define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M                            0xFFFF
10783 #define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE                          0x0
10784 
10785 #define SIO_HI_RA_RAM_VB_ENTRY5__A                                          0x42007A
10786 #define SIO_HI_RA_RAM_VB_ENTRY5__W                                          16
10787 #define SIO_HI_RA_RAM_VB_ENTRY5__M                                          0xFFFF
10788 #define SIO_HI_RA_RAM_VB_ENTRY5__PRE                                        0x0
10789 #define SIO_HI_RA_RAM_VB_OFFSET5__A                                         0x42007B
10790 #define SIO_HI_RA_RAM_VB_OFFSET5__W                                         16
10791 #define SIO_HI_RA_RAM_VB_OFFSET5__M                                         0xFFFF
10792 #define SIO_HI_RA_RAM_VB_OFFSET5__PRE                                       0x0
10793 
10794 #define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B                            0
10795 #define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W                            16
10796 #define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M                            0xFFFF
10797 #define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE                          0x0
10798 
10799 #define SIO_HI_RA_RAM_VB_ENTRY6__A                                          0x42007C
10800 #define SIO_HI_RA_RAM_VB_ENTRY6__W                                          16
10801 #define SIO_HI_RA_RAM_VB_ENTRY6__M                                          0xFFFF
10802 #define SIO_HI_RA_RAM_VB_ENTRY6__PRE                                        0x0
10803 #define SIO_HI_RA_RAM_VB_OFFSET6__A                                         0x42007D
10804 #define SIO_HI_RA_RAM_VB_OFFSET6__W                                         16
10805 #define SIO_HI_RA_RAM_VB_OFFSET6__M                                         0xFFFF
10806 #define SIO_HI_RA_RAM_VB_OFFSET6__PRE                                       0x0
10807 
10808 #define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B                            0
10809 #define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W                            16
10810 #define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M                            0xFFFF
10811 #define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE                          0x0
10812 
10813 #define SIO_HI_RA_RAM_VB_ENTRY7__A                                          0x42007E
10814 #define SIO_HI_RA_RAM_VB_ENTRY7__W                                          16
10815 #define SIO_HI_RA_RAM_VB_ENTRY7__M                                          0xFFFF
10816 #define SIO_HI_RA_RAM_VB_ENTRY7__PRE                                        0x0
10817 #define SIO_HI_RA_RAM_VB_OFFSET7__A                                         0x42007F
10818 #define SIO_HI_RA_RAM_VB_OFFSET7__W                                         16
10819 #define SIO_HI_RA_RAM_VB_OFFSET7__M                                         0xFFFF
10820 #define SIO_HI_RA_RAM_VB_OFFSET7__PRE                                       0x0
10821 
10822 #define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B                            0
10823 #define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W                            16
10824 #define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M                            0xFFFF
10825 #define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE                          0x0
10826 
10827 #define SIO_HI_IF_RAM_TRP_BPT_0__A                                          0x430000
10828 #define SIO_HI_IF_RAM_TRP_BPT_0__W                                          12
10829 #define SIO_HI_IF_RAM_TRP_BPT_0__M                                          0xFFF
10830 #define SIO_HI_IF_RAM_TRP_BPT_0__PRE                                        0x0
10831 #define SIO_HI_IF_RAM_TRP_BPT_1__A                                          0x430001
10832 #define SIO_HI_IF_RAM_TRP_BPT_1__W                                          12
10833 #define SIO_HI_IF_RAM_TRP_BPT_1__M                                          0xFFF
10834 #define SIO_HI_IF_RAM_TRP_BPT_1__PRE                                        0x0
10835 #define SIO_HI_IF_RAM_TRP_STK_0__A                                          0x430002
10836 #define SIO_HI_IF_RAM_TRP_STK_0__W                                          12
10837 #define SIO_HI_IF_RAM_TRP_STK_0__M                                          0xFFF
10838 #define SIO_HI_IF_RAM_TRP_STK_0__PRE                                        0x0
10839 #define SIO_HI_IF_RAM_TRP_STK_1__A                                          0x430003
10840 #define SIO_HI_IF_RAM_TRP_STK_1__W                                          12
10841 #define SIO_HI_IF_RAM_TRP_STK_1__M                                          0xFFF
10842 #define SIO_HI_IF_RAM_TRP_STK_1__PRE                                        0x0
10843 #define SIO_HI_IF_RAM_FUN_BASE__A                                           0x430300
10844 #define SIO_HI_IF_RAM_FUN_BASE__W                                           12
10845 #define SIO_HI_IF_RAM_FUN_BASE__M                                           0xFFF
10846 #define SIO_HI_IF_RAM_FUN_BASE__PRE                                         0x0
10847 
10848 #define SIO_HI_IF_COMM_EXEC__A                                              0x440000
10849 #define SIO_HI_IF_COMM_EXEC__W                                              2
10850 #define SIO_HI_IF_COMM_EXEC__M                                              0x3
10851 #define SIO_HI_IF_COMM_EXEC__PRE                                            0x0
10852 #define   SIO_HI_IF_COMM_EXEC_STOP                                          0x0
10853 #define   SIO_HI_IF_COMM_EXEC_ACTIVE                                        0x1
10854 #define   SIO_HI_IF_COMM_EXEC_HOLD                                          0x2
10855 #define   SIO_HI_IF_COMM_EXEC_STEP                                          0x3
10856 
10857 #define SIO_HI_IF_COMM_STATE__A                                             0x440001
10858 #define SIO_HI_IF_COMM_STATE__W                                             10
10859 #define SIO_HI_IF_COMM_STATE__M                                             0x3FF
10860 #define SIO_HI_IF_COMM_STATE__PRE                                           0x0
10861 #define SIO_HI_IF_COMM_INT_REQ__A                                           0x440003
10862 #define SIO_HI_IF_COMM_INT_REQ__W                                           1
10863 #define SIO_HI_IF_COMM_INT_REQ__M                                           0x1
10864 #define SIO_HI_IF_COMM_INT_REQ__PRE                                         0x0
10865 #define SIO_HI_IF_COMM_INT_STA__A                                           0x440005
10866 #define SIO_HI_IF_COMM_INT_STA__W                                           1
10867 #define SIO_HI_IF_COMM_INT_STA__M                                           0x1
10868 #define SIO_HI_IF_COMM_INT_STA__PRE                                         0x0
10869 #define   SIO_HI_IF_COMM_INT_STA_STAT__B                                    0
10870 #define   SIO_HI_IF_COMM_INT_STA_STAT__W                                    1
10871 #define   SIO_HI_IF_COMM_INT_STA_STAT__M                                    0x1
10872 #define   SIO_HI_IF_COMM_INT_STA_STAT__PRE                                  0x0
10873 
10874 #define SIO_HI_IF_COMM_INT_MSK__A                                           0x440006
10875 #define SIO_HI_IF_COMM_INT_MSK__W                                           1
10876 #define SIO_HI_IF_COMM_INT_MSK__M                                           0x1
10877 #define SIO_HI_IF_COMM_INT_MSK__PRE                                         0x0
10878 #define   SIO_HI_IF_COMM_INT_MSK_STAT__B                                    0
10879 #define   SIO_HI_IF_COMM_INT_MSK_STAT__W                                    1
10880 #define   SIO_HI_IF_COMM_INT_MSK_STAT__M                                    0x1
10881 #define   SIO_HI_IF_COMM_INT_MSK_STAT__PRE                                  0x0
10882 
10883 #define SIO_HI_IF_COMM_INT_STM__A                                           0x440007
10884 #define SIO_HI_IF_COMM_INT_STM__W                                           1
10885 #define SIO_HI_IF_COMM_INT_STM__M                                           0x1
10886 #define SIO_HI_IF_COMM_INT_STM__PRE                                         0x0
10887 #define   SIO_HI_IF_COMM_INT_STM_STAT__B                                    0
10888 #define   SIO_HI_IF_COMM_INT_STM_STAT__W                                    1
10889 #define   SIO_HI_IF_COMM_INT_STM_STAT__M                                    0x1
10890 #define   SIO_HI_IF_COMM_INT_STM_STAT__PRE                                  0x0
10891 
10892 #define SIO_HI_IF_STK_0__A                                                  0x440010
10893 #define SIO_HI_IF_STK_0__W                                                  10
10894 #define SIO_HI_IF_STK_0__M                                                  0x3FF
10895 #define SIO_HI_IF_STK_0__PRE                                                0x2
10896 
10897 #define   SIO_HI_IF_STK_0_ADDR__B                                           0
10898 #define   SIO_HI_IF_STK_0_ADDR__W                                           10
10899 #define   SIO_HI_IF_STK_0_ADDR__M                                           0x3FF
10900 #define   SIO_HI_IF_STK_0_ADDR__PRE                                         0x2
10901 
10902 #define SIO_HI_IF_STK_1__A                                                  0x440011
10903 #define SIO_HI_IF_STK_1__W                                                  10
10904 #define SIO_HI_IF_STK_1__M                                                  0x3FF
10905 #define SIO_HI_IF_STK_1__PRE                                                0x2
10906 #define   SIO_HI_IF_STK_1_ADDR__B                                           0
10907 #define   SIO_HI_IF_STK_1_ADDR__W                                           10
10908 #define   SIO_HI_IF_STK_1_ADDR__M                                           0x3FF
10909 #define   SIO_HI_IF_STK_1_ADDR__PRE                                         0x2
10910 
10911 #define SIO_HI_IF_STK_2__A                                                  0x440012
10912 #define SIO_HI_IF_STK_2__W                                                  10
10913 #define SIO_HI_IF_STK_2__M                                                  0x3FF
10914 #define SIO_HI_IF_STK_2__PRE                                                0x2
10915 #define   SIO_HI_IF_STK_2_ADDR__B                                           0
10916 #define   SIO_HI_IF_STK_2_ADDR__W                                           10
10917 #define   SIO_HI_IF_STK_2_ADDR__M                                           0x3FF
10918 #define   SIO_HI_IF_STK_2_ADDR__PRE                                         0x2
10919 
10920 #define SIO_HI_IF_STK_3__A                                                  0x440013
10921 #define SIO_HI_IF_STK_3__W                                                  10
10922 #define SIO_HI_IF_STK_3__M                                                  0x3FF
10923 #define SIO_HI_IF_STK_3__PRE                                                0x2
10924 
10925 #define   SIO_HI_IF_STK_3_ADDR__B                                           0
10926 #define   SIO_HI_IF_STK_3_ADDR__W                                           10
10927 #define   SIO_HI_IF_STK_3_ADDR__M                                           0x3FF
10928 #define   SIO_HI_IF_STK_3_ADDR__PRE                                         0x2
10929 
10930 #define SIO_HI_IF_BPT_IDX__A                                                0x44001F
10931 #define SIO_HI_IF_BPT_IDX__W                                                1
10932 #define SIO_HI_IF_BPT_IDX__M                                                0x1
10933 #define SIO_HI_IF_BPT_IDX__PRE                                              0x0
10934 
10935 #define   SIO_HI_IF_BPT_IDX_ADDR__B                                         0
10936 #define   SIO_HI_IF_BPT_IDX_ADDR__W                                         1
10937 #define   SIO_HI_IF_BPT_IDX_ADDR__M                                         0x1
10938 #define   SIO_HI_IF_BPT_IDX_ADDR__PRE                                       0x0
10939 
10940 #define SIO_HI_IF_BPT__A                                                    0x440020
10941 #define SIO_HI_IF_BPT__W                                                    10
10942 #define SIO_HI_IF_BPT__M                                                    0x3FF
10943 #define SIO_HI_IF_BPT__PRE                                                  0x2
10944 
10945 #define   SIO_HI_IF_BPT_ADDR__B                                             0
10946 #define   SIO_HI_IF_BPT_ADDR__W                                             10
10947 #define   SIO_HI_IF_BPT_ADDR__M                                             0x3FF
10948 #define   SIO_HI_IF_BPT_ADDR__PRE                                           0x2
10949 
10950 #define SIO_CC_COMM_EXEC__A                                                 0x450000
10951 #define SIO_CC_COMM_EXEC__W                                                 2
10952 #define SIO_CC_COMM_EXEC__M                                                 0x3
10953 #define SIO_CC_COMM_EXEC__PRE                                               0x0
10954 #define   SIO_CC_COMM_EXEC_STOP                                             0x0
10955 #define   SIO_CC_COMM_EXEC_ACTIVE                                           0x1
10956 #define   SIO_CC_COMM_EXEC_HOLD                                             0x2
10957 
10958 #define SIO_CC_PLL_MODE__A                                                  0x450010
10959 #define SIO_CC_PLL_MODE__W                                                  6
10960 #define SIO_CC_PLL_MODE__M                                                  0x3F
10961 #define SIO_CC_PLL_MODE__PRE                                                0x0
10962 
10963 #define   SIO_CC_PLL_MODE_FREF_SEL__B                                       0
10964 #define   SIO_CC_PLL_MODE_FREF_SEL__W                                       2
10965 #define   SIO_CC_PLL_MODE_FREF_SEL__M                                       0x3
10966 #define   SIO_CC_PLL_MODE_FREF_SEL__PRE                                     0x0
10967 #define     SIO_CC_PLL_MODE_FREF_SEL_OHW                                    0x0
10968 #define     SIO_CC_PLL_MODE_FREF_SEL_27_00                                  0x1
10969 #define     SIO_CC_PLL_MODE_FREF_SEL_20_25                                  0x2
10970 #define     SIO_CC_PLL_MODE_FREF_SEL_4_00                                   0x3
10971 
10972 #define   SIO_CC_PLL_MODE_LOCKSEL__B                                        2
10973 #define   SIO_CC_PLL_MODE_LOCKSEL__W                                        2
10974 #define   SIO_CC_PLL_MODE_LOCKSEL__M                                        0xC
10975 #define   SIO_CC_PLL_MODE_LOCKSEL__PRE                                      0x0
10976 
10977 #define   SIO_CC_PLL_MODE_BYPASS__B                                         4
10978 #define   SIO_CC_PLL_MODE_BYPASS__W                                         2
10979 #define   SIO_CC_PLL_MODE_BYPASS__M                                         0x30
10980 #define   SIO_CC_PLL_MODE_BYPASS__PRE                                       0x0
10981 #define     SIO_CC_PLL_MODE_BYPASS_OHW                                      0x0
10982 #define     SIO_CC_PLL_MODE_BYPASS_OFF                                      0x10
10983 #define     SIO_CC_PLL_MODE_BYPASS_ON                                       0x20
10984 
10985 #define SIO_CC_PLL_TEST__A                                                  0x450011
10986 #define SIO_CC_PLL_TEST__W                                                  8
10987 #define SIO_CC_PLL_TEST__M                                                  0xFF
10988 #define SIO_CC_PLL_TEST__PRE                                                0x0
10989 
10990 #define SIO_CC_PLL_LOCK__A                                                  0x450012
10991 #define SIO_CC_PLL_LOCK__W                                                  1
10992 #define SIO_CC_PLL_LOCK__M                                                  0x1
10993 #define SIO_CC_PLL_LOCK__PRE                                                0x0
10994 #define SIO_CC_CLK_MODE__A                                                  0x450014
10995 #define SIO_CC_CLK_MODE__W                                                  5
10996 #define SIO_CC_CLK_MODE__M                                                  0x1F
10997 #define SIO_CC_CLK_MODE__PRE                                                0x0
10998 
10999 #define   SIO_CC_CLK_MODE_DELAY__B                                          0
11000 #define   SIO_CC_CLK_MODE_DELAY__W                                          4
11001 #define   SIO_CC_CLK_MODE_DELAY__M                                          0xF
11002 #define   SIO_CC_CLK_MODE_DELAY__PRE                                        0x0
11003 
11004 #define   SIO_CC_CLK_MODE_INVERT__B                                         4
11005 #define   SIO_CC_CLK_MODE_INVERT__W                                         1
11006 #define   SIO_CC_CLK_MODE_INVERT__M                                         0x10
11007 #define   SIO_CC_CLK_MODE_INVERT__PRE                                       0x0
11008 
11009 #define SIO_CC_PWD_MODE__A                                                  0x450015
11010 #define SIO_CC_PWD_MODE__W                                                  3
11011 #define SIO_CC_PWD_MODE__M                                                  0x7
11012 #define SIO_CC_PWD_MODE__PRE                                                0x0
11013 
11014 #define   SIO_CC_PWD_MODE_LEVEL__B                                          0
11015 #define   SIO_CC_PWD_MODE_LEVEL__W                                          2
11016 #define   SIO_CC_PWD_MODE_LEVEL__M                                          0x3
11017 #define   SIO_CC_PWD_MODE_LEVEL__PRE                                        0x0
11018 #define     SIO_CC_PWD_MODE_LEVEL_NONE                                      0x0
11019 #define     SIO_CC_PWD_MODE_LEVEL_CLOCK                                     0x1
11020 #define     SIO_CC_PWD_MODE_LEVEL_PLL                                       0x2
11021 #define     SIO_CC_PWD_MODE_LEVEL_OSC                                       0x3
11022 
11023 #define   SIO_CC_PWD_MODE_USE_LOCK__B                                       2
11024 #define   SIO_CC_PWD_MODE_USE_LOCK__W                                       1
11025 #define   SIO_CC_PWD_MODE_USE_LOCK__M                                       0x4
11026 #define   SIO_CC_PWD_MODE_USE_LOCK__PRE                                     0x0
11027 
11028 #define SIO_CC_SOFT_RST__A                                                  0x450016
11029 #define SIO_CC_SOFT_RST__W                                                  2
11030 #define SIO_CC_SOFT_RST__M                                                  0x3
11031 #define SIO_CC_SOFT_RST__PRE                                                0x0
11032 
11033 #define   SIO_CC_SOFT_RST_SYS__B                                            0
11034 #define   SIO_CC_SOFT_RST_SYS__W                                            1
11035 #define   SIO_CC_SOFT_RST_SYS__M                                            0x1
11036 #define   SIO_CC_SOFT_RST_SYS__PRE                                          0x0
11037 
11038 #define   SIO_CC_SOFT_RST_OSC__B                                            1
11039 #define   SIO_CC_SOFT_RST_OSC__W                                            1
11040 #define   SIO_CC_SOFT_RST_OSC__M                                            0x2
11041 #define   SIO_CC_SOFT_RST_OSC__PRE                                          0x0
11042 
11043 #define SIO_CC_UPDATE__A                                                    0x450017
11044 #define SIO_CC_UPDATE__W                                                    16
11045 #define SIO_CC_UPDATE__M                                                    0xFFFF
11046 #define SIO_CC_UPDATE__PRE                                                  0x0
11047 #define   SIO_CC_UPDATE_KEY                                                 0xFABA
11048 
11049 #define SIO_SA_COMM_EXEC__A                                                 0x460000
11050 #define SIO_SA_COMM_EXEC__W                                                 2
11051 #define SIO_SA_COMM_EXEC__M                                                 0x3
11052 #define SIO_SA_COMM_EXEC__PRE                                               0x0
11053 #define   SIO_SA_COMM_EXEC_STOP                                             0x0
11054 #define   SIO_SA_COMM_EXEC_ACTIVE                                           0x1
11055 #define   SIO_SA_COMM_EXEC_HOLD                                             0x2
11056 
11057 #define SIO_SA_COMM_INT_REQ__A                                              0x460003
11058 #define SIO_SA_COMM_INT_REQ__W                                              1
11059 #define SIO_SA_COMM_INT_REQ__M                                              0x1
11060 #define SIO_SA_COMM_INT_REQ__PRE                                            0x0
11061 #define SIO_SA_COMM_INT_STA__A                                              0x460005
11062 #define SIO_SA_COMM_INT_STA__W                                              4
11063 #define SIO_SA_COMM_INT_STA__M                                              0xF
11064 #define SIO_SA_COMM_INT_STA__PRE                                            0x0
11065 
11066 #define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__B                             0
11067 #define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__W                             1
11068 #define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__M                             0x1
11069 #define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE                           0x0
11070 
11071 #define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B                          1
11072 #define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W                          1
11073 #define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M                          0x2
11074 #define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE                        0x0
11075 
11076 #define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__B                             2
11077 #define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__W                             1
11078 #define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__M                             0x4
11079 #define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE                           0x0
11080 
11081 #define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B                           3
11082 #define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W                           1
11083 #define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M                           0x8
11084 #define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE                         0x0
11085 
11086 #define SIO_SA_COMM_INT_MSK__A                                              0x460006
11087 #define SIO_SA_COMM_INT_MSK__W                                              4
11088 #define SIO_SA_COMM_INT_MSK__M                                              0xF
11089 #define SIO_SA_COMM_INT_MSK__PRE                                            0x0
11090 
11091 #define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B                            0
11092 #define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W                            1
11093 #define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M                            0x1
11094 #define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE                          0x0
11095 
11096 #define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B                         1
11097 #define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W                         1
11098 #define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M                         0x2
11099 #define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE                       0x0
11100 
11101 #define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B                            2
11102 #define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W                            1
11103 #define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M                            0x4
11104 #define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE                          0x0
11105 
11106 #define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B                          3
11107 #define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W                          1
11108 #define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M                          0x8
11109 #define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE                        0x0
11110 
11111 #define SIO_SA_COMM_INT_STM__A                                              0x460007
11112 #define SIO_SA_COMM_INT_STM__W                                              4
11113 #define SIO_SA_COMM_INT_STM__M                                              0xF
11114 #define SIO_SA_COMM_INT_STM__PRE                                            0x0
11115 
11116 #define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B                            0
11117 #define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W                            1
11118 #define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M                            0x1
11119 #define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE                          0x0
11120 
11121 #define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B                         1
11122 #define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W                         1
11123 #define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M                         0x2
11124 #define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE                       0x0
11125 
11126 #define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B                            2
11127 #define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W                            1
11128 #define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M                            0x4
11129 #define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE                          0x0
11130 
11131 #define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B                          3
11132 #define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W                          1
11133 #define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M                          0x8
11134 #define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE                        0x0
11135 
11136 #define SIO_SA_PRESCALER__A                                                 0x460010
11137 #define SIO_SA_PRESCALER__W                                                 13
11138 #define SIO_SA_PRESCALER__M                                                 0x1FFF
11139 #define SIO_SA_PRESCALER__PRE                                               0x18B7
11140 #define SIO_SA_TX_DATA0__A                                                  0x460011
11141 #define SIO_SA_TX_DATA0__W                                                  16
11142 #define SIO_SA_TX_DATA0__M                                                  0xFFFF
11143 #define SIO_SA_TX_DATA0__PRE                                                0x0
11144 #define SIO_SA_TX_DATA1__A                                                  0x460012
11145 #define SIO_SA_TX_DATA1__W                                                  16
11146 #define SIO_SA_TX_DATA1__M                                                  0xFFFF
11147 #define SIO_SA_TX_DATA1__PRE                                                0x0
11148 #define SIO_SA_TX_DATA2__A                                                  0x460013
11149 #define SIO_SA_TX_DATA2__W                                                  16
11150 #define SIO_SA_TX_DATA2__M                                                  0xFFFF
11151 #define SIO_SA_TX_DATA2__PRE                                                0x0
11152 #define SIO_SA_TX_DATA3__A                                                  0x460014
11153 #define SIO_SA_TX_DATA3__W                                                  16
11154 #define SIO_SA_TX_DATA3__M                                                  0xFFFF
11155 #define SIO_SA_TX_DATA3__PRE                                                0x0
11156 #define SIO_SA_TX_LENGTH__A                                                 0x460015
11157 #define SIO_SA_TX_LENGTH__W                                                 6
11158 #define SIO_SA_TX_LENGTH__M                                                 0x3F
11159 #define SIO_SA_TX_LENGTH__PRE                                               0x0
11160 #define SIO_SA_TX_COMMAND__A                                                0x460016
11161 #define SIO_SA_TX_COMMAND__W                                                2
11162 #define SIO_SA_TX_COMMAND__M                                                0x3
11163 #define SIO_SA_TX_COMMAND__PRE                                              0x3
11164 
11165 #define   SIO_SA_TX_COMMAND_TX_INVERT__B                                    0
11166 #define   SIO_SA_TX_COMMAND_TX_INVERT__W                                    1
11167 #define   SIO_SA_TX_COMMAND_TX_INVERT__M                                    0x1
11168 #define   SIO_SA_TX_COMMAND_TX_INVERT__PRE                                  0x1
11169 
11170 #define   SIO_SA_TX_COMMAND_TX_ENABLE__B                                    1
11171 #define   SIO_SA_TX_COMMAND_TX_ENABLE__W                                    1
11172 #define   SIO_SA_TX_COMMAND_TX_ENABLE__M                                    0x2
11173 #define   SIO_SA_TX_COMMAND_TX_ENABLE__PRE                                  0x2
11174 
11175 #define SIO_SA_TX_STATUS__A                                                 0x460017
11176 #define SIO_SA_TX_STATUS__W                                                 2
11177 #define SIO_SA_TX_STATUS__M                                                 0x3
11178 #define SIO_SA_TX_STATUS__PRE                                               0x0
11179 
11180 #define   SIO_SA_TX_STATUS_BUSY__B                                          0
11181 #define   SIO_SA_TX_STATUS_BUSY__W                                          1
11182 #define   SIO_SA_TX_STATUS_BUSY__M                                          0x1
11183 #define   SIO_SA_TX_STATUS_BUSY__PRE                                        0x0
11184 
11185 #define   SIO_SA_TX_STATUS_BUFF_FULL__B                                     1
11186 #define   SIO_SA_TX_STATUS_BUFF_FULL__W                                     1
11187 #define   SIO_SA_TX_STATUS_BUFF_FULL__M                                     0x2
11188 #define   SIO_SA_TX_STATUS_BUFF_FULL__PRE                                   0x0
11189 
11190 #define SIO_SA_RX_DATA0__A                                                  0x460018
11191 #define SIO_SA_RX_DATA0__W                                                  16
11192 #define SIO_SA_RX_DATA0__M                                                  0xFFFF
11193 #define SIO_SA_RX_DATA0__PRE                                                0x0
11194 #define SIO_SA_RX_DATA1__A                                                  0x460019
11195 #define SIO_SA_RX_DATA1__W                                                  16
11196 #define SIO_SA_RX_DATA1__M                                                  0xFFFF
11197 #define SIO_SA_RX_DATA1__PRE                                                0x0
11198 #define SIO_SA_RX_LENGTH__A                                                 0x46001A
11199 #define SIO_SA_RX_LENGTH__W                                                 6
11200 #define SIO_SA_RX_LENGTH__M                                                 0x3F
11201 #define SIO_SA_RX_LENGTH__PRE                                               0x0
11202 #define SIO_SA_RX_COMMAND__A                                                0x46001B
11203 #define SIO_SA_RX_COMMAND__W                                                1
11204 #define SIO_SA_RX_COMMAND__M                                                0x1
11205 #define SIO_SA_RX_COMMAND__PRE                                              0x1
11206 
11207 #define   SIO_SA_RX_COMMAND_RX_INVERT__B                                    0
11208 #define   SIO_SA_RX_COMMAND_RX_INVERT__W                                    1
11209 #define   SIO_SA_RX_COMMAND_RX_INVERT__M                                    0x1
11210 #define   SIO_SA_RX_COMMAND_RX_INVERT__PRE                                  0x1
11211 
11212 #define SIO_SA_RX_STATUS__A                                                 0x46001C
11213 #define SIO_SA_RX_STATUS__W                                                 2
11214 #define SIO_SA_RX_STATUS__M                                                 0x3
11215 #define SIO_SA_RX_STATUS__PRE                                               0x0
11216 
11217 #define   SIO_SA_RX_STATUS_BUSY__B                                          0
11218 #define   SIO_SA_RX_STATUS_BUSY__W                                          1
11219 #define   SIO_SA_RX_STATUS_BUSY__M                                          0x1
11220 #define   SIO_SA_RX_STATUS_BUSY__PRE                                        0x0
11221 
11222 #define   SIO_SA_RX_STATUS_BUFF_FULL__B                                     1
11223 #define   SIO_SA_RX_STATUS_BUFF_FULL__W                                     1
11224 #define   SIO_SA_RX_STATUS_BUFF_FULL__M                                     0x2
11225 #define   SIO_SA_RX_STATUS_BUFF_FULL__PRE                                   0x0
11226 
11227 #define SIO_PDR_COMM_EXEC__A                                                0x7F0000
11228 #define SIO_PDR_COMM_EXEC__W                                                2
11229 #define SIO_PDR_COMM_EXEC__M                                                0x3
11230 #define SIO_PDR_COMM_EXEC__PRE                                              0x0
11231 #define   SIO_PDR_COMM_EXEC_STOP                                            0x0
11232 #define   SIO_PDR_COMM_EXEC_ACTIVE                                          0x1
11233 #define   SIO_PDR_COMM_EXEC_HOLD                                            0x2
11234 
11235 #define SIO_PDR_MON_CFG__A                                                  0x7F0010
11236 #define SIO_PDR_MON_CFG__W                                                  2
11237 #define SIO_PDR_MON_CFG__M                                                  0x3
11238 #define SIO_PDR_MON_CFG__PRE                                                0x0
11239 
11240 #define   SIO_PDR_MON_CFG_OSEL__B                                           0
11241 #define   SIO_PDR_MON_CFG_OSEL__W                                           1
11242 #define   SIO_PDR_MON_CFG_OSEL__M                                           0x1
11243 #define   SIO_PDR_MON_CFG_OSEL__PRE                                         0x0
11244 
11245 #define   SIO_PDR_MON_CFG_IACT__B                                           1
11246 #define   SIO_PDR_MON_CFG_IACT__W                                           1
11247 #define   SIO_PDR_MON_CFG_IACT__M                                           0x2
11248 #define   SIO_PDR_MON_CFG_IACT__PRE                                         0x0
11249 
11250 #define SIO_PDR_FDB_CFG__A                                                  0x7F0011
11251 #define SIO_PDR_FDB_CFG__W                                                  2
11252 #define SIO_PDR_FDB_CFG__M                                                  0x3
11253 #define SIO_PDR_FDB_CFG__PRE                                                0x0
11254 #define   SIO_PDR_FDB_CFG_SEL__B                                            0
11255 #define   SIO_PDR_FDB_CFG_SEL__W                                            2
11256 #define   SIO_PDR_FDB_CFG_SEL__M                                            0x3
11257 #define   SIO_PDR_FDB_CFG_SEL__PRE                                          0x0
11258 
11259 #define SIO_PDR_SMA_RX_SEL__A                                               0x7F0012
11260 #define SIO_PDR_SMA_RX_SEL__W                                               4
11261 #define SIO_PDR_SMA_RX_SEL__M                                               0xF
11262 #define SIO_PDR_SMA_RX_SEL__PRE                                             0x0
11263 #define   SIO_PDR_SMA_RX_SEL_SEL__B                                         0
11264 #define   SIO_PDR_SMA_RX_SEL_SEL__W                                         4
11265 #define   SIO_PDR_SMA_RX_SEL_SEL__M                                         0xF
11266 #define   SIO_PDR_SMA_RX_SEL_SEL__PRE                                       0x0
11267 
11268 #define SIO_PDR_SMA_TX_SILENT__A                                            0x7F0013
11269 #define SIO_PDR_SMA_TX_SILENT__W                                            1
11270 #define SIO_PDR_SMA_TX_SILENT__M                                            0x1
11271 #define SIO_PDR_SMA_TX_SILENT__PRE                                          0x0
11272 #define SIO_PDR_UIO_IN_LO__A                                                0x7F0014
11273 #define SIO_PDR_UIO_IN_LO__W                                                16
11274 #define SIO_PDR_UIO_IN_LO__M                                                0xFFFF
11275 #define SIO_PDR_UIO_IN_LO__PRE                                              0x0
11276 #define   SIO_PDR_UIO_IN_LO_DATA__B                                         0
11277 #define   SIO_PDR_UIO_IN_LO_DATA__W                                         16
11278 #define   SIO_PDR_UIO_IN_LO_DATA__M                                         0xFFFF
11279 #define   SIO_PDR_UIO_IN_LO_DATA__PRE                                       0x0
11280 
11281 #define SIO_PDR_UIO_IN_HI__A                                                0x7F0015
11282 #define SIO_PDR_UIO_IN_HI__W                                                14
11283 #define SIO_PDR_UIO_IN_HI__M                                                0x3FFF
11284 #define SIO_PDR_UIO_IN_HI__PRE                                              0x0
11285 #define   SIO_PDR_UIO_IN_HI_DATA__B                                         0
11286 #define   SIO_PDR_UIO_IN_HI_DATA__W                                         14
11287 #define   SIO_PDR_UIO_IN_HI_DATA__M                                         0x3FFF
11288 #define   SIO_PDR_UIO_IN_HI_DATA__PRE                                       0x0
11289 
11290 #define SIO_PDR_UIO_OUT_LO__A                                               0x7F0016
11291 #define SIO_PDR_UIO_OUT_LO__W                                               16
11292 #define SIO_PDR_UIO_OUT_LO__M                                               0xFFFF
11293 #define SIO_PDR_UIO_OUT_LO__PRE                                             0x0
11294 #define   SIO_PDR_UIO_OUT_LO_DATA__B                                        0
11295 #define   SIO_PDR_UIO_OUT_LO_DATA__W                                        16
11296 #define   SIO_PDR_UIO_OUT_LO_DATA__M                                        0xFFFF
11297 #define   SIO_PDR_UIO_OUT_LO_DATA__PRE                                      0x0
11298 
11299 #define SIO_PDR_UIO_OUT_HI__A                                               0x7F0017
11300 #define SIO_PDR_UIO_OUT_HI__W                                               14
11301 #define SIO_PDR_UIO_OUT_HI__M                                               0x3FFF
11302 #define SIO_PDR_UIO_OUT_HI__PRE                                             0x0
11303 #define   SIO_PDR_UIO_OUT_HI_DATA__B                                        0
11304 #define   SIO_PDR_UIO_OUT_HI_DATA__W                                        14
11305 #define   SIO_PDR_UIO_OUT_HI_DATA__M                                        0x3FFF
11306 #define   SIO_PDR_UIO_OUT_HI_DATA__PRE                                      0x0
11307 
11308 #define SIO_PDR_PWM1_MODE__A                                                0x7F0018
11309 #define SIO_PDR_PWM1_MODE__W                                                2
11310 #define SIO_PDR_PWM1_MODE__M                                                0x3
11311 #define SIO_PDR_PWM1_MODE__PRE                                              0x0
11312 #define SIO_PDR_PWM1_PRESCALE__A                                            0x7F0019
11313 #define SIO_PDR_PWM1_PRESCALE__W                                            6
11314 #define SIO_PDR_PWM1_PRESCALE__M                                            0x3F
11315 #define SIO_PDR_PWM1_PRESCALE__PRE                                          0x0
11316 #define SIO_PDR_PWM1_VALUE__A                                               0x7F001A
11317 #define SIO_PDR_PWM1_VALUE__W                                               11
11318 #define SIO_PDR_PWM1_VALUE__M                                               0x7FF
11319 #define SIO_PDR_PWM1_VALUE__PRE                                             0x0
11320 #define SIO_PDR_PWM2_MODE__A                                                0x7F001C
11321 #define SIO_PDR_PWM2_MODE__W                                                2
11322 #define SIO_PDR_PWM2_MODE__M                                                0x3
11323 #define SIO_PDR_PWM2_MODE__PRE                                              0x0
11324 #define SIO_PDR_PWM2_PRESCALE__A                                            0x7F001D
11325 #define SIO_PDR_PWM2_PRESCALE__W                                            6
11326 #define SIO_PDR_PWM2_PRESCALE__M                                            0x3F
11327 #define SIO_PDR_PWM2_PRESCALE__PRE                                          0x0
11328 #define SIO_PDR_PWM2_VALUE__A                                               0x7F001E
11329 #define SIO_PDR_PWM2_VALUE__W                                               11
11330 #define SIO_PDR_PWM2_VALUE__M                                               0x7FF
11331 #define SIO_PDR_PWM2_VALUE__PRE                                             0x0
11332 #define SIO_PDR_OHW_CFG__A                                                  0x7F001F
11333 #define SIO_PDR_OHW_CFG__W                                                  7
11334 #define SIO_PDR_OHW_CFG__M                                                  0x7F
11335 #define SIO_PDR_OHW_CFG__PRE                                                0x0
11336 
11337 #define   SIO_PDR_OHW_CFG_FREF_SEL__B                                       0
11338 #define   SIO_PDR_OHW_CFG_FREF_SEL__W                                       2
11339 #define   SIO_PDR_OHW_CFG_FREF_SEL__M                                       0x3
11340 #define   SIO_PDR_OHW_CFG_FREF_SEL__PRE                                     0x0
11341 
11342 #define   SIO_PDR_OHW_CFG_BYPASS__B                                         2
11343 #define   SIO_PDR_OHW_CFG_BYPASS__W                                         1
11344 #define   SIO_PDR_OHW_CFG_BYPASS__M                                         0x4
11345 #define   SIO_PDR_OHW_CFG_BYPASS__PRE                                       0x0
11346 
11347 #define   SIO_PDR_OHW_CFG_ASEL__B                                           3
11348 #define   SIO_PDR_OHW_CFG_ASEL__W                                           3
11349 #define   SIO_PDR_OHW_CFG_ASEL__M                                           0x38
11350 #define   SIO_PDR_OHW_CFG_ASEL__PRE                                         0x0
11351 
11352 #define   SIO_PDR_OHW_CFG_SPEED__B                                          6
11353 #define   SIO_PDR_OHW_CFG_SPEED__W                                          1
11354 #define   SIO_PDR_OHW_CFG_SPEED__M                                          0x40
11355 #define   SIO_PDR_OHW_CFG_SPEED__PRE                                        0x0
11356 
11357 #define SIO_PDR_I2S_WS_CFG__A                                               0x7F0020
11358 #define SIO_PDR_I2S_WS_CFG__W                                               9
11359 #define SIO_PDR_I2S_WS_CFG__M                                               0x1FF
11360 #define SIO_PDR_I2S_WS_CFG__PRE                                             0x10
11361 #define   SIO_PDR_I2S_WS_CFG_MODE__B                                        0
11362 #define   SIO_PDR_I2S_WS_CFG_MODE__W                                        3
11363 #define   SIO_PDR_I2S_WS_CFG_MODE__M                                        0x7
11364 #define   SIO_PDR_I2S_WS_CFG_MODE__PRE                                      0x0
11365 #define   SIO_PDR_I2S_WS_CFG_DRIVE__B                                       3
11366 #define   SIO_PDR_I2S_WS_CFG_DRIVE__W                                       3
11367 #define   SIO_PDR_I2S_WS_CFG_DRIVE__M                                       0x38
11368 #define   SIO_PDR_I2S_WS_CFG_DRIVE__PRE                                     0x10
11369 #define   SIO_PDR_I2S_WS_CFG_KEEP__B                                        6
11370 #define   SIO_PDR_I2S_WS_CFG_KEEP__W                                        2
11371 #define   SIO_PDR_I2S_WS_CFG_KEEP__M                                        0xC0
11372 #define   SIO_PDR_I2S_WS_CFG_KEEP__PRE                                      0x0
11373 #define   SIO_PDR_I2S_WS_CFG_UIO__B                                         8
11374 #define   SIO_PDR_I2S_WS_CFG_UIO__W                                         1
11375 #define   SIO_PDR_I2S_WS_CFG_UIO__M                                         0x100
11376 #define   SIO_PDR_I2S_WS_CFG_UIO__PRE                                       0x0
11377 
11378 #define SIO_PDR_GPIO_CFG__A                                                 0x7F0021
11379 #define SIO_PDR_GPIO_CFG__W                                                 9
11380 #define SIO_PDR_GPIO_CFG__M                                                 0x1FF
11381 #define SIO_PDR_GPIO_CFG__PRE                                               0x10
11382 #define   SIO_PDR_GPIO_CFG_MODE__B                                          0
11383 #define   SIO_PDR_GPIO_CFG_MODE__W                                          3
11384 #define   SIO_PDR_GPIO_CFG_MODE__M                                          0x7
11385 #define   SIO_PDR_GPIO_CFG_MODE__PRE                                        0x0
11386 #define   SIO_PDR_GPIO_CFG_DRIVE__B                                         3
11387 #define   SIO_PDR_GPIO_CFG_DRIVE__W                                         3
11388 #define   SIO_PDR_GPIO_CFG_DRIVE__M                                         0x38
11389 #define   SIO_PDR_GPIO_CFG_DRIVE__PRE                                       0x10
11390 #define   SIO_PDR_GPIO_CFG_KEEP__B                                          6
11391 #define   SIO_PDR_GPIO_CFG_KEEP__W                                          2
11392 #define   SIO_PDR_GPIO_CFG_KEEP__M                                          0xC0
11393 #define   SIO_PDR_GPIO_CFG_KEEP__PRE                                        0x0
11394 #define   SIO_PDR_GPIO_CFG_UIO__B                                           8
11395 #define   SIO_PDR_GPIO_CFG_UIO__W                                           1
11396 #define   SIO_PDR_GPIO_CFG_UIO__M                                           0x100
11397 #define   SIO_PDR_GPIO_CFG_UIO__PRE                                         0x0
11398 
11399 #define SIO_PDR_IRQN_CFG__A                                                 0x7F0022
11400 #define SIO_PDR_IRQN_CFG__W                                                 9
11401 #define SIO_PDR_IRQN_CFG__M                                                 0x1FF
11402 #define SIO_PDR_IRQN_CFG__PRE                                               0x10
11403 #define   SIO_PDR_IRQN_CFG_MODE__B                                          0
11404 #define   SIO_PDR_IRQN_CFG_MODE__W                                          3
11405 #define   SIO_PDR_IRQN_CFG_MODE__M                                          0x7
11406 #define   SIO_PDR_IRQN_CFG_MODE__PRE                                        0x0
11407 #define   SIO_PDR_IRQN_CFG_DRIVE__B                                         3
11408 #define   SIO_PDR_IRQN_CFG_DRIVE__W                                         3
11409 #define   SIO_PDR_IRQN_CFG_DRIVE__M                                         0x38
11410 #define   SIO_PDR_IRQN_CFG_DRIVE__PRE                                       0x10
11411 #define   SIO_PDR_IRQN_CFG_KEEP__B                                          6
11412 #define   SIO_PDR_IRQN_CFG_KEEP__W                                          2
11413 #define   SIO_PDR_IRQN_CFG_KEEP__M                                          0xC0
11414 #define   SIO_PDR_IRQN_CFG_KEEP__PRE                                        0x0
11415 #define   SIO_PDR_IRQN_CFG_UIO__B                                           8
11416 #define   SIO_PDR_IRQN_CFG_UIO__W                                           1
11417 #define   SIO_PDR_IRQN_CFG_UIO__M                                           0x100
11418 #define   SIO_PDR_IRQN_CFG_UIO__PRE                                         0x0
11419 
11420 #define SIO_PDR_OOB_CRX_CFG__A                                              0x7F0023
11421 #define SIO_PDR_OOB_CRX_CFG__W                                              9
11422 #define SIO_PDR_OOB_CRX_CFG__M                                              0x1FF
11423 #define SIO_PDR_OOB_CRX_CFG__PRE                                            0x10
11424 #define   SIO_PDR_OOB_CRX_CFG_MODE__B                                       0
11425 #define   SIO_PDR_OOB_CRX_CFG_MODE__W                                       3
11426 #define   SIO_PDR_OOB_CRX_CFG_MODE__M                                       0x7
11427 #define   SIO_PDR_OOB_CRX_CFG_MODE__PRE                                     0x0
11428 #define   SIO_PDR_OOB_CRX_CFG_DRIVE__B                                      3
11429 #define   SIO_PDR_OOB_CRX_CFG_DRIVE__W                                      3
11430 #define   SIO_PDR_OOB_CRX_CFG_DRIVE__M                                      0x38
11431 #define   SIO_PDR_OOB_CRX_CFG_DRIVE__PRE                                    0x10
11432 #define   SIO_PDR_OOB_CRX_CFG_KEEP__B                                       6
11433 #define   SIO_PDR_OOB_CRX_CFG_KEEP__W                                       2
11434 #define   SIO_PDR_OOB_CRX_CFG_KEEP__M                                       0xC0
11435 #define   SIO_PDR_OOB_CRX_CFG_KEEP__PRE                                     0x0
11436 #define   SIO_PDR_OOB_CRX_CFG_UIO__B                                        8
11437 #define   SIO_PDR_OOB_CRX_CFG_UIO__W                                        1
11438 #define   SIO_PDR_OOB_CRX_CFG_UIO__M                                        0x100
11439 #define   SIO_PDR_OOB_CRX_CFG_UIO__PRE                                      0x0
11440 
11441 #define SIO_PDR_OOB_DRX_CFG__A                                              0x7F0024
11442 #define SIO_PDR_OOB_DRX_CFG__W                                              9
11443 #define SIO_PDR_OOB_DRX_CFG__M                                              0x1FF
11444 #define SIO_PDR_OOB_DRX_CFG__PRE                                            0x10
11445 #define   SIO_PDR_OOB_DRX_CFG_MODE__B                                       0
11446 #define   SIO_PDR_OOB_DRX_CFG_MODE__W                                       3
11447 #define   SIO_PDR_OOB_DRX_CFG_MODE__M                                       0x7
11448 #define   SIO_PDR_OOB_DRX_CFG_MODE__PRE                                     0x0
11449 #define   SIO_PDR_OOB_DRX_CFG_DRIVE__B                                      3
11450 #define   SIO_PDR_OOB_DRX_CFG_DRIVE__W                                      3
11451 #define   SIO_PDR_OOB_DRX_CFG_DRIVE__M                                      0x38
11452 #define   SIO_PDR_OOB_DRX_CFG_DRIVE__PRE                                    0x10
11453 #define   SIO_PDR_OOB_DRX_CFG_KEEP__B                                       6
11454 #define   SIO_PDR_OOB_DRX_CFG_KEEP__W                                       2
11455 #define   SIO_PDR_OOB_DRX_CFG_KEEP__M                                       0xC0
11456 #define   SIO_PDR_OOB_DRX_CFG_KEEP__PRE                                     0x0
11457 #define   SIO_PDR_OOB_DRX_CFG_UIO__B                                        8
11458 #define   SIO_PDR_OOB_DRX_CFG_UIO__W                                        1
11459 #define   SIO_PDR_OOB_DRX_CFG_UIO__M                                        0x100
11460 #define   SIO_PDR_OOB_DRX_CFG_UIO__PRE                                      0x0
11461 
11462 #define SIO_PDR_MSTRT_CFG__A                                                0x7F0025
11463 #define SIO_PDR_MSTRT_CFG__W                                                9
11464 #define SIO_PDR_MSTRT_CFG__M                                                0x1FF
11465 #define SIO_PDR_MSTRT_CFG__PRE                                              0x50
11466 #define   SIO_PDR_MSTRT_CFG_MODE__B                                         0
11467 #define   SIO_PDR_MSTRT_CFG_MODE__W                                         3
11468 #define   SIO_PDR_MSTRT_CFG_MODE__M                                         0x7
11469 #define   SIO_PDR_MSTRT_CFG_MODE__PRE                                       0x0
11470 #define   SIO_PDR_MSTRT_CFG_DRIVE__B                                        3
11471 #define   SIO_PDR_MSTRT_CFG_DRIVE__W                                        3
11472 #define   SIO_PDR_MSTRT_CFG_DRIVE__M                                        0x38
11473 #define   SIO_PDR_MSTRT_CFG_DRIVE__PRE                                      0x10
11474 #define   SIO_PDR_MSTRT_CFG_KEEP__B                                         6
11475 #define   SIO_PDR_MSTRT_CFG_KEEP__W                                         2
11476 #define   SIO_PDR_MSTRT_CFG_KEEP__M                                         0xC0
11477 #define   SIO_PDR_MSTRT_CFG_KEEP__PRE                                       0x40
11478 #define   SIO_PDR_MSTRT_CFG_UIO__B                                          8
11479 #define   SIO_PDR_MSTRT_CFG_UIO__W                                          1
11480 #define   SIO_PDR_MSTRT_CFG_UIO__M                                          0x100
11481 #define   SIO_PDR_MSTRT_CFG_UIO__PRE                                        0x0
11482 
11483 #define SIO_PDR_MERR_CFG__A                                                 0x7F0026
11484 #define SIO_PDR_MERR_CFG__W                                                 9
11485 #define SIO_PDR_MERR_CFG__M                                                 0x1FF
11486 #define SIO_PDR_MERR_CFG__PRE                                               0x50
11487 #define   SIO_PDR_MERR_CFG_MODE__B                                          0
11488 #define   SIO_PDR_MERR_CFG_MODE__W                                          3
11489 #define   SIO_PDR_MERR_CFG_MODE__M                                          0x7
11490 #define   SIO_PDR_MERR_CFG_MODE__PRE                                        0x0
11491 #define   SIO_PDR_MERR_CFG_DRIVE__B                                         3
11492 #define   SIO_PDR_MERR_CFG_DRIVE__W                                         3
11493 #define   SIO_PDR_MERR_CFG_DRIVE__M                                         0x38
11494 #define   SIO_PDR_MERR_CFG_DRIVE__PRE                                       0x10
11495 #define   SIO_PDR_MERR_CFG_KEEP__B                                          6
11496 #define   SIO_PDR_MERR_CFG_KEEP__W                                          2
11497 #define   SIO_PDR_MERR_CFG_KEEP__M                                          0xC0
11498 #define   SIO_PDR_MERR_CFG_KEEP__PRE                                        0x40
11499 #define   SIO_PDR_MERR_CFG_UIO__B                                           8
11500 #define   SIO_PDR_MERR_CFG_UIO__W                                           1
11501 #define   SIO_PDR_MERR_CFG_UIO__M                                           0x100
11502 #define   SIO_PDR_MERR_CFG_UIO__PRE                                         0x0
11503 
11504 #define SIO_PDR_MCLK_CFG__A                                                 0x7F0028
11505 #define SIO_PDR_MCLK_CFG__W                                                 9
11506 #define SIO_PDR_MCLK_CFG__M                                                 0x1FF
11507 #define SIO_PDR_MCLK_CFG__PRE                                               0x50
11508 #define   SIO_PDR_MCLK_CFG_MODE__B                                          0
11509 #define   SIO_PDR_MCLK_CFG_MODE__W                                          3
11510 #define   SIO_PDR_MCLK_CFG_MODE__M                                          0x7
11511 #define   SIO_PDR_MCLK_CFG_MODE__PRE                                        0x0
11512 #define   SIO_PDR_MCLK_CFG_DRIVE__B                                         3
11513 #define   SIO_PDR_MCLK_CFG_DRIVE__W                                         3
11514 #define   SIO_PDR_MCLK_CFG_DRIVE__M                                         0x38
11515 #define   SIO_PDR_MCLK_CFG_DRIVE__PRE                                       0x10
11516 #define   SIO_PDR_MCLK_CFG_KEEP__B                                          6
11517 #define   SIO_PDR_MCLK_CFG_KEEP__W                                          2
11518 #define   SIO_PDR_MCLK_CFG_KEEP__M                                          0xC0
11519 #define   SIO_PDR_MCLK_CFG_KEEP__PRE                                        0x40
11520 #define   SIO_PDR_MCLK_CFG_UIO__B                                           8
11521 #define   SIO_PDR_MCLK_CFG_UIO__W                                           1
11522 #define   SIO_PDR_MCLK_CFG_UIO__M                                           0x100
11523 #define   SIO_PDR_MCLK_CFG_UIO__PRE                                         0x0
11524 
11525 #define SIO_PDR_MVAL_CFG__A                                                 0x7F0029
11526 #define SIO_PDR_MVAL_CFG__W                                                 9
11527 #define SIO_PDR_MVAL_CFG__M                                                 0x1FF
11528 #define SIO_PDR_MVAL_CFG__PRE                                               0x50
11529 #define   SIO_PDR_MVAL_CFG_MODE__B                                          0
11530 #define   SIO_PDR_MVAL_CFG_MODE__W                                          3
11531 #define   SIO_PDR_MVAL_CFG_MODE__M                                          0x7
11532 #define   SIO_PDR_MVAL_CFG_MODE__PRE                                        0x0
11533 #define   SIO_PDR_MVAL_CFG_DRIVE__B                                         3
11534 #define   SIO_PDR_MVAL_CFG_DRIVE__W                                         3
11535 #define   SIO_PDR_MVAL_CFG_DRIVE__M                                         0x38
11536 #define   SIO_PDR_MVAL_CFG_DRIVE__PRE                                       0x10
11537 #define   SIO_PDR_MVAL_CFG_KEEP__B                                          6
11538 #define   SIO_PDR_MVAL_CFG_KEEP__W                                          2
11539 #define   SIO_PDR_MVAL_CFG_KEEP__M                                          0xC0
11540 #define   SIO_PDR_MVAL_CFG_KEEP__PRE                                        0x40
11541 #define   SIO_PDR_MVAL_CFG_UIO__B                                           8
11542 #define   SIO_PDR_MVAL_CFG_UIO__W                                           1
11543 #define   SIO_PDR_MVAL_CFG_UIO__M                                           0x100
11544 #define   SIO_PDR_MVAL_CFG_UIO__PRE                                         0x0
11545 
11546 #define SIO_PDR_MD0_CFG__A                                                  0x7F002A
11547 #define SIO_PDR_MD0_CFG__W                                                  9
11548 #define SIO_PDR_MD0_CFG__M                                                  0x1FF
11549 #define SIO_PDR_MD0_CFG__PRE                                                0x50
11550 #define   SIO_PDR_MD0_CFG_MODE__B                                           0
11551 #define   SIO_PDR_MD0_CFG_MODE__W                                           3
11552 #define   SIO_PDR_MD0_CFG_MODE__M                                           0x7
11553 #define   SIO_PDR_MD0_CFG_MODE__PRE                                         0x0
11554 #define   SIO_PDR_MD0_CFG_DRIVE__B                                          3
11555 #define   SIO_PDR_MD0_CFG_DRIVE__W                                          3
11556 #define   SIO_PDR_MD0_CFG_DRIVE__M                                          0x38
11557 #define   SIO_PDR_MD0_CFG_DRIVE__PRE                                        0x10
11558 #define   SIO_PDR_MD0_CFG_KEEP__B                                           6
11559 #define   SIO_PDR_MD0_CFG_KEEP__W                                           2
11560 #define   SIO_PDR_MD0_CFG_KEEP__M                                           0xC0
11561 #define   SIO_PDR_MD0_CFG_KEEP__PRE                                         0x40
11562 #define   SIO_PDR_MD0_CFG_UIO__B                                            8
11563 #define   SIO_PDR_MD0_CFG_UIO__W                                            1
11564 #define   SIO_PDR_MD0_CFG_UIO__M                                            0x100
11565 #define   SIO_PDR_MD0_CFG_UIO__PRE                                          0x0
11566 
11567 #define SIO_PDR_MD1_CFG__A                                                  0x7F002B
11568 #define SIO_PDR_MD1_CFG__W                                                  9
11569 #define SIO_PDR_MD1_CFG__M                                                  0x1FF
11570 #define SIO_PDR_MD1_CFG__PRE                                                0x50
11571 #define   SIO_PDR_MD1_CFG_MODE__B                                           0
11572 #define   SIO_PDR_MD1_CFG_MODE__W                                           3
11573 #define   SIO_PDR_MD1_CFG_MODE__M                                           0x7
11574 #define   SIO_PDR_MD1_CFG_MODE__PRE                                         0x0
11575 #define   SIO_PDR_MD1_CFG_DRIVE__B                                          3
11576 #define   SIO_PDR_MD1_CFG_DRIVE__W                                          3
11577 #define   SIO_PDR_MD1_CFG_DRIVE__M                                          0x38
11578 #define   SIO_PDR_MD1_CFG_DRIVE__PRE                                        0x10
11579 #define   SIO_PDR_MD1_CFG_KEEP__B                                           6
11580 #define   SIO_PDR_MD1_CFG_KEEP__W                                           2
11581 #define   SIO_PDR_MD1_CFG_KEEP__M                                           0xC0
11582 #define   SIO_PDR_MD1_CFG_KEEP__PRE                                         0x40
11583 #define   SIO_PDR_MD1_CFG_UIO__B                                            8
11584 #define   SIO_PDR_MD1_CFG_UIO__W                                            1
11585 #define   SIO_PDR_MD1_CFG_UIO__M                                            0x100
11586 #define   SIO_PDR_MD1_CFG_UIO__PRE                                          0x0
11587 
11588 #define SIO_PDR_MD2_CFG__A                                                  0x7F002C
11589 #define SIO_PDR_MD2_CFG__W                                                  9
11590 #define SIO_PDR_MD2_CFG__M                                                  0x1FF
11591 #define SIO_PDR_MD2_CFG__PRE                                                0x50
11592 #define   SIO_PDR_MD2_CFG_MODE__B                                           0
11593 #define   SIO_PDR_MD2_CFG_MODE__W                                           3
11594 #define   SIO_PDR_MD2_CFG_MODE__M                                           0x7
11595 #define   SIO_PDR_MD2_CFG_MODE__PRE                                         0x0
11596 #define   SIO_PDR_MD2_CFG_DRIVE__B                                          3
11597 #define   SIO_PDR_MD2_CFG_DRIVE__W                                          3
11598 #define   SIO_PDR_MD2_CFG_DRIVE__M                                          0x38
11599 #define   SIO_PDR_MD2_CFG_DRIVE__PRE                                        0x10
11600 #define   SIO_PDR_MD2_CFG_KEEP__B                                           6
11601 #define   SIO_PDR_MD2_CFG_KEEP__W                                           2
11602 #define   SIO_PDR_MD2_CFG_KEEP__M                                           0xC0
11603 #define   SIO_PDR_MD2_CFG_KEEP__PRE                                         0x40
11604 #define   SIO_PDR_MD2_CFG_UIO__B                                            8
11605 #define   SIO_PDR_MD2_CFG_UIO__W                                            1
11606 #define   SIO_PDR_MD2_CFG_UIO__M                                            0x100
11607 #define   SIO_PDR_MD2_CFG_UIO__PRE                                          0x0
11608 
11609 #define SIO_PDR_MD3_CFG__A                                                  0x7F002D
11610 #define SIO_PDR_MD3_CFG__W                                                  9
11611 #define SIO_PDR_MD3_CFG__M                                                  0x1FF
11612 #define SIO_PDR_MD3_CFG__PRE                                                0x50
11613 #define   SIO_PDR_MD3_CFG_MODE__B                                           0
11614 #define   SIO_PDR_MD3_CFG_MODE__W                                           3
11615 #define   SIO_PDR_MD3_CFG_MODE__M                                           0x7
11616 #define   SIO_PDR_MD3_CFG_MODE__PRE                                         0x0
11617 #define   SIO_PDR_MD3_CFG_DRIVE__B                                          3
11618 #define   SIO_PDR_MD3_CFG_DRIVE__W                                          3
11619 #define   SIO_PDR_MD3_CFG_DRIVE__M                                          0x38
11620 #define   SIO_PDR_MD3_CFG_DRIVE__PRE                                        0x10
11621 #define   SIO_PDR_MD3_CFG_KEEP__B                                           6
11622 #define   SIO_PDR_MD3_CFG_KEEP__W                                           2
11623 #define   SIO_PDR_MD3_CFG_KEEP__M                                           0xC0
11624 #define   SIO_PDR_MD3_CFG_KEEP__PRE                                         0x40
11625 #define   SIO_PDR_MD3_CFG_UIO__B                                            8
11626 #define   SIO_PDR_MD3_CFG_UIO__W                                            1
11627 #define   SIO_PDR_MD3_CFG_UIO__M                                            0x100
11628 #define   SIO_PDR_MD3_CFG_UIO__PRE                                          0x0
11629 
11630 #define SIO_PDR_MD4_CFG__A                                                  0x7F002F
11631 #define SIO_PDR_MD4_CFG__W                                                  9
11632 #define SIO_PDR_MD4_CFG__M                                                  0x1FF
11633 #define SIO_PDR_MD4_CFG__PRE                                                0x50
11634 #define   SIO_PDR_MD4_CFG_MODE__B                                           0
11635 #define   SIO_PDR_MD4_CFG_MODE__W                                           3
11636 #define   SIO_PDR_MD4_CFG_MODE__M                                           0x7
11637 #define   SIO_PDR_MD4_CFG_MODE__PRE                                         0x0
11638 #define   SIO_PDR_MD4_CFG_DRIVE__B                                          3
11639 #define   SIO_PDR_MD4_CFG_DRIVE__W                                          3
11640 #define   SIO_PDR_MD4_CFG_DRIVE__M                                          0x38
11641 #define   SIO_PDR_MD4_CFG_DRIVE__PRE                                        0x10
11642 #define   SIO_PDR_MD4_CFG_KEEP__B                                           6
11643 #define   SIO_PDR_MD4_CFG_KEEP__W                                           2
11644 #define   SIO_PDR_MD4_CFG_KEEP__M                                           0xC0
11645 #define   SIO_PDR_MD4_CFG_KEEP__PRE                                         0x40
11646 #define   SIO_PDR_MD4_CFG_UIO__B                                            8
11647 #define   SIO_PDR_MD4_CFG_UIO__W                                            1
11648 #define   SIO_PDR_MD4_CFG_UIO__M                                            0x100
11649 #define   SIO_PDR_MD4_CFG_UIO__PRE                                          0x0
11650 
11651 #define SIO_PDR_MD5_CFG__A                                                  0x7F0030
11652 #define SIO_PDR_MD5_CFG__W                                                  9
11653 #define SIO_PDR_MD5_CFG__M                                                  0x1FF
11654 #define SIO_PDR_MD5_CFG__PRE                                                0x50
11655 #define   SIO_PDR_MD5_CFG_MODE__B                                           0
11656 #define   SIO_PDR_MD5_CFG_MODE__W                                           3
11657 #define   SIO_PDR_MD5_CFG_MODE__M                                           0x7
11658 #define   SIO_PDR_MD5_CFG_MODE__PRE                                         0x0
11659 #define   SIO_PDR_MD5_CFG_DRIVE__B                                          3
11660 #define   SIO_PDR_MD5_CFG_DRIVE__W                                          3
11661 #define   SIO_PDR_MD5_CFG_DRIVE__M                                          0x38
11662 #define   SIO_PDR_MD5_CFG_DRIVE__PRE                                        0x10
11663 #define   SIO_PDR_MD5_CFG_KEEP__B                                           6
11664 #define   SIO_PDR_MD5_CFG_KEEP__W                                           2
11665 #define   SIO_PDR_MD5_CFG_KEEP__M                                           0xC0
11666 #define   SIO_PDR_MD5_CFG_KEEP__PRE                                         0x40
11667 #define   SIO_PDR_MD5_CFG_UIO__B                                            8
11668 #define   SIO_PDR_MD5_CFG_UIO__W                                            1
11669 #define   SIO_PDR_MD5_CFG_UIO__M                                            0x100
11670 #define   SIO_PDR_MD5_CFG_UIO__PRE                                          0x0
11671 
11672 #define SIO_PDR_MD6_CFG__A                                                  0x7F0031
11673 #define SIO_PDR_MD6_CFG__W                                                  9
11674 #define SIO_PDR_MD6_CFG__M                                                  0x1FF
11675 #define SIO_PDR_MD6_CFG__PRE                                                0x50
11676 #define   SIO_PDR_MD6_CFG_MODE__B                                           0
11677 #define   SIO_PDR_MD6_CFG_MODE__W                                           3
11678 #define   SIO_PDR_MD6_CFG_MODE__M                                           0x7
11679 #define   SIO_PDR_MD6_CFG_MODE__PRE                                         0x0
11680 #define   SIO_PDR_MD6_CFG_DRIVE__B                                          3
11681 #define   SIO_PDR_MD6_CFG_DRIVE__W                                          3
11682 #define   SIO_PDR_MD6_CFG_DRIVE__M                                          0x38
11683 #define   SIO_PDR_MD6_CFG_DRIVE__PRE                                        0x10
11684 #define   SIO_PDR_MD6_CFG_KEEP__B                                           6
11685 #define   SIO_PDR_MD6_CFG_KEEP__W                                           2
11686 #define   SIO_PDR_MD6_CFG_KEEP__M                                           0xC0
11687 #define   SIO_PDR_MD6_CFG_KEEP__PRE                                         0x40
11688 #define   SIO_PDR_MD6_CFG_UIO__B                                            8
11689 #define   SIO_PDR_MD6_CFG_UIO__W                                            1
11690 #define   SIO_PDR_MD6_CFG_UIO__M                                            0x100
11691 #define   SIO_PDR_MD6_CFG_UIO__PRE                                          0x0
11692 
11693 #define SIO_PDR_MD7_CFG__A                                                  0x7F0032
11694 #define SIO_PDR_MD7_CFG__W                                                  9
11695 #define SIO_PDR_MD7_CFG__M                                                  0x1FF
11696 #define SIO_PDR_MD7_CFG__PRE                                                0x50
11697 #define   SIO_PDR_MD7_CFG_MODE__B                                           0
11698 #define   SIO_PDR_MD7_CFG_MODE__W                                           3
11699 #define   SIO_PDR_MD7_CFG_MODE__M                                           0x7
11700 #define   SIO_PDR_MD7_CFG_MODE__PRE                                         0x0
11701 #define   SIO_PDR_MD7_CFG_DRIVE__B                                          3
11702 #define   SIO_PDR_MD7_CFG_DRIVE__W                                          3
11703 #define   SIO_PDR_MD7_CFG_DRIVE__M                                          0x38
11704 #define   SIO_PDR_MD7_CFG_DRIVE__PRE                                        0x10
11705 #define   SIO_PDR_MD7_CFG_KEEP__B                                           6
11706 #define   SIO_PDR_MD7_CFG_KEEP__W                                           2
11707 #define   SIO_PDR_MD7_CFG_KEEP__M                                           0xC0
11708 #define   SIO_PDR_MD7_CFG_KEEP__PRE                                         0x40
11709 #define   SIO_PDR_MD7_CFG_UIO__B                                            8
11710 #define   SIO_PDR_MD7_CFG_UIO__W                                            1
11711 #define   SIO_PDR_MD7_CFG_UIO__M                                            0x100
11712 #define   SIO_PDR_MD7_CFG_UIO__PRE                                          0x0
11713 
11714 #define SIO_PDR_I2C_SCL1_CFG__A                                             0x7F0033
11715 #define SIO_PDR_I2C_SCL1_CFG__W                                             9
11716 #define SIO_PDR_I2C_SCL1_CFG__M                                             0x1FF
11717 #define SIO_PDR_I2C_SCL1_CFG__PRE                                           0x11
11718 #define   SIO_PDR_I2C_SCL1_CFG_MODE__B                                      0
11719 #define   SIO_PDR_I2C_SCL1_CFG_MODE__W                                      3
11720 #define   SIO_PDR_I2C_SCL1_CFG_MODE__M                                      0x7
11721 #define   SIO_PDR_I2C_SCL1_CFG_MODE__PRE                                    0x1
11722 #define   SIO_PDR_I2C_SCL1_CFG_DRIVE__B                                     3
11723 #define   SIO_PDR_I2C_SCL1_CFG_DRIVE__W                                     3
11724 #define   SIO_PDR_I2C_SCL1_CFG_DRIVE__M                                     0x38
11725 #define   SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE                                   0x10
11726 #define   SIO_PDR_I2C_SCL1_CFG_KEEP__B                                      6
11727 #define   SIO_PDR_I2C_SCL1_CFG_KEEP__W                                      2
11728 #define   SIO_PDR_I2C_SCL1_CFG_KEEP__M                                      0xC0
11729 #define   SIO_PDR_I2C_SCL1_CFG_KEEP__PRE                                    0x0
11730 #define   SIO_PDR_I2C_SCL1_CFG_UIO__B                                       8
11731 #define   SIO_PDR_I2C_SCL1_CFG_UIO__W                                       1
11732 #define   SIO_PDR_I2C_SCL1_CFG_UIO__M                                       0x100
11733 #define   SIO_PDR_I2C_SCL1_CFG_UIO__PRE                                     0x0
11734 
11735 #define SIO_PDR_I2C_SDA1_CFG__A                                             0x7F0034
11736 #define SIO_PDR_I2C_SDA1_CFG__W                                             9
11737 #define SIO_PDR_I2C_SDA1_CFG__M                                             0x1FF
11738 #define SIO_PDR_I2C_SDA1_CFG__PRE                                           0x11
11739 #define   SIO_PDR_I2C_SDA1_CFG_MODE__B                                      0
11740 #define   SIO_PDR_I2C_SDA1_CFG_MODE__W                                      3
11741 #define   SIO_PDR_I2C_SDA1_CFG_MODE__M                                      0x7
11742 #define   SIO_PDR_I2C_SDA1_CFG_MODE__PRE                                    0x1
11743 #define   SIO_PDR_I2C_SDA1_CFG_DRIVE__B                                     3
11744 #define   SIO_PDR_I2C_SDA1_CFG_DRIVE__W                                     3
11745 #define   SIO_PDR_I2C_SDA1_CFG_DRIVE__M                                     0x38
11746 #define   SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE                                   0x10
11747 #define   SIO_PDR_I2C_SDA1_CFG_KEEP__B                                      6
11748 #define   SIO_PDR_I2C_SDA1_CFG_KEEP__W                                      2
11749 #define   SIO_PDR_I2C_SDA1_CFG_KEEP__M                                      0xC0
11750 #define   SIO_PDR_I2C_SDA1_CFG_KEEP__PRE                                    0x0
11751 #define   SIO_PDR_I2C_SDA1_CFG_UIO__B                                       8
11752 #define   SIO_PDR_I2C_SDA1_CFG_UIO__W                                       1
11753 #define   SIO_PDR_I2C_SDA1_CFG_UIO__M                                       0x100
11754 #define   SIO_PDR_I2C_SDA1_CFG_UIO__PRE                                     0x0
11755 
11756 #define SIO_PDR_VSYNC_CFG__A                                                0x7F0036
11757 #define SIO_PDR_VSYNC_CFG__W                                                9
11758 #define SIO_PDR_VSYNC_CFG__M                                                0x1FF
11759 #define SIO_PDR_VSYNC_CFG__PRE                                              0x10
11760 #define   SIO_PDR_VSYNC_CFG_MODE__B                                         0
11761 #define   SIO_PDR_VSYNC_CFG_MODE__W                                         3
11762 #define   SIO_PDR_VSYNC_CFG_MODE__M                                         0x7
11763 #define   SIO_PDR_VSYNC_CFG_MODE__PRE                                       0x0
11764 #define   SIO_PDR_VSYNC_CFG_DRIVE__B                                        3
11765 #define   SIO_PDR_VSYNC_CFG_DRIVE__W                                        3
11766 #define   SIO_PDR_VSYNC_CFG_DRIVE__M                                        0x38
11767 #define   SIO_PDR_VSYNC_CFG_DRIVE__PRE                                      0x10
11768 #define   SIO_PDR_VSYNC_CFG_KEEP__B                                         6
11769 #define   SIO_PDR_VSYNC_CFG_KEEP__W                                         2
11770 #define   SIO_PDR_VSYNC_CFG_KEEP__M                                         0xC0
11771 #define   SIO_PDR_VSYNC_CFG_KEEP__PRE                                       0x0
11772 #define   SIO_PDR_VSYNC_CFG_UIO__B                                          8
11773 #define   SIO_PDR_VSYNC_CFG_UIO__W                                          1
11774 #define   SIO_PDR_VSYNC_CFG_UIO__M                                          0x100
11775 #define   SIO_PDR_VSYNC_CFG_UIO__PRE                                        0x0
11776 
11777 #define SIO_PDR_SMA_RX_CFG__A                                               0x7F0037
11778 #define SIO_PDR_SMA_RX_CFG__W                                               9
11779 #define SIO_PDR_SMA_RX_CFG__M                                               0x1FF
11780 #define SIO_PDR_SMA_RX_CFG__PRE                                             0x10
11781 #define   SIO_PDR_SMA_RX_CFG_MODE__B                                        0
11782 #define   SIO_PDR_SMA_RX_CFG_MODE__W                                        3
11783 #define   SIO_PDR_SMA_RX_CFG_MODE__M                                        0x7
11784 #define   SIO_PDR_SMA_RX_CFG_MODE__PRE                                      0x0
11785 #define   SIO_PDR_SMA_RX_CFG_DRIVE__B                                       3
11786 #define   SIO_PDR_SMA_RX_CFG_DRIVE__W                                       3
11787 #define   SIO_PDR_SMA_RX_CFG_DRIVE__M                                       0x38
11788 #define   SIO_PDR_SMA_RX_CFG_DRIVE__PRE                                     0x10
11789 #define   SIO_PDR_SMA_RX_CFG_KEEP__B                                        6
11790 #define   SIO_PDR_SMA_RX_CFG_KEEP__W                                        2
11791 #define   SIO_PDR_SMA_RX_CFG_KEEP__M                                        0xC0
11792 #define   SIO_PDR_SMA_RX_CFG_KEEP__PRE                                      0x0
11793 #define   SIO_PDR_SMA_RX_CFG_UIO__B                                         8
11794 #define   SIO_PDR_SMA_RX_CFG_UIO__W                                         1
11795 #define   SIO_PDR_SMA_RX_CFG_UIO__M                                         0x100
11796 #define   SIO_PDR_SMA_RX_CFG_UIO__PRE                                       0x0
11797 
11798 #define SIO_PDR_SMA_TX_CFG__A                                               0x7F0038
11799 #define SIO_PDR_SMA_TX_CFG__W                                               9
11800 #define SIO_PDR_SMA_TX_CFG__M                                               0x1FF
11801 #define SIO_PDR_SMA_TX_CFG__PRE                                             0x90
11802 #define   SIO_PDR_SMA_TX_CFG_MODE__B                                        0
11803 #define   SIO_PDR_SMA_TX_CFG_MODE__W                                        3
11804 #define   SIO_PDR_SMA_TX_CFG_MODE__M                                        0x7
11805 #define   SIO_PDR_SMA_TX_CFG_MODE__PRE                                      0x0
11806 #define   SIO_PDR_SMA_TX_CFG_DRIVE__B                                       3
11807 #define   SIO_PDR_SMA_TX_CFG_DRIVE__W                                       3
11808 #define   SIO_PDR_SMA_TX_CFG_DRIVE__M                                       0x38
11809 #define   SIO_PDR_SMA_TX_CFG_DRIVE__PRE                                     0x10
11810 #define   SIO_PDR_SMA_TX_CFG_KEEP__B                                        6
11811 #define   SIO_PDR_SMA_TX_CFG_KEEP__W                                        2
11812 #define   SIO_PDR_SMA_TX_CFG_KEEP__M                                        0xC0
11813 #define   SIO_PDR_SMA_TX_CFG_KEEP__PRE                                      0x80
11814 #define   SIO_PDR_SMA_TX_CFG_UIO__B                                         8
11815 #define   SIO_PDR_SMA_TX_CFG_UIO__W                                         1
11816 #define   SIO_PDR_SMA_TX_CFG_UIO__M                                         0x100
11817 #define   SIO_PDR_SMA_TX_CFG_UIO__PRE                                       0x0
11818 
11819 #define SIO_PDR_I2C_SDA2_CFG__A                                             0x7F003F
11820 #define SIO_PDR_I2C_SDA2_CFG__W                                             9
11821 #define SIO_PDR_I2C_SDA2_CFG__M                                             0x1FF
11822 #define SIO_PDR_I2C_SDA2_CFG__PRE                                           0x11
11823 #define   SIO_PDR_I2C_SDA2_CFG_MODE__B                                      0
11824 #define   SIO_PDR_I2C_SDA2_CFG_MODE__W                                      3
11825 #define   SIO_PDR_I2C_SDA2_CFG_MODE__M                                      0x7
11826 #define   SIO_PDR_I2C_SDA2_CFG_MODE__PRE                                    0x1
11827 #define   SIO_PDR_I2C_SDA2_CFG_DRIVE__B                                     3
11828 #define   SIO_PDR_I2C_SDA2_CFG_DRIVE__W                                     3
11829 #define   SIO_PDR_I2C_SDA2_CFG_DRIVE__M                                     0x38
11830 #define   SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE                                   0x10
11831 #define   SIO_PDR_I2C_SDA2_CFG_KEEP__B                                      6
11832 #define   SIO_PDR_I2C_SDA2_CFG_KEEP__W                                      2
11833 #define   SIO_PDR_I2C_SDA2_CFG_KEEP__M                                      0xC0
11834 #define   SIO_PDR_I2C_SDA2_CFG_KEEP__PRE                                    0x0
11835 #define   SIO_PDR_I2C_SDA2_CFG_UIO__B                                       8
11836 #define   SIO_PDR_I2C_SDA2_CFG_UIO__W                                       1
11837 #define   SIO_PDR_I2C_SDA2_CFG_UIO__M                                       0x100
11838 #define   SIO_PDR_I2C_SDA2_CFG_UIO__PRE                                     0x0
11839 
11840 #define SIO_PDR_I2C_SCL2_CFG__A                                             0x7F0040
11841 #define SIO_PDR_I2C_SCL2_CFG__W                                             9
11842 #define SIO_PDR_I2C_SCL2_CFG__M                                             0x1FF
11843 #define SIO_PDR_I2C_SCL2_CFG__PRE                                           0x11
11844 #define   SIO_PDR_I2C_SCL2_CFG_MODE__B                                      0
11845 #define   SIO_PDR_I2C_SCL2_CFG_MODE__W                                      3
11846 #define   SIO_PDR_I2C_SCL2_CFG_MODE__M                                      0x7
11847 #define   SIO_PDR_I2C_SCL2_CFG_MODE__PRE                                    0x1
11848 #define   SIO_PDR_I2C_SCL2_CFG_DRIVE__B                                     3
11849 #define   SIO_PDR_I2C_SCL2_CFG_DRIVE__W                                     3
11850 #define   SIO_PDR_I2C_SCL2_CFG_DRIVE__M                                     0x38
11851 #define   SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE                                   0x10
11852 #define   SIO_PDR_I2C_SCL2_CFG_KEEP__B                                      6
11853 #define   SIO_PDR_I2C_SCL2_CFG_KEEP__W                                      2
11854 #define   SIO_PDR_I2C_SCL2_CFG_KEEP__M                                      0xC0
11855 #define   SIO_PDR_I2C_SCL2_CFG_KEEP__PRE                                    0x0
11856 #define   SIO_PDR_I2C_SCL2_CFG_UIO__B                                       8
11857 #define   SIO_PDR_I2C_SCL2_CFG_UIO__W                                       1
11858 #define   SIO_PDR_I2C_SCL2_CFG_UIO__M                                       0x100
11859 #define   SIO_PDR_I2C_SCL2_CFG_UIO__PRE                                     0x0
11860 
11861 #define SIO_PDR_I2S_CL_CFG__A                                               0x7F0041
11862 #define SIO_PDR_I2S_CL_CFG__W                                               9
11863 #define SIO_PDR_I2S_CL_CFG__M                                               0x1FF
11864 #define SIO_PDR_I2S_CL_CFG__PRE                                             0x10
11865 #define   SIO_PDR_I2S_CL_CFG_MODE__B                                        0
11866 #define   SIO_PDR_I2S_CL_CFG_MODE__W                                        3
11867 #define   SIO_PDR_I2S_CL_CFG_MODE__M                                        0x7
11868 #define   SIO_PDR_I2S_CL_CFG_MODE__PRE                                      0x0
11869 #define   SIO_PDR_I2S_CL_CFG_DRIVE__B                                       3
11870 #define   SIO_PDR_I2S_CL_CFG_DRIVE__W                                       3
11871 #define   SIO_PDR_I2S_CL_CFG_DRIVE__M                                       0x38
11872 #define   SIO_PDR_I2S_CL_CFG_DRIVE__PRE                                     0x10
11873 #define   SIO_PDR_I2S_CL_CFG_KEEP__B                                        6
11874 #define   SIO_PDR_I2S_CL_CFG_KEEP__W                                        2
11875 #define   SIO_PDR_I2S_CL_CFG_KEEP__M                                        0xC0
11876 #define   SIO_PDR_I2S_CL_CFG_KEEP__PRE                                      0x0
11877 #define   SIO_PDR_I2S_CL_CFG_UIO__B                                         8
11878 #define   SIO_PDR_I2S_CL_CFG_UIO__W                                         1
11879 #define   SIO_PDR_I2S_CL_CFG_UIO__M                                         0x100
11880 #define   SIO_PDR_I2S_CL_CFG_UIO__PRE                                       0x0
11881 
11882 #define SIO_PDR_I2S_DA_CFG__A                                               0x7F0042
11883 #define SIO_PDR_I2S_DA_CFG__W                                               9
11884 #define SIO_PDR_I2S_DA_CFG__M                                               0x1FF
11885 #define SIO_PDR_I2S_DA_CFG__PRE                                             0x10
11886 #define   SIO_PDR_I2S_DA_CFG_MODE__B                                        0
11887 #define   SIO_PDR_I2S_DA_CFG_MODE__W                                        3
11888 #define   SIO_PDR_I2S_DA_CFG_MODE__M                                        0x7
11889 #define   SIO_PDR_I2S_DA_CFG_MODE__PRE                                      0x0
11890 #define   SIO_PDR_I2S_DA_CFG_DRIVE__B                                       3
11891 #define   SIO_PDR_I2S_DA_CFG_DRIVE__W                                       3
11892 #define   SIO_PDR_I2S_DA_CFG_DRIVE__M                                       0x38
11893 #define   SIO_PDR_I2S_DA_CFG_DRIVE__PRE                                     0x10
11894 #define   SIO_PDR_I2S_DA_CFG_KEEP__B                                        6
11895 #define   SIO_PDR_I2S_DA_CFG_KEEP__W                                        2
11896 #define   SIO_PDR_I2S_DA_CFG_KEEP__M                                        0xC0
11897 #define   SIO_PDR_I2S_DA_CFG_KEEP__PRE                                      0x0
11898 #define   SIO_PDR_I2S_DA_CFG_UIO__B                                         8
11899 #define   SIO_PDR_I2S_DA_CFG_UIO__W                                         1
11900 #define   SIO_PDR_I2S_DA_CFG_UIO__M                                         0x100
11901 #define   SIO_PDR_I2S_DA_CFG_UIO__PRE                                       0x0
11902 
11903 #define SIO_PDR_GPIO_GPIO_FNC__A                                            0x7F0050
11904 #define SIO_PDR_GPIO_GPIO_FNC__W                                            2
11905 #define SIO_PDR_GPIO_GPIO_FNC__M                                            0x3
11906 #define SIO_PDR_GPIO_GPIO_FNC__PRE                                          0x0
11907 #define   SIO_PDR_GPIO_GPIO_FNC_SEL__B                                      0
11908 #define   SIO_PDR_GPIO_GPIO_FNC_SEL__W                                      2
11909 #define   SIO_PDR_GPIO_GPIO_FNC_SEL__M                                      0x3
11910 #define   SIO_PDR_GPIO_GPIO_FNC_SEL__PRE                                    0x0
11911 
11912 #define SIO_PDR_IRQN_GPIO_FNC__A                                            0x7F0051
11913 #define SIO_PDR_IRQN_GPIO_FNC__W                                            2
11914 #define SIO_PDR_IRQN_GPIO_FNC__M                                            0x3
11915 #define SIO_PDR_IRQN_GPIO_FNC__PRE                                          0x0
11916 #define   SIO_PDR_IRQN_GPIO_FNC_SEL__B                                      0
11917 #define   SIO_PDR_IRQN_GPIO_FNC_SEL__W                                      2
11918 #define   SIO_PDR_IRQN_GPIO_FNC_SEL__M                                      0x3
11919 #define   SIO_PDR_IRQN_GPIO_FNC_SEL__PRE                                    0x0
11920 
11921 #define SIO_PDR_MSTRT_GPIO_FNC__A                                           0x7F0052
11922 #define SIO_PDR_MSTRT_GPIO_FNC__W                                           2
11923 #define SIO_PDR_MSTRT_GPIO_FNC__M                                           0x3
11924 #define SIO_PDR_MSTRT_GPIO_FNC__PRE                                         0x0
11925 #define   SIO_PDR_MSTRT_GPIO_FNC_SEL__B                                     0
11926 #define   SIO_PDR_MSTRT_GPIO_FNC_SEL__W                                     2
11927 #define   SIO_PDR_MSTRT_GPIO_FNC_SEL__M                                     0x3
11928 #define   SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE                                   0x0
11929 
11930 #define SIO_PDR_MERR_GPIO_FNC__A                                            0x7F0053
11931 #define SIO_PDR_MERR_GPIO_FNC__W                                            2
11932 #define SIO_PDR_MERR_GPIO_FNC__M                                            0x3
11933 #define SIO_PDR_MERR_GPIO_FNC__PRE                                          0x0
11934 #define   SIO_PDR_MERR_GPIO_FNC_SEL__B                                      0
11935 #define   SIO_PDR_MERR_GPIO_FNC_SEL__W                                      2
11936 #define   SIO_PDR_MERR_GPIO_FNC_SEL__M                                      0x3
11937 #define   SIO_PDR_MERR_GPIO_FNC_SEL__PRE                                    0x0
11938 
11939 #define SIO_PDR_MCLK_GPIO_FNC__A                                            0x7F0054
11940 #define SIO_PDR_MCLK_GPIO_FNC__W                                            2
11941 #define SIO_PDR_MCLK_GPIO_FNC__M                                            0x3
11942 #define SIO_PDR_MCLK_GPIO_FNC__PRE                                          0x0
11943 #define   SIO_PDR_MCLK_GPIO_FNC_SEL__B                                      0
11944 #define   SIO_PDR_MCLK_GPIO_FNC_SEL__W                                      2
11945 #define   SIO_PDR_MCLK_GPIO_FNC_SEL__M                                      0x3
11946 #define   SIO_PDR_MCLK_GPIO_FNC_SEL__PRE                                    0x0
11947 
11948 #define SIO_PDR_MVAL_GPIO_FNC__A                                            0x7F0055
11949 #define SIO_PDR_MVAL_GPIO_FNC__W                                            2
11950 #define SIO_PDR_MVAL_GPIO_FNC__M                                            0x3
11951 #define SIO_PDR_MVAL_GPIO_FNC__PRE                                          0x0
11952 #define   SIO_PDR_MVAL_GPIO_FNC_SEL__B                                      0
11953 #define   SIO_PDR_MVAL_GPIO_FNC_SEL__W                                      2
11954 #define   SIO_PDR_MVAL_GPIO_FNC_SEL__M                                      0x3
11955 #define   SIO_PDR_MVAL_GPIO_FNC_SEL__PRE                                    0x0
11956 
11957 #define SIO_PDR_MD0_GPIO_FNC__A                                             0x7F0056
11958 #define SIO_PDR_MD0_GPIO_FNC__W                                             2
11959 #define SIO_PDR_MD0_GPIO_FNC__M                                             0x3
11960 #define SIO_PDR_MD0_GPIO_FNC__PRE                                           0x0
11961 #define   SIO_PDR_MD0_GPIO_FNC_SEL__B                                       0
11962 #define   SIO_PDR_MD0_GPIO_FNC_SEL__W                                       2
11963 #define   SIO_PDR_MD0_GPIO_FNC_SEL__M                                       0x3
11964 #define   SIO_PDR_MD0_GPIO_FNC_SEL__PRE                                     0x0
11965 
11966 #define SIO_PDR_MD1_GPIO_FNC__A                                             0x7F0057
11967 #define SIO_PDR_MD1_GPIO_FNC__W                                             2
11968 #define SIO_PDR_MD1_GPIO_FNC__M                                             0x3
11969 #define SIO_PDR_MD1_GPIO_FNC__PRE                                           0x0
11970 #define   SIO_PDR_MD1_GPIO_FNC_SEL__B                                       0
11971 #define   SIO_PDR_MD1_GPIO_FNC_SEL__W                                       2
11972 #define   SIO_PDR_MD1_GPIO_FNC_SEL__M                                       0x3
11973 #define   SIO_PDR_MD1_GPIO_FNC_SEL__PRE                                     0x0
11974 
11975 #define SIO_PDR_MD2_GPIO_FNC__A                                             0x7F0058
11976 #define SIO_PDR_MD2_GPIO_FNC__W                                             2
11977 #define SIO_PDR_MD2_GPIO_FNC__M                                             0x3
11978 #define SIO_PDR_MD2_GPIO_FNC__PRE                                           0x0
11979 #define   SIO_PDR_MD2_GPIO_FNC_SEL__B                                       0
11980 #define   SIO_PDR_MD2_GPIO_FNC_SEL__W                                       2
11981 #define   SIO_PDR_MD2_GPIO_FNC_SEL__M                                       0x3
11982 #define   SIO_PDR_MD2_GPIO_FNC_SEL__PRE                                     0x0
11983 
11984 #define SIO_PDR_MD3_GPIO_FNC__A                                             0x7F0059
11985 #define SIO_PDR_MD3_GPIO_FNC__W                                             2
11986 #define SIO_PDR_MD3_GPIO_FNC__M                                             0x3
11987 #define SIO_PDR_MD3_GPIO_FNC__PRE                                           0x0
11988 #define   SIO_PDR_MD3_GPIO_FNC_SEL__B                                       0
11989 #define   SIO_PDR_MD3_GPIO_FNC_SEL__W                                       2
11990 #define   SIO_PDR_MD3_GPIO_FNC_SEL__M                                       0x3
11991 #define   SIO_PDR_MD3_GPIO_FNC_SEL__PRE                                     0x0
11992 
11993 #define SIO_PDR_MD4_GPIO_FNC__A                                             0x7F005A
11994 #define SIO_PDR_MD4_GPIO_FNC__W                                             2
11995 #define SIO_PDR_MD4_GPIO_FNC__M                                             0x3
11996 #define SIO_PDR_MD4_GPIO_FNC__PRE                                           0x0
11997 #define   SIO_PDR_MD4_GPIO_FNC_SEL__B                                       0
11998 #define   SIO_PDR_MD4_GPIO_FNC_SEL__W                                       2
11999 #define   SIO_PDR_MD4_GPIO_FNC_SEL__M                                       0x3
12000 #define   SIO_PDR_MD4_GPIO_FNC_SEL__PRE                                     0x0
12001 
12002 #define SIO_PDR_MD5_GPIO_FNC__A                                             0x7F005B
12003 #define SIO_PDR_MD5_GPIO_FNC__W                                             2
12004 #define SIO_PDR_MD5_GPIO_FNC__M                                             0x3
12005 #define SIO_PDR_MD5_GPIO_FNC__PRE                                           0x0
12006 #define   SIO_PDR_MD5_GPIO_FNC_SEL__B                                       0
12007 #define   SIO_PDR_MD5_GPIO_FNC_SEL__W                                       2
12008 #define   SIO_PDR_MD5_GPIO_FNC_SEL__M                                       0x3
12009 #define   SIO_PDR_MD5_GPIO_FNC_SEL__PRE                                     0x0
12010 
12011 #define SIO_PDR_MD6_GPIO_FNC__A                                             0x7F005C
12012 #define SIO_PDR_MD6_GPIO_FNC__W                                             2
12013 #define SIO_PDR_MD6_GPIO_FNC__M                                             0x3
12014 #define SIO_PDR_MD6_GPIO_FNC__PRE                                           0x0
12015 #define   SIO_PDR_MD6_GPIO_FNC_SEL__B                                       0
12016 #define   SIO_PDR_MD6_GPIO_FNC_SEL__W                                       2
12017 #define   SIO_PDR_MD6_GPIO_FNC_SEL__M                                       0x3
12018 #define   SIO_PDR_MD6_GPIO_FNC_SEL__PRE                                     0x0
12019 
12020 #define SIO_PDR_MD7_GPIO_FNC__A                                             0x7F005D
12021 #define SIO_PDR_MD7_GPIO_FNC__W                                             2
12022 #define SIO_PDR_MD7_GPIO_FNC__M                                             0x3
12023 #define SIO_PDR_MD7_GPIO_FNC__PRE                                           0x0
12024 #define   SIO_PDR_MD7_GPIO_FNC_SEL__B                                       0
12025 #define   SIO_PDR_MD7_GPIO_FNC_SEL__W                                       2
12026 #define   SIO_PDR_MD7_GPIO_FNC_SEL__M                                       0x3
12027 #define   SIO_PDR_MD7_GPIO_FNC_SEL__PRE                                     0x0
12028 
12029 #define SIO_PDR_SMA_RX_GPIO_FNC__A                                          0x7F005E
12030 #define SIO_PDR_SMA_RX_GPIO_FNC__W                                          2
12031 #define SIO_PDR_SMA_RX_GPIO_FNC__M                                          0x3
12032 #define SIO_PDR_SMA_RX_GPIO_FNC__PRE                                        0x0
12033 #define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__B                                    0
12034 #define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__W                                    2
12035 #define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__M                                    0x3
12036 #define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE                                  0x0
12037 
12038 #define SIO_PDR_SMA_TX_GPIO_FNC__A                                          0x7F005F
12039 #define SIO_PDR_SMA_TX_GPIO_FNC__W                                          2
12040 #define SIO_PDR_SMA_TX_GPIO_FNC__M                                          0x3
12041 #define SIO_PDR_SMA_TX_GPIO_FNC__PRE                                        0x0
12042 #define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__B                                    0
12043 #define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__W                                    2
12044 #define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__M                                    0x3
12045 #define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE                                  0x0
12046 
12047 #define VSB_COMM_EXEC__A                                                    0x1C00000
12048 #define VSB_COMM_EXEC__W                                                    2
12049 #define VSB_COMM_EXEC__M                                                    0x3
12050 #define VSB_COMM_EXEC__PRE                                                  0x0
12051 #define   VSB_COMM_EXEC_STOP                                                0x0
12052 #define   VSB_COMM_EXEC_ACTIVE                                              0x1
12053 #define   VSB_COMM_EXEC_HOLD                                                0x2
12054 
12055 #define VSB_COMM_MB__A                                                      0x1C00002
12056 #define VSB_COMM_MB__W                                                      16
12057 #define VSB_COMM_MB__M                                                      0xFFFF
12058 #define VSB_COMM_MB__PRE                                                    0x0
12059 #define VSB_COMM_INT_REQ__A                                                 0x1C00003
12060 #define VSB_COMM_INT_REQ__W                                                 1
12061 #define VSB_COMM_INT_REQ__M                                                 0x1
12062 #define VSB_COMM_INT_REQ__PRE                                               0x0
12063 
12064 #define   VSB_COMM_INT_REQ_TOP_INT_REQ__B                                   0
12065 #define   VSB_COMM_INT_REQ_TOP_INT_REQ__W                                   1
12066 #define   VSB_COMM_INT_REQ_TOP_INT_REQ__M                                   0x1
12067 #define   VSB_COMM_INT_REQ_TOP_INT_REQ__PRE                                 0x0
12068 
12069 #define VSB_COMM_INT_STA__A                                                 0x1C00005
12070 #define VSB_COMM_INT_STA__W                                                 16
12071 #define VSB_COMM_INT_STA__M                                                 0xFFFF
12072 #define VSB_COMM_INT_STA__PRE                                               0x0
12073 
12074 #define VSB_COMM_INT_MSK__A                                                 0x1C00006
12075 #define VSB_COMM_INT_MSK__W                                                 16
12076 #define VSB_COMM_INT_MSK__M                                                 0xFFFF
12077 #define VSB_COMM_INT_MSK__PRE                                               0x0
12078 
12079 #define VSB_COMM_INT_STM__A                                                 0x1C00007
12080 #define VSB_COMM_INT_STM__W                                                 16
12081 #define VSB_COMM_INT_STM__M                                                 0xFFFF
12082 #define VSB_COMM_INT_STM__PRE                                               0x0
12083 
12084 #define VSB_TOP_COMM_EXEC__A                                                0x1C10000
12085 #define VSB_TOP_COMM_EXEC__W                                                2
12086 #define VSB_TOP_COMM_EXEC__M                                                0x3
12087 #define VSB_TOP_COMM_EXEC__PRE                                              0x0
12088 #define   VSB_TOP_COMM_EXEC_STOP                                            0x0
12089 #define   VSB_TOP_COMM_EXEC_ACTIVE                                          0x1
12090 #define   VSB_TOP_COMM_EXEC_HOLD                                            0x2
12091 
12092 #define VSB_TOP_COMM_MB__A                                                  0x1C10002
12093 #define VSB_TOP_COMM_MB__W                                                  10
12094 #define VSB_TOP_COMM_MB__M                                                  0x3FF
12095 #define VSB_TOP_COMM_MB__PRE                                                0x0
12096 
12097 #define   VSB_TOP_COMM_MB_CTL__B                                            0
12098 #define   VSB_TOP_COMM_MB_CTL__W                                            1
12099 #define   VSB_TOP_COMM_MB_CTL__M                                            0x1
12100 #define   VSB_TOP_COMM_MB_CTL__PRE                                          0x0
12101 #define     VSB_TOP_COMM_MB_CTL_CTL_OFF                                     0x0
12102 #define     VSB_TOP_COMM_MB_CTL_CTL_ON                                      0x1
12103 
12104 #define   VSB_TOP_COMM_MB_OBS__B                                            1
12105 #define   VSB_TOP_COMM_MB_OBS__W                                            1
12106 #define   VSB_TOP_COMM_MB_OBS__M                                            0x2
12107 #define   VSB_TOP_COMM_MB_OBS__PRE                                          0x0
12108 #define     VSB_TOP_COMM_MB_OBS_OBS_OFF                                     0x0
12109 #define     VSB_TOP_COMM_MB_OBS_OBS_ON                                      0x2
12110 
12111 #define   VSB_TOP_COMM_MB_MUX_CTL__B                                        2
12112 #define   VSB_TOP_COMM_MB_MUX_CTL__W                                        4
12113 #define   VSB_TOP_COMM_MB_MUX_CTL__M                                        0x3C
12114 #define   VSB_TOP_COMM_MB_MUX_CTL__PRE                                      0x0
12115 
12116 #define   VSB_TOP_COMM_MB_MUX_OBS__B                                        6
12117 #define   VSB_TOP_COMM_MB_MUX_OBS__W                                        4
12118 #define   VSB_TOP_COMM_MB_MUX_OBS__M                                        0x3C0
12119 #define   VSB_TOP_COMM_MB_MUX_OBS__PRE                                      0x0
12120 #define     VSB_TOP_COMM_MB_MUX_OBS_VSB_FEC                                 0x0
12121 #define     VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM                                 0x40
12122 #define     VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM_AMPLITUDE                       0x80
12123 #define     VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_1                             0xC0
12124 #define     VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2                             0x100
12125 #define     VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_1                               0x140
12126 #define     VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_2                               0x180
12127 #define     VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1                               0x1C0
12128 #define     VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2                               0x200
12129 
12130 #define VSB_TOP_COMM_INT_REQ__A                                             0x1C10003
12131 #define VSB_TOP_COMM_INT_REQ__W                                             1
12132 #define VSB_TOP_COMM_INT_REQ__M                                             0x1
12133 #define VSB_TOP_COMM_INT_REQ__PRE                                           0x0
12134 #define VSB_TOP_COMM_INT_STA__A                                             0x1C10005
12135 #define VSB_TOP_COMM_INT_STA__W                                             6
12136 #define VSB_TOP_COMM_INT_STA__M                                             0x3F
12137 #define VSB_TOP_COMM_INT_STA__PRE                                           0x0
12138 
12139 #define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__B                             0
12140 #define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__W                             1
12141 #define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__M                             0x1
12142 #define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__PRE                           0x0
12143 
12144 #define   VSB_TOP_COMM_INT_STA_LOCK_STA__B                                  1
12145 #define   VSB_TOP_COMM_INT_STA_LOCK_STA__W                                  1
12146 #define   VSB_TOP_COMM_INT_STA_LOCK_STA__M                                  0x2
12147 #define   VSB_TOP_COMM_INT_STA_LOCK_STA__PRE                                0x0
12148 
12149 #define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__B                                2
12150 #define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__W                                1
12151 #define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__M                                0x4
12152 #define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__PRE                              0x0
12153 
12154 #define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__B                             3
12155 #define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__W                             1
12156 #define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__M                             0x8
12157 #define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__PRE                           0x0
12158 
12159 #define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__B                           4
12160 #define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__W                           1
12161 #define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__M                           0x10
12162 #define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__PRE                         0x0
12163 
12164 #define   VSB_TOP_COMM_INT_STA_MERSER_STA__B                                5
12165 #define   VSB_TOP_COMM_INT_STA_MERSER_STA__W                                1
12166 #define   VSB_TOP_COMM_INT_STA_MERSER_STA__M                                0x20
12167 #define   VSB_TOP_COMM_INT_STA_MERSER_STA__PRE                              0x0
12168 
12169 #define VSB_TOP_COMM_INT_MSK__A                                             0x1C10006
12170 #define VSB_TOP_COMM_INT_MSK__W                                             6
12171 #define VSB_TOP_COMM_INT_MSK__M                                             0x3F
12172 #define VSB_TOP_COMM_INT_MSK__PRE                                           0x0
12173 
12174 #define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__B                             0
12175 #define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__W                             1
12176 #define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__M                             0x1
12177 #define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__PRE                           0x0
12178 
12179 #define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__B                                  1
12180 #define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__W                                  1
12181 #define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__M                                  0x2
12182 #define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__PRE                                0x0
12183 
12184 #define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__B                                2
12185 #define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__W                                1
12186 #define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__M                                0x4
12187 #define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__PRE                              0x0
12188 
12189 #define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__B                             3
12190 #define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__W                             1
12191 #define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__M                             0x8
12192 #define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__PRE                           0x0
12193 
12194 #define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__B                           4
12195 #define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__W                           1
12196 #define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__M                           0x10
12197 #define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__PRE                         0x0
12198 
12199 #define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__B                                5
12200 #define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__W                                1
12201 #define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__M                                0x20
12202 #define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__PRE                              0x0
12203 
12204 #define VSB_TOP_COMM_INT_STM__A                                             0x1C10007
12205 #define VSB_TOP_COMM_INT_STM__W                                             6
12206 #define VSB_TOP_COMM_INT_STM__M                                             0x3F
12207 #define VSB_TOP_COMM_INT_STM__PRE                                           0x0
12208 
12209 #define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__B                             0
12210 #define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__W                             1
12211 #define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__M                             0x1
12212 #define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__PRE                           0x0
12213 
12214 #define   VSB_TOP_COMM_INT_STM_LOCK_STM__B                                  1
12215 #define   VSB_TOP_COMM_INT_STM_LOCK_STM__W                                  1
12216 #define   VSB_TOP_COMM_INT_STM_LOCK_STM__M                                  0x2
12217 #define   VSB_TOP_COMM_INT_STM_LOCK_STM__PRE                                0x0
12218 
12219 #define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__B                                2
12220 #define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__W                                1
12221 #define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__M                                0x4
12222 #define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__PRE                              0x0
12223 
12224 #define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__B                             3
12225 #define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__W                             1
12226 #define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__M                             0x8
12227 #define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__PRE                           0x0
12228 
12229 #define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__B                           4
12230 #define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__W                           1
12231 #define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__M                           0x10
12232 #define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__PRE                         0x0
12233 
12234 #define   VSB_TOP_COMM_INT_STM_MERSER_STM__B                                5
12235 #define   VSB_TOP_COMM_INT_STM_MERSER_STM__W                                1
12236 #define   VSB_TOP_COMM_INT_STM_MERSER_STM__M                                0x20
12237 #define   VSB_TOP_COMM_INT_STM_MERSER_STM__PRE                              0x0
12238 
12239 #define VSB_TOP_CKGN1ACQ__A                                                 0x1C10010
12240 #define VSB_TOP_CKGN1ACQ__W                                                 8
12241 #define VSB_TOP_CKGN1ACQ__M                                                 0xFF
12242 #define VSB_TOP_CKGN1ACQ__PRE                                               0x4
12243 
12244 #define VSB_TOP_CKGN1TRK__A                                                 0x1C10011
12245 #define VSB_TOP_CKGN1TRK__W                                                 8
12246 #define VSB_TOP_CKGN1TRK__M                                                 0xFF
12247 #define VSB_TOP_CKGN1TRK__PRE                                               0x0
12248 
12249 #define VSB_TOP_CKGN2ACQ__A                                                 0x1C10012
12250 #define VSB_TOP_CKGN2ACQ__W                                                 8
12251 #define VSB_TOP_CKGN2ACQ__M                                                 0xFF
12252 #define VSB_TOP_CKGN2ACQ__PRE                                               0x2
12253 
12254 #define VSB_TOP_CKGN2TRK__A                                                 0x1C10013
12255 #define VSB_TOP_CKGN2TRK__W                                                 8
12256 #define VSB_TOP_CKGN2TRK__M                                                 0xFF
12257 #define VSB_TOP_CKGN2TRK__PRE                                               0x1
12258 
12259 #define VSB_TOP_CKGN3__A                                                    0x1C10014
12260 #define VSB_TOP_CKGN3__W                                                    8
12261 #define VSB_TOP_CKGN3__M                                                    0xFF
12262 #define VSB_TOP_CKGN3__PRE                                                  0x5
12263 
12264 #define VSB_TOP_CYGN1ACQ__A                                                 0x1C10015
12265 #define VSB_TOP_CYGN1ACQ__W                                                 8
12266 #define VSB_TOP_CYGN1ACQ__M                                                 0xFF
12267 #define VSB_TOP_CYGN1ACQ__PRE                                               0x3
12268 
12269 #define VSB_TOP_CYGN1TRK__A                                                 0x1C10016
12270 #define VSB_TOP_CYGN1TRK__W                                                 8
12271 #define VSB_TOP_CYGN1TRK__M                                                 0xFF
12272 #define VSB_TOP_CYGN1TRK__PRE                                               0x0
12273 
12274 #define VSB_TOP_CYGN2ACQ__A                                                 0x1C10017
12275 #define VSB_TOP_CYGN2ACQ__W                                                 8
12276 #define VSB_TOP_CYGN2ACQ__M                                                 0xFF
12277 #define VSB_TOP_CYGN2ACQ__PRE                                               0x3
12278 
12279 #define VSB_TOP_CYGN2TRK__A                                                 0x1C10018
12280 #define VSB_TOP_CYGN2TRK__W                                                 8
12281 #define VSB_TOP_CYGN2TRK__M                                                 0xFF
12282 #define VSB_TOP_CYGN2TRK__PRE                                               0x2
12283 
12284 #define VSB_TOP_CYGN3__A                                                    0x1C10019
12285 #define VSB_TOP_CYGN3__W                                                    8
12286 #define VSB_TOP_CYGN3__M                                                    0xFF
12287 #define VSB_TOP_CYGN3__PRE                                                  0x6
12288 #define VSB_TOP_SYNCCTRLWORD__A                                             0x1C1001A
12289 #define VSB_TOP_SYNCCTRLWORD__W                                             5
12290 #define VSB_TOP_SYNCCTRLWORD__M                                             0x1F
12291 #define VSB_TOP_SYNCCTRLWORD__PRE                                           0x0
12292 
12293 #define   VSB_TOP_SYNCCTRLWORD_PRST__B                                      0
12294 #define   VSB_TOP_SYNCCTRLWORD_PRST__W                                      1
12295 #define   VSB_TOP_SYNCCTRLWORD_PRST__M                                      0x1
12296 #define   VSB_TOP_SYNCCTRLWORD_PRST__PRE                                    0x0
12297 
12298 #define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__B                                   1
12299 #define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__W                                   1
12300 #define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__M                                   0x2
12301 #define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__PRE                                 0x0
12302 
12303 #define   VSB_TOP_SYNCCTRLWORD_INVCNST__B                                   2
12304 #define   VSB_TOP_SYNCCTRLWORD_INVCNST__W                                   1
12305 #define   VSB_TOP_SYNCCTRLWORD_INVCNST__M                                   0x4
12306 #define   VSB_TOP_SYNCCTRLWORD_INVCNST__PRE                                 0x0
12307 
12308 #define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__B                                 3
12309 #define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__W                                 1
12310 #define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__M                                 0x8
12311 #define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__PRE                               0x0
12312 
12313 #define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__B                               4
12314 #define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__W                               1
12315 #define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M                               0x10
12316 #define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE                             0x0
12317 
12318 #define VSB_TOP_MAINSMUP__A                                                 0x1C1001B
12319 #define VSB_TOP_MAINSMUP__W                                                 8
12320 #define VSB_TOP_MAINSMUP__M                                                 0xFF
12321 #define VSB_TOP_MAINSMUP__PRE                                               0xFF
12322 
12323 #define VSB_TOP_EQSMUP__A                                                   0x1C1001C
12324 #define VSB_TOP_EQSMUP__W                                                   8
12325 #define VSB_TOP_EQSMUP__M                                                   0xFF
12326 #define VSB_TOP_EQSMUP__PRE                                                 0xFF
12327 #define VSB_TOP_SYSMUXCTRL__A                                               0x1C1001D
12328 #define VSB_TOP_SYSMUXCTRL__W                                               13
12329 #define VSB_TOP_SYSMUXCTRL__M                                               0x1FFF
12330 #define VSB_TOP_SYSMUXCTRL__PRE                                             0x0
12331 
12332 #define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__B                                 0
12333 #define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__W                                 1
12334 #define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__M                                 0x1
12335 #define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__PRE                               0x0
12336 
12337 #define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__B                             1
12338 #define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__W                             1
12339 #define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__M                             0x2
12340 #define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__PRE                           0x0
12341 
12342 #define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__B                            2
12343 #define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__W                            1
12344 #define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__M                            0x4
12345 #define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__PRE                          0x0
12346 
12347 #define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__B                        3
12348 #define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__W                        1
12349 #define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__M                        0x8
12350 #define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__PRE                      0x0
12351 
12352 #define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__B                            4
12353 #define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__W                            1
12354 #define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__M                            0x10
12355 #define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__PRE                          0x0
12356 
12357 #define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__B                        5
12358 #define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__W                        1
12359 #define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__M                        0x20
12360 #define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__PRE                      0x0
12361 
12362 #define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__B                            6
12363 #define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__W                            1
12364 #define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__M                            0x40
12365 #define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__PRE                          0x0
12366 
12367 #define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__B                        7
12368 #define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__W                        1
12369 #define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__M                        0x80
12370 #define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__PRE                      0x0
12371 
12372 #define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__B                              8
12373 #define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__W                              4
12374 #define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__M                              0xF00
12375 #define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__PRE                            0x0
12376 
12377 #define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__B                          12
12378 #define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__W                          1
12379 #define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__M                          0x1000
12380 #define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__PRE                        0x0
12381 
12382 #define VSB_TOP_SNRTH_RCA1__A                                               0x1C1001E
12383 #define VSB_TOP_SNRTH_RCA1__W                                               8
12384 #define VSB_TOP_SNRTH_RCA1__M                                               0xFF
12385 #define VSB_TOP_SNRTH_RCA1__PRE                                             0x53
12386 
12387 #define   VSB_TOP_SNRTH_RCA1_DN__B                                          0
12388 #define   VSB_TOP_SNRTH_RCA1_DN__W                                          4
12389 #define   VSB_TOP_SNRTH_RCA1_DN__M                                          0xF
12390 #define   VSB_TOP_SNRTH_RCA1_DN__PRE                                        0x3
12391 
12392 #define   VSB_TOP_SNRTH_RCA1_UP__B                                          4
12393 #define   VSB_TOP_SNRTH_RCA1_UP__W                                          4
12394 #define   VSB_TOP_SNRTH_RCA1_UP__M                                          0xF0
12395 #define   VSB_TOP_SNRTH_RCA1_UP__PRE                                        0x50
12396 
12397 #define VSB_TOP_SNRTH_RCA2__A                                               0x1C1001F
12398 #define VSB_TOP_SNRTH_RCA2__W                                               8
12399 #define VSB_TOP_SNRTH_RCA2__M                                               0xFF
12400 #define VSB_TOP_SNRTH_RCA2__PRE                                             0x75
12401 
12402 #define   VSB_TOP_SNRTH_RCA2_DN__B                                          0
12403 #define   VSB_TOP_SNRTH_RCA2_DN__W                                          4
12404 #define   VSB_TOP_SNRTH_RCA2_DN__M                                          0xF
12405 #define   VSB_TOP_SNRTH_RCA2_DN__PRE                                        0x5
12406 
12407 #define   VSB_TOP_SNRTH_RCA2_UP__B                                          4
12408 #define   VSB_TOP_SNRTH_RCA2_UP__W                                          4
12409 #define   VSB_TOP_SNRTH_RCA2_UP__M                                          0xF0
12410 #define   VSB_TOP_SNRTH_RCA2_UP__PRE                                        0x70
12411 
12412 #define VSB_TOP_SNRTH_DDM1__A                                               0x1C10020
12413 #define VSB_TOP_SNRTH_DDM1__W                                               8
12414 #define VSB_TOP_SNRTH_DDM1__M                                               0xFF
12415 #define VSB_TOP_SNRTH_DDM1__PRE                                             0xCA
12416 
12417 #define   VSB_TOP_SNRTH_DDM1_DN__B                                          0
12418 #define   VSB_TOP_SNRTH_DDM1_DN__W                                          4
12419 #define   VSB_TOP_SNRTH_DDM1_DN__M                                          0xF
12420 #define   VSB_TOP_SNRTH_DDM1_DN__PRE                                        0xA
12421 
12422 #define   VSB_TOP_SNRTH_DDM1_UP__B                                          4
12423 #define   VSB_TOP_SNRTH_DDM1_UP__W                                          4
12424 #define   VSB_TOP_SNRTH_DDM1_UP__M                                          0xF0
12425 #define   VSB_TOP_SNRTH_DDM1_UP__PRE                                        0xC0
12426 
12427 #define VSB_TOP_SNRTH_DDM2__A                                               0x1C10021
12428 #define VSB_TOP_SNRTH_DDM2__W                                               8
12429 #define VSB_TOP_SNRTH_DDM2__M                                               0xFF
12430 #define VSB_TOP_SNRTH_DDM2__PRE                                             0xCA
12431 
12432 #define   VSB_TOP_SNRTH_DDM2_DN__B                                          0
12433 #define   VSB_TOP_SNRTH_DDM2_DN__W                                          4
12434 #define   VSB_TOP_SNRTH_DDM2_DN__M                                          0xF
12435 #define   VSB_TOP_SNRTH_DDM2_DN__PRE                                        0xA
12436 
12437 #define   VSB_TOP_SNRTH_DDM2_UP__B                                          4
12438 #define   VSB_TOP_SNRTH_DDM2_UP__W                                          4
12439 #define   VSB_TOP_SNRTH_DDM2_UP__M                                          0xF0
12440 #define   VSB_TOP_SNRTH_DDM2_UP__PRE                                        0xC0
12441 
12442 #define VSB_TOP_SNRTH_PT__A                                                 0x1C10022
12443 #define VSB_TOP_SNRTH_PT__W                                                 8
12444 #define VSB_TOP_SNRTH_PT__M                                                 0xFF
12445 #define VSB_TOP_SNRTH_PT__PRE                                               0xD8
12446 
12447 #define   VSB_TOP_SNRTH_PT_DN__B                                            0
12448 #define   VSB_TOP_SNRTH_PT_DN__W                                            4
12449 #define   VSB_TOP_SNRTH_PT_DN__M                                            0xF
12450 #define   VSB_TOP_SNRTH_PT_DN__PRE                                          0x8
12451 
12452 #define   VSB_TOP_SNRTH_PT_UP__B                                            4
12453 #define   VSB_TOP_SNRTH_PT_UP__W                                            4
12454 #define   VSB_TOP_SNRTH_PT_UP__M                                            0xF0
12455 #define   VSB_TOP_SNRTH_PT_UP__PRE                                          0xD0
12456 
12457 #define VSB_TOP_CYSMSTATES__A                                               0x1C10023
12458 #define VSB_TOP_CYSMSTATES__W                                               8
12459 #define VSB_TOP_CYSMSTATES__M                                               0xFF
12460 #define VSB_TOP_CYSMSTATES__PRE                                             0x0
12461 
12462 #define   VSB_TOP_CYSMSTATES_SYSST__B                                       0
12463 #define   VSB_TOP_CYSMSTATES_SYSST__W                                       4
12464 #define   VSB_TOP_CYSMSTATES_SYSST__M                                       0xF
12465 #define   VSB_TOP_CYSMSTATES_SYSST__PRE                                     0x0
12466 
12467 #define   VSB_TOP_CYSMSTATES_EQST__B                                        4
12468 #define   VSB_TOP_CYSMSTATES_EQST__W                                        4
12469 #define   VSB_TOP_CYSMSTATES_EQST__M                                        0xF0
12470 #define   VSB_TOP_CYSMSTATES_EQST__PRE                                      0x0
12471 
12472 #define VSB_TOP_SMALL_NOTCH_CONTROL__A                                      0x1C10024
12473 #define VSB_TOP_SMALL_NOTCH_CONTROL__W                                      8
12474 #define VSB_TOP_SMALL_NOTCH_CONTROL__M                                      0xFF
12475 #define VSB_TOP_SMALL_NOTCH_CONTROL__PRE                                    0x0
12476 
12477 #define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__B                                 0
12478 #define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__W                                 1
12479 #define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__M                                 0x1
12480 #define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__PRE                               0x0
12481 
12482 #define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__B                            1
12483 #define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__W                            1
12484 #define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M                            0x2
12485 #define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__PRE                          0x0
12486 
12487 #define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__B                            2
12488 #define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__W                            1
12489 #define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__M                            0x4
12490 #define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__PRE                          0x0
12491 
12492 #define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__B                              3
12493 #define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__W                              4
12494 #define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__M                              0x78
12495 #define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__PRE                            0x0
12496 
12497 #define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__B                         7
12498 #define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__W                         1
12499 #define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M                         0x80
12500 #define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE                       0x0
12501 
12502 #define VSB_TOP_TAPREADCYC__A                                               0x1C10025
12503 #define VSB_TOP_TAPREADCYC__W                                               9
12504 #define VSB_TOP_TAPREADCYC__M                                               0x1FF
12505 #define VSB_TOP_TAPREADCYC__PRE                                             0x1
12506 
12507 #define VSB_TOP_VALIDPKLVL__A                                               0x1C10026
12508 #define VSB_TOP_VALIDPKLVL__W                                               13
12509 #define VSB_TOP_VALIDPKLVL__M                                               0x1FFF
12510 #define VSB_TOP_VALIDPKLVL__PRE                                             0x100
12511 
12512 #define VSB_TOP_CENTROID_FINE_DELAY__A                                      0x1C10027
12513 #define VSB_TOP_CENTROID_FINE_DELAY__W                                      10
12514 #define VSB_TOP_CENTROID_FINE_DELAY__M                                      0x3FF
12515 #define VSB_TOP_CENTROID_FINE_DELAY__PRE                                    0xFF
12516 
12517 #define VSB_TOP_CENTROID_SMACH_DELAY__A                                     0x1C10028
12518 #define VSB_TOP_CENTROID_SMACH_DELAY__W                                     10
12519 #define VSB_TOP_CENTROID_SMACH_DELAY__M                                     0x3FF
12520 #define VSB_TOP_CENTROID_SMACH_DELAY__PRE                                   0x1FF
12521 
12522 #define VSB_TOP_SNR__A                                                      0x1C10029
12523 #define VSB_TOP_SNR__W                                                      14
12524 #define VSB_TOP_SNR__M                                                      0x3FFF
12525 #define VSB_TOP_SNR__PRE                                                    0x0
12526 #define VSB_TOP_LOCKSTATUS__A                                               0x1C1002A
12527 #define VSB_TOP_LOCKSTATUS__W                                               7
12528 #define VSB_TOP_LOCKSTATUS__M                                               0x7F
12529 #define VSB_TOP_LOCKSTATUS__PRE                                             0x0
12530 
12531 #define   VSB_TOP_LOCKSTATUS_VSBMODE__B                                     0
12532 #define   VSB_TOP_LOCKSTATUS_VSBMODE__W                                     4
12533 #define   VSB_TOP_LOCKSTATUS_VSBMODE__M                                     0xF
12534 #define   VSB_TOP_LOCKSTATUS_VSBMODE__PRE                                   0x0
12535 
12536 #define   VSB_TOP_LOCKSTATUS_FRMLOCK__B                                     4
12537 #define   VSB_TOP_LOCKSTATUS_FRMLOCK__W                                     1
12538 #define   VSB_TOP_LOCKSTATUS_FRMLOCK__M                                     0x10
12539 #define   VSB_TOP_LOCKSTATUS_FRMLOCK__PRE                                   0x0
12540 
12541 #define   VSB_TOP_LOCKSTATUS_CYLOCK__B                                      5
12542 #define   VSB_TOP_LOCKSTATUS_CYLOCK__W                                      1
12543 #define   VSB_TOP_LOCKSTATUS_CYLOCK__M                                      0x20
12544 #define   VSB_TOP_LOCKSTATUS_CYLOCK__PRE                                    0x0
12545 
12546 #define   VSB_TOP_LOCKSTATUS_DDMON__B                                       6
12547 #define   VSB_TOP_LOCKSTATUS_DDMON__W                                       1
12548 #define   VSB_TOP_LOCKSTATUS_DDMON__M                                       0x40
12549 #define   VSB_TOP_LOCKSTATUS_DDMON__PRE                                     0x0
12550 
12551 #define VSB_TOP_CTST__A                                                     0x1C1002B
12552 #define VSB_TOP_CTST__W                                                     4
12553 #define VSB_TOP_CTST__M                                                     0xF
12554 #define VSB_TOP_CTST__PRE                                                   0x0
12555 #define VSB_TOP_EQSMRSTCTRL__A                                              0x1C1002C
12556 #define VSB_TOP_EQSMRSTCTRL__W                                              7
12557 #define VSB_TOP_EQSMRSTCTRL__M                                              0x7F
12558 #define VSB_TOP_EQSMRSTCTRL__PRE                                            0x0
12559 
12560 #define   VSB_TOP_EQSMRSTCTRL_RCAON__B                                      0
12561 #define   VSB_TOP_EQSMRSTCTRL_RCAON__W                                      1
12562 #define   VSB_TOP_EQSMRSTCTRL_RCAON__M                                      0x1
12563 #define   VSB_TOP_EQSMRSTCTRL_RCAON__PRE                                    0x0
12564 
12565 #define   VSB_TOP_EQSMRSTCTRL_DFEON__B                                      1
12566 #define   VSB_TOP_EQSMRSTCTRL_DFEON__W                                      1
12567 #define   VSB_TOP_EQSMRSTCTRL_DFEON__M                                      0x2
12568 #define   VSB_TOP_EQSMRSTCTRL_DFEON__PRE                                    0x0
12569 
12570 #define   VSB_TOP_EQSMRSTCTRL_DDMEN1__B                                     2
12571 #define   VSB_TOP_EQSMRSTCTRL_DDMEN1__W                                     1
12572 #define   VSB_TOP_EQSMRSTCTRL_DDMEN1__M                                     0x4
12573 #define   VSB_TOP_EQSMRSTCTRL_DDMEN1__PRE                                   0x0
12574 
12575 #define   VSB_TOP_EQSMRSTCTRL_DDMEN2__B                                     3
12576 #define   VSB_TOP_EQSMRSTCTRL_DDMEN2__W                                     1
12577 #define   VSB_TOP_EQSMRSTCTRL_DDMEN2__M                                     0x8
12578 #define   VSB_TOP_EQSMRSTCTRL_DDMEN2__PRE                                   0x0
12579 
12580 #define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__B                                  4
12581 #define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__W                                  1
12582 #define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__M                                  0x10
12583 #define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__PRE                                0x0
12584 
12585 #define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__B                                 5
12586 #define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__W                                 1
12587 #define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__M                                 0x20
12588 #define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__PRE                               0x0
12589 
12590 #define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__B                            6
12591 #define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__W                            1
12592 #define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__M                            0x40
12593 #define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__PRE                          0x0
12594 
12595 #define VSB_TOP_EQSMTRNCTRL__A                                              0x1C1002D
12596 #define VSB_TOP_EQSMTRNCTRL__W                                              7
12597 #define VSB_TOP_EQSMTRNCTRL__M                                              0x7F
12598 #define VSB_TOP_EQSMTRNCTRL__PRE                                            0x40
12599 
12600 #define   VSB_TOP_EQSMTRNCTRL_RCAON__B                                      0
12601 #define   VSB_TOP_EQSMTRNCTRL_RCAON__W                                      1
12602 #define   VSB_TOP_EQSMTRNCTRL_RCAON__M                                      0x1
12603 #define   VSB_TOP_EQSMTRNCTRL_RCAON__PRE                                    0x0
12604 
12605 #define   VSB_TOP_EQSMTRNCTRL_DFEON__B                                      1
12606 #define   VSB_TOP_EQSMTRNCTRL_DFEON__W                                      1
12607 #define   VSB_TOP_EQSMTRNCTRL_DFEON__M                                      0x2
12608 #define   VSB_TOP_EQSMTRNCTRL_DFEON__PRE                                    0x0
12609 
12610 #define   VSB_TOP_EQSMTRNCTRL_DDMEN1__B                                     2
12611 #define   VSB_TOP_EQSMTRNCTRL_DDMEN1__W                                     1
12612 #define   VSB_TOP_EQSMTRNCTRL_DDMEN1__M                                     0x4
12613 #define   VSB_TOP_EQSMTRNCTRL_DDMEN1__PRE                                   0x0
12614 
12615 #define   VSB_TOP_EQSMTRNCTRL_DDMEN2__B                                     3
12616 #define   VSB_TOP_EQSMTRNCTRL_DDMEN2__W                                     1
12617 #define   VSB_TOP_EQSMTRNCTRL_DDMEN2__M                                     0x8
12618 #define   VSB_TOP_EQSMTRNCTRL_DDMEN2__PRE                                   0x0
12619 
12620 #define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__B                                  4
12621 #define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__W                                  1
12622 #define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__M                                  0x10
12623 #define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__PRE                                0x0
12624 
12625 #define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__B                                 5
12626 #define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__W                                 1
12627 #define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__M                                 0x20
12628 #define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__PRE                               0x0
12629 
12630 #define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__B                            6
12631 #define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__W                            1
12632 #define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__M                            0x40
12633 #define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__PRE                          0x40
12634 
12635 #define VSB_TOP_EQSMRCA1CTRL__A                                             0x1C1002E
12636 #define VSB_TOP_EQSMRCA1CTRL__W                                             7
12637 #define VSB_TOP_EQSMRCA1CTRL__M                                             0x7F
12638 #define VSB_TOP_EQSMRCA1CTRL__PRE                                           0x1
12639 
12640 #define   VSB_TOP_EQSMRCA1CTRL_RCAON__B                                     0
12641 #define   VSB_TOP_EQSMRCA1CTRL_RCAON__W                                     1
12642 #define   VSB_TOP_EQSMRCA1CTRL_RCAON__M                                     0x1
12643 #define   VSB_TOP_EQSMRCA1CTRL_RCAON__PRE                                   0x1
12644 
12645 #define   VSB_TOP_EQSMRCA1CTRL_DFEON__B                                     1
12646 #define   VSB_TOP_EQSMRCA1CTRL_DFEON__W                                     1
12647 #define   VSB_TOP_EQSMRCA1CTRL_DFEON__M                                     0x2
12648 #define   VSB_TOP_EQSMRCA1CTRL_DFEON__PRE                                   0x0
12649 
12650 #define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__B                                    2
12651 #define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__W                                    1
12652 #define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__M                                    0x4
12653 #define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__PRE                                  0x0
12654 
12655 #define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__B                                    3
12656 #define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__W                                    1
12657 #define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__M                                    0x8
12658 #define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__PRE                                  0x0
12659 
12660 #define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__B                                 4
12661 #define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__W                                 1
12662 #define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__M                                 0x10
12663 #define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__PRE                               0x0
12664 
12665 #define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__B                                5
12666 #define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__W                                1
12667 #define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__M                                0x20
12668 #define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__PRE                              0x0
12669 
12670 #define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__B                           6
12671 #define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__W                           1
12672 #define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__M                           0x40
12673 #define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__PRE                         0x0
12674 
12675 #define VSB_TOP_EQSMRCA2CTRL__A                                             0x1C1002F
12676 #define VSB_TOP_EQSMRCA2CTRL__W                                             7
12677 #define VSB_TOP_EQSMRCA2CTRL__M                                             0x7F
12678 #define VSB_TOP_EQSMRCA2CTRL__PRE                                           0x3
12679 
12680 #define   VSB_TOP_EQSMRCA2CTRL_RCAON__B                                     0
12681 #define   VSB_TOP_EQSMRCA2CTRL_RCAON__W                                     1
12682 #define   VSB_TOP_EQSMRCA2CTRL_RCAON__M                                     0x1
12683 #define   VSB_TOP_EQSMRCA2CTRL_RCAON__PRE                                   0x1
12684 
12685 #define   VSB_TOP_EQSMRCA2CTRL_DFEON__B                                     1
12686 #define   VSB_TOP_EQSMRCA2CTRL_DFEON__W                                     1
12687 #define   VSB_TOP_EQSMRCA2CTRL_DFEON__M                                     0x2
12688 #define   VSB_TOP_EQSMRCA2CTRL_DFEON__PRE                                   0x2
12689 
12690 #define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__B                                    2
12691 #define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__W                                    1
12692 #define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__M                                    0x4
12693 #define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__PRE                                  0x0
12694 
12695 #define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__B                                    3
12696 #define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__W                                    1
12697 #define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__M                                    0x8
12698 #define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__PRE                                  0x0
12699 
12700 #define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__B                                 4
12701 #define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__W                                 1
12702 #define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__M                                 0x10
12703 #define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__PRE                               0x0
12704 
12705 #define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__B                                5
12706 #define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__W                                1
12707 #define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__M                                0x20
12708 #define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__PRE                              0x0
12709 
12710 #define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__B                           6
12711 #define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__W                           1
12712 #define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__M                           0x40
12713 #define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__PRE                         0x0
12714 
12715 #define VSB_TOP_EQSMDDM1CTRL__A                                             0x1C10030
12716 #define VSB_TOP_EQSMDDM1CTRL__W                                             7
12717 #define VSB_TOP_EQSMDDM1CTRL__M                                             0x7F
12718 #define VSB_TOP_EQSMDDM1CTRL__PRE                                           0x6
12719 
12720 #define   VSB_TOP_EQSMDDM1CTRL_RCAON__B                                     0
12721 #define   VSB_TOP_EQSMDDM1CTRL_RCAON__W                                     1
12722 #define   VSB_TOP_EQSMDDM1CTRL_RCAON__M                                     0x1
12723 #define   VSB_TOP_EQSMDDM1CTRL_RCAON__PRE                                   0x0
12724 
12725 #define   VSB_TOP_EQSMDDM1CTRL_DFEON__B                                     1
12726 #define   VSB_TOP_EQSMDDM1CTRL_DFEON__W                                     1
12727 #define   VSB_TOP_EQSMDDM1CTRL_DFEON__M                                     0x2
12728 #define   VSB_TOP_EQSMDDM1CTRL_DFEON__PRE                                   0x2
12729 
12730 #define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__B                                    2
12731 #define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__W                                    1
12732 #define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__M                                    0x4
12733 #define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__PRE                                  0x4
12734 
12735 #define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__B                                    3
12736 #define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__W                                    1
12737 #define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__M                                    0x8
12738 #define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__PRE                                  0x0
12739 
12740 #define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__B                                 4
12741 #define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__W                                 1
12742 #define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__M                                 0x10
12743 #define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__PRE                               0x0
12744 
12745 #define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__B                                5
12746 #define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__W                                1
12747 #define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__M                                0x20
12748 #define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__PRE                              0x0
12749 
12750 #define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__B                           6
12751 #define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__W                           1
12752 #define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__M                           0x40
12753 #define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__PRE                         0x0
12754 
12755 #define VSB_TOP_EQSMDDM2CTRL__A                                             0x1C10031
12756 #define VSB_TOP_EQSMDDM2CTRL__W                                             7
12757 #define VSB_TOP_EQSMDDM2CTRL__M                                             0x7F
12758 #define VSB_TOP_EQSMDDM2CTRL__PRE                                           0x1E
12759 
12760 #define   VSB_TOP_EQSMDDM2CTRL_RCAON__B                                     0
12761 #define   VSB_TOP_EQSMDDM2CTRL_RCAON__W                                     1
12762 #define   VSB_TOP_EQSMDDM2CTRL_RCAON__M                                     0x1
12763 #define   VSB_TOP_EQSMDDM2CTRL_RCAON__PRE                                   0x0
12764 
12765 #define   VSB_TOP_EQSMDDM2CTRL_DFEON__B                                     1
12766 #define   VSB_TOP_EQSMDDM2CTRL_DFEON__W                                     1
12767 #define   VSB_TOP_EQSMDDM2CTRL_DFEON__M                                     0x2
12768 #define   VSB_TOP_EQSMDDM2CTRL_DFEON__PRE                                   0x2
12769 
12770 #define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__B                                    2
12771 #define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__W                                    1
12772 #define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__M                                    0x4
12773 #define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__PRE                                  0x4
12774 
12775 #define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__B                                    3
12776 #define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__W                                    1
12777 #define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__M                                    0x8
12778 #define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__PRE                                  0x8
12779 
12780 #define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__B                                 4
12781 #define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__W                                 1
12782 #define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__M                                 0x10
12783 #define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__PRE                               0x10
12784 
12785 #define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__B                                5
12786 #define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__W                                1
12787 #define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__M                                0x20
12788 #define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__PRE                              0x0
12789 
12790 #define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__B                           6
12791 #define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__W                           1
12792 #define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__M                           0x40
12793 #define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__PRE                         0x0
12794 
12795 #define VSB_TOP_SYSSMRSTCTRL__A                                             0x1C10032
12796 #define VSB_TOP_SYSSMRSTCTRL__W                                             11
12797 #define VSB_TOP_SYSSMRSTCTRL__M                                             0x7FF
12798 #define VSB_TOP_SYSSMRSTCTRL__PRE                                           0x7F9
12799 
12800 #define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__B                                  0
12801 #define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__W                                  1
12802 #define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__M                                  0x1
12803 #define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__PRE                                0x1
12804 
12805 #define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__B                                   1
12806 #define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__W                                   1
12807 #define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__M                                   0x2
12808 #define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__PRE                                 0x0
12809 
12810 #define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__B                                  2
12811 #define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__W                                  1
12812 #define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__M                                  0x4
12813 #define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__PRE                                0x0
12814 
12815 #define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__B                             3
12816 #define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__W                             1
12817 #define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__M                             0x8
12818 #define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__PRE                           0x8
12819 
12820 #define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__B                                  4
12821 #define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__W                                  1
12822 #define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__M                                  0x10
12823 #define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__PRE                                0x10
12824 
12825 #define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__B                                  5
12826 #define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__W                                  1
12827 #define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__M                                  0x20
12828 #define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__PRE                                0x20
12829 
12830 #define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__B                                  6
12831 #define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__W                                  1
12832 #define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__M                                  0x40
12833 #define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__PRE                                0x40
12834 
12835 #define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__B                                     7
12836 #define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__W                                     1
12837 #define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__M                                     0x80
12838 #define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__PRE                                   0x80
12839 
12840 #define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__B                                    8
12841 #define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__W                                    1
12842 #define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__M                                    0x100
12843 #define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__PRE                                  0x100
12844 
12845 #define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__B                                   9
12846 #define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__W                                   1
12847 #define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__M                                   0x200
12848 #define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__PRE                                 0x200
12849 
12850 #define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__B                           10
12851 #define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__W                           1
12852 #define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__M                           0x400
12853 #define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__PRE                         0x400
12854 
12855 #define VSB_TOP_SYSSMCYCTRL__A                                              0x1C10033
12856 #define VSB_TOP_SYSSMCYCTRL__W                                              11
12857 #define VSB_TOP_SYSSMCYCTRL__M                                              0x7FF
12858 #define VSB_TOP_SYSSMCYCTRL__PRE                                            0x4E9
12859 
12860 #define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__B                                   0
12861 #define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__W                                   1
12862 #define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__M                                   0x1
12863 #define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__PRE                                 0x1
12864 
12865 #define   VSB_TOP_SYSSMCYCTRL_CTCALEN__B                                    1
12866 #define   VSB_TOP_SYSSMCYCTRL_CTCALEN__W                                    1
12867 #define   VSB_TOP_SYSSMCYCTRL_CTCALEN__M                                    0x2
12868 #define   VSB_TOP_SYSSMCYCTRL_CTCALEN__PRE                                  0x0
12869 
12870 #define   VSB_TOP_SYSSMCYCTRL_STARTTRN__B                                   2
12871 #define   VSB_TOP_SYSSMCYCTRL_STARTTRN__W                                   1
12872 #define   VSB_TOP_SYSSMCYCTRL_STARTTRN__M                                   0x4
12873 #define   VSB_TOP_SYSSMCYCTRL_STARTTRN__PRE                                 0x0
12874 
12875 #define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__B                              3
12876 #define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__W                              1
12877 #define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__M                              0x8
12878 #define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__PRE                            0x8
12879 
12880 #define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__B                                   4
12881 #define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__W                                   1
12882 #define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__M                                   0x10
12883 #define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__PRE                                 0x0
12884 
12885 #define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__B                                   5
12886 #define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__W                                   1
12887 #define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__M                                   0x20
12888 #define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__PRE                                 0x20
12889 
12890 #define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__B                                   6
12891 #define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__W                                   1
12892 #define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__M                                   0x40
12893 #define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__PRE                                 0x40
12894 
12895 #define   VSB_TOP_SYSSMCYCTRL_CKFRZ__B                                      7
12896 #define   VSB_TOP_SYSSMCYCTRL_CKFRZ__W                                      1
12897 #define   VSB_TOP_SYSSMCYCTRL_CKFRZ__M                                      0x80
12898 #define   VSB_TOP_SYSSMCYCTRL_CKFRZ__PRE                                    0x80
12899 
12900 #define   VSB_TOP_SYSSMCYCTRL_CKBWSW__B                                     8
12901 #define   VSB_TOP_SYSSMCYCTRL_CKBWSW__W                                     1
12902 #define   VSB_TOP_SYSSMCYCTRL_CKBWSW__M                                     0x100
12903 #define   VSB_TOP_SYSSMCYCTRL_CKBWSW__PRE                                   0x0
12904 
12905 #define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__B                                    9
12906 #define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__W                                    1
12907 #define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__M                                    0x200
12908 #define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__PRE                                  0x0
12909 
12910 #define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__B                            10
12911 #define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__W                            1
12912 #define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__M                            0x400
12913 #define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__PRE                          0x400
12914 
12915 #define VSB_TOP_SYSSMTRNCTRL__A                                             0x1C10034
12916 #define VSB_TOP_SYSSMTRNCTRL__W                                             11
12917 #define VSB_TOP_SYSSMTRNCTRL__M                                             0x7FF
12918 #define VSB_TOP_SYSSMTRNCTRL__PRE                                           0x204
12919 
12920 #define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__B                                  0
12921 #define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__W                                  1
12922 #define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__M                                  0x1
12923 #define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__PRE                                0x0
12924 
12925 #define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__B                                   1
12926 #define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__W                                   1
12927 #define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__M                                   0x2
12928 #define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__PRE                                 0x0
12929 
12930 #define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__B                                  2
12931 #define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__W                                  1
12932 #define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__M                                  0x4
12933 #define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__PRE                                0x4
12934 
12935 #define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__B                             3
12936 #define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__W                             1
12937 #define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__M                             0x8
12938 #define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__PRE                           0x0
12939 
12940 #define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__B                                  4
12941 #define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__W                                  1
12942 #define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__M                                  0x10
12943 #define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__PRE                                0x0
12944 
12945 #define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__B                                  5
12946 #define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__W                                  1
12947 #define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__M                                  0x20
12948 #define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__PRE                                0x0
12949 
12950 #define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__B                                  6
12951 #define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__W                                  1
12952 #define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__M                                  0x40
12953 #define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__PRE                                0x0
12954 
12955 #define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__B                                     7
12956 #define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__W                                     1
12957 #define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__M                                     0x80
12958 #define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__PRE                                   0x0
12959 
12960 #define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__B                                    8
12961 #define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__W                                    1
12962 #define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__M                                    0x100
12963 #define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__PRE                                  0x0
12964 
12965 #define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__B                                   9
12966 #define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__W                                   1
12967 #define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__M                                   0x200
12968 #define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__PRE                                 0x200
12969 
12970 #define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__B                           10
12971 #define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__W                           1
12972 #define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M                           0x400
12973 #define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__PRE                         0x0
12974 
12975 #define VSB_TOP_SYSSMEQCTRL__A                                              0x1C10035
12976 #define VSB_TOP_SYSSMEQCTRL__W                                              11
12977 #define VSB_TOP_SYSSMEQCTRL__M                                              0x7FF
12978 #define VSB_TOP_SYSSMEQCTRL__PRE                                            0x304
12979 
12980 #define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__B                                   0
12981 #define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__W                                   1
12982 #define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__M                                   0x1
12983 #define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__PRE                                 0x0
12984 
12985 #define   VSB_TOP_SYSSMEQCTRL_CTCALEN__B                                    1
12986 #define   VSB_TOP_SYSSMEQCTRL_CTCALEN__W                                    1
12987 #define   VSB_TOP_SYSSMEQCTRL_CTCALEN__M                                    0x2
12988 #define   VSB_TOP_SYSSMEQCTRL_CTCALEN__PRE                                  0x0
12989 
12990 #define   VSB_TOP_SYSSMEQCTRL_STARTTRN__B                                   2
12991 #define   VSB_TOP_SYSSMEQCTRL_STARTTRN__W                                   1
12992 #define   VSB_TOP_SYSSMEQCTRL_STARTTRN__M                                   0x4
12993 #define   VSB_TOP_SYSSMEQCTRL_STARTTRN__PRE                                 0x4
12994 
12995 #define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__B                              3
12996 #define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__W                              1
12997 #define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__M                              0x8
12998 #define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__PRE                            0x0
12999 
13000 #define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__B                                   4
13001 #define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__W                                   1
13002 #define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__M                                   0x10
13003 #define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__PRE                                 0x0
13004 
13005 #define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__B                                   5
13006 #define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__W                                   1
13007 #define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__M                                   0x20
13008 #define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__PRE                                 0x0
13009 
13010 #define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__B                                   6
13011 #define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__W                                   1
13012 #define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__M                                   0x40
13013 #define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__PRE                                 0x0
13014 
13015 #define   VSB_TOP_SYSSMEQCTRL_CKFRZ__B                                      7
13016 #define   VSB_TOP_SYSSMEQCTRL_CKFRZ__W                                      1
13017 #define   VSB_TOP_SYSSMEQCTRL_CKFRZ__M                                      0x80
13018 #define   VSB_TOP_SYSSMEQCTRL_CKFRZ__PRE                                    0x0
13019 
13020 #define   VSB_TOP_SYSSMEQCTRL_CKBWSW__B                                     8
13021 #define   VSB_TOP_SYSSMEQCTRL_CKBWSW__W                                     1
13022 #define   VSB_TOP_SYSSMEQCTRL_CKBWSW__M                                     0x100
13023 #define   VSB_TOP_SYSSMEQCTRL_CKBWSW__PRE                                   0x100
13024 
13025 #define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__B                                    9
13026 #define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__W                                    1
13027 #define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__M                                    0x200
13028 #define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__PRE                                  0x200
13029 
13030 #define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__B                            10
13031 #define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__W                            1
13032 #define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__M                            0x400
13033 #define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__PRE                          0x0
13034 
13035 #define VSB_TOP_SYSSMAGCCTRL__A                                             0x1C10036
13036 #define VSB_TOP_SYSSMAGCCTRL__W                                             11
13037 #define VSB_TOP_SYSSMAGCCTRL__M                                             0x7FF
13038 #define VSB_TOP_SYSSMAGCCTRL__PRE                                           0xF9
13039 
13040 #define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__B                                  0
13041 #define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__W                                  1
13042 #define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__M                                  0x1
13043 #define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__PRE                                0x1
13044 
13045 #define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__B                                   1
13046 #define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__W                                   1
13047 #define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__M                                   0x2
13048 #define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__PRE                                 0x0
13049 
13050 #define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__B                                  2
13051 #define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__W                                  1
13052 #define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__M                                  0x4
13053 #define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__PRE                                0x0
13054 
13055 #define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__B                             3
13056 #define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__W                             1
13057 #define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__M                             0x8
13058 #define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__PRE                           0x8
13059 
13060 #define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__B                                  4
13061 #define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__W                                  1
13062 #define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__M                                  0x10
13063 #define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__PRE                                0x10
13064 
13065 #define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__B                                  5
13066 #define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__W                                  1
13067 #define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__M                                  0x20
13068 #define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__PRE                                0x20
13069 
13070 #define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__B                                  6
13071 #define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__W                                  1
13072 #define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__M                                  0x40
13073 #define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__PRE                                0x40
13074 
13075 #define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__B                                     7
13076 #define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__W                                     1
13077 #define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__M                                     0x80
13078 #define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__PRE                                   0x80
13079 
13080 #define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__B                                    8
13081 #define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__W                                    1
13082 #define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__M                                    0x100
13083 #define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__PRE                                  0x0
13084 
13085 #define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__B                                   9
13086 #define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__W                                   1
13087 #define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__M                                   0x200
13088 #define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__PRE                                 0x0
13089 
13090 #define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__B                           10
13091 #define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__W                           1
13092 #define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__M                           0x400
13093 #define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__PRE                         0x0
13094 
13095 #define VSB_TOP_SYSSMCTCTRL__A                                              0x1C10037
13096 #define VSB_TOP_SYSSMCTCTRL__W                                              11
13097 #define VSB_TOP_SYSSMCTCTRL__M                                              0x7FF
13098 #define VSB_TOP_SYSSMCTCTRL__PRE                                            0x4A
13099 
13100 #define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__B                                   0
13101 #define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__W                                   1
13102 #define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__M                                   0x1
13103 #define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__PRE                                 0x0
13104 
13105 #define   VSB_TOP_SYSSMCTCTRL_CTCALEN__B                                    1
13106 #define   VSB_TOP_SYSSMCTCTRL_CTCALEN__W                                    1
13107 #define   VSB_TOP_SYSSMCTCTRL_CTCALEN__M                                    0x2
13108 #define   VSB_TOP_SYSSMCTCTRL_CTCALEN__PRE                                  0x2
13109 
13110 #define   VSB_TOP_SYSSMCTCTRL_STARTTRN__B                                   2
13111 #define   VSB_TOP_SYSSMCTCTRL_STARTTRN__W                                   1
13112 #define   VSB_TOP_SYSSMCTCTRL_STARTTRN__M                                   0x4
13113 #define   VSB_TOP_SYSSMCTCTRL_STARTTRN__PRE                                 0x0
13114 
13115 #define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__B                              3
13116 #define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__W                              1
13117 #define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__M                              0x8
13118 #define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__PRE                            0x8
13119 
13120 #define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__B                                   4
13121 #define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__W                                   1
13122 #define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__M                                   0x10
13123 #define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__PRE                                 0x0
13124 
13125 #define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__B                                   5
13126 #define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__W                                   1
13127 #define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__M                                   0x20
13128 #define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__PRE                                 0x0
13129 
13130 #define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__B                                   6
13131 #define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__W                                   1
13132 #define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__M                                   0x40
13133 #define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__PRE                                 0x40
13134 
13135 #define   VSB_TOP_SYSSMCTCTRL_CKFRZ__B                                      7
13136 #define   VSB_TOP_SYSSMCTCTRL_CKFRZ__W                                      1
13137 #define   VSB_TOP_SYSSMCTCTRL_CKFRZ__M                                      0x80
13138 #define   VSB_TOP_SYSSMCTCTRL_CKFRZ__PRE                                    0x0
13139 
13140 #define   VSB_TOP_SYSSMCTCTRL_CKBWSW__B                                     8
13141 #define   VSB_TOP_SYSSMCTCTRL_CKBWSW__W                                     1
13142 #define   VSB_TOP_SYSSMCTCTRL_CKBWSW__M                                     0x100
13143 #define   VSB_TOP_SYSSMCTCTRL_CKBWSW__PRE                                   0x0
13144 
13145 #define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__B                                    9
13146 #define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__W                                    1
13147 #define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__M                                    0x200
13148 #define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__PRE                                  0x0
13149 
13150 #define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__B                            10
13151 #define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__W                            1
13152 #define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__M                            0x400
13153 #define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__PRE                          0x0
13154 
13155 #define VSB_TOP_EQCTRL__A                                                   0x1C10038
13156 #define VSB_TOP_EQCTRL__W                                                   10
13157 #define VSB_TOP_EQCTRL__M                                                   0x3FF
13158 #define VSB_TOP_EQCTRL__PRE                                                 0x6
13159 
13160 #define   VSB_TOP_EQCTRL_STASSIGNEN__B                                      0
13161 #define   VSB_TOP_EQCTRL_STASSIGNEN__W                                      1
13162 #define   VSB_TOP_EQCTRL_STASSIGNEN__M                                      0x1
13163 #define   VSB_TOP_EQCTRL_STASSIGNEN__PRE                                    0x0
13164 
13165 #define   VSB_TOP_EQCTRL_ORCANCMAEN__B                                      1
13166 #define   VSB_TOP_EQCTRL_ORCANCMAEN__W                                      1
13167 #define   VSB_TOP_EQCTRL_ORCANCMAEN__M                                      0x2
13168 #define   VSB_TOP_EQCTRL_ORCANCMAEN__PRE                                    0x2
13169 
13170 #define   VSB_TOP_EQCTRL_ODAGCGO__B                                         2
13171 #define   VSB_TOP_EQCTRL_ODAGCGO__W                                         1
13172 #define   VSB_TOP_EQCTRL_ODAGCGO__M                                         0x4
13173 #define   VSB_TOP_EQCTRL_ODAGCGO__PRE                                       0x4
13174 
13175 #define   VSB_TOP_EQCTRL_OPTGAIN__B                                         3
13176 #define   VSB_TOP_EQCTRL_OPTGAIN__W                                         3
13177 #define   VSB_TOP_EQCTRL_OPTGAIN__M                                         0x38
13178 #define   VSB_TOP_EQCTRL_OPTGAIN__PRE                                       0x0
13179 
13180 #define   VSB_TOP_EQCTRL_TAPRAMWRTEN__B                                     6
13181 #define   VSB_TOP_EQCTRL_TAPRAMWRTEN__W                                     1
13182 #define   VSB_TOP_EQCTRL_TAPRAMWRTEN__M                                     0x40
13183 #define   VSB_TOP_EQCTRL_TAPRAMWRTEN__PRE                                   0x0
13184 
13185 #define   VSB_TOP_EQCTRL_CMAGAIN__B                                         7
13186 #define   VSB_TOP_EQCTRL_CMAGAIN__W                                         3
13187 #define   VSB_TOP_EQCTRL_CMAGAIN__M                                         0x380
13188 #define   VSB_TOP_EQCTRL_CMAGAIN__PRE                                       0x0
13189 
13190 #define VSB_TOP_PREEQAGCCTRL__A                                             0x1C10039
13191 #define VSB_TOP_PREEQAGCCTRL__W                                             5
13192 #define VSB_TOP_PREEQAGCCTRL__M                                             0x1F
13193 #define VSB_TOP_PREEQAGCCTRL__PRE                                           0x10
13194 
13195 #define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__B                             0
13196 #define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__W                             4
13197 #define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__M                             0xF
13198 #define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__PRE                           0x0
13199 
13200 #define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__B                               4
13201 #define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__W                               1
13202 #define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M                               0x10
13203 #define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE                             0x10
13204 
13205 #define VSB_TOP_PREEQAGCPWRREFLVLHI__A                                      0x1C1003A
13206 #define VSB_TOP_PREEQAGCPWRREFLVLHI__W                                      8
13207 #define VSB_TOP_PREEQAGCPWRREFLVLHI__M                                      0xFF
13208 #define VSB_TOP_PREEQAGCPWRREFLVLHI__PRE                                    0x0
13209 
13210 #define VSB_TOP_PREEQAGCPWRREFLVLLO__A                                      0x1C1003B
13211 #define VSB_TOP_PREEQAGCPWRREFLVLLO__W                                      16
13212 #define VSB_TOP_PREEQAGCPWRREFLVLLO__M                                      0xFFFF
13213 #define VSB_TOP_PREEQAGCPWRREFLVLLO__PRE                                    0x1D66
13214 
13215 #define VSB_TOP_CORINGSEL__A                                                0x1C1003C
13216 #define VSB_TOP_CORINGSEL__W                                                8
13217 #define VSB_TOP_CORINGSEL__M                                                0xFF
13218 #define VSB_TOP_CORINGSEL__PRE                                              0x3
13219 #define VSB_TOP_BEDETCTRL__A                                                0x1C1003D
13220 #define VSB_TOP_BEDETCTRL__W                                                9
13221 #define VSB_TOP_BEDETCTRL__M                                                0x1FF
13222 #define VSB_TOP_BEDETCTRL__PRE                                              0x145
13223 
13224 #define   VSB_TOP_BEDETCTRL_MIXRATIO__B                                     0
13225 #define   VSB_TOP_BEDETCTRL_MIXRATIO__W                                     3
13226 #define   VSB_TOP_BEDETCTRL_MIXRATIO__M                                     0x7
13227 #define   VSB_TOP_BEDETCTRL_MIXRATIO__PRE                                   0x5
13228 
13229 #define   VSB_TOP_BEDETCTRL_CYOFFSEL__B                                     3
13230 #define   VSB_TOP_BEDETCTRL_CYOFFSEL__W                                     1
13231 #define   VSB_TOP_BEDETCTRL_CYOFFSEL__M                                     0x8
13232 #define   VSB_TOP_BEDETCTRL_CYOFFSEL__PRE                                   0x0
13233 
13234 #define   VSB_TOP_BEDETCTRL_DATAOFFSEL__B                                   4
13235 #define   VSB_TOP_BEDETCTRL_DATAOFFSEL__W                                   1
13236 #define   VSB_TOP_BEDETCTRL_DATAOFFSEL__M                                   0x10
13237 #define   VSB_TOP_BEDETCTRL_DATAOFFSEL__PRE                                 0x0
13238 
13239 #define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__B                                   5
13240 #define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__W                                   1
13241 #define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__M                                   0x20
13242 #define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__PRE                                 0x0
13243 
13244 #define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__B                                   6
13245 #define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__W                                   1
13246 #define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__M                                   0x40
13247 #define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__PRE                                 0x40
13248 
13249 #define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__B                                   7
13250 #define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__W                                   1
13251 #define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__M                                   0x80
13252 #define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__PRE                                 0x0
13253 
13254 #define   VSB_TOP_BEDETCTRL_BYPASS_DMP__B                                   8
13255 #define   VSB_TOP_BEDETCTRL_BYPASS_DMP__W                                   1
13256 #define   VSB_TOP_BEDETCTRL_BYPASS_DMP__M                                   0x100
13257 #define   VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE                                 0x100
13258 
13259 #define VSB_TOP_LBAGCREFLVL__A                                              0x1C1003E
13260 #define VSB_TOP_LBAGCREFLVL__W                                              12
13261 #define VSB_TOP_LBAGCREFLVL__M                                              0xFFF
13262 #define VSB_TOP_LBAGCREFLVL__PRE                                            0x200
13263 
13264 #define VSB_TOP_UBAGCREFLVL__A                                              0x1C1003F
13265 #define VSB_TOP_UBAGCREFLVL__W                                              12
13266 #define VSB_TOP_UBAGCREFLVL__M                                              0xFFF
13267 #define VSB_TOP_UBAGCREFLVL__PRE                                            0x400
13268 
13269 #define VSB_TOP_NOTCH1_BIN_NUM__A                                           0x1C10040
13270 #define VSB_TOP_NOTCH1_BIN_NUM__W                                           11
13271 #define VSB_TOP_NOTCH1_BIN_NUM__M                                           0x7FF
13272 #define VSB_TOP_NOTCH1_BIN_NUM__PRE                                         0xB2
13273 
13274 #define VSB_TOP_NOTCH2_BIN_NUM__A                                           0x1C10041
13275 #define VSB_TOP_NOTCH2_BIN_NUM__W                                           11
13276 #define VSB_TOP_NOTCH2_BIN_NUM__M                                           0x7FF
13277 #define VSB_TOP_NOTCH2_BIN_NUM__PRE                                         0x40B
13278 
13279 #define VSB_TOP_NOTCH_START_BIN_NUM__A                                      0x1C10042
13280 #define VSB_TOP_NOTCH_START_BIN_NUM__W                                      11
13281 #define VSB_TOP_NOTCH_START_BIN_NUM__M                                      0x7FF
13282 #define VSB_TOP_NOTCH_START_BIN_NUM__PRE                                    0x7C0
13283 
13284 #define VSB_TOP_NOTCH_STOP_BIN_NUM__A                                       0x1C10043
13285 #define VSB_TOP_NOTCH_STOP_BIN_NUM__W                                       11
13286 #define VSB_TOP_NOTCH_STOP_BIN_NUM__M                                       0x7FF
13287 #define VSB_TOP_NOTCH_STOP_BIN_NUM__PRE                                     0x43F
13288 
13289 #define VSB_TOP_NOTCH_TEST_DURATION__A                                      0x1C10044
13290 #define VSB_TOP_NOTCH_TEST_DURATION__W                                      11
13291 #define VSB_TOP_NOTCH_TEST_DURATION__M                                      0x7FF
13292 #define VSB_TOP_NOTCH_TEST_DURATION__PRE                                    0x7FF
13293 
13294 #define VSB_TOP_RESULT_LARGE_PEAK_BIN__A                                    0x1C10045
13295 #define VSB_TOP_RESULT_LARGE_PEAK_BIN__W                                    11
13296 #define VSB_TOP_RESULT_LARGE_PEAK_BIN__M                                    0x7FF
13297 #define VSB_TOP_RESULT_LARGE_PEAK_BIN__PRE                                  0x0
13298 
13299 #define VSB_TOP_RESULT_LARGE_PEAK_VALUE__A                                  0x1C10046
13300 #define VSB_TOP_RESULT_LARGE_PEAK_VALUE__W                                  16
13301 #define VSB_TOP_RESULT_LARGE_PEAK_VALUE__M                                  0xFFFF
13302 #define VSB_TOP_RESULT_LARGE_PEAK_VALUE__PRE                                0x0
13303 
13304 #define VSB_TOP_RESULT_SMALL_PEAK_BIN__A                                    0x1C10047
13305 #define VSB_TOP_RESULT_SMALL_PEAK_BIN__W                                    11
13306 #define VSB_TOP_RESULT_SMALL_PEAK_BIN__M                                    0x7FF
13307 #define VSB_TOP_RESULT_SMALL_PEAK_BIN__PRE                                  0x0
13308 
13309 #define VSB_TOP_RESULT_SMALL_PEAK_VALUE__A                                  0x1C10048
13310 #define VSB_TOP_RESULT_SMALL_PEAK_VALUE__W                                  16
13311 #define VSB_TOP_RESULT_SMALL_PEAK_VALUE__M                                  0xFFFF
13312 #define VSB_TOP_RESULT_SMALL_PEAK_VALUE__PRE                                0x0
13313 
13314 #define VSB_TOP_NOTCH_SWEEP_RUNNING__A                                      0x1C10049
13315 #define VSB_TOP_NOTCH_SWEEP_RUNNING__W                                      1
13316 #define VSB_TOP_NOTCH_SWEEP_RUNNING__M                                      0x1
13317 #define VSB_TOP_NOTCH_SWEEP_RUNNING__PRE                                    0x0
13318 
13319 #define VSB_TOP_PREEQDAGCRATIO__A                                           0x1C1004A
13320 #define VSB_TOP_PREEQDAGCRATIO__W                                           13
13321 #define VSB_TOP_PREEQDAGCRATIO__M                                           0x1FFF
13322 #define VSB_TOP_PREEQDAGCRATIO__PRE                                         0x0
13323 #define VSB_TOP_AGC_TRUNCCTRL__A                                            0x1C1004B
13324 #define VSB_TOP_AGC_TRUNCCTRL__W                                            4
13325 #define VSB_TOP_AGC_TRUNCCTRL__M                                            0xF
13326 #define VSB_TOP_AGC_TRUNCCTRL__PRE                                          0xF
13327 
13328 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__B                                0
13329 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__W                                2
13330 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__M                                0x3
13331 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__PRE                              0x3
13332 
13333 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__B                                2
13334 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__W                                1
13335 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__M                                0x4
13336 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__PRE                              0x4
13337 
13338 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__B                                 3
13339 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__W                                 1
13340 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M                                 0x8
13341 #define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE                               0x8
13342 
13343 #define VSB_TOP_BEAGC_DEADZONEINIT__A                                       0x1C1004C
13344 #define VSB_TOP_BEAGC_DEADZONEINIT__W                                       8
13345 #define VSB_TOP_BEAGC_DEADZONEINIT__M                                       0xFF
13346 #define VSB_TOP_BEAGC_DEADZONEINIT__PRE                                     0x50
13347 
13348 #define VSB_TOP_BEAGC_REFLEVEL__A                                           0x1C1004D
13349 #define VSB_TOP_BEAGC_REFLEVEL__W                                           9
13350 #define VSB_TOP_BEAGC_REFLEVEL__M                                           0x1FF
13351 #define VSB_TOP_BEAGC_REFLEVEL__PRE                                         0xAE
13352 
13353 #define VSB_TOP_BEAGC_GAINSHIFT__A                                          0x1C1004E
13354 #define VSB_TOP_BEAGC_GAINSHIFT__W                                          3
13355 #define VSB_TOP_BEAGC_GAINSHIFT__M                                          0x7
13356 #define VSB_TOP_BEAGC_GAINSHIFT__PRE                                        0x3
13357 
13358 #define VSB_TOP_BEAGC_REGINIT__A                                            0x1C1004F
13359 #define VSB_TOP_BEAGC_REGINIT__W                                            15
13360 #define VSB_TOP_BEAGC_REGINIT__M                                            0x7FFF
13361 #define VSB_TOP_BEAGC_REGINIT__PRE                                          0x40
13362 
13363 #define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__B                                14
13364 #define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__W                                1
13365 #define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M                                0x4000
13366 #define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE                              0x0
13367 
13368 #define VSB_TOP_BEAGC_SCALE__A                                              0x1C10050
13369 #define VSB_TOP_BEAGC_SCALE__W                                              14
13370 #define VSB_TOP_BEAGC_SCALE__M                                              0x3FFF
13371 #define VSB_TOP_BEAGC_SCALE__PRE                                            0x0
13372 
13373 #define VSB_TOP_CFAGC_DEADZONEINIT__A                                       0x1C10051
13374 #define VSB_TOP_CFAGC_DEADZONEINIT__W                                       8
13375 #define VSB_TOP_CFAGC_DEADZONEINIT__M                                       0xFF
13376 #define VSB_TOP_CFAGC_DEADZONEINIT__PRE                                     0x50
13377 
13378 #define VSB_TOP_CFAGC_REFLEVEL__A                                           0x1C10052
13379 #define VSB_TOP_CFAGC_REFLEVEL__W                                           9
13380 #define VSB_TOP_CFAGC_REFLEVEL__M                                           0x1FF
13381 #define VSB_TOP_CFAGC_REFLEVEL__PRE                                         0xAE
13382 
13383 #define VSB_TOP_CFAGC_GAINSHIFT__A                                          0x1C10053
13384 #define VSB_TOP_CFAGC_GAINSHIFT__W                                          3
13385 #define VSB_TOP_CFAGC_GAINSHIFT__M                                          0x7
13386 #define VSB_TOP_CFAGC_GAINSHIFT__PRE                                        0x3
13387 
13388 #define VSB_TOP_CFAGC_REGINIT__A                                            0x1C10054
13389 #define VSB_TOP_CFAGC_REGINIT__W                                            15
13390 #define VSB_TOP_CFAGC_REGINIT__M                                            0x7FFF
13391 #define VSB_TOP_CFAGC_REGINIT__PRE                                          0x80
13392 
13393 #define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__B                                14
13394 #define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__W                                1
13395 #define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M                                0x4000
13396 #define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE                              0x0
13397 
13398 #define VSB_TOP_CFAGC_SCALE__A                                              0x1C10055
13399 #define VSB_TOP_CFAGC_SCALE__W                                              14
13400 #define VSB_TOP_CFAGC_SCALE__M                                              0x3FFF
13401 #define VSB_TOP_CFAGC_SCALE__PRE                                            0x0
13402 
13403 #define VSB_TOP_CKTRKONCTL__A                                               0x1C10056
13404 #define VSB_TOP_CKTRKONCTL__W                                               2
13405 #define VSB_TOP_CKTRKONCTL__M                                               0x3
13406 #define VSB_TOP_CKTRKONCTL__PRE                                             0x0
13407 
13408 #define VSB_TOP_CYTRKONCTL__A                                               0x1C10057
13409 #define VSB_TOP_CYTRKONCTL__W                                               2
13410 #define VSB_TOP_CYTRKONCTL__M                                               0x3
13411 #define VSB_TOP_CYTRKONCTL__PRE                                             0x0
13412 
13413 #define VSB_TOP_PTONCTL__A                                                  0x1C10058
13414 #define VSB_TOP_PTONCTL__W                                                  2
13415 #define VSB_TOP_PTONCTL__M                                                  0x3
13416 #define VSB_TOP_PTONCTL__PRE                                                0x0
13417 
13418 #define VSB_TOP_NOTCH_SCALE_1__A                                            0x1C10059
13419 #define VSB_TOP_NOTCH_SCALE_1__W                                            8
13420 #define VSB_TOP_NOTCH_SCALE_1__M                                            0xFF
13421 #define VSB_TOP_NOTCH_SCALE_1__PRE                                          0xA
13422 
13423 #define VSB_TOP_NOTCH_SCALE_2__A                                            0x1C1005A
13424 #define VSB_TOP_NOTCH_SCALE_2__W                                            8
13425 #define VSB_TOP_NOTCH_SCALE_2__M                                            0xFF
13426 #define VSB_TOP_NOTCH_SCALE_2__PRE                                          0xA
13427 
13428 #define VSB_TOP_FIRSTLARGFFETAP__A                                          0x1C1005B
13429 #define VSB_TOP_FIRSTLARGFFETAP__W                                          12
13430 #define VSB_TOP_FIRSTLARGFFETAP__M                                          0xFFF
13431 #define VSB_TOP_FIRSTLARGFFETAP__PRE                                        0x0
13432 
13433 #define VSB_TOP_FIRSTLARGFFETAPADDR__A                                      0x1C1005C
13434 #define VSB_TOP_FIRSTLARGFFETAPADDR__W                                      11
13435 #define VSB_TOP_FIRSTLARGFFETAPADDR__M                                      0x7FF
13436 #define VSB_TOP_FIRSTLARGFFETAPADDR__PRE                                    0x0
13437 
13438 #define VSB_TOP_SECONDLARGFFETAP__A                                         0x1C1005D
13439 #define VSB_TOP_SECONDLARGFFETAP__W                                         12
13440 #define VSB_TOP_SECONDLARGFFETAP__M                                         0xFFF
13441 #define VSB_TOP_SECONDLARGFFETAP__PRE                                       0x0
13442 
13443 #define VSB_TOP_SECONDLARGFFETAPADDR__A                                     0x1C1005E
13444 #define VSB_TOP_SECONDLARGFFETAPADDR__W                                     11
13445 #define VSB_TOP_SECONDLARGFFETAPADDR__M                                     0x7FF
13446 #define VSB_TOP_SECONDLARGFFETAPADDR__PRE                                   0x0
13447 
13448 #define VSB_TOP_FIRSTLARGDFETAP__A                                          0x1C1005F
13449 #define VSB_TOP_FIRSTLARGDFETAP__W                                          12
13450 #define VSB_TOP_FIRSTLARGDFETAP__M                                          0xFFF
13451 #define VSB_TOP_FIRSTLARGDFETAP__PRE                                        0x0
13452 
13453 #define VSB_TOP_FIRSTLARGDFETAPADDR__A                                      0x1C10060
13454 #define VSB_TOP_FIRSTLARGDFETAPADDR__W                                      11
13455 #define VSB_TOP_FIRSTLARGDFETAPADDR__M                                      0x7FF
13456 #define VSB_TOP_FIRSTLARGDFETAPADDR__PRE                                    0x0
13457 
13458 #define VSB_TOP_SECONDLARGDFETAP__A                                         0x1C10061
13459 #define VSB_TOP_SECONDLARGDFETAP__W                                         12
13460 #define VSB_TOP_SECONDLARGDFETAP__M                                         0xFFF
13461 #define VSB_TOP_SECONDLARGDFETAP__PRE                                       0x0
13462 
13463 #define VSB_TOP_SECONDLARGDFETAPADDR__A                                     0x1C10062
13464 #define VSB_TOP_SECONDLARGDFETAPADDR__W                                     11
13465 #define VSB_TOP_SECONDLARGDFETAPADDR__M                                     0x7FF
13466 #define VSB_TOP_SECONDLARGDFETAPADDR__PRE                                   0x0
13467 
13468 #define VSB_TOP_PARAOWDBUS__A                                               0x1C10063
13469 #define VSB_TOP_PARAOWDBUS__W                                               12
13470 #define VSB_TOP_PARAOWDBUS__M                                               0xFFF
13471 #define VSB_TOP_PARAOWDBUS__PRE                                             0x0
13472 #define VSB_TOP_PARAOWCTRL__A                                               0x1C10064
13473 #define VSB_TOP_PARAOWCTRL__W                                               7
13474 #define VSB_TOP_PARAOWCTRL__M                                               0x7F
13475 #define VSB_TOP_PARAOWCTRL__PRE                                             0x0
13476 
13477 #define   VSB_TOP_PARAOWCTRL_PARAOWABUS__B                                  0
13478 #define   VSB_TOP_PARAOWCTRL_PARAOWABUS__W                                  6
13479 #define   VSB_TOP_PARAOWCTRL_PARAOWABUS__M                                  0x3F
13480 #define   VSB_TOP_PARAOWCTRL_PARAOWABUS__PRE                                0x0
13481 
13482 #define   VSB_TOP_PARAOWCTRL_PARAOWEN__B                                    6
13483 #define   VSB_TOP_PARAOWCTRL_PARAOWEN__W                                    1
13484 #define   VSB_TOP_PARAOWCTRL_PARAOWEN__M                                    0x40
13485 #define   VSB_TOP_PARAOWCTRL_PARAOWEN__PRE                                  0x0
13486 
13487 #define VSB_TOP_CURRENTSEGLOCAT__A                                          0x1C10065
13488 #define VSB_TOP_CURRENTSEGLOCAT__W                                          10
13489 #define VSB_TOP_CURRENTSEGLOCAT__M                                          0x3FF
13490 #define VSB_TOP_CURRENTSEGLOCAT__PRE                                        0x0
13491 
13492 #define VSB_TOP_MEASUREMENT_PERIOD__A                                       0x1C10066
13493 #define VSB_TOP_MEASUREMENT_PERIOD__W                                       16
13494 #define VSB_TOP_MEASUREMENT_PERIOD__M                                       0xFFFF
13495 #define VSB_TOP_MEASUREMENT_PERIOD__PRE                                     0x0
13496 
13497 #define VSB_TOP_NR_SYM_ERRS__A                                              0x1C10067
13498 #define VSB_TOP_NR_SYM_ERRS__W                                              16
13499 #define VSB_TOP_NR_SYM_ERRS__M                                              0xFFFF
13500 #define VSB_TOP_NR_SYM_ERRS__PRE                                            0xFFFF
13501 
13502 #define VSB_TOP_ERR_ENERGY_L__A                                             0x1C10068
13503 #define VSB_TOP_ERR_ENERGY_L__W                                             16
13504 #define VSB_TOP_ERR_ENERGY_L__M                                             0xFFFF
13505 #define VSB_TOP_ERR_ENERGY_L__PRE                                           0xFFFF
13506 
13507 #define VSB_TOP_ERR_ENERGY_H__A                                             0x1C10069
13508 #define VSB_TOP_ERR_ENERGY_H__W                                             16
13509 #define VSB_TOP_ERR_ENERGY_H__M                                             0xFFFF
13510 #define VSB_TOP_ERR_ENERGY_H__PRE                                           0xFFFF
13511 
13512 #define VSB_TOP_SLICER_SEL_8LEV__A                                          0x1C1006A
13513 #define VSB_TOP_SLICER_SEL_8LEV__W                                          1
13514 #define VSB_TOP_SLICER_SEL_8LEV__M                                          0x1
13515 #define VSB_TOP_SLICER_SEL_8LEV__PRE                                        0x1
13516 
13517 #define VSB_TOP_BNFIELD__A                                                  0x1C1006B
13518 #define VSB_TOP_BNFIELD__W                                                  3
13519 #define VSB_TOP_BNFIELD__M                                                  0x7
13520 #define VSB_TOP_BNFIELD__PRE                                                0x3
13521 
13522 #define VSB_TOP_CLPLASTNUM__A                                               0x1C1006C
13523 #define VSB_TOP_CLPLASTNUM__W                                               8
13524 #define VSB_TOP_CLPLASTNUM__M                                               0xFF
13525 #define VSB_TOP_CLPLASTNUM__PRE                                             0x0
13526 
13527 #define VSB_TOP_BNSQERR__A                                                  0x1C1006D
13528 #define VSB_TOP_BNSQERR__W                                                  16
13529 #define VSB_TOP_BNSQERR__M                                                  0xFFFF
13530 #define VSB_TOP_BNSQERR__PRE                                                0x1AD
13531 
13532 #define VSB_TOP_BNTHRESH__A                                                 0x1C1006E
13533 #define VSB_TOP_BNTHRESH__W                                                 9
13534 #define VSB_TOP_BNTHRESH__M                                                 0x1FF
13535 #define VSB_TOP_BNTHRESH__PRE                                               0x120
13536 
13537 #define VSB_TOP_BNCLPNUM__A                                                 0x1C1006F
13538 #define VSB_TOP_BNCLPNUM__W                                                 16
13539 #define VSB_TOP_BNCLPNUM__M                                                 0xFFFF
13540 #define VSB_TOP_BNCLPNUM__PRE                                               0x0
13541 #define VSB_TOP_PHASELOCKCTRL__A                                            0x1C10070
13542 #define VSB_TOP_PHASELOCKCTRL__W                                            7
13543 #define VSB_TOP_PHASELOCKCTRL__M                                            0x7F
13544 #define VSB_TOP_PHASELOCKCTRL__PRE                                          0x0
13545 
13546 #define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__B                           0
13547 #define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__W                           1
13548 #define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__M                           0x1
13549 #define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__PRE                         0x0
13550 
13551 #define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__B                                1
13552 #define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__W                                1
13553 #define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M                                0x2
13554 #define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__PRE                              0x0
13555 
13556 #define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__B                           2
13557 #define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__W                           1
13558 #define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__M                           0x4
13559 #define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__PRE                         0x0
13560 
13561 #define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__B                                3
13562 #define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__W                                1
13563 #define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__M                                0x8
13564 #define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__PRE                              0x0
13565 
13566 #define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__B                           4
13567 #define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__W                           1
13568 #define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__M                           0x10
13569 #define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__PRE                         0x0
13570 
13571 #define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__B                                5
13572 #define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__W                                1
13573 #define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__M                                0x20
13574 #define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__PRE                              0x0
13575 
13576 #define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__B                                 6
13577 #define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__W                                 1
13578 #define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__M                                 0x40
13579 #define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE                               0x0
13580 
13581 #define VSB_TOP_DLOCKACCUM__A                                               0x1C10071
13582 #define VSB_TOP_DLOCKACCUM__W                                               16
13583 #define VSB_TOP_DLOCKACCUM__M                                               0xFFFF
13584 #define VSB_TOP_DLOCKACCUM__PRE                                             0x0
13585 
13586 #define VSB_TOP_PLOCKACCUM__A                                               0x1C10072
13587 #define VSB_TOP_PLOCKACCUM__W                                               16
13588 #define VSB_TOP_PLOCKACCUM__M                                               0xFFFF
13589 #define VSB_TOP_PLOCKACCUM__PRE                                             0x0
13590 
13591 #define VSB_TOP_CLOCKACCUM__A                                               0x1C10073
13592 #define VSB_TOP_CLOCKACCUM__W                                               16
13593 #define VSB_TOP_CLOCKACCUM__M                                               0xFFFF
13594 #define VSB_TOP_CLOCKACCUM__PRE                                             0x0
13595 
13596 #define VSB_TOP_DCRMVACUMI__A                                               0x1C10074
13597 #define VSB_TOP_DCRMVACUMI__W                                               10
13598 #define VSB_TOP_DCRMVACUMI__M                                               0x3FF
13599 #define VSB_TOP_DCRMVACUMI__PRE                                             0x0
13600 
13601 #define VSB_TOP_DCRMVACUMQ__A                                               0x1C10075
13602 #define VSB_TOP_DCRMVACUMQ__W                                               10
13603 #define VSB_TOP_DCRMVACUMQ__M                                               0x3FF
13604 #define VSB_TOP_DCRMVACUMQ__PRE                                             0x0
13605 
13606 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A                                0x1C20000
13607 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W                                12
13608 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M                                0xFFF
13609 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__PRE                              0x0
13610 
13611 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__A                                0x1C20001
13612 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__W                                12
13613 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__M                                0xFFF
13614 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__PRE                              0x0
13615 
13616 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__A                                0x1C20002
13617 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__W                                12
13618 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__M                                0xFFF
13619 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__PRE                              0x0
13620 
13621 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__A                                0x1C20003
13622 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__W                                12
13623 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__M                                0xFFF
13624 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__PRE                              0x0
13625 
13626 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__A                                0x1C20004
13627 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__W                                12
13628 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__M                                0xFFF
13629 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__PRE                              0x0
13630 
13631 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__A                                0x1C20005
13632 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__W                                12
13633 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__M                                0xFFF
13634 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__PRE                              0x0
13635 
13636 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__A                                0x1C20006
13637 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__W                                12
13638 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__M                                0xFFF
13639 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__PRE                              0x0
13640 
13641 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__A                                0x1C20007
13642 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__W                                12
13643 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__M                                0xFFF
13644 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__PRE                              0x0
13645 
13646 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__A                                0x1C20008
13647 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__W                                12
13648 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__M                                0xFFF
13649 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__PRE                              0x0
13650 
13651 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__A                               0x1C20009
13652 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__W                               12
13653 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__M                               0xFFF
13654 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__PRE                             0x0
13655 
13656 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__A                               0x1C2000A
13657 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__W                               12
13658 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__M                               0xFFF
13659 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__PRE                             0x0
13660 
13661 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__A                               0x1C2000B
13662 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__W                               12
13663 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__M                               0xFFF
13664 #define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__PRE                             0x0
13665 
13666 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__A                            0x1C2000C
13667 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__W                            12
13668 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__M                            0xFFF
13669 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__PRE                          0x0
13670 
13671 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__A                            0x1C2000D
13672 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__W                            12
13673 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__M                            0xFFF
13674 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__PRE                          0x0
13675 
13676 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__A                            0x1C2000E
13677 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__W                            12
13678 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__M                            0xFFF
13679 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__PRE                          0x0
13680 
13681 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__A                            0x1C2000F
13682 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__W                            12
13683 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__M                            0xFFF
13684 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__PRE                          0x0
13685 
13686 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__A                            0x1C20010
13687 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__W                            12
13688 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__M                            0xFFF
13689 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__PRE                          0x0
13690 
13691 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__A                            0x1C20011
13692 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__W                            12
13693 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__M                            0xFFF
13694 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__PRE                          0x0
13695 
13696 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__A                            0x1C20012
13697 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__W                            12
13698 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__M                            0xFFF
13699 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__PRE                          0x0
13700 
13701 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__A                            0x1C20013
13702 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__W                            12
13703 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__M                            0xFFF
13704 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__PRE                          0x0
13705 
13706 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__A                            0x1C20014
13707 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__W                            12
13708 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__M                            0xFFF
13709 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__PRE                          0x0
13710 
13711 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__A                           0x1C20015
13712 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__W                           12
13713 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__M                           0xFFF
13714 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__PRE                         0x0
13715 
13716 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__A                           0x1C20016
13717 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__W                           12
13718 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__M                           0xFFF
13719 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__PRE                         0x0
13720 
13721 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__A                           0x1C20017
13722 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__W                           12
13723 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__M                           0xFFF
13724 #define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__PRE                         0x0
13725 
13726 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__A                             0x1C20018
13727 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__W                             12
13728 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__M                             0xFFF
13729 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__PRE                           0x0
13730 
13731 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__A                             0x1C20019
13732 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__W                             12
13733 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__M                             0xFFF
13734 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__PRE                           0x0
13735 
13736 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__A                             0x1C2001A
13737 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__W                             12
13738 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__M                             0xFFF
13739 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__PRE                           0x0
13740 
13741 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__A                             0x1C2001B
13742 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__W                             12
13743 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__M                             0xFFF
13744 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__PRE                           0x0
13745 
13746 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__A                             0x1C2001C
13747 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__W                             12
13748 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__M                             0xFFF
13749 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__PRE                           0x0
13750 
13751 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__A                             0x1C2001D
13752 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__W                             12
13753 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__M                             0xFFF
13754 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__PRE                           0x0
13755 
13756 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__A                             0x1C2001E
13757 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__W                             12
13758 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__M                             0xFFF
13759 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__PRE                           0x0
13760 
13761 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__A                             0x1C2001F
13762 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__W                             12
13763 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__M                             0xFFF
13764 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__PRE                           0x0
13765 
13766 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__A                             0x1C20020
13767 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__W                             12
13768 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__M                             0xFFF
13769 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__PRE                           0x0
13770 
13771 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__A                            0x1C20021
13772 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__W                            12
13773 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__M                            0xFFF
13774 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__PRE                          0x0
13775 
13776 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__A                            0x1C20022
13777 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__W                            12
13778 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__M                            0xFFF
13779 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__PRE                          0x0
13780 
13781 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__A                            0x1C20023
13782 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__W                            12
13783 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__M                            0xFFF
13784 #define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__PRE                          0x0
13785 
13786 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__A                            0x1C20024
13787 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__W                            12
13788 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__M                            0xFFF
13789 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__PRE                          0x0
13790 
13791 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__A                            0x1C20025
13792 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__W                            12
13793 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__M                            0xFFF
13794 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__PRE                          0x0
13795 
13796 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__A                            0x1C20026
13797 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__W                            12
13798 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__M                            0xFFF
13799 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__PRE                          0x0
13800 
13801 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__A                            0x1C20027
13802 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__W                            12
13803 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__M                            0xFFF
13804 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__PRE                          0x0
13805 
13806 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__A                            0x1C20028
13807 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__W                            12
13808 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__M                            0xFFF
13809 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__PRE                          0x0
13810 
13811 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__A                            0x1C20029
13812 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__W                            12
13813 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__M                            0xFFF
13814 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__PRE                          0x0
13815 
13816 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__A                            0x1C2002A
13817 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__W                            12
13818 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__M                            0xFFF
13819 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__PRE                          0x0
13820 
13821 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__A                            0x1C2002B
13822 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__W                            12
13823 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__M                            0xFFF
13824 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__PRE                          0x0
13825 
13826 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__A                            0x1C2002C
13827 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__W                            12
13828 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__M                            0xFFF
13829 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__PRE                          0x0
13830 
13831 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__A                           0x1C2002D
13832 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__W                           12
13833 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__M                           0xFFF
13834 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__PRE                         0x0
13835 
13836 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__A                           0x1C2002E
13837 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__W                           12
13838 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__M                           0xFFF
13839 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__PRE                         0x0
13840 
13841 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__A                           0x1C2002F
13842 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__W                           12
13843 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__M                           0xFFF
13844 #define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__PRE                         0x0
13845 
13846 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__A                             0x1C20030
13847 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__W                             12
13848 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__M                             0xFFF
13849 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__PRE                           0x0
13850 
13851 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__A                             0x1C20031
13852 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__W                             12
13853 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__M                             0xFFF
13854 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__PRE                           0x0
13855 
13856 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__A                             0x1C20032
13857 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__W                             12
13858 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__M                             0xFFF
13859 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__PRE                           0x0
13860 
13861 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__A                             0x1C20033
13862 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__W                             12
13863 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__M                             0xFFF
13864 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__PRE                           0x0
13865 
13866 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__A                             0x1C20034
13867 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__W                             12
13868 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__M                             0xFFF
13869 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__PRE                           0x0
13870 
13871 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__A                             0x1C20035
13872 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__W                             12
13873 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__M                             0xFFF
13874 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__PRE                           0x0
13875 
13876 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__A                             0x1C20036
13877 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__W                             12
13878 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__M                             0xFFF
13879 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__PRE                           0x0
13880 
13881 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__A                             0x1C20037
13882 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__W                             12
13883 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__M                             0xFFF
13884 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__PRE                           0x0
13885 
13886 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__A                             0x1C20038
13887 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__W                             12
13888 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__M                             0xFFF
13889 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__PRE                           0x0
13890 
13891 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__A                            0x1C20039
13892 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__W                            12
13893 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__M                            0xFFF
13894 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__PRE                          0x0
13895 
13896 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__A                            0x1C2003A
13897 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__W                            12
13898 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__M                            0xFFF
13899 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__PRE                          0x0
13900 
13901 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__A                            0x1C2003B
13902 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__W                            12
13903 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__M                            0xFFF
13904 #define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__PRE                          0x0
13905 
13906 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__A                            0x1C2003C
13907 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__W                            12
13908 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__M                            0xFFF
13909 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__PRE                          0x0
13910 
13911 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__A                            0x1C2003D
13912 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__W                            12
13913 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__M                            0xFFF
13914 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__PRE                          0x0
13915 
13916 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__A                            0x1C2003E
13917 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__W                            12
13918 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__M                            0xFFF
13919 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__PRE                          0x0
13920 
13921 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__A                            0x1C2003F
13922 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__W                            12
13923 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__M                            0xFFF
13924 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__PRE                          0x0
13925 
13926 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__A                            0x1C20040
13927 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__W                            12
13928 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__M                            0xFFF
13929 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__PRE                          0x0
13930 
13931 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__A                            0x1C20041
13932 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__W                            12
13933 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__M                            0xFFF
13934 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__PRE                          0x0
13935 
13936 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__A                            0x1C20042
13937 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__W                            12
13938 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__M                            0xFFF
13939 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__PRE                          0x0
13940 
13941 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__A                            0x1C20043
13942 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__W                            12
13943 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__M                            0xFFF
13944 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__PRE                          0x0
13945 
13946 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__A                            0x1C20044
13947 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__W                            12
13948 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__M                            0xFFF
13949 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__PRE                          0x0
13950 
13951 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__A                           0x1C20045
13952 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__W                           12
13953 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__M                           0xFFF
13954 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__PRE                         0x0
13955 
13956 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__A                           0x1C20046
13957 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__W                           12
13958 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__M                           0xFFF
13959 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__PRE                         0x0
13960 
13961 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__A                           0x1C20047
13962 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__W                           12
13963 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__M                           0xFFF
13964 #define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__PRE                         0x0
13965 
13966 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__A                             0x1C20048
13967 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__W                             12
13968 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__M                             0xFFF
13969 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__PRE                           0x0
13970 
13971 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__A                             0x1C20049
13972 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__W                             12
13973 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__M                             0xFFF
13974 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__PRE                           0x0
13975 
13976 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__A                             0x1C2004A
13977 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__W                             12
13978 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__M                             0xFFF
13979 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__PRE                           0x0
13980 
13981 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__A                             0x1C2004B
13982 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__W                             12
13983 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__M                             0xFFF
13984 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__PRE                           0x0
13985 
13986 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__A                             0x1C2004C
13987 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__W                             12
13988 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__M                             0xFFF
13989 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__PRE                           0x0
13990 
13991 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__A                             0x1C2004D
13992 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__W                             12
13993 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__M                             0xFFF
13994 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__PRE                           0x0
13995 
13996 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__A                             0x1C2004E
13997 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__W                             12
13998 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__M                             0xFFF
13999 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__PRE                           0x0
14000 
14001 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__A                             0x1C2004F
14002 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__W                             12
14003 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__M                             0xFFF
14004 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__PRE                           0x0
14005 
14006 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__A                             0x1C20050
14007 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__W                             12
14008 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__M                             0xFFF
14009 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__PRE                           0x0
14010 
14011 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__A                            0x1C20051
14012 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__W                            12
14013 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__M                            0xFFF
14014 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__PRE                          0x0
14015 
14016 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__A                            0x1C20052
14017 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__W                            12
14018 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__M                            0xFFF
14019 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__PRE                          0x0
14020 
14021 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__A                            0x1C20053
14022 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__W                            12
14023 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__M                            0xFFF
14024 #define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__PRE                          0x0
14025 
14026 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__A                            0x1C20054
14027 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__W                            12
14028 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__M                            0xFFF
14029 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__PRE                          0x0
14030 
14031 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__A                            0x1C20055
14032 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__W                            12
14033 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__M                            0xFFF
14034 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__PRE                          0x0
14035 
14036 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__A                            0x1C20056
14037 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__W                            12
14038 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__M                            0xFFF
14039 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__PRE                          0x0
14040 
14041 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__A                            0x1C20057
14042 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__W                            12
14043 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__M                            0xFFF
14044 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__PRE                          0x0
14045 
14046 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__A                            0x1C20058
14047 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__W                            12
14048 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__M                            0xFFF
14049 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__PRE                          0x0
14050 
14051 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__A                            0x1C20059
14052 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__W                            12
14053 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__M                            0xFFF
14054 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__PRE                          0x0
14055 
14056 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__A                            0x1C2005A
14057 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__W                            12
14058 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__M                            0xFFF
14059 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__PRE                          0x0
14060 
14061 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__A                            0x1C2005B
14062 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__W                            12
14063 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__M                            0xFFF
14064 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__PRE                          0x0
14065 
14066 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__A                            0x1C2005C
14067 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__W                            12
14068 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__M                            0xFFF
14069 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__PRE                          0x0
14070 
14071 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__A                           0x1C2005D
14072 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__W                           12
14073 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__M                           0xFFF
14074 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__PRE                         0x0
14075 
14076 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__A                           0x1C2005E
14077 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__W                           12
14078 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__M                           0xFFF
14079 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__PRE                         0x0
14080 
14081 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__A                           0x1C2005F
14082 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__W                           12
14083 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__M                           0xFFF
14084 #define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__PRE                         0x0
14085 
14086 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__A                             0x1C20060
14087 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__W                             12
14088 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__M                             0xFFF
14089 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__PRE                           0x0
14090 
14091 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__A                             0x1C20061
14092 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__W                             12
14093 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__M                             0xFFF
14094 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__PRE                           0x0
14095 
14096 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__A                             0x1C20062
14097 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__W                             12
14098 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__M                             0xFFF
14099 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__PRE                           0x0
14100 
14101 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__A                             0x1C20063
14102 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__W                             12
14103 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__M                             0xFFF
14104 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__PRE                           0x0
14105 
14106 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__A                             0x1C20064
14107 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__W                             12
14108 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__M                             0xFFF
14109 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__PRE                           0x0
14110 
14111 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__A                             0x1C20065
14112 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__W                             12
14113 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__M                             0xFFF
14114 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__PRE                           0x0
14115 
14116 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__A                             0x1C20066
14117 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__W                             12
14118 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__M                             0xFFF
14119 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__PRE                           0x0
14120 
14121 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__A                             0x1C20067
14122 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__W                             12
14123 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__M                             0xFFF
14124 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__PRE                           0x0
14125 
14126 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__A                             0x1C20068
14127 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__W                             12
14128 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__M                             0xFFF
14129 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__PRE                           0x0
14130 
14131 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__A                            0x1C20069
14132 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__W                            12
14133 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__M                            0xFFF
14134 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__PRE                          0x0
14135 
14136 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__A                            0x1C2006A
14137 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__W                            12
14138 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__M                            0xFFF
14139 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__PRE                          0x0
14140 
14141 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__A                            0x1C2006B
14142 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__W                            12
14143 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__M                            0xFFF
14144 #define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__PRE                          0x0
14145 
14146 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__A                                   0x1C2006C
14147 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__W                                   7
14148 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__M                                   0x7F
14149 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__PRE                                 0x0
14150 
14151 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__A                                   0x1C2006D
14152 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__W                                   7
14153 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__M                                   0x7F
14154 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__PRE                                 0x0
14155 
14156 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__A                                   0x1C2006E
14157 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__W                                   7
14158 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__M                                   0x7F
14159 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__PRE                                 0x0
14160 
14161 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__A                                   0x1C2006F
14162 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__W                                   7
14163 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__M                                   0x7F
14164 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__PRE                                 0x0
14165 
14166 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__A                                   0x1C20070
14167 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__W                                   7
14168 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__M                                   0x7F
14169 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__PRE                                 0x0
14170 
14171 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__A                                   0x1C20071
14172 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__W                                   7
14173 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__M                                   0x7F
14174 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__PRE                                 0x0
14175 
14176 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__A                                   0x1C20072
14177 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__W                                   7
14178 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__M                                   0x7F
14179 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__PRE                                 0x0
14180 
14181 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__A                                   0x1C20073
14182 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__W                                   7
14183 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__M                                   0x7F
14184 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__PRE                                 0x0
14185 
14186 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__A                                   0x1C20074
14187 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__W                                   7
14188 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__M                                   0x7F
14189 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__PRE                                 0x0
14190 
14191 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__A                                  0x1C20075
14192 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__W                                  7
14193 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__M                                  0x7F
14194 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__PRE                                0x0
14195 
14196 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__A                                  0x1C20076
14197 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__W                                  7
14198 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__M                                  0x7F
14199 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__PRE                                0x0
14200 
14201 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__A                                  0x1C20077
14202 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__W                                  7
14203 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__M                                  0x7F
14204 #define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__PRE                                0x0
14205 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__A                                    0x1C20078
14206 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__W                                    15
14207 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__M                                    0x7FFF
14208 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__PRE                                  0x0
14209 
14210 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__B                0
14211 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__W                7
14212 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__M                0x7F
14213 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__PRE              0x0
14214 
14215 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__B                 8
14216 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__W                 7
14217 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__M                 0x7F00
14218 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__PRE               0x0
14219 
14220 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__A                                    0x1C20079
14221 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__W                                    15
14222 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__M                                    0x7FFF
14223 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__PRE                                  0x0
14224 
14225 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__B                0
14226 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__W                7
14227 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__M                0x7F
14228 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__PRE              0x0
14229 
14230 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__B                 8
14231 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__W                 7
14232 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__M                 0x7F00
14233 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__PRE               0x0
14234 
14235 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__A                                    0x1C2007A
14236 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__W                                    15
14237 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__M                                    0x7FFF
14238 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__PRE                                  0x0
14239 
14240 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__B                0
14241 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__W                7
14242 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__M                0x7F
14243 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__PRE              0x0
14244 
14245 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__B                 8
14246 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__W                 7
14247 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__M                 0x7F00
14248 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__PRE               0x0
14249 
14250 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__A                                    0x1C2007B
14251 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__W                                    15
14252 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__M                                    0x7FFF
14253 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__PRE                                  0x0
14254 
14255 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__B                0
14256 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__W                7
14257 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__M                0x7F
14258 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__PRE              0x0
14259 
14260 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__B                 8
14261 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__W                 7
14262 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__M                 0x7F00
14263 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__PRE               0x0
14264 
14265 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__A                                    0x1C2007C
14266 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__W                                    15
14267 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__M                                    0x7FFF
14268 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__PRE                                  0x0
14269 
14270 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__B                0
14271 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__W                7
14272 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__M                0x7F
14273 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__PRE              0x0
14274 
14275 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__B                 8
14276 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__W                 7
14277 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__M                 0x7F00
14278 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__PRE               0x0
14279 
14280 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__A                                    0x1C2007D
14281 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__W                                    15
14282 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__M                                    0x7FFF
14283 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__PRE                                  0x0
14284 
14285 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__B                0
14286 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__W                7
14287 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__M                0x7F
14288 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__PRE              0x0
14289 
14290 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__B                 8
14291 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__W                 7
14292 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__M                 0x7F00
14293 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__PRE               0x0
14294 
14295 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__A                                    0x1C2007E
14296 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__W                                    15
14297 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__M                                    0x7FFF
14298 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__PRE                                  0x0
14299 
14300 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__B                0
14301 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__W                7
14302 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__M                0x7F
14303 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__PRE              0x0
14304 
14305 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__B                 8
14306 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__W                 7
14307 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__M                 0x7F00
14308 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__PRE               0x0
14309 
14310 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__A                                    0x1C2007F
14311 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__W                                    15
14312 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__M                                    0x7FFF
14313 #define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__PRE                                  0x0
14314 
14315 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__B                0
14316 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__W                7
14317 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__M                0x7F
14318 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__PRE              0x0
14319 
14320 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__B                 8
14321 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__W                 7
14322 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M                 0x7F00
14323 #define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE               0x0
14324 
14325 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A                                    0x1C30000
14326 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W                                    15
14327 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M                                    0x7FFF
14328 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__PRE                                  0x0
14329 
14330 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__B                0
14331 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__W                7
14332 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__M                0x7F
14333 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__PRE              0x0
14334 
14335 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__B                 8
14336 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__W                 7
14337 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__M                 0x7F00
14338 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__PRE               0x0
14339 
14340 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__A                                   0x1C30001
14341 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__W                                   15
14342 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__M                                   0x7FFF
14343 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__PRE                                 0x0
14344 
14345 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__B              0
14346 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__W              7
14347 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__M              0x7F
14348 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__PRE            0x0
14349 
14350 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__B               8
14351 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__W               7
14352 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__M               0x7F00
14353 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__PRE             0x0
14354 
14355 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__A                                   0x1C30002
14356 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__W                                   15
14357 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__M                                   0x7FFF
14358 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__PRE                                 0x0
14359 
14360 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__B              0
14361 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__W              7
14362 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__M              0x7F
14363 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__PRE            0x0
14364 
14365 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__B               8
14366 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__W               7
14367 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__M               0x7F00
14368 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__PRE             0x0
14369 
14370 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__A                                   0x1C30003
14371 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__W                                   15
14372 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__M                                   0x7FFF
14373 #define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__PRE                                 0x0
14374 
14375 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__B              0
14376 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__W              7
14377 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__M              0x7F
14378 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__PRE            0x0
14379 
14380 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__B               8
14381 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__W               7
14382 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__M               0x7F00
14383 #define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__PRE             0x0
14384 
14385 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__A                                    0x1C30004
14386 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__W                                    15
14387 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__M                                    0x7FFF
14388 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__PRE                                  0x0
14389 
14390 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__B                0
14391 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__W                7
14392 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__M                0x7F
14393 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__PRE              0x0
14394 
14395 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__B                 8
14396 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__W                 7
14397 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__M                 0x7F00
14398 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__PRE               0x0
14399 
14400 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__A                                    0x1C30005
14401 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__W                                    15
14402 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__M                                    0x7FFF
14403 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__PRE                                  0x0
14404 
14405 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__B                0
14406 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__W                7
14407 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__M                0x7F
14408 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__PRE              0x0
14409 
14410 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__B                 8
14411 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__W                 7
14412 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__M                 0x7F00
14413 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__PRE               0x0
14414 
14415 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__A                                    0x1C30006
14416 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__W                                    15
14417 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__M                                    0x7FFF
14418 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__PRE                                  0x0
14419 
14420 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__B                0
14421 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__W                7
14422 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__M                0x7F
14423 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__PRE              0x0
14424 
14425 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__B                 8
14426 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__W                 7
14427 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__M                 0x7F00
14428 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__PRE               0x0
14429 
14430 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__A                                    0x1C30007
14431 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__W                                    15
14432 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__M                                    0x7FFF
14433 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__PRE                                  0x0
14434 
14435 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__B                0
14436 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__W                7
14437 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__M                0x7F
14438 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__PRE              0x0
14439 
14440 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__B                 8
14441 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__W                 7
14442 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__M                 0x7F00
14443 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__PRE               0x0
14444 
14445 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__A                                    0x1C30008
14446 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__W                                    15
14447 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__M                                    0x7FFF
14448 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__PRE                                  0x0
14449 
14450 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__B                0
14451 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__W                7
14452 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__M                0x7F
14453 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__PRE              0x0
14454 
14455 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__B                 8
14456 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__W                 7
14457 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__M                 0x7F00
14458 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__PRE               0x0
14459 
14460 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__A                                    0x1C30009
14461 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__W                                    15
14462 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__M                                    0x7FFF
14463 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__PRE                                  0x0
14464 
14465 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__B                0
14466 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__W                7
14467 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__M                0x7F
14468 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__PRE              0x0
14469 
14470 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__B                 8
14471 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__W                 7
14472 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__M                 0x7F00
14473 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__PRE               0x0
14474 
14475 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__A                                    0x1C3000A
14476 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__W                                    15
14477 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__M                                    0x7FFF
14478 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__PRE                                  0x0
14479 
14480 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__B                0
14481 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__W                7
14482 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__M                0x7F
14483 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__PRE              0x0
14484 
14485 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__B                 8
14486 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__W                 7
14487 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__M                 0x7F00
14488 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__PRE               0x0
14489 
14490 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__A                                    0x1C3000B
14491 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__W                                    15
14492 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__M                                    0x7FFF
14493 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__PRE                                  0x0
14494 
14495 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__B                0
14496 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__W                7
14497 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__M                0x7F
14498 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__PRE              0x0
14499 
14500 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__B                 8
14501 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__W                 7
14502 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__M                 0x7F00
14503 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__PRE               0x0
14504 
14505 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__A                                    0x1C3000C
14506 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__W                                    15
14507 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__M                                    0x7FFF
14508 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__PRE                                  0x0
14509 
14510 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__B                0
14511 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__W                7
14512 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__M                0x7F
14513 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__PRE              0x0
14514 
14515 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__B                 8
14516 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__W                 7
14517 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__M                 0x7F00
14518 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__PRE               0x0
14519 
14520 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__A                                   0x1C3000D
14521 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__W                                   15
14522 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__M                                   0x7FFF
14523 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__PRE                                 0x0
14524 
14525 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__B              0
14526 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__W              7
14527 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__M              0x7F
14528 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__PRE            0x0
14529 
14530 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__B               8
14531 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__W               7
14532 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__M               0x7F00
14533 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__PRE             0x0
14534 
14535 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__A                                   0x1C3000E
14536 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__W                                   15
14537 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__M                                   0x7FFF
14538 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__PRE                                 0x0
14539 
14540 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__B              0
14541 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__W              7
14542 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__M              0x7F
14543 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__PRE            0x0
14544 
14545 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__B               8
14546 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__W               7
14547 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__M               0x7F00
14548 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__PRE             0x0
14549 
14550 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__A                                   0x1C3000F
14551 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__W                                   15
14552 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__M                                   0x7FFF
14553 #define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__PRE                                 0x0
14554 
14555 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__B              0
14556 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__W              7
14557 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__M              0x7F
14558 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__PRE            0x0
14559 
14560 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__B               8
14561 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__W               7
14562 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__M               0x7F00
14563 #define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__PRE             0x0
14564 
14565 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__A                                    0x1C30010
14566 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__W                                    15
14567 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__M                                    0x7FFF
14568 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__PRE                                  0x0
14569 
14570 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__B                0
14571 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__W                7
14572 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__M                0x7F
14573 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__PRE              0x0
14574 
14575 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__B                 8
14576 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__W                 7
14577 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__M                 0x7F00
14578 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__PRE               0x0
14579 
14580 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__A                                    0x1C30011
14581 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__W                                    15
14582 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__M                                    0x7FFF
14583 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__PRE                                  0x0
14584 
14585 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__B                0
14586 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__W                7
14587 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__M                0x7F
14588 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__PRE              0x0
14589 
14590 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__B                 8
14591 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__W                 7
14592 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__M                 0x7F00
14593 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__PRE               0x0
14594 
14595 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__A                                    0x1C30012
14596 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__W                                    15
14597 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__M                                    0x7FFF
14598 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__PRE                                  0x0
14599 
14600 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__B                0
14601 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__W                7
14602 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__M                0x7F
14603 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__PRE              0x0
14604 
14605 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__B                 8
14606 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__W                 7
14607 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__M                 0x7F00
14608 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__PRE               0x0
14609 
14610 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__A                                    0x1C30013
14611 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__W                                    15
14612 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__M                                    0x7FFF
14613 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__PRE                                  0x0
14614 
14615 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__B                0
14616 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__W                7
14617 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__M                0x7F
14618 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__PRE              0x0
14619 
14620 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__B                 8
14621 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__W                 7
14622 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__M                 0x7F00
14623 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__PRE               0x0
14624 
14625 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__A                                    0x1C30014
14626 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__W                                    15
14627 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__M                                    0x7FFF
14628 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__PRE                                  0x0
14629 
14630 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__B                0
14631 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__W                7
14632 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__M                0x7F
14633 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__PRE              0x0
14634 
14635 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__B                 8
14636 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__W                 7
14637 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__M                 0x7F00
14638 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__PRE               0x0
14639 
14640 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__A                                    0x1C30015
14641 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__W                                    15
14642 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__M                                    0x7FFF
14643 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__PRE                                  0x0
14644 
14645 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__B                0
14646 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__W                7
14647 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__M                0x7F
14648 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__PRE              0x0
14649 
14650 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__B                 8
14651 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__W                 7
14652 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__M                 0x7F00
14653 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__PRE               0x0
14654 
14655 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__A                                    0x1C30016
14656 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__W                                    15
14657 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__M                                    0x7FFF
14658 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__PRE                                  0x0
14659 
14660 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__B                0
14661 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__W                7
14662 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__M                0x7F
14663 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__PRE              0x0
14664 
14665 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__B                 8
14666 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__W                 7
14667 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__M                 0x7F00
14668 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__PRE               0x0
14669 
14670 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__A                                    0x1C30017
14671 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__W                                    15
14672 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__M                                    0x7FFF
14673 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__PRE                                  0x0
14674 
14675 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__B                0
14676 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__W                7
14677 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__M                0x7F
14678 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__PRE              0x0
14679 
14680 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__B                 8
14681 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__W                 7
14682 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__M                 0x7F00
14683 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__PRE               0x0
14684 
14685 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__A                                    0x1C30018
14686 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__W                                    15
14687 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__M                                    0x7FFF
14688 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__PRE                                  0x0
14689 
14690 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__B                0
14691 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__W                7
14692 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__M                0x7F
14693 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__PRE              0x0
14694 
14695 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__B                 8
14696 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__W                 7
14697 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__M                 0x7F00
14698 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__PRE               0x0
14699 
14700 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__A                                   0x1C30019
14701 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__W                                   15
14702 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__M                                   0x7FFF
14703 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__PRE                                 0x0
14704 
14705 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__B              0
14706 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__W              7
14707 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__M              0x7F
14708 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__PRE            0x0
14709 
14710 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__B               8
14711 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__W               7
14712 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__M               0x7F00
14713 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__PRE             0x0
14714 
14715 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__A                                   0x1C3001A
14716 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__W                                   15
14717 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__M                                   0x7FFF
14718 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__PRE                                 0x0
14719 
14720 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__B              0
14721 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__W              7
14722 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__M              0x7F
14723 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__PRE            0x0
14724 
14725 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__B               8
14726 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__W               7
14727 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__M               0x7F00
14728 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__PRE             0x0
14729 
14730 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__A                                   0x1C3001B
14731 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__W                                   15
14732 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__M                                   0x7FFF
14733 #define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__PRE                                 0x0
14734 
14735 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__B              0
14736 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__W              7
14737 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__M              0x7F
14738 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__PRE            0x0
14739 
14740 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__B               8
14741 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__W               7
14742 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__M               0x7F00
14743 #define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__PRE             0x0
14744 
14745 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__A                                    0x1C3001C
14746 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__W                                    15
14747 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__M                                    0x7FFF
14748 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__PRE                                  0x0
14749 
14750 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__B                0
14751 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__W                7
14752 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__M                0x7F
14753 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__PRE              0x0
14754 
14755 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__B                 8
14756 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__W                 7
14757 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__M                 0x7F00
14758 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__PRE               0x0
14759 
14760 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__A                                    0x1C3001D
14761 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__W                                    15
14762 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__M                                    0x7FFF
14763 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__PRE                                  0x0
14764 
14765 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__B                0
14766 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__W                7
14767 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__M                0x7F
14768 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__PRE              0x0
14769 
14770 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__B                 8
14771 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__W                 7
14772 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__M                 0x7F00
14773 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__PRE               0x0
14774 
14775 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__A                                    0x1C3001E
14776 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__W                                    15
14777 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__M                                    0x7FFF
14778 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__PRE                                  0x0
14779 
14780 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__B                0
14781 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__W                7
14782 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__M                0x7F
14783 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__PRE              0x0
14784 
14785 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__B                 8
14786 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__W                 7
14787 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__M                 0x7F00
14788 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__PRE               0x0
14789 
14790 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__A                                    0x1C3001F
14791 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__W                                    15
14792 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__M                                    0x7FFF
14793 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__PRE                                  0x0
14794 
14795 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__B                0
14796 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__W                7
14797 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__M                0x7F
14798 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__PRE              0x0
14799 
14800 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__B                 8
14801 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__W                 7
14802 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__M                 0x7F00
14803 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__PRE               0x0
14804 
14805 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__A                                    0x1C30020
14806 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__W                                    15
14807 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__M                                    0x7FFF
14808 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__PRE                                  0x0
14809 
14810 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__B                0
14811 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__W                7
14812 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__M                0x7F
14813 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__PRE              0x0
14814 
14815 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__B                 8
14816 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__W                 7
14817 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__M                 0x7F00
14818 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__PRE               0x0
14819 
14820 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__A                                    0x1C30021
14821 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__W                                    15
14822 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__M                                    0x7FFF
14823 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__PRE                                  0x0
14824 
14825 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__B                0
14826 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__W                7
14827 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__M                0x7F
14828 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__PRE              0x0
14829 
14830 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__B                 8
14831 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__W                 7
14832 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__M                 0x7F00
14833 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__PRE               0x0
14834 
14835 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__A                                    0x1C30022
14836 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__W                                    15
14837 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__M                                    0x7FFF
14838 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__PRE                                  0x0
14839 
14840 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__B                0
14841 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__W                7
14842 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__M                0x7F
14843 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__PRE              0x0
14844 
14845 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__B                 8
14846 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__W                 7
14847 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__M                 0x7F00
14848 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__PRE               0x0
14849 
14850 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__A                                    0x1C30023
14851 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__W                                    15
14852 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__M                                    0x7FFF
14853 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__PRE                                  0x0
14854 
14855 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__B                0
14856 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__W                7
14857 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__M                0x7F
14858 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__PRE              0x0
14859 
14860 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__B                 8
14861 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__W                 7
14862 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__M                 0x7F00
14863 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__PRE               0x0
14864 
14865 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__A                                    0x1C30024
14866 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__W                                    15
14867 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__M                                    0x7FFF
14868 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__PRE                                  0x0
14869 
14870 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__B                0
14871 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__W                7
14872 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__M                0x7F
14873 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__PRE              0x0
14874 
14875 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__B                 8
14876 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__W                 7
14877 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__M                 0x7F00
14878 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__PRE               0x0
14879 
14880 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__A                                   0x1C30025
14881 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__W                                   15
14882 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__M                                   0x7FFF
14883 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__PRE                                 0x0
14884 
14885 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__B              0
14886 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__W              7
14887 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__M              0x7F
14888 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__PRE            0x0
14889 
14890 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__B               8
14891 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__W               7
14892 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__M               0x7F00
14893 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__PRE             0x0
14894 
14895 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__A                                   0x1C30026
14896 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__W                                   15
14897 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__M                                   0x7FFF
14898 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__PRE                                 0x0
14899 
14900 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__B              0
14901 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__W              7
14902 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__M              0x7F
14903 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__PRE            0x0
14904 
14905 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__B               8
14906 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__W               7
14907 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__M               0x7F00
14908 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__PRE             0x0
14909 
14910 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__A                                   0x1C30027
14911 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__W                                   15
14912 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__M                                   0x7FFF
14913 #define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__PRE                                 0x0
14914 
14915 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__B              0
14916 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__W              7
14917 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__M              0x7F
14918 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__PRE            0x0
14919 
14920 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__B               8
14921 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__W               7
14922 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__M               0x7F00
14923 #define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__PRE             0x0
14924 
14925 #define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__A                                 0x1C30028
14926 #define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__W                                 12
14927 #define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__M                                 0xFFF
14928 #define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__PRE                               0x0
14929 
14930 #define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__A                             0x1C30029
14931 #define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__W                             12
14932 #define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__M                             0xFFF
14933 #define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__PRE                           0x0
14934 
14935 #define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__A                              0x1C3002A
14936 #define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__W                              12
14937 #define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__M                              0xFFF
14938 #define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__PRE                            0x0
14939 
14940 #define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__A                             0x1C3002B
14941 #define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__W                             12
14942 #define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__M                             0xFFF
14943 #define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__PRE                           0x0
14944 
14945 #define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__A                              0x1C3002C
14946 #define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__W                              12
14947 #define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__M                              0xFFF
14948 #define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__PRE                            0x0
14949 
14950 #define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__A                             0x1C3002D
14951 #define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__W                             12
14952 #define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__M                             0xFFF
14953 #define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__PRE                           0x0
14954 
14955 #define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__A                              0x1C3002E
14956 #define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__W                              12
14957 #define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__M                              0xFFF
14958 #define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__PRE                            0x0
14959 
14960 #define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__A                             0x1C3002F
14961 #define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__W                             12
14962 #define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__M                             0xFFF
14963 #define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__PRE                           0x0
14964 
14965 #define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__A                              0x1C30030
14966 #define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__W                              12
14967 #define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__M                              0xFFF
14968 #define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__PRE                            0x0
14969 
14970 #define VSB_SYSCTRL_RAM1_DFETRAINGAIN__A                                    0x1C30031
14971 #define VSB_SYSCTRL_RAM1_DFETRAINGAIN__W                                    7
14972 #define VSB_SYSCTRL_RAM1_DFETRAINGAIN__M                                    0x7F
14973 #define VSB_SYSCTRL_RAM1_DFETRAINGAIN__PRE                                  0x0
14974 #define VSB_SYSCTRL_RAM1_DFERCA1GAIN__A                                     0x1C30032
14975 #define VSB_SYSCTRL_RAM1_DFERCA1GAIN__W                                     15
14976 #define VSB_SYSCTRL_RAM1_DFERCA1GAIN__M                                     0x7FFF
14977 #define VSB_SYSCTRL_RAM1_DFERCA1GAIN__PRE                                   0x0
14978 
14979 #define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__B                  0
14980 #define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__W                  7
14981 #define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__M                  0x7F
14982 #define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__PRE                0x0
14983 
14984 #define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__B                   8
14985 #define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__W                   7
14986 #define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__M                   0x7F00
14987 #define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__PRE                 0x0
14988 
14989 #define VSB_SYSCTRL_RAM1_DFERCA2GAIN__A                                     0x1C30033
14990 #define VSB_SYSCTRL_RAM1_DFERCA2GAIN__W                                     15
14991 #define VSB_SYSCTRL_RAM1_DFERCA2GAIN__M                                     0x7FFF
14992 #define VSB_SYSCTRL_RAM1_DFERCA2GAIN__PRE                                   0x0
14993 
14994 #define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__B                  0
14995 #define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__W                  7
14996 #define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__M                  0x7F
14997 #define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__PRE                0x0
14998 
14999 #define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__B                   8
15000 #define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__W                   7
15001 #define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__M                   0x7F00
15002 #define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__PRE                 0x0
15003 
15004 #define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__A                                     0x1C30034
15005 #define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__W                                     15
15006 #define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__M                                     0x7FFF
15007 #define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__PRE                                   0x0
15008 
15009 #define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__B                  0
15010 #define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__W                  7
15011 #define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__M                  0x7F
15012 #define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__PRE                0x0
15013 
15014 #define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__B                   8
15015 #define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__W                   7
15016 #define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__M                   0x7F00
15017 #define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__PRE                 0x0
15018 
15019 #define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__A                                     0x1C30035
15020 #define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__W                                     15
15021 #define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__M                                     0x7FFF
15022 #define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__PRE                                   0x0
15023 
15024 #define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__B                  0
15025 #define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__W                  7
15026 #define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__M                  0x7F
15027 #define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__PRE                0x0
15028 
15029 #define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__B                   8
15030 #define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__W                   7
15031 #define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__M                   0x7F00
15032 #define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__PRE                 0x0
15033 
15034 #define VSB_TCMEQ_RAM__A                                                    0x1C40000
15035 
15036 #define   VSB_TCMEQ_RAM_TCMEQ_RAM__B                                        0
15037 #define   VSB_TCMEQ_RAM_TCMEQ_RAM__W                                        16
15038 #define   VSB_TCMEQ_RAM_TCMEQ_RAM__M                                        0xFFFF
15039 #define   VSB_TCMEQ_RAM_TCMEQ_RAM__PRE                                      0x0
15040 
15041 #define VSB_FCPRE_RAM__A                                                    0x1C50000
15042 
15043 #define   VSB_FCPRE_RAM_FCPRE_RAM__B                                        0
15044 #define   VSB_FCPRE_RAM_FCPRE_RAM__W                                        16
15045 #define   VSB_FCPRE_RAM_FCPRE_RAM__M                                        0xFFFF
15046 #define   VSB_FCPRE_RAM_FCPRE_RAM__PRE                                      0x0
15047 
15048 #define VSB_EQTAP_RAM__A                                                    0x1C60000
15049 
15050 #define   VSB_EQTAP_RAM_EQTAP_RAM__B                                        0
15051 #define   VSB_EQTAP_RAM_EQTAP_RAM__W                                        12
15052 #define   VSB_EQTAP_RAM_EQTAP_RAM__M                                        0xFFF
15053 #define   VSB_EQTAP_RAM_EQTAP_RAM__PRE                                      0x0
15054 
15055 #endif
15056