1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * adv7604 - Analog Devices ADV7604 video decoder driver 4 * 5 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 * 7 */ 8 9 /* 10 * References (c = chapter, p = page): 11 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 12 * Revision 2.5, June 2010 13 * REF_02 - Analog devices, Register map documentation, Documentation of 14 * the register maps, Software manual, Rev. F, June 2010 15 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 16 */ 17 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/hdmi.h> 21 #include <linux/i2c.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of_graph.h> 25 #include <linux/slab.h> 26 #include <linux/v4l2-dv-timings.h> 27 #include <linux/videodev2.h> 28 #include <linux/workqueue.h> 29 #include <linux/regmap.h> 30 #include <linux/interrupt.h> 31 32 #include <media/i2c/adv7604.h> 33 #include <media/cec.h> 34 #include <media/v4l2-ctrls.h> 35 #include <media/v4l2-device.h> 36 #include <media/v4l2-event.h> 37 #include <media/v4l2-dv-timings.h> 38 #include <media/v4l2-fwnode.h> 39 40 static int debug; 41 module_param(debug, int, 0644); 42 MODULE_PARM_DESC(debug, "debug level (0-2)"); 43 44 MODULE_DESCRIPTION("Analog Devices ADV7604/10/11/12 video decoder driver"); 45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 46 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 47 MODULE_LICENSE("GPL"); 48 49 /* ADV7604 system clock frequency */ 50 #define ADV76XX_FSC (28636360) 51 52 #define ADV76XX_RGB_OUT (1 << 1) 53 54 #define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0) 55 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 56 #define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0) 57 58 #define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5) 59 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 60 #define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5) 61 #define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 62 #define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5) 63 #define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 64 65 #define ADV76XX_OP_CH_SEL_GBR (0 << 5) 66 #define ADV76XX_OP_CH_SEL_GRB (1 << 5) 67 #define ADV76XX_OP_CH_SEL_BGR (2 << 5) 68 #define ADV76XX_OP_CH_SEL_RGB (3 << 5) 69 #define ADV76XX_OP_CH_SEL_BRG (4 << 5) 70 #define ADV76XX_OP_CH_SEL_RBG (5 << 5) 71 72 #define ADV76XX_OP_SWAP_CB_CR (1 << 0) 73 74 #define ADV76XX_MAX_ADDRS (3) 75 76 #define ADV76XX_MAX_EDID_BLOCKS 4 77 78 enum adv76xx_type { 79 ADV7604, 80 ADV7611, // including ADV7610 81 ADV7612, 82 }; 83 84 struct adv76xx_reg_seq { 85 unsigned int reg; 86 u8 val; 87 }; 88 89 struct adv76xx_format_info { 90 u32 code; 91 u8 op_ch_sel; 92 bool rgb_out; 93 bool swap_cb_cr; 94 u8 op_format_sel; 95 }; 96 97 struct adv76xx_cfg_read_infoframe { 98 const char *desc; 99 u8 present_mask; 100 u8 head_addr; 101 u8 payload_addr; 102 }; 103 104 struct adv76xx_chip_info { 105 enum adv76xx_type type; 106 107 bool has_afe; 108 unsigned int max_port; 109 unsigned int num_dv_ports; 110 111 unsigned int edid_enable_reg; 112 unsigned int edid_status_reg; 113 unsigned int edid_segment_reg; 114 unsigned int edid_segment_mask; 115 unsigned int edid_spa_loc_reg; 116 unsigned int edid_spa_loc_msb_mask; 117 unsigned int edid_spa_port_b_reg; 118 unsigned int lcf_reg; 119 120 unsigned int cable_det_mask; 121 unsigned int tdms_lock_mask; 122 unsigned int fmt_change_digital_mask; 123 unsigned int cp_csc; 124 125 unsigned int cec_irq_status; 126 unsigned int cec_rx_enable; 127 unsigned int cec_rx_enable_mask; 128 bool cec_irq_swap; 129 130 const struct adv76xx_format_info *formats; 131 unsigned int nformats; 132 133 void (*set_termination)(struct v4l2_subdev *sd, bool enable); 134 void (*setup_irqs)(struct v4l2_subdev *sd); 135 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 136 unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 137 138 /* 0 = AFE, 1 = HDMI */ 139 const struct adv76xx_reg_seq *recommended_settings[2]; 140 unsigned int num_recommended_settings[2]; 141 142 unsigned long page_mask; 143 144 /* Masks for timings */ 145 unsigned int linewidth_mask; 146 unsigned int field0_height_mask; 147 unsigned int field1_height_mask; 148 unsigned int hfrontporch_mask; 149 unsigned int hsync_mask; 150 unsigned int hbackporch_mask; 151 unsigned int field0_vfrontporch_mask; 152 unsigned int field1_vfrontporch_mask; 153 unsigned int field0_vsync_mask; 154 unsigned int field1_vsync_mask; 155 unsigned int field0_vbackporch_mask; 156 unsigned int field1_vbackporch_mask; 157 }; 158 159 /* 160 ********************************************************************** 161 * 162 * Arrays with configuration parameters for the ADV7604 163 * 164 ********************************************************************** 165 */ 166 167 struct adv76xx_state { 168 const struct adv76xx_chip_info *info; 169 struct adv76xx_platform_data pdata; 170 171 struct gpio_desc *hpd_gpio[4]; 172 struct gpio_desc *reset_gpio; 173 174 struct v4l2_subdev sd; 175 struct media_pad pads[ADV76XX_PAD_MAX]; 176 unsigned int source_pad; 177 178 struct v4l2_ctrl_handler hdl; 179 180 enum adv76xx_pad selected_input; 181 182 struct v4l2_dv_timings timings; 183 const struct adv76xx_format_info *format; 184 185 struct { 186 u8 edid[ADV76XX_MAX_EDID_BLOCKS * 128]; 187 u32 present; 188 unsigned blocks; 189 } edid; 190 u16 spa_port_a[2]; 191 struct v4l2_fract aspect_ratio; 192 u32 rgb_quantization_range; 193 struct delayed_work delayed_work_enable_hotplug; 194 bool restart_stdi_once; 195 196 /* CEC */ 197 struct cec_adapter *cec_adap; 198 u8 cec_addr[ADV76XX_MAX_ADDRS]; 199 u8 cec_valid_addrs; 200 bool cec_enabled_adap; 201 202 /* i2c clients */ 203 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX]; 204 205 /* Regmaps */ 206 struct regmap *regmap[ADV76XX_PAGE_MAX]; 207 208 /* controls */ 209 struct v4l2_ctrl *detect_tx_5v_ctrl; 210 struct v4l2_ctrl *analog_sampling_phase_ctrl; 211 struct v4l2_ctrl *free_run_color_manual_ctrl; 212 struct v4l2_ctrl *free_run_color_ctrl; 213 struct v4l2_ctrl *rgb_quantization_range_ctrl; 214 }; 215 216 static bool adv76xx_has_afe(struct adv76xx_state *state) 217 { 218 return state->info->has_afe; 219 } 220 221 /* Unsupported timings. This device cannot support 720p30. */ 222 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = { 223 V4L2_DV_BT_CEA_1280X720P30, 224 { } 225 }; 226 227 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl) 228 { 229 int i; 230 231 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++) 232 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false)) 233 return false; 234 return true; 235 } 236 237 struct adv76xx_video_standards { 238 struct v4l2_dv_timings timings; 239 u8 vid_std; 240 u8 v_freq; 241 }; 242 243 /* sorted by number of lines */ 244 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = { 245 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 246 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 247 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 248 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 249 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 250 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 251 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 252 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 253 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 254 /* TODO add 1920x1080P60_RB (CVT timing) */ 255 { }, 256 }; 257 258 /* sorted by number of lines */ 259 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = { 260 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 261 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 262 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 263 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 264 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 265 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 266 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 267 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 268 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 269 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 270 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 271 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 272 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 273 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 274 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 275 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 276 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 277 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 278 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 279 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 280 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 281 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 282 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 283 { }, 284 }; 285 286 /* sorted by number of lines */ 287 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = { 288 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 289 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 290 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 291 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 292 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 293 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 294 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 295 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 296 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 297 { }, 298 }; 299 300 /* sorted by number of lines */ 301 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = { 302 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 303 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 304 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 305 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 306 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 307 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 308 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 309 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 310 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 311 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 312 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 313 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 314 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 315 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 316 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 317 { }, 318 }; 319 320 static const struct v4l2_event adv76xx_ev_fmt = { 321 .type = V4L2_EVENT_SOURCE_CHANGE, 322 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 323 }; 324 325 /* ----------------------------------------------------------------------- */ 326 327 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) 328 { 329 return container_of(sd, struct adv76xx_state, sd); 330 } 331 332 static inline unsigned htotal(const struct v4l2_bt_timings *t) 333 { 334 return V4L2_DV_BT_FRAME_WIDTH(t); 335 } 336 337 static inline unsigned vtotal(const struct v4l2_bt_timings *t) 338 { 339 return V4L2_DV_BT_FRAME_HEIGHT(t); 340 } 341 342 /* ----------------------------------------------------------------------- */ 343 344 static int adv76xx_read_check(struct adv76xx_state *state, 345 int client_page, u8 reg) 346 { 347 struct i2c_client *client = state->i2c_clients[client_page]; 348 int err; 349 unsigned int val; 350 351 err = regmap_read(state->regmap[client_page], reg, &val); 352 353 if (err) { 354 v4l_err(client, "error reading %02x, %02x\n", 355 client->addr, reg); 356 return err; 357 } 358 return val; 359 } 360 361 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX 362 * size to one or more registers. 363 * 364 * A value of zero will be returned on success, a negative errno will 365 * be returned in error cases. 366 */ 367 static int adv76xx_write_block(struct adv76xx_state *state, int client_page, 368 unsigned int init_reg, const void *val, 369 size_t val_len) 370 { 371 struct regmap *regmap = state->regmap[client_page]; 372 373 if (val_len > I2C_SMBUS_BLOCK_MAX) 374 val_len = I2C_SMBUS_BLOCK_MAX; 375 376 return regmap_raw_write(regmap, init_reg, val, val_len); 377 } 378 379 /* ----------------------------------------------------------------------- */ 380 381 static inline int io_read(struct v4l2_subdev *sd, u8 reg) 382 { 383 struct adv76xx_state *state = to_state(sd); 384 385 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg); 386 } 387 388 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 389 { 390 struct adv76xx_state *state = to_state(sd); 391 392 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); 393 } 394 395 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, 396 u8 val) 397 { 398 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); 399 } 400 401 static inline int __always_unused avlink_read(struct v4l2_subdev *sd, u8 reg) 402 { 403 struct adv76xx_state *state = to_state(sd); 404 405 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg); 406 } 407 408 static inline int __always_unused avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 409 { 410 struct adv76xx_state *state = to_state(sd); 411 412 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); 413 } 414 415 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 416 { 417 struct adv76xx_state *state = to_state(sd); 418 419 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg); 420 } 421 422 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 423 { 424 struct adv76xx_state *state = to_state(sd); 425 426 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); 427 } 428 429 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, 430 u8 val) 431 { 432 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); 433 } 434 435 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 436 { 437 struct adv76xx_state *state = to_state(sd); 438 439 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg); 440 } 441 442 static inline int __always_unused infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 443 { 444 struct adv76xx_state *state = to_state(sd); 445 446 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); 447 } 448 449 static inline int __always_unused afe_read(struct v4l2_subdev *sd, u8 reg) 450 { 451 struct adv76xx_state *state = to_state(sd); 452 453 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg); 454 } 455 456 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 457 { 458 struct adv76xx_state *state = to_state(sd); 459 460 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); 461 } 462 463 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 464 { 465 struct adv76xx_state *state = to_state(sd); 466 467 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg); 468 } 469 470 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 471 { 472 struct adv76xx_state *state = to_state(sd); 473 474 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); 475 } 476 477 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 478 { 479 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); 480 } 481 482 static inline int __always_unused edid_read(struct v4l2_subdev *sd, u8 reg) 483 { 484 struct adv76xx_state *state = to_state(sd); 485 486 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg); 487 } 488 489 static inline int __always_unused edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 490 { 491 struct adv76xx_state *state = to_state(sd); 492 493 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); 494 } 495 496 static inline int edid_write_block(struct v4l2_subdev *sd, 497 unsigned int total_len, const u8 *val) 498 { 499 struct adv76xx_state *state = to_state(sd); 500 int err = 0; 501 int i = 0; 502 int len = 0; 503 504 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", 505 __func__, total_len); 506 507 while (!err && i < total_len) { 508 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? 509 I2C_SMBUS_BLOCK_MAX : 510 (total_len - i); 511 512 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID, 513 i, val + i, len); 514 i += len; 515 } 516 517 return err; 518 } 519 520 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd) 521 { 522 const struct adv76xx_chip_info *info = state->info; 523 unsigned int i; 524 525 if (info->type == ADV7604) { 526 for (i = 0; i < state->info->num_dv_ports; ++i) 527 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 528 } else { 529 for (i = 0; i < state->info->num_dv_ports; ++i) 530 io_write_clr_set(&state->sd, 0x20, 0x80 >> i, 531 (!!(hpd & BIT(i))) << (7 - i)); 532 } 533 534 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); 535 } 536 537 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work) 538 { 539 struct delayed_work *dwork = to_delayed_work(work); 540 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state, 541 delayed_work_enable_hotplug); 542 struct v4l2_subdev *sd = &state->sd; 543 544 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 545 546 adv76xx_set_hpd(state, state->edid.present); 547 } 548 549 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 550 { 551 struct adv76xx_state *state = to_state(sd); 552 553 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg); 554 } 555 556 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 557 { 558 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 559 } 560 561 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 562 { 563 struct adv76xx_state *state = to_state(sd); 564 565 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); 566 } 567 568 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 569 { 570 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); 571 } 572 573 static inline int __always_unused test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 574 { 575 struct adv76xx_state *state = to_state(sd); 576 577 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); 578 } 579 580 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 581 { 582 struct adv76xx_state *state = to_state(sd); 583 584 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg); 585 } 586 587 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 588 { 589 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 590 } 591 592 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 593 { 594 struct adv76xx_state *state = to_state(sd); 595 596 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); 597 } 598 599 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 600 { 601 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); 602 } 603 604 static inline int __always_unused vdp_read(struct v4l2_subdev *sd, u8 reg) 605 { 606 struct adv76xx_state *state = to_state(sd); 607 608 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg); 609 } 610 611 static inline int __always_unused vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 612 { 613 struct adv76xx_state *state = to_state(sd); 614 615 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); 616 } 617 618 #define ADV76XX_REG(page, offset) (((page) << 8) | (offset)) 619 #define ADV76XX_REG_SEQ_TERM 0xffff 620 621 #ifdef CONFIG_VIDEO_ADV_DEBUG 622 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) 623 { 624 struct adv76xx_state *state = to_state(sd); 625 unsigned int page = reg >> 8; 626 unsigned int val; 627 int err; 628 629 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) 630 return -EINVAL; 631 632 reg &= 0xff; 633 err = regmap_read(state->regmap[page], reg, &val); 634 635 return err ? err : val; 636 } 637 #endif 638 639 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 640 { 641 struct adv76xx_state *state = to_state(sd); 642 unsigned int page = reg >> 8; 643 644 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) 645 return -EINVAL; 646 647 reg &= 0xff; 648 649 return regmap_write(state->regmap[page], reg, val); 650 } 651 652 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, 653 const struct adv76xx_reg_seq *reg_seq) 654 { 655 unsigned int i; 656 657 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) 658 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 659 } 660 661 /* ----------------------------------------------------------------------------- 662 * Format helpers 663 */ 664 665 static const struct adv76xx_format_info adv7604_formats[] = { 666 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 667 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 668 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 669 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 670 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 671 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 672 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false, 673 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 674 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true, 675 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 676 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 677 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 678 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 679 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 680 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 681 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 682 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 683 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 684 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 685 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 686 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 687 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 688 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false, 689 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 690 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true, 691 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 692 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false, 693 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 694 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true, 695 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 696 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 697 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 698 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 699 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 700 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 701 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 702 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 703 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 704 }; 705 706 static const struct adv76xx_format_info adv7611_formats[] = { 707 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 708 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 709 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 710 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 711 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 712 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 713 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false, 714 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 715 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true, 716 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT }, 717 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 718 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 719 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 720 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 721 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 722 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 723 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 724 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 725 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false, 726 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 727 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true, 728 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 729 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false, 730 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 731 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true, 732 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT }, 733 }; 734 735 static const struct adv76xx_format_info adv7612_formats[] = { 736 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false, 737 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT }, 738 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false, 739 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 740 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true, 741 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT }, 742 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false, 743 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 744 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true, 745 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 746 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false, 747 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 748 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true, 749 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT }, 750 }; 751 752 static const struct adv76xx_format_info * 753 adv76xx_format_info(struct adv76xx_state *state, u32 code) 754 { 755 unsigned int i; 756 757 for (i = 0; i < state->info->nformats; ++i) { 758 if (state->info->formats[i].code == code) 759 return &state->info->formats[i]; 760 } 761 762 return NULL; 763 } 764 765 /* ----------------------------------------------------------------------- */ 766 767 static inline bool is_analog_input(struct v4l2_subdev *sd) 768 { 769 struct adv76xx_state *state = to_state(sd); 770 771 return state->selected_input == ADV7604_PAD_VGA_RGB || 772 state->selected_input == ADV7604_PAD_VGA_COMP; 773 } 774 775 static inline bool is_digital_input(struct v4l2_subdev *sd) 776 { 777 struct adv76xx_state *state = to_state(sd); 778 779 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || 780 state->selected_input == ADV7604_PAD_HDMI_PORT_B || 781 state->selected_input == ADV7604_PAD_HDMI_PORT_C || 782 state->selected_input == ADV7604_PAD_HDMI_PORT_D; 783 } 784 785 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = { 786 .type = V4L2_DV_BT_656_1120, 787 /* keep this initialization for compatibility with GCC < 4.4.6 */ 788 .reserved = { 0 }, 789 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000, 790 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 791 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 792 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 793 V4L2_DV_BT_CAP_CUSTOM) 794 }; 795 796 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = { 797 .type = V4L2_DV_BT_656_1120, 798 /* keep this initialization for compatibility with GCC < 4.4.6 */ 799 .reserved = { 0 }, 800 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000, 801 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 802 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, 803 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING | 804 V4L2_DV_BT_CAP_CUSTOM) 805 }; 806 807 /* 808 * Return the DV timings capabilities for the requested sink pad. As a special 809 * case, pad value -1 returns the capabilities for the currently selected input. 810 */ 811 static const struct v4l2_dv_timings_cap * 812 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad) 813 { 814 if (pad == -1) { 815 struct adv76xx_state *state = to_state(sd); 816 817 pad = state->selected_input; 818 } 819 820 switch (pad) { 821 case ADV76XX_PAD_HDMI_PORT_A: 822 case ADV7604_PAD_HDMI_PORT_B: 823 case ADV7604_PAD_HDMI_PORT_C: 824 case ADV7604_PAD_HDMI_PORT_D: 825 return &adv76xx_timings_cap_digital; 826 827 case ADV7604_PAD_VGA_RGB: 828 case ADV7604_PAD_VGA_COMP: 829 default: 830 return &adv7604_timings_cap_analog; 831 } 832 } 833 834 835 /* ----------------------------------------------------------------------- */ 836 837 #ifdef CONFIG_VIDEO_ADV_DEBUG 838 static void adv76xx_inv_register(struct v4l2_subdev *sd) 839 { 840 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 841 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 842 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 843 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 844 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 845 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 846 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 847 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 848 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 849 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 850 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 851 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 852 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 853 } 854 855 static int adv76xx_g_register(struct v4l2_subdev *sd, 856 struct v4l2_dbg_register *reg) 857 { 858 int ret; 859 860 ret = adv76xx_read_reg(sd, reg->reg); 861 if (ret < 0) { 862 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 863 adv76xx_inv_register(sd); 864 return ret; 865 } 866 867 reg->size = 1; 868 reg->val = ret; 869 870 return 0; 871 } 872 873 static int adv76xx_s_register(struct v4l2_subdev *sd, 874 const struct v4l2_dbg_register *reg) 875 { 876 int ret; 877 878 ret = adv76xx_write_reg(sd, reg->reg, reg->val); 879 if (ret < 0) { 880 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 881 adv76xx_inv_register(sd); 882 return ret; 883 } 884 885 return 0; 886 } 887 #endif 888 889 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 890 { 891 u8 value = io_read(sd, 0x6f); 892 893 return ((value & 0x10) >> 4) 894 | ((value & 0x08) >> 2) 895 | ((value & 0x04) << 0) 896 | ((value & 0x02) << 2); 897 } 898 899 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 900 { 901 u8 value = io_read(sd, 0x6f); 902 903 return value & 1; 904 } 905 906 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd) 907 { 908 /* Reads CABLE_DET_A_RAW. For input B support, need to 909 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW) 910 */ 911 u8 value = io_read(sd, 0x6f); 912 913 return value & 1; 914 } 915 916 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 917 { 918 struct adv76xx_state *state = to_state(sd); 919 const struct adv76xx_chip_info *info = state->info; 920 u16 cable_det = info->read_cable_det(sd); 921 922 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); 923 } 924 925 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 926 u8 prim_mode, 927 const struct adv76xx_video_standards *predef_vid_timings, 928 const struct v4l2_dv_timings *timings) 929 { 930 int i; 931 932 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 933 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 934 is_digital_input(sd) ? 250000 : 1000000, false)) 935 continue; 936 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 937 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 938 prim_mode); /* v_freq and prim mode */ 939 return 0; 940 } 941 942 return -1; 943 } 944 945 static int configure_predefined_video_timings(struct v4l2_subdev *sd, 946 struct v4l2_dv_timings *timings) 947 { 948 struct adv76xx_state *state = to_state(sd); 949 int err; 950 951 v4l2_dbg(1, debug, sd, "%s", __func__); 952 953 if (adv76xx_has_afe(state)) { 954 /* reset to default values */ 955 io_write(sd, 0x16, 0x43); 956 io_write(sd, 0x17, 0x5a); 957 } 958 /* disable embedded syncs for auto graphics mode */ 959 cp_write_clr_set(sd, 0x81, 0x10, 0x00); 960 cp_write(sd, 0x8f, 0x00); 961 cp_write(sd, 0x90, 0x00); 962 cp_write(sd, 0xa2, 0x00); 963 cp_write(sd, 0xa3, 0x00); 964 cp_write(sd, 0xa4, 0x00); 965 cp_write(sd, 0xa5, 0x00); 966 cp_write(sd, 0xa6, 0x00); 967 cp_write(sd, 0xa7, 0x00); 968 cp_write(sd, 0xab, 0x00); 969 cp_write(sd, 0xac, 0x00); 970 971 if (is_analog_input(sd)) { 972 err = find_and_set_predefined_video_timings(sd, 973 0x01, adv7604_prim_mode_comp, timings); 974 if (err) 975 err = find_and_set_predefined_video_timings(sd, 976 0x02, adv7604_prim_mode_gr, timings); 977 } else if (is_digital_input(sd)) { 978 err = find_and_set_predefined_video_timings(sd, 979 0x05, adv76xx_prim_mode_hdmi_comp, timings); 980 if (err) 981 err = find_and_set_predefined_video_timings(sd, 982 0x06, adv76xx_prim_mode_hdmi_gr, timings); 983 } else { 984 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 985 __func__, state->selected_input); 986 err = -1; 987 } 988 989 990 return err; 991 } 992 993 static void configure_custom_video_timings(struct v4l2_subdev *sd, 994 const struct v4l2_bt_timings *bt) 995 { 996 struct adv76xx_state *state = to_state(sd); 997 u32 width = htotal(bt); 998 u32 height = vtotal(bt); 999 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 1000 u16 cp_start_eav = width - bt->hfrontporch; 1001 u16 cp_start_vbi = height - bt->vfrontporch; 1002 u16 cp_end_vbi = bt->vsync + bt->vbackporch; 1003 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 1004 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; 1005 const u8 pll[2] = { 1006 0xc0 | ((width >> 8) & 0x1f), 1007 width & 0xff 1008 }; 1009 1010 v4l2_dbg(2, debug, sd, "%s\n", __func__); 1011 1012 if (is_analog_input(sd)) { 1013 /* auto graphics */ 1014 io_write(sd, 0x00, 0x07); /* video std */ 1015 io_write(sd, 0x01, 0x02); /* prim mode */ 1016 /* enable embedded syncs for auto graphics mode */ 1017 cp_write_clr_set(sd, 0x81, 0x10, 0x10); 1018 1019 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 1020 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 1021 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 1022 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], 1023 0x16, pll, 2)) 1024 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 1025 1026 /* active video - horizontal timing */ 1027 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 1028 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 1029 ((cp_start_eav >> 8) & 0x0f)); 1030 cp_write(sd, 0xa4, cp_start_eav & 0xff); 1031 1032 /* active video - vertical timing */ 1033 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 1034 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 1035 ((cp_end_vbi >> 8) & 0xf)); 1036 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 1037 } else if (is_digital_input(sd)) { 1038 /* set default prim_mode/vid_std for HDMI 1039 according to [REF_03, c. 4.2] */ 1040 io_write(sd, 0x00, 0x02); /* video std */ 1041 io_write(sd, 0x01, 0x06); /* prim mode */ 1042 } else { 1043 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1044 __func__, state->selected_input); 1045 } 1046 1047 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 1048 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 1049 cp_write(sd, 0xab, (height >> 4) & 0xff); 1050 cp_write(sd, 0xac, (height & 0x0f) << 4); 1051 } 1052 1053 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1054 { 1055 struct adv76xx_state *state = to_state(sd); 1056 u8 offset_buf[4]; 1057 1058 if (auto_offset) { 1059 offset_a = 0x3ff; 1060 offset_b = 0x3ff; 1061 offset_c = 0x3ff; 1062 } 1063 1064 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1065 __func__, auto_offset ? "Auto" : "Manual", 1066 offset_a, offset_b, offset_c); 1067 1068 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1069 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1070 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1071 offset_buf[3] = offset_c & 0x0ff; 1072 1073 /* Registers must be written in this order with no i2c access in between */ 1074 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1075 0x77, offset_buf, 4)) 1076 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1077 } 1078 1079 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1080 { 1081 struct adv76xx_state *state = to_state(sd); 1082 u8 gain_buf[4]; 1083 u8 gain_man = 1; 1084 u8 agc_mode_man = 1; 1085 1086 if (auto_gain) { 1087 gain_man = 0; 1088 agc_mode_man = 0; 1089 gain_a = 0x100; 1090 gain_b = 0x100; 1091 gain_c = 0x100; 1092 } 1093 1094 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1095 __func__, auto_gain ? "Auto" : "Manual", 1096 gain_a, gain_b, gain_c); 1097 1098 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1099 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1100 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1101 gain_buf[3] = ((gain_c & 0x0ff)); 1102 1103 /* Registers must be written in this order with no i2c access in between */ 1104 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], 1105 0x73, gain_buf, 4)) 1106 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1107 } 1108 1109 static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1110 { 1111 struct adv76xx_state *state = to_state(sd); 1112 bool rgb_output = io_read(sd, 0x02) & 0x02; 1113 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1114 u8 y = HDMI_COLORSPACE_RGB; 1115 1116 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1117 y = infoframe_read(sd, 0x01) >> 5; 1118 1119 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1120 __func__, state->rgb_quantization_range, 1121 rgb_output, hdmi_signal); 1122 1123 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); 1124 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); 1125 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); 1126 1127 switch (state->rgb_quantization_range) { 1128 case V4L2_DV_RGB_RANGE_AUTO: 1129 if (state->selected_input == ADV7604_PAD_VGA_RGB) { 1130 /* Receiving analog RGB signal 1131 * Set RGB full range (0-255) */ 1132 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1133 break; 1134 } 1135 1136 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1137 /* Receiving analog YPbPr signal 1138 * Set automode */ 1139 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1140 break; 1141 } 1142 1143 if (hdmi_signal) { 1144 /* Receiving HDMI signal 1145 * Set automode */ 1146 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); 1147 break; 1148 } 1149 1150 /* Receiving DVI-D signal 1151 * ADV7604 selects RGB limited range regardless of 1152 * input format (CE/IT) in automatic mode */ 1153 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { 1154 /* RGB limited range (16-235) */ 1155 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1156 } else { 1157 /* RGB full range (0-255) */ 1158 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1159 1160 if (is_digital_input(sd) && rgb_output) { 1161 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1162 } else { 1163 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1164 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1165 } 1166 } 1167 break; 1168 case V4L2_DV_RGB_RANGE_LIMITED: 1169 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1170 /* YCrCb limited range (16-235) */ 1171 io_write_clr_set(sd, 0x02, 0xf0, 0x20); 1172 break; 1173 } 1174 1175 if (y != HDMI_COLORSPACE_RGB) 1176 break; 1177 1178 /* RGB limited range (16-235) */ 1179 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1180 1181 break; 1182 case V4L2_DV_RGB_RANGE_FULL: 1183 if (state->selected_input == ADV7604_PAD_VGA_COMP) { 1184 /* YCrCb full range (0-255) */ 1185 io_write_clr_set(sd, 0x02, 0xf0, 0x60); 1186 break; 1187 } 1188 1189 if (y != HDMI_COLORSPACE_RGB) 1190 break; 1191 1192 /* RGB full range (0-255) */ 1193 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1194 1195 if (is_analog_input(sd) || hdmi_signal) 1196 break; 1197 1198 /* Adjust gain/offset for DVI-D signals only */ 1199 if (rgb_output) { 1200 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); 1201 } else { 1202 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1203 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); 1204 } 1205 break; 1206 } 1207 } 1208 1209 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl) 1210 { 1211 struct v4l2_subdev *sd = 1212 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1213 1214 struct adv76xx_state *state = to_state(sd); 1215 1216 switch (ctrl->id) { 1217 case V4L2_CID_BRIGHTNESS: 1218 cp_write(sd, 0x3c, ctrl->val); 1219 return 0; 1220 case V4L2_CID_CONTRAST: 1221 cp_write(sd, 0x3a, ctrl->val); 1222 return 0; 1223 case V4L2_CID_SATURATION: 1224 cp_write(sd, 0x3b, ctrl->val); 1225 return 0; 1226 case V4L2_CID_HUE: 1227 cp_write(sd, 0x3d, ctrl->val); 1228 return 0; 1229 case V4L2_CID_DV_RX_RGB_RANGE: 1230 state->rgb_quantization_range = ctrl->val; 1231 set_rgb_quantization_range(sd); 1232 return 0; 1233 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1234 if (!adv76xx_has_afe(state)) 1235 return -EINVAL; 1236 /* Set the analog sampling phase. This is needed to find the 1237 best sampling phase for analog video: an application or 1238 driver has to try a number of phases and analyze the picture 1239 quality before settling on the best performing phase. */ 1240 afe_write(sd, 0xc8, ctrl->val); 1241 return 0; 1242 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1243 /* Use the default blue color for free running mode, 1244 or supply your own. */ 1245 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); 1246 return 0; 1247 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 1248 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 1249 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 1250 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 1251 return 0; 1252 } 1253 return -EINVAL; 1254 } 1255 1256 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 1257 { 1258 struct v4l2_subdev *sd = 1259 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; 1260 1261 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { 1262 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; 1263 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) 1264 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; 1265 return 0; 1266 } 1267 return -EINVAL; 1268 } 1269 1270 /* ----------------------------------------------------------------------- */ 1271 1272 static inline bool no_power(struct v4l2_subdev *sd) 1273 { 1274 /* Entire chip or CP powered off */ 1275 return io_read(sd, 0x0c) & 0x24; 1276 } 1277 1278 static inline bool no_signal_tmds(struct v4l2_subdev *sd) 1279 { 1280 struct adv76xx_state *state = to_state(sd); 1281 1282 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 1283 } 1284 1285 static inline bool no_lock_tmds(struct v4l2_subdev *sd) 1286 { 1287 struct adv76xx_state *state = to_state(sd); 1288 const struct adv76xx_chip_info *info = state->info; 1289 1290 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 1291 } 1292 1293 static inline bool is_hdmi(struct v4l2_subdev *sd) 1294 { 1295 return hdmi_read(sd, 0x05) & 0x80; 1296 } 1297 1298 static inline bool no_lock_sspd(struct v4l2_subdev *sd) 1299 { 1300 struct adv76xx_state *state = to_state(sd); 1301 1302 /* 1303 * Chips without a AFE don't expose registers for the SSPD, so just assume 1304 * that we have a lock. 1305 */ 1306 if (adv76xx_has_afe(state)) 1307 return false; 1308 1309 /* TODO channel 2 */ 1310 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 1311 } 1312 1313 static inline bool no_lock_stdi(struct v4l2_subdev *sd) 1314 { 1315 /* TODO channel 2 */ 1316 return !(cp_read(sd, 0xb1) & 0x80); 1317 } 1318 1319 static inline bool no_signal(struct v4l2_subdev *sd) 1320 { 1321 bool ret; 1322 1323 ret = no_power(sd); 1324 1325 ret |= no_lock_stdi(sd); 1326 ret |= no_lock_sspd(sd); 1327 1328 if (is_digital_input(sd)) { 1329 ret |= no_lock_tmds(sd); 1330 ret |= no_signal_tmds(sd); 1331 } 1332 1333 return ret; 1334 } 1335 1336 static inline bool no_lock_cp(struct v4l2_subdev *sd) 1337 { 1338 struct adv76xx_state *state = to_state(sd); 1339 1340 if (!adv76xx_has_afe(state)) 1341 return false; 1342 1343 /* CP has detected a non standard number of lines on the incoming 1344 video compared to what it is configured to receive by s_dv_timings */ 1345 return io_read(sd, 0x12) & 0x01; 1346 } 1347 1348 static inline bool in_free_run(struct v4l2_subdev *sd) 1349 { 1350 return cp_read(sd, 0xff) & 0x10; 1351 } 1352 1353 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) 1354 { 1355 *status = 0; 1356 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 1357 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1358 if (!in_free_run(sd) && no_lock_cp(sd)) 1359 *status |= is_digital_input(sd) ? 1360 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 1361 1362 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1363 1364 return 0; 1365 } 1366 1367 /* ----------------------------------------------------------------------- */ 1368 1369 struct stdi_readback { 1370 u16 bl, lcf, lcvs; 1371 u8 hs_pol, vs_pol; 1372 bool interlaced; 1373 }; 1374 1375 static int stdi2dv_timings(struct v4l2_subdev *sd, 1376 struct stdi_readback *stdi, 1377 struct v4l2_dv_timings *timings) 1378 { 1379 struct adv76xx_state *state = to_state(sd); 1380 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; 1381 u32 pix_clk; 1382 int i; 1383 1384 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 1385 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt; 1386 1387 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i], 1388 adv76xx_get_dv_timings_cap(sd, -1), 1389 adv76xx_check_dv_timings, NULL)) 1390 continue; 1391 if (vtotal(bt) != stdi->lcf + 1) 1392 continue; 1393 if (bt->vsync != stdi->lcvs) 1394 continue; 1395 1396 pix_clk = hfreq * htotal(bt); 1397 1398 if ((pix_clk < bt->pixelclock + 1000000) && 1399 (pix_clk > bt->pixelclock - 1000000)) { 1400 *timings = v4l2_dv_timings_presets[i]; 1401 return 0; 1402 } 1403 } 1404 1405 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, 1406 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1407 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1408 false, timings)) 1409 return 0; 1410 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1411 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1412 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1413 false, state->aspect_ratio, timings)) 1414 return 0; 1415 1416 v4l2_dbg(2, debug, sd, 1417 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1418 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1419 stdi->hs_pol, stdi->vs_pol); 1420 return -1; 1421 } 1422 1423 1424 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1425 { 1426 struct adv76xx_state *state = to_state(sd); 1427 const struct adv76xx_chip_info *info = state->info; 1428 u8 polarity; 1429 1430 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1431 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 1432 return -1; 1433 } 1434 1435 /* read STDI */ 1436 stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1437 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 1438 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1439 stdi->interlaced = io_read(sd, 0x12) & 0x10; 1440 1441 if (adv76xx_has_afe(state)) { 1442 /* read SSPD */ 1443 polarity = cp_read(sd, 0xb5); 1444 if ((polarity & 0x03) == 0x01) { 1445 stdi->hs_pol = polarity & 0x10 1446 ? (polarity & 0x08 ? '+' : '-') : 'x'; 1447 stdi->vs_pol = polarity & 0x40 1448 ? (polarity & 0x20 ? '+' : '-') : 'x'; 1449 } else { 1450 stdi->hs_pol = 'x'; 1451 stdi->vs_pol = 'x'; 1452 } 1453 } else { 1454 polarity = hdmi_read(sd, 0x05); 1455 stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1456 stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1457 } 1458 1459 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1460 v4l2_dbg(2, debug, sd, 1461 "%s: signal lost during readout of STDI/SSPD\n", __func__); 1462 return -1; 1463 } 1464 1465 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1466 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1467 memset(stdi, 0, sizeof(struct stdi_readback)); 1468 return -1; 1469 } 1470 1471 v4l2_dbg(2, debug, sd, 1472 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1473 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1474 stdi->hs_pol, stdi->vs_pol, 1475 stdi->interlaced ? "interlaced" : "progressive"); 1476 1477 return 0; 1478 } 1479 1480 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, 1481 struct v4l2_enum_dv_timings *timings) 1482 { 1483 struct adv76xx_state *state = to_state(sd); 1484 1485 if (timings->pad >= state->source_pad) 1486 return -EINVAL; 1487 1488 return v4l2_enum_dv_timings_cap(timings, 1489 adv76xx_get_dv_timings_cap(sd, timings->pad), 1490 adv76xx_check_dv_timings, NULL); 1491 } 1492 1493 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, 1494 struct v4l2_dv_timings_cap *cap) 1495 { 1496 struct adv76xx_state *state = to_state(sd); 1497 unsigned int pad = cap->pad; 1498 1499 if (cap->pad >= state->source_pad) 1500 return -EINVAL; 1501 1502 *cap = *adv76xx_get_dv_timings_cap(sd, pad); 1503 cap->pad = pad; 1504 1505 return 0; 1506 } 1507 1508 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1509 if the format is listed in adv76xx_timings[] */ 1510 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1511 struct v4l2_dv_timings *timings) 1512 { 1513 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1), 1514 is_digital_input(sd) ? 250000 : 1000000, 1515 adv76xx_check_dv_timings, NULL); 1516 } 1517 1518 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1519 { 1520 int a, b; 1521 1522 a = hdmi_read(sd, 0x06); 1523 b = hdmi_read(sd, 0x3b); 1524 if (a < 0 || b < 0) 1525 return 0; 1526 1527 return a * 1000000 + ((b & 0x30) >> 4) * 250000; 1528 } 1529 1530 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1531 { 1532 int a, b; 1533 1534 a = hdmi_read(sd, 0x51); 1535 b = hdmi_read(sd, 0x52); 1536 if (a < 0 || b < 0) 1537 return 0; 1538 1539 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1540 } 1541 1542 static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1543 { 1544 struct adv76xx_state *state = to_state(sd); 1545 const struct adv76xx_chip_info *info = state->info; 1546 unsigned int freq, bits_per_channel, pixelrepetition; 1547 1548 freq = info->read_hdmi_pixelclock(sd); 1549 if (is_hdmi(sd)) { 1550 /* adjust for deep color mode and pixel repetition */ 1551 bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1552 pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1; 1553 1554 freq = freq * 8 / bits_per_channel / pixelrepetition; 1555 } 1556 1557 return freq; 1558 } 1559 1560 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, 1561 struct v4l2_dv_timings *timings) 1562 { 1563 struct adv76xx_state *state = to_state(sd); 1564 const struct adv76xx_chip_info *info = state->info; 1565 struct v4l2_bt_timings *bt = &timings->bt; 1566 struct stdi_readback stdi; 1567 1568 if (!timings) 1569 return -EINVAL; 1570 1571 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1572 1573 if (no_signal(sd)) { 1574 state->restart_stdi_once = true; 1575 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1576 return -ENOLINK; 1577 } 1578 1579 /* read STDI */ 1580 if (read_stdi(sd, &stdi)) { 1581 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 1582 return -ENOLINK; 1583 } 1584 bt->interlaced = stdi.interlaced ? 1585 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1586 1587 if (is_digital_input(sd)) { 1588 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1589 u8 vic = 0; 1590 u32 w, h; 1591 1592 w = hdmi_read16(sd, 0x07, info->linewidth_mask); 1593 h = hdmi_read16(sd, 0x09, info->field0_height_mask); 1594 1595 if (hdmi_signal && (io_read(sd, 0x60) & 1)) 1596 vic = infoframe_read(sd, 0x04); 1597 1598 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) && 1599 bt->width == w && bt->height == h) 1600 goto found; 1601 1602 timings->type = V4L2_DV_BT_656_1120; 1603 1604 bt->width = w; 1605 bt->height = h; 1606 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd); 1607 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); 1608 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); 1609 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); 1610 bt->vfrontporch = hdmi_read16(sd, 0x2a, 1611 info->field0_vfrontporch_mask) / 2; 1612 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; 1613 bt->vbackporch = hdmi_read16(sd, 0x32, 1614 info->field0_vbackporch_mask) / 2; 1615 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1616 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1617 if (bt->interlaced == V4L2_DV_INTERLACED) { 1618 bt->height += hdmi_read16(sd, 0x0b, 1619 info->field1_height_mask); 1620 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 1621 info->field1_vfrontporch_mask) / 2; 1622 bt->il_vsync = hdmi_read16(sd, 0x30, 1623 info->field1_vsync_mask) / 2; 1624 bt->il_vbackporch = hdmi_read16(sd, 0x34, 1625 info->field1_vbackporch_mask) / 2; 1626 } 1627 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1628 } else { 1629 /* find format 1630 * Since LCVS values are inaccurate [REF_03, p. 275-276], 1631 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1632 */ 1633 if (!stdi2dv_timings(sd, &stdi, timings)) 1634 goto found; 1635 stdi.lcvs += 1; 1636 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1637 if (!stdi2dv_timings(sd, &stdi, timings)) 1638 goto found; 1639 stdi.lcvs -= 2; 1640 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1641 if (stdi2dv_timings(sd, &stdi, timings)) { 1642 /* 1643 * The STDI block may measure wrong values, especially 1644 * for lcvs and lcf. If the driver can not find any 1645 * valid timing, the STDI block is restarted to measure 1646 * the video timings again. The function will return an 1647 * error, but the restart of STDI will generate a new 1648 * STDI interrupt and the format detection process will 1649 * restart. 1650 */ 1651 if (state->restart_stdi_once) { 1652 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1653 /* TODO restart STDI for Sync Channel 2 */ 1654 /* enter one-shot mode */ 1655 cp_write_clr_set(sd, 0x86, 0x06, 0x00); 1656 /* trigger STDI restart */ 1657 cp_write_clr_set(sd, 0x86, 0x06, 0x04); 1658 /* reset to continuous mode */ 1659 cp_write_clr_set(sd, 0x86, 0x06, 0x02); 1660 state->restart_stdi_once = false; 1661 return -ENOLINK; 1662 } 1663 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1664 return -ERANGE; 1665 } 1666 state->restart_stdi_once = true; 1667 } 1668 found: 1669 1670 if (no_signal(sd)) { 1671 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 1672 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1673 return -ENOLINK; 1674 } 1675 1676 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 1677 (is_digital_input(sd) && bt->pixelclock > 225000000)) { 1678 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 1679 __func__, (u32)bt->pixelclock); 1680 return -ERANGE; 1681 } 1682 1683 if (debug > 1) 1684 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", 1685 timings, true); 1686 1687 return 0; 1688 } 1689 1690 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, 1691 struct v4l2_dv_timings *timings) 1692 { 1693 struct adv76xx_state *state = to_state(sd); 1694 struct v4l2_bt_timings *bt; 1695 int err; 1696 1697 if (!timings) 1698 return -EINVAL; 1699 1700 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { 1701 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1702 return 0; 1703 } 1704 1705 bt = &timings->bt; 1706 1707 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1), 1708 adv76xx_check_dv_timings, NULL)) 1709 return -ERANGE; 1710 1711 adv76xx_fill_optional_dv_timings_fields(sd, timings); 1712 1713 state->timings = *timings; 1714 1715 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); 1716 1717 /* Use prim_mode and vid_std when available */ 1718 err = configure_predefined_video_timings(sd, timings); 1719 if (err) { 1720 /* custom settings when the video format 1721 does not have prim_mode/vid_std */ 1722 configure_custom_video_timings(sd, bt); 1723 } 1724 1725 set_rgb_quantization_range(sd); 1726 1727 if (debug > 1) 1728 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", 1729 timings, true); 1730 return 0; 1731 } 1732 1733 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, 1734 struct v4l2_dv_timings *timings) 1735 { 1736 struct adv76xx_state *state = to_state(sd); 1737 1738 *timings = state->timings; 1739 return 0; 1740 } 1741 1742 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1743 { 1744 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1745 } 1746 1747 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1748 { 1749 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1750 } 1751 1752 static void enable_input(struct v4l2_subdev *sd) 1753 { 1754 struct adv76xx_state *state = to_state(sd); 1755 1756 if (is_analog_input(sd)) { 1757 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1758 } else if (is_digital_input(sd)) { 1759 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); 1760 state->info->set_termination(sd, true); 1761 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1762 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ 1763 } else { 1764 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1765 __func__, state->selected_input); 1766 } 1767 } 1768 1769 static void disable_input(struct v4l2_subdev *sd) 1770 { 1771 struct adv76xx_state *state = to_state(sd); 1772 1773 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 1774 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 1775 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1776 state->info->set_termination(sd, false); 1777 } 1778 1779 static void select_input(struct v4l2_subdev *sd) 1780 { 1781 struct adv76xx_state *state = to_state(sd); 1782 const struct adv76xx_chip_info *info = state->info; 1783 1784 if (is_analog_input(sd)) { 1785 adv76xx_write_reg_seq(sd, info->recommended_settings[0]); 1786 1787 afe_write(sd, 0x00, 0x08); /* power up ADC */ 1788 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 1789 afe_write(sd, 0xc8, 0x00); /* phase control */ 1790 } else if (is_digital_input(sd)) { 1791 hdmi_write(sd, 0x00, state->selected_input & 0x03); 1792 1793 adv76xx_write_reg_seq(sd, info->recommended_settings[1]); 1794 1795 if (adv76xx_has_afe(state)) { 1796 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1797 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 1798 afe_write(sd, 0xc8, 0x40); /* phase control */ 1799 } 1800 1801 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1802 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1803 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 1804 } else { 1805 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1806 __func__, state->selected_input); 1807 } 1808 1809 /* Enable video adjustment (contrast, saturation, brightness and hue) */ 1810 cp_write_clr_set(sd, 0x3e, 0x80, 0x80); 1811 } 1812 1813 static int adv76xx_s_routing(struct v4l2_subdev *sd, 1814 u32 input, u32 output, u32 config) 1815 { 1816 struct adv76xx_state *state = to_state(sd); 1817 1818 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1819 __func__, input, state->selected_input); 1820 1821 if (input == state->selected_input) 1822 return 0; 1823 1824 if (input > state->info->max_port) 1825 return -EINVAL; 1826 1827 state->selected_input = input; 1828 1829 disable_input(sd); 1830 select_input(sd); 1831 enable_input(sd); 1832 1833 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 1834 1835 return 0; 1836 } 1837 1838 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, 1839 struct v4l2_subdev_state *sd_state, 1840 struct v4l2_subdev_mbus_code_enum *code) 1841 { 1842 struct adv76xx_state *state = to_state(sd); 1843 1844 if (code->index >= state->info->nformats) 1845 return -EINVAL; 1846 1847 code->code = state->info->formats[code->index].code; 1848 1849 return 0; 1850 } 1851 1852 static void adv76xx_fill_format(struct adv76xx_state *state, 1853 struct v4l2_mbus_framefmt *format) 1854 { 1855 memset(format, 0, sizeof(*format)); 1856 1857 format->width = state->timings.bt.width; 1858 format->height = state->timings.bt.height; 1859 format->field = V4L2_FIELD_NONE; 1860 format->colorspace = V4L2_COLORSPACE_SRGB; 1861 1862 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) 1863 format->colorspace = (state->timings.bt.height <= 576) ? 1864 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1865 } 1866 1867 /* 1868 * Compute the op_ch_sel value required to obtain on the bus the component order 1869 * corresponding to the selected format taking into account bus reordering 1870 * applied by the board at the output of the device. 1871 * 1872 * The following table gives the op_ch_value from the format component order 1873 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1874 * adv76xx_bus_order value in row). 1875 * 1876 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1877 * ----------+------------------------------------------------- 1878 * RGB (NOP) | GBR GRB BGR RGB BRG RBG 1879 * GRB (1-2) | BGR RGB GBR GRB RBG BRG 1880 * RBG (2-3) | GRB GBR BRG RBG BGR RGB 1881 * BGR (1-3) | RBG BRG RGB BGR GRB GBR 1882 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1883 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1884 */ 1885 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state) 1886 { 1887 #define _SEL(a,b,c,d,e,f) { \ 1888 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \ 1889 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f } 1890 #define _BUS(x) [ADV7604_BUS_ORDER_##x] 1891 1892 static const unsigned int op_ch_sel[6][6] = { 1893 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG), 1894 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), 1895 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), 1896 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), 1897 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR), 1898 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB), 1899 }; 1900 1901 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1902 } 1903 1904 static void adv76xx_setup_format(struct adv76xx_state *state) 1905 { 1906 struct v4l2_subdev *sd = &state->sd; 1907 1908 io_write_clr_set(sd, 0x02, 0x02, 1909 state->format->rgb_out ? ADV76XX_RGB_OUT : 0); 1910 io_write(sd, 0x03, state->format->op_format_sel | 1911 state->pdata.op_format_mode_sel); 1912 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); 1913 io_write_clr_set(sd, 0x05, 0x01, 1914 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); 1915 set_rgb_quantization_range(sd); 1916 } 1917 1918 static int adv76xx_get_format(struct v4l2_subdev *sd, 1919 struct v4l2_subdev_state *sd_state, 1920 struct v4l2_subdev_format *format) 1921 { 1922 struct adv76xx_state *state = to_state(sd); 1923 1924 if (format->pad != state->source_pad) 1925 return -EINVAL; 1926 1927 adv76xx_fill_format(state, &format->format); 1928 1929 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1930 struct v4l2_mbus_framefmt *fmt; 1931 1932 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); 1933 format->format.code = fmt->code; 1934 } else { 1935 format->format.code = state->format->code; 1936 } 1937 1938 return 0; 1939 } 1940 1941 static int adv76xx_get_selection(struct v4l2_subdev *sd, 1942 struct v4l2_subdev_state *sd_state, 1943 struct v4l2_subdev_selection *sel) 1944 { 1945 struct adv76xx_state *state = to_state(sd); 1946 1947 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1948 return -EINVAL; 1949 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */ 1950 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) 1951 return -EINVAL; 1952 1953 sel->r.left = 0; 1954 sel->r.top = 0; 1955 sel->r.width = state->timings.bt.width; 1956 sel->r.height = state->timings.bt.height; 1957 1958 return 0; 1959 } 1960 1961 static int adv76xx_set_format(struct v4l2_subdev *sd, 1962 struct v4l2_subdev_state *sd_state, 1963 struct v4l2_subdev_format *format) 1964 { 1965 struct adv76xx_state *state = to_state(sd); 1966 const struct adv76xx_format_info *info; 1967 1968 if (format->pad != state->source_pad) 1969 return -EINVAL; 1970 1971 info = adv76xx_format_info(state, format->format.code); 1972 if (!info) 1973 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1974 1975 adv76xx_fill_format(state, &format->format); 1976 format->format.code = info->code; 1977 1978 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1979 struct v4l2_mbus_framefmt *fmt; 1980 1981 fmt = v4l2_subdev_state_get_format(sd_state, format->pad); 1982 fmt->code = format->format.code; 1983 } else { 1984 state->format = info; 1985 adv76xx_setup_format(state); 1986 } 1987 1988 return 0; 1989 } 1990 1991 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 1992 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) 1993 { 1994 struct adv76xx_state *state = to_state(sd); 1995 1996 if ((cec_read(sd, 0x11) & 0x01) == 0) { 1997 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); 1998 return; 1999 } 2000 2001 if (tx_raw_status & 0x02) { 2002 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n", 2003 __func__); 2004 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, 2005 1, 0, 0, 0); 2006 return; 2007 } 2008 if (tx_raw_status & 0x04) { 2009 u8 status; 2010 u8 nack_cnt; 2011 u8 low_drive_cnt; 2012 2013 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); 2014 /* 2015 * We set this status bit since this hardware performs 2016 * retransmissions. 2017 */ 2018 status = CEC_TX_STATUS_MAX_RETRIES; 2019 nack_cnt = cec_read(sd, 0x14) & 0xf; 2020 if (nack_cnt) 2021 status |= CEC_TX_STATUS_NACK; 2022 low_drive_cnt = cec_read(sd, 0x14) >> 4; 2023 if (low_drive_cnt) 2024 status |= CEC_TX_STATUS_LOW_DRIVE; 2025 cec_transmit_done(state->cec_adap, status, 2026 0, nack_cnt, low_drive_cnt, 0); 2027 return; 2028 } 2029 if (tx_raw_status & 0x01) { 2030 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); 2031 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); 2032 return; 2033 } 2034 } 2035 2036 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled) 2037 { 2038 struct adv76xx_state *state = to_state(sd); 2039 const struct adv76xx_chip_info *info = state->info; 2040 u8 cec_irq; 2041 2042 /* cec controller */ 2043 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f; 2044 if (!cec_irq) 2045 return; 2046 2047 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); 2048 adv76xx_cec_tx_raw_status(sd, cec_irq); 2049 if (cec_irq & 0x08) { 2050 struct cec_msg msg; 2051 2052 msg.len = cec_read(sd, 0x25) & 0x1f; 2053 if (msg.len > CEC_MAX_MSG_SIZE) 2054 msg.len = CEC_MAX_MSG_SIZE; 2055 2056 if (msg.len) { 2057 u8 i; 2058 2059 for (i = 0; i < msg.len; i++) 2060 msg.msg[i] = cec_read(sd, i + 0x15); 2061 cec_write(sd, info->cec_rx_enable, 2062 info->cec_rx_enable_mask); /* re-enable rx */ 2063 cec_received_msg(state->cec_adap, &msg); 2064 } 2065 } 2066 2067 if (info->cec_irq_swap) { 2068 /* 2069 * Note: the bit order is swapped between 0x4d and 0x4e 2070 * on adv7604 2071 */ 2072 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) | 2073 ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3); 2074 } 2075 io_write(sd, info->cec_irq_status + 1, cec_irq); 2076 2077 if (handled) 2078 *handled = true; 2079 } 2080 2081 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable) 2082 { 2083 struct adv76xx_state *state = cec_get_drvdata(adap); 2084 const struct adv76xx_chip_info *info = state->info; 2085 struct v4l2_subdev *sd = &state->sd; 2086 2087 if (!state->cec_enabled_adap && enable) { 2088 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ 2089 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ 2090 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ 2091 /* enabled irqs: */ 2092 /* tx: ready */ 2093 /* tx: arbitration lost */ 2094 /* tx: retry timeout */ 2095 /* rx: ready */ 2096 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f); 2097 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask); 2098 } else if (state->cec_enabled_adap && !enable) { 2099 /* disable cec interrupts */ 2100 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00); 2101 /* disable address mask 1-3 */ 2102 cec_write_clr_set(sd, 0x27, 0x70, 0x00); 2103 /* power down cec section */ 2104 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); 2105 state->cec_valid_addrs = 0; 2106 } 2107 state->cec_enabled_adap = enable; 2108 adv76xx_s_detect_tx_5v_ctrl(sd); 2109 return 0; 2110 } 2111 2112 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) 2113 { 2114 struct adv76xx_state *state = cec_get_drvdata(adap); 2115 struct v4l2_subdev *sd = &state->sd; 2116 unsigned int i, free_idx = ADV76XX_MAX_ADDRS; 2117 2118 if (!state->cec_enabled_adap) 2119 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; 2120 2121 if (addr == CEC_LOG_ADDR_INVALID) { 2122 cec_write_clr_set(sd, 0x27, 0x70, 0); 2123 state->cec_valid_addrs = 0; 2124 return 0; 2125 } 2126 2127 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) { 2128 bool is_valid = state->cec_valid_addrs & (1 << i); 2129 2130 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid) 2131 free_idx = i; 2132 if (is_valid && state->cec_addr[i] == addr) 2133 return 0; 2134 } 2135 if (i == ADV76XX_MAX_ADDRS) { 2136 i = free_idx; 2137 if (i == ADV76XX_MAX_ADDRS) 2138 return -ENXIO; 2139 } 2140 state->cec_addr[i] = addr; 2141 state->cec_valid_addrs |= 1 << i; 2142 2143 switch (i) { 2144 case 0: 2145 /* enable address mask 0 */ 2146 cec_write_clr_set(sd, 0x27, 0x10, 0x10); 2147 /* set address for mask 0 */ 2148 cec_write_clr_set(sd, 0x28, 0x0f, addr); 2149 break; 2150 case 1: 2151 /* enable address mask 1 */ 2152 cec_write_clr_set(sd, 0x27, 0x20, 0x20); 2153 /* set address for mask 1 */ 2154 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); 2155 break; 2156 case 2: 2157 /* enable address mask 2 */ 2158 cec_write_clr_set(sd, 0x27, 0x40, 0x40); 2159 /* set address for mask 1 */ 2160 cec_write_clr_set(sd, 0x29, 0x0f, addr); 2161 break; 2162 } 2163 return 0; 2164 } 2165 2166 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2167 u32 signal_free_time, struct cec_msg *msg) 2168 { 2169 struct adv76xx_state *state = cec_get_drvdata(adap); 2170 struct v4l2_subdev *sd = &state->sd; 2171 u8 len = msg->len; 2172 unsigned int i; 2173 2174 /* 2175 * The number of retries is the number of attempts - 1, but retry 2176 * at least once. It's not clear if a value of 0 is allowed, so 2177 * let's do at least one retry. 2178 */ 2179 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); 2180 2181 if (len > 16) { 2182 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); 2183 return -EINVAL; 2184 } 2185 2186 /* write data */ 2187 for (i = 0; i < len; i++) 2188 cec_write(sd, i, msg->msg[i]); 2189 2190 /* set length (data + header) */ 2191 cec_write(sd, 0x10, len); 2192 /* start transmit, enable tx */ 2193 cec_write(sd, 0x11, 0x01); 2194 return 0; 2195 } 2196 2197 static const struct cec_adap_ops adv76xx_cec_adap_ops = { 2198 .adap_enable = adv76xx_cec_adap_enable, 2199 .adap_log_addr = adv76xx_cec_adap_log_addr, 2200 .adap_transmit = adv76xx_cec_adap_transmit, 2201 }; 2202 #endif 2203 2204 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 2205 { 2206 struct adv76xx_state *state = to_state(sd); 2207 const struct adv76xx_chip_info *info = state->info; 2208 const u8 irq_reg_0x43 = io_read(sd, 0x43); 2209 const u8 irq_reg_0x6b = io_read(sd, 0x6b); 2210 const u8 irq_reg_0x70 = io_read(sd, 0x70); 2211 u8 fmt_change_digital; 2212 u8 fmt_change; 2213 u8 tx_5v; 2214 2215 if (irq_reg_0x43) 2216 io_write(sd, 0x44, irq_reg_0x43); 2217 if (irq_reg_0x70) 2218 io_write(sd, 0x71, irq_reg_0x70); 2219 if (irq_reg_0x6b) 2220 io_write(sd, 0x6c, irq_reg_0x6b); 2221 2222 v4l2_dbg(2, debug, sd, "%s: ", __func__); 2223 2224 /* format change */ 2225 fmt_change = irq_reg_0x43 & 0x98; 2226 fmt_change_digital = is_digital_input(sd) 2227 ? irq_reg_0x6b & info->fmt_change_digital_mask 2228 : 0; 2229 2230 if (fmt_change || fmt_change_digital) { 2231 v4l2_dbg(1, debug, sd, 2232 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 2233 __func__, fmt_change, fmt_change_digital); 2234 2235 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); 2236 2237 if (handled) 2238 *handled = true; 2239 } 2240 /* HDMI/DVI mode */ 2241 if (irq_reg_0x6b & 0x01) { 2242 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 2243 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 2244 set_rgb_quantization_range(sd); 2245 if (handled) 2246 *handled = true; 2247 } 2248 2249 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 2250 /* cec */ 2251 adv76xx_cec_isr(sd, handled); 2252 #endif 2253 2254 /* tx 5v detect */ 2255 tx_5v = irq_reg_0x70 & info->cable_det_mask; 2256 if (tx_5v) { 2257 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 2258 adv76xx_s_detect_tx_5v_ctrl(sd); 2259 if (handled) 2260 *handled = true; 2261 } 2262 return 0; 2263 } 2264 2265 static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id) 2266 { 2267 struct adv76xx_state *state = dev_id; 2268 bool handled = false; 2269 2270 adv76xx_isr(&state->sd, 0, &handled); 2271 2272 return handled ? IRQ_HANDLED : IRQ_NONE; 2273 } 2274 2275 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2276 { 2277 struct adv76xx_state *state = to_state(sd); 2278 u8 *data = NULL; 2279 2280 memset(edid->reserved, 0, sizeof(edid->reserved)); 2281 2282 switch (edid->pad) { 2283 case ADV76XX_PAD_HDMI_PORT_A: 2284 case ADV7604_PAD_HDMI_PORT_B: 2285 case ADV7604_PAD_HDMI_PORT_C: 2286 case ADV7604_PAD_HDMI_PORT_D: 2287 if (state->edid.present & (1 << edid->pad)) 2288 data = state->edid.edid; 2289 break; 2290 default: 2291 return -EINVAL; 2292 } 2293 2294 if (edid->start_block == 0 && edid->blocks == 0) { 2295 edid->blocks = data ? state->edid.blocks : 0; 2296 return 0; 2297 } 2298 2299 if (!data) 2300 return -ENODATA; 2301 2302 if (edid->start_block >= state->edid.blocks) 2303 return -EINVAL; 2304 2305 if (edid->start_block + edid->blocks > state->edid.blocks) 2306 edid->blocks = state->edid.blocks - edid->start_block; 2307 2308 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); 2309 2310 return 0; 2311 } 2312 2313 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 2314 { 2315 struct adv76xx_state *state = to_state(sd); 2316 const struct adv76xx_chip_info *info = state->info; 2317 unsigned int spa_loc; 2318 u16 pa, parent_pa; 2319 int err; 2320 int i; 2321 2322 memset(edid->reserved, 0, sizeof(edid->reserved)); 2323 2324 if (edid->pad > ADV7604_PAD_HDMI_PORT_D) 2325 return -EINVAL; 2326 if (edid->start_block != 0) 2327 return -EINVAL; 2328 if (edid->blocks == 0) { 2329 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2330 state->edid.present &= ~(1 << edid->pad); 2331 adv76xx_set_hpd(state, state->edid.present); 2332 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2333 2334 /* Fall back to a 16:9 aspect ratio */ 2335 state->aspect_ratio.numerator = 16; 2336 state->aspect_ratio.denominator = 9; 2337 2338 if (!state->edid.present) { 2339 state->edid.blocks = 0; 2340 cec_phys_addr_invalidate(state->cec_adap); 2341 } 2342 2343 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 2344 __func__, edid->pad, state->edid.present); 2345 return 0; 2346 } 2347 if (edid->blocks > ADV76XX_MAX_EDID_BLOCKS) { 2348 edid->blocks = ADV76XX_MAX_EDID_BLOCKS; 2349 return -E2BIG; 2350 } 2351 2352 pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc); 2353 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL); 2354 if (err) 2355 return err; 2356 2357 if (!spa_loc) { 2358 /* 2359 * There is no SPA, so just set spa_loc to 128 and pa to whatever 2360 * data is there. 2361 */ 2362 spa_loc = 128; 2363 pa = (edid->edid[spa_loc] << 8) | edid->edid[spa_loc + 1]; 2364 } 2365 2366 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 2367 __func__, edid->pad, state->edid.present); 2368 2369 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2370 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2371 adv76xx_set_hpd(state, 0); 2372 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 2373 2374 switch (edid->pad) { 2375 case ADV76XX_PAD_HDMI_PORT_A: 2376 state->spa_port_a[0] = pa >> 8; 2377 state->spa_port_a[1] = pa & 0xff; 2378 break; 2379 case ADV7604_PAD_HDMI_PORT_B: 2380 rep_write(sd, info->edid_spa_port_b_reg, pa >> 8); 2381 rep_write(sd, info->edid_spa_port_b_reg + 1, pa & 0xff); 2382 break; 2383 case ADV7604_PAD_HDMI_PORT_C: 2384 rep_write(sd, info->edid_spa_port_b_reg + 2, pa >> 8); 2385 rep_write(sd, info->edid_spa_port_b_reg + 3, pa & 0xff); 2386 break; 2387 case ADV7604_PAD_HDMI_PORT_D: 2388 rep_write(sd, info->edid_spa_port_b_reg + 4, pa >> 8); 2389 rep_write(sd, info->edid_spa_port_b_reg + 5, pa & 0xff); 2390 break; 2391 default: 2392 return -EINVAL; 2393 } 2394 2395 if (info->edid_spa_loc_reg) { 2396 u8 mask = info->edid_spa_loc_msb_mask; 2397 2398 rep_write(sd, info->edid_spa_loc_reg, spa_loc & 0xff); 2399 rep_write_clr_set(sd, info->edid_spa_loc_reg + 1, 2400 mask, (spa_loc & 0x100) ? mask : 0); 2401 } 2402 2403 edid->edid[spa_loc] = state->spa_port_a[0]; 2404 edid->edid[spa_loc + 1] = state->spa_port_a[1]; 2405 2406 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 2407 state->edid.blocks = edid->blocks; 2408 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 2409 edid->edid[0x16]); 2410 state->edid.present |= 1 << edid->pad; 2411 2412 rep_write_clr_set(sd, info->edid_segment_reg, 2413 info->edid_segment_mask, 0); 2414 err = edid_write_block(sd, 128 * min(edid->blocks, 2U), state->edid.edid); 2415 if (err < 0) { 2416 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 2417 return err; 2418 } 2419 if (edid->blocks > 2) { 2420 rep_write_clr_set(sd, info->edid_segment_reg, 2421 info->edid_segment_mask, 2422 info->edid_segment_mask); 2423 err = edid_write_block(sd, 128 * (edid->blocks - 2), 2424 state->edid.edid + 256); 2425 if (err < 0) { 2426 v4l2_err(sd, "error %d writing edid pad %d\n", 2427 err, edid->pad); 2428 return err; 2429 } 2430 } 2431 2432 /* adv76xx calculates the checksums and enables I2C access to internal 2433 EDID RAM from DDC port. */ 2434 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2435 2436 for (i = 0; i < 1000; i++) { 2437 if (rep_read(sd, info->edid_status_reg) & state->edid.present) 2438 break; 2439 mdelay(1); 2440 } 2441 if (i == 1000) { 2442 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 2443 return -EIO; 2444 } 2445 cec_s_phys_addr(state->cec_adap, parent_pa, false); 2446 2447 /* enable hotplug after 100 ms */ 2448 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); 2449 return 0; 2450 } 2451 2452 /*********** avi info frame CEA-861-E **************/ 2453 2454 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = { 2455 { "AVI", 0x01, 0xe0, 0x00 }, 2456 { "Audio", 0x02, 0xe3, 0x1c }, 2457 { "SDP", 0x04, 0xe6, 0x2a }, 2458 { "Vendor", 0x10, 0xec, 0x54 } 2459 }; 2460 2461 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, 2462 union hdmi_infoframe *frame) 2463 { 2464 uint8_t buffer[32]; 2465 u8 len; 2466 int i; 2467 2468 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { 2469 v4l2_info(sd, "%s infoframe not received\n", 2470 adv76xx_cri[index].desc); 2471 return -ENOENT; 2472 } 2473 2474 for (i = 0; i < 3; i++) 2475 buffer[i] = infoframe_read(sd, 2476 adv76xx_cri[index].head_addr + i); 2477 2478 len = buffer[2] + 1; 2479 2480 if (len + 3 > sizeof(buffer)) { 2481 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, 2482 adv76xx_cri[index].desc, len); 2483 return -ENOENT; 2484 } 2485 2486 for (i = 0; i < len; i++) 2487 buffer[i + 3] = infoframe_read(sd, 2488 adv76xx_cri[index].payload_addr + i); 2489 2490 if (hdmi_infoframe_unpack(frame, buffer, len + 3) < 0) { 2491 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, 2492 adv76xx_cri[index].desc); 2493 return -ENOENT; 2494 } 2495 return 0; 2496 } 2497 2498 static void adv76xx_log_infoframes(struct v4l2_subdev *sd) 2499 { 2500 int i; 2501 2502 if (!is_hdmi(sd)) { 2503 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); 2504 return; 2505 } 2506 2507 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) { 2508 union hdmi_infoframe frame; 2509 struct i2c_client *client = v4l2_get_subdevdata(sd); 2510 2511 if (!adv76xx_read_infoframe(sd, i, &frame)) 2512 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); 2513 } 2514 } 2515 2516 static int adv76xx_log_status(struct v4l2_subdev *sd) 2517 { 2518 struct adv76xx_state *state = to_state(sd); 2519 const struct adv76xx_chip_info *info = state->info; 2520 struct v4l2_dv_timings timings; 2521 struct stdi_readback stdi; 2522 u8 reg_io_0x02 = io_read(sd, 0x02); 2523 u8 edid_enabled; 2524 u8 cable_det; 2525 2526 static const char * const csc_coeff_sel_rb[16] = { 2527 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2528 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2529 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2530 "reserved", "reserved", "reserved", "reserved", "manual" 2531 }; 2532 static const char * const input_color_space_txt[16] = { 2533 "RGB limited range (16-235)", "RGB full range (0-255)", 2534 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2535 "xvYCC Bt.601", "xvYCC Bt.709", 2536 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2537 "invalid", "invalid", "invalid", "invalid", "invalid", 2538 "invalid", "invalid", "automatic" 2539 }; 2540 static const char * const hdmi_color_space_txt[16] = { 2541 "RGB limited range (16-235)", "RGB full range (0-255)", 2542 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2543 "xvYCC Bt.601", "xvYCC Bt.709", 2544 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2545 "sYCC", "opYCC 601", "opRGB", "invalid", "invalid", 2546 "invalid", "invalid", "invalid" 2547 }; 2548 static const char * const rgb_quantization_range_txt[] = { 2549 "Automatic", 2550 "RGB limited range (16-235)", 2551 "RGB full range (0-255)", 2552 }; 2553 static const char * const deep_color_mode_txt[4] = { 2554 "8-bits per channel", 2555 "10-bits per channel", 2556 "12-bits per channel", 2557 "16-bits per channel (not supported)" 2558 }; 2559 2560 v4l2_info(sd, "-----Chip status-----\n"); 2561 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2562 edid_enabled = rep_read(sd, info->edid_status_reg); 2563 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 2564 ((edid_enabled & 0x01) ? "Yes" : "No"), 2565 ((edid_enabled & 0x02) ? "Yes" : "No"), 2566 ((edid_enabled & 0x04) ? "Yes" : "No"), 2567 ((edid_enabled & 0x08) ? "Yes" : "No")); 2568 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? 2569 "enabled" : "disabled"); 2570 if (state->cec_enabled_adap) { 2571 int i; 2572 2573 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) { 2574 bool is_valid = state->cec_valid_addrs & (1 << i); 2575 2576 if (is_valid) 2577 v4l2_info(sd, "CEC Logical Address: 0x%x\n", 2578 state->cec_addr[i]); 2579 } 2580 } 2581 2582 v4l2_info(sd, "-----Signal status-----\n"); 2583 cable_det = info->read_cable_det(sd); 2584 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2585 ((cable_det & 0x01) ? "Yes" : "No"), 2586 ((cable_det & 0x02) ? "Yes" : "No"), 2587 ((cable_det & 0x04) ? "Yes" : "No"), 2588 ((cable_det & 0x08) ? "Yes" : "No")); 2589 v4l2_info(sd, "TMDS signal detected: %s\n", 2590 no_signal_tmds(sd) ? "false" : "true"); 2591 v4l2_info(sd, "TMDS signal locked: %s\n", 2592 no_lock_tmds(sd) ? "false" : "true"); 2593 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 2594 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 2595 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 2596 v4l2_info(sd, "CP free run: %s\n", 2597 (in_free_run(sd)) ? "on" : "off"); 2598 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2599 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2600 (io_read(sd, 0x01) & 0x70) >> 4); 2601 2602 v4l2_info(sd, "-----Video Timings-----\n"); 2603 if (read_stdi(sd, &stdi)) 2604 v4l2_info(sd, "STDI: not locked\n"); 2605 else 2606 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 2607 stdi.lcf, stdi.bl, stdi.lcvs, 2608 stdi.interlaced ? "interlaced" : "progressive", 2609 stdi.hs_pol, stdi.vs_pol); 2610 if (adv76xx_query_dv_timings(sd, &timings)) 2611 v4l2_info(sd, "No video detected\n"); 2612 else 2613 v4l2_print_dv_timings(sd->name, "Detected format: ", 2614 &timings, true); 2615 v4l2_print_dv_timings(sd->name, "Configured format: ", 2616 &state->timings, true); 2617 2618 if (no_signal(sd)) 2619 return 0; 2620 2621 v4l2_info(sd, "-----Color space-----\n"); 2622 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2623 rgb_quantization_range_txt[state->rgb_quantization_range]); 2624 v4l2_info(sd, "Input color space: %s\n", 2625 input_color_space_txt[reg_io_0x02 >> 4]); 2626 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", 2627 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2628 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ? 2629 "(16-235)" : "(0-255)", 2630 (reg_io_0x02 & 0x08) ? "enabled" : "disabled"); 2631 v4l2_info(sd, "Color space conversion: %s\n", 2632 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); 2633 2634 if (!is_digital_input(sd)) 2635 return 0; 2636 2637 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2638 v4l2_info(sd, "Digital video port selected: %c\n", 2639 (hdmi_read(sd, 0x00) & 0x03) + 'A'); 2640 v4l2_info(sd, "HDCP encrypted content: %s\n", 2641 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2642 v4l2_info(sd, "HDCP keys read: %s%s\n", 2643 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2644 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2645 if (is_hdmi(sd)) { 2646 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2647 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2648 bool audio_mute = io_read(sd, 0x65) & 0x40; 2649 2650 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2651 audio_pll_locked ? "locked" : "not locked", 2652 audio_sample_packet_detect ? "detected" : "not detected", 2653 audio_mute ? "muted" : "enabled"); 2654 if (audio_pll_locked && audio_sample_packet_detect) { 2655 v4l2_info(sd, "Audio format: %s\n", 2656 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 2657 } 2658 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2659 (hdmi_read(sd, 0x5c) << 8) + 2660 (hdmi_read(sd, 0x5d) & 0xf0)); 2661 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2662 (hdmi_read(sd, 0x5e) << 8) + 2663 hdmi_read(sd, 0x5f)); 2664 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2665 2666 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 2667 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); 2668 2669 adv76xx_log_infoframes(sd); 2670 } 2671 2672 return 0; 2673 } 2674 2675 static int adv76xx_subscribe_event(struct v4l2_subdev *sd, 2676 struct v4l2_fh *fh, 2677 struct v4l2_event_subscription *sub) 2678 { 2679 switch (sub->type) { 2680 case V4L2_EVENT_SOURCE_CHANGE: 2681 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 2682 case V4L2_EVENT_CTRL: 2683 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 2684 default: 2685 return -EINVAL; 2686 } 2687 } 2688 2689 static int adv76xx_registered(struct v4l2_subdev *sd) 2690 { 2691 struct adv76xx_state *state = to_state(sd); 2692 struct i2c_client *client = v4l2_get_subdevdata(sd); 2693 int err; 2694 2695 err = cec_register_adapter(state->cec_adap, &client->dev); 2696 if (err) 2697 cec_delete_adapter(state->cec_adap); 2698 return err; 2699 } 2700 2701 static void adv76xx_unregistered(struct v4l2_subdev *sd) 2702 { 2703 struct adv76xx_state *state = to_state(sd); 2704 2705 cec_unregister_adapter(state->cec_adap); 2706 } 2707 2708 /* ----------------------------------------------------------------------- */ 2709 2710 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = { 2711 .s_ctrl = adv76xx_s_ctrl, 2712 .g_volatile_ctrl = adv76xx_g_volatile_ctrl, 2713 }; 2714 2715 static const struct v4l2_subdev_core_ops adv76xx_core_ops = { 2716 .log_status = adv76xx_log_status, 2717 .interrupt_service_routine = adv76xx_isr, 2718 .subscribe_event = adv76xx_subscribe_event, 2719 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 2720 #ifdef CONFIG_VIDEO_ADV_DEBUG 2721 .g_register = adv76xx_g_register, 2722 .s_register = adv76xx_s_register, 2723 #endif 2724 }; 2725 2726 static const struct v4l2_subdev_video_ops adv76xx_video_ops = { 2727 .s_routing = adv76xx_s_routing, 2728 .g_input_status = adv76xx_g_input_status, 2729 .s_dv_timings = adv76xx_s_dv_timings, 2730 .g_dv_timings = adv76xx_g_dv_timings, 2731 .query_dv_timings = adv76xx_query_dv_timings, 2732 }; 2733 2734 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = { 2735 .enum_mbus_code = adv76xx_enum_mbus_code, 2736 .get_selection = adv76xx_get_selection, 2737 .get_fmt = adv76xx_get_format, 2738 .set_fmt = adv76xx_set_format, 2739 .get_edid = adv76xx_get_edid, 2740 .set_edid = adv76xx_set_edid, 2741 .dv_timings_cap = adv76xx_dv_timings_cap, 2742 .enum_dv_timings = adv76xx_enum_dv_timings, 2743 }; 2744 2745 static const struct v4l2_subdev_ops adv76xx_ops = { 2746 .core = &adv76xx_core_ops, 2747 .video = &adv76xx_video_ops, 2748 .pad = &adv76xx_pad_ops, 2749 }; 2750 2751 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = { 2752 .registered = adv76xx_registered, 2753 .unregistered = adv76xx_unregistered, 2754 }; 2755 2756 /* -------------------------- custom ctrls ---------------------------------- */ 2757 2758 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2759 .ops = &adv76xx_ctrl_ops, 2760 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2761 .name = "Analog Sampling Phase", 2762 .type = V4L2_CTRL_TYPE_INTEGER, 2763 .min = 0, 2764 .max = 0x1f, 2765 .step = 1, 2766 .def = 0, 2767 }; 2768 2769 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = { 2770 .ops = &adv76xx_ctrl_ops, 2771 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2772 .name = "Free Running Color, Manual", 2773 .type = V4L2_CTRL_TYPE_BOOLEAN, 2774 .min = false, 2775 .max = true, 2776 .step = 1, 2777 .def = false, 2778 }; 2779 2780 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = { 2781 .ops = &adv76xx_ctrl_ops, 2782 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2783 .name = "Free Running Color", 2784 .type = V4L2_CTRL_TYPE_INTEGER, 2785 .min = 0x0, 2786 .max = 0xffffff, 2787 .step = 0x1, 2788 .def = 0x0, 2789 }; 2790 2791 /* ----------------------------------------------------------------------- */ 2792 2793 struct adv76xx_register_map { 2794 const char *name; 2795 u8 default_addr; 2796 }; 2797 2798 static const struct adv76xx_register_map adv76xx_default_addresses[] = { 2799 [ADV76XX_PAGE_IO] = { "main", 0x4c }, 2800 [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 }, 2801 [ADV76XX_PAGE_CEC] = { "cec", 0x40 }, 2802 [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e }, 2803 [ADV7604_PAGE_ESDP] = { "esdp", 0x38 }, 2804 [ADV7604_PAGE_DPP] = { "dpp", 0x3c }, 2805 [ADV76XX_PAGE_AFE] = { "afe", 0x26 }, 2806 [ADV76XX_PAGE_REP] = { "rep", 0x32 }, 2807 [ADV76XX_PAGE_EDID] = { "edid", 0x36 }, 2808 [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 }, 2809 [ADV76XX_PAGE_TEST] = { "test", 0x30 }, 2810 [ADV76XX_PAGE_CP] = { "cp", 0x22 }, 2811 [ADV7604_PAGE_VDP] = { "vdp", 0x24 }, 2812 }; 2813 2814 static int adv76xx_core_init(struct v4l2_subdev *sd) 2815 { 2816 struct adv76xx_state *state = to_state(sd); 2817 const struct adv76xx_chip_info *info = state->info; 2818 struct adv76xx_platform_data *pdata = &state->pdata; 2819 2820 hdmi_write(sd, 0x48, 2821 (pdata->disable_pwrdnb ? 0x80 : 0) | 2822 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2823 2824 disable_input(sd); 2825 2826 if (pdata->default_input >= 0 && 2827 pdata->default_input < state->source_pad) { 2828 state->selected_input = pdata->default_input; 2829 select_input(sd); 2830 enable_input(sd); 2831 } 2832 2833 /* power */ 2834 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2835 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 2836 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 2837 2838 /* HPD */ 2839 if (info->type != ADV7604) { 2840 /* Set manual HPD values to 0 */ 2841 io_write_clr_set(sd, 0x20, 0xc0, 0); 2842 /* 2843 * Set HPA_DELAY to 200 ms and set automatic HPD control 2844 * to: internal EDID is active AND a cable is detected 2845 * AND the manual HPD control is set to 1. 2846 */ 2847 hdmi_write_clr_set(sd, 0x6c, 0xf6, 0x26); 2848 } 2849 2850 /* video format */ 2851 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3); 2852 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 2853 pdata->insert_av_codes << 2 | 2854 pdata->replicate_av_codes << 1); 2855 adv76xx_setup_format(state); 2856 2857 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 2858 2859 /* VS, HS polarities */ 2860 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | 2861 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); 2862 2863 /* Adjust drive strength */ 2864 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2865 pdata->dr_str_clk << 2 | 2866 pdata->dr_str_sync); 2867 2868 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 2869 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2870 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 2871 ADI recommended setting [REF_01, c. 2.3.3] */ 2872 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 2873 ADI recommended setting [REF_01, c. 2.3.3] */ 2874 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 2875 for digital formats */ 2876 2877 /* HDMI audio */ 2878 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 2879 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ 2880 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 2881 2882 /* TODO from platform data */ 2883 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2884 2885 if (adv76xx_has_afe(state)) { 2886 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2887 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2888 } 2889 2890 /* interrupts */ 2891 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 2892 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2893 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2894 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2895 info->setup_irqs(sd); 2896 2897 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2898 } 2899 2900 static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2901 { 2902 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2903 } 2904 2905 static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2906 { 2907 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2908 } 2909 2910 static void adv7612_setup_irqs(struct v4l2_subdev *sd) 2911 { 2912 io_write(sd, 0x41, 0xd0); /* disable INT2 */ 2913 } 2914 2915 static void adv76xx_unregister_clients(struct adv76xx_state *state) 2916 { 2917 unsigned int i; 2918 2919 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) 2920 i2c_unregister_device(state->i2c_clients[i]); 2921 } 2922 2923 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, 2924 unsigned int page) 2925 { 2926 struct i2c_client *client = v4l2_get_subdevdata(sd); 2927 struct adv76xx_state *state = to_state(sd); 2928 struct adv76xx_platform_data *pdata = &state->pdata; 2929 unsigned int io_reg = 0xf2 + page; 2930 struct i2c_client *new_client; 2931 2932 if (pdata && pdata->i2c_addresses[page]) 2933 new_client = i2c_new_dummy_device(client->adapter, 2934 pdata->i2c_addresses[page]); 2935 else 2936 new_client = i2c_new_ancillary_device(client, 2937 adv76xx_default_addresses[page].name, 2938 adv76xx_default_addresses[page].default_addr); 2939 2940 if (!IS_ERR(new_client)) 2941 io_write(sd, io_reg, new_client->addr << 1); 2942 2943 return new_client; 2944 } 2945 2946 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = { 2947 /* reset ADI recommended settings for HDMI: */ 2948 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2949 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2950 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2951 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2952 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2953 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2954 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2955 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2956 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2957 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2958 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2959 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2960 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2961 2962 /* set ADI recommended settings for digitizer */ 2963 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2964 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2965 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2966 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2967 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2968 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2969 2970 { ADV76XX_REG_SEQ_TERM, 0 }, 2971 }; 2972 2973 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = { 2974 /* set ADI recommended settings for HDMI: */ 2975 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2976 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2977 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2978 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2979 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2980 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2981 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2982 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2983 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2984 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2985 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2986 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2987 2988 /* reset ADI recommended settings for digitizer */ 2989 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2990 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2991 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2992 2993 { ADV76XX_REG_SEQ_TERM, 0 }, 2994 }; 2995 2996 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = { 2997 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 2998 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 2999 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 3000 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 3001 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 3002 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 3003 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 3004 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 3005 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 3006 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 3007 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 }, 3008 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e }, 3009 3010 { ADV76XX_REG_SEQ_TERM, 0 }, 3011 }; 3012 3013 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = { 3014 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 }, 3015 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 }, 3016 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 }, 3017 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f }, 3018 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 }, 3019 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda }, 3020 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 }, 3021 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 }, 3022 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 }, 3023 { ADV76XX_REG_SEQ_TERM, 0 }, 3024 }; 3025 3026 static const struct adv76xx_chip_info adv76xx_chip_info[] = { 3027 [ADV7604] = { 3028 .type = ADV7604, 3029 .has_afe = true, 3030 .max_port = ADV7604_PAD_VGA_COMP, 3031 .num_dv_ports = 4, 3032 .edid_enable_reg = 0x77, 3033 .edid_status_reg = 0x7d, 3034 .edid_segment_reg = 0x77, 3035 .edid_segment_mask = 0x10, 3036 .edid_spa_loc_reg = 0x76, 3037 .edid_spa_loc_msb_mask = 0x40, 3038 .edid_spa_port_b_reg = 0x70, 3039 .lcf_reg = 0xb3, 3040 .tdms_lock_mask = 0xe0, 3041 .cable_det_mask = 0x1e, 3042 .fmt_change_digital_mask = 0xc1, 3043 .cp_csc = 0xfc, 3044 .cec_irq_status = 0x4d, 3045 .cec_rx_enable = 0x26, 3046 .cec_rx_enable_mask = 0x01, 3047 .cec_irq_swap = true, 3048 .formats = adv7604_formats, 3049 .nformats = ARRAY_SIZE(adv7604_formats), 3050 .set_termination = adv7604_set_termination, 3051 .setup_irqs = adv7604_setup_irqs, 3052 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 3053 .read_cable_det = adv7604_read_cable_det, 3054 .recommended_settings = { 3055 [0] = adv7604_recommended_settings_afe, 3056 [1] = adv7604_recommended_settings_hdmi, 3057 }, 3058 .num_recommended_settings = { 3059 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 3060 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 3061 }, 3062 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 3063 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) | 3064 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 3065 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) | 3066 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) | 3067 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) | 3068 BIT(ADV7604_PAGE_VDP), 3069 .linewidth_mask = 0xfff, 3070 .field0_height_mask = 0xfff, 3071 .field1_height_mask = 0xfff, 3072 .hfrontporch_mask = 0x3ff, 3073 .hsync_mask = 0x3ff, 3074 .hbackporch_mask = 0x3ff, 3075 .field0_vfrontporch_mask = 0x1fff, 3076 .field0_vsync_mask = 0x1fff, 3077 .field0_vbackporch_mask = 0x1fff, 3078 .field1_vfrontporch_mask = 0x1fff, 3079 .field1_vsync_mask = 0x1fff, 3080 .field1_vbackporch_mask = 0x1fff, 3081 }, 3082 [ADV7611] = { 3083 .type = ADV7611, 3084 .has_afe = false, 3085 .max_port = ADV76XX_PAD_HDMI_PORT_A, 3086 .num_dv_ports = 1, 3087 .edid_enable_reg = 0x74, 3088 .edid_status_reg = 0x76, 3089 .edid_segment_reg = 0x7a, 3090 .edid_segment_mask = 0x01, 3091 .lcf_reg = 0xa3, 3092 .tdms_lock_mask = 0x43, 3093 .cable_det_mask = 0x01, 3094 .fmt_change_digital_mask = 0x03, 3095 .cp_csc = 0xf4, 3096 .cec_irq_status = 0x93, 3097 .cec_rx_enable = 0x2c, 3098 .cec_rx_enable_mask = 0x02, 3099 .formats = adv7611_formats, 3100 .nformats = ARRAY_SIZE(adv7611_formats), 3101 .set_termination = adv7611_set_termination, 3102 .setup_irqs = adv7611_setup_irqs, 3103 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 3104 .read_cable_det = adv7611_read_cable_det, 3105 .recommended_settings = { 3106 [1] = adv7611_recommended_settings_hdmi, 3107 }, 3108 .num_recommended_settings = { 3109 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 3110 }, 3111 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 3112 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 3113 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 3114 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 3115 .linewidth_mask = 0x1fff, 3116 .field0_height_mask = 0x1fff, 3117 .field1_height_mask = 0x1fff, 3118 .hfrontporch_mask = 0x1fff, 3119 .hsync_mask = 0x1fff, 3120 .hbackporch_mask = 0x1fff, 3121 .field0_vfrontporch_mask = 0x3fff, 3122 .field0_vsync_mask = 0x3fff, 3123 .field0_vbackporch_mask = 0x3fff, 3124 .field1_vfrontporch_mask = 0x3fff, 3125 .field1_vsync_mask = 0x3fff, 3126 .field1_vbackporch_mask = 0x3fff, 3127 }, 3128 [ADV7612] = { 3129 .type = ADV7612, 3130 .has_afe = false, 3131 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */ 3132 .num_dv_ports = 1, /* normally 2 */ 3133 .edid_enable_reg = 0x74, 3134 .edid_status_reg = 0x76, 3135 .edid_segment_reg = 0x7a, 3136 .edid_segment_mask = 0x01, 3137 .edid_spa_loc_reg = 0x70, 3138 .edid_spa_loc_msb_mask = 0x01, 3139 .edid_spa_port_b_reg = 0x52, 3140 .lcf_reg = 0xa3, 3141 .tdms_lock_mask = 0x43, 3142 .cable_det_mask = 0x01, 3143 .fmt_change_digital_mask = 0x03, 3144 .cp_csc = 0xf4, 3145 .cec_irq_status = 0x93, 3146 .cec_rx_enable = 0x2c, 3147 .cec_rx_enable_mask = 0x02, 3148 .formats = adv7612_formats, 3149 .nformats = ARRAY_SIZE(adv7612_formats), 3150 .set_termination = adv7611_set_termination, 3151 .setup_irqs = adv7612_setup_irqs, 3152 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 3153 .read_cable_det = adv7612_read_cable_det, 3154 .recommended_settings = { 3155 [1] = adv7612_recommended_settings_hdmi, 3156 }, 3157 .num_recommended_settings = { 3158 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi), 3159 }, 3160 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) | 3161 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) | 3162 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) | 3163 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP), 3164 .linewidth_mask = 0x1fff, 3165 .field0_height_mask = 0x1fff, 3166 .field1_height_mask = 0x1fff, 3167 .hfrontporch_mask = 0x1fff, 3168 .hsync_mask = 0x1fff, 3169 .hbackporch_mask = 0x1fff, 3170 .field0_vfrontporch_mask = 0x3fff, 3171 .field0_vsync_mask = 0x3fff, 3172 .field0_vbackporch_mask = 0x3fff, 3173 .field1_vfrontporch_mask = 0x3fff, 3174 .field1_vsync_mask = 0x3fff, 3175 .field1_vbackporch_mask = 0x3fff, 3176 }, 3177 }; 3178 3179 static const struct i2c_device_id adv76xx_i2c_id[] = { 3180 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] }, 3181 { "adv7610", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 3182 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] }, 3183 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] }, 3184 { } 3185 }; 3186 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id); 3187 3188 static const struct of_device_id adv76xx_of_id[] __maybe_unused = { 3189 { .compatible = "adi,adv7610", .data = &adv76xx_chip_info[ADV7611] }, 3190 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] }, 3191 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] }, 3192 { } 3193 }; 3194 MODULE_DEVICE_TABLE(of, adv76xx_of_id); 3195 3196 static int adv76xx_parse_dt(struct adv76xx_state *state) 3197 { 3198 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; 3199 struct device_node *endpoint; 3200 struct device_node *np; 3201 unsigned int flags; 3202 int ret; 3203 u32 v; 3204 3205 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; 3206 3207 /* Parse the endpoint. */ 3208 endpoint = of_graph_get_next_endpoint(np, NULL); 3209 if (!endpoint) 3210 return -EINVAL; 3211 3212 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg); 3213 of_node_put(endpoint); 3214 if (ret) 3215 return ret; 3216 3217 if (!of_property_read_u32(np, "default-input", &v)) 3218 state->pdata.default_input = v; 3219 else 3220 state->pdata.default_input = -1; 3221 3222 flags = bus_cfg.bus.parallel.flags; 3223 3224 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 3225 state->pdata.inv_hs_pol = 1; 3226 3227 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 3228 state->pdata.inv_vs_pol = 1; 3229 3230 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 3231 state->pdata.inv_llc_pol = 1; 3232 3233 if (bus_cfg.bus_type == V4L2_MBUS_BT656) 3234 state->pdata.insert_av_codes = 1; 3235 3236 /* Disable the interrupt for now as no DT-based board uses it. */ 3237 state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH; 3238 3239 /* Hardcode the remaining platform data fields. */ 3240 state->pdata.disable_pwrdnb = 0; 3241 state->pdata.disable_cable_det_rst = 0; 3242 state->pdata.blank_data = 1; 3243 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; 3244 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; 3245 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH; 3246 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH; 3247 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH; 3248 3249 return 0; 3250 } 3251 3252 static const struct regmap_config adv76xx_regmap_cnf[] = { 3253 { 3254 .name = "io", 3255 .reg_bits = 8, 3256 .val_bits = 8, 3257 3258 .max_register = 0xff, 3259 .cache_type = REGCACHE_NONE, 3260 }, 3261 { 3262 .name = "avlink", 3263 .reg_bits = 8, 3264 .val_bits = 8, 3265 3266 .max_register = 0xff, 3267 .cache_type = REGCACHE_NONE, 3268 }, 3269 { 3270 .name = "cec", 3271 .reg_bits = 8, 3272 .val_bits = 8, 3273 3274 .max_register = 0xff, 3275 .cache_type = REGCACHE_NONE, 3276 }, 3277 { 3278 .name = "infoframe", 3279 .reg_bits = 8, 3280 .val_bits = 8, 3281 3282 .max_register = 0xff, 3283 .cache_type = REGCACHE_NONE, 3284 }, 3285 { 3286 .name = "esdp", 3287 .reg_bits = 8, 3288 .val_bits = 8, 3289 3290 .max_register = 0xff, 3291 .cache_type = REGCACHE_NONE, 3292 }, 3293 { 3294 .name = "epp", 3295 .reg_bits = 8, 3296 .val_bits = 8, 3297 3298 .max_register = 0xff, 3299 .cache_type = REGCACHE_NONE, 3300 }, 3301 { 3302 .name = "afe", 3303 .reg_bits = 8, 3304 .val_bits = 8, 3305 3306 .max_register = 0xff, 3307 .cache_type = REGCACHE_NONE, 3308 }, 3309 { 3310 .name = "rep", 3311 .reg_bits = 8, 3312 .val_bits = 8, 3313 3314 .max_register = 0xff, 3315 .cache_type = REGCACHE_NONE, 3316 }, 3317 { 3318 .name = "edid", 3319 .reg_bits = 8, 3320 .val_bits = 8, 3321 3322 .max_register = 0xff, 3323 .cache_type = REGCACHE_NONE, 3324 }, 3325 3326 { 3327 .name = "hdmi", 3328 .reg_bits = 8, 3329 .val_bits = 8, 3330 3331 .max_register = 0xff, 3332 .cache_type = REGCACHE_NONE, 3333 }, 3334 { 3335 .name = "test", 3336 .reg_bits = 8, 3337 .val_bits = 8, 3338 3339 .max_register = 0xff, 3340 .cache_type = REGCACHE_NONE, 3341 }, 3342 { 3343 .name = "cp", 3344 .reg_bits = 8, 3345 .val_bits = 8, 3346 3347 .max_register = 0xff, 3348 .cache_type = REGCACHE_NONE, 3349 }, 3350 { 3351 .name = "vdp", 3352 .reg_bits = 8, 3353 .val_bits = 8, 3354 3355 .max_register = 0xff, 3356 .cache_type = REGCACHE_NONE, 3357 }, 3358 }; 3359 3360 static int configure_regmap(struct adv76xx_state *state, int region) 3361 { 3362 int err; 3363 3364 if (!state->i2c_clients[region]) 3365 return -ENODEV; 3366 3367 state->regmap[region] = 3368 devm_regmap_init_i2c(state->i2c_clients[region], 3369 &adv76xx_regmap_cnf[region]); 3370 3371 if (IS_ERR(state->regmap[region])) { 3372 err = PTR_ERR(state->regmap[region]); 3373 v4l_err(state->i2c_clients[region], 3374 "Error initializing regmap %d with error %d\n", 3375 region, err); 3376 return -EINVAL; 3377 } 3378 3379 return 0; 3380 } 3381 3382 static int configure_regmaps(struct adv76xx_state *state) 3383 { 3384 int i, err; 3385 3386 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) { 3387 err = configure_regmap(state, i); 3388 if (err && (err != -ENODEV)) 3389 return err; 3390 } 3391 return 0; 3392 } 3393 3394 static void adv76xx_reset(struct adv76xx_state *state) 3395 { 3396 if (state->reset_gpio) { 3397 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */ 3398 gpiod_set_value_cansleep(state->reset_gpio, 0); 3399 usleep_range(5000, 10000); 3400 gpiod_set_value_cansleep(state->reset_gpio, 1); 3401 /* It is recommended to wait 5 ms after the low pulse before */ 3402 /* an I2C write is performed to the ADV76XX. */ 3403 usleep_range(5000, 10000); 3404 } 3405 } 3406 3407 static int adv76xx_probe(struct i2c_client *client) 3408 { 3409 const struct i2c_device_id *id = i2c_client_get_device_id(client); 3410 static const struct v4l2_dv_timings cea640x480 = 3411 V4L2_DV_BT_CEA_640X480P59_94; 3412 struct adv76xx_state *state; 3413 struct v4l2_ctrl_handler *hdl; 3414 struct v4l2_ctrl *ctrl; 3415 struct v4l2_subdev *sd; 3416 unsigned int i; 3417 unsigned int val, val2; 3418 int err; 3419 3420 /* Check if the adapter supports the needed features */ 3421 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 3422 return -EIO; 3423 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", 3424 client->addr << 1); 3425 3426 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 3427 if (!state) 3428 return -ENOMEM; 3429 3430 state->i2c_clients[ADV76XX_PAGE_IO] = client; 3431 3432 /* initialize variables */ 3433 state->restart_stdi_once = true; 3434 state->selected_input = ~0; 3435 3436 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 3437 const struct of_device_id *oid; 3438 3439 oid = of_match_node(adv76xx_of_id, client->dev.of_node); 3440 state->info = oid->data; 3441 3442 err = adv76xx_parse_dt(state); 3443 if (err < 0) { 3444 v4l_err(client, "DT parsing error\n"); 3445 return err; 3446 } 3447 } else if (client->dev.platform_data) { 3448 struct adv76xx_platform_data *pdata = client->dev.platform_data; 3449 3450 state->info = (const struct adv76xx_chip_info *)id->driver_data; 3451 state->pdata = *pdata; 3452 } else { 3453 v4l_err(client, "No platform data!\n"); 3454 return -ENODEV; 3455 } 3456 3457 /* Request GPIOs. */ 3458 for (i = 0; i < state->info->num_dv_ports; ++i) { 3459 state->hpd_gpio[i] = 3460 devm_gpiod_get_index_optional(&client->dev, "hpd", i, 3461 GPIOD_OUT_LOW); 3462 if (IS_ERR(state->hpd_gpio[i])) 3463 return PTR_ERR(state->hpd_gpio[i]); 3464 3465 if (state->hpd_gpio[i]) 3466 v4l_info(client, "Handling HPD %u GPIO\n", i); 3467 } 3468 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 3469 GPIOD_OUT_HIGH); 3470 if (IS_ERR(state->reset_gpio)) 3471 return PTR_ERR(state->reset_gpio); 3472 3473 adv76xx_reset(state); 3474 3475 state->timings = cea640x480; 3476 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 3477 3478 sd = &state->sd; 3479 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); 3480 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 3481 id->name, i2c_adapter_id(client->adapter), 3482 client->addr); 3483 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 3484 sd->internal_ops = &adv76xx_int_ops; 3485 3486 /* Configure IO Regmap region */ 3487 err = configure_regmap(state, ADV76XX_PAGE_IO); 3488 3489 if (err) { 3490 v4l2_err(sd, "Error configuring IO regmap region\n"); 3491 return -ENODEV; 3492 } 3493 3494 /* 3495 * Verify that the chip is present. On ADV7604 the RD_INFO register only 3496 * identifies the revision, while on ADV7611 it identifies the model as 3497 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 3498 */ 3499 switch (state->info->type) { 3500 case ADV7604: 3501 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); 3502 if (err) { 3503 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3504 return -ENODEV; 3505 } 3506 if (val != 0x68) { 3507 v4l2_err(sd, "not an ADV7604 on address 0x%x\n", 3508 client->addr << 1); 3509 return -ENODEV; 3510 } 3511 break; 3512 case ADV7611: 3513 case ADV7612: 3514 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3515 0xea, 3516 &val); 3517 if (err) { 3518 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3519 return -ENODEV; 3520 } 3521 val2 = val << 8; 3522 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 3523 0xeb, 3524 &val); 3525 if (err) { 3526 v4l2_err(sd, "Error %d reading IO Regmap\n", err); 3527 return -ENODEV; 3528 } 3529 val |= val2; 3530 if ((state->info->type == ADV7611 && val != 0x2051) || 3531 (state->info->type == ADV7612 && val != 0x2041)) { 3532 v4l2_err(sd, "not an %s on address 0x%x\n", 3533 state->info->type == ADV7611 ? "ADV7610/11" : "ADV7612", 3534 client->addr << 1); 3535 return -ENODEV; 3536 } 3537 break; 3538 } 3539 3540 /* control handlers */ 3541 hdl = &state->hdl; 3542 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8); 3543 3544 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3545 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 3546 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3547 V4L2_CID_CONTRAST, 0, 255, 1, 128); 3548 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3549 V4L2_CID_SATURATION, 0, 255, 1, 128); 3550 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops, 3551 V4L2_CID_HUE, 0, 255, 1, 0); 3552 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3553 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC, 3554 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC); 3555 if (ctrl) 3556 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 3557 3558 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 3559 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3560 (1 << state->info->num_dv_ports) - 1, 0, 0); 3561 state->rgb_quantization_range_ctrl = 3562 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops, 3563 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 3564 0, V4L2_DV_RGB_RANGE_AUTO); 3565 3566 /* custom controls */ 3567 if (adv76xx_has_afe(state)) 3568 state->analog_sampling_phase_ctrl = 3569 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 3570 state->free_run_color_manual_ctrl = 3571 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL); 3572 state->free_run_color_ctrl = 3573 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL); 3574 3575 sd->ctrl_handler = hdl; 3576 if (hdl->error) { 3577 err = hdl->error; 3578 goto err_hdl; 3579 } 3580 if (adv76xx_s_detect_tx_5v_ctrl(sd)) { 3581 err = -ENODEV; 3582 goto err_hdl; 3583 } 3584 3585 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { 3586 struct i2c_client *dummy_client; 3587 3588 if (!(BIT(i) & state->info->page_mask)) 3589 continue; 3590 3591 dummy_client = adv76xx_dummy_client(sd, i); 3592 if (IS_ERR(dummy_client)) { 3593 err = PTR_ERR(dummy_client); 3594 v4l2_err(sd, "failed to create i2c client %u\n", i); 3595 goto err_i2c; 3596 } 3597 3598 state->i2c_clients[i] = dummy_client; 3599 } 3600 3601 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 3602 adv76xx_delayed_work_enable_hotplug); 3603 3604 state->source_pad = state->info->num_dv_ports 3605 + (state->info->has_afe ? 2 : 0); 3606 for (i = 0; i < state->source_pad; ++i) 3607 state->pads[i].flags = MEDIA_PAD_FL_SINK; 3608 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; 3609 sd->entity.function = MEDIA_ENT_F_DV_DECODER; 3610 3611 err = media_entity_pads_init(&sd->entity, state->source_pad + 1, 3612 state->pads); 3613 if (err) 3614 goto err_work_queues; 3615 3616 /* Configure regmaps */ 3617 err = configure_regmaps(state); 3618 if (err) 3619 goto err_entity; 3620 3621 err = adv76xx_core_init(sd); 3622 if (err) 3623 goto err_entity; 3624 3625 if (client->irq) { 3626 err = devm_request_threaded_irq(&client->dev, 3627 client->irq, 3628 NULL, adv76xx_irq_handler, 3629 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 3630 client->name, state); 3631 if (err) 3632 goto err_entity; 3633 } 3634 3635 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC) 3636 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops, 3637 state, dev_name(&client->dev), 3638 CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS); 3639 err = PTR_ERR_OR_ZERO(state->cec_adap); 3640 if (err) 3641 goto err_entity; 3642 #endif 3643 3644 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 3645 client->addr << 1, client->adapter->name); 3646 3647 err = v4l2_async_register_subdev(sd); 3648 if (err) 3649 goto err_entity; 3650 3651 return 0; 3652 3653 err_entity: 3654 media_entity_cleanup(&sd->entity); 3655 err_work_queues: 3656 cancel_delayed_work(&state->delayed_work_enable_hotplug); 3657 err_i2c: 3658 adv76xx_unregister_clients(state); 3659 err_hdl: 3660 v4l2_ctrl_handler_free(hdl); 3661 return err; 3662 } 3663 3664 /* ----------------------------------------------------------------------- */ 3665 3666 static void adv76xx_remove(struct i2c_client *client) 3667 { 3668 struct v4l2_subdev *sd = i2c_get_clientdata(client); 3669 struct adv76xx_state *state = to_state(sd); 3670 3671 /* disable interrupts */ 3672 io_write(sd, 0x40, 0); 3673 io_write(sd, 0x41, 0); 3674 io_write(sd, 0x46, 0); 3675 io_write(sd, 0x6e, 0); 3676 io_write(sd, 0x73, 0); 3677 3678 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 3679 v4l2_async_unregister_subdev(sd); 3680 media_entity_cleanup(&sd->entity); 3681 adv76xx_unregister_clients(to_state(sd)); 3682 v4l2_ctrl_handler_free(sd->ctrl_handler); 3683 } 3684 3685 /* ----------------------------------------------------------------------- */ 3686 3687 static struct i2c_driver adv76xx_driver = { 3688 .driver = { 3689 .name = "adv7604", 3690 .of_match_table = of_match_ptr(adv76xx_of_id), 3691 }, 3692 .probe = adv76xx_probe, 3693 .remove = adv76xx_remove, 3694 .id_table = adv76xx_i2c_id, 3695 }; 3696 3697 module_i2c_driver(adv76xx_driver); 3698