1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina 4 * 5 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> 6 */ 7 #include <linux/videodev2.h> 8 #include <linux/slab.h> 9 #include <linux/i2c.h> 10 #include <linux/log2.h> 11 #include <linux/gpio.h> 12 #include <linux/delay.h> 13 #include <linux/v4l2-mediabus.h> 14 #include <linux/module.h> 15 #include <linux/property.h> 16 17 #include <media/v4l2-async.h> 18 #include <media/v4l2-clk.h> 19 #include <media/v4l2-common.h> 20 #include <media/v4l2-ctrls.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-event.h> 23 #include <media/v4l2-fwnode.h> 24 25 /* 26 * MT9M111, MT9M112 and MT9M131: 27 * i2c address is 0x48 or 0x5d (depending on SADDR pin) 28 * The platform has to define struct i2c_board_info objects and link to them 29 * from struct soc_camera_host_desc 30 */ 31 32 /* 33 * Sensor core register addresses (0x000..0x0ff) 34 */ 35 #define MT9M111_CHIP_VERSION 0x000 36 #define MT9M111_ROW_START 0x001 37 #define MT9M111_COLUMN_START 0x002 38 #define MT9M111_WINDOW_HEIGHT 0x003 39 #define MT9M111_WINDOW_WIDTH 0x004 40 #define MT9M111_HORIZONTAL_BLANKING_B 0x005 41 #define MT9M111_VERTICAL_BLANKING_B 0x006 42 #define MT9M111_HORIZONTAL_BLANKING_A 0x007 43 #define MT9M111_VERTICAL_BLANKING_A 0x008 44 #define MT9M111_SHUTTER_WIDTH 0x009 45 #define MT9M111_ROW_SPEED 0x00a 46 #define MT9M111_EXTRA_DELAY 0x00b 47 #define MT9M111_SHUTTER_DELAY 0x00c 48 #define MT9M111_RESET 0x00d 49 #define MT9M111_READ_MODE_B 0x020 50 #define MT9M111_READ_MODE_A 0x021 51 #define MT9M111_FLASH_CONTROL 0x023 52 #define MT9M111_GREEN1_GAIN 0x02b 53 #define MT9M111_BLUE_GAIN 0x02c 54 #define MT9M111_RED_GAIN 0x02d 55 #define MT9M111_GREEN2_GAIN 0x02e 56 #define MT9M111_GLOBAL_GAIN 0x02f 57 #define MT9M111_CONTEXT_CONTROL 0x0c8 58 #define MT9M111_PAGE_MAP 0x0f0 59 #define MT9M111_BYTE_WISE_ADDR 0x0f1 60 61 #define MT9M111_RESET_SYNC_CHANGES (1 << 15) 62 #define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9) 63 #define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8) 64 #define MT9M111_RESET_RESET_SOC (1 << 5) 65 #define MT9M111_RESET_OUTPUT_DISABLE (1 << 4) 66 #define MT9M111_RESET_CHIP_ENABLE (1 << 3) 67 #define MT9M111_RESET_ANALOG_STANDBY (1 << 2) 68 #define MT9M111_RESET_RESTART_FRAME (1 << 1) 69 #define MT9M111_RESET_RESET_MODE (1 << 0) 70 71 #define MT9M111_RM_FULL_POWER_RD (0 << 10) 72 #define MT9M111_RM_LOW_POWER_RD (1 << 10) 73 #define MT9M111_RM_COL_SKIP_4X (1 << 5) 74 #define MT9M111_RM_ROW_SKIP_4X (1 << 4) 75 #define MT9M111_RM_COL_SKIP_2X (1 << 3) 76 #define MT9M111_RM_ROW_SKIP_2X (1 << 2) 77 #define MT9M111_RMB_MIRROR_COLS (1 << 1) 78 #define MT9M111_RMB_MIRROR_ROWS (1 << 0) 79 #define MT9M111_CTXT_CTRL_RESTART (1 << 15) 80 #define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12) 81 #define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10) 82 #define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9) 83 #define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8) 84 #define MT9M111_CTXT_CTRL_XENON_EN (1 << 7) 85 #define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3) 86 #define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2) 87 #define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1) 88 #define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0) 89 90 /* 91 * Colorpipe register addresses (0x100..0x1ff) 92 */ 93 #define MT9M111_OPER_MODE_CTRL 0x106 94 #define MT9M111_OUTPUT_FORMAT_CTRL 0x108 95 #define MT9M111_TPG_CTRL 0x148 96 #define MT9M111_REDUCER_XZOOM_B 0x1a0 97 #define MT9M111_REDUCER_XSIZE_B 0x1a1 98 #define MT9M111_REDUCER_YZOOM_B 0x1a3 99 #define MT9M111_REDUCER_YSIZE_B 0x1a4 100 #define MT9M111_REDUCER_XZOOM_A 0x1a6 101 #define MT9M111_REDUCER_XSIZE_A 0x1a7 102 #define MT9M111_REDUCER_YZOOM_A 0x1a9 103 #define MT9M111_REDUCER_YSIZE_A 0x1aa 104 #define MT9M111_EFFECTS_MODE 0x1e2 105 106 #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a 107 #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b 108 109 #define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14) 110 #define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1) 111 #define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9) 112 #define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8) 113 #define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14) 114 #define MT9M111_OUTFMT_BYPASS_IFP (1 << 10) 115 #define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9) 116 #define MT9M111_OUTFMT_RGB (1 << 8) 117 #define MT9M111_OUTFMT_RGB565 (0 << 6) 118 #define MT9M111_OUTFMT_RGB555 (1 << 6) 119 #define MT9M111_OUTFMT_RGB444x (2 << 6) 120 #define MT9M111_OUTFMT_RGBx444 (3 << 6) 121 #define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4) 122 #define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4) 123 #define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4) 124 #define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4) 125 #define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3) 126 #define MT9M111_OUTFMT_AVG_CHROMA (1 << 2) 127 #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1) 128 #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0) 129 #define MT9M111_TPG_SEL_MASK GENMASK(2, 0) 130 #define MT9M111_EFFECTS_MODE_MASK GENMASK(2, 0) 131 #define MT9M111_RM_PWR_MASK BIT(10) 132 #define MT9M111_RM_SKIP2_MASK GENMASK(3, 2) 133 134 /* 135 * Camera control register addresses (0x200..0x2ff not implemented) 136 */ 137 138 #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg) 139 #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val)) 140 #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) 141 #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val)) 142 #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ 143 (val), (mask)) 144 145 #define MT9M111_MIN_DARK_ROWS 8 146 #define MT9M111_MIN_DARK_COLS 26 147 #define MT9M111_MAX_HEIGHT 1024 148 #define MT9M111_MAX_WIDTH 1280 149 150 struct mt9m111_context { 151 u16 read_mode; 152 u16 blanking_h; 153 u16 blanking_v; 154 u16 reducer_xzoom; 155 u16 reducer_yzoom; 156 u16 reducer_xsize; 157 u16 reducer_ysize; 158 u16 output_fmt_ctrl2; 159 u16 control; 160 }; 161 162 static struct mt9m111_context context_a = { 163 .read_mode = MT9M111_READ_MODE_A, 164 .blanking_h = MT9M111_HORIZONTAL_BLANKING_A, 165 .blanking_v = MT9M111_VERTICAL_BLANKING_A, 166 .reducer_xzoom = MT9M111_REDUCER_XZOOM_A, 167 .reducer_yzoom = MT9M111_REDUCER_YZOOM_A, 168 .reducer_xsize = MT9M111_REDUCER_XSIZE_A, 169 .reducer_ysize = MT9M111_REDUCER_YSIZE_A, 170 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A, 171 .control = MT9M111_CTXT_CTRL_RESTART, 172 }; 173 174 static struct mt9m111_context context_b = { 175 .read_mode = MT9M111_READ_MODE_B, 176 .blanking_h = MT9M111_HORIZONTAL_BLANKING_B, 177 .blanking_v = MT9M111_VERTICAL_BLANKING_B, 178 .reducer_xzoom = MT9M111_REDUCER_XZOOM_B, 179 .reducer_yzoom = MT9M111_REDUCER_YZOOM_B, 180 .reducer_xsize = MT9M111_REDUCER_XSIZE_B, 181 .reducer_ysize = MT9M111_REDUCER_YSIZE_B, 182 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B, 183 .control = MT9M111_CTXT_CTRL_RESTART | 184 MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B | 185 MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B | 186 MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B | 187 MT9M111_CTXT_CTRL_HBLANK_SEL_B, 188 }; 189 190 /* MT9M111 has only one fixed colorspace per pixelcode */ 191 struct mt9m111_datafmt { 192 u32 code; 193 enum v4l2_colorspace colorspace; 194 }; 195 196 static const struct mt9m111_datafmt mt9m111_colour_fmts[] = { 197 {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB}, 198 {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_SRGB}, 199 {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB}, 200 {MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_SRGB}, 201 {MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, 202 {MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB}, 203 {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB}, 204 {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB}, 205 {MEDIA_BUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB}, 206 {MEDIA_BUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB}, 207 {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB}, 208 {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, 209 }; 210 211 enum mt9m111_mode_id { 212 MT9M111_MODE_SXGA_8FPS, 213 MT9M111_MODE_SXGA_15FPS, 214 MT9M111_MODE_QSXGA_30FPS, 215 MT9M111_NUM_MODES, 216 }; 217 218 struct mt9m111_mode_info { 219 unsigned int sensor_w; 220 unsigned int sensor_h; 221 unsigned int max_image_w; 222 unsigned int max_image_h; 223 unsigned int max_fps; 224 unsigned int reg_val; 225 unsigned int reg_mask; 226 }; 227 228 struct mt9m111 { 229 struct v4l2_subdev subdev; 230 struct v4l2_ctrl_handler hdl; 231 struct v4l2_ctrl *gain; 232 struct mt9m111_context *ctx; 233 struct v4l2_rect rect; /* cropping rectangle */ 234 struct v4l2_clk *clk; 235 unsigned int width; /* output */ 236 unsigned int height; /* sizes */ 237 struct v4l2_fract frame_interval; 238 const struct mt9m111_mode_info *current_mode; 239 struct mutex power_lock; /* lock to protect power_count */ 240 int power_count; 241 const struct mt9m111_datafmt *fmt; 242 int lastpage; /* PageMap cache value */ 243 bool is_streaming; 244 /* user point of view - 0: falling 1: rising edge */ 245 unsigned int pclk_sample:1; 246 #ifdef CONFIG_MEDIA_CONTROLLER 247 struct media_pad pad; 248 #endif 249 }; 250 251 static const struct mt9m111_mode_info mt9m111_mode_data[MT9M111_NUM_MODES] = { 252 [MT9M111_MODE_SXGA_8FPS] = { 253 .sensor_w = 1280, 254 .sensor_h = 1024, 255 .max_image_w = 1280, 256 .max_image_h = 1024, 257 .max_fps = 8, 258 .reg_val = MT9M111_RM_LOW_POWER_RD, 259 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 260 }, 261 [MT9M111_MODE_SXGA_15FPS] = { 262 .sensor_w = 1280, 263 .sensor_h = 1024, 264 .max_image_w = 1280, 265 .max_image_h = 1024, 266 .max_fps = 15, 267 .reg_val = MT9M111_RM_FULL_POWER_RD, 268 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 269 }, 270 [MT9M111_MODE_QSXGA_30FPS] = { 271 .sensor_w = 1280, 272 .sensor_h = 1024, 273 .max_image_w = 640, 274 .max_image_h = 512, 275 .max_fps = 30, 276 .reg_val = MT9M111_RM_LOW_POWER_RD | MT9M111_RM_COL_SKIP_2X | 277 MT9M111_RM_ROW_SKIP_2X, 278 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK, 279 }, 280 }; 281 282 /* Find a data format by a pixel code */ 283 static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111, 284 u32 code) 285 { 286 int i; 287 for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++) 288 if (mt9m111_colour_fmts[i].code == code) 289 return mt9m111_colour_fmts + i; 290 291 return mt9m111->fmt; 292 } 293 294 static struct mt9m111 *to_mt9m111(const struct i2c_client *client) 295 { 296 return container_of(i2c_get_clientdata(client), struct mt9m111, subdev); 297 } 298 299 static int reg_page_map_set(struct i2c_client *client, const u16 reg) 300 { 301 int ret; 302 u16 page; 303 struct mt9m111 *mt9m111 = to_mt9m111(client); 304 305 page = (reg >> 8); 306 if (page == mt9m111->lastpage) 307 return 0; 308 if (page > 2) 309 return -EINVAL; 310 311 ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page); 312 if (!ret) 313 mt9m111->lastpage = page; 314 return ret; 315 } 316 317 static int mt9m111_reg_read(struct i2c_client *client, const u16 reg) 318 { 319 int ret; 320 321 ret = reg_page_map_set(client, reg); 322 if (!ret) 323 ret = i2c_smbus_read_word_swapped(client, reg & 0xff); 324 325 dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret); 326 return ret; 327 } 328 329 static int mt9m111_reg_write(struct i2c_client *client, const u16 reg, 330 const u16 data) 331 { 332 int ret; 333 334 ret = reg_page_map_set(client, reg); 335 if (!ret) 336 ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data); 337 dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret); 338 return ret; 339 } 340 341 static int mt9m111_reg_set(struct i2c_client *client, const u16 reg, 342 const u16 data) 343 { 344 int ret; 345 346 ret = mt9m111_reg_read(client, reg); 347 if (ret >= 0) 348 ret = mt9m111_reg_write(client, reg, ret | data); 349 return ret; 350 } 351 352 static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg, 353 const u16 data) 354 { 355 int ret; 356 357 ret = mt9m111_reg_read(client, reg); 358 if (ret >= 0) 359 ret = mt9m111_reg_write(client, reg, ret & ~data); 360 return ret; 361 } 362 363 static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg, 364 const u16 data, const u16 mask) 365 { 366 int ret; 367 368 ret = mt9m111_reg_read(client, reg); 369 if (ret >= 0) 370 ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data); 371 return ret; 372 } 373 374 static int mt9m111_set_context(struct mt9m111 *mt9m111, 375 struct mt9m111_context *ctx) 376 { 377 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 378 return reg_write(CONTEXT_CONTROL, ctx->control); 379 } 380 381 static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111, 382 struct mt9m111_context *ctx, struct v4l2_rect *rect, 383 unsigned int width, unsigned int height) 384 { 385 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 386 int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width); 387 if (!ret) 388 ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height); 389 if (!ret) 390 ret = mt9m111_reg_write(client, ctx->reducer_xsize, width); 391 if (!ret) 392 ret = mt9m111_reg_write(client, ctx->reducer_ysize, height); 393 return ret; 394 } 395 396 static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect, 397 int width, int height, u32 code) 398 { 399 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 400 int ret; 401 402 ret = reg_write(COLUMN_START, rect->left); 403 if (!ret) 404 ret = reg_write(ROW_START, rect->top); 405 406 if (!ret) 407 ret = reg_write(WINDOW_WIDTH, rect->width); 408 if (!ret) 409 ret = reg_write(WINDOW_HEIGHT, rect->height); 410 411 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { 412 /* IFP in use, down-scaling possible */ 413 if (!ret) 414 ret = mt9m111_setup_rect_ctx(mt9m111, &context_b, 415 rect, width, height); 416 if (!ret) 417 ret = mt9m111_setup_rect_ctx(mt9m111, &context_a, 418 rect, width, height); 419 } 420 421 dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n", 422 __func__, code, rect->width, rect->height, rect->left, rect->top, 423 width, height, ret); 424 425 return ret; 426 } 427 428 static int mt9m111_enable(struct mt9m111 *mt9m111) 429 { 430 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 431 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE); 432 } 433 434 static int mt9m111_reset(struct mt9m111 *mt9m111) 435 { 436 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 437 int ret; 438 439 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); 440 if (!ret) 441 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); 442 if (!ret) 443 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE 444 | MT9M111_RESET_RESET_SOC); 445 446 return ret; 447 } 448 449 static int mt9m111_set_selection(struct v4l2_subdev *sd, 450 struct v4l2_subdev_pad_config *cfg, 451 struct v4l2_subdev_selection *sel) 452 { 453 struct i2c_client *client = v4l2_get_subdevdata(sd); 454 struct mt9m111 *mt9m111 = to_mt9m111(client); 455 struct v4l2_rect rect = sel->r; 456 int width, height; 457 int ret, align = 0; 458 459 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE || 460 sel->target != V4L2_SEL_TGT_CROP) 461 return -EINVAL; 462 463 if (mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 || 464 mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { 465 /* Bayer format - even size lengths */ 466 align = 1; 467 /* Let the user play with the starting pixel */ 468 } 469 470 /* FIXME: the datasheet doesn't specify minimum sizes */ 471 v4l_bound_align_image(&rect.width, 2, MT9M111_MAX_WIDTH, align, 472 &rect.height, 2, MT9M111_MAX_HEIGHT, align, 0); 473 rect.left = clamp(rect.left, MT9M111_MIN_DARK_COLS, 474 MT9M111_MIN_DARK_COLS + MT9M111_MAX_WIDTH - 475 (__s32)rect.width); 476 rect.top = clamp(rect.top, MT9M111_MIN_DARK_ROWS, 477 MT9M111_MIN_DARK_ROWS + MT9M111_MAX_HEIGHT - 478 (__s32)rect.height); 479 480 width = min(mt9m111->width, rect.width); 481 height = min(mt9m111->height, rect.height); 482 483 ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code); 484 if (!ret) { 485 mt9m111->rect = rect; 486 mt9m111->width = width; 487 mt9m111->height = height; 488 } 489 490 return ret; 491 } 492 493 static int mt9m111_get_selection(struct v4l2_subdev *sd, 494 struct v4l2_subdev_pad_config *cfg, 495 struct v4l2_subdev_selection *sel) 496 { 497 struct i2c_client *client = v4l2_get_subdevdata(sd); 498 struct mt9m111 *mt9m111 = to_mt9m111(client); 499 500 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 501 return -EINVAL; 502 503 switch (sel->target) { 504 case V4L2_SEL_TGT_CROP_BOUNDS: 505 sel->r.left = MT9M111_MIN_DARK_COLS; 506 sel->r.top = MT9M111_MIN_DARK_ROWS; 507 sel->r.width = MT9M111_MAX_WIDTH; 508 sel->r.height = MT9M111_MAX_HEIGHT; 509 return 0; 510 case V4L2_SEL_TGT_CROP: 511 sel->r = mt9m111->rect; 512 return 0; 513 default: 514 return -EINVAL; 515 } 516 } 517 518 static int mt9m111_get_fmt(struct v4l2_subdev *sd, 519 struct v4l2_subdev_pad_config *cfg, 520 struct v4l2_subdev_format *format) 521 { 522 struct v4l2_mbus_framefmt *mf = &format->format; 523 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 524 525 if (format->pad) 526 return -EINVAL; 527 528 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 529 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 530 mf = v4l2_subdev_get_try_format(sd, cfg, format->pad); 531 format->format = *mf; 532 return 0; 533 #else 534 return -ENOTTY; 535 #endif 536 } 537 538 mf->width = mt9m111->width; 539 mf->height = mt9m111->height; 540 mf->code = mt9m111->fmt->code; 541 mf->colorspace = mt9m111->fmt->colorspace; 542 mf->field = V4L2_FIELD_NONE; 543 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 544 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 545 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 546 547 return 0; 548 } 549 550 static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111, 551 u32 code) 552 { 553 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 554 u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | 555 MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB | 556 MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 | 557 MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 | 558 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | 559 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 560 int ret; 561 562 switch (code) { 563 case MEDIA_BUS_FMT_SBGGR8_1X8: 564 data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | 565 MT9M111_OUTFMT_RGB; 566 break; 567 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE: 568 data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB; 569 break; 570 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: 571 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 | 572 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; 573 break; 574 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE: 575 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555; 576 break; 577 case MEDIA_BUS_FMT_RGB565_2X8_LE: 578 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | 579 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; 580 break; 581 case MEDIA_BUS_FMT_RGB565_2X8_BE: 582 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565; 583 break; 584 case MEDIA_BUS_FMT_BGR565_2X8_BE: 585 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | 586 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 587 break; 588 case MEDIA_BUS_FMT_BGR565_2X8_LE: 589 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | 590 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | 591 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 592 break; 593 case MEDIA_BUS_FMT_UYVY8_2X8: 594 data_outfmt2 = 0; 595 break; 596 case MEDIA_BUS_FMT_VYUY8_2X8: 597 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 598 break; 599 case MEDIA_BUS_FMT_YUYV8_2X8: 600 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; 601 break; 602 case MEDIA_BUS_FMT_YVYU8_2X8: 603 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | 604 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; 605 break; 606 default: 607 dev_err(&client->dev, "Pixel format not handled: %x\n", code); 608 return -EINVAL; 609 } 610 611 /* receiver samples on falling edge, chip-hw default is rising */ 612 if (mt9m111->pclk_sample == 0) 613 mask_outfmt2 |= MT9M111_OUTFMT_INV_PIX_CLOCK; 614 615 ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2, 616 data_outfmt2, mask_outfmt2); 617 if (!ret) 618 ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2, 619 data_outfmt2, mask_outfmt2); 620 621 return ret; 622 } 623 624 static int mt9m111_set_fmt(struct v4l2_subdev *sd, 625 struct v4l2_subdev_pad_config *cfg, 626 struct v4l2_subdev_format *format) 627 { 628 struct v4l2_mbus_framefmt *mf = &format->format; 629 struct i2c_client *client = v4l2_get_subdevdata(sd); 630 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 631 const struct mt9m111_datafmt *fmt; 632 struct v4l2_rect *rect = &mt9m111->rect; 633 bool bayer; 634 int ret; 635 636 if (mt9m111->is_streaming) 637 return -EBUSY; 638 639 if (format->pad) 640 return -EINVAL; 641 642 fmt = mt9m111_find_datafmt(mt9m111, mf->code); 643 644 bayer = fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 || 645 fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE; 646 647 /* 648 * With Bayer format enforce even side lengths, but let the user play 649 * with the starting pixel 650 */ 651 if (bayer) { 652 rect->width = ALIGN(rect->width, 2); 653 rect->height = ALIGN(rect->height, 2); 654 } 655 656 if (fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { 657 /* IFP bypass mode, no scaling */ 658 mf->width = rect->width; 659 mf->height = rect->height; 660 } else { 661 /* No upscaling */ 662 if (mf->width > rect->width) 663 mf->width = rect->width; 664 if (mf->height > rect->height) 665 mf->height = rect->height; 666 } 667 668 dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__, 669 mf->width, mf->height, fmt->code); 670 671 mf->code = fmt->code; 672 mf->colorspace = fmt->colorspace; 673 mf->field = V4L2_FIELD_NONE; 674 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 675 mf->quantization = V4L2_QUANTIZATION_DEFAULT; 676 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT; 677 678 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 679 cfg->try_fmt = *mf; 680 return 0; 681 } 682 683 ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code); 684 if (!ret) 685 ret = mt9m111_set_pixfmt(mt9m111, mf->code); 686 if (!ret) { 687 mt9m111->width = mf->width; 688 mt9m111->height = mf->height; 689 mt9m111->fmt = fmt; 690 } 691 692 return ret; 693 } 694 695 static const struct mt9m111_mode_info * 696 mt9m111_find_mode(struct mt9m111 *mt9m111, unsigned int req_fps, 697 unsigned int width, unsigned int height) 698 { 699 const struct mt9m111_mode_info *mode; 700 struct v4l2_rect *sensor_rect = &mt9m111->rect; 701 unsigned int gap, gap_best = (unsigned int) -1; 702 int i, best_gap_idx = MT9M111_MODE_SXGA_15FPS; 703 bool skip_30fps = false; 704 705 /* 706 * The fps selection is based on the row, column skipping mechanism. 707 * So ensure that the sensor window is set to default else the fps 708 * aren't calculated correctly within the sensor hw. 709 */ 710 if (sensor_rect->width != MT9M111_MAX_WIDTH || 711 sensor_rect->height != MT9M111_MAX_HEIGHT) { 712 dev_info(mt9m111->subdev.dev, 713 "Framerate selection is not supported for cropped " 714 "images\n"); 715 return NULL; 716 } 717 718 /* 30fps only supported for images not exceeding 640x512 */ 719 if (width > MT9M111_MAX_WIDTH / 2 || height > MT9M111_MAX_HEIGHT / 2) { 720 dev_dbg(mt9m111->subdev.dev, 721 "Framerates > 15fps are supported only for images " 722 "not exceeding 640x512\n"); 723 skip_30fps = true; 724 } 725 726 /* find best matched fps */ 727 for (i = 0; i < MT9M111_NUM_MODES; i++) { 728 unsigned int fps = mt9m111_mode_data[i].max_fps; 729 730 if (fps == 30 && skip_30fps) 731 continue; 732 733 gap = abs(fps - req_fps); 734 if (gap < gap_best) { 735 best_gap_idx = i; 736 gap_best = gap; 737 } 738 } 739 740 /* 741 * Use context a/b default timing values instead of calculate blanking 742 * timing values. 743 */ 744 mode = &mt9m111_mode_data[best_gap_idx]; 745 mt9m111->ctx = (best_gap_idx == MT9M111_MODE_QSXGA_30FPS) ? &context_a : 746 &context_b; 747 return mode; 748 } 749 750 #ifdef CONFIG_VIDEO_ADV_DEBUG 751 static int mt9m111_g_register(struct v4l2_subdev *sd, 752 struct v4l2_dbg_register *reg) 753 { 754 struct i2c_client *client = v4l2_get_subdevdata(sd); 755 int val; 756 757 if (reg->reg > 0x2ff) 758 return -EINVAL; 759 760 val = mt9m111_reg_read(client, reg->reg); 761 reg->size = 2; 762 reg->val = (u64)val; 763 764 if (reg->val > 0xffff) 765 return -EIO; 766 767 return 0; 768 } 769 770 static int mt9m111_s_register(struct v4l2_subdev *sd, 771 const struct v4l2_dbg_register *reg) 772 { 773 struct i2c_client *client = v4l2_get_subdevdata(sd); 774 775 if (reg->reg > 0x2ff) 776 return -EINVAL; 777 778 if (mt9m111_reg_write(client, reg->reg, reg->val) < 0) 779 return -EIO; 780 781 return 0; 782 } 783 #endif 784 785 static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask) 786 { 787 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 788 int ret; 789 790 if (flip) 791 ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask); 792 else 793 ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask); 794 795 return ret; 796 } 797 798 static int mt9m111_get_global_gain(struct mt9m111 *mt9m111) 799 { 800 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 801 int data; 802 803 data = reg_read(GLOBAL_GAIN); 804 if (data >= 0) 805 return (data & 0x2f) * (1 << ((data >> 10) & 1)) * 806 (1 << ((data >> 9) & 1)); 807 return data; 808 } 809 810 static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain) 811 { 812 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 813 u16 val; 814 815 if (gain > 63 * 2 * 2) 816 return -EINVAL; 817 818 if ((gain >= 64 * 2) && (gain < 63 * 2 * 2)) 819 val = (1 << 10) | (1 << 9) | (gain / 4); 820 else if ((gain >= 64) && (gain < 64 * 2)) 821 val = (1 << 9) | (gain / 2); 822 else 823 val = gain; 824 825 return reg_write(GLOBAL_GAIN, val); 826 } 827 828 static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val) 829 { 830 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 831 832 if (val == V4L2_EXPOSURE_AUTO) 833 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); 834 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); 835 } 836 837 static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on) 838 { 839 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 840 841 if (on) 842 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); 843 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); 844 } 845 846 static const char * const mt9m111_test_pattern_menu[] = { 847 "Disabled", 848 "Vertical monochrome gradient", 849 "Flat color type 1", 850 "Flat color type 2", 851 "Flat color type 3", 852 "Flat color type 4", 853 "Flat color type 5", 854 "Color bar", 855 }; 856 857 static int mt9m111_set_test_pattern(struct mt9m111 *mt9m111, int val) 858 { 859 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 860 861 return mt9m111_reg_mask(client, MT9M111_TPG_CTRL, val, 862 MT9M111_TPG_SEL_MASK); 863 } 864 865 static int mt9m111_set_colorfx(struct mt9m111 *mt9m111, int val) 866 { 867 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 868 static const struct v4l2_control colorfx[] = { 869 { V4L2_COLORFX_NONE, 0 }, 870 { V4L2_COLORFX_BW, 1 }, 871 { V4L2_COLORFX_SEPIA, 2 }, 872 { V4L2_COLORFX_NEGATIVE, 3 }, 873 { V4L2_COLORFX_SOLARIZATION, 4 }, 874 }; 875 int i; 876 877 for (i = 0; i < ARRAY_SIZE(colorfx); i++) { 878 if (colorfx[i].id == val) { 879 return mt9m111_reg_mask(client, MT9M111_EFFECTS_MODE, 880 colorfx[i].value, 881 MT9M111_EFFECTS_MODE_MASK); 882 } 883 } 884 885 return -EINVAL; 886 } 887 888 static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl) 889 { 890 struct mt9m111 *mt9m111 = container_of(ctrl->handler, 891 struct mt9m111, hdl); 892 893 switch (ctrl->id) { 894 case V4L2_CID_VFLIP: 895 return mt9m111_set_flip(mt9m111, ctrl->val, 896 MT9M111_RMB_MIRROR_ROWS); 897 case V4L2_CID_HFLIP: 898 return mt9m111_set_flip(mt9m111, ctrl->val, 899 MT9M111_RMB_MIRROR_COLS); 900 case V4L2_CID_GAIN: 901 return mt9m111_set_global_gain(mt9m111, ctrl->val); 902 case V4L2_CID_EXPOSURE_AUTO: 903 return mt9m111_set_autoexposure(mt9m111, ctrl->val); 904 case V4L2_CID_AUTO_WHITE_BALANCE: 905 return mt9m111_set_autowhitebalance(mt9m111, ctrl->val); 906 case V4L2_CID_TEST_PATTERN: 907 return mt9m111_set_test_pattern(mt9m111, ctrl->val); 908 case V4L2_CID_COLORFX: 909 return mt9m111_set_colorfx(mt9m111, ctrl->val); 910 } 911 912 return -EINVAL; 913 } 914 915 static int mt9m111_suspend(struct mt9m111 *mt9m111) 916 { 917 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 918 int ret; 919 920 v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111)); 921 922 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); 923 if (!ret) 924 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC | 925 MT9M111_RESET_OUTPUT_DISABLE | 926 MT9M111_RESET_ANALOG_STANDBY); 927 if (!ret) 928 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE); 929 930 return ret; 931 } 932 933 static void mt9m111_restore_state(struct mt9m111 *mt9m111) 934 { 935 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 936 937 mt9m111_set_context(mt9m111, mt9m111->ctx); 938 mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code); 939 mt9m111_setup_geometry(mt9m111, &mt9m111->rect, 940 mt9m111->width, mt9m111->height, mt9m111->fmt->code); 941 v4l2_ctrl_handler_setup(&mt9m111->hdl); 942 mt9m111_reg_mask(client, mt9m111->ctx->read_mode, 943 mt9m111->current_mode->reg_val, 944 mt9m111->current_mode->reg_mask); 945 } 946 947 static int mt9m111_resume(struct mt9m111 *mt9m111) 948 { 949 int ret = mt9m111_enable(mt9m111); 950 if (!ret) 951 ret = mt9m111_reset(mt9m111); 952 if (!ret) 953 mt9m111_restore_state(mt9m111); 954 955 return ret; 956 } 957 958 static int mt9m111_init(struct mt9m111 *mt9m111) 959 { 960 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 961 int ret; 962 963 ret = mt9m111_enable(mt9m111); 964 if (!ret) 965 ret = mt9m111_reset(mt9m111); 966 if (!ret) 967 ret = mt9m111_set_context(mt9m111, mt9m111->ctx); 968 if (ret) 969 dev_err(&client->dev, "mt9m111 init failed: %d\n", ret); 970 return ret; 971 } 972 973 static int mt9m111_power_on(struct mt9m111 *mt9m111) 974 { 975 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); 976 int ret; 977 978 ret = v4l2_clk_enable(mt9m111->clk); 979 if (ret < 0) 980 return ret; 981 982 ret = mt9m111_resume(mt9m111); 983 if (ret < 0) { 984 dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret); 985 v4l2_clk_disable(mt9m111->clk); 986 } 987 988 return ret; 989 } 990 991 static void mt9m111_power_off(struct mt9m111 *mt9m111) 992 { 993 mt9m111_suspend(mt9m111); 994 v4l2_clk_disable(mt9m111->clk); 995 } 996 997 static int mt9m111_s_power(struct v4l2_subdev *sd, int on) 998 { 999 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1000 int ret = 0; 1001 1002 mutex_lock(&mt9m111->power_lock); 1003 1004 /* 1005 * If the power count is modified from 0 to != 0 or from != 0 to 0, 1006 * update the power state. 1007 */ 1008 if (mt9m111->power_count == !on) { 1009 if (on) 1010 ret = mt9m111_power_on(mt9m111); 1011 else 1012 mt9m111_power_off(mt9m111); 1013 } 1014 1015 if (!ret) { 1016 /* Update the power count. */ 1017 mt9m111->power_count += on ? 1 : -1; 1018 WARN_ON(mt9m111->power_count < 0); 1019 } 1020 1021 mutex_unlock(&mt9m111->power_lock); 1022 return ret; 1023 } 1024 1025 static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = { 1026 .s_ctrl = mt9m111_s_ctrl, 1027 }; 1028 1029 static const struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = { 1030 .s_power = mt9m111_s_power, 1031 .log_status = v4l2_ctrl_subdev_log_status, 1032 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1033 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1034 #ifdef CONFIG_VIDEO_ADV_DEBUG 1035 .g_register = mt9m111_g_register, 1036 .s_register = mt9m111_s_register, 1037 #endif 1038 }; 1039 1040 static int mt9m111_g_frame_interval(struct v4l2_subdev *sd, 1041 struct v4l2_subdev_frame_interval *fi) 1042 { 1043 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1044 1045 fi->interval = mt9m111->frame_interval; 1046 1047 return 0; 1048 } 1049 1050 static int mt9m111_s_frame_interval(struct v4l2_subdev *sd, 1051 struct v4l2_subdev_frame_interval *fi) 1052 { 1053 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1054 const struct mt9m111_mode_info *mode; 1055 struct v4l2_fract *fract = &fi->interval; 1056 int fps; 1057 1058 if (mt9m111->is_streaming) 1059 return -EBUSY; 1060 1061 if (fi->pad != 0) 1062 return -EINVAL; 1063 1064 if (fract->numerator == 0) { 1065 fract->denominator = 30; 1066 fract->numerator = 1; 1067 } 1068 1069 fps = DIV_ROUND_CLOSEST(fract->denominator, fract->numerator); 1070 1071 /* Find best fitting mode. Do not update the mode if no one was found. */ 1072 mode = mt9m111_find_mode(mt9m111, fps, mt9m111->width, mt9m111->height); 1073 if (!mode) 1074 return 0; 1075 1076 if (mode->max_fps != fps) { 1077 fract->denominator = mode->max_fps; 1078 fract->numerator = 1; 1079 } 1080 1081 mt9m111->current_mode = mode; 1082 mt9m111->frame_interval = fi->interval; 1083 1084 return 0; 1085 } 1086 1087 static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd, 1088 struct v4l2_subdev_pad_config *cfg, 1089 struct v4l2_subdev_mbus_code_enum *code) 1090 { 1091 if (code->pad || code->index >= ARRAY_SIZE(mt9m111_colour_fmts)) 1092 return -EINVAL; 1093 1094 code->code = mt9m111_colour_fmts[code->index].code; 1095 return 0; 1096 } 1097 1098 static int mt9m111_s_stream(struct v4l2_subdev *sd, int enable) 1099 { 1100 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1101 1102 mt9m111->is_streaming = !!enable; 1103 return 0; 1104 } 1105 1106 static int mt9m111_init_cfg(struct v4l2_subdev *sd, 1107 struct v4l2_subdev_pad_config *cfg) 1108 { 1109 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API 1110 struct v4l2_mbus_framefmt *format = 1111 v4l2_subdev_get_try_format(sd, cfg, 0); 1112 1113 format->width = MT9M111_MAX_WIDTH; 1114 format->height = MT9M111_MAX_HEIGHT; 1115 format->code = mt9m111_colour_fmts[0].code; 1116 format->colorspace = mt9m111_colour_fmts[0].colorspace; 1117 format->field = V4L2_FIELD_NONE; 1118 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1119 format->quantization = V4L2_QUANTIZATION_DEFAULT; 1120 format->xfer_func = V4L2_XFER_FUNC_DEFAULT; 1121 #endif 1122 return 0; 1123 } 1124 1125 static int mt9m111_g_mbus_config(struct v4l2_subdev *sd, 1126 struct v4l2_mbus_config *cfg) 1127 { 1128 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); 1129 1130 cfg->flags = V4L2_MBUS_MASTER | 1131 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH | 1132 V4L2_MBUS_DATA_ACTIVE_HIGH; 1133 1134 cfg->flags |= mt9m111->pclk_sample ? V4L2_MBUS_PCLK_SAMPLE_RISING : 1135 V4L2_MBUS_PCLK_SAMPLE_FALLING; 1136 1137 cfg->type = V4L2_MBUS_PARALLEL; 1138 1139 return 0; 1140 } 1141 1142 static const struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = { 1143 .g_mbus_config = mt9m111_g_mbus_config, 1144 .s_stream = mt9m111_s_stream, 1145 .g_frame_interval = mt9m111_g_frame_interval, 1146 .s_frame_interval = mt9m111_s_frame_interval, 1147 }; 1148 1149 static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = { 1150 .init_cfg = mt9m111_init_cfg, 1151 .enum_mbus_code = mt9m111_enum_mbus_code, 1152 .get_selection = mt9m111_get_selection, 1153 .set_selection = mt9m111_set_selection, 1154 .get_fmt = mt9m111_get_fmt, 1155 .set_fmt = mt9m111_set_fmt, 1156 }; 1157 1158 static const struct v4l2_subdev_ops mt9m111_subdev_ops = { 1159 .core = &mt9m111_subdev_core_ops, 1160 .video = &mt9m111_subdev_video_ops, 1161 .pad = &mt9m111_subdev_pad_ops, 1162 }; 1163 1164 /* 1165 * Interface active, can use i2c. If it fails, it can indeed mean, that 1166 * this wasn't our capture interface, so, we wait for the right one 1167 */ 1168 static int mt9m111_video_probe(struct i2c_client *client) 1169 { 1170 struct mt9m111 *mt9m111 = to_mt9m111(client); 1171 s32 data; 1172 int ret; 1173 1174 ret = mt9m111_s_power(&mt9m111->subdev, 1); 1175 if (ret < 0) 1176 return ret; 1177 1178 data = reg_read(CHIP_VERSION); 1179 1180 switch (data) { 1181 case 0x143a: /* MT9M111 or MT9M131 */ 1182 dev_info(&client->dev, 1183 "Detected a MT9M111/MT9M131 chip ID %x\n", data); 1184 break; 1185 case 0x148c: /* MT9M112 */ 1186 dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data); 1187 break; 1188 default: 1189 dev_err(&client->dev, 1190 "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n", 1191 data); 1192 ret = -ENODEV; 1193 goto done; 1194 } 1195 1196 ret = mt9m111_init(mt9m111); 1197 if (ret) 1198 goto done; 1199 1200 ret = v4l2_ctrl_handler_setup(&mt9m111->hdl); 1201 1202 done: 1203 mt9m111_s_power(&mt9m111->subdev, 0); 1204 return ret; 1205 } 1206 1207 static int mt9m111_probe_fw(struct i2c_client *client, struct mt9m111 *mt9m111) 1208 { 1209 struct v4l2_fwnode_endpoint bus_cfg = { 1210 .bus_type = V4L2_MBUS_PARALLEL 1211 }; 1212 struct fwnode_handle *np; 1213 int ret; 1214 1215 np = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL); 1216 if (!np) 1217 return -EINVAL; 1218 1219 ret = v4l2_fwnode_endpoint_parse(np, &bus_cfg); 1220 if (ret) 1221 goto out_put_fw; 1222 1223 mt9m111->pclk_sample = !!(bus_cfg.bus.parallel.flags & 1224 V4L2_MBUS_PCLK_SAMPLE_RISING); 1225 1226 out_put_fw: 1227 fwnode_handle_put(np); 1228 return ret; 1229 } 1230 1231 static int mt9m111_probe(struct i2c_client *client, 1232 const struct i2c_device_id *did) 1233 { 1234 struct mt9m111 *mt9m111; 1235 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); 1236 int ret; 1237 1238 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { 1239 dev_warn(&adapter->dev, 1240 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); 1241 return -EIO; 1242 } 1243 1244 mt9m111 = devm_kzalloc(&client->dev, sizeof(struct mt9m111), GFP_KERNEL); 1245 if (!mt9m111) 1246 return -ENOMEM; 1247 1248 ret = mt9m111_probe_fw(client, mt9m111); 1249 if (ret) 1250 return ret; 1251 1252 mt9m111->clk = v4l2_clk_get(&client->dev, "mclk"); 1253 if (IS_ERR(mt9m111->clk)) 1254 return PTR_ERR(mt9m111->clk); 1255 1256 /* Default HIGHPOWER context */ 1257 mt9m111->ctx = &context_b; 1258 1259 v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops); 1260 mt9m111->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1261 V4L2_SUBDEV_FL_HAS_EVENTS; 1262 1263 v4l2_ctrl_handler_init(&mt9m111->hdl, 7); 1264 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1265 V4L2_CID_VFLIP, 0, 1, 1, 0); 1266 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1267 V4L2_CID_HFLIP, 0, 1, 1, 0); 1268 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1269 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); 1270 mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, 1271 V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32); 1272 v4l2_ctrl_new_std_menu(&mt9m111->hdl, 1273 &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0, 1274 V4L2_EXPOSURE_AUTO); 1275 v4l2_ctrl_new_std_menu_items(&mt9m111->hdl, 1276 &mt9m111_ctrl_ops, V4L2_CID_TEST_PATTERN, 1277 ARRAY_SIZE(mt9m111_test_pattern_menu) - 1, 0, 0, 1278 mt9m111_test_pattern_menu); 1279 v4l2_ctrl_new_std_menu(&mt9m111->hdl, &mt9m111_ctrl_ops, 1280 V4L2_CID_COLORFX, V4L2_COLORFX_SOLARIZATION, 1281 ~(BIT(V4L2_COLORFX_NONE) | 1282 BIT(V4L2_COLORFX_BW) | 1283 BIT(V4L2_COLORFX_SEPIA) | 1284 BIT(V4L2_COLORFX_NEGATIVE) | 1285 BIT(V4L2_COLORFX_SOLARIZATION)), 1286 V4L2_COLORFX_NONE); 1287 mt9m111->subdev.ctrl_handler = &mt9m111->hdl; 1288 if (mt9m111->hdl.error) { 1289 ret = mt9m111->hdl.error; 1290 goto out_clkput; 1291 } 1292 1293 #ifdef CONFIG_MEDIA_CONTROLLER 1294 mt9m111->pad.flags = MEDIA_PAD_FL_SOURCE; 1295 mt9m111->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1296 ret = media_entity_pads_init(&mt9m111->subdev.entity, 1, &mt9m111->pad); 1297 if (ret < 0) 1298 goto out_hdlfree; 1299 #endif 1300 1301 mt9m111->current_mode = &mt9m111_mode_data[MT9M111_MODE_SXGA_15FPS]; 1302 mt9m111->frame_interval.numerator = 1; 1303 mt9m111->frame_interval.denominator = mt9m111->current_mode->max_fps; 1304 1305 /* Second stage probe - when a capture adapter is there */ 1306 mt9m111->rect.left = MT9M111_MIN_DARK_COLS; 1307 mt9m111->rect.top = MT9M111_MIN_DARK_ROWS; 1308 mt9m111->rect.width = MT9M111_MAX_WIDTH; 1309 mt9m111->rect.height = MT9M111_MAX_HEIGHT; 1310 mt9m111->width = mt9m111->rect.width; 1311 mt9m111->height = mt9m111->rect.height; 1312 mt9m111->fmt = &mt9m111_colour_fmts[0]; 1313 mt9m111->lastpage = -1; 1314 mutex_init(&mt9m111->power_lock); 1315 1316 ret = mt9m111_video_probe(client); 1317 if (ret < 0) 1318 goto out_entityclean; 1319 1320 mt9m111->subdev.dev = &client->dev; 1321 ret = v4l2_async_register_subdev(&mt9m111->subdev); 1322 if (ret < 0) 1323 goto out_entityclean; 1324 1325 return 0; 1326 1327 out_entityclean: 1328 #ifdef CONFIG_MEDIA_CONTROLLER 1329 media_entity_cleanup(&mt9m111->subdev.entity); 1330 out_hdlfree: 1331 #endif 1332 v4l2_ctrl_handler_free(&mt9m111->hdl); 1333 out_clkput: 1334 v4l2_clk_put(mt9m111->clk); 1335 1336 return ret; 1337 } 1338 1339 static int mt9m111_remove(struct i2c_client *client) 1340 { 1341 struct mt9m111 *mt9m111 = to_mt9m111(client); 1342 1343 v4l2_async_unregister_subdev(&mt9m111->subdev); 1344 media_entity_cleanup(&mt9m111->subdev.entity); 1345 v4l2_clk_put(mt9m111->clk); 1346 v4l2_ctrl_handler_free(&mt9m111->hdl); 1347 1348 return 0; 1349 } 1350 static const struct of_device_id mt9m111_of_match[] = { 1351 { .compatible = "micron,mt9m111", }, 1352 {}, 1353 }; 1354 MODULE_DEVICE_TABLE(of, mt9m111_of_match); 1355 1356 static const struct i2c_device_id mt9m111_id[] = { 1357 { "mt9m111", 0 }, 1358 { } 1359 }; 1360 MODULE_DEVICE_TABLE(i2c, mt9m111_id); 1361 1362 static struct i2c_driver mt9m111_i2c_driver = { 1363 .driver = { 1364 .name = "mt9m111", 1365 .of_match_table = of_match_ptr(mt9m111_of_match), 1366 }, 1367 .probe = mt9m111_probe, 1368 .remove = mt9m111_remove, 1369 .id_table = mt9m111_id, 1370 }; 1371 1372 module_i2c_driver(mt9m111_i2c_driver); 1373 1374 MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver"); 1375 MODULE_AUTHOR("Robert Jarzmik"); 1376 MODULE_LICENSE("GPL"); 1377