1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Wave5 series multi-standard codec IP - platform driver 4 * 5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC 6 */ 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/clk.h> 11 #include <linux/firmware.h> 12 #include <linux/interrupt.h> 13 #include "wave5-vpu.h" 14 #include "wave5-regdefine.h" 15 #include "wave5-vpuconfig.h" 16 #include "wave5.h" 17 18 #define VPU_PLATFORM_DEVICE_NAME "vdec" 19 #define VPU_CLK_NAME "vcodec" 20 21 #define WAVE5_IS_ENC BIT(0) 22 #define WAVE5_IS_DEC BIT(1) 23 24 struct wave5_match_data { 25 int flags; 26 const char *fw_name; 27 }; 28 29 int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout) 30 { 31 int ret; 32 33 ret = wait_for_completion_timeout(&inst->irq_done, 34 msecs_to_jiffies(timeout)); 35 if (!ret) 36 return -ETIMEDOUT; 37 38 reinit_completion(&inst->irq_done); 39 40 return 0; 41 } 42 43 static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) 44 { 45 u32 seq_done; 46 u32 cmd_done; 47 u32 irq_reason; 48 struct vpu_instance *inst; 49 struct vpu_device *dev = dev_id; 50 51 if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) { 52 irq_reason = wave5_vdi_read_register(dev, W5_VPU_VINT_REASON); 53 wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_reason); 54 wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1); 55 56 list_for_each_entry(inst, &dev->instances, list) { 57 seq_done = wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO); 58 cmd_done = wave5_vdi_read_register(dev, W5_RET_QUEUE_CMD_DONE_INST); 59 60 if (irq_reason & BIT(INT_WAVE5_INIT_SEQ) || 61 irq_reason & BIT(INT_WAVE5_ENC_SET_PARAM)) { 62 if (seq_done & BIT(inst->id)) { 63 seq_done &= ~BIT(inst->id); 64 wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, 65 seq_done); 66 complete(&inst->irq_done); 67 } 68 } 69 70 if (irq_reason & BIT(INT_WAVE5_DEC_PIC) || 71 irq_reason & BIT(INT_WAVE5_ENC_PIC)) { 72 if (cmd_done & BIT(inst->id)) { 73 cmd_done &= ~BIT(inst->id); 74 wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, 75 cmd_done); 76 inst->ops->finish_process(inst); 77 } 78 } 79 80 wave5_vpu_clear_interrupt(inst, irq_reason); 81 } 82 } 83 84 return IRQ_HANDLED; 85 } 86 87 static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name, 88 u32 *revision) 89 { 90 const struct firmware *fw; 91 int ret; 92 unsigned int product_id; 93 94 ret = request_firmware(&fw, fw_name, dev); 95 if (ret) { 96 dev_err(dev, "request_firmware, fail: %d\n", ret); 97 return ret; 98 } 99 100 ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size); 101 if (ret) { 102 dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret); 103 release_firmware(fw); 104 return ret; 105 } 106 release_firmware(fw); 107 108 ret = wave5_vpu_get_version_info(dev, revision, &product_id); 109 if (ret) { 110 dev_err(dev, "vpu_get_version_info fail: %d\n", ret); 111 return ret; 112 } 113 114 dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n", 115 __func__, product_id, *revision); 116 117 return 0; 118 } 119 120 static int wave5_vpu_probe(struct platform_device *pdev) 121 { 122 int ret; 123 struct vpu_device *dev; 124 const struct wave5_match_data *match_data; 125 u32 fw_revision; 126 127 match_data = device_get_match_data(&pdev->dev); 128 if (!match_data) { 129 dev_err(&pdev->dev, "missing device match data\n"); 130 return -EINVAL; 131 } 132 133 /* physical addresses limited to 32 bits */ 134 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 135 if (ret) { 136 dev_err(&pdev->dev, "Failed to set DMA mask: %d\n", ret); 137 return ret; 138 } 139 140 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 141 if (!dev) 142 return -ENOMEM; 143 144 dev->vdb_register = devm_platform_ioremap_resource(pdev, 0); 145 if (IS_ERR(dev->vdb_register)) 146 return PTR_ERR(dev->vdb_register); 147 ida_init(&dev->inst_ida); 148 149 mutex_init(&dev->dev_lock); 150 mutex_init(&dev->hw_lock); 151 dev_set_drvdata(&pdev->dev, dev); 152 dev->dev = &pdev->dev; 153 154 ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks); 155 156 /* continue without clock, assume externally managed */ 157 if (ret < 0) { 158 dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret); 159 ret = 0; 160 } 161 dev->num_clks = ret; 162 163 ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks); 164 if (ret) { 165 dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret); 166 return ret; 167 } 168 169 ret = of_property_read_u32(pdev->dev.of_node, "sram-size", 170 &dev->sram_size); 171 if (ret) { 172 dev_warn(&pdev->dev, "sram-size not found\n"); 173 dev->sram_size = 0; 174 } 175 176 dev->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0); 177 if (!dev->sram_pool) 178 dev_warn(&pdev->dev, "sram node not found\n"); 179 180 dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER); 181 ret = wave5_vdi_init(&pdev->dev); 182 if (ret < 0) { 183 dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret); 184 goto err_clk_dis; 185 } 186 dev->product = wave5_vpu_get_product_id(dev); 187 188 INIT_LIST_HEAD(&dev->instances); 189 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 190 if (ret) { 191 dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret); 192 goto err_vdi_release; 193 } 194 195 if (match_data->flags & WAVE5_IS_DEC) { 196 ret = wave5_vpu_dec_register_device(dev); 197 if (ret) { 198 dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret); 199 goto err_v4l2_unregister; 200 } 201 } 202 if (match_data->flags & WAVE5_IS_ENC) { 203 ret = wave5_vpu_enc_register_device(dev); 204 if (ret) { 205 dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret); 206 goto err_dec_unreg; 207 } 208 } 209 210 dev->irq = platform_get_irq(pdev, 0); 211 if (dev->irq < 0) { 212 dev_err(&pdev->dev, "failed to get irq resource\n"); 213 ret = -ENXIO; 214 goto err_enc_unreg; 215 } 216 217 ret = devm_request_threaded_irq(&pdev->dev, dev->irq, NULL, 218 wave5_vpu_irq_thread, IRQF_ONESHOT, "vpu_irq", dev); 219 if (ret) { 220 dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret); 221 goto err_enc_unreg; 222 } 223 224 ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name, &fw_revision); 225 if (ret) { 226 dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret); 227 goto err_enc_unreg; 228 } 229 230 dev_info(&pdev->dev, "Added wave5 driver with caps: %s %s\n", 231 (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "", 232 (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : ""); 233 dev_info(&pdev->dev, "Product Code: 0x%x\n", dev->product_code); 234 dev_info(&pdev->dev, "Firmware Revision: %u\n", fw_revision); 235 return 0; 236 237 err_enc_unreg: 238 if (match_data->flags & WAVE5_IS_ENC) 239 wave5_vpu_enc_unregister_device(dev); 240 err_dec_unreg: 241 if (match_data->flags & WAVE5_IS_DEC) 242 wave5_vpu_dec_unregister_device(dev); 243 err_v4l2_unregister: 244 v4l2_device_unregister(&dev->v4l2_dev); 245 err_vdi_release: 246 wave5_vdi_release(&pdev->dev); 247 err_clk_dis: 248 clk_bulk_disable_unprepare(dev->num_clks, dev->clks); 249 250 return ret; 251 } 252 253 static void wave5_vpu_remove(struct platform_device *pdev) 254 { 255 struct vpu_device *dev = dev_get_drvdata(&pdev->dev); 256 257 mutex_destroy(&dev->dev_lock); 258 mutex_destroy(&dev->hw_lock); 259 clk_bulk_disable_unprepare(dev->num_clks, dev->clks); 260 wave5_vpu_enc_unregister_device(dev); 261 wave5_vpu_dec_unregister_device(dev); 262 v4l2_device_unregister(&dev->v4l2_dev); 263 wave5_vdi_release(&pdev->dev); 264 ida_destroy(&dev->inst_ida); 265 } 266 267 static const struct wave5_match_data ti_wave521c_data = { 268 .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, 269 .fw_name = "cnm/wave521c_k3_codec_fw.bin", 270 }; 271 272 static const struct of_device_id wave5_dt_ids[] = { 273 { .compatible = "ti,j721s2-wave521c", .data = &ti_wave521c_data }, 274 { /* sentinel */ } 275 }; 276 MODULE_DEVICE_TABLE(of, wave5_dt_ids); 277 278 static struct platform_driver wave5_vpu_driver = { 279 .driver = { 280 .name = VPU_PLATFORM_DEVICE_NAME, 281 .of_match_table = of_match_ptr(wave5_dt_ids), 282 }, 283 .probe = wave5_vpu_probe, 284 .remove_new = wave5_vpu_remove, 285 }; 286 287 module_platform_driver(wave5_vpu_driver); 288 MODULE_DESCRIPTION("chips&media VPU V4L2 driver"); 289 MODULE_LICENSE("Dual BSD/GPL"); 290