1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <media/videobuf2-v4l2.h> 4 #include <media/videobuf2-dma-contig.h> 5 #include <media/v4l2-event.h> 6 #include <media/v4l2-mem2mem.h> 7 #include <linux/module.h> 8 9 #include "mtk_vcodec_dec.h" 10 #include "mtk_vcodec_dec_pm.h" 11 #include "vdec_drv_if.h" 12 13 /** 14 * struct mtk_stateless_control - CID control type 15 * @cfg: control configuration 16 * @codec_type: codec type (V4L2 pixel format) for CID control type 17 */ 18 struct mtk_stateless_control { 19 struct v4l2_ctrl_config cfg; 20 int codec_type; 21 }; 22 23 static const struct mtk_stateless_control mtk_stateless_controls[] = { 24 { 25 .cfg = { 26 .id = V4L2_CID_STATELESS_H264_SPS, 27 }, 28 .codec_type = V4L2_PIX_FMT_H264_SLICE, 29 }, 30 { 31 .cfg = { 32 .id = V4L2_CID_STATELESS_H264_PPS, 33 }, 34 .codec_type = V4L2_PIX_FMT_H264_SLICE, 35 }, 36 { 37 .cfg = { 38 .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX, 39 }, 40 .codec_type = V4L2_PIX_FMT_H264_SLICE, 41 }, 42 { 43 .cfg = { 44 .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, 45 }, 46 .codec_type = V4L2_PIX_FMT_H264_SLICE, 47 }, 48 { 49 .cfg = { 50 .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, 51 .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, 52 .max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 53 .menu_skip_mask = 54 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | 55 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED), 56 }, 57 .codec_type = V4L2_PIX_FMT_H264_SLICE, 58 }, 59 { 60 .cfg = { 61 .id = V4L2_CID_STATELESS_H264_DECODE_MODE, 62 .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 63 .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 64 .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 65 }, 66 .codec_type = V4L2_PIX_FMT_H264_SLICE, 67 }, 68 { 69 .cfg = { 70 .id = V4L2_CID_STATELESS_H264_START_CODE, 71 .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 72 .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 73 .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 74 }, 75 .codec_type = V4L2_PIX_FMT_H264_SLICE, 76 }, 77 { 78 .cfg = { 79 .id = V4L2_CID_STATELESS_VP8_FRAME, 80 }, 81 .codec_type = V4L2_PIX_FMT_VP8_FRAME, 82 }, 83 { 84 .cfg = { 85 .id = V4L2_CID_MPEG_VIDEO_VP8_PROFILE, 86 .min = V4L2_MPEG_VIDEO_VP8_PROFILE_0, 87 .def = V4L2_MPEG_VIDEO_VP8_PROFILE_0, 88 .max = V4L2_MPEG_VIDEO_VP8_PROFILE_3, 89 }, 90 .codec_type = V4L2_PIX_FMT_VP8_FRAME, 91 }, 92 { 93 .cfg = { 94 .id = V4L2_CID_STATELESS_VP9_FRAME, 95 }, 96 .codec_type = V4L2_PIX_FMT_VP9_FRAME, 97 }, 98 { 99 .cfg = { 100 .id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE, 101 .min = V4L2_MPEG_VIDEO_VP9_PROFILE_0, 102 .def = V4L2_MPEG_VIDEO_VP9_PROFILE_0, 103 .max = V4L2_MPEG_VIDEO_VP9_PROFILE_3, 104 }, 105 .codec_type = V4L2_PIX_FMT_VP9_FRAME, 106 }, 107 { 108 .cfg = { 109 .id = V4L2_CID_STATELESS_HEVC_SPS, 110 }, 111 .codec_type = V4L2_PIX_FMT_HEVC_SLICE, 112 }, 113 { 114 .cfg = { 115 .id = V4L2_CID_STATELESS_HEVC_PPS, 116 }, 117 .codec_type = V4L2_PIX_FMT_HEVC_SLICE, 118 }, 119 { 120 .cfg = { 121 .id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, 122 }, 123 .codec_type = V4L2_PIX_FMT_HEVC_SLICE, 124 }, 125 { 126 .cfg = { 127 .id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, 128 }, 129 .codec_type = V4L2_PIX_FMT_HEVC_SLICE, 130 }, 131 { 132 .cfg = { 133 .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, 134 .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, 135 .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 136 .menu_skip_mask = 137 BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), 138 }, 139 .codec_type = V4L2_PIX_FMT_HEVC_SLICE, 140 }, 141 { 142 .cfg = { 143 .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, 144 .min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, 145 .def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, 146 .max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, 147 }, 148 .codec_type = V4L2_PIX_FMT_HEVC_SLICE, 149 }, 150 { 151 .cfg = { 152 .id = V4L2_CID_STATELESS_HEVC_START_CODE, 153 .min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, 154 .def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, 155 .max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, 156 }, 157 .codec_type = V4L2_PIX_FMT_HEVC_SLICE, 158 }, 159 { 160 .cfg = { 161 .id = V4L2_CID_STATELESS_AV1_SEQUENCE, 162 163 }, 164 .codec_type = V4L2_PIX_FMT_AV1_FRAME, 165 }, 166 { 167 .cfg = { 168 .id = V4L2_CID_STATELESS_AV1_FRAME, 169 170 }, 171 .codec_type = V4L2_PIX_FMT_AV1_FRAME, 172 }, 173 { 174 .cfg = { 175 .id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY, 176 .dims = { V4L2_AV1_MAX_TILE_COUNT }, 177 178 }, 179 .codec_type = V4L2_PIX_FMT_AV1_FRAME, 180 }, 181 { 182 .cfg = { 183 .id = V4L2_CID_MPEG_VIDEO_AV1_PROFILE, 184 .min = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, 185 .def = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, 186 .max = V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN, 187 }, 188 .codec_type = V4L2_PIX_FMT_AV1_FRAME, 189 }, 190 { 191 .cfg = { 192 .id = V4L2_CID_MPEG_VIDEO_AV1_LEVEL, 193 .min = V4L2_MPEG_VIDEO_AV1_LEVEL_2_0, 194 .def = V4L2_MPEG_VIDEO_AV1_LEVEL_4_0, 195 .max = V4L2_MPEG_VIDEO_AV1_LEVEL_5_1, 196 }, 197 .codec_type = V4L2_PIX_FMT_AV1_FRAME, 198 }, 199 }; 200 201 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) 202 203 static struct mtk_video_fmt mtk_video_formats[9]; 204 205 static struct mtk_video_fmt default_out_format; 206 static struct mtk_video_fmt default_cap_format; 207 static unsigned int num_formats; 208 209 static const struct v4l2_frmsize_stepwise stepwise_fhd = { 210 .min_width = MTK_VDEC_MIN_W, 211 .max_width = MTK_VDEC_MAX_W, 212 .step_width = 16, 213 .min_height = MTK_VDEC_MIN_H, 214 .max_height = MTK_VDEC_MAX_H, 215 .step_height = 16 216 }; 217 218 static void mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_dec_ctx *ctx, int error, 219 struct media_request *src_buf_req) 220 { 221 struct vb2_v4l2_buffer *vb2_dst; 222 enum vb2_buffer_state state; 223 224 if (error) 225 state = VB2_BUF_STATE_ERROR; 226 else 227 state = VB2_BUF_STATE_DONE; 228 229 vb2_dst = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx); 230 if (vb2_dst) { 231 v4l2_m2m_buf_done(vb2_dst, state); 232 mtk_v4l2_vdec_dbg(2, ctx, "free frame buffer id:%d to done list", 233 vb2_dst->vb2_buf.index); 234 } else { 235 mtk_v4l2_vdec_err(ctx, "dst buffer is NULL"); 236 } 237 238 if (src_buf_req) 239 v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl); 240 } 241 242 static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_dec_ctx *ctx) 243 { 244 struct mtk_video_dec_buf *framebuf; 245 struct vb2_v4l2_buffer *vb2_v4l2; 246 struct vb2_buffer *dst_buf; 247 struct vdec_fb *pfb; 248 249 vb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx); 250 if (!vb2_v4l2) { 251 mtk_v4l2_vdec_dbg(1, ctx, "[%d] dst_buf empty!!", ctx->id); 252 return NULL; 253 } 254 255 dst_buf = &vb2_v4l2->vb2_buf; 256 framebuf = container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb); 257 258 pfb = &framebuf->frame_buffer; 259 pfb->base_y.va = vb2_plane_vaddr(dst_buf, 0); 260 pfb->base_y.dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0); 261 pfb->base_y.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[0]; 262 263 if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2) { 264 pfb->base_c.va = vb2_plane_vaddr(dst_buf, 1); 265 pfb->base_c.dma_addr = 266 vb2_dma_contig_plane_dma_addr(dst_buf, 1); 267 pfb->base_c.size = ctx->q_data[MTK_Q_DATA_DST].sizeimage[1]; 268 } 269 mtk_v4l2_vdec_dbg(1, ctx, 270 "id=%d Framebuf pfb=%p VA=%p Y/C_DMA=%pad_%pad Sz=%zx frame_count = %d", 271 dst_buf->index, pfb, pfb->base_y.va, &pfb->base_y.dma_addr, 272 &pfb->base_c.dma_addr, pfb->base_y.size, ctx->decoded_frame_cnt); 273 274 return pfb; 275 } 276 277 static void vb2ops_vdec_buf_request_complete(struct vb2_buffer *vb) 278 { 279 struct mtk_vcodec_dec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 280 281 v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->ctrl_hdl); 282 } 283 284 static void mtk_vdec_worker(struct work_struct *work) 285 { 286 struct mtk_vcodec_dec_ctx *ctx = 287 container_of(work, struct mtk_vcodec_dec_ctx, decode_work); 288 struct mtk_vcodec_dec_dev *dev = ctx->dev; 289 struct vb2_v4l2_buffer *vb2_v4l2_src; 290 struct vb2_buffer *vb2_src; 291 struct mtk_vcodec_mem *bs_src; 292 struct mtk_video_dec_buf *dec_buf_src; 293 struct media_request *src_buf_req; 294 enum vb2_buffer_state state; 295 bool res_chg = false; 296 int ret; 297 298 vb2_v4l2_src = v4l2_m2m_next_src_buf(ctx->m2m_ctx); 299 if (!vb2_v4l2_src) { 300 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); 301 mtk_v4l2_vdec_dbg(1, ctx, "[%d] no available source buffer", ctx->id); 302 return; 303 } 304 305 vb2_src = &vb2_v4l2_src->vb2_buf; 306 dec_buf_src = container_of(vb2_v4l2_src, struct mtk_video_dec_buf, 307 m2m_buf.vb); 308 bs_src = &dec_buf_src->bs_buffer; 309 310 mtk_v4l2_vdec_dbg(3, ctx, "[%d] (%d) id=%d, vb=%p", ctx->id, 311 vb2_src->vb2_queue->type, vb2_src->index, vb2_src); 312 313 bs_src->va = vb2_plane_vaddr(vb2_src, 0); 314 bs_src->dma_addr = vb2_dma_contig_plane_dma_addr(vb2_src, 0); 315 bs_src->size = (size_t)vb2_src->planes[0].bytesused; 316 if (!bs_src->va) { 317 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); 318 mtk_v4l2_vdec_err(ctx, "[%d] id=%d source buffer is NULL", ctx->id, 319 vb2_src->index); 320 return; 321 } 322 323 mtk_v4l2_vdec_dbg(3, ctx, "[%d] Bitstream VA=%p DMA=%pad Size=%zx vb=%p", 324 ctx->id, bs_src->va, &bs_src->dma_addr, bs_src->size, vb2_src); 325 /* Apply request controls. */ 326 src_buf_req = vb2_src->req_obj.req; 327 if (src_buf_req) 328 v4l2_ctrl_request_setup(src_buf_req, &ctx->ctrl_hdl); 329 else 330 mtk_v4l2_vdec_err(ctx, "vb2 buffer media request is NULL"); 331 332 ret = vdec_if_decode(ctx, bs_src, NULL, &res_chg); 333 if (ret && ret != -EAGAIN) { 334 mtk_v4l2_vdec_err(ctx, 335 "[%d] decode src_buf[%d] sz=0x%zx pts=%llu ret=%d res_chg=%d", 336 ctx->id, vb2_src->index, bs_src->size, 337 vb2_src->timestamp, ret, res_chg); 338 if (ret == -EIO) { 339 mutex_lock(&ctx->lock); 340 dec_buf_src->error = true; 341 mutex_unlock(&ctx->lock); 342 } 343 } 344 345 state = ret ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE; 346 if (!IS_VDEC_LAT_ARCH(dev->vdec_pdata->hw_arch) || 347 ctx->current_codec == V4L2_PIX_FMT_VP8_FRAME) { 348 v4l2_m2m_buf_done_and_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx, state); 349 if (src_buf_req) 350 v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl); 351 } else { 352 if (ret != -EAGAIN) { 353 v4l2_m2m_src_buf_remove(ctx->m2m_ctx); 354 v4l2_m2m_buf_done(vb2_v4l2_src, state); 355 } 356 v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); 357 } 358 } 359 360 static void vb2ops_vdec_stateless_buf_queue(struct vb2_buffer *vb) 361 { 362 struct mtk_vcodec_dec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 363 struct vb2_v4l2_buffer *vb2_v4l2 = to_vb2_v4l2_buffer(vb); 364 365 mtk_v4l2_vdec_dbg(3, ctx, "[%d] (%d) id=%d, vb=%p", ctx->id, vb->vb2_queue->type, 366 vb->index, vb); 367 368 mutex_lock(&ctx->lock); 369 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb2_v4l2); 370 mutex_unlock(&ctx->lock); 371 if (vb->vb2_queue->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 372 return; 373 374 /* If an OUTPUT buffer, we may need to update the state */ 375 if (ctx->state == MTK_STATE_INIT) { 376 ctx->state = MTK_STATE_HEADER; 377 mtk_v4l2_vdec_dbg(1, ctx, "Init driver from init to header."); 378 } else { 379 mtk_v4l2_vdec_dbg(3, ctx, "[%d] already init driver %d", ctx->id, ctx->state); 380 } 381 } 382 383 static int mtk_vdec_flush_decoder(struct mtk_vcodec_dec_ctx *ctx) 384 { 385 bool res_chg; 386 387 return vdec_if_decode(ctx, NULL, NULL, &res_chg); 388 } 389 390 static int mtk_vcodec_get_pic_info(struct mtk_vcodec_dec_ctx *ctx) 391 { 392 struct mtk_q_data *q_data; 393 int ret = 0; 394 395 q_data = &ctx->q_data[MTK_Q_DATA_DST]; 396 if (q_data->fmt->num_planes == 1) { 397 mtk_v4l2_vdec_err(ctx, "[%d]Error!! 10bit mode not support one plane", ctx->id); 398 return -EINVAL; 399 } 400 401 ctx->capture_fourcc = q_data->fmt->fourcc; 402 ret = vdec_if_get_param(ctx, GET_PARAM_PIC_INFO, &ctx->picinfo); 403 if (ret) { 404 mtk_v4l2_vdec_err(ctx, "[%d]Error!! Get GET_PARAM_PICTURE_INFO Fail", ctx->id); 405 return ret; 406 } 407 408 ctx->last_decoded_picinfo = ctx->picinfo; 409 410 q_data->sizeimage[0] = ctx->picinfo.fb_sz[0]; 411 q_data->bytesperline[0] = ctx->picinfo.buf_w * 5 / 4; 412 413 q_data->sizeimage[1] = ctx->picinfo.fb_sz[1]; 414 q_data->bytesperline[1] = ctx->picinfo.buf_w * 5 / 4; 415 416 q_data->coded_width = ctx->picinfo.buf_w; 417 q_data->coded_height = ctx->picinfo.buf_h; 418 mtk_v4l2_vdec_dbg(1, ctx, "[%d] wxh=%dx%d pic wxh=%dx%d sz[0]=0x%x sz[1]=0x%x", 419 ctx->id, ctx->picinfo.buf_w, ctx->picinfo.buf_h, 420 ctx->picinfo.pic_w, ctx->picinfo.pic_h, 421 q_data->sizeimage[0], q_data->sizeimage[1]); 422 423 return ret; 424 } 425 426 static int mtk_vdec_s_ctrl(struct v4l2_ctrl *ctrl) 427 { 428 struct mtk_vcodec_dec_ctx *ctx = ctrl_to_dec_ctx(ctrl); 429 struct v4l2_ctrl_h264_sps *h264; 430 struct v4l2_ctrl_hevc_sps *h265; 431 struct v4l2_ctrl_vp9_frame *frame; 432 struct v4l2_ctrl_av1_sequence *seq; 433 struct v4l2_ctrl *hdr_ctrl; 434 const struct mtk_vcodec_dec_pdata *dec_pdata = ctx->dev->vdec_pdata; 435 const struct mtk_video_fmt *fmt; 436 int i = 0, ret = 0; 437 438 hdr_ctrl = ctrl; 439 if (!hdr_ctrl || !hdr_ctrl->p_new.p) 440 return -EINVAL; 441 442 switch (hdr_ctrl->id) { 443 case V4L2_CID_STATELESS_H264_SPS: 444 h264 = (struct v4l2_ctrl_h264_sps *)hdr_ctrl->p_new.p; 445 446 if (h264->bit_depth_chroma_minus8 == 2 && h264->bit_depth_luma_minus8 == 2) { 447 ctx->is_10bit_bitstream = true; 448 } else if (h264->bit_depth_chroma_minus8 != 0 && 449 h264->bit_depth_luma_minus8 != 0) { 450 mtk_v4l2_vdec_err(ctx, "H264: chroma_minus8:%d, luma_minus8:%d", 451 h264->bit_depth_chroma_minus8, 452 h264->bit_depth_luma_minus8); 453 return -EINVAL; 454 } 455 break; 456 case V4L2_CID_STATELESS_HEVC_SPS: 457 h265 = (struct v4l2_ctrl_hevc_sps *)hdr_ctrl->p_new.p; 458 459 if (h265->bit_depth_chroma_minus8 == 2 && h265->bit_depth_luma_minus8 == 2) { 460 ctx->is_10bit_bitstream = true; 461 } else if (h265->bit_depth_chroma_minus8 != 0 && 462 h265->bit_depth_luma_minus8 != 0) { 463 mtk_v4l2_vdec_err(ctx, "HEVC: chroma_minus8:%d, luma_minus8:%d", 464 h265->bit_depth_chroma_minus8, 465 h265->bit_depth_luma_minus8); 466 return -EINVAL; 467 } 468 break; 469 case V4L2_CID_STATELESS_VP9_FRAME: 470 frame = (struct v4l2_ctrl_vp9_frame *)hdr_ctrl->p_new.p; 471 472 if (frame->bit_depth == 10) { 473 ctx->is_10bit_bitstream = true; 474 } else if (frame->bit_depth != 8) { 475 mtk_v4l2_vdec_err(ctx, "VP9: bit_depth:%d", frame->bit_depth); 476 return -EINVAL; 477 } 478 break; 479 case V4L2_CID_STATELESS_AV1_SEQUENCE: 480 seq = (struct v4l2_ctrl_av1_sequence *)hdr_ctrl->p_new.p; 481 482 if (seq->bit_depth == 10) { 483 ctx->is_10bit_bitstream = true; 484 } else if (seq->bit_depth != 8) { 485 mtk_v4l2_vdec_err(ctx, "AV1: bit_depth:%d", seq->bit_depth); 486 return -EINVAL; 487 } 488 break; 489 default: 490 mtk_v4l2_vdec_dbg(3, ctx, "Not supported to set ctrl id: 0x%x\n", hdr_ctrl->id); 491 return ret; 492 } 493 494 if (!ctx->is_10bit_bitstream) 495 return ret; 496 497 for (i = 0; i < *dec_pdata->num_formats; i++) { 498 fmt = &dec_pdata->vdec_formats[i]; 499 if (fmt->fourcc == V4L2_PIX_FMT_MT2110R && 500 hdr_ctrl->id == V4L2_CID_STATELESS_H264_SPS) { 501 ctx->q_data[MTK_Q_DATA_DST].fmt = fmt; 502 break; 503 } 504 505 if (fmt->fourcc == V4L2_PIX_FMT_MT2110T && 506 (hdr_ctrl->id == V4L2_CID_STATELESS_HEVC_SPS || 507 hdr_ctrl->id == V4L2_CID_STATELESS_VP9_FRAME || 508 hdr_ctrl->id == V4L2_CID_STATELESS_AV1_SEQUENCE)) { 509 ctx->q_data[MTK_Q_DATA_DST].fmt = fmt; 510 break; 511 } 512 } 513 ret = mtk_vcodec_get_pic_info(ctx); 514 515 return ret; 516 } 517 518 static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = { 519 .s_ctrl = mtk_vdec_s_ctrl, 520 }; 521 522 static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx) 523 { 524 unsigned int i; 525 526 v4l2_ctrl_handler_init(&ctx->ctrl_hdl, NUM_CTRLS); 527 if (ctx->ctrl_hdl.error) { 528 mtk_v4l2_vdec_err(ctx, "v4l2_ctrl_handler_init failed\n"); 529 return ctx->ctrl_hdl.error; 530 } 531 532 for (i = 0; i < NUM_CTRLS; i++) { 533 struct v4l2_ctrl_config cfg = mtk_stateless_controls[i].cfg; 534 cfg.ops = &mtk_vcodec_dec_ctrl_ops; 535 v4l2_ctrl_new_custom(&ctx->ctrl_hdl, &cfg, NULL); 536 if (ctx->ctrl_hdl.error) { 537 mtk_v4l2_vdec_err(ctx, "Adding control %d failed %d", i, 538 ctx->ctrl_hdl.error); 539 return ctx->ctrl_hdl.error; 540 } 541 } 542 543 v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); 544 545 return 0; 546 } 547 548 static int fops_media_request_validate(struct media_request *mreq) 549 { 550 const unsigned int buffer_cnt = vb2_request_buffer_cnt(mreq); 551 552 switch (buffer_cnt) { 553 case 1: 554 /* We expect exactly one buffer with the request */ 555 break; 556 case 0: 557 pr_debug(MTK_DBG_VCODEC_STR "No buffer provided with the request."); 558 return -ENOENT; 559 default: 560 pr_debug(MTK_DBG_VCODEC_STR "Too many buffers (%d) provided with the request.", 561 buffer_cnt); 562 return -EINVAL; 563 } 564 565 return vb2_request_validate(mreq); 566 } 567 568 const struct media_device_ops mtk_vcodec_media_ops = { 569 .req_validate = fops_media_request_validate, 570 .req_queue = v4l2_m2m_request_queue, 571 }; 572 573 static void mtk_vcodec_add_formats(unsigned int fourcc, 574 struct mtk_vcodec_dec_ctx *ctx) 575 { 576 struct mtk_vcodec_dec_dev *dev = ctx->dev; 577 const struct mtk_vcodec_dec_pdata *pdata = dev->vdec_pdata; 578 int count_formats = *pdata->num_formats; 579 580 switch (fourcc) { 581 case V4L2_PIX_FMT_H264_SLICE: 582 case V4L2_PIX_FMT_VP8_FRAME: 583 case V4L2_PIX_FMT_VP9_FRAME: 584 case V4L2_PIX_FMT_HEVC_SLICE: 585 case V4L2_PIX_FMT_AV1_FRAME: 586 mtk_video_formats[count_formats].fourcc = fourcc; 587 mtk_video_formats[count_formats].type = MTK_FMT_DEC; 588 mtk_video_formats[count_formats].num_planes = 1; 589 mtk_video_formats[count_formats].frmsize = stepwise_fhd; 590 591 if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED) && 592 fourcc != V4L2_PIX_FMT_VP8_FRAME) { 593 mtk_video_formats[count_formats].frmsize.max_width = 594 VCODEC_DEC_4K_CODED_WIDTH; 595 mtk_video_formats[count_formats].frmsize.max_height = 596 VCODEC_DEC_4K_CODED_HEIGHT; 597 } 598 break; 599 case V4L2_PIX_FMT_MM21: 600 case V4L2_PIX_FMT_MT21C: 601 case V4L2_PIX_FMT_MT2110T: 602 case V4L2_PIX_FMT_MT2110R: 603 mtk_video_formats[count_formats].fourcc = fourcc; 604 mtk_video_formats[count_formats].type = MTK_FMT_FRAME; 605 mtk_video_formats[count_formats].num_planes = 2; 606 break; 607 default: 608 mtk_v4l2_vdec_err(ctx, "Can not add unsupported format type"); 609 return; 610 } 611 612 num_formats++; 613 mtk_v4l2_vdec_dbg(3, ctx, "num_formats: %d dec_capability: 0x%x", 614 count_formats, ctx->dev->dec_capability); 615 } 616 617 static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_dec_ctx *ctx) 618 { 619 int cap_format_count = 0, out_format_count = 0; 620 621 if (num_formats) 622 return; 623 624 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MT21C) { 625 mtk_vcodec_add_formats(V4L2_PIX_FMT_MT21C, ctx); 626 cap_format_count++; 627 } 628 if (ctx->dev->dec_capability & MTK_VDEC_IS_SUPPORT_10BIT) { 629 mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110T, ctx); 630 cap_format_count++; 631 mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110R, ctx); 632 cap_format_count++; 633 } 634 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MM21) { 635 mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx); 636 cap_format_count++; 637 } 638 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_H264_SLICE) { 639 mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx); 640 out_format_count++; 641 } 642 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP8_FRAME) { 643 mtk_vcodec_add_formats(V4L2_PIX_FMT_VP8_FRAME, ctx); 644 out_format_count++; 645 } 646 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP9_FRAME) { 647 mtk_vcodec_add_formats(V4L2_PIX_FMT_VP9_FRAME, ctx); 648 out_format_count++; 649 } 650 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_HEVC_FRAME) { 651 mtk_vcodec_add_formats(V4L2_PIX_FMT_HEVC_SLICE, ctx); 652 out_format_count++; 653 } 654 if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_AV1_FRAME) { 655 mtk_vcodec_add_formats(V4L2_PIX_FMT_AV1_FRAME, ctx); 656 out_format_count++; 657 } 658 659 if (cap_format_count) 660 default_cap_format = mtk_video_formats[cap_format_count - 1]; 661 if (out_format_count) 662 default_out_format = 663 mtk_video_formats[cap_format_count + out_format_count - 1]; 664 } 665 666 static void mtk_init_vdec_params(struct mtk_vcodec_dec_ctx *ctx) 667 { 668 struct vb2_queue *src_vq; 669 670 src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx, 671 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 672 673 if (!ctx->dev->vdec_pdata->is_subdev_supported) 674 ctx->dev->dec_capability |= 675 MTK_VDEC_FORMAT_H264_SLICE | MTK_VDEC_FORMAT_MM21; 676 mtk_vcodec_get_supported_formats(ctx); 677 678 /* Support request api for output plane */ 679 src_vq->supports_requests = true; 680 src_vq->requires_requests = true; 681 } 682 683 static int vb2ops_vdec_out_buf_validate(struct vb2_buffer *vb) 684 { 685 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 686 687 vbuf->field = V4L2_FIELD_NONE; 688 return 0; 689 } 690 691 static struct vb2_ops mtk_vdec_request_vb2_ops = { 692 .queue_setup = vb2ops_vdec_queue_setup, 693 .wait_prepare = vb2_ops_wait_prepare, 694 .wait_finish = vb2_ops_wait_finish, 695 .start_streaming = vb2ops_vdec_start_streaming, 696 .stop_streaming = vb2ops_vdec_stop_streaming, 697 698 .buf_queue = vb2ops_vdec_stateless_buf_queue, 699 .buf_out_validate = vb2ops_vdec_out_buf_validate, 700 .buf_init = vb2ops_vdec_buf_init, 701 .buf_prepare = vb2ops_vdec_buf_prepare, 702 .buf_finish = vb2ops_vdec_buf_finish, 703 .buf_request_complete = vb2ops_vdec_buf_request_complete, 704 }; 705 706 const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = { 707 .init_vdec_params = mtk_init_vdec_params, 708 .ctrls_setup = mtk_vcodec_dec_ctrls_setup, 709 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops, 710 .vdec_formats = mtk_video_formats, 711 .num_formats = &num_formats, 712 .default_out_fmt = &default_out_format, 713 .default_cap_fmt = &default_cap_format, 714 .uses_stateless_api = true, 715 .worker = mtk_vdec_worker, 716 .flush_decoder = mtk_vdec_flush_decoder, 717 .cap_to_disp = mtk_vdec_stateless_cap_to_disp, 718 .get_cap_buffer = vdec_get_cap_buffer, 719 .is_subdev_supported = false, 720 .hw_arch = MTK_VDEC_PURE_SINGLE_CORE, 721 }; 722 723 /* This platform data is used for one lat and one core architecture. */ 724 const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata = { 725 .init_vdec_params = mtk_init_vdec_params, 726 .ctrls_setup = mtk_vcodec_dec_ctrls_setup, 727 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops, 728 .vdec_formats = mtk_video_formats, 729 .num_formats = &num_formats, 730 .default_out_fmt = &default_out_format, 731 .default_cap_fmt = &default_cap_format, 732 .uses_stateless_api = true, 733 .worker = mtk_vdec_worker, 734 .flush_decoder = mtk_vdec_flush_decoder, 735 .cap_to_disp = mtk_vdec_stateless_cap_to_disp, 736 .get_cap_buffer = vdec_get_cap_buffer, 737 .is_subdev_supported = true, 738 .hw_arch = MTK_VDEC_LAT_SINGLE_CORE, 739 }; 740 741 const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = { 742 .init_vdec_params = mtk_init_vdec_params, 743 .ctrls_setup = mtk_vcodec_dec_ctrls_setup, 744 .vdec_vb2_ops = &mtk_vdec_request_vb2_ops, 745 .vdec_formats = mtk_video_formats, 746 .num_formats = &num_formats, 747 .default_out_fmt = &default_out_format, 748 .default_cap_fmt = &default_cap_format, 749 .uses_stateless_api = true, 750 .worker = mtk_vdec_worker, 751 .flush_decoder = mtk_vdec_flush_decoder, 752 .cap_to_disp = mtk_vdec_stateless_cap_to_disp, 753 .get_cap_buffer = vdec_get_cap_buffer, 754 .is_subdev_supported = true, 755 .hw_arch = MTK_VDEC_PURE_SINGLE_CORE, 756 }; 757