1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Renesas R-Car Fine Display Processor 4 * 5 * Video format converter and frame deinterlacer device. 6 * 7 * Author: Kieran Bingham, <kieran@bingham.xyz> 8 * Copyright (c) 2016 Renesas Electronics Corporation. 9 * 10 * This code is developed and inspired from the vim2m, rcar_jpu, 11 * m2m-deinterlace, and vsp1 drivers. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/fs.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/sched.h> 25 #include <linux/slab.h> 26 #include <linux/timer.h> 27 #include <media/rcar-fcp.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-event.h> 31 #include <media/v4l2-ioctl.h> 32 #include <media/v4l2-mem2mem.h> 33 #include <media/videobuf2-dma-contig.h> 34 35 static unsigned int debug; 36 module_param(debug, uint, 0644); 37 MODULE_PARM_DESC(debug, "activate debug info"); 38 39 /* Minimum and maximum frame width/height */ 40 #define FDP1_MIN_W 80U 41 #define FDP1_MIN_H 80U 42 43 #define FDP1_MAX_W 3840U 44 #define FDP1_MAX_H 2160U 45 46 #define FDP1_MAX_PLANES 3U 47 #define FDP1_MAX_STRIDE 8190U 48 49 /* Flags that indicate a format can be used for capture/output */ 50 #define FDP1_CAPTURE BIT(0) 51 #define FDP1_OUTPUT BIT(1) 52 53 #define DRIVER_NAME "rcar_fdp1" 54 55 /* Number of Job's to have available on the processing queue */ 56 #define FDP1_NUMBER_JOBS 8 57 58 #define dprintk(fdp1, fmt, arg...) \ 59 v4l2_dbg(1, debug, &fdp1->v4l2_dev, "%s: " fmt, __func__, ## arg) 60 61 /* 62 * FDP1 registers and bits 63 */ 64 65 /* FDP1 start register - Imm */ 66 #define FD1_CTL_CMD 0x0000 67 #define FD1_CTL_CMD_STRCMD BIT(0) 68 69 /* Sync generator register - Imm */ 70 #define FD1_CTL_SGCMD 0x0004 71 #define FD1_CTL_SGCMD_SGEN BIT(0) 72 73 /* Register set end register - Imm */ 74 #define FD1_CTL_REGEND 0x0008 75 #define FD1_CTL_REGEND_REGEND BIT(0) 76 77 /* Channel activation register - Vupdt */ 78 #define FD1_CTL_CHACT 0x000c 79 #define FD1_CTL_CHACT_SMW BIT(9) 80 #define FD1_CTL_CHACT_WR BIT(8) 81 #define FD1_CTL_CHACT_SMR BIT(3) 82 #define FD1_CTL_CHACT_RD2 BIT(2) 83 #define FD1_CTL_CHACT_RD1 BIT(1) 84 #define FD1_CTL_CHACT_RD0 BIT(0) 85 86 /* Operation Mode Register - Vupdt */ 87 #define FD1_CTL_OPMODE 0x0010 88 #define FD1_CTL_OPMODE_PRG BIT(4) 89 #define FD1_CTL_OPMODE_VIMD_INTERRUPT (0 << 0) 90 #define FD1_CTL_OPMODE_VIMD_BESTEFFORT (1 << 0) 91 #define FD1_CTL_OPMODE_VIMD_NOINTERRUPT (2 << 0) 92 93 #define FD1_CTL_VPERIOD 0x0014 94 #define FD1_CTL_CLKCTRL 0x0018 95 #define FD1_CTL_CLKCTRL_CSTP_N BIT(0) 96 97 /* Software reset register */ 98 #define FD1_CTL_SRESET 0x001c 99 #define FD1_CTL_SRESET_SRST BIT(0) 100 101 /* Control status register (V-update-status) */ 102 #define FD1_CTL_STATUS 0x0024 103 #define FD1_CTL_STATUS_VINT_CNT_MASK GENMASK(31, 16) 104 #define FD1_CTL_STATUS_VINT_CNT_SHIFT 16 105 #define FD1_CTL_STATUS_SGREGSET BIT(10) 106 #define FD1_CTL_STATUS_SGVERR BIT(9) 107 #define FD1_CTL_STATUS_SGFREND BIT(8) 108 #define FD1_CTL_STATUS_BSY BIT(0) 109 110 #define FD1_CTL_VCYCLE_STAT 0x0028 111 112 /* Interrupt enable register */ 113 #define FD1_CTL_IRQENB 0x0038 114 /* Interrupt status register */ 115 #define FD1_CTL_IRQSTA 0x003c 116 /* Interrupt control register */ 117 #define FD1_CTL_IRQFSET 0x0040 118 119 /* Common IRQ Bit settings */ 120 #define FD1_CTL_IRQ_VERE BIT(16) 121 #define FD1_CTL_IRQ_VINTE BIT(4) 122 #define FD1_CTL_IRQ_FREE BIT(0) 123 #define FD1_CTL_IRQ_MASK (FD1_CTL_IRQ_VERE | \ 124 FD1_CTL_IRQ_VINTE | \ 125 FD1_CTL_IRQ_FREE) 126 127 /* RPF */ 128 #define FD1_RPF_SIZE 0x0060 129 #define FD1_RPF_SIZE_MASK GENMASK(12, 0) 130 #define FD1_RPF_SIZE_H_SHIFT 16 131 #define FD1_RPF_SIZE_V_SHIFT 0 132 133 #define FD1_RPF_FORMAT 0x0064 134 #define FD1_RPF_FORMAT_CIPM BIT(16) 135 #define FD1_RPF_FORMAT_RSPYCS BIT(13) 136 #define FD1_RPF_FORMAT_RSPUVS BIT(12) 137 #define FD1_RPF_FORMAT_CF BIT(8) 138 139 #define FD1_RPF_PSTRIDE 0x0068 140 #define FD1_RPF_PSTRIDE_Y_SHIFT 16 141 #define FD1_RPF_PSTRIDE_C_SHIFT 0 142 143 /* RPF0 Source Component Y Address register */ 144 #define FD1_RPF0_ADDR_Y 0x006c 145 146 /* RPF1 Current Picture Registers */ 147 #define FD1_RPF1_ADDR_Y 0x0078 148 #define FD1_RPF1_ADDR_C0 0x007c 149 #define FD1_RPF1_ADDR_C1 0x0080 150 151 /* RPF2 next picture register */ 152 #define FD1_RPF2_ADDR_Y 0x0084 153 154 #define FD1_RPF_SMSK_ADDR 0x0090 155 #define FD1_RPF_SWAP 0x0094 156 157 /* WPF */ 158 #define FD1_WPF_FORMAT 0x00c0 159 #define FD1_WPF_FORMAT_PDV_SHIFT 24 160 #define FD1_WPF_FORMAT_FCNL BIT(20) 161 #define FD1_WPF_FORMAT_WSPYCS BIT(15) 162 #define FD1_WPF_FORMAT_WSPUVS BIT(14) 163 #define FD1_WPF_FORMAT_WRTM_601_16 (0 << 9) 164 #define FD1_WPF_FORMAT_WRTM_601_0 (1 << 9) 165 #define FD1_WPF_FORMAT_WRTM_709_16 (2 << 9) 166 #define FD1_WPF_FORMAT_CSC BIT(8) 167 168 #define FD1_WPF_RNDCTL 0x00c4 169 #define FD1_WPF_RNDCTL_CBRM BIT(28) 170 #define FD1_WPF_RNDCTL_CLMD_NOCLIP (0 << 12) 171 #define FD1_WPF_RNDCTL_CLMD_CLIP_16_235 (1 << 12) 172 #define FD1_WPF_RNDCTL_CLMD_CLIP_1_254 (2 << 12) 173 174 #define FD1_WPF_PSTRIDE 0x00c8 175 #define FD1_WPF_PSTRIDE_Y_SHIFT 16 176 #define FD1_WPF_PSTRIDE_C_SHIFT 0 177 178 /* WPF Destination picture */ 179 #define FD1_WPF_ADDR_Y 0x00cc 180 #define FD1_WPF_ADDR_C0 0x00d0 181 #define FD1_WPF_ADDR_C1 0x00d4 182 #define FD1_WPF_SWAP 0x00d8 183 #define FD1_WPF_SWAP_OSWAP_SHIFT 0 184 #define FD1_WPF_SWAP_SSWAP_SHIFT 4 185 186 /* WPF/RPF Common */ 187 #define FD1_RWPF_SWAP_BYTE BIT(0) 188 #define FD1_RWPF_SWAP_WORD BIT(1) 189 #define FD1_RWPF_SWAP_LWRD BIT(2) 190 #define FD1_RWPF_SWAP_LLWD BIT(3) 191 192 /* IPC */ 193 #define FD1_IPC_MODE 0x0100 194 #define FD1_IPC_MODE_DLI BIT(8) 195 #define FD1_IPC_MODE_DIM_ADAPT2D3D (0 << 0) 196 #define FD1_IPC_MODE_DIM_FIXED2D (1 << 0) 197 #define FD1_IPC_MODE_DIM_FIXED3D (2 << 0) 198 #define FD1_IPC_MODE_DIM_PREVFIELD (3 << 0) 199 #define FD1_IPC_MODE_DIM_NEXTFIELD (4 << 0) 200 201 #define FD1_IPC_SMSK_THRESH 0x0104 202 #define FD1_IPC_SMSK_THRESH_CONST 0x00010002 203 204 #define FD1_IPC_COMB_DET 0x0108 205 #define FD1_IPC_COMB_DET_CONST 0x00200040 206 207 #define FD1_IPC_MOTDEC 0x010c 208 #define FD1_IPC_MOTDEC_CONST 0x00008020 209 210 /* DLI registers */ 211 #define FD1_IPC_DLI_BLEND 0x0120 212 #define FD1_IPC_DLI_BLEND_CONST 0x0080ff02 213 214 #define FD1_IPC_DLI_HGAIN 0x0124 215 #define FD1_IPC_DLI_HGAIN_CONST 0x001000ff 216 217 #define FD1_IPC_DLI_SPRS 0x0128 218 #define FD1_IPC_DLI_SPRS_CONST 0x009004ff 219 220 #define FD1_IPC_DLI_ANGLE 0x012c 221 #define FD1_IPC_DLI_ANGLE_CONST 0x0004080c 222 223 #define FD1_IPC_DLI_ISOPIX0 0x0130 224 #define FD1_IPC_DLI_ISOPIX0_CONST 0xff10ff10 225 226 #define FD1_IPC_DLI_ISOPIX1 0x0134 227 #define FD1_IPC_DLI_ISOPIX1_CONST 0x0000ff10 228 229 /* Sensor registers */ 230 #define FD1_IPC_SENSOR_TH0 0x0140 231 #define FD1_IPC_SENSOR_TH0_CONST 0x20208080 232 233 #define FD1_IPC_SENSOR_TH1 0x0144 234 #define FD1_IPC_SENSOR_TH1_CONST 0 235 236 #define FD1_IPC_SENSOR_CTL0 0x0170 237 #define FD1_IPC_SENSOR_CTL0_CONST 0x00002201 238 239 #define FD1_IPC_SENSOR_CTL1 0x0174 240 #define FD1_IPC_SENSOR_CTL1_CONST 0 241 242 #define FD1_IPC_SENSOR_CTL2 0x0178 243 #define FD1_IPC_SENSOR_CTL2_X_SHIFT 16 244 #define FD1_IPC_SENSOR_CTL2_Y_SHIFT 0 245 246 #define FD1_IPC_SENSOR_CTL3 0x017c 247 #define FD1_IPC_SENSOR_CTL3_0_SHIFT 16 248 #define FD1_IPC_SENSOR_CTL3_1_SHIFT 0 249 250 /* Line memory pixel number register */ 251 #define FD1_IPC_LMEM 0x01e0 252 #define FD1_IPC_LMEM_LINEAR 1024 253 #define FD1_IPC_LMEM_TILE 960 254 255 /* Internal Data (HW Version) */ 256 #define FD1_IP_INTDATA 0x0800 257 #define FD1_IP_M3W 0x02010202 258 #define FD1_IP_H3 0x02010203 259 #define FD1_IP_M3N 0x02010204 260 #define FD1_IP_E3 0x02010205 261 262 /* LUTs */ 263 #define FD1_LUT_DIF_ADJ 0x1000 264 #define FD1_LUT_SAD_ADJ 0x1400 265 #define FD1_LUT_BLD_GAIN 0x1800 266 #define FD1_LUT_DIF_GAIN 0x1c00 267 #define FD1_LUT_MDET 0x2000 268 269 /** 270 * struct fdp1_fmt - The FDP1 internal format data 271 * @fourcc: the fourcc code, to match the V4L2 API 272 * @bpp: bits per pixel per plane 273 * @num_planes: number of planes 274 * @hsub: horizontal subsampling factor 275 * @vsub: vertical subsampling factor 276 * @fmt: 7-bit format code for the fdp1 hardware 277 * @swap_yc: the Y and C components are swapped (Y comes before C) 278 * @swap_uv: the U and V components are swapped (V comes before U) 279 * @swap: swap register control 280 * @types: types of queue this format is applicable to 281 */ 282 struct fdp1_fmt { 283 u32 fourcc; 284 u8 bpp[3]; 285 u8 num_planes; 286 u8 hsub; 287 u8 vsub; 288 u8 fmt; 289 bool swap_yc; 290 bool swap_uv; 291 u8 swap; 292 u8 types; 293 }; 294 295 static const struct fdp1_fmt fdp1_formats[] = { 296 /* RGB formats are only supported by the Write Pixel Formatter */ 297 298 { V4L2_PIX_FMT_RGB332, { 8, 0, 0 }, 1, 1, 1, 0x00, false, false, 299 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 300 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 301 FDP1_CAPTURE }, 302 { V4L2_PIX_FMT_XRGB444, { 16, 0, 0 }, 1, 1, 1, 0x01, false, false, 303 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 304 FD1_RWPF_SWAP_WORD, 305 FDP1_CAPTURE }, 306 { V4L2_PIX_FMT_XRGB555, { 16, 0, 0 }, 1, 1, 1, 0x04, false, false, 307 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 308 FD1_RWPF_SWAP_WORD, 309 FDP1_CAPTURE }, 310 { V4L2_PIX_FMT_RGB565, { 16, 0, 0 }, 1, 1, 1, 0x06, false, false, 311 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 312 FD1_RWPF_SWAP_WORD, 313 FDP1_CAPTURE }, 314 { V4L2_PIX_FMT_ABGR32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false, 315 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD, 316 FDP1_CAPTURE }, 317 { V4L2_PIX_FMT_XBGR32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false, 318 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD, 319 FDP1_CAPTURE }, 320 { V4L2_PIX_FMT_ARGB32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false, 321 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 322 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 323 FDP1_CAPTURE }, 324 { V4L2_PIX_FMT_XRGB32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false, 325 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 326 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 327 FDP1_CAPTURE }, 328 { V4L2_PIX_FMT_RGB24, { 24, 0, 0 }, 1, 1, 1, 0x15, false, false, 329 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 330 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 331 FDP1_CAPTURE }, 332 { V4L2_PIX_FMT_BGR24, { 24, 0, 0 }, 1, 1, 1, 0x18, false, false, 333 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 334 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 335 FDP1_CAPTURE }, 336 { V4L2_PIX_FMT_ARGB444, { 16, 0, 0 }, 1, 1, 1, 0x19, false, false, 337 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 338 FD1_RWPF_SWAP_WORD, 339 FDP1_CAPTURE }, 340 { V4L2_PIX_FMT_ARGB555, { 16, 0, 0 }, 1, 1, 1, 0x1b, false, false, 341 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 342 FD1_RWPF_SWAP_WORD, 343 FDP1_CAPTURE }, 344 345 /* YUV Formats are supported by Read and Write Pixel Formatters */ 346 347 { V4L2_PIX_FMT_NV16M, { 8, 16, 0 }, 2, 2, 1, 0x41, false, false, 348 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 349 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 350 FDP1_CAPTURE | FDP1_OUTPUT }, 351 { V4L2_PIX_FMT_NV61M, { 8, 16, 0 }, 2, 2, 1, 0x41, false, true, 352 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 353 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 354 FDP1_CAPTURE | FDP1_OUTPUT }, 355 { V4L2_PIX_FMT_NV12M, { 8, 16, 0 }, 2, 2, 2, 0x42, false, false, 356 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 357 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 358 FDP1_CAPTURE | FDP1_OUTPUT }, 359 { V4L2_PIX_FMT_NV21M, { 8, 16, 0 }, 2, 2, 2, 0x42, false, true, 360 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 361 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 362 FDP1_CAPTURE | FDP1_OUTPUT }, 363 { V4L2_PIX_FMT_UYVY, { 16, 0, 0 }, 1, 2, 1, 0x47, false, false, 364 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 365 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 366 FDP1_CAPTURE | FDP1_OUTPUT }, 367 { V4L2_PIX_FMT_VYUY, { 16, 0, 0 }, 1, 2, 1, 0x47, false, true, 368 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 369 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 370 FDP1_CAPTURE | FDP1_OUTPUT }, 371 { V4L2_PIX_FMT_YUYV, { 16, 0, 0 }, 1, 2, 1, 0x47, true, false, 372 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 373 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 374 FDP1_CAPTURE | FDP1_OUTPUT }, 375 { V4L2_PIX_FMT_YVYU, { 16, 0, 0 }, 1, 2, 1, 0x47, true, true, 376 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 377 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 378 FDP1_CAPTURE | FDP1_OUTPUT }, 379 { V4L2_PIX_FMT_YUV444M, { 8, 8, 8 }, 3, 1, 1, 0x4a, false, false, 380 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 381 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 382 FDP1_CAPTURE | FDP1_OUTPUT }, 383 { V4L2_PIX_FMT_YVU444M, { 8, 8, 8 }, 3, 1, 1, 0x4a, false, true, 384 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 385 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 386 FDP1_CAPTURE | FDP1_OUTPUT }, 387 { V4L2_PIX_FMT_YUV422M, { 8, 8, 8 }, 3, 2, 1, 0x4b, false, false, 388 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 389 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 390 FDP1_CAPTURE | FDP1_OUTPUT }, 391 { V4L2_PIX_FMT_YVU422M, { 8, 8, 8 }, 3, 2, 1, 0x4b, false, true, 392 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 393 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 394 FDP1_CAPTURE | FDP1_OUTPUT }, 395 { V4L2_PIX_FMT_YUV420M, { 8, 8, 8 }, 3, 2, 2, 0x4c, false, false, 396 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 397 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 398 FDP1_CAPTURE | FDP1_OUTPUT }, 399 { V4L2_PIX_FMT_YVU420M, { 8, 8, 8 }, 3, 2, 2, 0x4c, false, true, 400 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 401 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 402 FDP1_CAPTURE | FDP1_OUTPUT }, 403 }; 404 405 static int fdp1_fmt_is_rgb(const struct fdp1_fmt *fmt) 406 { 407 return fmt->fmt <= 0x1b; /* Last RGB code */ 408 } 409 410 /* 411 * FDP1 Lookup tables range from 0...255 only 412 * 413 * Each table must be less than 256 entries, and all tables 414 * are padded out to 256 entries by duplicating the last value. 415 */ 416 static const u8 fdp1_diff_adj[] = { 417 0x00, 0x24, 0x43, 0x5e, 0x76, 0x8c, 0x9e, 0xaf, 418 0xbd, 0xc9, 0xd4, 0xdd, 0xe4, 0xea, 0xef, 0xf3, 419 0xf6, 0xf9, 0xfb, 0xfc, 0xfd, 0xfe, 0xfe, 0xff, 420 }; 421 422 static const u8 fdp1_sad_adj[] = { 423 0x00, 0x24, 0x43, 0x5e, 0x76, 0x8c, 0x9e, 0xaf, 424 0xbd, 0xc9, 0xd4, 0xdd, 0xe4, 0xea, 0xef, 0xf3, 425 0xf6, 0xf9, 0xfb, 0xfc, 0xfd, 0xfe, 0xfe, 0xff, 426 }; 427 428 static const u8 fdp1_bld_gain[] = { 429 0x80, 430 }; 431 432 static const u8 fdp1_dif_gain[] = { 433 0x80, 434 }; 435 436 static const u8 fdp1_mdet[] = { 437 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 438 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 439 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 440 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 441 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 442 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 443 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 444 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 445 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 446 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 447 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 448 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 449 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 450 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 451 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 452 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 453 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 454 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 455 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 456 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 457 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 458 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 459 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 460 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 461 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 462 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 463 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 464 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 465 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 466 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 467 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 468 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff 469 }; 470 471 /* Per-queue, driver-specific private data */ 472 struct fdp1_q_data { 473 const struct fdp1_fmt *fmt; 474 struct v4l2_pix_format_mplane format; 475 476 unsigned int vsize; 477 unsigned int stride_y; 478 unsigned int stride_c; 479 }; 480 481 static const struct fdp1_fmt *fdp1_find_format(u32 pixelformat) 482 { 483 const struct fdp1_fmt *fmt; 484 unsigned int i; 485 486 for (i = 0; i < ARRAY_SIZE(fdp1_formats); i++) { 487 fmt = &fdp1_formats[i]; 488 if (fmt->fourcc == pixelformat) 489 return fmt; 490 } 491 492 return NULL; 493 } 494 495 enum fdp1_deint_mode { 496 FDP1_PROGRESSIVE = 0, /* Must be zero when !deinterlacing */ 497 FDP1_ADAPT2D3D, 498 FDP1_FIXED2D, 499 FDP1_FIXED3D, 500 FDP1_PREVFIELD, 501 FDP1_NEXTFIELD, 502 }; 503 504 #define FDP1_DEINT_MODE_USES_NEXT(mode) \ 505 (mode == FDP1_ADAPT2D3D || \ 506 mode == FDP1_FIXED3D || \ 507 mode == FDP1_NEXTFIELD) 508 509 #define FDP1_DEINT_MODE_USES_PREV(mode) \ 510 (mode == FDP1_ADAPT2D3D || \ 511 mode == FDP1_FIXED3D || \ 512 mode == FDP1_PREVFIELD) 513 514 /* 515 * FDP1 operates on potentially 3 fields, which are tracked 516 * from the VB buffers using this context structure. 517 * Will always be a field or a full frame, never two fields. 518 */ 519 struct fdp1_field_buffer { 520 struct vb2_v4l2_buffer *vb; 521 dma_addr_t addrs[3]; 522 523 /* Should be NONE:TOP:BOTTOM only */ 524 enum v4l2_field field; 525 526 /* Flag to indicate this is the last field in the vb */ 527 bool last_field; 528 529 /* Buffer queue lists */ 530 struct list_head list; 531 }; 532 533 struct fdp1_buffer { 534 struct v4l2_m2m_buffer m2m_buf; 535 struct fdp1_field_buffer fields[2]; 536 unsigned int num_fields; 537 }; 538 539 static inline struct fdp1_buffer *to_fdp1_buffer(struct vb2_v4l2_buffer *vb) 540 { 541 return container_of(vb, struct fdp1_buffer, m2m_buf.vb); 542 } 543 544 struct fdp1_job { 545 struct fdp1_field_buffer *previous; 546 struct fdp1_field_buffer *active; 547 struct fdp1_field_buffer *next; 548 struct fdp1_field_buffer *dst; 549 550 /* A job can only be on one list at a time */ 551 struct list_head list; 552 }; 553 554 struct fdp1_dev { 555 struct v4l2_device v4l2_dev; 556 struct video_device vfd; 557 558 struct mutex dev_mutex; 559 spinlock_t irqlock; 560 spinlock_t device_process_lock; 561 562 void __iomem *regs; 563 unsigned int irq; 564 struct device *dev; 565 566 /* Job Queues */ 567 struct fdp1_job jobs[FDP1_NUMBER_JOBS]; 568 struct list_head free_job_list; 569 struct list_head queued_job_list; 570 struct list_head hw_job_list; 571 572 unsigned int clk_rate; 573 574 struct rcar_fcp_device *fcp; 575 struct v4l2_m2m_dev *m2m_dev; 576 }; 577 578 struct fdp1_ctx { 579 struct v4l2_fh fh; 580 struct fdp1_dev *fdp1; 581 582 struct v4l2_ctrl_handler hdl; 583 unsigned int sequence; 584 585 /* Processed buffers in this transaction */ 586 u8 num_processed; 587 588 /* Transaction length (i.e. how many buffers per transaction) */ 589 u32 translen; 590 591 /* Abort requested by m2m */ 592 int aborting; 593 594 /* Deinterlace processing mode */ 595 enum fdp1_deint_mode deint_mode; 596 597 /* 598 * Adaptive 2D/3D mode uses a shared mask 599 * This is allocated at streamon, if the ADAPT2D3D mode 600 * is requested 601 */ 602 unsigned int smsk_size; 603 dma_addr_t smsk_addr[2]; 604 void *smsk_cpu; 605 606 /* Capture pipeline, can specify an alpha value 607 * for supported formats. 0-255 only 608 */ 609 unsigned char alpha; 610 611 /* Source and destination queue data */ 612 struct fdp1_q_data out_q; /* HW Source */ 613 struct fdp1_q_data cap_q; /* HW Destination */ 614 615 /* 616 * Field Queues 617 * Interlaced fields are used on 3 occasions, and tracked in this list. 618 * 619 * V4L2 Buffers are tracked inside the fdp1_buffer 620 * and released when the last 'field' completes 621 */ 622 struct list_head fields_queue; 623 unsigned int buffers_queued; 624 625 /* 626 * For de-interlacing we need to track our previous buffer 627 * while preparing our job lists. 628 */ 629 struct fdp1_field_buffer *previous; 630 }; 631 632 static inline struct fdp1_ctx *fh_to_ctx(struct v4l2_fh *fh) 633 { 634 return container_of(fh, struct fdp1_ctx, fh); 635 } 636 637 static struct fdp1_q_data *get_q_data(struct fdp1_ctx *ctx, 638 enum v4l2_buf_type type) 639 { 640 if (V4L2_TYPE_IS_OUTPUT(type)) 641 return &ctx->out_q; 642 else 643 return &ctx->cap_q; 644 } 645 646 /* 647 * list_remove_job: Take the first item off the specified job list 648 * 649 * Returns: pointer to a job, or NULL if the list is empty. 650 */ 651 static struct fdp1_job *list_remove_job(struct fdp1_dev *fdp1, 652 struct list_head *list) 653 { 654 struct fdp1_job *job; 655 unsigned long flags; 656 657 spin_lock_irqsave(&fdp1->irqlock, flags); 658 job = list_first_entry_or_null(list, struct fdp1_job, list); 659 if (job) 660 list_del(&job->list); 661 spin_unlock_irqrestore(&fdp1->irqlock, flags); 662 663 return job; 664 } 665 666 /* 667 * list_add_job: Add a job to the specified job list 668 * 669 * Returns: void - always succeeds 670 */ 671 static void list_add_job(struct fdp1_dev *fdp1, 672 struct list_head *list, 673 struct fdp1_job *job) 674 { 675 unsigned long flags; 676 677 spin_lock_irqsave(&fdp1->irqlock, flags); 678 list_add_tail(&job->list, list); 679 spin_unlock_irqrestore(&fdp1->irqlock, flags); 680 } 681 682 static struct fdp1_job *fdp1_job_alloc(struct fdp1_dev *fdp1) 683 { 684 return list_remove_job(fdp1, &fdp1->free_job_list); 685 } 686 687 static void fdp1_job_free(struct fdp1_dev *fdp1, struct fdp1_job *job) 688 { 689 /* Ensure that all residue from previous jobs is gone */ 690 memset(job, 0, sizeof(struct fdp1_job)); 691 692 list_add_job(fdp1, &fdp1->free_job_list, job); 693 } 694 695 static void queue_job(struct fdp1_dev *fdp1, struct fdp1_job *job) 696 { 697 list_add_job(fdp1, &fdp1->queued_job_list, job); 698 } 699 700 static struct fdp1_job *get_queued_job(struct fdp1_dev *fdp1) 701 { 702 return list_remove_job(fdp1, &fdp1->queued_job_list); 703 } 704 705 static void queue_hw_job(struct fdp1_dev *fdp1, struct fdp1_job *job) 706 { 707 list_add_job(fdp1, &fdp1->hw_job_list, job); 708 } 709 710 static struct fdp1_job *get_hw_queued_job(struct fdp1_dev *fdp1) 711 { 712 return list_remove_job(fdp1, &fdp1->hw_job_list); 713 } 714 715 /* 716 * Buffer lists handling 717 */ 718 static void fdp1_field_complete(struct fdp1_ctx *ctx, 719 struct fdp1_field_buffer *fbuf) 720 { 721 /* job->previous may be on the first field */ 722 if (!fbuf) 723 return; 724 725 if (fbuf->last_field) 726 v4l2_m2m_buf_done(fbuf->vb, VB2_BUF_STATE_DONE); 727 } 728 729 static void fdp1_queue_field(struct fdp1_ctx *ctx, 730 struct fdp1_field_buffer *fbuf) 731 { 732 unsigned long flags; 733 734 spin_lock_irqsave(&ctx->fdp1->irqlock, flags); 735 list_add_tail(&fbuf->list, &ctx->fields_queue); 736 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags); 737 738 ctx->buffers_queued++; 739 } 740 741 static struct fdp1_field_buffer *fdp1_dequeue_field(struct fdp1_ctx *ctx) 742 { 743 struct fdp1_field_buffer *fbuf; 744 unsigned long flags; 745 746 ctx->buffers_queued--; 747 748 spin_lock_irqsave(&ctx->fdp1->irqlock, flags); 749 fbuf = list_first_entry_or_null(&ctx->fields_queue, 750 struct fdp1_field_buffer, list); 751 if (fbuf) 752 list_del(&fbuf->list); 753 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags); 754 755 return fbuf; 756 } 757 758 /* 759 * Return the next field in the queue - or NULL, 760 * without removing the item from the list 761 */ 762 static struct fdp1_field_buffer *fdp1_peek_queued_field(struct fdp1_ctx *ctx) 763 { 764 struct fdp1_field_buffer *fbuf; 765 unsigned long flags; 766 767 spin_lock_irqsave(&ctx->fdp1->irqlock, flags); 768 fbuf = list_first_entry_or_null(&ctx->fields_queue, 769 struct fdp1_field_buffer, list); 770 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags); 771 772 return fbuf; 773 } 774 775 static u32 fdp1_read(struct fdp1_dev *fdp1, unsigned int reg) 776 { 777 u32 value = ioread32(fdp1->regs + reg); 778 779 if (debug >= 2) 780 dprintk(fdp1, "Read 0x%08x from 0x%04x\n", value, reg); 781 782 return value; 783 } 784 785 static void fdp1_write(struct fdp1_dev *fdp1, u32 val, unsigned int reg) 786 { 787 if (debug >= 2) 788 dprintk(fdp1, "Write 0x%08x to 0x%04x\n", val, reg); 789 790 iowrite32(val, fdp1->regs + reg); 791 } 792 793 /* IPC registers are to be programmed with constant values */ 794 static void fdp1_set_ipc_dli(struct fdp1_ctx *ctx) 795 { 796 struct fdp1_dev *fdp1 = ctx->fdp1; 797 798 fdp1_write(fdp1, FD1_IPC_SMSK_THRESH_CONST, FD1_IPC_SMSK_THRESH); 799 fdp1_write(fdp1, FD1_IPC_COMB_DET_CONST, FD1_IPC_COMB_DET); 800 fdp1_write(fdp1, FD1_IPC_MOTDEC_CONST, FD1_IPC_MOTDEC); 801 802 fdp1_write(fdp1, FD1_IPC_DLI_BLEND_CONST, FD1_IPC_DLI_BLEND); 803 fdp1_write(fdp1, FD1_IPC_DLI_HGAIN_CONST, FD1_IPC_DLI_HGAIN); 804 fdp1_write(fdp1, FD1_IPC_DLI_SPRS_CONST, FD1_IPC_DLI_SPRS); 805 fdp1_write(fdp1, FD1_IPC_DLI_ANGLE_CONST, FD1_IPC_DLI_ANGLE); 806 fdp1_write(fdp1, FD1_IPC_DLI_ISOPIX0_CONST, FD1_IPC_DLI_ISOPIX0); 807 fdp1_write(fdp1, FD1_IPC_DLI_ISOPIX1_CONST, FD1_IPC_DLI_ISOPIX1); 808 } 809 810 811 static void fdp1_set_ipc_sensor(struct fdp1_ctx *ctx) 812 { 813 struct fdp1_dev *fdp1 = ctx->fdp1; 814 struct fdp1_q_data *src_q_data = &ctx->out_q; 815 unsigned int x0, x1; 816 unsigned int hsize = src_q_data->format.width; 817 unsigned int vsize = src_q_data->format.height; 818 819 x0 = hsize / 3; 820 x1 = 2 * hsize / 3; 821 822 fdp1_write(fdp1, FD1_IPC_SENSOR_TH0_CONST, FD1_IPC_SENSOR_TH0); 823 fdp1_write(fdp1, FD1_IPC_SENSOR_TH1_CONST, FD1_IPC_SENSOR_TH1); 824 fdp1_write(fdp1, FD1_IPC_SENSOR_CTL0_CONST, FD1_IPC_SENSOR_CTL0); 825 fdp1_write(fdp1, FD1_IPC_SENSOR_CTL1_CONST, FD1_IPC_SENSOR_CTL1); 826 827 fdp1_write(fdp1, ((hsize - 1) << FD1_IPC_SENSOR_CTL2_X_SHIFT) | 828 ((vsize - 1) << FD1_IPC_SENSOR_CTL2_Y_SHIFT), 829 FD1_IPC_SENSOR_CTL2); 830 831 fdp1_write(fdp1, (x0 << FD1_IPC_SENSOR_CTL3_0_SHIFT) | 832 (x1 << FD1_IPC_SENSOR_CTL3_1_SHIFT), 833 FD1_IPC_SENSOR_CTL3); 834 } 835 836 /* 837 * fdp1_write_lut: Write a padded LUT to the hw 838 * 839 * FDP1 uses constant data for de-interlacing processing, 840 * with large tables. These hardware tables are all 256 bytes 841 * long, however they often contain repeated data at the end. 842 * 843 * The last byte of the table is written to all remaining entries. 844 */ 845 static void fdp1_write_lut(struct fdp1_dev *fdp1, const u8 *lut, 846 unsigned int len, unsigned int base) 847 { 848 unsigned int i; 849 u8 pad; 850 851 /* Tables larger than the hw are clipped */ 852 len = min(len, 256u); 853 854 for (i = 0; i < len; i++) 855 fdp1_write(fdp1, lut[i], base + (i*4)); 856 857 /* Tables are padded with the last entry */ 858 pad = lut[i-1]; 859 860 for (; i < 256; i++) 861 fdp1_write(fdp1, pad, base + (i*4)); 862 } 863 864 static void fdp1_set_lut(struct fdp1_dev *fdp1) 865 { 866 fdp1_write_lut(fdp1, fdp1_diff_adj, ARRAY_SIZE(fdp1_diff_adj), 867 FD1_LUT_DIF_ADJ); 868 fdp1_write_lut(fdp1, fdp1_sad_adj, ARRAY_SIZE(fdp1_sad_adj), 869 FD1_LUT_SAD_ADJ); 870 fdp1_write_lut(fdp1, fdp1_bld_gain, ARRAY_SIZE(fdp1_bld_gain), 871 FD1_LUT_BLD_GAIN); 872 fdp1_write_lut(fdp1, fdp1_dif_gain, ARRAY_SIZE(fdp1_dif_gain), 873 FD1_LUT_DIF_GAIN); 874 fdp1_write_lut(fdp1, fdp1_mdet, ARRAY_SIZE(fdp1_mdet), 875 FD1_LUT_MDET); 876 } 877 878 static void fdp1_configure_rpf(struct fdp1_ctx *ctx, 879 struct fdp1_job *job) 880 { 881 struct fdp1_dev *fdp1 = ctx->fdp1; 882 u32 picture_size; 883 u32 pstride; 884 u32 format; 885 u32 smsk_addr; 886 887 struct fdp1_q_data *q_data = &ctx->out_q; 888 889 /* Picture size is common to Source and Destination frames */ 890 picture_size = (q_data->format.width << FD1_RPF_SIZE_H_SHIFT) 891 | (q_data->vsize << FD1_RPF_SIZE_V_SHIFT); 892 893 /* Strides */ 894 pstride = q_data->stride_y << FD1_RPF_PSTRIDE_Y_SHIFT; 895 if (q_data->format.num_planes > 1) 896 pstride |= q_data->stride_c << FD1_RPF_PSTRIDE_C_SHIFT; 897 898 /* Format control */ 899 format = q_data->fmt->fmt; 900 if (q_data->fmt->swap_yc) 901 format |= FD1_RPF_FORMAT_RSPYCS; 902 903 if (q_data->fmt->swap_uv) 904 format |= FD1_RPF_FORMAT_RSPUVS; 905 906 if (job->active->field == V4L2_FIELD_BOTTOM) { 907 format |= FD1_RPF_FORMAT_CF; /* Set for Bottom field */ 908 smsk_addr = ctx->smsk_addr[0]; 909 } else { 910 smsk_addr = ctx->smsk_addr[1]; 911 } 912 913 /* Deint mode is non-zero when deinterlacing */ 914 if (ctx->deint_mode) 915 format |= FD1_RPF_FORMAT_CIPM; 916 917 fdp1_write(fdp1, format, FD1_RPF_FORMAT); 918 fdp1_write(fdp1, q_data->fmt->swap, FD1_RPF_SWAP); 919 fdp1_write(fdp1, picture_size, FD1_RPF_SIZE); 920 fdp1_write(fdp1, pstride, FD1_RPF_PSTRIDE); 921 fdp1_write(fdp1, smsk_addr, FD1_RPF_SMSK_ADDR); 922 923 /* Previous Field Channel (CH0) */ 924 if (job->previous) 925 fdp1_write(fdp1, job->previous->addrs[0], FD1_RPF0_ADDR_Y); 926 927 /* Current Field Channel (CH1) */ 928 fdp1_write(fdp1, job->active->addrs[0], FD1_RPF1_ADDR_Y); 929 fdp1_write(fdp1, job->active->addrs[1], FD1_RPF1_ADDR_C0); 930 fdp1_write(fdp1, job->active->addrs[2], FD1_RPF1_ADDR_C1); 931 932 /* Next Field Channel (CH2) */ 933 if (job->next) 934 fdp1_write(fdp1, job->next->addrs[0], FD1_RPF2_ADDR_Y); 935 } 936 937 static void fdp1_configure_wpf(struct fdp1_ctx *ctx, 938 struct fdp1_job *job) 939 { 940 struct fdp1_dev *fdp1 = ctx->fdp1; 941 struct fdp1_q_data *src_q_data = &ctx->out_q; 942 struct fdp1_q_data *q_data = &ctx->cap_q; 943 u32 pstride; 944 u32 format; 945 u32 swap; 946 u32 rndctl; 947 948 pstride = q_data->format.plane_fmt[0].bytesperline 949 << FD1_WPF_PSTRIDE_Y_SHIFT; 950 951 if (q_data->format.num_planes > 1) 952 pstride |= q_data->format.plane_fmt[1].bytesperline 953 << FD1_WPF_PSTRIDE_C_SHIFT; 954 955 format = q_data->fmt->fmt; /* Output Format Code */ 956 957 if (q_data->fmt->swap_yc) 958 format |= FD1_WPF_FORMAT_WSPYCS; 959 960 if (q_data->fmt->swap_uv) 961 format |= FD1_WPF_FORMAT_WSPUVS; 962 963 if (fdp1_fmt_is_rgb(q_data->fmt)) { 964 /* Enable Colour Space conversion */ 965 format |= FD1_WPF_FORMAT_CSC; 966 967 /* Set WRTM */ 968 if (src_q_data->format.ycbcr_enc == V4L2_YCBCR_ENC_709) 969 format |= FD1_WPF_FORMAT_WRTM_709_16; 970 else if (src_q_data->format.quantization == 971 V4L2_QUANTIZATION_FULL_RANGE) 972 format |= FD1_WPF_FORMAT_WRTM_601_0; 973 else 974 format |= FD1_WPF_FORMAT_WRTM_601_16; 975 } 976 977 /* Set an alpha value into the Pad Value */ 978 format |= ctx->alpha << FD1_WPF_FORMAT_PDV_SHIFT; 979 980 /* Determine picture rounding and clipping */ 981 rndctl = FD1_WPF_RNDCTL_CBRM; /* Rounding Off */ 982 rndctl |= FD1_WPF_RNDCTL_CLMD_NOCLIP; 983 984 /* WPF Swap needs both ISWAP and OSWAP setting */ 985 swap = q_data->fmt->swap << FD1_WPF_SWAP_OSWAP_SHIFT; 986 swap |= src_q_data->fmt->swap << FD1_WPF_SWAP_SSWAP_SHIFT; 987 988 fdp1_write(fdp1, format, FD1_WPF_FORMAT); 989 fdp1_write(fdp1, rndctl, FD1_WPF_RNDCTL); 990 fdp1_write(fdp1, swap, FD1_WPF_SWAP); 991 fdp1_write(fdp1, pstride, FD1_WPF_PSTRIDE); 992 993 fdp1_write(fdp1, job->dst->addrs[0], FD1_WPF_ADDR_Y); 994 fdp1_write(fdp1, job->dst->addrs[1], FD1_WPF_ADDR_C0); 995 fdp1_write(fdp1, job->dst->addrs[2], FD1_WPF_ADDR_C1); 996 } 997 998 static void fdp1_configure_deint_mode(struct fdp1_ctx *ctx, 999 struct fdp1_job *job) 1000 { 1001 struct fdp1_dev *fdp1 = ctx->fdp1; 1002 u32 opmode = FD1_CTL_OPMODE_VIMD_NOINTERRUPT; 1003 u32 ipcmode = FD1_IPC_MODE_DLI; /* Always set */ 1004 u32 channels = FD1_CTL_CHACT_WR | FD1_CTL_CHACT_RD1; /* Always on */ 1005 1006 /* De-interlacing Mode */ 1007 switch (ctx->deint_mode) { 1008 default: 1009 case FDP1_PROGRESSIVE: 1010 dprintk(fdp1, "Progressive Mode\n"); 1011 opmode |= FD1_CTL_OPMODE_PRG; 1012 ipcmode |= FD1_IPC_MODE_DIM_FIXED2D; 1013 break; 1014 case FDP1_ADAPT2D3D: 1015 dprintk(fdp1, "Adapt2D3D Mode\n"); 1016 if (ctx->sequence == 0 || ctx->aborting) 1017 ipcmode |= FD1_IPC_MODE_DIM_FIXED2D; 1018 else 1019 ipcmode |= FD1_IPC_MODE_DIM_ADAPT2D3D; 1020 1021 if (ctx->sequence > 1) { 1022 channels |= FD1_CTL_CHACT_SMW; 1023 channels |= FD1_CTL_CHACT_RD0 | FD1_CTL_CHACT_RD2; 1024 } 1025 1026 if (ctx->sequence > 2) 1027 channels |= FD1_CTL_CHACT_SMR; 1028 1029 break; 1030 case FDP1_FIXED3D: 1031 dprintk(fdp1, "Fixed 3D Mode\n"); 1032 ipcmode |= FD1_IPC_MODE_DIM_FIXED3D; 1033 /* Except for first and last frame, enable all channels */ 1034 if (!(ctx->sequence == 0 || ctx->aborting)) 1035 channels |= FD1_CTL_CHACT_RD0 | FD1_CTL_CHACT_RD2; 1036 break; 1037 case FDP1_FIXED2D: 1038 dprintk(fdp1, "Fixed 2D Mode\n"); 1039 ipcmode |= FD1_IPC_MODE_DIM_FIXED2D; 1040 /* No extra channels enabled */ 1041 break; 1042 case FDP1_PREVFIELD: 1043 dprintk(fdp1, "Previous Field Mode\n"); 1044 ipcmode |= FD1_IPC_MODE_DIM_PREVFIELD; 1045 channels |= FD1_CTL_CHACT_RD0; /* Previous */ 1046 break; 1047 case FDP1_NEXTFIELD: 1048 dprintk(fdp1, "Next Field Mode\n"); 1049 ipcmode |= FD1_IPC_MODE_DIM_NEXTFIELD; 1050 channels |= FD1_CTL_CHACT_RD2; /* Next */ 1051 break; 1052 } 1053 1054 fdp1_write(fdp1, channels, FD1_CTL_CHACT); 1055 fdp1_write(fdp1, opmode, FD1_CTL_OPMODE); 1056 fdp1_write(fdp1, ipcmode, FD1_IPC_MODE); 1057 } 1058 1059 /* 1060 * fdp1_device_process() - Run the hardware 1061 * 1062 * Configure and start the hardware to generate a single frame 1063 * of output given our input parameters. 1064 */ 1065 static int fdp1_device_process(struct fdp1_ctx *ctx) 1066 1067 { 1068 struct fdp1_dev *fdp1 = ctx->fdp1; 1069 struct fdp1_job *job; 1070 unsigned long flags; 1071 1072 spin_lock_irqsave(&fdp1->device_process_lock, flags); 1073 1074 /* Get a job to process */ 1075 job = get_queued_job(fdp1); 1076 if (!job) { 1077 /* 1078 * VINT can call us to see if we can queue another job. 1079 * If we have no work to do, we simply return. 1080 */ 1081 spin_unlock_irqrestore(&fdp1->device_process_lock, flags); 1082 return 0; 1083 } 1084 1085 /* First Frame only? ... */ 1086 fdp1_write(fdp1, FD1_CTL_CLKCTRL_CSTP_N, FD1_CTL_CLKCTRL); 1087 1088 /* Set the mode, and configuration */ 1089 fdp1_configure_deint_mode(ctx, job); 1090 1091 /* DLI Static Configuration */ 1092 fdp1_set_ipc_dli(ctx); 1093 1094 /* Sensor Configuration */ 1095 fdp1_set_ipc_sensor(ctx); 1096 1097 /* Setup the source picture */ 1098 fdp1_configure_rpf(ctx, job); 1099 1100 /* Setup the destination picture */ 1101 fdp1_configure_wpf(ctx, job); 1102 1103 /* Line Memory Pixel Number Register for linear access */ 1104 fdp1_write(fdp1, FD1_IPC_LMEM_LINEAR, FD1_IPC_LMEM); 1105 1106 /* Enable Interrupts */ 1107 fdp1_write(fdp1, FD1_CTL_IRQ_MASK, FD1_CTL_IRQENB); 1108 1109 /* Finally, the Immediate Registers */ 1110 1111 /* This job is now in the HW queue */ 1112 queue_hw_job(fdp1, job); 1113 1114 /* Start the command */ 1115 fdp1_write(fdp1, FD1_CTL_CMD_STRCMD, FD1_CTL_CMD); 1116 1117 /* Registers will update to HW at next VINT */ 1118 fdp1_write(fdp1, FD1_CTL_REGEND_REGEND, FD1_CTL_REGEND); 1119 1120 /* Enable VINT Generator */ 1121 fdp1_write(fdp1, FD1_CTL_SGCMD_SGEN, FD1_CTL_SGCMD); 1122 1123 spin_unlock_irqrestore(&fdp1->device_process_lock, flags); 1124 1125 return 0; 1126 } 1127 1128 /* 1129 * mem2mem callbacks 1130 */ 1131 1132 /* 1133 * job_ready() - check whether an instance is ready to be scheduled to run 1134 */ 1135 static int fdp1_m2m_job_ready(void *priv) 1136 { 1137 struct fdp1_ctx *ctx = priv; 1138 struct fdp1_q_data *src_q_data = &ctx->out_q; 1139 int srcbufs = 1; 1140 int dstbufs = 1; 1141 1142 dprintk(ctx->fdp1, "+ Src: %d : Dst: %d\n", 1143 v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx), 1144 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx)); 1145 1146 /* One output buffer is required for each field */ 1147 if (V4L2_FIELD_HAS_BOTH(src_q_data->format.field)) 1148 dstbufs = 2; 1149 1150 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < srcbufs 1151 || v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < dstbufs) { 1152 dprintk(ctx->fdp1, "Not enough buffers available\n"); 1153 return 0; 1154 } 1155 1156 return 1; 1157 } 1158 1159 static void fdp1_m2m_job_abort(void *priv) 1160 { 1161 struct fdp1_ctx *ctx = priv; 1162 1163 dprintk(ctx->fdp1, "+\n"); 1164 1165 /* Will cancel the transaction in the next interrupt handler */ 1166 ctx->aborting = 1; 1167 1168 /* Immediate abort sequence */ 1169 fdp1_write(ctx->fdp1, 0, FD1_CTL_SGCMD); 1170 fdp1_write(ctx->fdp1, FD1_CTL_SRESET_SRST, FD1_CTL_SRESET); 1171 } 1172 1173 /* 1174 * fdp1_prepare_job: Prepare and queue a new job for a single action of work 1175 * 1176 * Prepare the next field, (or frame in progressive) and an output 1177 * buffer for the hardware to perform a single operation. 1178 */ 1179 static struct fdp1_job *fdp1_prepare_job(struct fdp1_ctx *ctx) 1180 { 1181 struct vb2_v4l2_buffer *vbuf; 1182 struct fdp1_buffer *fbuf; 1183 struct fdp1_dev *fdp1 = ctx->fdp1; 1184 struct fdp1_job *job; 1185 unsigned int buffers_required = 1; 1186 1187 dprintk(fdp1, "+\n"); 1188 1189 if (FDP1_DEINT_MODE_USES_NEXT(ctx->deint_mode)) 1190 buffers_required = 2; 1191 1192 if (ctx->buffers_queued < buffers_required) 1193 return NULL; 1194 1195 job = fdp1_job_alloc(fdp1); 1196 if (!job) { 1197 dprintk(fdp1, "No free jobs currently available\n"); 1198 return NULL; 1199 } 1200 1201 job->active = fdp1_dequeue_field(ctx); 1202 if (!job->active) { 1203 /* Buffer check should prevent this ever happening */ 1204 dprintk(fdp1, "No input buffers currently available\n"); 1205 1206 fdp1_job_free(fdp1, job); 1207 return NULL; 1208 } 1209 1210 dprintk(fdp1, "+ Buffer en-route...\n"); 1211 1212 /* Source buffers have been prepared on our buffer_queue 1213 * Prepare our Output buffer 1214 */ 1215 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 1216 fbuf = to_fdp1_buffer(vbuf); 1217 job->dst = &fbuf->fields[0]; 1218 1219 job->active->vb->sequence = ctx->sequence; 1220 job->dst->vb->sequence = ctx->sequence; 1221 ctx->sequence++; 1222 1223 if (FDP1_DEINT_MODE_USES_PREV(ctx->deint_mode)) { 1224 job->previous = ctx->previous; 1225 1226 /* Active buffer becomes the next job's previous buffer */ 1227 ctx->previous = job->active; 1228 } 1229 1230 if (FDP1_DEINT_MODE_USES_NEXT(ctx->deint_mode)) { 1231 /* Must be called after 'active' is dequeued */ 1232 job->next = fdp1_peek_queued_field(ctx); 1233 } 1234 1235 /* Transfer timestamps and flags from src->dst */ 1236 1237 job->dst->vb->vb2_buf.timestamp = job->active->vb->vb2_buf.timestamp; 1238 1239 job->dst->vb->flags = job->active->vb->flags & 1240 V4L2_BUF_FLAG_TSTAMP_SRC_MASK; 1241 1242 /* Ideally, the frame-end function will just 'check' to see 1243 * if there are more jobs instead 1244 */ 1245 ctx->translen++; 1246 1247 /* Finally, Put this job on the processing queue */ 1248 queue_job(fdp1, job); 1249 1250 dprintk(fdp1, "Job Queued translen = %d\n", ctx->translen); 1251 1252 return job; 1253 } 1254 1255 /* fdp1_m2m_device_run() - prepares and starts the device for an M2M task 1256 * 1257 * A single input buffer is taken and serialised into our fdp1_buffer 1258 * queue. The queue is then processed to create as many jobs as possible 1259 * from our available input. 1260 */ 1261 static void fdp1_m2m_device_run(void *priv) 1262 { 1263 struct fdp1_ctx *ctx = priv; 1264 struct fdp1_dev *fdp1 = ctx->fdp1; 1265 struct vb2_v4l2_buffer *src_vb; 1266 struct fdp1_buffer *buf; 1267 unsigned int i; 1268 1269 dprintk(fdp1, "+\n"); 1270 1271 ctx->translen = 0; 1272 1273 /* Get our incoming buffer of either one or two fields, or one frame */ 1274 src_vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 1275 buf = to_fdp1_buffer(src_vb); 1276 1277 for (i = 0; i < buf->num_fields; i++) { 1278 struct fdp1_field_buffer *fbuf = &buf->fields[i]; 1279 1280 fdp1_queue_field(ctx, fbuf); 1281 dprintk(fdp1, "Queued Buffer [%d] last_field:%d\n", 1282 i, fbuf->last_field); 1283 } 1284 1285 /* Queue as many jobs as our data provides for */ 1286 while (fdp1_prepare_job(ctx)) 1287 ; 1288 1289 if (ctx->translen == 0) { 1290 dprintk(fdp1, "No jobs were processed. M2M action complete\n"); 1291 v4l2_m2m_job_finish(fdp1->m2m_dev, ctx->fh.m2m_ctx); 1292 return; 1293 } 1294 1295 /* Kick the job processing action */ 1296 fdp1_device_process(ctx); 1297 } 1298 1299 /* 1300 * device_frame_end: 1301 * 1302 * Handles the M2M level after a buffer completion event. 1303 */ 1304 static void device_frame_end(struct fdp1_dev *fdp1, 1305 enum vb2_buffer_state state) 1306 { 1307 struct fdp1_ctx *ctx; 1308 unsigned long flags; 1309 struct fdp1_job *job = get_hw_queued_job(fdp1); 1310 1311 dprintk(fdp1, "+\n"); 1312 1313 ctx = v4l2_m2m_get_curr_priv(fdp1->m2m_dev); 1314 1315 if (ctx == NULL) { 1316 v4l2_err(&fdp1->v4l2_dev, 1317 "Instance released before the end of transaction\n"); 1318 return; 1319 } 1320 1321 ctx->num_processed++; 1322 1323 /* 1324 * fdp1_field_complete will call buf_done only when the last vb2_buffer 1325 * reference is complete 1326 */ 1327 if (FDP1_DEINT_MODE_USES_PREV(ctx->deint_mode)) 1328 fdp1_field_complete(ctx, job->previous); 1329 else 1330 fdp1_field_complete(ctx, job->active); 1331 1332 spin_lock_irqsave(&fdp1->irqlock, flags); 1333 v4l2_m2m_buf_done(job->dst->vb, state); 1334 job->dst = NULL; 1335 spin_unlock_irqrestore(&fdp1->irqlock, flags); 1336 1337 /* Move this job back to the free job list */ 1338 fdp1_job_free(fdp1, job); 1339 1340 dprintk(fdp1, "curr_ctx->num_processed %d curr_ctx->translen %d\n", 1341 ctx->num_processed, ctx->translen); 1342 1343 if (ctx->num_processed == ctx->translen || 1344 ctx->aborting) { 1345 dprintk(ctx->fdp1, "Finishing transaction\n"); 1346 ctx->num_processed = 0; 1347 v4l2_m2m_job_finish(fdp1->m2m_dev, ctx->fh.m2m_ctx); 1348 } else { 1349 /* 1350 * For pipelined performance support, this would 1351 * be called from a VINT handler 1352 */ 1353 fdp1_device_process(ctx); 1354 } 1355 } 1356 1357 /* 1358 * video ioctls 1359 */ 1360 static int fdp1_vidioc_querycap(struct file *file, void *priv, 1361 struct v4l2_capability *cap) 1362 { 1363 strscpy(cap->driver, DRIVER_NAME, sizeof(cap->driver)); 1364 strscpy(cap->card, DRIVER_NAME, sizeof(cap->card)); 1365 snprintf(cap->bus_info, sizeof(cap->bus_info), 1366 "platform:%s", DRIVER_NAME); 1367 return 0; 1368 } 1369 1370 static int fdp1_enum_fmt(struct v4l2_fmtdesc *f, u32 type) 1371 { 1372 unsigned int i, num; 1373 1374 num = 0; 1375 1376 for (i = 0; i < ARRAY_SIZE(fdp1_formats); ++i) { 1377 if (fdp1_formats[i].types & type) { 1378 if (num == f->index) 1379 break; 1380 ++num; 1381 } 1382 } 1383 1384 /* Format not found */ 1385 if (i >= ARRAY_SIZE(fdp1_formats)) 1386 return -EINVAL; 1387 1388 /* Format found */ 1389 f->pixelformat = fdp1_formats[i].fourcc; 1390 1391 return 0; 1392 } 1393 1394 static int fdp1_enum_fmt_vid_cap(struct file *file, void *priv, 1395 struct v4l2_fmtdesc *f) 1396 { 1397 return fdp1_enum_fmt(f, FDP1_CAPTURE); 1398 } 1399 1400 static int fdp1_enum_fmt_vid_out(struct file *file, void *priv, 1401 struct v4l2_fmtdesc *f) 1402 { 1403 return fdp1_enum_fmt(f, FDP1_OUTPUT); 1404 } 1405 1406 static int fdp1_g_fmt(struct file *file, void *priv, struct v4l2_format *f) 1407 { 1408 struct fdp1_q_data *q_data; 1409 struct fdp1_ctx *ctx = fh_to_ctx(priv); 1410 1411 if (!v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type)) 1412 return -EINVAL; 1413 1414 q_data = get_q_data(ctx, f->type); 1415 f->fmt.pix_mp = q_data->format; 1416 1417 return 0; 1418 } 1419 1420 static void fdp1_compute_stride(struct v4l2_pix_format_mplane *pix, 1421 const struct fdp1_fmt *fmt) 1422 { 1423 unsigned int i; 1424 1425 /* Compute and clamp the stride and image size. */ 1426 for (i = 0; i < min_t(unsigned int, fmt->num_planes, 2U); ++i) { 1427 unsigned int hsub = i > 0 ? fmt->hsub : 1; 1428 unsigned int vsub = i > 0 ? fmt->vsub : 1; 1429 /* From VSP : TODO: Confirm alignment limits for FDP1 */ 1430 unsigned int align = 128; 1431 unsigned int bpl; 1432 1433 bpl = clamp_t(unsigned int, pix->plane_fmt[i].bytesperline, 1434 pix->width / hsub * fmt->bpp[i] / 8, 1435 round_down(FDP1_MAX_STRIDE, align)); 1436 1437 pix->plane_fmt[i].bytesperline = round_up(bpl, align); 1438 pix->plane_fmt[i].sizeimage = pix->plane_fmt[i].bytesperline 1439 * pix->height / vsub; 1440 1441 } 1442 1443 if (fmt->num_planes == 3) { 1444 /* The two chroma planes must have the same stride. */ 1445 pix->plane_fmt[2].bytesperline = pix->plane_fmt[1].bytesperline; 1446 pix->plane_fmt[2].sizeimage = pix->plane_fmt[1].sizeimage; 1447 1448 } 1449 } 1450 1451 static void fdp1_try_fmt_output(struct fdp1_ctx *ctx, 1452 const struct fdp1_fmt **fmtinfo, 1453 struct v4l2_pix_format_mplane *pix) 1454 { 1455 const struct fdp1_fmt *fmt; 1456 unsigned int width; 1457 unsigned int height; 1458 1459 /* Validate the pixel format to ensure the output queue supports it. */ 1460 fmt = fdp1_find_format(pix->pixelformat); 1461 if (!fmt || !(fmt->types & FDP1_OUTPUT)) 1462 fmt = fdp1_find_format(V4L2_PIX_FMT_YUYV); 1463 1464 if (fmtinfo) 1465 *fmtinfo = fmt; 1466 1467 pix->pixelformat = fmt->fourcc; 1468 pix->num_planes = fmt->num_planes; 1469 1470 /* 1471 * Progressive video and all interlaced field orders are acceptable. 1472 * Default to V4L2_FIELD_INTERLACED. 1473 */ 1474 if (pix->field != V4L2_FIELD_NONE && 1475 pix->field != V4L2_FIELD_ALTERNATE && 1476 !V4L2_FIELD_HAS_BOTH(pix->field)) 1477 pix->field = V4L2_FIELD_INTERLACED; 1478 1479 /* 1480 * The deinterlacer doesn't care about the colorspace, accept all values 1481 * and default to V4L2_COLORSPACE_SMPTE170M. The YUV to RGB conversion 1482 * at the output of the deinterlacer supports a subset of encodings and 1483 * quantization methods and will only be available when the colorspace 1484 * allows it. 1485 */ 1486 if (pix->colorspace == V4L2_COLORSPACE_DEFAULT) 1487 pix->colorspace = V4L2_COLORSPACE_SMPTE170M; 1488 1489 /* 1490 * Align the width and height for YUV 4:2:2 and 4:2:0 formats and clamp 1491 * them to the supported frame size range. The height boundary are 1492 * related to the full frame, divide them by two when the format passes 1493 * fields in separate buffers. 1494 */ 1495 width = round_down(pix->width, fmt->hsub); 1496 pix->width = clamp(width, FDP1_MIN_W, FDP1_MAX_W); 1497 1498 height = round_down(pix->height, fmt->vsub); 1499 if (pix->field == V4L2_FIELD_ALTERNATE) 1500 pix->height = clamp(height, FDP1_MIN_H / 2, FDP1_MAX_H / 2); 1501 else 1502 pix->height = clamp(height, FDP1_MIN_H, FDP1_MAX_H); 1503 1504 fdp1_compute_stride(pix, fmt); 1505 } 1506 1507 static void fdp1_try_fmt_capture(struct fdp1_ctx *ctx, 1508 const struct fdp1_fmt **fmtinfo, 1509 struct v4l2_pix_format_mplane *pix) 1510 { 1511 struct fdp1_q_data *src_data = &ctx->out_q; 1512 enum v4l2_colorspace colorspace; 1513 enum v4l2_ycbcr_encoding ycbcr_enc; 1514 enum v4l2_quantization quantization; 1515 const struct fdp1_fmt *fmt; 1516 bool allow_rgb; 1517 1518 /* 1519 * Validate the pixel format. We can only accept RGB output formats if 1520 * the input encoding and quantization are compatible with the format 1521 * conversions supported by the hardware. The supported combinations are 1522 * 1523 * V4L2_YCBCR_ENC_601 + V4L2_QUANTIZATION_LIM_RANGE 1524 * V4L2_YCBCR_ENC_601 + V4L2_QUANTIZATION_FULL_RANGE 1525 * V4L2_YCBCR_ENC_709 + V4L2_QUANTIZATION_LIM_RANGE 1526 */ 1527 colorspace = src_data->format.colorspace; 1528 1529 ycbcr_enc = src_data->format.ycbcr_enc; 1530 if (ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) 1531 ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(colorspace); 1532 1533 quantization = src_data->format.quantization; 1534 if (quantization == V4L2_QUANTIZATION_DEFAULT) 1535 quantization = V4L2_MAP_QUANTIZATION_DEFAULT(false, colorspace, 1536 ycbcr_enc); 1537 1538 allow_rgb = ycbcr_enc == V4L2_YCBCR_ENC_601 || 1539 (ycbcr_enc == V4L2_YCBCR_ENC_709 && 1540 quantization == V4L2_QUANTIZATION_LIM_RANGE); 1541 1542 fmt = fdp1_find_format(pix->pixelformat); 1543 if (!fmt || (!allow_rgb && fdp1_fmt_is_rgb(fmt))) 1544 fmt = fdp1_find_format(V4L2_PIX_FMT_YUYV); 1545 1546 if (fmtinfo) 1547 *fmtinfo = fmt; 1548 1549 pix->pixelformat = fmt->fourcc; 1550 pix->num_planes = fmt->num_planes; 1551 pix->field = V4L2_FIELD_NONE; 1552 1553 /* 1554 * The colorspace on the capture queue is copied from the output queue 1555 * as the hardware can't change the colorspace. It can convert YCbCr to 1556 * RGB though, in which case the encoding and quantization are set to 1557 * default values as anything else wouldn't make sense. 1558 */ 1559 pix->colorspace = src_data->format.colorspace; 1560 pix->xfer_func = src_data->format.xfer_func; 1561 1562 if (fdp1_fmt_is_rgb(fmt)) { 1563 pix->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1564 pix->quantization = V4L2_QUANTIZATION_DEFAULT; 1565 } else { 1566 pix->ycbcr_enc = src_data->format.ycbcr_enc; 1567 pix->quantization = src_data->format.quantization; 1568 } 1569 1570 /* 1571 * The frame width is identical to the output queue, and the height is 1572 * either doubled or identical depending on whether the output queue 1573 * field order contains one or two fields per frame. 1574 */ 1575 pix->width = src_data->format.width; 1576 if (src_data->format.field == V4L2_FIELD_ALTERNATE) 1577 pix->height = 2 * src_data->format.height; 1578 else 1579 pix->height = src_data->format.height; 1580 1581 fdp1_compute_stride(pix, fmt); 1582 } 1583 1584 static int fdp1_try_fmt(struct file *file, void *priv, struct v4l2_format *f) 1585 { 1586 struct fdp1_ctx *ctx = fh_to_ctx(priv); 1587 1588 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 1589 fdp1_try_fmt_output(ctx, NULL, &f->fmt.pix_mp); 1590 else 1591 fdp1_try_fmt_capture(ctx, NULL, &f->fmt.pix_mp); 1592 1593 dprintk(ctx->fdp1, "Try %s format: %4.4s (0x%08x) %ux%u field %u\n", 1594 V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture", 1595 (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat, 1596 f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field); 1597 1598 return 0; 1599 } 1600 1601 static void fdp1_set_format(struct fdp1_ctx *ctx, 1602 struct v4l2_pix_format_mplane *pix, 1603 enum v4l2_buf_type type) 1604 { 1605 struct fdp1_q_data *q_data = get_q_data(ctx, type); 1606 const struct fdp1_fmt *fmtinfo; 1607 1608 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 1609 fdp1_try_fmt_output(ctx, &fmtinfo, pix); 1610 else 1611 fdp1_try_fmt_capture(ctx, &fmtinfo, pix); 1612 1613 q_data->fmt = fmtinfo; 1614 q_data->format = *pix; 1615 1616 q_data->vsize = pix->height; 1617 if (pix->field != V4L2_FIELD_NONE) 1618 q_data->vsize /= 2; 1619 1620 q_data->stride_y = pix->plane_fmt[0].bytesperline; 1621 q_data->stride_c = pix->plane_fmt[1].bytesperline; 1622 1623 /* Adjust strides for interleaved buffers */ 1624 if (pix->field == V4L2_FIELD_INTERLACED || 1625 pix->field == V4L2_FIELD_INTERLACED_TB || 1626 pix->field == V4L2_FIELD_INTERLACED_BT) { 1627 q_data->stride_y *= 2; 1628 q_data->stride_c *= 2; 1629 } 1630 1631 /* Propagate the format from the output node to the capture node. */ 1632 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 1633 struct fdp1_q_data *dst_data = &ctx->cap_q; 1634 1635 /* 1636 * Copy the format, clear the per-plane bytes per line and image 1637 * size, override the field and double the height if needed. 1638 */ 1639 dst_data->format = q_data->format; 1640 memset(dst_data->format.plane_fmt, 0, 1641 sizeof(dst_data->format.plane_fmt)); 1642 1643 dst_data->format.field = V4L2_FIELD_NONE; 1644 if (pix->field == V4L2_FIELD_ALTERNATE) 1645 dst_data->format.height *= 2; 1646 1647 fdp1_try_fmt_capture(ctx, &dst_data->fmt, &dst_data->format); 1648 1649 dst_data->vsize = dst_data->format.height; 1650 dst_data->stride_y = dst_data->format.plane_fmt[0].bytesperline; 1651 dst_data->stride_c = dst_data->format.plane_fmt[1].bytesperline; 1652 } 1653 } 1654 1655 static int fdp1_s_fmt(struct file *file, void *priv, struct v4l2_format *f) 1656 { 1657 struct fdp1_ctx *ctx = fh_to_ctx(priv); 1658 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; 1659 struct vb2_queue *vq = v4l2_m2m_get_vq(m2m_ctx, f->type); 1660 1661 if (vb2_is_busy(vq)) { 1662 v4l2_err(&ctx->fdp1->v4l2_dev, "%s queue busy\n", __func__); 1663 return -EBUSY; 1664 } 1665 1666 fdp1_set_format(ctx, &f->fmt.pix_mp, f->type); 1667 1668 dprintk(ctx->fdp1, "Set %s format: %4.4s (0x%08x) %ux%u field %u\n", 1669 V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture", 1670 (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat, 1671 f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field); 1672 1673 return 0; 1674 } 1675 1676 static int fdp1_g_ctrl(struct v4l2_ctrl *ctrl) 1677 { 1678 struct fdp1_ctx *ctx = 1679 container_of(ctrl->handler, struct fdp1_ctx, hdl); 1680 struct fdp1_q_data *src_q_data = &ctx->out_q; 1681 1682 switch (ctrl->id) { 1683 case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE: 1684 if (V4L2_FIELD_HAS_BOTH(src_q_data->format.field)) 1685 ctrl->val = 2; 1686 else 1687 ctrl->val = 1; 1688 return 0; 1689 } 1690 1691 return 1; 1692 } 1693 1694 static int fdp1_s_ctrl(struct v4l2_ctrl *ctrl) 1695 { 1696 struct fdp1_ctx *ctx = 1697 container_of(ctrl->handler, struct fdp1_ctx, hdl); 1698 1699 switch (ctrl->id) { 1700 case V4L2_CID_ALPHA_COMPONENT: 1701 ctx->alpha = ctrl->val; 1702 break; 1703 1704 case V4L2_CID_DEINTERLACING_MODE: 1705 ctx->deint_mode = ctrl->val; 1706 break; 1707 } 1708 1709 return 0; 1710 } 1711 1712 static const struct v4l2_ctrl_ops fdp1_ctrl_ops = { 1713 .s_ctrl = fdp1_s_ctrl, 1714 .g_volatile_ctrl = fdp1_g_ctrl, 1715 }; 1716 1717 static const char * const fdp1_ctrl_deint_menu[] = { 1718 "Progressive", 1719 "Adaptive 2D/3D", 1720 "Fixed 2D", 1721 "Fixed 3D", 1722 "Previous field", 1723 "Next field", 1724 NULL 1725 }; 1726 1727 static const struct v4l2_ioctl_ops fdp1_ioctl_ops = { 1728 .vidioc_querycap = fdp1_vidioc_querycap, 1729 1730 .vidioc_enum_fmt_vid_cap = fdp1_enum_fmt_vid_cap, 1731 .vidioc_enum_fmt_vid_out = fdp1_enum_fmt_vid_out, 1732 .vidioc_g_fmt_vid_cap_mplane = fdp1_g_fmt, 1733 .vidioc_g_fmt_vid_out_mplane = fdp1_g_fmt, 1734 .vidioc_try_fmt_vid_cap_mplane = fdp1_try_fmt, 1735 .vidioc_try_fmt_vid_out_mplane = fdp1_try_fmt, 1736 .vidioc_s_fmt_vid_cap_mplane = fdp1_s_fmt, 1737 .vidioc_s_fmt_vid_out_mplane = fdp1_s_fmt, 1738 1739 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 1740 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 1741 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 1742 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 1743 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 1744 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 1745 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 1746 1747 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 1748 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 1749 1750 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1751 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1752 }; 1753 1754 /* 1755 * Queue operations 1756 */ 1757 1758 static int fdp1_queue_setup(struct vb2_queue *vq, 1759 unsigned int *nbuffers, unsigned int *nplanes, 1760 unsigned int sizes[], 1761 struct device *alloc_ctxs[]) 1762 { 1763 struct fdp1_ctx *ctx = vb2_get_drv_priv(vq); 1764 struct fdp1_q_data *q_data; 1765 unsigned int i; 1766 1767 q_data = get_q_data(ctx, vq->type); 1768 1769 if (*nplanes) { 1770 if (*nplanes > FDP1_MAX_PLANES) 1771 return -EINVAL; 1772 1773 return 0; 1774 } 1775 1776 *nplanes = q_data->format.num_planes; 1777 1778 for (i = 0; i < *nplanes; i++) 1779 sizes[i] = q_data->format.plane_fmt[i].sizeimage; 1780 1781 return 0; 1782 } 1783 1784 static void fdp1_buf_prepare_field(struct fdp1_q_data *q_data, 1785 struct vb2_v4l2_buffer *vbuf, 1786 unsigned int field_num) 1787 { 1788 struct fdp1_buffer *buf = to_fdp1_buffer(vbuf); 1789 struct fdp1_field_buffer *fbuf = &buf->fields[field_num]; 1790 unsigned int num_fields; 1791 unsigned int i; 1792 1793 num_fields = V4L2_FIELD_HAS_BOTH(vbuf->field) ? 2 : 1; 1794 1795 fbuf->vb = vbuf; 1796 fbuf->last_field = (field_num + 1) == num_fields; 1797 1798 for (i = 0; i < vbuf->vb2_buf.num_planes; ++i) 1799 fbuf->addrs[i] = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, i); 1800 1801 switch (vbuf->field) { 1802 case V4L2_FIELD_INTERLACED: 1803 /* 1804 * Interlaced means bottom-top for 60Hz TV standards (NTSC) and 1805 * top-bottom for 50Hz. As TV standards are not applicable to 1806 * the mem-to-mem API, use the height as a heuristic. 1807 */ 1808 fbuf->field = (q_data->format.height < 576) == field_num 1809 ? V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM; 1810 break; 1811 case V4L2_FIELD_INTERLACED_TB: 1812 case V4L2_FIELD_SEQ_TB: 1813 fbuf->field = field_num ? V4L2_FIELD_BOTTOM : V4L2_FIELD_TOP; 1814 break; 1815 case V4L2_FIELD_INTERLACED_BT: 1816 case V4L2_FIELD_SEQ_BT: 1817 fbuf->field = field_num ? V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM; 1818 break; 1819 default: 1820 fbuf->field = vbuf->field; 1821 break; 1822 } 1823 1824 /* Buffer is completed */ 1825 if (!field_num) 1826 return; 1827 1828 /* Adjust buffer addresses for second field */ 1829 switch (vbuf->field) { 1830 case V4L2_FIELD_INTERLACED: 1831 case V4L2_FIELD_INTERLACED_TB: 1832 case V4L2_FIELD_INTERLACED_BT: 1833 for (i = 0; i < vbuf->vb2_buf.num_planes; i++) 1834 fbuf->addrs[i] += 1835 (i == 0 ? q_data->stride_y : q_data->stride_c); 1836 break; 1837 case V4L2_FIELD_SEQ_TB: 1838 case V4L2_FIELD_SEQ_BT: 1839 for (i = 0; i < vbuf->vb2_buf.num_planes; i++) 1840 fbuf->addrs[i] += q_data->vsize * 1841 (i == 0 ? q_data->stride_y : q_data->stride_c); 1842 break; 1843 } 1844 } 1845 1846 static int fdp1_buf_prepare(struct vb2_buffer *vb) 1847 { 1848 struct fdp1_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 1849 struct fdp1_q_data *q_data = get_q_data(ctx, vb->vb2_queue->type); 1850 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1851 struct fdp1_buffer *buf = to_fdp1_buffer(vbuf); 1852 unsigned int i; 1853 1854 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { 1855 bool field_valid = true; 1856 1857 /* Validate the buffer field. */ 1858 switch (q_data->format.field) { 1859 case V4L2_FIELD_NONE: 1860 if (vbuf->field != V4L2_FIELD_NONE) 1861 field_valid = false; 1862 break; 1863 1864 case V4L2_FIELD_ALTERNATE: 1865 if (vbuf->field != V4L2_FIELD_TOP && 1866 vbuf->field != V4L2_FIELD_BOTTOM) 1867 field_valid = false; 1868 break; 1869 1870 case V4L2_FIELD_INTERLACED: 1871 case V4L2_FIELD_SEQ_TB: 1872 case V4L2_FIELD_SEQ_BT: 1873 case V4L2_FIELD_INTERLACED_TB: 1874 case V4L2_FIELD_INTERLACED_BT: 1875 if (vbuf->field != q_data->format.field) 1876 field_valid = false; 1877 break; 1878 } 1879 1880 if (!field_valid) { 1881 dprintk(ctx->fdp1, 1882 "buffer field %u invalid for format field %u\n", 1883 vbuf->field, q_data->format.field); 1884 return -EINVAL; 1885 } 1886 } else { 1887 vbuf->field = V4L2_FIELD_NONE; 1888 } 1889 1890 /* Validate the planes sizes. */ 1891 for (i = 0; i < q_data->format.num_planes; i++) { 1892 unsigned long size = q_data->format.plane_fmt[i].sizeimage; 1893 1894 if (vb2_plane_size(vb, i) < size) { 1895 dprintk(ctx->fdp1, 1896 "data will not fit into plane [%u/%u] (%lu < %lu)\n", 1897 i, q_data->format.num_planes, 1898 vb2_plane_size(vb, i), size); 1899 return -EINVAL; 1900 } 1901 1902 /* We have known size formats all around */ 1903 vb2_set_plane_payload(vb, i, size); 1904 } 1905 1906 buf->num_fields = V4L2_FIELD_HAS_BOTH(vbuf->field) ? 2 : 1; 1907 for (i = 0; i < buf->num_fields; ++i) 1908 fdp1_buf_prepare_field(q_data, vbuf, i); 1909 1910 return 0; 1911 } 1912 1913 static void fdp1_buf_queue(struct vb2_buffer *vb) 1914 { 1915 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1916 struct fdp1_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 1917 1918 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); 1919 } 1920 1921 static int fdp1_start_streaming(struct vb2_queue *q, unsigned int count) 1922 { 1923 struct fdp1_ctx *ctx = vb2_get_drv_priv(q); 1924 struct fdp1_q_data *q_data = get_q_data(ctx, q->type); 1925 1926 if (V4L2_TYPE_IS_OUTPUT(q->type)) { 1927 /* 1928 * Force our deint_mode when we are progressive, 1929 * ignoring any setting on the device from the user, 1930 * Otherwise, lock in the requested de-interlace mode. 1931 */ 1932 if (q_data->format.field == V4L2_FIELD_NONE) 1933 ctx->deint_mode = FDP1_PROGRESSIVE; 1934 1935 if (ctx->deint_mode == FDP1_ADAPT2D3D) { 1936 u32 stride; 1937 dma_addr_t smsk_base; 1938 const u32 bpp = 2; /* bytes per pixel */ 1939 1940 stride = round_up(q_data->format.width, 8); 1941 1942 ctx->smsk_size = bpp * stride * q_data->vsize; 1943 1944 ctx->smsk_cpu = dma_alloc_coherent(ctx->fdp1->dev, 1945 ctx->smsk_size, &smsk_base, GFP_KERNEL); 1946 1947 if (ctx->smsk_cpu == NULL) { 1948 dprintk(ctx->fdp1, "Failed to alloc smsk\n"); 1949 return -ENOMEM; 1950 } 1951 1952 ctx->smsk_addr[0] = smsk_base; 1953 ctx->smsk_addr[1] = smsk_base + (ctx->smsk_size/2); 1954 } 1955 } 1956 1957 return 0; 1958 } 1959 1960 static void fdp1_stop_streaming(struct vb2_queue *q) 1961 { 1962 struct fdp1_ctx *ctx = vb2_get_drv_priv(q); 1963 struct vb2_v4l2_buffer *vbuf; 1964 unsigned long flags; 1965 1966 while (1) { 1967 if (V4L2_TYPE_IS_OUTPUT(q->type)) 1968 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 1969 else 1970 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 1971 if (vbuf == NULL) 1972 break; 1973 spin_lock_irqsave(&ctx->fdp1->irqlock, flags); 1974 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); 1975 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags); 1976 } 1977 1978 /* Empty Output queues */ 1979 if (V4L2_TYPE_IS_OUTPUT(q->type)) { 1980 /* Empty our internal queues */ 1981 struct fdp1_field_buffer *fbuf; 1982 1983 /* Free any queued buffers */ 1984 fbuf = fdp1_dequeue_field(ctx); 1985 while (fbuf != NULL) { 1986 fdp1_field_complete(ctx, fbuf); 1987 fbuf = fdp1_dequeue_field(ctx); 1988 } 1989 1990 /* Free smsk_data */ 1991 if (ctx->smsk_cpu) { 1992 dma_free_coherent(ctx->fdp1->dev, ctx->smsk_size, 1993 ctx->smsk_cpu, ctx->smsk_addr[0]); 1994 ctx->smsk_addr[0] = ctx->smsk_addr[1] = 0; 1995 ctx->smsk_cpu = NULL; 1996 } 1997 1998 WARN(!list_empty(&ctx->fields_queue), 1999 "Buffer queue not empty"); 2000 } else { 2001 /* Empty Capture queues (Jobs) */ 2002 struct fdp1_job *job; 2003 2004 job = get_queued_job(ctx->fdp1); 2005 while (job) { 2006 if (FDP1_DEINT_MODE_USES_PREV(ctx->deint_mode)) 2007 fdp1_field_complete(ctx, job->previous); 2008 else 2009 fdp1_field_complete(ctx, job->active); 2010 2011 v4l2_m2m_buf_done(job->dst->vb, VB2_BUF_STATE_ERROR); 2012 job->dst = NULL; 2013 2014 job = get_queued_job(ctx->fdp1); 2015 } 2016 2017 /* Free any held buffer in the ctx */ 2018 fdp1_field_complete(ctx, ctx->previous); 2019 2020 WARN(!list_empty(&ctx->fdp1->queued_job_list), 2021 "Queued Job List not empty"); 2022 2023 WARN(!list_empty(&ctx->fdp1->hw_job_list), 2024 "HW Job list not empty"); 2025 } 2026 } 2027 2028 static const struct vb2_ops fdp1_qops = { 2029 .queue_setup = fdp1_queue_setup, 2030 .buf_prepare = fdp1_buf_prepare, 2031 .buf_queue = fdp1_buf_queue, 2032 .start_streaming = fdp1_start_streaming, 2033 .stop_streaming = fdp1_stop_streaming, 2034 .wait_prepare = vb2_ops_wait_prepare, 2035 .wait_finish = vb2_ops_wait_finish, 2036 }; 2037 2038 static int queue_init(void *priv, struct vb2_queue *src_vq, 2039 struct vb2_queue *dst_vq) 2040 { 2041 struct fdp1_ctx *ctx = priv; 2042 int ret; 2043 2044 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 2045 src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; 2046 src_vq->drv_priv = ctx; 2047 src_vq->buf_struct_size = sizeof(struct fdp1_buffer); 2048 src_vq->ops = &fdp1_qops; 2049 src_vq->mem_ops = &vb2_dma_contig_memops; 2050 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 2051 src_vq->lock = &ctx->fdp1->dev_mutex; 2052 src_vq->dev = ctx->fdp1->dev; 2053 2054 ret = vb2_queue_init(src_vq); 2055 if (ret) 2056 return ret; 2057 2058 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 2059 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; 2060 dst_vq->drv_priv = ctx; 2061 dst_vq->buf_struct_size = sizeof(struct fdp1_buffer); 2062 dst_vq->ops = &fdp1_qops; 2063 dst_vq->mem_ops = &vb2_dma_contig_memops; 2064 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 2065 dst_vq->lock = &ctx->fdp1->dev_mutex; 2066 dst_vq->dev = ctx->fdp1->dev; 2067 2068 return vb2_queue_init(dst_vq); 2069 } 2070 2071 /* 2072 * File operations 2073 */ 2074 static int fdp1_open(struct file *file) 2075 { 2076 struct fdp1_dev *fdp1 = video_drvdata(file); 2077 struct v4l2_pix_format_mplane format; 2078 struct fdp1_ctx *ctx = NULL; 2079 struct v4l2_ctrl *ctrl; 2080 int ret = 0; 2081 2082 if (mutex_lock_interruptible(&fdp1->dev_mutex)) 2083 return -ERESTARTSYS; 2084 2085 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2086 if (!ctx) { 2087 ret = -ENOMEM; 2088 goto done; 2089 } 2090 2091 v4l2_fh_init(&ctx->fh, video_devdata(file)); 2092 file->private_data = &ctx->fh; 2093 ctx->fdp1 = fdp1; 2094 2095 /* Initialise Queues */ 2096 INIT_LIST_HEAD(&ctx->fields_queue); 2097 2098 ctx->translen = 1; 2099 ctx->sequence = 0; 2100 2101 /* Initialise controls */ 2102 2103 v4l2_ctrl_handler_init(&ctx->hdl, 3); 2104 v4l2_ctrl_new_std_menu_items(&ctx->hdl, &fdp1_ctrl_ops, 2105 V4L2_CID_DEINTERLACING_MODE, 2106 FDP1_NEXTFIELD, BIT(0), FDP1_FIXED3D, 2107 fdp1_ctrl_deint_menu); 2108 2109 ctrl = v4l2_ctrl_new_std(&ctx->hdl, &fdp1_ctrl_ops, 2110 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 2, 1, 1); 2111 if (ctrl) 2112 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 2113 2114 v4l2_ctrl_new_std(&ctx->hdl, &fdp1_ctrl_ops, 2115 V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 255); 2116 2117 if (ctx->hdl.error) { 2118 ret = ctx->hdl.error; 2119 goto error_ctx; 2120 } 2121 2122 ctx->fh.ctrl_handler = &ctx->hdl; 2123 v4l2_ctrl_handler_setup(&ctx->hdl); 2124 2125 /* Configure default parameters. */ 2126 memset(&format, 0, sizeof(format)); 2127 fdp1_set_format(ctx, &format, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 2128 2129 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(fdp1->m2m_dev, ctx, &queue_init); 2130 2131 if (IS_ERR(ctx->fh.m2m_ctx)) { 2132 ret = PTR_ERR(ctx->fh.m2m_ctx); 2133 goto error_ctx; 2134 } 2135 2136 /* Perform any power management required */ 2137 ret = pm_runtime_resume_and_get(fdp1->dev); 2138 if (ret < 0) 2139 goto error_pm; 2140 2141 v4l2_fh_add(&ctx->fh); 2142 2143 dprintk(fdp1, "Created instance: %p, m2m_ctx: %p\n", 2144 ctx, ctx->fh.m2m_ctx); 2145 2146 mutex_unlock(&fdp1->dev_mutex); 2147 return 0; 2148 2149 error_pm: 2150 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 2151 error_ctx: 2152 v4l2_ctrl_handler_free(&ctx->hdl); 2153 kfree(ctx); 2154 done: 2155 mutex_unlock(&fdp1->dev_mutex); 2156 return ret; 2157 } 2158 2159 static int fdp1_release(struct file *file) 2160 { 2161 struct fdp1_dev *fdp1 = video_drvdata(file); 2162 struct fdp1_ctx *ctx = fh_to_ctx(file->private_data); 2163 2164 dprintk(fdp1, "Releasing instance %p\n", ctx); 2165 2166 v4l2_fh_del(&ctx->fh); 2167 v4l2_fh_exit(&ctx->fh); 2168 v4l2_ctrl_handler_free(&ctx->hdl); 2169 mutex_lock(&fdp1->dev_mutex); 2170 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 2171 mutex_unlock(&fdp1->dev_mutex); 2172 kfree(ctx); 2173 2174 pm_runtime_put(fdp1->dev); 2175 2176 return 0; 2177 } 2178 2179 static const struct v4l2_file_operations fdp1_fops = { 2180 .owner = THIS_MODULE, 2181 .open = fdp1_open, 2182 .release = fdp1_release, 2183 .poll = v4l2_m2m_fop_poll, 2184 .unlocked_ioctl = video_ioctl2, 2185 .mmap = v4l2_m2m_fop_mmap, 2186 }; 2187 2188 static const struct video_device fdp1_videodev = { 2189 .name = DRIVER_NAME, 2190 .vfl_dir = VFL_DIR_M2M, 2191 .fops = &fdp1_fops, 2192 .device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING, 2193 .ioctl_ops = &fdp1_ioctl_ops, 2194 .minor = -1, 2195 .release = video_device_release_empty, 2196 }; 2197 2198 static const struct v4l2_m2m_ops m2m_ops = { 2199 .device_run = fdp1_m2m_device_run, 2200 .job_ready = fdp1_m2m_job_ready, 2201 .job_abort = fdp1_m2m_job_abort, 2202 }; 2203 2204 static irqreturn_t fdp1_irq_handler(int irq, void *dev_id) 2205 { 2206 struct fdp1_dev *fdp1 = dev_id; 2207 u32 int_status; 2208 u32 ctl_status; 2209 u32 vint_cnt; 2210 u32 cycles; 2211 2212 int_status = fdp1_read(fdp1, FD1_CTL_IRQSTA); 2213 cycles = fdp1_read(fdp1, FD1_CTL_VCYCLE_STAT); 2214 ctl_status = fdp1_read(fdp1, FD1_CTL_STATUS); 2215 vint_cnt = (ctl_status & FD1_CTL_STATUS_VINT_CNT_MASK) >> 2216 FD1_CTL_STATUS_VINT_CNT_SHIFT; 2217 2218 /* Clear interrupts */ 2219 fdp1_write(fdp1, ~(int_status) & FD1_CTL_IRQ_MASK, FD1_CTL_IRQSTA); 2220 2221 if (debug >= 2) { 2222 dprintk(fdp1, "IRQ: 0x%x %s%s%s\n", int_status, 2223 int_status & FD1_CTL_IRQ_VERE ? "[Error]" : "[!E]", 2224 int_status & FD1_CTL_IRQ_VINTE ? "[VSync]" : "[!V]", 2225 int_status & FD1_CTL_IRQ_FREE ? "[FrameEnd]" : "[!F]"); 2226 2227 dprintk(fdp1, "CycleStatus = %d (%dms)\n", 2228 cycles, cycles/(fdp1->clk_rate/1000)); 2229 2230 dprintk(fdp1, 2231 "Control Status = 0x%08x : VINT_CNT = %d %s:%s:%s:%s\n", 2232 ctl_status, vint_cnt, 2233 ctl_status & FD1_CTL_STATUS_SGREGSET ? "RegSet" : "", 2234 ctl_status & FD1_CTL_STATUS_SGVERR ? "Vsync Error" : "", 2235 ctl_status & FD1_CTL_STATUS_SGFREND ? "FrameEnd" : "", 2236 ctl_status & FD1_CTL_STATUS_BSY ? "Busy" : ""); 2237 dprintk(fdp1, "***********************************\n"); 2238 } 2239 2240 /* Spurious interrupt */ 2241 if (!(FD1_CTL_IRQ_MASK & int_status)) 2242 return IRQ_NONE; 2243 2244 /* Work completed, release the frame */ 2245 if (FD1_CTL_IRQ_VERE & int_status) 2246 device_frame_end(fdp1, VB2_BUF_STATE_ERROR); 2247 else if (FD1_CTL_IRQ_FREE & int_status) 2248 device_frame_end(fdp1, VB2_BUF_STATE_DONE); 2249 2250 return IRQ_HANDLED; 2251 } 2252 2253 static int fdp1_probe(struct platform_device *pdev) 2254 { 2255 struct fdp1_dev *fdp1; 2256 struct video_device *vfd; 2257 struct device_node *fcp_node; 2258 struct clk *clk; 2259 unsigned int i; 2260 2261 int ret; 2262 int hw_version; 2263 2264 fdp1 = devm_kzalloc(&pdev->dev, sizeof(*fdp1), GFP_KERNEL); 2265 if (!fdp1) 2266 return -ENOMEM; 2267 2268 INIT_LIST_HEAD(&fdp1->free_job_list); 2269 INIT_LIST_HEAD(&fdp1->queued_job_list); 2270 INIT_LIST_HEAD(&fdp1->hw_job_list); 2271 2272 /* Initialise the jobs on the free list */ 2273 for (i = 0; i < ARRAY_SIZE(fdp1->jobs); i++) 2274 list_add(&fdp1->jobs[i].list, &fdp1->free_job_list); 2275 2276 mutex_init(&fdp1->dev_mutex); 2277 2278 spin_lock_init(&fdp1->irqlock); 2279 spin_lock_init(&fdp1->device_process_lock); 2280 fdp1->dev = &pdev->dev; 2281 platform_set_drvdata(pdev, fdp1); 2282 2283 /* Memory-mapped registers */ 2284 fdp1->regs = devm_platform_ioremap_resource(pdev, 0); 2285 if (IS_ERR(fdp1->regs)) 2286 return PTR_ERR(fdp1->regs); 2287 2288 /* Interrupt service routine registration */ 2289 ret = platform_get_irq(pdev, 0); 2290 if (ret < 0) 2291 return ret; 2292 fdp1->irq = ret; 2293 2294 ret = devm_request_irq(&pdev->dev, fdp1->irq, fdp1_irq_handler, 0, 2295 dev_name(&pdev->dev), fdp1); 2296 if (ret) { 2297 dev_err(&pdev->dev, "cannot claim IRQ %d\n", fdp1->irq); 2298 return ret; 2299 } 2300 2301 /* FCP */ 2302 fcp_node = of_parse_phandle(pdev->dev.of_node, "renesas,fcp", 0); 2303 if (fcp_node) { 2304 fdp1->fcp = rcar_fcp_get(fcp_node); 2305 of_node_put(fcp_node); 2306 if (IS_ERR(fdp1->fcp)) { 2307 dev_dbg(&pdev->dev, "FCP not found (%ld)\n", 2308 PTR_ERR(fdp1->fcp)); 2309 return PTR_ERR(fdp1->fcp); 2310 } 2311 } 2312 2313 /* Determine our clock rate */ 2314 clk = clk_get(&pdev->dev, NULL); 2315 if (IS_ERR(clk)) { 2316 ret = PTR_ERR(clk); 2317 goto put_dev; 2318 } 2319 2320 fdp1->clk_rate = clk_get_rate(clk); 2321 clk_put(clk); 2322 2323 /* V4L2 device registration */ 2324 ret = v4l2_device_register(&pdev->dev, &fdp1->v4l2_dev); 2325 if (ret) { 2326 v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n"); 2327 goto put_dev; 2328 } 2329 2330 /* M2M registration */ 2331 fdp1->m2m_dev = v4l2_m2m_init(&m2m_ops); 2332 if (IS_ERR(fdp1->m2m_dev)) { 2333 v4l2_err(&fdp1->v4l2_dev, "Failed to init mem2mem device\n"); 2334 ret = PTR_ERR(fdp1->m2m_dev); 2335 goto unreg_dev; 2336 } 2337 2338 /* Video registration */ 2339 fdp1->vfd = fdp1_videodev; 2340 vfd = &fdp1->vfd; 2341 vfd->lock = &fdp1->dev_mutex; 2342 vfd->v4l2_dev = &fdp1->v4l2_dev; 2343 video_set_drvdata(vfd, fdp1); 2344 strscpy(vfd->name, fdp1_videodev.name, sizeof(vfd->name)); 2345 2346 ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); 2347 if (ret) { 2348 v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n"); 2349 goto release_m2m; 2350 } 2351 2352 v4l2_info(&fdp1->v4l2_dev, "Device registered as /dev/video%d\n", 2353 vfd->num); 2354 2355 /* Power up the cells to read HW */ 2356 pm_runtime_enable(&pdev->dev); 2357 ret = pm_runtime_resume_and_get(fdp1->dev); 2358 if (ret < 0) 2359 goto disable_pm; 2360 2361 hw_version = fdp1_read(fdp1, FD1_IP_INTDATA); 2362 switch (hw_version) { 2363 case FD1_IP_M3W: 2364 dprintk(fdp1, "FDP1 Version R-Car M3-W\n"); 2365 break; 2366 case FD1_IP_H3: 2367 dprintk(fdp1, "FDP1 Version R-Car H3\n"); 2368 break; 2369 case FD1_IP_M3N: 2370 dprintk(fdp1, "FDP1 Version R-Car M3-N\n"); 2371 break; 2372 case FD1_IP_E3: 2373 dprintk(fdp1, "FDP1 Version R-Car E3\n"); 2374 break; 2375 default: 2376 dev_err(fdp1->dev, "FDP1 Unidentifiable (0x%08x)\n", 2377 hw_version); 2378 } 2379 2380 /* Allow the hw to sleep until an open call puts it to use */ 2381 pm_runtime_put(fdp1->dev); 2382 2383 return 0; 2384 2385 disable_pm: 2386 pm_runtime_disable(fdp1->dev); 2387 2388 release_m2m: 2389 v4l2_m2m_release(fdp1->m2m_dev); 2390 2391 unreg_dev: 2392 v4l2_device_unregister(&fdp1->v4l2_dev); 2393 2394 put_dev: 2395 rcar_fcp_put(fdp1->fcp); 2396 return ret; 2397 } 2398 2399 static void fdp1_remove(struct platform_device *pdev) 2400 { 2401 struct fdp1_dev *fdp1 = platform_get_drvdata(pdev); 2402 2403 v4l2_m2m_release(fdp1->m2m_dev); 2404 video_unregister_device(&fdp1->vfd); 2405 v4l2_device_unregister(&fdp1->v4l2_dev); 2406 pm_runtime_disable(&pdev->dev); 2407 rcar_fcp_put(fdp1->fcp); 2408 } 2409 2410 static int __maybe_unused fdp1_pm_runtime_suspend(struct device *dev) 2411 { 2412 struct fdp1_dev *fdp1 = dev_get_drvdata(dev); 2413 2414 rcar_fcp_disable(fdp1->fcp); 2415 2416 return 0; 2417 } 2418 2419 static int __maybe_unused fdp1_pm_runtime_resume(struct device *dev) 2420 { 2421 struct fdp1_dev *fdp1 = dev_get_drvdata(dev); 2422 2423 /* Program in the static LUTs */ 2424 fdp1_set_lut(fdp1); 2425 2426 return rcar_fcp_enable(fdp1->fcp); 2427 } 2428 2429 static const struct dev_pm_ops fdp1_pm_ops = { 2430 SET_RUNTIME_PM_OPS(fdp1_pm_runtime_suspend, 2431 fdp1_pm_runtime_resume, 2432 NULL) 2433 }; 2434 2435 static const struct of_device_id fdp1_dt_ids[] = { 2436 { .compatible = "renesas,fdp1" }, 2437 { }, 2438 }; 2439 MODULE_DEVICE_TABLE(of, fdp1_dt_ids); 2440 2441 static struct platform_driver fdp1_pdrv = { 2442 .probe = fdp1_probe, 2443 .remove_new = fdp1_remove, 2444 .driver = { 2445 .name = DRIVER_NAME, 2446 .of_match_table = fdp1_dt_ids, 2447 .pm = &fdp1_pm_ops, 2448 }, 2449 }; 2450 2451 module_platform_driver(fdp1_pdrv); 2452 2453 MODULE_DESCRIPTION("Renesas R-Car Fine Display Processor Driver"); 2454 MODULE_AUTHOR("Kieran Bingham <kieran@bingham.xyz>"); 2455 MODULE_LICENSE("GPL"); 2456 MODULE_ALIAS("platform:" DRIVER_NAME); 2457