1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - CSI-2 Receiver 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * Copyright (C) 2022 Ideas on Board 7 * 8 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 9 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/lockdep.h> 15 #include <linux/phy/phy.h> 16 #include <linux/phy/phy-mipi-dphy.h> 17 18 #include <media/v4l2-ctrls.h> 19 #include <media/v4l2-fwnode.h> 20 21 #include "rkisp1-common.h" 22 #include "rkisp1-csi.h" 23 24 #define RKISP1_CSI_DEV_NAME RKISP1_DRIVER_NAME "_csi" 25 26 #define RKISP1_CSI_DEF_FMT MEDIA_BUS_FMT_SRGGB10_1X10 27 28 static inline struct rkisp1_csi *to_rkisp1_csi(struct v4l2_subdev *sd) 29 { 30 return container_of(sd, struct rkisp1_csi, sd); 31 } 32 33 int rkisp1_csi_link_sensor(struct rkisp1_device *rkisp1, struct v4l2_subdev *sd, 34 struct rkisp1_sensor_async *s_asd, 35 unsigned int source_pad) 36 { 37 struct rkisp1_csi *csi = &rkisp1->csi; 38 int ret; 39 40 s_asd->pixel_rate_ctrl = v4l2_ctrl_find(sd->ctrl_handler, 41 V4L2_CID_PIXEL_RATE); 42 if (!s_asd->pixel_rate_ctrl) { 43 dev_err(rkisp1->dev, "No pixel rate control in subdev %s\n", 44 sd->name); 45 return -EINVAL; 46 } 47 48 /* Create the link from the sensor to the CSI receiver. */ 49 ret = media_create_pad_link(&sd->entity, source_pad, 50 &csi->sd.entity, RKISP1_CSI_PAD_SINK, 51 !s_asd->index ? MEDIA_LNK_FL_ENABLED : 0); 52 if (ret) { 53 dev_err(csi->rkisp1->dev, "failed to link src pad of %s\n", 54 sd->name); 55 return ret; 56 } 57 58 return 0; 59 } 60 61 static int rkisp1_csi_config(struct rkisp1_csi *csi, 62 const struct rkisp1_sensor_async *sensor, 63 const struct rkisp1_mbus_info *format) 64 { 65 struct rkisp1_device *rkisp1 = csi->rkisp1; 66 unsigned int lanes = sensor->lanes; 67 u32 mipi_ctrl; 68 69 if (lanes < 1 || lanes > 4) 70 return -EINVAL; 71 72 mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) | 73 RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) | 74 RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP | 75 RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA; 76 77 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, mipi_ctrl); 78 79 /* V12 could also use a newer csi2-host, but we don't want that yet */ 80 if (rkisp1->info->isp_ver == RKISP1_V12) 81 rkisp1_write(rkisp1, RKISP1_CIF_ISP_CSI0_CTRL0, 0); 82 83 /* Configure Data Type and Virtual Channel */ 84 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL, 85 RKISP1_CIF_MIPI_DATA_SEL_DT(format->mipi_dt) | 86 RKISP1_CIF_MIPI_DATA_SEL_VC(0)); 87 88 /* Clear MIPI interrupts */ 89 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0); 90 91 /* 92 * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for 93 * isp bus may be dead when switch isp. 94 */ 95 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 96 RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI | 97 RKISP1_CIF_MIPI_ERR_DPHY | 98 RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) | 99 RKISP1_CIF_MIPI_ADD_DATA_OVFLW); 100 101 dev_dbg(rkisp1->dev, "\n MIPI_CTRL 0x%08x\n" 102 " MIPI_IMG_DATA_SEL 0x%08x\n" 103 " MIPI_STATUS 0x%08x\n" 104 " MIPI_IMSC 0x%08x\n", 105 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL), 106 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL), 107 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS), 108 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC)); 109 110 return 0; 111 } 112 113 static void rkisp1_csi_enable(struct rkisp1_csi *csi) 114 { 115 struct rkisp1_device *rkisp1 = csi->rkisp1; 116 u32 val; 117 118 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 119 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, 120 val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA); 121 } 122 123 static void rkisp1_csi_disable(struct rkisp1_csi *csi) 124 { 125 struct rkisp1_device *rkisp1 = csi->rkisp1; 126 u32 val; 127 128 /* Mask MIPI interrupts. */ 129 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 0); 130 131 /* Flush posted writes */ 132 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 133 134 /* 135 * Wait until the IRQ handler has ended. The IRQ handler may get called 136 * even after this, but it will return immediately as the MIPI 137 * interrupts have been masked. 138 */ 139 synchronize_irq(rkisp1->irqs[RKISP1_IRQ_MIPI]); 140 141 /* Clear MIPI interrupt status */ 142 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0); 143 144 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 145 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, 146 val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA)); 147 } 148 149 static int rkisp1_csi_start(struct rkisp1_csi *csi, 150 const struct rkisp1_sensor_async *sensor, 151 const struct rkisp1_mbus_info *format) 152 { 153 struct rkisp1_device *rkisp1 = csi->rkisp1; 154 union phy_configure_opts opts; 155 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; 156 s64 pixel_clock; 157 int ret; 158 159 ret = rkisp1_csi_config(csi, sensor, format); 160 if (ret) 161 return ret; 162 163 pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl); 164 if (!pixel_clock) { 165 dev_err(rkisp1->dev, "Invalid pixel rate value\n"); 166 return -EINVAL; 167 } 168 169 phy_mipi_dphy_get_default_config(pixel_clock, format->bus_width, 170 sensor->lanes, cfg); 171 phy_set_mode(csi->dphy, PHY_MODE_MIPI_DPHY); 172 phy_configure(csi->dphy, &opts); 173 phy_power_on(csi->dphy); 174 175 rkisp1_csi_enable(csi); 176 177 /* 178 * CIF spec says to wait for sufficient time after enabling 179 * the MIPI interface and before starting the sensor output. 180 */ 181 usleep_range(1000, 1200); 182 183 return 0; 184 } 185 186 static void rkisp1_csi_stop(struct rkisp1_csi *csi) 187 { 188 rkisp1_csi_disable(csi); 189 190 phy_power_off(csi->dphy); 191 } 192 193 irqreturn_t rkisp1_csi_isr(int irq, void *ctx) 194 { 195 struct device *dev = ctx; 196 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 197 u32 val, status; 198 199 status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS); 200 if (!status) 201 return IRQ_NONE; 202 203 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, status); 204 205 /* 206 * Disable DPHY errctrl interrupt, because this dphy 207 * erctrl signal is asserted until the next changes 208 * of line state. This time is may be too long and cpu 209 * is hold in this interrupt. 210 */ 211 if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) { 212 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 213 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 214 val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f)); 215 rkisp1->csi.is_dphy_errctrl_disabled = true; 216 } 217 218 /* 219 * Enable DPHY errctrl interrupt again, if mipi have receive 220 * the whole frame without any error. 221 */ 222 if (status == RKISP1_CIF_MIPI_FRAME_END) { 223 /* 224 * Enable DPHY errctrl interrupt again, if mipi have receive 225 * the whole frame without any error. 226 */ 227 if (rkisp1->csi.is_dphy_errctrl_disabled) { 228 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 229 val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f); 230 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, val); 231 rkisp1->csi.is_dphy_errctrl_disabled = false; 232 } 233 } else { 234 rkisp1->debug.mipi_error++; 235 } 236 237 return IRQ_HANDLED; 238 } 239 240 /* ---------------------------------------------------------------------------- 241 * Subdev pad operations 242 */ 243 244 static int rkisp1_csi_enum_mbus_code(struct v4l2_subdev *sd, 245 struct v4l2_subdev_state *sd_state, 246 struct v4l2_subdev_mbus_code_enum *code) 247 { 248 unsigned int i; 249 int pos = 0; 250 251 if (code->pad == RKISP1_CSI_PAD_SRC) { 252 const struct v4l2_mbus_framefmt *sink_fmt; 253 254 if (code->index) 255 return -EINVAL; 256 257 sink_fmt = v4l2_subdev_state_get_format(sd_state, 258 RKISP1_CSI_PAD_SINK); 259 code->code = sink_fmt->code; 260 261 return 0; 262 } 263 264 for (i = 0; ; i++) { 265 const struct rkisp1_mbus_info *fmt = 266 rkisp1_mbus_info_get_by_index(i); 267 268 if (!fmt) 269 return -EINVAL; 270 271 if (!(fmt->direction & RKISP1_ISP_SD_SINK)) 272 continue; 273 274 if (code->index == pos) { 275 code->code = fmt->mbus_code; 276 return 0; 277 } 278 279 pos++; 280 } 281 282 return -EINVAL; 283 } 284 285 static int rkisp1_csi_init_state(struct v4l2_subdev *sd, 286 struct v4l2_subdev_state *sd_state) 287 { 288 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt; 289 290 sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SINK); 291 src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SRC); 292 293 sink_fmt->width = RKISP1_DEFAULT_WIDTH; 294 sink_fmt->height = RKISP1_DEFAULT_HEIGHT; 295 sink_fmt->field = V4L2_FIELD_NONE; 296 sink_fmt->code = RKISP1_CSI_DEF_FMT; 297 298 *src_fmt = *sink_fmt; 299 300 return 0; 301 } 302 303 static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd, 304 struct v4l2_subdev_state *sd_state, 305 struct v4l2_subdev_format *fmt) 306 { 307 const struct rkisp1_mbus_info *mbus_info; 308 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt; 309 310 /* The format on the source pad always matches the sink pad. */ 311 if (fmt->pad == RKISP1_CSI_PAD_SRC) 312 return v4l2_subdev_get_fmt(sd, sd_state, fmt); 313 314 sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SINK); 315 316 sink_fmt->code = fmt->format.code; 317 318 mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code); 319 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) { 320 sink_fmt->code = RKISP1_CSI_DEF_FMT; 321 mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code); 322 } 323 324 sink_fmt->width = clamp_t(u32, fmt->format.width, 325 RKISP1_ISP_MIN_WIDTH, 326 RKISP1_ISP_MAX_WIDTH); 327 sink_fmt->height = clamp_t(u32, fmt->format.height, 328 RKISP1_ISP_MIN_HEIGHT, 329 RKISP1_ISP_MAX_HEIGHT); 330 331 fmt->format = *sink_fmt; 332 333 /* Propagate the format to the source pad. */ 334 src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SRC); 335 *src_fmt = *sink_fmt; 336 337 return 0; 338 } 339 340 /* ---------------------------------------------------------------------------- 341 * Subdev video operations 342 */ 343 344 static int rkisp1_csi_s_stream(struct v4l2_subdev *sd, int enable) 345 { 346 struct rkisp1_csi *csi = to_rkisp1_csi(sd); 347 struct rkisp1_device *rkisp1 = csi->rkisp1; 348 const struct v4l2_mbus_framefmt *sink_fmt; 349 const struct rkisp1_mbus_info *format; 350 struct rkisp1_sensor_async *source_asd; 351 struct v4l2_async_connection *asc; 352 struct v4l2_subdev_state *sd_state; 353 struct media_pad *source_pad; 354 struct v4l2_subdev *source; 355 int ret; 356 357 if (!enable) { 358 v4l2_subdev_call(csi->source, video, s_stream, false); 359 360 rkisp1_csi_stop(csi); 361 362 return 0; 363 } 364 365 source_pad = media_entity_remote_source_pad_unique(&sd->entity); 366 if (IS_ERR(source_pad)) { 367 dev_dbg(rkisp1->dev, "Failed to get source for CSI: %ld\n", 368 PTR_ERR(source_pad)); 369 return -EPIPE; 370 } 371 372 source = media_entity_to_v4l2_subdev(source_pad->entity); 373 if (!source) { 374 /* This should really not happen, so is not worth a message. */ 375 return -EPIPE; 376 } 377 378 asc = v4l2_async_connection_unique(source); 379 if (!asc) 380 return -EPIPE; 381 382 source_asd = container_of(asc, struct rkisp1_sensor_async, asd); 383 if (source_asd->mbus_type != V4L2_MBUS_CSI2_DPHY) 384 return -EINVAL; 385 386 sd_state = v4l2_subdev_lock_and_get_active_state(sd); 387 sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SINK); 388 format = rkisp1_mbus_info_get_by_code(sink_fmt->code); 389 v4l2_subdev_unlock_state(sd_state); 390 391 ret = rkisp1_csi_start(csi, source_asd, format); 392 if (ret) 393 return ret; 394 395 ret = v4l2_subdev_call(source, video, s_stream, true); 396 if (ret) { 397 rkisp1_csi_stop(csi); 398 return ret; 399 } 400 401 csi->source = source; 402 403 return 0; 404 } 405 406 /* ---------------------------------------------------------------------------- 407 * Registration 408 */ 409 410 static const struct media_entity_operations rkisp1_csi_media_ops = { 411 .link_validate = v4l2_subdev_link_validate, 412 }; 413 414 static const struct v4l2_subdev_video_ops rkisp1_csi_video_ops = { 415 .s_stream = rkisp1_csi_s_stream, 416 }; 417 418 static const struct v4l2_subdev_pad_ops rkisp1_csi_pad_ops = { 419 .enum_mbus_code = rkisp1_csi_enum_mbus_code, 420 .get_fmt = v4l2_subdev_get_fmt, 421 .set_fmt = rkisp1_csi_set_fmt, 422 }; 423 424 static const struct v4l2_subdev_ops rkisp1_csi_ops = { 425 .video = &rkisp1_csi_video_ops, 426 .pad = &rkisp1_csi_pad_ops, 427 }; 428 429 static const struct v4l2_subdev_internal_ops rkisp1_csi_internal_ops = { 430 .init_state = rkisp1_csi_init_state, 431 }; 432 433 int rkisp1_csi_register(struct rkisp1_device *rkisp1) 434 { 435 struct rkisp1_csi *csi = &rkisp1->csi; 436 struct media_pad *pads; 437 struct v4l2_subdev *sd; 438 int ret; 439 440 csi->rkisp1 = rkisp1; 441 442 sd = &csi->sd; 443 v4l2_subdev_init(sd, &rkisp1_csi_ops); 444 sd->internal_ops = &rkisp1_csi_internal_ops; 445 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 446 sd->entity.ops = &rkisp1_csi_media_ops; 447 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 448 sd->owner = THIS_MODULE; 449 strscpy(sd->name, RKISP1_CSI_DEV_NAME, sizeof(sd->name)); 450 451 pads = csi->pads; 452 pads[RKISP1_CSI_PAD_SINK].flags = MEDIA_PAD_FL_SINK | 453 MEDIA_PAD_FL_MUST_CONNECT; 454 pads[RKISP1_CSI_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE | 455 MEDIA_PAD_FL_MUST_CONNECT; 456 457 ret = media_entity_pads_init(&sd->entity, RKISP1_CSI_PAD_NUM, pads); 458 if (ret) 459 goto err_entity_cleanup; 460 461 ret = v4l2_subdev_init_finalize(sd); 462 if (ret) 463 goto err_entity_cleanup; 464 465 ret = v4l2_device_register_subdev(&csi->rkisp1->v4l2_dev, sd); 466 if (ret) { 467 dev_err(sd->dev, "Failed to register csi receiver subdev\n"); 468 goto err_subdev_cleanup; 469 } 470 471 return 0; 472 473 err_subdev_cleanup: 474 v4l2_subdev_cleanup(sd); 475 err_entity_cleanup: 476 media_entity_cleanup(&sd->entity); 477 csi->rkisp1 = NULL; 478 return ret; 479 } 480 481 void rkisp1_csi_unregister(struct rkisp1_device *rkisp1) 482 { 483 struct rkisp1_csi *csi = &rkisp1->csi; 484 485 if (!csi->rkisp1) 486 return; 487 488 v4l2_device_unregister_subdev(&csi->sd); 489 v4l2_subdev_cleanup(&csi->sd); 490 media_entity_cleanup(&csi->sd.entity); 491 } 492 493 int rkisp1_csi_init(struct rkisp1_device *rkisp1) 494 { 495 struct rkisp1_csi *csi = &rkisp1->csi; 496 497 csi->rkisp1 = rkisp1; 498 499 csi->dphy = devm_phy_get(rkisp1->dev, "dphy"); 500 if (IS_ERR(csi->dphy)) 501 return dev_err_probe(rkisp1->dev, PTR_ERR(csi->dphy), 502 "Couldn't get the MIPI D-PHY\n"); 503 504 phy_init(csi->dphy); 505 506 return 0; 507 } 508 509 void rkisp1_csi_cleanup(struct rkisp1_device *rkisp1) 510 { 511 struct rkisp1_csi *csi = &rkisp1->csi; 512 513 phy_exit(csi->dphy); 514 } 515