1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * linux/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com/ 7 */ 8 9 #include "s5p_mfc_common.h" 10 11 #include "s5p_mfc_cmd.h" 12 #include "s5p_mfc_debug.h" 13 #include "s5p_mfc_intr.h" 14 #include "s5p_mfc_opr.h" 15 #include "s5p_mfc_cmd_v6.h" 16 17 static int s5p_mfc_cmd_host2risc_v6(struct s5p_mfc_dev *dev, int cmd, 18 struct s5p_mfc_cmd_args *args) 19 { 20 mfc_debug(2, "Issue the command: %d\n", cmd); 21 22 /* Reset RISC2HOST command */ 23 mfc_write(dev, 0x0, S5P_FIMV_RISC2HOST_CMD_V6); 24 25 /* Issue the command */ 26 mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD_V6); 27 mfc_write(dev, 0x1, S5P_FIMV_HOST2RISC_INT_V6); 28 29 return 0; 30 } 31 32 static int s5p_mfc_sys_init_cmd_v6(struct s5p_mfc_dev *dev) 33 { 34 struct s5p_mfc_cmd_args h2r_args; 35 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv; 36 int ret; 37 38 ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_dev_context_buffer, dev); 39 if (ret) 40 return ret; 41 42 mfc_write(dev, dev->ctx_buf.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6); 43 mfc_write(dev, buf_size->dev_ctx, S5P_FIMV_CONTEXT_MEM_SIZE_V6); 44 return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SYS_INIT_V6, 45 &h2r_args); 46 } 47 48 static int s5p_mfc_sleep_cmd_v6(struct s5p_mfc_dev *dev) 49 { 50 struct s5p_mfc_cmd_args h2r_args; 51 52 memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args)); 53 return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SLEEP_V6, 54 &h2r_args); 55 } 56 57 static int s5p_mfc_wakeup_cmd_v6(struct s5p_mfc_dev *dev) 58 { 59 struct s5p_mfc_cmd_args h2r_args; 60 61 memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args)); 62 return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_WAKEUP_V6, 63 &h2r_args); 64 } 65 66 /* Open a new instance and get its number */ 67 static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx) 68 { 69 struct s5p_mfc_dev *dev = ctx->dev; 70 struct s5p_mfc_cmd_args h2r_args; 71 int codec_type; 72 73 mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode); 74 dev->curr_ctx = ctx->num; 75 switch (ctx->codec_mode) { 76 case S5P_MFC_CODEC_H264_DEC: 77 codec_type = S5P_FIMV_CODEC_H264_DEC_V6; 78 break; 79 case S5P_MFC_CODEC_H264_MVC_DEC: 80 codec_type = S5P_FIMV_CODEC_H264_MVC_DEC_V6; 81 break; 82 case S5P_MFC_CODEC_VC1_DEC: 83 codec_type = S5P_FIMV_CODEC_VC1_DEC_V6; 84 break; 85 case S5P_MFC_CODEC_MPEG4_DEC: 86 codec_type = S5P_FIMV_CODEC_MPEG4_DEC_V6; 87 break; 88 case S5P_MFC_CODEC_MPEG2_DEC: 89 codec_type = S5P_FIMV_CODEC_MPEG2_DEC_V6; 90 break; 91 case S5P_MFC_CODEC_H263_DEC: 92 codec_type = S5P_FIMV_CODEC_H263_DEC_V6; 93 break; 94 case S5P_MFC_CODEC_VC1RCV_DEC: 95 codec_type = S5P_FIMV_CODEC_VC1RCV_DEC_V6; 96 break; 97 case S5P_MFC_CODEC_VP8_DEC: 98 codec_type = S5P_FIMV_CODEC_VP8_DEC_V6; 99 break; 100 case S5P_MFC_CODEC_HEVC_DEC: 101 codec_type = S5P_FIMV_CODEC_HEVC_DEC; 102 break; 103 case S5P_MFC_CODEC_VP9_DEC: 104 codec_type = S5P_FIMV_CODEC_VP9_DEC; 105 break; 106 case S5P_MFC_CODEC_H264_ENC: 107 codec_type = S5P_FIMV_CODEC_H264_ENC_V6; 108 break; 109 case S5P_MFC_CODEC_H264_MVC_ENC: 110 codec_type = S5P_FIMV_CODEC_H264_MVC_ENC_V6; 111 break; 112 case S5P_MFC_CODEC_MPEG4_ENC: 113 codec_type = S5P_FIMV_CODEC_MPEG4_ENC_V6; 114 break; 115 case S5P_MFC_CODEC_H263_ENC: 116 codec_type = S5P_FIMV_CODEC_H263_ENC_V6; 117 break; 118 case S5P_MFC_CODEC_VP8_ENC: 119 codec_type = S5P_FIMV_CODEC_VP8_ENC_V7; 120 break; 121 case S5P_MFC_CODEC_HEVC_ENC: 122 codec_type = S5P_FIMV_CODEC_HEVC_ENC; 123 break; 124 default: 125 codec_type = S5P_FIMV_CODEC_NONE_V6; 126 } 127 mfc_write(dev, codec_type, S5P_FIMV_CODEC_TYPE_V6); 128 mfc_write(dev, ctx->ctx.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6); 129 mfc_write(dev, ctx->ctx.size, S5P_FIMV_CONTEXT_MEM_SIZE_V6); 130 mfc_write(dev, 0, S5P_FIMV_D_CRC_CTRL_V6); /* no crc */ 131 132 return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE_V6, 133 &h2r_args); 134 } 135 136 /* Close instance */ 137 static int s5p_mfc_close_inst_cmd_v6(struct s5p_mfc_ctx *ctx) 138 { 139 struct s5p_mfc_dev *dev = ctx->dev; 140 struct s5p_mfc_cmd_args h2r_args; 141 int ret = 0; 142 143 dev->curr_ctx = ctx->num; 144 if (ctx->state != MFCINST_FREE) { 145 mfc_write(dev, ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); 146 ret = s5p_mfc_cmd_host2risc_v6(dev, 147 S5P_FIMV_H2R_CMD_CLOSE_INSTANCE_V6, 148 &h2r_args); 149 } else { 150 ret = -EINVAL; 151 } 152 153 return ret; 154 } 155 156 /* Initialize cmd function pointers for MFC v6 */ 157 static struct s5p_mfc_hw_cmds s5p_mfc_cmds_v6 = { 158 .cmd_host2risc = s5p_mfc_cmd_host2risc_v6, 159 .sys_init_cmd = s5p_mfc_sys_init_cmd_v6, 160 .sleep_cmd = s5p_mfc_sleep_cmd_v6, 161 .wakeup_cmd = s5p_mfc_wakeup_cmd_v6, 162 .open_inst_cmd = s5p_mfc_open_inst_cmd_v6, 163 .close_inst_cmd = s5p_mfc_close_inst_cmd_v6, 164 }; 165 166 struct s5p_mfc_hw_cmds *s5p_mfc_init_hw_cmds_v6(void) 167 { 168 return &s5p_mfc_cmds_v6; 169 } 170