11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2e8454ff7SManjunatha Halli /* 3e8454ff7SManjunatha Halli * FM Driver for Connectivity chip of Texas Instruments. 4e8454ff7SManjunatha Halli * FM Common module header file 5e8454ff7SManjunatha Halli * 6e8454ff7SManjunatha Halli * Copyright (C) 2011 Texas Instruments 7e8454ff7SManjunatha Halli */ 8e8454ff7SManjunatha Halli 9e8454ff7SManjunatha Halli #ifndef _FMDRV_COMMON_H 10e8454ff7SManjunatha Halli #define _FMDRV_COMMON_H 11e8454ff7SManjunatha Halli 12e8454ff7SManjunatha Halli #define FM_ST_REG_TIMEOUT msecs_to_jiffies(6000) /* 6 sec */ 13e8454ff7SManjunatha Halli #define FM_PKT_LOGICAL_CHAN_NUMBER 0x08 /* Logical channel 8 */ 14e8454ff7SManjunatha Halli 15e8454ff7SManjunatha Halli #define REG_RD 0x1 16e8454ff7SManjunatha Halli #define REG_WR 0x0 17e8454ff7SManjunatha Halli 18e8454ff7SManjunatha Halli struct fm_reg_table { 19e8454ff7SManjunatha Halli u8 opcode; 20e8454ff7SManjunatha Halli u8 type; 21e8454ff7SManjunatha Halli u8 *name; 22e8454ff7SManjunatha Halli }; 23e8454ff7SManjunatha Halli 24e8454ff7SManjunatha Halli #define STEREO_GET 0 25e8454ff7SManjunatha Halli #define RSSI_LVL_GET 1 26e8454ff7SManjunatha Halli #define IF_COUNT_GET 2 27e8454ff7SManjunatha Halli #define FLAG_GET 3 28e8454ff7SManjunatha Halli #define RDS_SYNC_GET 4 29e8454ff7SManjunatha Halli #define RDS_DATA_GET 5 30e8454ff7SManjunatha Halli #define FREQ_SET 10 31e8454ff7SManjunatha Halli #define AF_FREQ_SET 11 32e8454ff7SManjunatha Halli #define MOST_MODE_SET 12 33e8454ff7SManjunatha Halli #define MOST_BLEND_SET 13 34e8454ff7SManjunatha Halli #define DEMPH_MODE_SET 14 35e8454ff7SManjunatha Halli #define SEARCH_LVL_SET 15 36e8454ff7SManjunatha Halli #define BAND_SET 16 37e8454ff7SManjunatha Halli #define MUTE_STATUS_SET 17 38e8454ff7SManjunatha Halli #define RDS_PAUSE_LVL_SET 18 39e8454ff7SManjunatha Halli #define RDS_PAUSE_DUR_SET 19 40e8454ff7SManjunatha Halli #define RDS_MEM_SET 20 41e8454ff7SManjunatha Halli #define RDS_BLK_B_SET 21 42e8454ff7SManjunatha Halli #define RDS_MSK_B_SET 22 43e8454ff7SManjunatha Halli #define RDS_PI_MASK_SET 23 44e8454ff7SManjunatha Halli #define RDS_PI_SET 24 45e8454ff7SManjunatha Halli #define RDS_SYSTEM_SET 25 46e8454ff7SManjunatha Halli #define INT_MASK_SET 26 47e8454ff7SManjunatha Halli #define SEARCH_DIR_SET 27 48e8454ff7SManjunatha Halli #define VOLUME_SET 28 49e8454ff7SManjunatha Halli #define AUDIO_ENABLE_SET 29 50e8454ff7SManjunatha Halli #define PCM_MODE_SET 30 51e8454ff7SManjunatha Halli #define I2S_MODE_CONFIG_SET 31 52e8454ff7SManjunatha Halli #define POWER_SET 32 53e8454ff7SManjunatha Halli #define INTX_CONFIG_SET 33 54e8454ff7SManjunatha Halli #define PULL_EN_SET 34 55e8454ff7SManjunatha Halli #define HILO_SET 35 56e8454ff7SManjunatha Halli #define SWITCH2FREF 36 57e8454ff7SManjunatha Halli #define FREQ_DRIFT_REPORT 37 58e8454ff7SManjunatha Halli 59e8454ff7SManjunatha Halli #define PCE_GET 40 60e8454ff7SManjunatha Halli #define FIRM_VER_GET 41 61e8454ff7SManjunatha Halli #define ASIC_VER_GET 42 62e8454ff7SManjunatha Halli #define ASIC_ID_GET 43 63e8454ff7SManjunatha Halli #define MAN_ID_GET 44 64e8454ff7SManjunatha Halli #define TUNER_MODE_SET 45 65e8454ff7SManjunatha Halli #define STOP_SEARCH 46 66e8454ff7SManjunatha Halli #define RDS_CNTRL_SET 47 67e8454ff7SManjunatha Halli 68e8454ff7SManjunatha Halli #define WRITE_HARDWARE_REG 100 69e8454ff7SManjunatha Halli #define CODE_DOWNLOAD 101 70e8454ff7SManjunatha Halli #define RESET 102 71e8454ff7SManjunatha Halli 72e8454ff7SManjunatha Halli #define FM_POWER_MODE 254 73e8454ff7SManjunatha Halli #define FM_INTERRUPT 255 74e8454ff7SManjunatha Halli 75e8454ff7SManjunatha Halli /* Transmitter API */ 76e8454ff7SManjunatha Halli 77e8454ff7SManjunatha Halli #define CHANL_SET 55 78e8454ff7SManjunatha Halli #define CHANL_BW_SET 56 79e8454ff7SManjunatha Halli #define REF_SET 57 80e8454ff7SManjunatha Halli #define POWER_ENB_SET 90 81e8454ff7SManjunatha Halli #define POWER_ATT_SET 58 82e8454ff7SManjunatha Halli #define POWER_LEV_SET 59 83e8454ff7SManjunatha Halli #define AUDIO_DEV_SET 60 84e8454ff7SManjunatha Halli #define PILOT_DEV_SET 61 85e8454ff7SManjunatha Halli #define RDS_DEV_SET 62 86e8454ff7SManjunatha Halli #define TX_BAND_SET 65 87e8454ff7SManjunatha Halli #define PUPD_SET 91 88e8454ff7SManjunatha Halli #define AUDIO_IO_SET 63 89e8454ff7SManjunatha Halli #define PREMPH_SET 64 90e8454ff7SManjunatha Halli #define MONO_SET 66 91e8454ff7SManjunatha Halli #define MUTE 92 92e8454ff7SManjunatha Halli #define MPX_LMT_ENABLE 67 93e8454ff7SManjunatha Halli #define PI_SET 93 94e8454ff7SManjunatha Halli #define ECC_SET 69 95e8454ff7SManjunatha Halli #define PTY 70 96e8454ff7SManjunatha Halli #define AF 71 97e8454ff7SManjunatha Halli #define DISPLAY_MODE 74 98e8454ff7SManjunatha Halli #define RDS_REP_SET 77 99e8454ff7SManjunatha Halli #define RDS_CONFIG_DATA_SET 98 100e8454ff7SManjunatha Halli #define RDS_DATA_SET 99 101e8454ff7SManjunatha Halli #define RDS_DATA_ENB 94 102e8454ff7SManjunatha Halli #define TA_SET 78 103e8454ff7SManjunatha Halli #define TP_SET 79 104e8454ff7SManjunatha Halli #define DI_SET 80 105e8454ff7SManjunatha Halli #define MS_SET 81 106e8454ff7SManjunatha Halli #define PS_SCROLL_SPEED 82 107e8454ff7SManjunatha Halli #define TX_AUDIO_LEVEL_TEST 96 108e8454ff7SManjunatha Halli #define TX_AUDIO_LEVEL_TEST_THRESHOLD 73 109e8454ff7SManjunatha Halli #define TX_AUDIO_INPUT_LEVEL_RANGE_SET 54 110e8454ff7SManjunatha Halli #define RX_ANTENNA_SELECT 87 111e8454ff7SManjunatha Halli #define I2C_DEV_ADDR_SET 86 112e8454ff7SManjunatha Halli #define REF_ERR_CALIB_PARAM_SET 88 113e8454ff7SManjunatha Halli #define REF_ERR_CALIB_PERIODICITY_SET 89 114e8454ff7SManjunatha Halli #define SOC_INT_TRIGGER 52 115e8454ff7SManjunatha Halli #define SOC_AUDIO_PATH_SET 83 116e8454ff7SManjunatha Halli #define SOC_PCMI_OVERRIDE 84 117e8454ff7SManjunatha Halli #define SOC_I2S_OVERRIDE 85 118e8454ff7SManjunatha Halli #define RSSI_BLOCK_SCAN_FREQ_SET 95 119e8454ff7SManjunatha Halli #define RSSI_BLOCK_SCAN_START 97 120e8454ff7SManjunatha Halli #define RSSI_BLOCK_SCAN_DATA_GET 5 121e8454ff7SManjunatha Halli #define READ_FMANT_TUNE_VALUE 104 122e8454ff7SManjunatha Halli 123e8454ff7SManjunatha Halli /* SKB helpers */ 124e8454ff7SManjunatha Halli struct fm_skb_cb { 125e8454ff7SManjunatha Halli __u8 fm_op; 126e8454ff7SManjunatha Halli struct completion *completion; 127e8454ff7SManjunatha Halli }; 128e8454ff7SManjunatha Halli 129e8454ff7SManjunatha Halli #define fm_cb(skb) ((struct fm_skb_cb *)(skb->cb)) 130e8454ff7SManjunatha Halli 131e8454ff7SManjunatha Halli /* FM Channel-8 command message format */ 132e8454ff7SManjunatha Halli struct fm_cmd_msg_hdr { 133e8454ff7SManjunatha Halli __u8 hdr; /* Logical Channel-8 */ 134e8454ff7SManjunatha Halli __u8 len; /* Number of bytes follows */ 135e8454ff7SManjunatha Halli __u8 op; /* FM Opcode */ 136e8454ff7SManjunatha Halli __u8 rd_wr; /* Read/Write command */ 137e8454ff7SManjunatha Halli __u8 dlen; /* Length of payload */ 138e8454ff7SManjunatha Halli } __attribute__ ((packed)); 139e8454ff7SManjunatha Halli 140e8454ff7SManjunatha Halli #define FM_CMD_MSG_HDR_SIZE 5 /* sizeof(struct fm_cmd_msg_hdr) */ 141e8454ff7SManjunatha Halli 142e8454ff7SManjunatha Halli /* FM Channel-8 event messgage format */ 143e8454ff7SManjunatha Halli struct fm_event_msg_hdr { 144e8454ff7SManjunatha Halli __u8 header; /* Logical Channel-8 */ 145e8454ff7SManjunatha Halli __u8 len; /* Number of bytes follows */ 146e8454ff7SManjunatha Halli __u8 status; /* Event status */ 147e8454ff7SManjunatha Halli __u8 num_fm_hci_cmds; /* Number of pkts the host allowed to send */ 148e8454ff7SManjunatha Halli __u8 op; /* FM Opcode */ 149e8454ff7SManjunatha Halli __u8 rd_wr; /* Read/Write command */ 150e8454ff7SManjunatha Halli __u8 dlen; /* Length of payload */ 151e8454ff7SManjunatha Halli } __attribute__ ((packed)); 152e8454ff7SManjunatha Halli 153e8454ff7SManjunatha Halli #define FM_EVT_MSG_HDR_SIZE 7 /* sizeof(struct fm_event_msg_hdr) */ 154e8454ff7SManjunatha Halli 155e8454ff7SManjunatha Halli /* TI's magic number in firmware file */ 156e8454ff7SManjunatha Halli #define FM_FW_FILE_HEADER_MAGIC 0x42535442 157e8454ff7SManjunatha Halli 158e8454ff7SManjunatha Halli #define FM_ENABLE 1 159e8454ff7SManjunatha Halli #define FM_DISABLE 0 160e8454ff7SManjunatha Halli 161e8454ff7SManjunatha Halli /* FLAG_GET register bits */ 162*cce8cccaSMauro Carvalho Chehab #define FM_FR_EVENT BIT(0) 163*cce8cccaSMauro Carvalho Chehab #define FM_BL_EVENT BIT(1) 164*cce8cccaSMauro Carvalho Chehab #define FM_RDS_EVENT BIT(2) 165*cce8cccaSMauro Carvalho Chehab #define FM_BBLK_EVENT BIT(3) 166*cce8cccaSMauro Carvalho Chehab #define FM_LSYNC_EVENT BIT(4) 167*cce8cccaSMauro Carvalho Chehab #define FM_LEV_EVENT BIT(5) 168*cce8cccaSMauro Carvalho Chehab #define FM_IFFR_EVENT BIT(6) 169*cce8cccaSMauro Carvalho Chehab #define FM_PI_EVENT BIT(7) 170*cce8cccaSMauro Carvalho Chehab #define FM_PD_EVENT BIT(8) 171*cce8cccaSMauro Carvalho Chehab #define FM_STIC_EVENT BIT(9) 172*cce8cccaSMauro Carvalho Chehab #define FM_MAL_EVENT BIT(10) 173*cce8cccaSMauro Carvalho Chehab #define FM_POW_ENB_EVENT BIT(11) 174e8454ff7SManjunatha Halli 175e8454ff7SManjunatha Halli /* 176e8454ff7SManjunatha Halli * Firmware files of FM. ASIC ID and ASIC version will be appened to this, 177e8454ff7SManjunatha Halli * later. 178e8454ff7SManjunatha Halli */ 179e8454ff7SManjunatha Halli #define FM_FMC_FW_FILE_START ("fmc_ch8") 180e8454ff7SManjunatha Halli #define FM_RX_FW_FILE_START ("fm_rx_ch8") 181e8454ff7SManjunatha Halli #define FM_TX_FW_FILE_START ("fm_tx_ch8") 182e8454ff7SManjunatha Halli 183e8454ff7SManjunatha Halli #define FM_UNDEFINED_FREQ 0xFFFFFFFF 184e8454ff7SManjunatha Halli 185e8454ff7SManjunatha Halli /* Band types */ 186e8454ff7SManjunatha Halli #define FM_BAND_EUROPE_US 0 187e8454ff7SManjunatha Halli #define FM_BAND_JAPAN 1 188e8454ff7SManjunatha Halli 189e8454ff7SManjunatha Halli /* Seek directions */ 190e8454ff7SManjunatha Halli #define FM_SEARCH_DIRECTION_DOWN 0 191e8454ff7SManjunatha Halli #define FM_SEARCH_DIRECTION_UP 1 192e8454ff7SManjunatha Halli 193e8454ff7SManjunatha Halli /* Tunner modes */ 194e8454ff7SManjunatha Halli #define FM_TUNER_STOP_SEARCH_MODE 0 195e8454ff7SManjunatha Halli #define FM_TUNER_PRESET_MODE 1 196e8454ff7SManjunatha Halli #define FM_TUNER_AUTONOMOUS_SEARCH_MODE 2 197e8454ff7SManjunatha Halli #define FM_TUNER_AF_JUMP_MODE 3 198e8454ff7SManjunatha Halli 199e8454ff7SManjunatha Halli /* Min and Max volume */ 200e8454ff7SManjunatha Halli #define FM_RX_VOLUME_MIN 0 201e8454ff7SManjunatha Halli #define FM_RX_VOLUME_MAX 70 202e8454ff7SManjunatha Halli 203e8454ff7SManjunatha Halli /* Volume gain step */ 204e8454ff7SManjunatha Halli #define FM_RX_VOLUME_GAIN_STEP 0x370 205e8454ff7SManjunatha Halli 206e8454ff7SManjunatha Halli /* Mute modes */ 207e8454ff7SManjunatha Halli #define FM_MUTE_ON 0 208e8454ff7SManjunatha Halli #define FM_MUTE_OFF 1 209e8454ff7SManjunatha Halli #define FM_MUTE_ATTENUATE 2 210e8454ff7SManjunatha Halli 211e8454ff7SManjunatha Halli #define FM_RX_UNMUTE_MODE 0x00 212e8454ff7SManjunatha Halli #define FM_RX_RF_DEP_MODE 0x01 213e8454ff7SManjunatha Halli #define FM_RX_AC_MUTE_MODE 0x02 214e8454ff7SManjunatha Halli #define FM_RX_HARD_MUTE_LEFT_MODE 0x04 215e8454ff7SManjunatha Halli #define FM_RX_HARD_MUTE_RIGHT_MODE 0x08 216e8454ff7SManjunatha Halli #define FM_RX_SOFT_MUTE_FORCE_MODE 0x10 217e8454ff7SManjunatha Halli 218e8454ff7SManjunatha Halli /* RF dependent mute mode */ 219e8454ff7SManjunatha Halli #define FM_RX_RF_DEPENDENT_MUTE_ON 1 220e8454ff7SManjunatha Halli #define FM_RX_RF_DEPENDENT_MUTE_OFF 0 221e8454ff7SManjunatha Halli 222e8454ff7SManjunatha Halli /* RSSI threshold min and max */ 223e8454ff7SManjunatha Halli #define FM_RX_RSSI_THRESHOLD_MIN -128 224e8454ff7SManjunatha Halli #define FM_RX_RSSI_THRESHOLD_MAX 127 225e8454ff7SManjunatha Halli 226e8454ff7SManjunatha Halli /* Stereo/Mono mode */ 227e8454ff7SManjunatha Halli #define FM_STEREO_MODE 0 228e8454ff7SManjunatha Halli #define FM_MONO_MODE 1 229e8454ff7SManjunatha Halli #define FM_STEREO_SOFT_BLEND 1 230e8454ff7SManjunatha Halli 231e8454ff7SManjunatha Halli /* FM RX De-emphasis filter modes */ 232e8454ff7SManjunatha Halli #define FM_RX_EMPHASIS_FILTER_50_USEC 0 233e8454ff7SManjunatha Halli #define FM_RX_EMPHASIS_FILTER_75_USEC 1 234e8454ff7SManjunatha Halli 235e8454ff7SManjunatha Halli /* FM RDS modes */ 236e8454ff7SManjunatha Halli #define FM_RDS_DISABLE 0 237e8454ff7SManjunatha Halli #define FM_RDS_ENABLE 1 238e8454ff7SManjunatha Halli 239e8454ff7SManjunatha Halli #define FM_NO_PI_CODE 0 240e8454ff7SManjunatha Halli 241e8454ff7SManjunatha Halli /* FM and RX RDS block enable/disable */ 242e8454ff7SManjunatha Halli #define FM_RX_PWR_SET_FM_ON_RDS_OFF 0x1 243e8454ff7SManjunatha Halli #define FM_RX_PWR_SET_FM_AND_RDS_BLK_ON 0x3 244e8454ff7SManjunatha Halli #define FM_RX_PWR_SET_FM_AND_RDS_BLK_OFF 0x0 245e8454ff7SManjunatha Halli 246e8454ff7SManjunatha Halli /* RX RDS */ 247e8454ff7SManjunatha Halli #define FM_RX_RDS_FLUSH_FIFO 0x1 248e8454ff7SManjunatha Halli #define FM_RX_RDS_FIFO_THRESHOLD 64 /* tuples */ 249e8454ff7SManjunatha Halli #define FM_RDS_BLK_SIZE 3 /* 3 bytes */ 250e8454ff7SManjunatha Halli 251e8454ff7SManjunatha Halli /* RDS block types */ 252e8454ff7SManjunatha Halli #define FM_RDS_BLOCK_A 0 253e8454ff7SManjunatha Halli #define FM_RDS_BLOCK_B 1 254e8454ff7SManjunatha Halli #define FM_RDS_BLOCK_C 2 255e8454ff7SManjunatha Halli #define FM_RDS_BLOCK_Ctag 3 256e8454ff7SManjunatha Halli #define FM_RDS_BLOCK_D 4 257e8454ff7SManjunatha Halli #define FM_RDS_BLOCK_E 5 258e8454ff7SManjunatha Halli 259e8454ff7SManjunatha Halli #define FM_RDS_BLK_IDX_A 0 260e8454ff7SManjunatha Halli #define FM_RDS_BLK_IDX_B 1 261e8454ff7SManjunatha Halli #define FM_RDS_BLK_IDX_C 2 262e8454ff7SManjunatha Halli #define FM_RDS_BLK_IDX_D 3 263e8454ff7SManjunatha Halli #define FM_RDS_BLK_IDX_UNKNOWN 0xF0 264e8454ff7SManjunatha Halli 265e8454ff7SManjunatha Halli #define FM_RDS_STATUS_ERR_MASK 0x18 266e8454ff7SManjunatha Halli 267e8454ff7SManjunatha Halli /* 268e8454ff7SManjunatha Halli * Represents an RDS group type & version. 269e8454ff7SManjunatha Halli * There are 15 groups, each group has 2 versions: A and B. 270e8454ff7SManjunatha Halli */ 271*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_0A BIT(0) 272*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_0B BIT(1) 273*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_1A BIT(2) 274*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_1B BIT(3) 275*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_2A BIT(4) 276*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_2B BIT(5) 277*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_3A BIT(6) 278*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_3B BIT(7) 279*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_4A BIT(8) 280*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_4B BIT(9) 281*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_5A BIT(10) 282*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_5B BIT(11) 283*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_6A BIT(12) 284*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_6B BIT(13) 285*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_7A BIT(14) 286*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_7B BIT(15) 287*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_8A BIT(16) 288*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_8B BIT(17) 289*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_9A BIT(18) 290*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_9B BIT(19) 291*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_10A BIT(20) 292*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_10B BIT(21) 293*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_11A BIT(22) 294*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_11B BIT(23) 295*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_12A BIT(24) 296*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_12B BIT(25) 297*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_13A BIT(26) 298*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_13B BIT(27) 299*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_14A BIT(28) 300*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_14B BIT(29) 301*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_15A BIT(30) 302*cce8cccaSMauro Carvalho Chehab #define FM_RDS_GROUP_TYPE_MASK_15B BIT(31) 303e8454ff7SManjunatha Halli 304e8454ff7SManjunatha Halli /* RX Alternate Frequency info */ 305e8454ff7SManjunatha Halli #define FM_RDS_MIN_AF 1 306e8454ff7SManjunatha Halli #define FM_RDS_MAX_AF 204 307e8454ff7SManjunatha Halli #define FM_RDS_MAX_AF_JAPAN 140 308e8454ff7SManjunatha Halli #define FM_RDS_1_AF_FOLLOWS 225 309e8454ff7SManjunatha Halli #define FM_RDS_25_AF_FOLLOWS 249 310e8454ff7SManjunatha Halli 311e8454ff7SManjunatha Halli /* RDS system type (RDS/RBDS) */ 312e8454ff7SManjunatha Halli #define FM_RDS_SYSTEM_RDS 0 313e8454ff7SManjunatha Halli #define FM_RDS_SYSTEM_RBDS 1 314e8454ff7SManjunatha Halli 315e8454ff7SManjunatha Halli /* AF on/off */ 316e8454ff7SManjunatha Halli #define FM_RX_RDS_AF_SWITCH_MODE_ON 1 317e8454ff7SManjunatha Halli #define FM_RX_RDS_AF_SWITCH_MODE_OFF 0 318e8454ff7SManjunatha Halli 319e8454ff7SManjunatha Halli /* Retry count when interrupt process goes wrong */ 320e8454ff7SManjunatha Halli #define FM_IRQ_TIMEOUT_RETRY_MAX 5 /* 5 times */ 321e8454ff7SManjunatha Halli 322e8454ff7SManjunatha Halli /* Audio IO set values */ 323e8454ff7SManjunatha Halli #define FM_RX_AUDIO_ENABLE_I2S 0x01 324e8454ff7SManjunatha Halli #define FM_RX_AUDIO_ENABLE_ANALOG 0x02 325e8454ff7SManjunatha Halli #define FM_RX_AUDIO_ENABLE_I2S_AND_ANALOG 0x03 326e8454ff7SManjunatha Halli #define FM_RX_AUDIO_ENABLE_DISABLE 0x00 327e8454ff7SManjunatha Halli 328e8454ff7SManjunatha Halli /* HI/LO set values */ 329e8454ff7SManjunatha Halli #define FM_RX_IFFREQ_TO_HI_SIDE 0x0 330e8454ff7SManjunatha Halli #define FM_RX_IFFREQ_TO_LO_SIDE 0x1 331e8454ff7SManjunatha Halli #define FM_RX_IFFREQ_HILO_AUTOMATIC 0x2 332e8454ff7SManjunatha Halli 333e8454ff7SManjunatha Halli /* 334e8454ff7SManjunatha Halli * Default RX mode configuration. Chip will be configured 335e8454ff7SManjunatha Halli * with this default values after loading RX firmware. 336e8454ff7SManjunatha Halli */ 337e8454ff7SManjunatha Halli #define FM_DEFAULT_RX_VOLUME 10 338e8454ff7SManjunatha Halli #define FM_DEFAULT_RSSI_THRESHOLD 3 339e8454ff7SManjunatha Halli 340e8454ff7SManjunatha Halli /* Range for TX power level in units for dB/uV */ 341e8454ff7SManjunatha Halli #define FM_PWR_LVL_LOW 91 342e8454ff7SManjunatha Halli #define FM_PWR_LVL_HIGH 122 343e8454ff7SManjunatha Halli 344e8454ff7SManjunatha Halli /* Chip specific default TX power level value */ 345e8454ff7SManjunatha Halli #define FM_PWR_LVL_DEF 4 346e8454ff7SManjunatha Halli 347e8454ff7SManjunatha Halli /* FM TX Pre-emphasis filter values */ 348e8454ff7SManjunatha Halli #define FM_TX_PREEMPH_OFF 1 349e8454ff7SManjunatha Halli #define FM_TX_PREEMPH_50US 0 350e8454ff7SManjunatha Halli #define FM_TX_PREEMPH_75US 2 351e8454ff7SManjunatha Halli 35225985edcSLucas De Marchi /* FM TX antenna impedance values */ 353e8454ff7SManjunatha Halli #define FM_TX_ANT_IMP_50 0 354e8454ff7SManjunatha Halli #define FM_TX_ANT_IMP_200 1 355e8454ff7SManjunatha Halli #define FM_TX_ANT_IMP_500 2 356e8454ff7SManjunatha Halli 357e8454ff7SManjunatha Halli /* Functions exported by FM common sub-module */ 358a6127803SXi Wang int fmc_prepare(struct fmdev *); 359a6127803SXi Wang int fmc_release(struct fmdev *); 360e8454ff7SManjunatha Halli 361e8454ff7SManjunatha Halli void fmc_update_region_info(struct fmdev *, u8); 362a6127803SXi Wang int fmc_send_cmd(struct fmdev *, u8, u16, 363e8454ff7SManjunatha Halli void *, unsigned int, void *, int *); 364a6127803SXi Wang int fmc_is_rds_data_available(struct fmdev *, struct file *, 365e8454ff7SManjunatha Halli struct poll_table_struct *); 366a6127803SXi Wang int fmc_transfer_rds_from_internal_buff(struct fmdev *, struct file *, 367e8454ff7SManjunatha Halli u8 __user *, size_t); 368e8454ff7SManjunatha Halli 369a6127803SXi Wang int fmc_set_freq(struct fmdev *, u32); 370a6127803SXi Wang int fmc_set_mode(struct fmdev *, u8); 371a6127803SXi Wang int fmc_set_region(struct fmdev *, u8); 372a6127803SXi Wang int fmc_set_mute_mode(struct fmdev *, u8); 373a6127803SXi Wang int fmc_set_stereo_mono(struct fmdev *, u16); 374a6127803SXi Wang int fmc_set_rds_mode(struct fmdev *, u8); 375e8454ff7SManjunatha Halli 376a6127803SXi Wang int fmc_get_freq(struct fmdev *, u32 *); 377a6127803SXi Wang int fmc_get_region(struct fmdev *, u8 *); 378a6127803SXi Wang int fmc_get_mode(struct fmdev *, u8 *); 379e8454ff7SManjunatha Halli 380e8454ff7SManjunatha Halli /* 381e8454ff7SManjunatha Halli * channel spacing 382e8454ff7SManjunatha Halli */ 383e8454ff7SManjunatha Halli #define FM_CHANNEL_SPACING_50KHZ 1 384e8454ff7SManjunatha Halli #define FM_CHANNEL_SPACING_100KHZ 2 385e8454ff7SManjunatha Halli #define FM_CHANNEL_SPACING_200KHZ 4 386e8454ff7SManjunatha Halli #define FM_FREQ_MUL 50 387e8454ff7SManjunatha Halli 388e8454ff7SManjunatha Halli #endif 389e8454ff7SManjunatha Halli 390