1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Tegra20 External Memory Controller driver 4 * 5 * Author: Dmitry Osipenko <digetx@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk/tegra.h> 10 #include <linux/completion.h> 11 #include <linux/debugfs.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/sort.h> 20 #include <linux/types.h> 21 22 #include <soc/tegra/fuse.h> 23 24 #define EMC_INTSTATUS 0x000 25 #define EMC_INTMASK 0x004 26 #define EMC_DBG 0x008 27 #define EMC_TIMING_CONTROL 0x028 28 #define EMC_RC 0x02c 29 #define EMC_RFC 0x030 30 #define EMC_RAS 0x034 31 #define EMC_RP 0x038 32 #define EMC_R2W 0x03c 33 #define EMC_W2R 0x040 34 #define EMC_R2P 0x044 35 #define EMC_W2P 0x048 36 #define EMC_RD_RCD 0x04c 37 #define EMC_WR_RCD 0x050 38 #define EMC_RRD 0x054 39 #define EMC_REXT 0x058 40 #define EMC_WDV 0x05c 41 #define EMC_QUSE 0x060 42 #define EMC_QRST 0x064 43 #define EMC_QSAFE 0x068 44 #define EMC_RDV 0x06c 45 #define EMC_REFRESH 0x070 46 #define EMC_BURST_REFRESH_NUM 0x074 47 #define EMC_PDEX2WR 0x078 48 #define EMC_PDEX2RD 0x07c 49 #define EMC_PCHG2PDEN 0x080 50 #define EMC_ACT2PDEN 0x084 51 #define EMC_AR2PDEN 0x088 52 #define EMC_RW2PDEN 0x08c 53 #define EMC_TXSR 0x090 54 #define EMC_TCKE 0x094 55 #define EMC_TFAW 0x098 56 #define EMC_TRPAB 0x09c 57 #define EMC_TCLKSTABLE 0x0a0 58 #define EMC_TCLKSTOP 0x0a4 59 #define EMC_TREFBW 0x0a8 60 #define EMC_QUSE_EXTRA 0x0ac 61 #define EMC_ODT_WRITE 0x0b0 62 #define EMC_ODT_READ 0x0b4 63 #define EMC_FBIO_CFG5 0x104 64 #define EMC_FBIO_CFG6 0x114 65 #define EMC_AUTO_CAL_INTERVAL 0x2a8 66 #define EMC_CFG_2 0x2b8 67 #define EMC_CFG_DIG_DLL 0x2bc 68 #define EMC_DLL_XFORM_DQS 0x2c0 69 #define EMC_DLL_XFORM_QUSE 0x2c4 70 #define EMC_ZCAL_REF_CNT 0x2e0 71 #define EMC_ZCAL_WAIT_CNT 0x2e4 72 #define EMC_CFG_CLKTRIM_0 0x2d0 73 #define EMC_CFG_CLKTRIM_1 0x2d4 74 #define EMC_CFG_CLKTRIM_2 0x2d8 75 76 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0) 77 #define EMC_CLKCHANGE_PD_ENABLE BIT(1) 78 #define EMC_CLKCHANGE_SR_ENABLE BIT(2) 79 80 #define EMC_TIMING_UPDATE BIT(0) 81 82 #define EMC_REFRESH_OVERFLOW_INT BIT(3) 83 #define EMC_CLKCHANGE_COMPLETE_INT BIT(4) 84 85 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0) 86 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) 87 #define EMC_DBG_FORCE_UPDATE BIT(2) 88 #define EMC_DBG_READ_DQM_CTRL BIT(9) 89 #define EMC_DBG_CFG_PRIORITY BIT(24) 90 91 static const u16 emc_timing_registers[] = { 92 EMC_RC, 93 EMC_RFC, 94 EMC_RAS, 95 EMC_RP, 96 EMC_R2W, 97 EMC_W2R, 98 EMC_R2P, 99 EMC_W2P, 100 EMC_RD_RCD, 101 EMC_WR_RCD, 102 EMC_RRD, 103 EMC_REXT, 104 EMC_WDV, 105 EMC_QUSE, 106 EMC_QRST, 107 EMC_QSAFE, 108 EMC_RDV, 109 EMC_REFRESH, 110 EMC_BURST_REFRESH_NUM, 111 EMC_PDEX2WR, 112 EMC_PDEX2RD, 113 EMC_PCHG2PDEN, 114 EMC_ACT2PDEN, 115 EMC_AR2PDEN, 116 EMC_RW2PDEN, 117 EMC_TXSR, 118 EMC_TCKE, 119 EMC_TFAW, 120 EMC_TRPAB, 121 EMC_TCLKSTABLE, 122 EMC_TCLKSTOP, 123 EMC_TREFBW, 124 EMC_QUSE_EXTRA, 125 EMC_FBIO_CFG6, 126 EMC_ODT_WRITE, 127 EMC_ODT_READ, 128 EMC_FBIO_CFG5, 129 EMC_CFG_DIG_DLL, 130 EMC_DLL_XFORM_DQS, 131 EMC_DLL_XFORM_QUSE, 132 EMC_ZCAL_REF_CNT, 133 EMC_ZCAL_WAIT_CNT, 134 EMC_AUTO_CAL_INTERVAL, 135 EMC_CFG_CLKTRIM_0, 136 EMC_CFG_CLKTRIM_1, 137 EMC_CFG_CLKTRIM_2, 138 }; 139 140 struct emc_timing { 141 unsigned long rate; 142 u32 data[ARRAY_SIZE(emc_timing_registers)]; 143 }; 144 145 struct tegra_emc { 146 struct device *dev; 147 struct completion clk_handshake_complete; 148 struct notifier_block clk_nb; 149 struct clk *clk; 150 void __iomem *regs; 151 152 struct emc_timing *timings; 153 unsigned int num_timings; 154 155 struct { 156 struct dentry *root; 157 unsigned long min_rate; 158 unsigned long max_rate; 159 } debugfs; 160 }; 161 162 static irqreturn_t tegra_emc_isr(int irq, void *data) 163 { 164 struct tegra_emc *emc = data; 165 u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT; 166 u32 status; 167 168 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; 169 if (!status) 170 return IRQ_NONE; 171 172 /* notify about EMC-CAR handshake completion */ 173 if (status & EMC_CLKCHANGE_COMPLETE_INT) 174 complete(&emc->clk_handshake_complete); 175 176 /* notify about HW problem */ 177 if (status & EMC_REFRESH_OVERFLOW_INT) 178 dev_err_ratelimited(emc->dev, 179 "refresh request overflow timeout\n"); 180 181 /* clear interrupts */ 182 writel_relaxed(status, emc->regs + EMC_INTSTATUS); 183 184 return IRQ_HANDLED; 185 } 186 187 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, 188 unsigned long rate) 189 { 190 struct emc_timing *timing = NULL; 191 unsigned int i; 192 193 for (i = 0; i < emc->num_timings; i++) { 194 if (emc->timings[i].rate >= rate) { 195 timing = &emc->timings[i]; 196 break; 197 } 198 } 199 200 if (!timing) { 201 dev_err(emc->dev, "no timing for rate %lu\n", rate); 202 return NULL; 203 } 204 205 return timing; 206 } 207 208 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) 209 { 210 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); 211 unsigned int i; 212 213 if (!timing) 214 return -EINVAL; 215 216 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", 217 __func__, timing->rate, rate); 218 219 /* program shadow registers */ 220 for (i = 0; i < ARRAY_SIZE(timing->data); i++) 221 writel_relaxed(timing->data[i], 222 emc->regs + emc_timing_registers[i]); 223 224 /* wait until programming has settled */ 225 readl_relaxed(emc->regs + emc_timing_registers[i - 1]); 226 227 reinit_completion(&emc->clk_handshake_complete); 228 229 return 0; 230 } 231 232 static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) 233 { 234 unsigned long timeout; 235 236 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); 237 238 if (flush) { 239 /* manually initiate memory timing update */ 240 writel_relaxed(EMC_TIMING_UPDATE, 241 emc->regs + EMC_TIMING_CONTROL); 242 return 0; 243 } 244 245 timeout = wait_for_completion_timeout(&emc->clk_handshake_complete, 246 msecs_to_jiffies(100)); 247 if (timeout == 0) { 248 dev_err(emc->dev, "EMC-CAR handshake failed\n"); 249 return -EIO; 250 } 251 252 return 0; 253 } 254 255 static int tegra_emc_clk_change_notify(struct notifier_block *nb, 256 unsigned long msg, void *data) 257 { 258 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); 259 struct clk_notifier_data *cnd = data; 260 int err; 261 262 switch (msg) { 263 case PRE_RATE_CHANGE: 264 err = emc_prepare_timing_change(emc, cnd->new_rate); 265 break; 266 267 case ABORT_RATE_CHANGE: 268 err = emc_prepare_timing_change(emc, cnd->old_rate); 269 if (err) 270 break; 271 272 err = emc_complete_timing_change(emc, true); 273 break; 274 275 case POST_RATE_CHANGE: 276 err = emc_complete_timing_change(emc, false); 277 break; 278 279 default: 280 return NOTIFY_DONE; 281 } 282 283 return notifier_from_errno(err); 284 } 285 286 static int load_one_timing_from_dt(struct tegra_emc *emc, 287 struct emc_timing *timing, 288 struct device_node *node) 289 { 290 u32 rate; 291 int err; 292 293 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { 294 dev_err(emc->dev, "incompatible DT node: %pOF\n", node); 295 return -EINVAL; 296 } 297 298 err = of_property_read_u32(node, "clock-frequency", &rate); 299 if (err) { 300 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", 301 node, err); 302 return err; 303 } 304 305 err = of_property_read_u32_array(node, "nvidia,emc-registers", 306 timing->data, 307 ARRAY_SIZE(emc_timing_registers)); 308 if (err) { 309 dev_err(emc->dev, 310 "timing %pOF: failed to read emc timing data: %d\n", 311 node, err); 312 return err; 313 } 314 315 /* 316 * The EMC clock rate is twice the bus rate, and the bus rate is 317 * measured in kHz. 318 */ 319 timing->rate = rate * 2 * 1000; 320 321 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n", 322 __func__, node, timing->rate); 323 324 return 0; 325 } 326 327 static int cmp_timings(const void *_a, const void *_b) 328 { 329 const struct emc_timing *a = _a; 330 const struct emc_timing *b = _b; 331 332 if (a->rate < b->rate) 333 return -1; 334 335 if (a->rate > b->rate) 336 return 1; 337 338 return 0; 339 } 340 341 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, 342 struct device_node *node) 343 { 344 struct device_node *child; 345 struct emc_timing *timing; 346 int child_count; 347 int err; 348 349 child_count = of_get_child_count(node); 350 if (!child_count) { 351 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node); 352 return -EINVAL; 353 } 354 355 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), 356 GFP_KERNEL); 357 if (!emc->timings) 358 return -ENOMEM; 359 360 emc->num_timings = child_count; 361 timing = emc->timings; 362 363 for_each_child_of_node(node, child) { 364 err = load_one_timing_from_dt(emc, timing++, child); 365 if (err) { 366 of_node_put(child); 367 return err; 368 } 369 } 370 371 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, 372 NULL); 373 374 dev_info(emc->dev, 375 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", 376 emc->num_timings, 377 tegra_read_ram_code(), 378 emc->timings[0].rate / 1000000, 379 emc->timings[emc->num_timings - 1].rate / 1000000); 380 381 return 0; 382 } 383 384 static struct device_node * 385 tegra_emc_find_node_by_ram_code(struct device *dev) 386 { 387 struct device_node *np; 388 u32 value, ram_code; 389 int err; 390 391 if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) 392 return of_node_get(dev->of_node); 393 394 ram_code = tegra_read_ram_code(); 395 396 for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np; 397 np = of_find_node_by_name(np, "emc-tables")) { 398 err = of_property_read_u32(np, "nvidia,ram-code", &value); 399 if (err || value != ram_code) { 400 of_node_put(np); 401 continue; 402 } 403 404 return np; 405 } 406 407 dev_err(dev, "no memory timings for RAM code %u found in device tree\n", 408 ram_code); 409 410 return NULL; 411 } 412 413 static int emc_setup_hw(struct tegra_emc *emc) 414 { 415 u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT; 416 u32 emc_cfg, emc_dbg; 417 418 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); 419 420 /* 421 * Depending on a memory type, DRAM should enter either self-refresh 422 * or power-down state on EMC clock change. 423 */ 424 if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && 425 !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { 426 dev_err(emc->dev, 427 "bootloader didn't specify DRAM auto-suspend mode\n"); 428 return -EINVAL; 429 } 430 431 /* enable EMC and CAR to handshake on PLL divider/source changes */ 432 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; 433 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); 434 435 /* initialize interrupt */ 436 writel_relaxed(intmask, emc->regs + EMC_INTMASK); 437 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); 438 439 /* ensure that unwanted debug features are disabled */ 440 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 441 emc_dbg |= EMC_DBG_CFG_PRIORITY; 442 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; 443 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; 444 emc_dbg &= ~EMC_DBG_FORCE_UPDATE; 445 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 446 447 return 0; 448 } 449 450 static long emc_round_rate(unsigned long rate, 451 unsigned long min_rate, 452 unsigned long max_rate, 453 void *arg) 454 { 455 struct emc_timing *timing = NULL; 456 struct tegra_emc *emc = arg; 457 unsigned int i; 458 459 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); 460 461 for (i = 0; i < emc->num_timings; i++) { 462 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) 463 continue; 464 465 if (emc->timings[i].rate > max_rate) { 466 i = max(i, 1u) - 1; 467 468 if (emc->timings[i].rate < min_rate) 469 break; 470 } 471 472 if (emc->timings[i].rate < min_rate) 473 continue; 474 475 timing = &emc->timings[i]; 476 break; 477 } 478 479 if (!timing) { 480 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", 481 rate, min_rate, max_rate); 482 return -EINVAL; 483 } 484 485 return timing->rate; 486 } 487 488 /* 489 * debugfs interface 490 * 491 * The memory controller driver exposes some files in debugfs that can be used 492 * to control the EMC frequency. The top-level directory can be found here: 493 * 494 * /sys/kernel/debug/emc 495 * 496 * It contains the following files: 497 * 498 * - available_rates: This file contains a list of valid, space-separated 499 * EMC frequencies. 500 * 501 * - min_rate: Writing a value to this file sets the given frequency as the 502 * floor of the permitted range. If this is higher than the currently 503 * configured EMC frequency, this will cause the frequency to be 504 * increased so that it stays within the valid range. 505 * 506 * - max_rate: Similarily to the min_rate file, writing a value to this file 507 * sets the given frequency as the ceiling of the permitted range. If 508 * the value is lower than the currently configured EMC frequency, this 509 * will cause the frequency to be decreased so that it stays within the 510 * valid range. 511 */ 512 513 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) 514 { 515 unsigned int i; 516 517 for (i = 0; i < emc->num_timings; i++) 518 if (rate == emc->timings[i].rate) 519 return true; 520 521 return false; 522 } 523 524 static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data) 525 { 526 struct tegra_emc *emc = s->private; 527 const char *prefix = ""; 528 unsigned int i; 529 530 for (i = 0; i < emc->num_timings; i++) { 531 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); 532 prefix = " "; 533 } 534 535 seq_puts(s, "\n"); 536 537 return 0; 538 } 539 540 static int tegra_emc_debug_available_rates_open(struct inode *inode, 541 struct file *file) 542 { 543 return single_open(file, tegra_emc_debug_available_rates_show, 544 inode->i_private); 545 } 546 547 static const struct file_operations tegra_emc_debug_available_rates_fops = { 548 .open = tegra_emc_debug_available_rates_open, 549 .read = seq_read, 550 .llseek = seq_lseek, 551 .release = single_release, 552 }; 553 554 static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) 555 { 556 struct tegra_emc *emc = data; 557 558 *rate = emc->debugfs.min_rate; 559 560 return 0; 561 } 562 563 static int tegra_emc_debug_min_rate_set(void *data, u64 rate) 564 { 565 struct tegra_emc *emc = data; 566 int err; 567 568 if (!tegra_emc_validate_rate(emc, rate)) 569 return -EINVAL; 570 571 err = clk_set_min_rate(emc->clk, rate); 572 if (err < 0) 573 return err; 574 575 emc->debugfs.min_rate = rate; 576 577 return 0; 578 } 579 580 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops, 581 tegra_emc_debug_min_rate_get, 582 tegra_emc_debug_min_rate_set, "%llu\n"); 583 584 static int tegra_emc_debug_max_rate_get(void *data, u64 *rate) 585 { 586 struct tegra_emc *emc = data; 587 588 *rate = emc->debugfs.max_rate; 589 590 return 0; 591 } 592 593 static int tegra_emc_debug_max_rate_set(void *data, u64 rate) 594 { 595 struct tegra_emc *emc = data; 596 int err; 597 598 if (!tegra_emc_validate_rate(emc, rate)) 599 return -EINVAL; 600 601 err = clk_set_max_rate(emc->clk, rate); 602 if (err < 0) 603 return err; 604 605 emc->debugfs.max_rate = rate; 606 607 return 0; 608 } 609 610 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops, 611 tegra_emc_debug_max_rate_get, 612 tegra_emc_debug_max_rate_set, "%llu\n"); 613 614 static void tegra_emc_debugfs_init(struct tegra_emc *emc) 615 { 616 struct device *dev = emc->dev; 617 unsigned int i; 618 int err; 619 620 emc->debugfs.min_rate = ULONG_MAX; 621 emc->debugfs.max_rate = 0; 622 623 for (i = 0; i < emc->num_timings; i++) { 624 if (emc->timings[i].rate < emc->debugfs.min_rate) 625 emc->debugfs.min_rate = emc->timings[i].rate; 626 627 if (emc->timings[i].rate > emc->debugfs.max_rate) 628 emc->debugfs.max_rate = emc->timings[i].rate; 629 } 630 631 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, 632 emc->debugfs.max_rate); 633 if (err < 0) { 634 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", 635 emc->debugfs.min_rate, emc->debugfs.max_rate, 636 emc->clk); 637 } 638 639 emc->debugfs.root = debugfs_create_dir("emc", NULL); 640 if (!emc->debugfs.root) { 641 dev_err(emc->dev, "failed to create debugfs directory\n"); 642 return; 643 } 644 645 debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, 646 emc, &tegra_emc_debug_available_rates_fops); 647 debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, 648 emc, &tegra_emc_debug_min_rate_fops); 649 debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, 650 emc, &tegra_emc_debug_max_rate_fops); 651 } 652 653 static int tegra_emc_probe(struct platform_device *pdev) 654 { 655 struct device_node *np; 656 struct tegra_emc *emc; 657 struct resource *res; 658 int irq, err; 659 660 /* driver has nothing to do in a case of memory timing absence */ 661 if (of_get_child_count(pdev->dev.of_node) == 0) { 662 dev_info(&pdev->dev, 663 "EMC device tree node doesn't have memory timings\n"); 664 return 0; 665 } 666 667 irq = platform_get_irq(pdev, 0); 668 if (irq < 0) { 669 dev_err(&pdev->dev, "interrupt not specified\n"); 670 dev_err(&pdev->dev, "please update your device tree\n"); 671 return irq; 672 } 673 674 np = tegra_emc_find_node_by_ram_code(&pdev->dev); 675 if (!np) 676 return -EINVAL; 677 678 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); 679 if (!emc) { 680 of_node_put(np); 681 return -ENOMEM; 682 } 683 684 init_completion(&emc->clk_handshake_complete); 685 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; 686 emc->dev = &pdev->dev; 687 688 err = tegra_emc_load_timings_from_dt(emc, np); 689 of_node_put(np); 690 if (err) 691 return err; 692 693 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 694 emc->regs = devm_ioremap_resource(&pdev->dev, res); 695 if (IS_ERR(emc->regs)) 696 return PTR_ERR(emc->regs); 697 698 err = emc_setup_hw(emc); 699 if (err) 700 return err; 701 702 err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, 703 dev_name(&pdev->dev), emc); 704 if (err) { 705 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); 706 return err; 707 } 708 709 tegra20_clk_set_emc_round_callback(emc_round_rate, emc); 710 711 emc->clk = devm_clk_get(&pdev->dev, "emc"); 712 if (IS_ERR(emc->clk)) { 713 err = PTR_ERR(emc->clk); 714 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); 715 goto unset_cb; 716 } 717 718 err = clk_notifier_register(emc->clk, &emc->clk_nb); 719 if (err) { 720 dev_err(&pdev->dev, "failed to register clk notifier: %d\n", 721 err); 722 goto unset_cb; 723 } 724 725 platform_set_drvdata(pdev, emc); 726 tegra_emc_debugfs_init(emc); 727 728 return 0; 729 730 unset_cb: 731 tegra20_clk_set_emc_round_callback(NULL, NULL); 732 733 return err; 734 } 735 736 static const struct of_device_id tegra_emc_of_match[] = { 737 { .compatible = "nvidia,tegra20-emc", }, 738 {}, 739 }; 740 741 static struct platform_driver tegra_emc_driver = { 742 .probe = tegra_emc_probe, 743 .driver = { 744 .name = "tegra20-emc", 745 .of_match_table = tegra_emc_of_match, 746 .suppress_bind_attrs = true, 747 }, 748 }; 749 750 static int __init tegra_emc_init(void) 751 { 752 return platform_driver_register(&tegra_emc_driver); 753 } 754 subsys_initcall(tegra_emc_init); 755