1 // SPDX-License-Identifier: GPL-2.0-only 2 /* linux/drivers/mfd/sm501.c 3 * 4 * Copyright (C) 2006 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * Vincent Sanders <vince@simtec.co.uk> 7 * 8 * SM501 MFD driver 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/list.h> 16 #include <linux/device.h> 17 #include <linux/platform_device.h> 18 #include <linux/pci.h> 19 #include <linux/platform_data/i2c-gpio.h> 20 #include <linux/gpio/machine.h> 21 #include <linux/slab.h> 22 23 #include <linux/sm501.h> 24 #include <linux/sm501-regs.h> 25 #include <linux/serial_8250.h> 26 27 #include <linux/io.h> 28 29 struct sm501_device { 30 struct list_head list; 31 struct platform_device pdev; 32 }; 33 34 struct sm501_gpio; 35 36 #ifdef CONFIG_MFD_SM501_GPIO 37 #include <linux/gpio.h> 38 39 struct sm501_gpio_chip { 40 struct gpio_chip gpio; 41 struct sm501_gpio *ourgpio; /* to get back to parent. */ 42 void __iomem *regbase; 43 void __iomem *control; /* address of control reg. */ 44 }; 45 46 struct sm501_gpio { 47 struct sm501_gpio_chip low; 48 struct sm501_gpio_chip high; 49 spinlock_t lock; 50 51 unsigned int registered : 1; 52 void __iomem *regs; 53 struct resource *regs_res; 54 }; 55 #else 56 struct sm501_gpio { 57 /* no gpio support, empty definition for sm501_devdata. */ 58 }; 59 #endif 60 61 struct sm501_devdata { 62 spinlock_t reg_lock; 63 struct mutex clock_lock; 64 struct list_head devices; 65 struct sm501_gpio gpio; 66 67 struct device *dev; 68 struct resource *io_res; 69 struct resource *mem_res; 70 struct resource *regs_claim; 71 struct sm501_platdata *platdata; 72 73 74 unsigned int in_suspend; 75 unsigned long pm_misc; 76 77 int unit_power[20]; 78 unsigned int pdev_id; 79 unsigned int irq; 80 void __iomem *regs; 81 unsigned int rev; 82 }; 83 84 85 #define MHZ (1000 * 1000) 86 87 #ifdef DEBUG 88 static const unsigned int div_tab[] = { 89 [0] = 1, 90 [1] = 2, 91 [2] = 4, 92 [3] = 8, 93 [4] = 16, 94 [5] = 32, 95 [6] = 64, 96 [7] = 128, 97 [8] = 3, 98 [9] = 6, 99 [10] = 12, 100 [11] = 24, 101 [12] = 48, 102 [13] = 96, 103 [14] = 192, 104 [15] = 384, 105 [16] = 5, 106 [17] = 10, 107 [18] = 20, 108 [19] = 40, 109 [20] = 80, 110 [21] = 160, 111 [22] = 320, 112 [23] = 604, 113 }; 114 115 static unsigned long decode_div(unsigned long pll2, unsigned long val, 116 unsigned int lshft, unsigned int selbit, 117 unsigned long mask) 118 { 119 if (val & selbit) 120 pll2 = 288 * MHZ; 121 122 return pll2 / div_tab[(val >> lshft) & mask]; 123 } 124 125 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x) 126 127 /* sm501_dump_clk 128 * 129 * Print out the current clock configuration for the device 130 */ 131 132 static void sm501_dump_clk(struct sm501_devdata *sm) 133 { 134 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); 135 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); 136 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); 137 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 138 unsigned long sdclk0, sdclk1; 139 unsigned long pll2 = 0; 140 141 switch (misct & 0x30) { 142 case 0x00: 143 pll2 = 336 * MHZ; 144 break; 145 case 0x10: 146 pll2 = 288 * MHZ; 147 break; 148 case 0x20: 149 pll2 = 240 * MHZ; 150 break; 151 case 0x30: 152 pll2 = 192 * MHZ; 153 break; 154 } 155 156 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; 157 sdclk0 /= div_tab[((misct >> 8) & 0xf)]; 158 159 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; 160 sdclk1 /= div_tab[((misct >> 16) & 0xf)]; 161 162 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", 163 misct, pm0, pm1); 164 165 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", 166 fmt_freq(pll2), sdclk0, sdclk1); 167 168 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); 169 170 dev_dbg(sm->dev, "PM0[%c]: " 171 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 172 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 173 (pmc & 3 ) == 0 ? '*' : '-', 174 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)), 175 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)), 176 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)), 177 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15))); 178 179 dev_dbg(sm->dev, "PM1[%c]: " 180 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 181 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 182 (pmc & 3 ) == 1 ? '*' : '-', 183 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)), 184 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)), 185 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)), 186 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15))); 187 } 188 189 static void sm501_dump_regs(struct sm501_devdata *sm) 190 { 191 void __iomem *regs = sm->regs; 192 193 dev_info(sm->dev, "System Control %08x\n", 194 smc501_readl(regs + SM501_SYSTEM_CONTROL)); 195 dev_info(sm->dev, "Misc Control %08x\n", 196 smc501_readl(regs + SM501_MISC_CONTROL)); 197 dev_info(sm->dev, "GPIO Control Low %08x\n", 198 smc501_readl(regs + SM501_GPIO31_0_CONTROL)); 199 dev_info(sm->dev, "GPIO Control Hi %08x\n", 200 smc501_readl(regs + SM501_GPIO63_32_CONTROL)); 201 dev_info(sm->dev, "DRAM Control %08x\n", 202 smc501_readl(regs + SM501_DRAM_CONTROL)); 203 dev_info(sm->dev, "Arbitration Ctrl %08x\n", 204 smc501_readl(regs + SM501_ARBTRTN_CONTROL)); 205 dev_info(sm->dev, "Misc Timing %08x\n", 206 smc501_readl(regs + SM501_MISC_TIMING)); 207 } 208 209 static void sm501_dump_gate(struct sm501_devdata *sm) 210 { 211 dev_info(sm->dev, "CurrentGate %08x\n", 212 smc501_readl(sm->regs + SM501_CURRENT_GATE)); 213 dev_info(sm->dev, "CurrentClock %08x\n", 214 smc501_readl(sm->regs + SM501_CURRENT_CLOCK)); 215 dev_info(sm->dev, "PowerModeControl %08x\n", 216 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL)); 217 } 218 219 #else 220 static inline void sm501_dump_gate(struct sm501_devdata *sm) { } 221 static inline void sm501_dump_regs(struct sm501_devdata *sm) { } 222 static inline void sm501_dump_clk(struct sm501_devdata *sm) { } 223 #endif 224 225 /* sm501_sync_regs 226 * 227 * ensure the 228 */ 229 230 static void sm501_sync_regs(struct sm501_devdata *sm) 231 { 232 smc501_readl(sm->regs); 233 } 234 235 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) 236 { 237 /* during suspend/resume, we are currently not allowed to sleep, 238 * so change to using mdelay() instead of msleep() if we 239 * are in one of these paths */ 240 241 if (sm->in_suspend) 242 mdelay(delay); 243 else 244 msleep(delay); 245 } 246 247 /* sm501_misc_control 248 * 249 * alters the miscellaneous control parameters 250 */ 251 252 int sm501_misc_control(struct device *dev, 253 unsigned long set, unsigned long clear) 254 { 255 struct sm501_devdata *sm = dev_get_drvdata(dev); 256 unsigned long misc; 257 unsigned long save; 258 unsigned long to; 259 260 spin_lock_irqsave(&sm->reg_lock, save); 261 262 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); 263 to = (misc & ~clear) | set; 264 265 if (to != misc) { 266 smc501_writel(to, sm->regs + SM501_MISC_CONTROL); 267 sm501_sync_regs(sm); 268 269 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); 270 } 271 272 spin_unlock_irqrestore(&sm->reg_lock, save); 273 return to; 274 } 275 276 EXPORT_SYMBOL_GPL(sm501_misc_control); 277 278 /* sm501_modify_reg 279 * 280 * Modify a register in the SM501 which may be shared with other 281 * drivers. 282 */ 283 284 unsigned long sm501_modify_reg(struct device *dev, 285 unsigned long reg, 286 unsigned long set, 287 unsigned long clear) 288 { 289 struct sm501_devdata *sm = dev_get_drvdata(dev); 290 unsigned long data; 291 unsigned long save; 292 293 spin_lock_irqsave(&sm->reg_lock, save); 294 295 data = smc501_readl(sm->regs + reg); 296 data |= set; 297 data &= ~clear; 298 299 smc501_writel(data, sm->regs + reg); 300 sm501_sync_regs(sm); 301 302 spin_unlock_irqrestore(&sm->reg_lock, save); 303 304 return data; 305 } 306 307 EXPORT_SYMBOL_GPL(sm501_modify_reg); 308 309 /* sm501_unit_power 310 * 311 * alters the power active gate to set specific units on or off 312 */ 313 314 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) 315 { 316 struct sm501_devdata *sm = dev_get_drvdata(dev); 317 unsigned long mode; 318 unsigned long gate; 319 unsigned long clock; 320 321 mutex_lock(&sm->clock_lock); 322 323 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 324 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 325 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 326 327 mode &= 3; /* get current power mode */ 328 329 if (unit >= ARRAY_SIZE(sm->unit_power)) { 330 dev_err(dev, "%s: bad unit %d\n", __func__, unit); 331 goto already; 332 } 333 334 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit, 335 sm->unit_power[unit], to); 336 337 if (to == 0 && sm->unit_power[unit] == 0) { 338 dev_err(sm->dev, "unit %d is already shutdown\n", unit); 339 goto already; 340 } 341 342 sm->unit_power[unit] += to ? 1 : -1; 343 to = sm->unit_power[unit] ? 1 : 0; 344 345 if (to) { 346 if (gate & (1 << unit)) 347 goto already; 348 gate |= (1 << unit); 349 } else { 350 if (!(gate & (1 << unit))) 351 goto already; 352 gate &= ~(1 << unit); 353 } 354 355 switch (mode) { 356 case 1: 357 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 358 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 359 mode = 0; 360 break; 361 case 2: 362 case 0: 363 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 364 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 365 mode = 1; 366 break; 367 368 default: 369 gate = -1; 370 goto already; 371 } 372 373 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 374 sm501_sync_regs(sm); 375 376 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 377 gate, clock, mode); 378 379 sm501_mdelay(sm, 16); 380 381 already: 382 mutex_unlock(&sm->clock_lock); 383 return gate; 384 } 385 386 EXPORT_SYMBOL_GPL(sm501_unit_power); 387 388 /* clock value structure. */ 389 struct sm501_clock { 390 unsigned long mclk; 391 int divider; 392 int shift; 393 unsigned int m, n, k; 394 }; 395 396 /* sm501_calc_clock 397 * 398 * Calculates the nearest discrete clock frequency that 399 * can be achieved with the specified input clock. 400 * the maximum divisor is 3 or 5 401 */ 402 403 static int sm501_calc_clock(unsigned long freq, 404 struct sm501_clock *clock, 405 int max_div, 406 unsigned long mclk, 407 long *best_diff) 408 { 409 int ret = 0; 410 int divider; 411 int shift; 412 long diff; 413 414 /* try dividers 1 and 3 for CRT and for panel, 415 try divider 5 for panel only.*/ 416 417 for (divider = 1; divider <= max_div; divider += 2) { 418 /* try all 8 shift values.*/ 419 for (shift = 0; shift < 8; shift++) { 420 /* Calculate difference to requested clock */ 421 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq; 422 if (diff < 0) 423 diff = -diff; 424 425 /* If it is less than the current, use it */ 426 if (diff < *best_diff) { 427 *best_diff = diff; 428 429 clock->mclk = mclk; 430 clock->divider = divider; 431 clock->shift = shift; 432 ret = 1; 433 } 434 } 435 } 436 437 return ret; 438 } 439 440 /* sm501_calc_pll 441 * 442 * Calculates the nearest discrete clock frequency that can be 443 * achieved using the programmable PLL. 444 * the maximum divisor is 3 or 5 445 */ 446 447 static unsigned long sm501_calc_pll(unsigned long freq, 448 struct sm501_clock *clock, 449 int max_div) 450 { 451 unsigned long mclk; 452 unsigned int m, n, k; 453 long best_diff = 999999999; 454 455 /* 456 * The SM502 datasheet doesn't specify the min/max values for M and N. 457 * N = 1 at least doesn't work in practice. 458 */ 459 for (m = 2; m <= 255; m++) { 460 for (n = 2; n <= 127; n++) { 461 for (k = 0; k <= 1; k++) { 462 mclk = (24000000UL * m / n) >> k; 463 464 if (sm501_calc_clock(freq, clock, max_div, 465 mclk, &best_diff)) { 466 clock->m = m; 467 clock->n = n; 468 clock->k = k; 469 } 470 } 471 } 472 } 473 474 /* Return best clock. */ 475 return clock->mclk / (clock->divider << clock->shift); 476 } 477 478 /* sm501_select_clock 479 * 480 * Calculates the nearest discrete clock frequency that can be 481 * achieved using the 288MHz and 336MHz PLLs. 482 * the maximum divisor is 3 or 5 483 */ 484 485 static unsigned long sm501_select_clock(unsigned long freq, 486 struct sm501_clock *clock, 487 int max_div) 488 { 489 unsigned long mclk; 490 long best_diff = 999999999; 491 492 /* Try 288MHz and 336MHz clocks. */ 493 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { 494 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff); 495 } 496 497 /* Return best clock. */ 498 return clock->mclk / (clock->divider << clock->shift); 499 } 500 501 /* sm501_set_clock 502 * 503 * set one of the four clock sources to the closest available frequency to 504 * the one specified 505 */ 506 507 unsigned long sm501_set_clock(struct device *dev, 508 int clksrc, 509 unsigned long req_freq) 510 { 511 struct sm501_devdata *sm = dev_get_drvdata(dev); 512 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 513 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 514 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 515 unsigned int pll_reg = 0; 516 unsigned long sm501_freq; /* the actual frequency achieved */ 517 u64 reg; 518 519 struct sm501_clock to; 520 521 /* find achivable discrete frequency and setup register value 522 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK 523 * has an extra bit for the divider */ 524 525 switch (clksrc) { 526 case SM501_CLOCK_P2XCLK: 527 /* This clock is divided in half so to achieve the 528 * requested frequency the value must be multiplied by 529 * 2. This clock also has an additional pre divisor */ 530 531 if (sm->rev >= 0xC0) { 532 /* SM502 -> use the programmable PLL */ 533 sm501_freq = (sm501_calc_pll(2 * req_freq, 534 &to, 5) / 2); 535 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 536 if (to.divider == 3) 537 reg |= 0x08; /* /3 divider required */ 538 else if (to.divider == 5) 539 reg |= 0x10; /* /5 divider required */ 540 reg |= 0x40; /* select the programmable PLL */ 541 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m; 542 } else { 543 sm501_freq = (sm501_select_clock(2 * req_freq, 544 &to, 5) / 2); 545 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 546 if (to.divider == 3) 547 reg |= 0x08; /* /3 divider required */ 548 else if (to.divider == 5) 549 reg |= 0x10; /* /5 divider required */ 550 if (to.mclk != 288000000) 551 reg |= 0x20; /* which mclk pll is source */ 552 } 553 break; 554 555 case SM501_CLOCK_V2XCLK: 556 /* This clock is divided in half so to achieve the 557 * requested frequency the value must be multiplied by 2. */ 558 559 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 560 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 561 if (to.divider == 3) 562 reg |= 0x08; /* /3 divider required */ 563 if (to.mclk != 288000000) 564 reg |= 0x10; /* which mclk pll is source */ 565 break; 566 567 case SM501_CLOCK_MCLK: 568 case SM501_CLOCK_M1XCLK: 569 /* These clocks are the same and not further divided */ 570 571 sm501_freq = sm501_select_clock( req_freq, &to, 3); 572 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 573 if (to.divider == 3) 574 reg |= 0x08; /* /3 divider required */ 575 if (to.mclk != 288000000) 576 reg |= 0x10; /* which mclk pll is source */ 577 break; 578 579 default: 580 return 0; /* this is bad */ 581 } 582 583 mutex_lock(&sm->clock_lock); 584 585 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 586 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 587 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 588 589 clock = clock & ~(0xFF << clksrc); 590 clock |= reg<<clksrc; 591 592 mode &= 3; /* find current mode */ 593 594 switch (mode) { 595 case 1: 596 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 597 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 598 mode = 0; 599 break; 600 case 2: 601 case 0: 602 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 603 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 604 mode = 1; 605 break; 606 607 default: 608 mutex_unlock(&sm->clock_lock); 609 return -1; 610 } 611 612 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 613 614 if (pll_reg) 615 smc501_writel(pll_reg, 616 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); 617 618 sm501_sync_regs(sm); 619 620 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 621 gate, clock, mode); 622 623 sm501_mdelay(sm, 16); 624 mutex_unlock(&sm->clock_lock); 625 626 sm501_dump_clk(sm); 627 628 return sm501_freq; 629 } 630 631 EXPORT_SYMBOL_GPL(sm501_set_clock); 632 633 /* sm501_find_clock 634 * 635 * finds the closest available frequency for a given clock 636 */ 637 638 unsigned long sm501_find_clock(struct device *dev, 639 int clksrc, 640 unsigned long req_freq) 641 { 642 struct sm501_devdata *sm = dev_get_drvdata(dev); 643 unsigned long sm501_freq; /* the frequency achieveable by the 501 */ 644 struct sm501_clock to; 645 646 switch (clksrc) { 647 case SM501_CLOCK_P2XCLK: 648 if (sm->rev >= 0xC0) { 649 /* SM502 -> use the programmable PLL */ 650 sm501_freq = (sm501_calc_pll(2 * req_freq, 651 &to, 5) / 2); 652 } else { 653 sm501_freq = (sm501_select_clock(2 * req_freq, 654 &to, 5) / 2); 655 } 656 break; 657 658 case SM501_CLOCK_V2XCLK: 659 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 660 break; 661 662 case SM501_CLOCK_MCLK: 663 case SM501_CLOCK_M1XCLK: 664 sm501_freq = sm501_select_clock(req_freq, &to, 3); 665 break; 666 667 default: 668 sm501_freq = 0; /* error */ 669 } 670 671 return sm501_freq; 672 } 673 674 EXPORT_SYMBOL_GPL(sm501_find_clock); 675 676 static struct sm501_device *to_sm_device(struct platform_device *pdev) 677 { 678 return container_of(pdev, struct sm501_device, pdev); 679 } 680 681 /* sm501_device_release 682 * 683 * A release function for the platform devices we create to allow us to 684 * free any items we allocated 685 */ 686 687 static void sm501_device_release(struct device *dev) 688 { 689 kfree(to_sm_device(to_platform_device(dev))); 690 } 691 692 /* sm501_create_subdev 693 * 694 * Create a skeleton platform device with resources for passing to a 695 * sub-driver 696 */ 697 698 static struct platform_device * 699 sm501_create_subdev(struct sm501_devdata *sm, char *name, 700 unsigned int res_count, unsigned int platform_data_size) 701 { 702 struct sm501_device *smdev; 703 704 smdev = kzalloc(sizeof(struct sm501_device) + 705 (sizeof(struct resource) * res_count) + 706 platform_data_size, GFP_KERNEL); 707 if (!smdev) 708 return NULL; 709 710 smdev->pdev.dev.release = sm501_device_release; 711 712 smdev->pdev.name = name; 713 smdev->pdev.id = sm->pdev_id; 714 smdev->pdev.dev.parent = sm->dev; 715 smdev->pdev.dev.coherent_dma_mask = 0xffffffff; 716 717 if (res_count) { 718 smdev->pdev.resource = (struct resource *)(smdev+1); 719 smdev->pdev.num_resources = res_count; 720 } 721 if (platform_data_size) 722 smdev->pdev.dev.platform_data = (void *)(smdev+1); 723 724 return &smdev->pdev; 725 } 726 727 /* sm501_register_device 728 * 729 * Register a platform device created with sm501_create_subdev() 730 */ 731 732 static int sm501_register_device(struct sm501_devdata *sm, 733 struct platform_device *pdev) 734 { 735 struct sm501_device *smdev = to_sm_device(pdev); 736 int ptr; 737 int ret; 738 739 for (ptr = 0; ptr < pdev->num_resources; ptr++) { 740 printk(KERN_DEBUG "%s[%d] %pR\n", 741 pdev->name, ptr, &pdev->resource[ptr]); 742 } 743 744 ret = platform_device_register(pdev); 745 746 if (ret >= 0) { 747 dev_dbg(sm->dev, "registered %s\n", pdev->name); 748 list_add_tail(&smdev->list, &sm->devices); 749 } else 750 dev_err(sm->dev, "error registering %s (%d)\n", 751 pdev->name, ret); 752 753 return ret; 754 } 755 756 /* sm501_create_subio 757 * 758 * Fill in an IO resource for a sub device 759 */ 760 761 static void sm501_create_subio(struct sm501_devdata *sm, 762 struct resource *res, 763 resource_size_t offs, 764 resource_size_t size) 765 { 766 res->flags = IORESOURCE_MEM; 767 res->parent = sm->io_res; 768 res->start = sm->io_res->start + offs; 769 res->end = res->start + size - 1; 770 } 771 772 /* sm501_create_mem 773 * 774 * Fill in an MEM resource for a sub device 775 */ 776 777 static void sm501_create_mem(struct sm501_devdata *sm, 778 struct resource *res, 779 resource_size_t *offs, 780 resource_size_t size) 781 { 782 *offs -= size; /* adjust memory size */ 783 784 res->flags = IORESOURCE_MEM; 785 res->parent = sm->mem_res; 786 res->start = sm->mem_res->start + *offs; 787 res->end = res->start + size - 1; 788 } 789 790 /* sm501_create_irq 791 * 792 * Fill in an IRQ resource for a sub device 793 */ 794 795 static void sm501_create_irq(struct sm501_devdata *sm, 796 struct resource *res) 797 { 798 res->flags = IORESOURCE_IRQ; 799 res->parent = NULL; 800 res->start = res->end = sm->irq; 801 } 802 803 static int sm501_register_usbhost(struct sm501_devdata *sm, 804 resource_size_t *mem_avail) 805 { 806 struct platform_device *pdev; 807 808 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0); 809 if (!pdev) 810 return -ENOMEM; 811 812 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000); 813 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024); 814 sm501_create_irq(sm, &pdev->resource[2]); 815 816 return sm501_register_device(sm, pdev); 817 } 818 819 static void sm501_setup_uart_data(struct sm501_devdata *sm, 820 struct plat_serial8250_port *uart_data, 821 unsigned int offset) 822 { 823 uart_data->membase = sm->regs + offset; 824 uart_data->mapbase = sm->io_res->start + offset; 825 uart_data->iotype = UPIO_MEM; 826 uart_data->irq = sm->irq; 827 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 828 uart_data->regshift = 2; 829 uart_data->uartclk = (9600 * 16); 830 } 831 832 static int sm501_register_uart(struct sm501_devdata *sm, int devices) 833 { 834 struct platform_device *pdev; 835 struct plat_serial8250_port *uart_data; 836 837 pdev = sm501_create_subdev(sm, "serial8250", 0, 838 sizeof(struct plat_serial8250_port) * 3); 839 if (!pdev) 840 return -ENOMEM; 841 842 uart_data = dev_get_platdata(&pdev->dev); 843 844 if (devices & SM501_USE_UART0) { 845 sm501_setup_uart_data(sm, uart_data++, 0x30000); 846 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1); 847 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0); 848 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0); 849 } 850 if (devices & SM501_USE_UART1) { 851 sm501_setup_uart_data(sm, uart_data++, 0x30020); 852 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1); 853 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0); 854 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0); 855 } 856 857 pdev->id = PLAT8250_DEV_SM501; 858 859 return sm501_register_device(sm, pdev); 860 } 861 862 static int sm501_register_display(struct sm501_devdata *sm, 863 resource_size_t *mem_avail) 864 { 865 struct platform_device *pdev; 866 867 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0); 868 if (!pdev) 869 return -ENOMEM; 870 871 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000); 872 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000); 873 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail); 874 sm501_create_irq(sm, &pdev->resource[3]); 875 876 return sm501_register_device(sm, pdev); 877 } 878 879 #ifdef CONFIG_MFD_SM501_GPIO 880 881 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio) 882 { 883 return container_of(gpio, struct sm501_devdata, gpio); 884 } 885 886 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) 887 888 { 889 struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip); 890 unsigned long result; 891 892 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW); 893 result >>= offset; 894 895 return result & 1UL; 896 } 897 898 static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip, 899 unsigned long bit) 900 { 901 unsigned long ctrl; 902 903 /* check and modify if this pin is not set as gpio. */ 904 905 if (smc501_readl(smchip->control) & bit) { 906 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, 907 "changing mode of gpio, bit %08lx\n", bit); 908 909 ctrl = smc501_readl(smchip->control); 910 ctrl &= ~bit; 911 smc501_writel(ctrl, smchip->control); 912 913 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); 914 } 915 } 916 917 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 918 919 { 920 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 921 struct sm501_gpio *smgpio = smchip->ourgpio; 922 unsigned long bit = 1 << offset; 923 void __iomem *regs = smchip->regbase; 924 unsigned long save; 925 unsigned long val; 926 927 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 928 __func__, chip, offset); 929 930 spin_lock_irqsave(&smgpio->lock, save); 931 932 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit; 933 if (value) 934 val |= bit; 935 smc501_writel(val, regs); 936 937 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 938 sm501_gpio_ensure_gpio(smchip, bit); 939 940 spin_unlock_irqrestore(&smgpio->lock, save); 941 } 942 943 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) 944 { 945 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 946 struct sm501_gpio *smgpio = smchip->ourgpio; 947 void __iomem *regs = smchip->regbase; 948 unsigned long bit = 1 << offset; 949 unsigned long save; 950 unsigned long ddr; 951 952 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 953 __func__, chip, offset); 954 955 spin_lock_irqsave(&smgpio->lock, save); 956 957 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); 958 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); 959 960 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 961 sm501_gpio_ensure_gpio(smchip, bit); 962 963 spin_unlock_irqrestore(&smgpio->lock, save); 964 965 return 0; 966 } 967 968 static int sm501_gpio_output(struct gpio_chip *chip, 969 unsigned offset, int value) 970 { 971 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 972 struct sm501_gpio *smgpio = smchip->ourgpio; 973 unsigned long bit = 1 << offset; 974 void __iomem *regs = smchip->regbase; 975 unsigned long save; 976 unsigned long val; 977 unsigned long ddr; 978 979 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n", 980 __func__, chip, offset, value); 981 982 spin_lock_irqsave(&smgpio->lock, save); 983 984 val = smc501_readl(regs + SM501_GPIO_DATA_LOW); 985 if (value) 986 val |= bit; 987 else 988 val &= ~bit; 989 smc501_writel(val, regs); 990 991 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); 992 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); 993 994 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 995 smc501_writel(val, regs + SM501_GPIO_DATA_LOW); 996 997 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 998 spin_unlock_irqrestore(&smgpio->lock, save); 999 1000 return 0; 1001 } 1002 1003 static const struct gpio_chip gpio_chip_template = { 1004 .ngpio = 32, 1005 .direction_input = sm501_gpio_input, 1006 .direction_output = sm501_gpio_output, 1007 .set = sm501_gpio_set, 1008 .get = sm501_gpio_get, 1009 }; 1010 1011 static int sm501_gpio_register_chip(struct sm501_devdata *sm, 1012 struct sm501_gpio *gpio, 1013 struct sm501_gpio_chip *chip) 1014 { 1015 struct sm501_platdata *pdata = sm->platdata; 1016 struct gpio_chip *gchip = &chip->gpio; 1017 int base = pdata->gpio_base; 1018 1019 chip->gpio = gpio_chip_template; 1020 1021 if (chip == &gpio->high) { 1022 if (base > 0) 1023 base += 32; 1024 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH; 1025 chip->control = sm->regs + SM501_GPIO63_32_CONTROL; 1026 gchip->label = "SM501-HIGH"; 1027 } else { 1028 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW; 1029 chip->control = sm->regs + SM501_GPIO31_0_CONTROL; 1030 gchip->label = "SM501-LOW"; 1031 } 1032 1033 gchip->base = base; 1034 chip->ourgpio = gpio; 1035 1036 return gpiochip_add_data(gchip, chip); 1037 } 1038 1039 static int sm501_register_gpio(struct sm501_devdata *sm) 1040 { 1041 struct sm501_gpio *gpio = &sm->gpio; 1042 resource_size_t iobase = sm->io_res->start + SM501_GPIO; 1043 int ret; 1044 1045 dev_dbg(sm->dev, "registering gpio block %08llx\n", 1046 (unsigned long long)iobase); 1047 1048 spin_lock_init(&gpio->lock); 1049 1050 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio"); 1051 if (!gpio->regs_res) { 1052 dev_err(sm->dev, "gpio: failed to request region\n"); 1053 return -ENXIO; 1054 } 1055 1056 gpio->regs = ioremap(iobase, 0x20); 1057 if (!gpio->regs) { 1058 dev_err(sm->dev, "gpio: failed to remap registers\n"); 1059 ret = -ENXIO; 1060 goto err_claimed; 1061 } 1062 1063 /* Register both our chips. */ 1064 1065 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low); 1066 if (ret) { 1067 dev_err(sm->dev, "failed to add low chip\n"); 1068 goto err_mapped; 1069 } 1070 1071 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high); 1072 if (ret) { 1073 dev_err(sm->dev, "failed to add high chip\n"); 1074 goto err_low_chip; 1075 } 1076 1077 gpio->registered = 1; 1078 1079 return 0; 1080 1081 err_low_chip: 1082 gpiochip_remove(&gpio->low.gpio); 1083 1084 err_mapped: 1085 iounmap(gpio->regs); 1086 1087 err_claimed: 1088 release_resource(gpio->regs_res); 1089 kfree(gpio->regs_res); 1090 1091 return ret; 1092 } 1093 1094 static void sm501_gpio_remove(struct sm501_devdata *sm) 1095 { 1096 struct sm501_gpio *gpio = &sm->gpio; 1097 1098 if (!sm->gpio.registered) 1099 return; 1100 1101 gpiochip_remove(&gpio->low.gpio); 1102 gpiochip_remove(&gpio->high.gpio); 1103 1104 iounmap(gpio->regs); 1105 release_resource(gpio->regs_res); 1106 kfree(gpio->regs_res); 1107 } 1108 1109 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1110 { 1111 return sm->gpio.registered; 1112 } 1113 #else 1114 static inline int sm501_register_gpio(struct sm501_devdata *sm) 1115 { 1116 return 0; 1117 } 1118 1119 static inline void sm501_gpio_remove(struct sm501_devdata *sm) 1120 { 1121 } 1122 1123 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1124 { 1125 return 0; 1126 } 1127 #endif 1128 1129 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm, 1130 struct sm501_platdata_gpio_i2c *iic) 1131 { 1132 struct i2c_gpio_platform_data *icd; 1133 struct platform_device *pdev; 1134 struct gpiod_lookup_table *lookup; 1135 1136 pdev = sm501_create_subdev(sm, "i2c-gpio", 0, 1137 sizeof(struct i2c_gpio_platform_data)); 1138 if (!pdev) 1139 return -ENOMEM; 1140 1141 /* Create a gpiod lookup using gpiochip-local offsets */ 1142 lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3), 1143 GFP_KERNEL); 1144 if (!lookup) 1145 return -ENOMEM; 1146 1147 lookup->dev_id = "i2c-gpio"; 1148 if (iic->pin_sda < 32) 1149 lookup->table[0].chip_label = "SM501-LOW"; 1150 else 1151 lookup->table[0].chip_label = "SM501-HIGH"; 1152 lookup->table[0].chip_hwnum = iic->pin_sda % 32; 1153 lookup->table[0].con_id = NULL; 1154 lookup->table[0].idx = 0; 1155 lookup->table[0].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN; 1156 if (iic->pin_scl < 32) 1157 lookup->table[1].chip_label = "SM501-LOW"; 1158 else 1159 lookup->table[1].chip_label = "SM501-HIGH"; 1160 lookup->table[1].chip_hwnum = iic->pin_scl % 32; 1161 lookup->table[1].con_id = NULL; 1162 lookup->table[1].idx = 1; 1163 lookup->table[1].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN; 1164 gpiod_add_lookup_table(lookup); 1165 1166 icd = dev_get_platdata(&pdev->dev); 1167 icd->timeout = iic->timeout; 1168 icd->udelay = iic->udelay; 1169 1170 /* note, we can't use either of the pin numbers, as the i2c-gpio 1171 * driver uses the platform.id field to generate the bus number 1172 * to register with the i2c core; The i2c core doesn't have enough 1173 * entries to deal with anything we currently use. 1174 */ 1175 1176 pdev->id = iic->bus_num; 1177 1178 dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n", 1179 iic->bus_num, 1180 iic->pin_sda, iic->pin_scl); 1181 1182 return sm501_register_device(sm, pdev); 1183 } 1184 1185 static int sm501_register_gpio_i2c(struct sm501_devdata *sm, 1186 struct sm501_platdata *pdata) 1187 { 1188 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c; 1189 int index; 1190 int ret; 1191 1192 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) { 1193 ret = sm501_register_gpio_i2c_instance(sm, iic); 1194 if (ret < 0) 1195 return ret; 1196 } 1197 1198 return 0; 1199 } 1200 1201 /* sm501_dbg_regs 1202 * 1203 * Debug attribute to attach to parent device to show core registers 1204 */ 1205 1206 static ssize_t sm501_dbg_regs(struct device *dev, 1207 struct device_attribute *attr, char *buff) 1208 { 1209 struct sm501_devdata *sm = dev_get_drvdata(dev) ; 1210 unsigned int reg; 1211 char *ptr = buff; 1212 int ret; 1213 1214 for (reg = 0x00; reg < 0x70; reg += 4) { 1215 ret = sprintf(ptr, "%08x = %08x\n", 1216 reg, smc501_readl(sm->regs + reg)); 1217 ptr += ret; 1218 } 1219 1220 return ptr - buff; 1221 } 1222 1223 1224 static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL); 1225 1226 /* sm501_init_reg 1227 * 1228 * Helper function for the init code to setup a register 1229 * 1230 * clear the bits which are set in r->mask, and then set 1231 * the bits set in r->set. 1232 */ 1233 1234 static inline void sm501_init_reg(struct sm501_devdata *sm, 1235 unsigned long reg, 1236 struct sm501_reg_init *r) 1237 { 1238 unsigned long tmp; 1239 1240 tmp = smc501_readl(sm->regs + reg); 1241 tmp &= ~r->mask; 1242 tmp |= r->set; 1243 smc501_writel(tmp, sm->regs + reg); 1244 } 1245 1246 /* sm501_init_regs 1247 * 1248 * Setup core register values 1249 */ 1250 1251 static void sm501_init_regs(struct sm501_devdata *sm, 1252 struct sm501_initdata *init) 1253 { 1254 sm501_misc_control(sm->dev, 1255 init->misc_control.set, 1256 init->misc_control.mask); 1257 1258 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing); 1259 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low); 1260 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high); 1261 1262 if (init->m1xclk) { 1263 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk); 1264 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk); 1265 } 1266 1267 if (init->mclk) { 1268 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); 1269 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk); 1270 } 1271 1272 } 1273 1274 /* Check the PLL sources for the M1CLK and M1XCLK 1275 * 1276 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then 1277 * there is a risk (see errata AB-5) that the SM501 will cease proper 1278 * function. If this happens, then it is likely the SM501 will 1279 * hang the system. 1280 */ 1281 1282 static int sm501_check_clocks(struct sm501_devdata *sm) 1283 { 1284 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 1285 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); 1286 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); 1287 1288 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0)); 1289 } 1290 1291 static unsigned int sm501_mem_local[] = { 1292 [0] = 4*1024*1024, 1293 [1] = 8*1024*1024, 1294 [2] = 16*1024*1024, 1295 [3] = 32*1024*1024, 1296 [4] = 64*1024*1024, 1297 [5] = 2*1024*1024, 1298 }; 1299 1300 /* sm501_init_dev 1301 * 1302 * Common init code for an SM501 1303 */ 1304 1305 static int sm501_init_dev(struct sm501_devdata *sm) 1306 { 1307 struct sm501_initdata *idata; 1308 struct sm501_platdata *pdata; 1309 resource_size_t mem_avail; 1310 unsigned long dramctrl; 1311 unsigned long devid; 1312 int ret; 1313 1314 mutex_init(&sm->clock_lock); 1315 spin_lock_init(&sm->reg_lock); 1316 1317 INIT_LIST_HEAD(&sm->devices); 1318 1319 devid = smc501_readl(sm->regs + SM501_DEVICEID); 1320 1321 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { 1322 dev_err(sm->dev, "incorrect device id %08lx\n", devid); 1323 return -EINVAL; 1324 } 1325 1326 /* disable irqs */ 1327 smc501_writel(0, sm->regs + SM501_IRQ_MASK); 1328 1329 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL); 1330 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; 1331 1332 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", 1333 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq); 1334 1335 sm->rev = devid & SM501_DEVICEID_REVMASK; 1336 1337 sm501_dump_gate(sm); 1338 1339 ret = device_create_file(sm->dev, &dev_attr_dbg_regs); 1340 if (ret) 1341 dev_err(sm->dev, "failed to create debug regs file\n"); 1342 1343 sm501_dump_clk(sm); 1344 1345 /* check to see if we have some device initialisation */ 1346 1347 pdata = sm->platdata; 1348 idata = pdata ? pdata->init : NULL; 1349 1350 if (idata) { 1351 sm501_init_regs(sm, idata); 1352 1353 if (idata->devices & SM501_USE_USB_HOST) 1354 sm501_register_usbhost(sm, &mem_avail); 1355 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1)) 1356 sm501_register_uart(sm, idata->devices); 1357 if (idata->devices & SM501_USE_GPIO) 1358 sm501_register_gpio(sm); 1359 } 1360 1361 if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) { 1362 if (!sm501_gpio_isregistered(sm)) 1363 dev_err(sm->dev, "no gpio available for i2c gpio.\n"); 1364 else 1365 sm501_register_gpio_i2c(sm, pdata); 1366 } 1367 1368 ret = sm501_check_clocks(sm); 1369 if (ret) { 1370 dev_err(sm->dev, "M1X and M clocks sourced from different " 1371 "PLLs\n"); 1372 return -EINVAL; 1373 } 1374 1375 /* always create a framebuffer */ 1376 sm501_register_display(sm, &mem_avail); 1377 1378 return 0; 1379 } 1380 1381 static int sm501_plat_probe(struct platform_device *dev) 1382 { 1383 struct sm501_devdata *sm; 1384 int ret; 1385 1386 sm = kzalloc(sizeof(*sm), GFP_KERNEL); 1387 if (!sm) { 1388 ret = -ENOMEM; 1389 goto err1; 1390 } 1391 1392 sm->dev = &dev->dev; 1393 sm->pdev_id = dev->id; 1394 sm->platdata = dev_get_platdata(&dev->dev); 1395 1396 ret = platform_get_irq(dev, 0); 1397 if (ret < 0) { 1398 dev_err(&dev->dev, "failed to get irq resource\n"); 1399 goto err_res; 1400 } 1401 sm->irq = ret; 1402 1403 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 1404 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1405 if (!sm->io_res || !sm->mem_res) { 1406 dev_err(&dev->dev, "failed to get IO resource\n"); 1407 ret = -ENOENT; 1408 goto err_res; 1409 } 1410 1411 sm->regs_claim = request_mem_region(sm->io_res->start, 1412 0x100, "sm501"); 1413 if (!sm->regs_claim) { 1414 dev_err(&dev->dev, "cannot claim registers\n"); 1415 ret = -EBUSY; 1416 goto err_res; 1417 } 1418 1419 platform_set_drvdata(dev, sm); 1420 1421 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res)); 1422 if (!sm->regs) { 1423 dev_err(&dev->dev, "cannot remap registers\n"); 1424 ret = -EIO; 1425 goto err_claim; 1426 } 1427 1428 return sm501_init_dev(sm); 1429 1430 err_claim: 1431 release_resource(sm->regs_claim); 1432 kfree(sm->regs_claim); 1433 err_res: 1434 kfree(sm); 1435 err1: 1436 return ret; 1437 1438 } 1439 1440 #ifdef CONFIG_PM 1441 1442 /* power management support */ 1443 1444 static void sm501_set_power(struct sm501_devdata *sm, int on) 1445 { 1446 struct sm501_platdata *pd = sm->platdata; 1447 1448 if (!pd) 1449 return; 1450 1451 if (pd->get_power) { 1452 if (pd->get_power(sm->dev) == on) { 1453 dev_dbg(sm->dev, "is already %d\n", on); 1454 return; 1455 } 1456 } 1457 1458 if (pd->set_power) { 1459 dev_dbg(sm->dev, "setting power to %d\n", on); 1460 1461 pd->set_power(sm->dev, on); 1462 sm501_mdelay(sm, 10); 1463 } 1464 } 1465 1466 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state) 1467 { 1468 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1469 1470 sm->in_suspend = 1; 1471 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); 1472 1473 sm501_dump_regs(sm); 1474 1475 if (sm->platdata) { 1476 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF) 1477 sm501_set_power(sm, 0); 1478 } 1479 1480 return 0; 1481 } 1482 1483 static int sm501_plat_resume(struct platform_device *pdev) 1484 { 1485 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1486 1487 sm501_set_power(sm, 1); 1488 1489 sm501_dump_regs(sm); 1490 sm501_dump_gate(sm); 1491 sm501_dump_clk(sm); 1492 1493 /* check to see if we are in the same state as when suspended */ 1494 1495 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { 1496 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); 1497 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); 1498 1499 /* our suspend causes the controller state to change, 1500 * either by something attempting setup, power loss, 1501 * or an external reset event on power change */ 1502 1503 if (sm->platdata && sm->platdata->init) { 1504 sm501_init_regs(sm, sm->platdata->init); 1505 } 1506 } 1507 1508 /* dump our state from resume */ 1509 1510 sm501_dump_regs(sm); 1511 sm501_dump_clk(sm); 1512 1513 sm->in_suspend = 0; 1514 1515 return 0; 1516 } 1517 #else 1518 #define sm501_plat_suspend NULL 1519 #define sm501_plat_resume NULL 1520 #endif 1521 1522 /* Initialisation data for PCI devices */ 1523 1524 static struct sm501_initdata sm501_pci_initdata = { 1525 .gpio_high = { 1526 .set = 0x3F000000, /* 24bit panel */ 1527 .mask = 0x0, 1528 }, 1529 .misc_timing = { 1530 .set = 0x010100, /* SDRAM timing */ 1531 .mask = 0x1F1F00, 1532 }, 1533 .misc_control = { 1534 .set = SM501_MISC_PNL_24BIT, 1535 .mask = 0, 1536 }, 1537 1538 .devices = SM501_USE_ALL, 1539 1540 /* Errata AB-3 says that 72MHz is the fastest available 1541 * for 33MHZ PCI with proper bus-mastering operation */ 1542 1543 .mclk = 72 * MHZ, 1544 .m1xclk = 144 * MHZ, 1545 }; 1546 1547 static struct sm501_platdata_fbsub sm501_pdata_fbsub = { 1548 .flags = (SM501FB_FLAG_USE_INIT_MODE | 1549 SM501FB_FLAG_USE_HWCURSOR | 1550 SM501FB_FLAG_USE_HWACCEL | 1551 SM501FB_FLAG_DISABLE_AT_EXIT), 1552 }; 1553 1554 static struct sm501_platdata_fb sm501_fb_pdata = { 1555 .fb_route = SM501_FB_OWN, 1556 .fb_crt = &sm501_pdata_fbsub, 1557 .fb_pnl = &sm501_pdata_fbsub, 1558 }; 1559 1560 static struct sm501_platdata sm501_pci_platdata = { 1561 .init = &sm501_pci_initdata, 1562 .fb = &sm501_fb_pdata, 1563 .gpio_base = -1, 1564 }; 1565 1566 static int sm501_pci_probe(struct pci_dev *dev, 1567 const struct pci_device_id *id) 1568 { 1569 struct sm501_devdata *sm; 1570 int err; 1571 1572 sm = kzalloc(sizeof(*sm), GFP_KERNEL); 1573 if (!sm) { 1574 err = -ENOMEM; 1575 goto err1; 1576 } 1577 1578 /* set a default set of platform data */ 1579 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata; 1580 1581 /* set a hopefully unique id for our child platform devices */ 1582 sm->pdev_id = 32 + dev->devfn; 1583 1584 pci_set_drvdata(dev, sm); 1585 1586 err = pci_enable_device(dev); 1587 if (err) { 1588 dev_err(&dev->dev, "cannot enable device\n"); 1589 goto err2; 1590 } 1591 1592 sm->dev = &dev->dev; 1593 sm->irq = dev->irq; 1594 1595 #ifdef __BIG_ENDIAN 1596 /* if the system is big-endian, we most probably have a 1597 * translation in the IO layer making the PCI bus little endian 1598 * so make the framebuffer swapped pixels */ 1599 1600 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN; 1601 #endif 1602 1603 /* check our resources */ 1604 1605 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) { 1606 dev_err(&dev->dev, "region #0 is not memory?\n"); 1607 err = -EINVAL; 1608 goto err3; 1609 } 1610 1611 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) { 1612 dev_err(&dev->dev, "region #1 is not memory?\n"); 1613 err = -EINVAL; 1614 goto err3; 1615 } 1616 1617 /* make our resources ready for sharing */ 1618 1619 sm->io_res = &dev->resource[1]; 1620 sm->mem_res = &dev->resource[0]; 1621 1622 sm->regs_claim = request_mem_region(sm->io_res->start, 1623 0x100, "sm501"); 1624 if (!sm->regs_claim) { 1625 dev_err(&dev->dev, "cannot claim registers\n"); 1626 err= -EBUSY; 1627 goto err3; 1628 } 1629 1630 sm->regs = pci_ioremap_bar(dev, 1); 1631 if (!sm->regs) { 1632 dev_err(&dev->dev, "cannot remap registers\n"); 1633 err = -EIO; 1634 goto err4; 1635 } 1636 1637 sm501_init_dev(sm); 1638 return 0; 1639 1640 err4: 1641 release_resource(sm->regs_claim); 1642 kfree(sm->regs_claim); 1643 err3: 1644 pci_disable_device(dev); 1645 err2: 1646 kfree(sm); 1647 err1: 1648 return err; 1649 } 1650 1651 static void sm501_remove_sub(struct sm501_devdata *sm, 1652 struct sm501_device *smdev) 1653 { 1654 list_del(&smdev->list); 1655 platform_device_unregister(&smdev->pdev); 1656 } 1657 1658 static void sm501_dev_remove(struct sm501_devdata *sm) 1659 { 1660 struct sm501_device *smdev, *tmp; 1661 1662 list_for_each_entry_safe(smdev, tmp, &sm->devices, list) 1663 sm501_remove_sub(sm, smdev); 1664 1665 device_remove_file(sm->dev, &dev_attr_dbg_regs); 1666 1667 sm501_gpio_remove(sm); 1668 } 1669 1670 static void sm501_pci_remove(struct pci_dev *dev) 1671 { 1672 struct sm501_devdata *sm = pci_get_drvdata(dev); 1673 1674 sm501_dev_remove(sm); 1675 iounmap(sm->regs); 1676 1677 release_resource(sm->regs_claim); 1678 kfree(sm->regs_claim); 1679 1680 pci_disable_device(dev); 1681 } 1682 1683 static int sm501_plat_remove(struct platform_device *dev) 1684 { 1685 struct sm501_devdata *sm = platform_get_drvdata(dev); 1686 1687 sm501_dev_remove(sm); 1688 iounmap(sm->regs); 1689 1690 release_resource(sm->regs_claim); 1691 kfree(sm->regs_claim); 1692 1693 return 0; 1694 } 1695 1696 static const struct pci_device_id sm501_pci_tbl[] = { 1697 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 1698 { 0, }, 1699 }; 1700 1701 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl); 1702 1703 static struct pci_driver sm501_pci_driver = { 1704 .name = "sm501", 1705 .id_table = sm501_pci_tbl, 1706 .probe = sm501_pci_probe, 1707 .remove = sm501_pci_remove, 1708 }; 1709 1710 MODULE_ALIAS("platform:sm501"); 1711 1712 static const struct of_device_id of_sm501_match_tbl[] = { 1713 { .compatible = "smi,sm501", }, 1714 { /* end */ } 1715 }; 1716 MODULE_DEVICE_TABLE(of, of_sm501_match_tbl); 1717 1718 static struct platform_driver sm501_plat_driver = { 1719 .driver = { 1720 .name = "sm501", 1721 .of_match_table = of_sm501_match_tbl, 1722 }, 1723 .probe = sm501_plat_probe, 1724 .remove = sm501_plat_remove, 1725 .suspend = sm501_plat_suspend, 1726 .resume = sm501_plat_resume, 1727 }; 1728 1729 static int __init sm501_base_init(void) 1730 { 1731 platform_driver_register(&sm501_plat_driver); 1732 return pci_register_driver(&sm501_pci_driver); 1733 } 1734 1735 static void __exit sm501_base_exit(void) 1736 { 1737 platform_driver_unregister(&sm501_plat_driver); 1738 pci_unregister_driver(&sm501_pci_driver); 1739 } 1740 1741 module_init(sm501_base_init); 1742 module_exit(sm501_base_exit); 1743 1744 MODULE_DESCRIPTION("SM501 Core Driver"); 1745 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders"); 1746 MODULE_LICENSE("GPL v2"); 1747