xref: /linux/drivers/mfd/sta2x11-mfd.c (revision 44f57d78) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * STA2x11 mfd for GPIO, SCTL and APBREG
4  *
5  * Copyright (c) 2009-2011 Wind River Systems, Inc.
6  * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
7  */
8 
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/export.h>
12 #include <linux/spinlock.h>
13 #include <linux/errno.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/list.h>
17 #include <linux/io.h>
18 #include <linux/ioport.h>
19 #include <linux/pci.h>
20 #include <linux/seq_file.h>
21 #include <linux/platform_device.h>
22 #include <linux/mfd/core.h>
23 #include <linux/mfd/sta2x11-mfd.h>
24 #include <linux/regmap.h>
25 
26 #include <asm/sta2x11.h>
27 
28 static inline int __reg_within_range(unsigned int r,
29 				     unsigned int start,
30 				     unsigned int end)
31 {
32 	return ((r >= start) && (r <= end));
33 }
34 
35 /* This describes STA2X11 MFD chip for us, we may have several */
36 struct sta2x11_mfd {
37 	struct sta2x11_instance *instance;
38 	struct regmap *regmap[sta2x11_n_mfd_plat_devs];
39 	spinlock_t lock[sta2x11_n_mfd_plat_devs];
40 	struct list_head list;
41 	void __iomem *regs[sta2x11_n_mfd_plat_devs];
42 };
43 
44 static LIST_HEAD(sta2x11_mfd_list);
45 
46 /* Three functions to act on the list */
47 static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev)
48 {
49 	struct sta2x11_instance *instance;
50 	struct sta2x11_mfd *mfd;
51 
52 	if (!pdev && !list_empty(&sta2x11_mfd_list)) {
53 		pr_warn("%s: Unspecified device, using first instance\n",
54 			__func__);
55 		return list_entry(sta2x11_mfd_list.next,
56 				  struct sta2x11_mfd, list);
57 	}
58 
59 	instance = sta2x11_get_instance(pdev);
60 	if (!instance)
61 		return NULL;
62 	list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
63 		if (mfd->instance == instance)
64 			return mfd;
65 	}
66 	return NULL;
67 }
68 
69 static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
70 {
71 	int i;
72 	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
73 	struct sta2x11_instance *instance;
74 
75 	if (mfd)
76 		return -EBUSY;
77 	instance = sta2x11_get_instance(pdev);
78 	if (!instance)
79 		return -EINVAL;
80 	mfd = kzalloc(sizeof(*mfd), flags);
81 	if (!mfd)
82 		return -ENOMEM;
83 	INIT_LIST_HEAD(&mfd->list);
84 	for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
85 		spin_lock_init(&mfd->lock[i]);
86 	mfd->instance = instance;
87 	list_add(&mfd->list, &sta2x11_mfd_list);
88 	return 0;
89 }
90 
91 /* This function is exported and is not expected to fail */
92 u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
93 		       enum sta2x11_mfd_plat_dev index)
94 {
95 	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
96 	u32 r;
97 	unsigned long flags;
98 	void __iomem *regs;
99 
100 	if (!mfd) {
101 		dev_warn(&pdev->dev, ": can't access sctl regs\n");
102 		return 0;
103 	}
104 
105 	regs = mfd->regs[index];
106 	if (!regs) {
107 		dev_warn(&pdev->dev, ": system ctl not initialized\n");
108 		return 0;
109 	}
110 	spin_lock_irqsave(&mfd->lock[index], flags);
111 	r = readl(regs + reg);
112 	r &= ~mask;
113 	r |= val;
114 	if (mask)
115 		writel(r, regs + reg);
116 	spin_unlock_irqrestore(&mfd->lock[index], flags);
117 	return r;
118 }
119 EXPORT_SYMBOL(__sta2x11_mfd_mask);
120 
121 int sta2x11_mfd_get_regs_data(struct platform_device *dev,
122 			      enum sta2x11_mfd_plat_dev index,
123 			      void __iomem **regs,
124 			      spinlock_t **lock)
125 {
126 	struct pci_dev *pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
127 	struct sta2x11_mfd *mfd;
128 
129 	if (!pdev)
130 		return -ENODEV;
131 	mfd = sta2x11_mfd_find(pdev);
132 	if (!mfd)
133 		return -ENODEV;
134 	if (index >= sta2x11_n_mfd_plat_devs)
135 		return -ENODEV;
136 	*regs = mfd->regs[index];
137 	*lock = &mfd->lock[index];
138 	pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs);
139 	return *regs ? 0 : -ENODEV;
140 }
141 EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);
142 
143 /*
144  * Special sta2x11-mfd regmap lock/unlock functions
145  */
146 
147 static void sta2x11_regmap_lock(void *__lock)
148 {
149 	spinlock_t *lock = __lock;
150 	spin_lock(lock);
151 }
152 
153 static void sta2x11_regmap_unlock(void *__lock)
154 {
155 	spinlock_t *lock = __lock;
156 	spin_unlock(lock);
157 }
158 
159 /* OTP (one time programmable registers do not require locking */
160 static void sta2x11_regmap_nolock(void *__lock)
161 {
162 }
163 
164 static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
165 	[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
166 	[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
167 	[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
168 	[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
169 };
170 
171 static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
172 {
173 	return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
174 }
175 
176 static struct regmap_config sta2x11_sctl_regmap_config = {
177 	.reg_bits = 32,
178 	.reg_stride = 4,
179 	.val_bits = 32,
180 	.lock = sta2x11_regmap_lock,
181 	.unlock = sta2x11_regmap_unlock,
182 	.max_register = SCTL_SCRSTSTA,
183 	.writeable_reg = sta2x11_sctl_writeable_reg,
184 };
185 
186 static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
187 {
188 	return (reg == STA2X11_SECR_CR) ||
189 		__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
190 }
191 
192 static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
193 {
194 	return false;
195 }
196 
197 static struct regmap_config sta2x11_scr_regmap_config = {
198 	.reg_bits = 32,
199 	.reg_stride = 4,
200 	.val_bits = 32,
201 	.lock = sta2x11_regmap_nolock,
202 	.unlock = sta2x11_regmap_nolock,
203 	.max_register = STA2X11_SECR_FVR1,
204 	.readable_reg = sta2x11_scr_readable_reg,
205 	.writeable_reg = sta2x11_scr_writeable_reg,
206 };
207 
208 static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
209 {
210 	/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
211 	if (reg >= APBREG_BSR_SARAC)
212 		reg -= APBREG_BSR_SARAC;
213 	switch (reg) {
214 	case APBREG_BSR:
215 	case APBREG_PAER:
216 	case APBREG_PWAC:
217 	case APBREG_PRAC:
218 	case APBREG_PCG:
219 	case APBREG_PUR:
220 	case APBREG_EMU_PCG:
221 		return true;
222 	default:
223 		return false;
224 	}
225 }
226 
227 static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
228 {
229 	if (reg >= APBREG_BSR_SARAC)
230 		reg -= APBREG_BSR_SARAC;
231 	if (!sta2x11_apbreg_readable_reg(dev, reg))
232 		return false;
233 	return reg != APBREG_PAER;
234 }
235 
236 static struct regmap_config sta2x11_apbreg_regmap_config = {
237 	.reg_bits = 32,
238 	.reg_stride = 4,
239 	.val_bits = 32,
240 	.lock = sta2x11_regmap_lock,
241 	.unlock = sta2x11_regmap_unlock,
242 	.max_register = APBREG_EMU_PCG_SARAC,
243 	.readable_reg = sta2x11_apbreg_readable_reg,
244 	.writeable_reg = sta2x11_apbreg_writeable_reg,
245 };
246 
247 static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
248 					      unsigned int reg)
249 {
250 	return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG ||
251 		__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) ||
252 		__reg_within_range(reg, MASTER_LOCK_REG,
253 				   SYSTEM_CONFIG_STATUS_REG) ||
254 		reg == MSP_CLK_CTRL_REG ||
255 		__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
256 }
257 
258 static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
259 					       unsigned int reg)
260 {
261 	if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
262 		return false;
263 	switch (reg) {
264 	case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
265 	case SYSTEM_CONFIG_STATUS_REG:
266 	case COMPENSATION_REG1:
267 	case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
268 	case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
269 		return false;
270 	default:
271 		return true;
272 	}
273 }
274 
275 static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
276 	.reg_bits = 32,
277 	.reg_stride = 4,
278 	.val_bits = 32,
279 	.lock = sta2x11_regmap_lock,
280 	.unlock = sta2x11_regmap_unlock,
281 	.max_register = TEST_CTL_REG,
282 	.readable_reg = sta2x11_apb_soc_regs_readable_reg,
283 	.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
284 };
285 
286 static struct regmap_config *
287 sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
288 	[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
289 	[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
290 	[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
291 	[sta2x11_scr] = &sta2x11_scr_regmap_config,
292 };
293 
294 /* Probe for the four platform devices */
295 
296 static int sta2x11_mfd_platform_probe(struct platform_device *dev,
297 				      enum sta2x11_mfd_plat_dev index)
298 {
299 	struct pci_dev **pdev;
300 	struct sta2x11_mfd *mfd;
301 	struct resource *res;
302 	const char *name = sta2x11_mfd_names[index];
303 	struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];
304 
305 	pdev = dev_get_platdata(&dev->dev);
306 	mfd = sta2x11_mfd_find(*pdev);
307 	if (!mfd)
308 		return -ENODEV;
309 	if (!regmap_config)
310 		return -ENODEV;
311 
312 	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
313 	if (!res)
314 		return -ENOMEM;
315 
316 	if (!request_mem_region(res->start, resource_size(res), name))
317 		return -EBUSY;
318 
319 	mfd->regs[index] = ioremap(res->start, resource_size(res));
320 	if (!mfd->regs[index]) {
321 		release_mem_region(res->start, resource_size(res));
322 		return -ENOMEM;
323 	}
324 	regmap_config->lock_arg = &mfd->lock;
325 	/*
326 	   No caching, registers could be reached both via regmap and via
327 	   void __iomem *
328 	*/
329 	regmap_config->cache_type = REGCACHE_NONE;
330 	mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
331 						   regmap_config);
332 	WARN_ON(IS_ERR(mfd->regmap[index]));
333 
334 	return 0;
335 }
336 
337 static int sta2x11_sctl_probe(struct platform_device *dev)
338 {
339 	return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
340 }
341 
342 static int sta2x11_apbreg_probe(struct platform_device *dev)
343 {
344 	return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
345 }
346 
347 static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
348 {
349 	return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
350 }
351 
352 static int sta2x11_scr_probe(struct platform_device *dev)
353 {
354 	return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
355 }
356 
357 /* The three platform drivers */
358 static struct platform_driver sta2x11_sctl_platform_driver = {
359 	.driver = {
360 		.name	= STA2X11_MFD_SCTL_NAME,
361 	},
362 	.probe		= sta2x11_sctl_probe,
363 };
364 
365 static struct platform_driver sta2x11_platform_driver = {
366 	.driver = {
367 		.name	= STA2X11_MFD_APBREG_NAME,
368 	},
369 	.probe		= sta2x11_apbreg_probe,
370 };
371 
372 static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
373 	.driver = {
374 		.name	= STA2X11_MFD_APB_SOC_REGS_NAME,
375 	},
376 	.probe		= sta2x11_apb_soc_regs_probe,
377 };
378 
379 static struct platform_driver sta2x11_scr_platform_driver = {
380 	.driver = {
381 		.name = STA2X11_MFD_SCR_NAME,
382 	},
383 	.probe = sta2x11_scr_probe,
384 };
385 
386 static struct platform_driver * const drivers[] = {
387 	&sta2x11_platform_driver,
388 	&sta2x11_sctl_platform_driver,
389 	&sta2x11_apb_soc_regs_platform_driver,
390 	&sta2x11_scr_platform_driver,
391 };
392 
393 static int __init sta2x11_drivers_init(void)
394 {
395 	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
396 }
397 
398 /*
399  * What follows are the PCI devices that host the above pdevs.
400  * Each logic block is 4kB and they are all consecutive: we use this info.
401  */
402 
403 /* Mfd 0 device */
404 
405 /* Mfd 0, Bar 0 */
406 enum mfd0_bar0_cells {
407 	STA2X11_GPIO_0 = 0,
408 	STA2X11_GPIO_1,
409 	STA2X11_GPIO_2,
410 	STA2X11_GPIO_3,
411 	STA2X11_SCTL,
412 	STA2X11_SCR,
413 	STA2X11_TIME,
414 };
415 /* Mfd 0 , Bar 1 */
416 enum mfd0_bar1_cells {
417 	STA2X11_APBREG = 0,
418 };
419 #define CELL_4K(_name, _cell) { \
420 		.name = _name, \
421 		.start = _cell * 4096, .end = _cell * 4096 + 4095, \
422 		.flags = IORESOURCE_MEM, \
423 		}
424 
425 static const struct resource gpio_resources[] = {
426 	{
427 		/* 4 consecutive cells, 1 driver */
428 		.name = STA2X11_MFD_GPIO_NAME,
429 		.start = 0,
430 		.end = (4 * 4096) - 1,
431 		.flags = IORESOURCE_MEM,
432 	}
433 };
434 static const struct resource sctl_resources[] = {
435 	CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
436 };
437 static const struct resource scr_resources[] = {
438 	CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
439 };
440 static const struct resource time_resources[] = {
441 	CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
442 };
443 
444 static const struct resource apbreg_resources[] = {
445 	CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
446 };
447 
448 #define DEV(_name, _r) \
449 	{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }
450 
451 static struct mfd_cell sta2x11_mfd0_bar0[] = {
452 	/* offset 0: we add pdata later */
453 	DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
454 	DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
455 	DEV(STA2X11_MFD_SCR_NAME,  scr_resources),
456 	DEV(STA2X11_MFD_TIME_NAME, time_resources),
457 };
458 
459 static struct mfd_cell sta2x11_mfd0_bar1[] = {
460 	DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
461 };
462 
463 /* Mfd 1 devices */
464 
465 /* Mfd 1, Bar 0 */
466 enum mfd1_bar0_cells {
467 	STA2X11_VIC = 0,
468 };
469 
470 /* Mfd 1, Bar 1 */
471 enum mfd1_bar1_cells {
472 	STA2X11_APB_SOC_REGS = 0,
473 };
474 
475 static const struct resource vic_resources[] = {
476 	CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
477 };
478 
479 static const struct resource apb_soc_regs_resources[] = {
480 	CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
481 };
482 
483 static struct mfd_cell sta2x11_mfd1_bar0[] = {
484 	DEV(STA2X11_MFD_VIC_NAME, vic_resources),
485 };
486 
487 static struct mfd_cell sta2x11_mfd1_bar1[] = {
488 	DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
489 };
490 
491 
492 static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
493 {
494 	pci_save_state(pdev);
495 	pci_disable_device(pdev);
496 	pci_set_power_state(pdev, pci_choose_state(pdev, state));
497 
498 	return 0;
499 }
500 
501 static int sta2x11_mfd_resume(struct pci_dev *pdev)
502 {
503 	int err;
504 
505 	pci_set_power_state(pdev, PCI_D0);
506 	err = pci_enable_device(pdev);
507 	if (err)
508 		return err;
509 	pci_restore_state(pdev);
510 
511 	return 0;
512 }
513 
514 struct sta2x11_mfd_bar_setup_data {
515 	struct mfd_cell *cells;
516 	int ncells;
517 };
518 
519 struct sta2x11_mfd_setup_data {
520 	struct sta2x11_mfd_bar_setup_data bars[2];
521 };
522 
523 #define STA2X11_MFD0 0
524 #define STA2X11_MFD1 1
525 
526 static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
527 	/* Mfd 0: gpio, sctl, scr, timers / apbregs */
528 	[STA2X11_MFD0] = {
529 		.bars = {
530 			[0] = {
531 				.cells = sta2x11_mfd0_bar0,
532 				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
533 			},
534 			[1] = {
535 				.cells = sta2x11_mfd0_bar1,
536 				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
537 			},
538 		},
539 	},
540 	/* Mfd 1: vic / apb-soc-regs */
541 	[STA2X11_MFD1] = {
542 		.bars = {
543 			[0] = {
544 				.cells = sta2x11_mfd1_bar0,
545 				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
546 			},
547 			[1] = {
548 				.cells = sta2x11_mfd1_bar1,
549 				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
550 			},
551 		},
552 	},
553 };
554 
555 static void sta2x11_mfd_setup(struct pci_dev *pdev,
556 			      struct sta2x11_mfd_setup_data *sd)
557 {
558 	int i, j;
559 	for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
560 		for (j = 0; j < sd->bars[i].ncells; j++) {
561 			sd->bars[i].cells[j].pdata_size = sizeof(pdev);
562 			sd->bars[i].cells[j].platform_data = &pdev;
563 		}
564 }
565 
566 static int sta2x11_mfd_probe(struct pci_dev *pdev,
567 			     const struct pci_device_id *pci_id)
568 {
569 	int err, i;
570 	struct sta2x11_mfd_setup_data *setup_data;
571 
572 	dev_info(&pdev->dev, "%s\n", __func__);
573 
574 	err = pci_enable_device(pdev);
575 	if (err) {
576 		dev_err(&pdev->dev, "Can't enable device.\n");
577 		return err;
578 	}
579 
580 	err = pci_enable_msi(pdev);
581 	if (err)
582 		dev_info(&pdev->dev, "Enable msi failed\n");
583 
584 	setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
585 		&mfd_setup_data[STA2X11_MFD0] :
586 		&mfd_setup_data[STA2X11_MFD1];
587 
588 	/* platform data is the pci device for all of them */
589 	sta2x11_mfd_setup(pdev, setup_data);
590 
591 	/* Record this pdev before mfd_add_devices: their probe looks for it */
592 	if (!sta2x11_mfd_find(pdev))
593 		sta2x11_mfd_add(pdev, GFP_ATOMIC);
594 
595 	/* Just 2 bars for all mfd's at present */
596 	for (i = 0; i < 2; i++) {
597 		err = mfd_add_devices(&pdev->dev, -1,
598 				      setup_data->bars[i].cells,
599 				      setup_data->bars[i].ncells,
600 				      &pdev->resource[i],
601 				      0, NULL);
602 		if (err) {
603 			dev_err(&pdev->dev,
604 				"mfd_add_devices[%d] failed: %d\n", i, err);
605 			goto err_disable;
606 		}
607 	}
608 
609 	return 0;
610 
611 err_disable:
612 	mfd_remove_devices(&pdev->dev);
613 	pci_disable_device(pdev);
614 	pci_disable_msi(pdev);
615 	return err;
616 }
617 
618 static const struct pci_device_id sta2x11_mfd_tbl[] = {
619 	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
620 	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
621 	{0,},
622 };
623 
624 static struct pci_driver sta2x11_mfd_driver = {
625 	.name =		"sta2x11-mfd",
626 	.id_table =	sta2x11_mfd_tbl,
627 	.probe =	sta2x11_mfd_probe,
628 	.suspend =	sta2x11_mfd_suspend,
629 	.resume =	sta2x11_mfd_resume,
630 };
631 
632 static int __init sta2x11_mfd_init(void)
633 {
634 	pr_info("%s\n", __func__);
635 	return pci_register_driver(&sta2x11_mfd_driver);
636 }
637 
638 /*
639  * All of this must be ready before "normal" devices like MMCI appear.
640  * But MFD (the pci device) can't be too early. The following choice
641  * prepares platform drivers very early and probe the PCI device later,
642  * but before other PCI devices.
643  */
644 subsys_initcall(sta2x11_drivers_init);
645 rootfs_initcall(sta2x11_mfd_init);
646