1c0e5f4e7SRui Feng /* SPDX-License-Identifier: GPL-2.0-only */ 2c0e5f4e7SRui Feng /* Driver for Realtek PCI-Express card reader 3c0e5f4e7SRui Feng * 4c0e5f4e7SRui Feng * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. 5c0e5f4e7SRui Feng * 6c0e5f4e7SRui Feng * Author: 7c0e5f4e7SRui Feng * Rui FENG <rui_feng@realsil.com.cn> 8c0e5f4e7SRui Feng * Wei WANG <wei_wang@realsil.com.cn> 9c0e5f4e7SRui Feng */ 10c0e5f4e7SRui Feng #ifndef RTS5261_H 11c0e5f4e7SRui Feng #define RTS5261_H 12c0e5f4e7SRui Feng 13c0e5f4e7SRui Feng /*New add*/ 14c0e5f4e7SRui Feng #define rts5261_vendor_setting_valid(reg) ((reg) & 0x010000) 150a3bbf92SRui Feng #define rts5261_reg_to_aspm(reg) \ 160a3bbf92SRui Feng (((~(reg) >> 28) & 0x02) | (((reg) >> 28) & 0x01)) 17c0e5f4e7SRui Feng #define rts5261_reg_check_reverse_socket(reg) ((reg) & 0x04) 186f61dd28SRui Feng #define rts5261_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) & 0x03) 196f61dd28SRui Feng #define rts5261_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) & 0x03) 20*5b0f429eSRui Feng #define rts5261_reg_to_rtd3(reg) ((reg) & 0x08) 21*5b0f429eSRui Feng #define rts5261_reg_check_mmc_support(reg) ((reg) & 0x10) 22c0e5f4e7SRui Feng 23c0e5f4e7SRui Feng #define RTS5261_AUTOLOAD_CFG0 0xFF7B 24c0e5f4e7SRui Feng #define RTS5261_AUTOLOAD_CFG1 0xFF7C 25c0e5f4e7SRui Feng #define RTS5261_AUTOLOAD_CFG2 0xFF7D 26c0e5f4e7SRui Feng #define RTS5261_AUTOLOAD_CFG3 0xFF7E 27c0e5f4e7SRui Feng #define RTS5261_AUTOLOAD_CFG4 0xFF7F 28c0e5f4e7SRui Feng #define RTS5261_FORCE_PRSNT_LOW (1 << 6) 29c0e5f4e7SRui Feng #define RTS5261_AUX_CLK_16M_EN (1 << 5) 30c0e5f4e7SRui Feng 31c0e5f4e7SRui Feng #define RTS5261_REG_VREF 0xFE97 32c0e5f4e7SRui Feng #define RTS5261_PWD_SUSPND_EN (1 << 4) 33c0e5f4e7SRui Feng 34c0e5f4e7SRui Feng #define RTS5261_PAD_H3L1 0xFF79 35c0e5f4e7SRui Feng #define PAD_GPIO_H3L1 (1 << 3) 36c0e5f4e7SRui Feng 37c0e5f4e7SRui Feng /* SSC_CTL2 0xFC12 */ 38c0e5f4e7SRui Feng #define RTS5261_SSC_DEPTH_MASK 0x07 39c0e5f4e7SRui Feng #define RTS5261_SSC_DEPTH_DISALBE 0x00 40c0e5f4e7SRui Feng #define RTS5261_SSC_DEPTH_8M 0x01 41c0e5f4e7SRui Feng #define RTS5261_SSC_DEPTH_4M 0x02 42c0e5f4e7SRui Feng #define RTS5261_SSC_DEPTH_2M 0x03 43c0e5f4e7SRui Feng #define RTS5261_SSC_DEPTH_1M 0x04 44c0e5f4e7SRui Feng #define RTS5261_SSC_DEPTH_512K 0x05 45c0e5f4e7SRui Feng #define RTS5261_SSC_DEPTH_256K 0x06 46c0e5f4e7SRui Feng #define RTS5261_SSC_DEPTH_128K 0x07 47c0e5f4e7SRui Feng 48c0e5f4e7SRui Feng /* efuse control register*/ 49c0e5f4e7SRui Feng #define RTS5261_EFUSE_CTL 0xFC30 50c0e5f4e7SRui Feng #define RTS5261_EFUSE_ENABLE 0x80 51c0e5f4e7SRui Feng /* EFUSE_MODE: 0=READ 1=PROGRAM */ 52c0e5f4e7SRui Feng #define RTS5261_EFUSE_MODE_MASK 0x40 53c0e5f4e7SRui Feng #define RTS5261_EFUSE_PROGRAM 0x40 54c0e5f4e7SRui Feng 55c0e5f4e7SRui Feng #define RTS5261_EFUSE_ADDR 0xFC31 56c0e5f4e7SRui Feng #define RTS5261_EFUSE_ADDR_MASK 0x3F 57c0e5f4e7SRui Feng 58c0e5f4e7SRui Feng #define RTS5261_EFUSE_WRITE_DATA 0xFC32 59c0e5f4e7SRui Feng #define RTS5261_EFUSE_READ_DATA 0xFC34 60c0e5f4e7SRui Feng 61c0e5f4e7SRui Feng /* DMACTL 0xFE2C */ 62c0e5f4e7SRui Feng #define RTS5261_DMA_PACK_SIZE_MASK 0xF0 63c0e5f4e7SRui Feng 64c0e5f4e7SRui Feng /* FW status register */ 65c0e5f4e7SRui Feng #define RTS5261_FW_STATUS 0xFF56 66c0e5f4e7SRui Feng #define RTS5261_EXPRESS_LINK_FAIL_MASK (0x01<<7) 67c0e5f4e7SRui Feng 68c0e5f4e7SRui Feng /* FW control register */ 69c0e5f4e7SRui Feng #define RTS5261_FW_CTL 0xFF5F 70c0e5f4e7SRui Feng #define RTS5261_INFORM_RTD3_COLD (0x01<<5) 71c0e5f4e7SRui Feng 72c0e5f4e7SRui Feng #define RTS5261_REG_FPDCTL 0xFF60 73c0e5f4e7SRui Feng 74c0e5f4e7SRui Feng #define RTS5261_REG_LDO12_CFG 0xFF6E 75c0e5f4e7SRui Feng #define RTS5261_LDO12_VO_TUNE_MASK (0x07<<1) 76c0e5f4e7SRui Feng #define RTS5261_LDO12_115 (0x03<<1) 77c0e5f4e7SRui Feng #define RTS5261_LDO12_120 (0x04<<1) 78c0e5f4e7SRui Feng #define RTS5261_LDO12_125 (0x05<<1) 79c0e5f4e7SRui Feng #define RTS5261_LDO12_130 (0x06<<1) 80c0e5f4e7SRui Feng #define RTS5261_LDO12_135 (0x07<<1) 81c0e5f4e7SRui Feng 82c0e5f4e7SRui Feng /* LDO control register */ 83c0e5f4e7SRui Feng #define RTS5261_CARD_PWR_CTL 0xFD50 84c0e5f4e7SRui Feng #define RTS5261_SD_CLK_ISO (0x01<<7) 85c0e5f4e7SRui Feng #define RTS5261_PAD_SD_DAT_FW_CTRL (0x01<<6) 86c0e5f4e7SRui Feng #define RTS5261_PUPDC (0x01<<5) 87c0e5f4e7SRui Feng #define RTS5261_SD_CMD_ISO (0x01<<4) 88c0e5f4e7SRui Feng #define RTS5261_SD_DAT_ISO_MASK (0x0F<<0) 89c0e5f4e7SRui Feng 90c0e5f4e7SRui Feng #define RTS5261_LDO1233318_POW_CTL 0xFF70 91c0e5f4e7SRui Feng #define RTS5261_LDO3318_POWERON (0x01<<3) 92c0e5f4e7SRui Feng #define RTS5261_LDO3_POWERON (0x01<<2) 93c0e5f4e7SRui Feng #define RTS5261_LDO2_POWERON (0x01<<1) 94c0e5f4e7SRui Feng #define RTS5261_LDO1_POWERON (0x01<<0) 95c0e5f4e7SRui Feng #define RTS5261_LDO_POWERON_MASK (0x0F<<0) 96c0e5f4e7SRui Feng 97c0e5f4e7SRui Feng #define RTS5261_DV3318_CFG 0xFF71 98c0e5f4e7SRui Feng #define RTS5261_DV3318_TUNE_MASK (0x07<<4) 99c0e5f4e7SRui Feng #define RTS5261_DV3318_18 (0x02<<4) 100c0e5f4e7SRui Feng #define RTS5261_DV3318_19 (0x04<<4) 101c0e5f4e7SRui Feng #define RTS5261_DV3318_33 (0x07<<4) 102c0e5f4e7SRui Feng 103c0e5f4e7SRui Feng /* CRD6603-433 190319 request changed */ 104c0e5f4e7SRui Feng #define RTS5261_LDO1_OCP_THD_740 (0x00<<5) 105c0e5f4e7SRui Feng #define RTS5261_LDO1_OCP_THD_800 (0x01<<5) 106c0e5f4e7SRui Feng #define RTS5261_LDO1_OCP_THD_860 (0x02<<5) 107c0e5f4e7SRui Feng #define RTS5261_LDO1_OCP_THD_920 (0x03<<5) 108c0e5f4e7SRui Feng #define RTS5261_LDO1_OCP_THD_980 (0x04<<5) 109c0e5f4e7SRui Feng #define RTS5261_LDO1_OCP_THD_1040 (0x05<<5) 110c0e5f4e7SRui Feng #define RTS5261_LDO1_OCP_THD_1100 (0x06<<5) 111c0e5f4e7SRui Feng #define RTS5261_LDO1_OCP_THD_1160 (0x07<<5) 112c0e5f4e7SRui Feng 113c0e5f4e7SRui Feng #define RTS5261_LDO1_LMT_THD_450 (0x00<<2) 114c0e5f4e7SRui Feng #define RTS5261_LDO1_LMT_THD_1000 (0x01<<2) 115c0e5f4e7SRui Feng #define RTS5261_LDO1_LMT_THD_1500 (0x02<<2) 116c0e5f4e7SRui Feng #define RTS5261_LDO1_LMT_THD_2000 (0x03<<2) 117c0e5f4e7SRui Feng 118c0e5f4e7SRui Feng #define RTS5261_LDO1_CFG1 0xFF73 119c0e5f4e7SRui Feng #define RTS5261_LDO1_TUNE_MASK (0x07<<1) 120c0e5f4e7SRui Feng #define RTS5261_LDO1_18 (0x05<<1) 121c0e5f4e7SRui Feng #define RTS5261_LDO1_33 (0x07<<1) 122c0e5f4e7SRui Feng #define RTS5261_LDO1_PWD_MASK (0x01<<0) 123c0e5f4e7SRui Feng 124c0e5f4e7SRui Feng #define RTS5261_LDO2_CFG0 0xFF74 125c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_THD_MASK (0x07<<5) 126c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_EN (0x01<<4) 127c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_LMT_THD_MASK (0x03<<2) 128c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_LMT_EN (0x01<<1) 129c0e5f4e7SRui Feng 130c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_THD_620 (0x00<<5) 131c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_THD_650 (0x01<<5) 132c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_THD_680 (0x02<<5) 133c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_THD_720 (0x03<<5) 134c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_THD_750 (0x04<<5) 135c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_THD_780 (0x05<<5) 136c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_THD_810 (0x06<<5) 137c0e5f4e7SRui Feng #define RTS5261_LDO2_OCP_THD_840 (0x07<<5) 138c0e5f4e7SRui Feng 139c0e5f4e7SRui Feng #define RTS5261_LDO2_CFG1 0xFF75 140c0e5f4e7SRui Feng #define RTS5261_LDO2_TUNE_MASK (0x07<<1) 141c0e5f4e7SRui Feng #define RTS5261_LDO2_18 (0x05<<1) 142c0e5f4e7SRui Feng #define RTS5261_LDO2_33 (0x07<<1) 143c0e5f4e7SRui Feng #define RTS5261_LDO2_PWD_MASK (0x01<<0) 144c0e5f4e7SRui Feng 145c0e5f4e7SRui Feng #define RTS5261_LDO3_CFG0 0xFF76 146c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_THD_MASK (0x07<<5) 147c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_EN (0x01<<4) 148c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_LMT_THD_MASK (0x03<<2) 149c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_LMT_EN (0x01<<1) 150c0e5f4e7SRui Feng 151c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_THD_620 (0x00<<5) 152c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_THD_650 (0x01<<5) 153c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_THD_680 (0x02<<5) 154c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_THD_720 (0x03<<5) 155c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_THD_750 (0x04<<5) 156c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_THD_780 (0x05<<5) 157c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_THD_810 (0x06<<5) 158c0e5f4e7SRui Feng #define RTS5261_LDO3_OCP_THD_840 (0x07<<5) 159c0e5f4e7SRui Feng 160c0e5f4e7SRui Feng #define RTS5261_LDO3_CFG1 0xFF77 161c0e5f4e7SRui Feng #define RTS5261_LDO3_TUNE_MASK (0x07<<1) 162c0e5f4e7SRui Feng #define RTS5261_LDO3_18 (0x05<<1) 163c0e5f4e7SRui Feng #define RTS5261_LDO3_33 (0x07<<1) 164c0e5f4e7SRui Feng #define RTS5261_LDO3_PWD_MASK (0x01<<0) 165c0e5f4e7SRui Feng 166c0e5f4e7SRui Feng #define RTS5261_REG_PME_FORCE_CTL 0xFF78 167c0e5f4e7SRui Feng #define FORCE_PM_CONTROL 0x20 168c0e5f4e7SRui Feng #define FORCE_PM_VALUE 0x10 169c0e5f4e7SRui Feng #define REG_EFUSE_BYPASS 0x08 170c0e5f4e7SRui Feng #define REG_EFUSE_POR 0x04 171c0e5f4e7SRui Feng #define REG_EFUSE_POWER_MASK 0x03 172c0e5f4e7SRui Feng #define REG_EFUSE_POWERON 0x03 173c0e5f4e7SRui Feng #define REG_EFUSE_POWEROFF 0x00 174c0e5f4e7SRui Feng 175c0e5f4e7SRui Feng 176c0e5f4e7SRui Feng /* Single LUN, support SD/SD EXPRESS */ 177c0e5f4e7SRui Feng #define DEFAULT_SINGLE 0 178c0e5f4e7SRui Feng #define SD_LUN 1 179c0e5f4e7SRui Feng #define SD_EXPRESS_LUN 2 180c0e5f4e7SRui Feng 181c0e5f4e7SRui Feng /* For Change_FPGA_SSCClock Function */ 182c0e5f4e7SRui Feng #define MULTIPLY_BY_1 0x00 183c0e5f4e7SRui Feng #define MULTIPLY_BY_2 0x01 184c0e5f4e7SRui Feng #define MULTIPLY_BY_3 0x02 185c0e5f4e7SRui Feng #define MULTIPLY_BY_4 0x03 186c0e5f4e7SRui Feng #define MULTIPLY_BY_5 0x04 187c0e5f4e7SRui Feng #define MULTIPLY_BY_6 0x05 188c0e5f4e7SRui Feng #define MULTIPLY_BY_7 0x06 189c0e5f4e7SRui Feng #define MULTIPLY_BY_8 0x07 190c0e5f4e7SRui Feng #define MULTIPLY_BY_9 0x08 191c0e5f4e7SRui Feng #define MULTIPLY_BY_10 0x09 192c0e5f4e7SRui Feng 193c0e5f4e7SRui Feng #define DIVIDE_BY_2 0x01 194c0e5f4e7SRui Feng #define DIVIDE_BY_3 0x02 195c0e5f4e7SRui Feng #define DIVIDE_BY_4 0x03 196c0e5f4e7SRui Feng #define DIVIDE_BY_5 0x04 197c0e5f4e7SRui Feng #define DIVIDE_BY_6 0x05 198c0e5f4e7SRui Feng #define DIVIDE_BY_7 0x06 199c0e5f4e7SRui Feng #define DIVIDE_BY_8 0x07 200c0e5f4e7SRui Feng #define DIVIDE_BY_9 0x08 201c0e5f4e7SRui Feng #define DIVIDE_BY_10 0x09 202c0e5f4e7SRui Feng 203c0e5f4e7SRui Feng int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 204c0e5f4e7SRui Feng u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); 205c0e5f4e7SRui Feng 206c0e5f4e7SRui Feng #endif /* RTS5261_H */ 207