1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Kevin Hilman <khilman@baylibre.com> 7 */ 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/iopoll.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/ioport.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/mmc/host.h> 19 #include <linux/mmc/mmc.h> 20 #include <linux/mmc/sdio.h> 21 #include <linux/mmc/slot-gpio.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/reset.h> 27 #include <linux/interrupt.h> 28 #include <linux/bitfield.h> 29 #include <linux/pinctrl/consumer.h> 30 31 #define DRIVER_NAME "meson-gx-mmc" 32 33 #define SD_EMMC_CLOCK 0x0 34 #define CLK_DIV_MASK GENMASK(5, 0) 35 #define CLK_SRC_MASK GENMASK(7, 6) 36 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 37 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 38 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 39 #define CLK_PHASE_0 0 40 #define CLK_PHASE_180 2 41 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 42 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 43 #define CLK_V2_ALWAYS_ON BIT(24) 44 45 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 46 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 47 #define CLK_V3_ALWAYS_ON BIT(28) 48 49 #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) 50 #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) 51 #define CLK_ALWAYS_ON(h) (h->data->always_on) 52 53 #define SD_EMMC_DELAY 0x4 54 #define SD_EMMC_ADJUST 0x8 55 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 56 #define ADJUST_DS_EN BIT(15) 57 #define ADJUST_ADJ_EN BIT(13) 58 59 #define SD_EMMC_DELAY1 0x4 60 #define SD_EMMC_DELAY2 0x8 61 #define SD_EMMC_V3_ADJUST 0xc 62 63 #define SD_EMMC_CALOUT 0x10 64 #define SD_EMMC_START 0x40 65 #define START_DESC_INIT BIT(0) 66 #define START_DESC_BUSY BIT(1) 67 #define START_DESC_ADDR_MASK GENMASK(31, 2) 68 69 #define SD_EMMC_CFG 0x44 70 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 71 #define CFG_BUS_WIDTH_1 0x0 72 #define CFG_BUS_WIDTH_4 0x1 73 #define CFG_BUS_WIDTH_8 0x2 74 #define CFG_DDR BIT(2) 75 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 76 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 77 #define CFG_RC_CC_MASK GENMASK(15, 12) 78 #define CFG_STOP_CLOCK BIT(22) 79 #define CFG_CLK_ALWAYS_ON BIT(18) 80 #define CFG_CHK_DS BIT(20) 81 #define CFG_AUTO_CLK BIT(23) 82 #define CFG_ERR_ABORT BIT(27) 83 84 #define SD_EMMC_STATUS 0x48 85 #define STATUS_BUSY BIT(31) 86 #define STATUS_DESC_BUSY BIT(30) 87 #define STATUS_DATI GENMASK(23, 16) 88 89 #define SD_EMMC_IRQ_EN 0x4c 90 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 91 #define IRQ_TXD_ERR BIT(8) 92 #define IRQ_DESC_ERR BIT(9) 93 #define IRQ_RESP_ERR BIT(10) 94 #define IRQ_CRC_ERR \ 95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 96 #define IRQ_RESP_TIMEOUT BIT(11) 97 #define IRQ_DESC_TIMEOUT BIT(12) 98 #define IRQ_TIMEOUTS \ 99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 100 #define IRQ_END_OF_CHAIN BIT(13) 101 #define IRQ_RESP_STATUS BIT(14) 102 #define IRQ_SDIO BIT(15) 103 #define IRQ_EN_MASK \ 104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\ 105 IRQ_SDIO) 106 107 #define SD_EMMC_CMD_CFG 0x50 108 #define SD_EMMC_CMD_ARG 0x54 109 #define SD_EMMC_CMD_DAT 0x58 110 #define SD_EMMC_CMD_RSP 0x5c 111 #define SD_EMMC_CMD_RSP1 0x60 112 #define SD_EMMC_CMD_RSP2 0x64 113 #define SD_EMMC_CMD_RSP3 0x68 114 115 #define SD_EMMC_RXD 0x94 116 #define SD_EMMC_TXD 0x94 117 #define SD_EMMC_LAST_REG SD_EMMC_TXD 118 119 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 120 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 121 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 122 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 123 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 124 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 125 126 #define SD_EMMC_PRE_REQ_DONE BIT(0) 127 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 128 129 #define MUX_CLK_NUM_PARENTS 2 130 131 struct meson_mmc_data { 132 unsigned int tx_delay_mask; 133 unsigned int rx_delay_mask; 134 unsigned int always_on; 135 unsigned int adjust; 136 }; 137 138 struct sd_emmc_desc { 139 u32 cmd_cfg; 140 u32 cmd_arg; 141 u32 cmd_data; 142 u32 cmd_resp; 143 }; 144 145 struct meson_host { 146 struct device *dev; 147 struct meson_mmc_data *data; 148 struct mmc_host *mmc; 149 struct mmc_command *cmd; 150 151 void __iomem *regs; 152 struct clk *core_clk; 153 struct clk *mux_clk; 154 struct clk *mmc_clk; 155 unsigned long req_rate; 156 bool ddr; 157 158 struct pinctrl *pinctrl; 159 struct pinctrl_state *pins_default; 160 struct pinctrl_state *pins_clk_gate; 161 162 unsigned int bounce_buf_size; 163 void *bounce_buf; 164 dma_addr_t bounce_dma_addr; 165 struct sd_emmc_desc *descs; 166 dma_addr_t descs_dma_addr; 167 168 int irq; 169 170 bool vqmmc_enabled; 171 }; 172 173 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 174 #define CMD_CFG_BLOCK_MODE BIT(9) 175 #define CMD_CFG_R1B BIT(10) 176 #define CMD_CFG_END_OF_CHAIN BIT(11) 177 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 178 #define CMD_CFG_NO_RESP BIT(16) 179 #define CMD_CFG_NO_CMD BIT(17) 180 #define CMD_CFG_DATA_IO BIT(18) 181 #define CMD_CFG_DATA_WR BIT(19) 182 #define CMD_CFG_RESP_NOCRC BIT(20) 183 #define CMD_CFG_RESP_128 BIT(21) 184 #define CMD_CFG_RESP_NUM BIT(22) 185 #define CMD_CFG_DATA_NUM BIT(23) 186 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 187 #define CMD_CFG_ERROR BIT(30) 188 #define CMD_CFG_OWNER BIT(31) 189 190 #define CMD_DATA_MASK GENMASK(31, 2) 191 #define CMD_DATA_BIG_ENDIAN BIT(1) 192 #define CMD_DATA_SRAM BIT(0) 193 #define CMD_RESP_MASK GENMASK(31, 1) 194 #define CMD_RESP_SRAM BIT(0) 195 196 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) 197 { 198 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; 199 200 if (!timeout) 201 return SD_EMMC_CMD_TIMEOUT_DATA; 202 203 timeout = roundup_pow_of_two(timeout); 204 205 return min(timeout, 32768U); /* max. 2^15 ms */ 206 } 207 208 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd) 209 { 210 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) 211 return cmd->mrq->cmd; 212 else if (mmc_op_multi(cmd->opcode) && 213 (!cmd->mrq->sbc || cmd->error || cmd->data->error)) 214 return cmd->mrq->stop; 215 else 216 return NULL; 217 } 218 219 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc, 220 struct mmc_request *mrq) 221 { 222 struct mmc_data *data = mrq->data; 223 struct scatterlist *sg; 224 int i; 225 bool use_desc_chain_mode = true; 226 227 /* 228 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been 229 * reported. For some strange reason this occurs in descriptor 230 * chain mode only. So let's fall back to bounce buffer mode 231 * for command SD_IO_RW_EXTENDED. 232 */ 233 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED) 234 return; 235 236 for_each_sg(data->sg, sg, data->sg_len, i) 237 /* check for 8 byte alignment */ 238 if (sg->offset & 7) { 239 WARN_ONCE(1, "unaligned scatterlist buffer\n"); 240 use_desc_chain_mode = false; 241 break; 242 } 243 244 if (use_desc_chain_mode) 245 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE; 246 } 247 248 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data) 249 { 250 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE; 251 } 252 253 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data) 254 { 255 return data && data->flags & MMC_DATA_READ && 256 !meson_mmc_desc_chain_mode(data); 257 } 258 259 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 260 { 261 struct mmc_data *data = mrq->data; 262 263 if (!data) 264 return; 265 266 meson_mmc_get_transfer_mode(mmc, mrq); 267 data->host_cookie |= SD_EMMC_PRE_REQ_DONE; 268 269 if (!meson_mmc_desc_chain_mode(data)) 270 return; 271 272 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, 273 mmc_get_dma_dir(data)); 274 if (!data->sg_count) 275 dev_err(mmc_dev(mmc), "dma_map_sg failed"); 276 } 277 278 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 279 int err) 280 { 281 struct mmc_data *data = mrq->data; 282 283 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count) 284 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 285 mmc_get_dma_dir(data)); 286 } 287 288 /* 289 * Gating the clock on this controller is tricky. It seems the mmc clock 290 * is also used by the controller. It may crash during some operation if the 291 * clock is stopped. The safest thing to do, whenever possible, is to keep 292 * clock running at stop it at the pad using the pinmux. 293 */ 294 static void meson_mmc_clk_gate(struct meson_host *host) 295 { 296 u32 cfg; 297 298 if (host->pins_clk_gate) { 299 pinctrl_select_state(host->pinctrl, host->pins_clk_gate); 300 } else { 301 /* 302 * If the pinmux is not provided - default to the classic and 303 * unsafe method 304 */ 305 cfg = readl(host->regs + SD_EMMC_CFG); 306 cfg |= CFG_STOP_CLOCK; 307 writel(cfg, host->regs + SD_EMMC_CFG); 308 } 309 } 310 311 static void meson_mmc_clk_ungate(struct meson_host *host) 312 { 313 u32 cfg; 314 315 if (host->pins_clk_gate) 316 pinctrl_select_state(host->pinctrl, host->pins_default); 317 318 /* Make sure the clock is not stopped in the controller */ 319 cfg = readl(host->regs + SD_EMMC_CFG); 320 cfg &= ~CFG_STOP_CLOCK; 321 writel(cfg, host->regs + SD_EMMC_CFG); 322 } 323 324 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, 325 bool ddr) 326 { 327 struct mmc_host *mmc = host->mmc; 328 int ret; 329 u32 cfg; 330 331 /* Same request - bail-out */ 332 if (host->ddr == ddr && host->req_rate == rate) 333 return 0; 334 335 /* stop clock */ 336 meson_mmc_clk_gate(host); 337 host->req_rate = 0; 338 mmc->actual_clock = 0; 339 340 /* return with clock being stopped */ 341 if (!rate) 342 return 0; 343 344 /* Stop the clock during rate change to avoid glitches */ 345 cfg = readl(host->regs + SD_EMMC_CFG); 346 cfg |= CFG_STOP_CLOCK; 347 writel(cfg, host->regs + SD_EMMC_CFG); 348 349 if (ddr) { 350 /* DDR modes require higher module clock */ 351 rate <<= 1; 352 cfg |= CFG_DDR; 353 } else { 354 cfg &= ~CFG_DDR; 355 } 356 writel(cfg, host->regs + SD_EMMC_CFG); 357 host->ddr = ddr; 358 359 ret = clk_set_rate(host->mmc_clk, rate); 360 if (ret) { 361 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", 362 rate, ret); 363 return ret; 364 } 365 366 host->req_rate = rate; 367 mmc->actual_clock = clk_get_rate(host->mmc_clk); 368 369 /* We should report the real output frequency of the controller */ 370 if (ddr) { 371 host->req_rate >>= 1; 372 mmc->actual_clock >>= 1; 373 } 374 375 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); 376 if (rate != mmc->actual_clock) 377 dev_dbg(host->dev, "requested rate was %lu\n", rate); 378 379 /* (re)start clock */ 380 meson_mmc_clk_ungate(host); 381 382 return 0; 383 } 384 385 /* 386 * The SD/eMMC IP block has an internal mux and divider used for 387 * generating the MMC clock. Use the clock framework to create and 388 * manage these clocks. 389 */ 390 static int meson_mmc_clk_init(struct meson_host *host) 391 { 392 struct clk_init_data init; 393 struct clk_mux *mux; 394 struct clk_divider *div; 395 char clk_name[32]; 396 int i, ret = 0; 397 const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; 398 const char *clk_parent[1]; 399 u32 clk_reg; 400 401 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 402 clk_reg = CLK_ALWAYS_ON(host); 403 clk_reg |= CLK_DIV_MASK; 404 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); 405 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); 406 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); 407 writel(clk_reg, host->regs + SD_EMMC_CLOCK); 408 409 /* get the mux parents */ 410 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { 411 struct clk *clk; 412 char name[16]; 413 414 snprintf(name, sizeof(name), "clkin%d", i); 415 clk = devm_clk_get(host->dev, name); 416 if (IS_ERR(clk)) { 417 if (clk != ERR_PTR(-EPROBE_DEFER)) 418 dev_err(host->dev, "Missing clock %s\n", name); 419 return PTR_ERR(clk); 420 } 421 422 mux_parent_names[i] = __clk_get_name(clk); 423 } 424 425 /* create the mux */ 426 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL); 427 if (!mux) 428 return -ENOMEM; 429 430 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev)); 431 init.name = clk_name; 432 init.ops = &clk_mux_ops; 433 init.flags = 0; 434 init.parent_names = mux_parent_names; 435 init.num_parents = MUX_CLK_NUM_PARENTS; 436 437 mux->reg = host->regs + SD_EMMC_CLOCK; 438 mux->shift = __ffs(CLK_SRC_MASK); 439 mux->mask = CLK_SRC_MASK >> mux->shift; 440 mux->hw.init = &init; 441 442 host->mux_clk = devm_clk_register(host->dev, &mux->hw); 443 if (WARN_ON(IS_ERR(host->mux_clk))) 444 return PTR_ERR(host->mux_clk); 445 446 /* create the divider */ 447 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); 448 if (!div) 449 return -ENOMEM; 450 451 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev)); 452 init.name = clk_name; 453 init.ops = &clk_divider_ops; 454 init.flags = CLK_SET_RATE_PARENT; 455 clk_parent[0] = __clk_get_name(host->mux_clk); 456 init.parent_names = clk_parent; 457 init.num_parents = 1; 458 459 div->reg = host->regs + SD_EMMC_CLOCK; 460 div->shift = __ffs(CLK_DIV_MASK); 461 div->width = __builtin_popcountl(CLK_DIV_MASK); 462 div->hw.init = &init; 463 div->flags = CLK_DIVIDER_ONE_BASED; 464 465 host->mmc_clk = devm_clk_register(host->dev, &div->hw); 466 if (WARN_ON(IS_ERR(host->mmc_clk))) 467 return PTR_ERR(host->mmc_clk); 468 469 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ 470 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); 471 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); 472 if (ret) 473 return ret; 474 475 return clk_prepare_enable(host->mmc_clk); 476 } 477 478 static void meson_mmc_disable_resampling(struct meson_host *host) 479 { 480 unsigned int val = readl(host->regs + host->data->adjust); 481 482 val &= ~ADJUST_ADJ_EN; 483 writel(val, host->regs + host->data->adjust); 484 } 485 486 static void meson_mmc_reset_resampling(struct meson_host *host) 487 { 488 unsigned int val; 489 490 meson_mmc_disable_resampling(host); 491 492 val = readl(host->regs + host->data->adjust); 493 val &= ~ADJUST_ADJ_DELAY_MASK; 494 writel(val, host->regs + host->data->adjust); 495 } 496 497 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) 498 { 499 struct meson_host *host = mmc_priv(mmc); 500 unsigned int val, dly, max_dly, i; 501 int ret; 502 503 /* Resampling is done using the source clock */ 504 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), 505 clk_get_rate(host->mmc_clk)); 506 507 val = readl(host->regs + host->data->adjust); 508 val |= ADJUST_ADJ_EN; 509 writel(val, host->regs + host->data->adjust); 510 511 if (mmc->doing_retune) 512 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; 513 else 514 dly = 0; 515 516 for (i = 0; i < max_dly; i++) { 517 val &= ~ADJUST_ADJ_DELAY_MASK; 518 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); 519 writel(val, host->regs + host->data->adjust); 520 521 ret = mmc_send_tuning(mmc, opcode, NULL); 522 if (!ret) { 523 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", 524 (dly + i) % max_dly); 525 return 0; 526 } 527 } 528 529 meson_mmc_reset_resampling(host); 530 return -EIO; 531 } 532 533 static int meson_mmc_prepare_ios_clock(struct meson_host *host, 534 struct mmc_ios *ios) 535 { 536 bool ddr; 537 538 switch (ios->timing) { 539 case MMC_TIMING_MMC_DDR52: 540 case MMC_TIMING_UHS_DDR50: 541 ddr = true; 542 break; 543 544 default: 545 ddr = false; 546 break; 547 } 548 549 return meson_mmc_clk_set(host, ios->clock, ddr); 550 } 551 552 static void meson_mmc_check_resampling(struct meson_host *host, 553 struct mmc_ios *ios) 554 { 555 switch (ios->timing) { 556 case MMC_TIMING_LEGACY: 557 case MMC_TIMING_MMC_HS: 558 case MMC_TIMING_SD_HS: 559 case MMC_TIMING_MMC_DDR52: 560 meson_mmc_disable_resampling(host); 561 break; 562 } 563 } 564 565 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 566 { 567 struct meson_host *host = mmc_priv(mmc); 568 u32 bus_width, val; 569 int err; 570 571 /* 572 * GPIO regulator, only controls switching between 1v8 and 573 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON. 574 */ 575 switch (ios->power_mode) { 576 case MMC_POWER_OFF: 577 if (!IS_ERR(mmc->supply.vmmc)) 578 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 579 580 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 581 regulator_disable(mmc->supply.vqmmc); 582 host->vqmmc_enabled = false; 583 } 584 585 break; 586 587 case MMC_POWER_UP: 588 if (!IS_ERR(mmc->supply.vmmc)) 589 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 590 591 break; 592 593 case MMC_POWER_ON: 594 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 595 int ret = regulator_enable(mmc->supply.vqmmc); 596 597 if (ret < 0) 598 dev_err(host->dev, 599 "failed to enable vqmmc regulator\n"); 600 else 601 host->vqmmc_enabled = true; 602 } 603 604 break; 605 } 606 607 /* Bus width */ 608 switch (ios->bus_width) { 609 case MMC_BUS_WIDTH_1: 610 bus_width = CFG_BUS_WIDTH_1; 611 break; 612 case MMC_BUS_WIDTH_4: 613 bus_width = CFG_BUS_WIDTH_4; 614 break; 615 case MMC_BUS_WIDTH_8: 616 bus_width = CFG_BUS_WIDTH_8; 617 break; 618 default: 619 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n", 620 ios->bus_width); 621 bus_width = CFG_BUS_WIDTH_4; 622 } 623 624 val = readl(host->regs + SD_EMMC_CFG); 625 val &= ~CFG_BUS_WIDTH_MASK; 626 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); 627 writel(val, host->regs + SD_EMMC_CFG); 628 629 meson_mmc_check_resampling(host, ios); 630 err = meson_mmc_prepare_ios_clock(host, ios); 631 if (err) 632 dev_err(host->dev, "Failed to set clock: %d\n,", err); 633 634 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); 635 } 636 637 static void meson_mmc_request_done(struct mmc_host *mmc, 638 struct mmc_request *mrq) 639 { 640 struct meson_host *host = mmc_priv(mmc); 641 642 host->cmd = NULL; 643 mmc_request_done(host->mmc, mrq); 644 } 645 646 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz) 647 { 648 struct meson_host *host = mmc_priv(mmc); 649 u32 cfg, blksz_old; 650 651 cfg = readl(host->regs + SD_EMMC_CFG); 652 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg); 653 654 if (!is_power_of_2(blksz)) 655 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz); 656 657 blksz = ilog2(blksz); 658 659 /* check if block-size matches, if not update */ 660 if (blksz == blksz_old) 661 return; 662 663 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__, 664 blksz_old, blksz); 665 666 cfg &= ~CFG_BLK_LEN_MASK; 667 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz); 668 writel(cfg, host->regs + SD_EMMC_CFG); 669 } 670 671 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg) 672 { 673 if (cmd->flags & MMC_RSP_PRESENT) { 674 if (cmd->flags & MMC_RSP_136) 675 *cmd_cfg |= CMD_CFG_RESP_128; 676 *cmd_cfg |= CMD_CFG_RESP_NUM; 677 678 if (!(cmd->flags & MMC_RSP_CRC)) 679 *cmd_cfg |= CMD_CFG_RESP_NOCRC; 680 681 if (cmd->flags & MMC_RSP_BUSY) 682 *cmd_cfg |= CMD_CFG_R1B; 683 } else { 684 *cmd_cfg |= CMD_CFG_NO_RESP; 685 } 686 } 687 688 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg) 689 { 690 struct meson_host *host = mmc_priv(mmc); 691 struct sd_emmc_desc *desc = host->descs; 692 struct mmc_data *data = host->cmd->data; 693 struct scatterlist *sg; 694 u32 start; 695 int i; 696 697 if (data->flags & MMC_DATA_WRITE) 698 cmd_cfg |= CMD_CFG_DATA_WR; 699 700 if (data->blocks > 1) { 701 cmd_cfg |= CMD_CFG_BLOCK_MODE; 702 meson_mmc_set_blksz(mmc, data->blksz); 703 } 704 705 for_each_sg(data->sg, sg, data->sg_count, i) { 706 unsigned int len = sg_dma_len(sg); 707 708 if (data->blocks > 1) 709 len /= data->blksz; 710 711 desc[i].cmd_cfg = cmd_cfg; 712 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len); 713 if (i > 0) 714 desc[i].cmd_cfg |= CMD_CFG_NO_CMD; 715 desc[i].cmd_arg = host->cmd->arg; 716 desc[i].cmd_resp = 0; 717 desc[i].cmd_data = sg_dma_address(sg); 718 } 719 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN; 720 721 dma_wmb(); /* ensure descriptor is written before kicked */ 722 start = host->descs_dma_addr | START_DESC_BUSY; 723 writel(start, host->regs + SD_EMMC_START); 724 } 725 726 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) 727 { 728 struct meson_host *host = mmc_priv(mmc); 729 struct mmc_data *data = cmd->data; 730 u32 cmd_cfg = 0, cmd_data = 0; 731 unsigned int xfer_bytes = 0; 732 733 /* Setup descriptors */ 734 dma_rmb(); 735 736 host->cmd = cmd; 737 738 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); 739 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ 740 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ 741 742 meson_mmc_set_response_bits(cmd, &cmd_cfg); 743 744 /* data? */ 745 if (data) { 746 data->bytes_xfered = 0; 747 cmd_cfg |= CMD_CFG_DATA_IO; 748 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 749 ilog2(meson_mmc_get_timeout_msecs(data))); 750 751 if (meson_mmc_desc_chain_mode(data)) { 752 meson_mmc_desc_chain_transfer(mmc, cmd_cfg); 753 return; 754 } 755 756 if (data->blocks > 1) { 757 cmd_cfg |= CMD_CFG_BLOCK_MODE; 758 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, 759 data->blocks); 760 meson_mmc_set_blksz(mmc, data->blksz); 761 } else { 762 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz); 763 } 764 765 xfer_bytes = data->blksz * data->blocks; 766 if (data->flags & MMC_DATA_WRITE) { 767 cmd_cfg |= CMD_CFG_DATA_WR; 768 WARN_ON(xfer_bytes > host->bounce_buf_size); 769 sg_copy_to_buffer(data->sg, data->sg_len, 770 host->bounce_buf, xfer_bytes); 771 dma_wmb(); 772 } 773 774 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK; 775 } else { 776 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK, 777 ilog2(SD_EMMC_CMD_TIMEOUT)); 778 } 779 780 /* Last descriptor */ 781 cmd_cfg |= CMD_CFG_END_OF_CHAIN; 782 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG); 783 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT); 784 writel(0, host->regs + SD_EMMC_CMD_RSP); 785 wmb(); /* ensure descriptor is written before kicked */ 786 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG); 787 } 788 789 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 790 { 791 struct meson_host *host = mmc_priv(mmc); 792 bool needs_pre_post_req = mrq->data && 793 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE); 794 795 if (needs_pre_post_req) { 796 meson_mmc_get_transfer_mode(mmc, mrq); 797 if (!meson_mmc_desc_chain_mode(mrq->data)) 798 needs_pre_post_req = false; 799 } 800 801 if (needs_pre_post_req) 802 meson_mmc_pre_req(mmc, mrq); 803 804 /* Stop execution */ 805 writel(0, host->regs + SD_EMMC_START); 806 807 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd); 808 809 if (needs_pre_post_req) 810 meson_mmc_post_req(mmc, mrq, 0); 811 } 812 813 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd) 814 { 815 struct meson_host *host = mmc_priv(mmc); 816 817 if (cmd->flags & MMC_RSP_136) { 818 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3); 819 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2); 820 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1); 821 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP); 822 } else if (cmd->flags & MMC_RSP_PRESENT) { 823 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP); 824 } 825 } 826 827 static irqreturn_t meson_mmc_irq(int irq, void *dev_id) 828 { 829 struct meson_host *host = dev_id; 830 struct mmc_command *cmd; 831 struct mmc_data *data; 832 u32 irq_en, status, raw_status; 833 irqreturn_t ret = IRQ_NONE; 834 835 irq_en = readl(host->regs + SD_EMMC_IRQ_EN); 836 raw_status = readl(host->regs + SD_EMMC_STATUS); 837 status = raw_status & irq_en; 838 839 if (!status) { 840 dev_dbg(host->dev, 841 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n", 842 irq_en, raw_status); 843 return IRQ_NONE; 844 } 845 846 if (WARN_ON(!host) || WARN_ON(!host->cmd)) 847 return IRQ_NONE; 848 849 /* ack all raised interrupts */ 850 writel(status, host->regs + SD_EMMC_STATUS); 851 852 cmd = host->cmd; 853 data = cmd->data; 854 cmd->error = 0; 855 if (status & IRQ_CRC_ERR) { 856 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status); 857 cmd->error = -EILSEQ; 858 ret = IRQ_WAKE_THREAD; 859 goto out; 860 } 861 862 if (status & IRQ_TIMEOUTS) { 863 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status); 864 cmd->error = -ETIMEDOUT; 865 ret = IRQ_WAKE_THREAD; 866 goto out; 867 } 868 869 meson_mmc_read_resp(host->mmc, cmd); 870 871 if (status & IRQ_SDIO) { 872 dev_dbg(host->dev, "IRQ: SDIO TODO.\n"); 873 ret = IRQ_HANDLED; 874 } 875 876 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { 877 if (data && !cmd->error) 878 data->bytes_xfered = data->blksz * data->blocks; 879 if (meson_mmc_bounce_buf_read(data) || 880 meson_mmc_get_next_command(cmd)) 881 ret = IRQ_WAKE_THREAD; 882 else 883 ret = IRQ_HANDLED; 884 } 885 886 out: 887 if (cmd->error) { 888 /* Stop desc in case of errors */ 889 u32 start = readl(host->regs + SD_EMMC_START); 890 891 start &= ~START_DESC_BUSY; 892 writel(start, host->regs + SD_EMMC_START); 893 } 894 895 if (ret == IRQ_HANDLED) 896 meson_mmc_request_done(host->mmc, cmd->mrq); 897 898 return ret; 899 } 900 901 static int meson_mmc_wait_desc_stop(struct meson_host *host) 902 { 903 u32 status; 904 905 /* 906 * It may sometimes take a while for it to actually halt. Here, we 907 * are giving it 5ms to comply 908 * 909 * If we don't confirm the descriptor is stopped, it might raise new 910 * IRQs after we have called mmc_request_done() which is bad. 911 */ 912 913 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, 914 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), 915 100, 5000); 916 } 917 918 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) 919 { 920 struct meson_host *host = dev_id; 921 struct mmc_command *next_cmd, *cmd = host->cmd; 922 struct mmc_data *data; 923 unsigned int xfer_bytes; 924 925 if (WARN_ON(!cmd)) 926 return IRQ_NONE; 927 928 if (cmd->error) { 929 meson_mmc_wait_desc_stop(host); 930 meson_mmc_request_done(host->mmc, cmd->mrq); 931 932 return IRQ_HANDLED; 933 } 934 935 data = cmd->data; 936 if (meson_mmc_bounce_buf_read(data)) { 937 xfer_bytes = data->blksz * data->blocks; 938 WARN_ON(xfer_bytes > host->bounce_buf_size); 939 sg_copy_from_buffer(data->sg, data->sg_len, 940 host->bounce_buf, xfer_bytes); 941 } 942 943 next_cmd = meson_mmc_get_next_command(cmd); 944 if (next_cmd) 945 meson_mmc_start_cmd(host->mmc, next_cmd); 946 else 947 meson_mmc_request_done(host->mmc, cmd->mrq); 948 949 return IRQ_HANDLED; 950 } 951 952 /* 953 * NOTE: we only need this until the GPIO/pinctrl driver can handle 954 * interrupts. For now, the MMC core will use this for polling. 955 */ 956 static int meson_mmc_get_cd(struct mmc_host *mmc) 957 { 958 int status = mmc_gpio_get_cd(mmc); 959 960 if (status == -ENOSYS) 961 return 1; /* assume present */ 962 963 return status; 964 } 965 966 static void meson_mmc_cfg_init(struct meson_host *host) 967 { 968 u32 cfg = 0; 969 970 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK, 971 ilog2(SD_EMMC_CFG_RESP_TIMEOUT)); 972 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP)); 973 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE)); 974 975 /* abort chain on R/W errors */ 976 cfg |= CFG_ERR_ABORT; 977 978 writel(cfg, host->regs + SD_EMMC_CFG); 979 } 980 981 static int meson_mmc_card_busy(struct mmc_host *mmc) 982 { 983 struct meson_host *host = mmc_priv(mmc); 984 u32 regval; 985 986 regval = readl(host->regs + SD_EMMC_STATUS); 987 988 /* We are only interrested in lines 0 to 3, so mask the other ones */ 989 return !(FIELD_GET(STATUS_DATI, regval) & 0xf); 990 } 991 992 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 993 { 994 /* vqmmc regulator is available */ 995 if (!IS_ERR(mmc->supply.vqmmc)) { 996 /* 997 * The usual amlogic setup uses a GPIO to switch from one 998 * regulator to the other. While the voltage ramp up is 999 * pretty fast, care must be taken when switching from 3.3v 1000 * to 1.8v. Please make sure the regulator framework is aware 1001 * of your own regulator constraints 1002 */ 1003 return mmc_regulator_set_vqmmc(mmc, ios); 1004 } 1005 1006 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 1007 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1008 return 0; 1009 1010 return -EINVAL; 1011 } 1012 1013 static const struct mmc_host_ops meson_mmc_ops = { 1014 .request = meson_mmc_request, 1015 .set_ios = meson_mmc_set_ios, 1016 .get_cd = meson_mmc_get_cd, 1017 .pre_req = meson_mmc_pre_req, 1018 .post_req = meson_mmc_post_req, 1019 .execute_tuning = meson_mmc_resampling_tuning, 1020 .card_busy = meson_mmc_card_busy, 1021 .start_signal_voltage_switch = meson_mmc_voltage_switch, 1022 }; 1023 1024 static int meson_mmc_probe(struct platform_device *pdev) 1025 { 1026 struct resource *res; 1027 struct meson_host *host; 1028 struct mmc_host *mmc; 1029 int ret; 1030 1031 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev); 1032 if (!mmc) 1033 return -ENOMEM; 1034 host = mmc_priv(mmc); 1035 host->mmc = mmc; 1036 host->dev = &pdev->dev; 1037 dev_set_drvdata(&pdev->dev, host); 1038 1039 /* Get regulators and the supported OCR mask */ 1040 host->vqmmc_enabled = false; 1041 ret = mmc_regulator_get_supply(mmc); 1042 if (ret) 1043 goto free_host; 1044 1045 ret = mmc_of_parse(mmc); 1046 if (ret) { 1047 if (ret != -EPROBE_DEFER) 1048 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret); 1049 goto free_host; 1050 } 1051 1052 host->data = (struct meson_mmc_data *) 1053 of_device_get_match_data(&pdev->dev); 1054 if (!host->data) { 1055 ret = -EINVAL; 1056 goto free_host; 1057 } 1058 1059 ret = device_reset_optional(&pdev->dev); 1060 if (ret) { 1061 if (ret != -EPROBE_DEFER) 1062 dev_err(&pdev->dev, "device reset failed: %d\n", ret); 1063 1064 return ret; 1065 } 1066 1067 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1068 host->regs = devm_ioremap_resource(&pdev->dev, res); 1069 if (IS_ERR(host->regs)) { 1070 ret = PTR_ERR(host->regs); 1071 goto free_host; 1072 } 1073 1074 host->irq = platform_get_irq(pdev, 0); 1075 if (host->irq <= 0) { 1076 dev_err(&pdev->dev, "failed to get interrupt resource.\n"); 1077 ret = -EINVAL; 1078 goto free_host; 1079 } 1080 1081 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1082 if (IS_ERR(host->pinctrl)) { 1083 ret = PTR_ERR(host->pinctrl); 1084 goto free_host; 1085 } 1086 1087 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1088 PINCTRL_STATE_DEFAULT); 1089 if (IS_ERR(host->pins_default)) { 1090 ret = PTR_ERR(host->pins_default); 1091 goto free_host; 1092 } 1093 1094 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl, 1095 "clk-gate"); 1096 if (IS_ERR(host->pins_clk_gate)) { 1097 dev_warn(&pdev->dev, 1098 "can't get clk-gate pinctrl, using clk_stop bit\n"); 1099 host->pins_clk_gate = NULL; 1100 } 1101 1102 host->core_clk = devm_clk_get(&pdev->dev, "core"); 1103 if (IS_ERR(host->core_clk)) { 1104 ret = PTR_ERR(host->core_clk); 1105 goto free_host; 1106 } 1107 1108 ret = clk_prepare_enable(host->core_clk); 1109 if (ret) 1110 goto free_host; 1111 1112 ret = meson_mmc_clk_init(host); 1113 if (ret) 1114 goto err_core_clk; 1115 1116 /* set config to sane default */ 1117 meson_mmc_cfg_init(host); 1118 1119 /* Stop execution */ 1120 writel(0, host->regs + SD_EMMC_START); 1121 1122 /* clear, ack and enable interrupts */ 1123 writel(0, host->regs + SD_EMMC_IRQ_EN); 1124 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1125 host->regs + SD_EMMC_STATUS); 1126 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN, 1127 host->regs + SD_EMMC_IRQ_EN); 1128 1129 ret = request_threaded_irq(host->irq, meson_mmc_irq, 1130 meson_mmc_irq_thread, IRQF_ONESHOT, 1131 dev_name(&pdev->dev), host); 1132 if (ret) 1133 goto err_init_clk; 1134 1135 mmc->caps |= MMC_CAP_CMD23; 1136 mmc->max_blk_count = CMD_CFG_LENGTH_MASK; 1137 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size; 1138 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc); 1139 mmc->max_seg_size = mmc->max_req_size; 1140 1141 /* 1142 * At the moment, we don't know how to reliably enable HS400. 1143 * From the different datasheets, it is not even clear if this mode 1144 * is officially supported by any of the SoCs 1145 */ 1146 mmc->caps2 &= ~MMC_CAP2_HS400; 1147 1148 /* data bounce buffer */ 1149 host->bounce_buf_size = mmc->max_req_size; 1150 host->bounce_buf = 1151 dma_alloc_coherent(host->dev, host->bounce_buf_size, 1152 &host->bounce_dma_addr, GFP_KERNEL); 1153 if (host->bounce_buf == NULL) { 1154 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n"); 1155 ret = -ENOMEM; 1156 goto err_free_irq; 1157 } 1158 1159 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1160 &host->descs_dma_addr, GFP_KERNEL); 1161 if (!host->descs) { 1162 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n"); 1163 ret = -ENOMEM; 1164 goto err_bounce_buf; 1165 } 1166 1167 mmc->ops = &meson_mmc_ops; 1168 mmc_add_host(mmc); 1169 1170 return 0; 1171 1172 err_bounce_buf: 1173 dma_free_coherent(host->dev, host->bounce_buf_size, 1174 host->bounce_buf, host->bounce_dma_addr); 1175 err_free_irq: 1176 free_irq(host->irq, host); 1177 err_init_clk: 1178 clk_disable_unprepare(host->mmc_clk); 1179 err_core_clk: 1180 clk_disable_unprepare(host->core_clk); 1181 free_host: 1182 mmc_free_host(mmc); 1183 return ret; 1184 } 1185 1186 static int meson_mmc_remove(struct platform_device *pdev) 1187 { 1188 struct meson_host *host = dev_get_drvdata(&pdev->dev); 1189 1190 mmc_remove_host(host->mmc); 1191 1192 /* disable interrupts */ 1193 writel(0, host->regs + SD_EMMC_IRQ_EN); 1194 free_irq(host->irq, host); 1195 1196 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN, 1197 host->descs, host->descs_dma_addr); 1198 dma_free_coherent(host->dev, host->bounce_buf_size, 1199 host->bounce_buf, host->bounce_dma_addr); 1200 1201 clk_disable_unprepare(host->mmc_clk); 1202 clk_disable_unprepare(host->core_clk); 1203 1204 mmc_free_host(host->mmc); 1205 return 0; 1206 } 1207 1208 static const struct meson_mmc_data meson_gx_data = { 1209 .tx_delay_mask = CLK_V2_TX_DELAY_MASK, 1210 .rx_delay_mask = CLK_V2_RX_DELAY_MASK, 1211 .always_on = CLK_V2_ALWAYS_ON, 1212 .adjust = SD_EMMC_ADJUST, 1213 }; 1214 1215 static const struct meson_mmc_data meson_axg_data = { 1216 .tx_delay_mask = CLK_V3_TX_DELAY_MASK, 1217 .rx_delay_mask = CLK_V3_RX_DELAY_MASK, 1218 .always_on = CLK_V3_ALWAYS_ON, 1219 .adjust = SD_EMMC_V3_ADJUST, 1220 }; 1221 1222 static const struct of_device_id meson_mmc_of_match[] = { 1223 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data }, 1224 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data }, 1225 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data }, 1226 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data }, 1227 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data }, 1228 {} 1229 }; 1230 MODULE_DEVICE_TABLE(of, meson_mmc_of_match); 1231 1232 static struct platform_driver meson_mmc_driver = { 1233 .probe = meson_mmc_probe, 1234 .remove = meson_mmc_remove, 1235 .driver = { 1236 .name = DRIVER_NAME, 1237 .of_match_table = of_match_ptr(meson_mmc_of_match), 1238 }, 1239 }; 1240 1241 module_platform_driver(meson_mmc_driver); 1242 1243 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver"); 1244 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>"); 1245 MODULE_LICENSE("GPL v2"); 1246