1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io-64-nonatomic-hi-lo.h> 14 #include <linux/mfd/tmio.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/pagemap.h> 21 #include <linux/scatterlist.h> 22 #include <linux/sys_soc.h> 23 24 #include "renesas_sdhi.h" 25 #include "tmio_mmc.h" 26 27 #define DM_CM_DTRAN_MODE 0x820 28 #define DM_CM_DTRAN_CTRL 0x828 29 #define DM_CM_RST 0x830 30 #define DM_CM_INFO1 0x840 31 #define DM_CM_INFO1_MASK 0x848 32 #define DM_CM_INFO2 0x850 33 #define DM_CM_INFO2_MASK 0x858 34 #define DM_DTRAN_ADDR 0x880 35 36 /* DM_CM_DTRAN_MODE */ 37 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 38 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 39 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 40 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 41 42 /* DM_CM_DTRAN_CTRL */ 43 #define DTRAN_CTRL_DM_START BIT(0) 44 45 /* DM_CM_RST */ 46 #define RST_DTRANRST1 BIT(9) 47 #define RST_DTRANRST0 BIT(8) 48 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 49 50 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 51 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 52 #define INFO1_DTRANEND1 BIT(20) 53 #define INFO1_DTRANEND1_OLD BIT(17) 54 #define INFO1_DTRANEND0 BIT(16) 55 56 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 57 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 58 #define INFO2_DTRANERR1 BIT(17) 59 #define INFO2_DTRANERR0 BIT(16) 60 61 enum renesas_sdhi_dma_cookie { 62 COOKIE_UNMAPPED, 63 COOKIE_PRE_MAPPED, 64 COOKIE_MAPPED, 65 }; 66 67 /* 68 * Specification of this driver: 69 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 70 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 71 * need a custom accessor. 72 */ 73 74 static unsigned long global_flags; 75 /* 76 * Workaround for avoiding to use RX DMAC by multiple channels. On R-Car M3-W 77 * ES1.0, when multiple SDHI channels use RX DMAC simultaneously, sometimes 78 * hundreds of data bytes are not stored into the system memory even if the 79 * DMAC interrupt happened. So, this driver then uses one RX DMAC channel only. 80 */ 81 #define SDHI_INTERNAL_DMAC_RX_IN_USE 0 82 83 /* Definitions for sampling clocks */ 84 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 85 { 86 .clk_rate = 0, 87 .tap = 0x00000300, 88 .tap_hs400_4tap = 0x00000100, 89 }, 90 }; 91 92 static const struct renesas_sdhi_of_data of_data_rza2 = { 93 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 94 TMIO_MMC_HAVE_CBSY, 95 .tmio_ocr_mask = MMC_VDD_32_33, 96 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 97 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 98 .bus_shift = 2, 99 .scc_offset = 0 - 0x1000, 100 .taps = rcar_gen3_scc_taps, 101 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 102 /* DMAC can handle 32bit blk count but only 1 segment */ 103 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 104 .max_segs = 1, 105 }; 106 107 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = { 108 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 109 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 110 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 111 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 112 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 113 .bus_shift = 2, 114 .scc_offset = 0x1000, 115 .taps = rcar_gen3_scc_taps, 116 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 117 /* DMAC can handle 32bit blk count but only 1 segment */ 118 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 119 .max_segs = 1, 120 .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK, 121 }; 122 123 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = { 124 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 125 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 126 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 127 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 128 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 129 .bus_shift = 2, 130 .scc_offset = 0x1000, 131 .taps = rcar_gen3_scc_taps, 132 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 133 /* DMAC can handle 32bit blk count but only 1 segment */ 134 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 135 .max_segs = 1, 136 }; 137 138 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 139 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 140 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 141 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 142 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 143 }; 144 145 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 146 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 147 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 148 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 149 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 150 }; 151 152 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 153 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 155 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 156 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 157 }; 158 159 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 160 .hs400_disabled = true, 161 .hs400_4taps = true, 162 }; 163 164 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = { 165 .hs400_disabled = true, 166 .hs400_4taps = true, 167 .dma_one_rx_only = true, 168 .old_info1_layout = true, 169 }; 170 171 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 172 .hs400_4taps = true, 173 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 174 .manual_tap_correction = true, 175 }; 176 177 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 178 .hs400_disabled = true, 179 }; 180 181 static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = { 182 .fixed_addr_mode = true, 183 }; 184 185 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 186 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 187 .manual_tap_correction = true, 188 }; 189 190 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 191 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 192 .manual_tap_correction = true, 193 }; 194 195 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 196 .hs400_4taps = true, 197 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 198 .hs400_calib_table = r8a7796_es13_calib_table, 199 .manual_tap_correction = true, 200 }; 201 202 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 203 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 204 .hs400_calib_table = r8a77965_calib_table, 205 .manual_tap_correction = true, 206 }; 207 208 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 209 .hs400_calib_table = r8a77990_calib_table, 210 .manual_tap_correction = true, 211 }; 212 213 static const struct renesas_sdhi_quirks sdhi_quirks_r9a09g011 = { 214 .fixed_addr_mode = true, 215 .hs400_disabled = true, 216 }; 217 218 /* 219 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 220 * So, we want to treat them equally and only have a match for ES1.2 to enforce 221 * this if there ever will be a way to distinguish ES1.2. 222 */ 223 static const struct soc_device_attribute sdhi_quirks_match[] = { 224 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 225 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 226 { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_one_rx }, 227 { .soc_id = "r8a7796", .revision = "ES1.[12]", .data = &sdhi_quirks_4tap_nohs400 }, 228 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 229 { .soc_id = "r8a77980", .revision = "ES1.*", .data = &sdhi_quirks_nohs400 }, 230 { /* Sentinel. */ } 231 }; 232 233 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = { 234 .of_data = &of_data_rcar_gen3, 235 .quirks = &sdhi_quirks_bad_taps2367, 236 }; 237 238 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = { 239 .of_data = &of_data_rcar_gen3, 240 .quirks = &sdhi_quirks_bad_taps1357, 241 }; 242 243 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = { 244 .of_data = &of_data_rcar_gen3, 245 .quirks = &sdhi_quirks_r8a77965, 246 }; 247 248 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = { 249 .of_data = &of_data_rcar_gen3_no_sdh_fallback, 250 .quirks = &sdhi_quirks_nohs400, 251 }; 252 253 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = { 254 .of_data = &of_data_rcar_gen3, 255 .quirks = &sdhi_quirks_r8a77990, 256 }; 257 258 static const struct renesas_sdhi_of_data_with_quirks of_r9a09g011_compatible = { 259 .of_data = &of_data_rcar_gen3, 260 .quirks = &sdhi_quirks_r9a09g011, 261 }; 262 263 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { 264 .of_data = &of_data_rcar_gen3, 265 }; 266 267 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = { 268 .of_data = &of_data_rcar_gen3, 269 .quirks = &sdhi_quirks_nohs400, 270 }; 271 272 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = { 273 .of_data = &of_data_rza2, 274 .quirks = &sdhi_quirks_fixed_addr, 275 }; 276 277 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 278 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 279 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 280 { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, }, 281 { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, }, 282 { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, }, 283 { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, 284 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 285 { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, 286 { .compatible = "renesas,sdhi-r9a09g011", .data = &of_r9a09g011_compatible, }, 287 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 288 { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, }, 289 {}, 290 }; 291 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 292 293 static void 294 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 295 { 296 struct renesas_sdhi *priv = host_to_priv(host); 297 u32 dma_irqs = INFO1_DTRANEND0 | 298 (sdhi_has_quirk(priv, old_info1_layout) ? 299 INFO1_DTRANEND1_OLD : INFO1_DTRANEND1); 300 301 if (!host->chan_tx || !host->chan_rx) 302 return; 303 304 writel(enable ? ~dma_irqs : INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK); 305 306 if (priv->dma_priv.enable) 307 priv->dma_priv.enable(host, enable); 308 } 309 310 static void 311 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) 312 { 313 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 314 315 renesas_sdhi_internal_dmac_enable_dma(host, false); 316 317 writel(RST_RESERVED_BITS & ~val, host->ctl + DM_CM_RST); 318 writel(RST_RESERVED_BITS | val, host->ctl + DM_CM_RST); 319 320 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 321 322 renesas_sdhi_internal_dmac_enable_dma(host, true); 323 } 324 325 static bool renesas_sdhi_internal_dmac_dma_irq(struct tmio_mmc_host *host) 326 { 327 struct renesas_sdhi *priv = host_to_priv(host); 328 struct renesas_sdhi_dma *dma_priv = &priv->dma_priv; 329 330 u32 dma_irqs = INFO1_DTRANEND0 | 331 (sdhi_has_quirk(priv, old_info1_layout) ? 332 INFO1_DTRANEND1_OLD : INFO1_DTRANEND1); 333 u32 status = readl(host->ctl + DM_CM_INFO1); 334 335 if (status & dma_irqs) { 336 writel(status ^ dma_irqs, host->ctl + DM_CM_INFO1); 337 set_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags); 338 if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags)) 339 tasklet_schedule(&dma_priv->dma_complete); 340 } 341 342 return status & dma_irqs; 343 } 344 345 static void 346 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) 347 { 348 struct renesas_sdhi *priv = host_to_priv(host); 349 struct renesas_sdhi_dma *dma_priv = &priv->dma_priv; 350 351 set_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags); 352 if (test_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags) || 353 host->data->error) 354 tasklet_schedule(&dma_priv->dma_complete); 355 } 356 357 /* 358 * renesas_sdhi_internal_dmac_map() will be called with two different 359 * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single 360 * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg 361 * pointer in a mmc_data instead of host->sg_ptr. 362 */ 363 static void 364 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host, 365 struct mmc_data *data, 366 enum renesas_sdhi_dma_cookie cookie) 367 { 368 bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) : 369 (data->host_cookie == cookie); 370 371 if (unmap) { 372 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 373 mmc_get_dma_dir(data)); 374 data->host_cookie = COOKIE_UNMAPPED; 375 } 376 } 377 378 static bool 379 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host, 380 struct mmc_data *data, 381 enum renesas_sdhi_dma_cookie cookie) 382 { 383 if (data->host_cookie == COOKIE_PRE_MAPPED) 384 return true; 385 386 if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 387 mmc_get_dma_dir(data))) 388 return false; 389 390 data->host_cookie = cookie; 391 392 /* This DMAC needs buffers to be 128-byte aligned */ 393 if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) { 394 renesas_sdhi_internal_dmac_unmap(host, data, cookie); 395 return false; 396 } 397 398 return true; 399 } 400 401 static void 402 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 403 struct mmc_data *data) 404 { 405 struct renesas_sdhi *priv = host_to_priv(host); 406 struct scatterlist *sg = host->sg_ptr; 407 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 408 409 if (!sdhi_has_quirk(priv, fixed_addr_mode)) 410 dtran_mode |= DTRAN_MODE_ADDR_MODE; 411 412 if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED)) 413 goto force_pio; 414 415 if (data->flags & MMC_DATA_READ) { 416 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 417 if (sdhi_has_quirk(priv, dma_one_rx_only) && 418 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 419 goto force_pio_with_unmap; 420 } else { 421 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 422 } 423 424 priv->dma_priv.end_flags = 0; 425 renesas_sdhi_internal_dmac_enable_dma(host, true); 426 427 /* set dma parameters */ 428 writel(dtran_mode, host->ctl + DM_CM_DTRAN_MODE); 429 writel(sg_dma_address(sg), host->ctl + DM_DTRAN_ADDR); 430 431 host->dma_on = true; 432 433 return; 434 435 force_pio_with_unmap: 436 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 437 438 force_pio: 439 renesas_sdhi_internal_dmac_enable_dma(host, false); 440 } 441 442 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 443 { 444 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 445 struct renesas_sdhi *priv = host_to_priv(host); 446 447 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 448 449 if (!host->cmd->error) { 450 /* start the DMAC */ 451 writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL); 452 } else { 453 /* on CMD errors, simulate DMA end immediately */ 454 set_bit(SDHI_DMA_END_FLAG_DMA, &priv->dma_priv.end_flags); 455 if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &priv->dma_priv.end_flags)) 456 tasklet_schedule(&priv->dma_priv.dma_complete); 457 } 458 } 459 460 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) 461 { 462 enum dma_data_direction dir; 463 464 if (!host->dma_on) 465 return false; 466 467 if (!host->data) 468 return false; 469 470 if (host->data->flags & MMC_DATA_READ) 471 dir = DMA_FROM_DEVICE; 472 else 473 dir = DMA_TO_DEVICE; 474 475 renesas_sdhi_internal_dmac_enable_dma(host, false); 476 renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED); 477 478 if (dir == DMA_FROM_DEVICE) 479 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 480 481 host->dma_on = false; 482 483 return true; 484 } 485 486 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 487 { 488 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 489 490 spin_lock_irq(&host->lock); 491 if (!renesas_sdhi_internal_dmac_complete(host)) 492 goto out; 493 494 tmio_mmc_do_data_irq(host); 495 out: 496 spin_unlock_irq(&host->lock); 497 } 498 499 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host) 500 { 501 if (host->data) 502 renesas_sdhi_internal_dmac_complete(host); 503 } 504 505 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc, 506 struct mmc_request *mrq, 507 int err) 508 { 509 struct tmio_mmc_host *host = mmc_priv(mmc); 510 struct mmc_data *data = mrq->data; 511 512 if (!data) 513 return; 514 515 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 516 } 517 518 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc, 519 struct mmc_request *mrq) 520 { 521 struct tmio_mmc_host *host = mmc_priv(mmc); 522 struct mmc_data *data = mrq->data; 523 524 if (!data) 525 return; 526 527 data->host_cookie = COOKIE_UNMAPPED; 528 renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED); 529 } 530 531 static void 532 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 533 struct tmio_mmc_data *pdata) 534 { 535 struct renesas_sdhi *priv = host_to_priv(host); 536 537 /* Disable DMAC interrupts initially */ 538 writel(INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK); 539 writel(INFO2_MASK_CLEAR, host->ctl + DM_CM_INFO2_MASK); 540 writel(0, host->ctl + DM_CM_INFO1); 541 writel(0, host->ctl + DM_CM_INFO2); 542 543 /* Each value is set to non-zero to assume "enabling" each DMA */ 544 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 545 546 tasklet_init(&priv->dma_priv.dma_complete, 547 renesas_sdhi_internal_dmac_complete_tasklet_fn, 548 (unsigned long)host); 549 tasklet_init(&host->dma_issue, 550 renesas_sdhi_internal_dmac_issue_tasklet_fn, 551 (unsigned long)host); 552 553 /* Add pre_req and post_req */ 554 host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req; 555 host->ops.post_req = renesas_sdhi_internal_dmac_post_req; 556 } 557 558 static void 559 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 560 { 561 /* Each value is set to zero to assume "disabling" each DMA */ 562 host->chan_rx = host->chan_tx = NULL; 563 } 564 565 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 566 .start = renesas_sdhi_internal_dmac_start_dma, 567 .enable = renesas_sdhi_internal_dmac_enable_dma, 568 .request = renesas_sdhi_internal_dmac_request_dma, 569 .release = renesas_sdhi_internal_dmac_release_dma, 570 .abort = renesas_sdhi_internal_dmac_abort_dma, 571 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 572 .end = renesas_sdhi_internal_dmac_end_dma, 573 .dma_irq = renesas_sdhi_internal_dmac_dma_irq, 574 }; 575 576 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 577 { 578 const struct soc_device_attribute *attr; 579 const struct renesas_sdhi_of_data_with_quirks *of_data_quirks; 580 const struct renesas_sdhi_quirks *quirks; 581 struct device *dev = &pdev->dev; 582 583 of_data_quirks = of_device_get_match_data(&pdev->dev); 584 quirks = of_data_quirks->quirks; 585 586 attr = soc_device_match(sdhi_quirks_match); 587 if (attr) 588 quirks = attr->data; 589 590 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 591 dma_set_max_seg_size(dev, 0xffffffff); 592 593 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops, 594 of_data_quirks->of_data, quirks); 595 } 596 597 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 598 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 599 pm_runtime_force_resume) 600 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 601 tmio_mmc_host_runtime_resume, 602 NULL) 603 }; 604 605 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 606 .driver = { 607 .name = "renesas_sdhi_internal_dmac", 608 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 609 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 610 .of_match_table = renesas_sdhi_internal_dmac_of_match, 611 }, 612 .probe = renesas_sdhi_internal_dmac_probe, 613 .remove_new = renesas_sdhi_remove, 614 }; 615 616 module_platform_driver(renesas_internal_dmac_sdhi_driver); 617 618 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 619 MODULE_AUTHOR("Yoshihiro Shimoda"); 620 MODULE_LICENSE("GPL v2"); 621