1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd 4 * Vincent Yang <vincent.yang@tw.fujitsu.com> 5 * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org> 6 * Copyright (C) 2019 Socionext Inc. 7 * Takao Orito <orito.takao@socionext.com> 8 */ 9 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/property.h> 18 19 #include "sdhci-pltfm.h" 20 #include "sdhci_f_sdh30.h" 21 22 /* milbeaut bridge controller register */ 23 #define MLB_SOFT_RESET 0x0200 24 #define MLB_SOFT_RESET_RSTX BIT(0) 25 26 #define MLB_WP_CD_LED_SET 0x0210 27 #define MLB_WP_CD_LED_SET_LED_INV BIT(2) 28 29 #define MLB_CR_SET 0x0220 30 #define MLB_CR_SET_CR_TOCLKUNIT BIT(24) 31 #define MLB_CR_SET_CR_TOCLKFREQ_SFT (16) 32 #define MLB_CR_SET_CR_TOCLKFREQ_MASK (0x3F << MLB_CR_SET_CR_TOCLKFREQ_SFT) 33 #define MLB_CR_SET_CR_BCLKFREQ_SFT (8) 34 #define MLB_CR_SET_CR_BCLKFREQ_MASK (0xFF << MLB_CR_SET_CR_BCLKFREQ_SFT) 35 #define MLB_CR_SET_CR_RTUNTIMER_SFT (4) 36 #define MLB_CR_SET_CR_RTUNTIMER_MASK (0xF << MLB_CR_SET_CR_RTUNTIMER_SFT) 37 38 #define MLB_SD_TOCLK_I_DIV 16 39 #define MLB_TOCLKFREQ_UNIT_THRES 16000000 40 #define MLB_CAL_TOCLKFREQ_MHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000000) 41 #define MLB_CAL_TOCLKFREQ_KHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000) 42 #define MLB_TOCLKFREQ_MAX 63 43 #define MLB_TOCLKFREQ_MIN 1 44 45 #define MLB_SD_BCLK_I_DIV 4 46 #define MLB_CAL_BCLKFREQ(rate) (rate / MLB_SD_BCLK_I_DIV / 1000000) 47 #define MLB_BCLKFREQ_MAX 255 48 #define MLB_BCLKFREQ_MIN 1 49 50 #define MLB_CDR_SET 0x0230 51 #define MLB_CDR_SET_CLK2POW16 3 52 53 struct f_sdhost_priv { 54 struct clk *clk_iface; 55 struct clk *clk; 56 struct device *dev; 57 bool enable_cmd_dat_delay; 58 }; 59 60 static void sdhci_milbeaut_soft_voltage_switch(struct sdhci_host *host) 61 { 62 u32 ctrl = 0; 63 64 usleep_range(2500, 3000); 65 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); 66 ctrl |= F_SDH30_CRES_O_DN; 67 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); 68 ctrl |= F_SDH30_MSEL_O_1_8; 69 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); 70 71 ctrl &= ~F_SDH30_CRES_O_DN; 72 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); 73 usleep_range(2500, 3000); 74 75 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); 76 ctrl |= F_SDH30_CMD_CHK_DIS; 77 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING); 78 } 79 80 static unsigned int sdhci_milbeaut_get_min_clock(struct sdhci_host *host) 81 { 82 return F_SDH30_MIN_CLOCK; 83 } 84 85 static void sdhci_milbeaut_reset(struct sdhci_host *host, u8 mask) 86 { 87 struct f_sdhost_priv *priv = sdhci_priv(host); 88 u16 clk; 89 u32 ctl; 90 ktime_t timeout; 91 92 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 93 clk = (clk & ~SDHCI_CLOCK_CARD_EN) | SDHCI_CLOCK_INT_EN; 94 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 95 96 sdhci_reset(host, mask); 97 98 clk |= SDHCI_CLOCK_CARD_EN; 99 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 100 101 timeout = ktime_add_ms(ktime_get(), 10); 102 while (1) { 103 bool timedout = ktime_after(ktime_get(), timeout); 104 105 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 106 if (clk & SDHCI_CLOCK_INT_STABLE) 107 break; 108 if (timedout) { 109 pr_err("%s: Internal clock never stabilised.\n", 110 mmc_hostname(host->mmc)); 111 sdhci_dumpregs(host); 112 return; 113 } 114 udelay(10); 115 } 116 117 if (priv->enable_cmd_dat_delay) { 118 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); 119 ctl |= F_SDH30_CMD_DAT_DELAY; 120 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); 121 } 122 } 123 124 static void sdhci_milbeaut_set_power(struct sdhci_host *host, 125 unsigned char mode, unsigned short vdd) 126 { 127 if (!IS_ERR(host->mmc->supply.vmmc)) { 128 struct mmc_host *mmc = host->mmc; 129 130 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 131 } 132 sdhci_set_power_noreg(host, mode, vdd); 133 } 134 135 static const struct sdhci_ops sdhci_milbeaut_ops = { 136 .voltage_switch = sdhci_milbeaut_soft_voltage_switch, 137 .get_min_clock = sdhci_milbeaut_get_min_clock, 138 .reset = sdhci_milbeaut_reset, 139 .set_clock = sdhci_set_clock, 140 .set_bus_width = sdhci_set_bus_width, 141 .set_uhs_signaling = sdhci_set_uhs_signaling, 142 .set_power = sdhci_milbeaut_set_power, 143 }; 144 145 static void sdhci_milbeaut_bridge_reset(struct sdhci_host *host, 146 int reset_flag) 147 { 148 if (reset_flag) 149 sdhci_writel(host, 0, MLB_SOFT_RESET); 150 else 151 sdhci_writel(host, MLB_SOFT_RESET_RSTX, MLB_SOFT_RESET); 152 } 153 154 static void sdhci_milbeaut_bridge_init(struct sdhci_host *host, 155 int rate) 156 { 157 u32 val, clk; 158 159 /* IO_SDIO_CR_SET should be set while reset */ 160 val = sdhci_readl(host, MLB_CR_SET); 161 val &= ~(MLB_CR_SET_CR_TOCLKFREQ_MASK | MLB_CR_SET_CR_TOCLKUNIT | 162 MLB_CR_SET_CR_BCLKFREQ_MASK); 163 if (rate >= MLB_TOCLKFREQ_UNIT_THRES) { 164 clk = MLB_CAL_TOCLKFREQ_MHZ(rate); 165 clk = min_t(u32, MLB_TOCLKFREQ_MAX, clk); 166 val |= MLB_CR_SET_CR_TOCLKUNIT | 167 (clk << MLB_CR_SET_CR_TOCLKFREQ_SFT); 168 } else { 169 clk = MLB_CAL_TOCLKFREQ_KHZ(rate); 170 clk = min_t(u32, MLB_TOCLKFREQ_MAX, clk); 171 clk = max_t(u32, MLB_TOCLKFREQ_MIN, clk); 172 val |= clk << MLB_CR_SET_CR_TOCLKFREQ_SFT; 173 } 174 175 clk = MLB_CAL_BCLKFREQ(rate); 176 clk = min_t(u32, MLB_BCLKFREQ_MAX, clk); 177 clk = max_t(u32, MLB_BCLKFREQ_MIN, clk); 178 val |= clk << MLB_CR_SET_CR_BCLKFREQ_SFT; 179 val &= ~MLB_CR_SET_CR_RTUNTIMER_MASK; 180 sdhci_writel(host, val, MLB_CR_SET); 181 182 sdhci_writel(host, MLB_CDR_SET_CLK2POW16, MLB_CDR_SET); 183 184 sdhci_writel(host, MLB_WP_CD_LED_SET_LED_INV, MLB_WP_CD_LED_SET); 185 } 186 187 static void sdhci_milbeaut_vendor_init(struct sdhci_host *host) 188 { 189 struct f_sdhost_priv *priv = sdhci_priv(host); 190 u32 ctl; 191 192 ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2); 193 ctl |= F_SDH30_CRES_O_DN; 194 sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2); 195 ctl &= ~F_SDH30_MSEL_O_1_8; 196 sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2); 197 ctl &= ~F_SDH30_CRES_O_DN; 198 sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2); 199 200 ctl = sdhci_readw(host, F_SDH30_AHB_CONFIG); 201 ctl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 | 202 F_SDH30_AHB_INCR_4; 203 ctl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN); 204 sdhci_writew(host, ctl, F_SDH30_AHB_CONFIG); 205 206 if (priv->enable_cmd_dat_delay) { 207 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); 208 ctl |= F_SDH30_CMD_DAT_DELAY; 209 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); 210 } 211 } 212 213 static const struct of_device_id mlb_dt_ids[] = { 214 { 215 .compatible = "socionext,milbeaut-m10v-sdhci-3.0", 216 }, 217 { /* sentinel */ } 218 }; 219 MODULE_DEVICE_TABLE(of, mlb_dt_ids); 220 221 static void sdhci_milbeaut_init(struct sdhci_host *host) 222 { 223 struct f_sdhost_priv *priv = sdhci_priv(host); 224 int rate = clk_get_rate(priv->clk); 225 u16 ctl; 226 227 sdhci_milbeaut_bridge_reset(host, 0); 228 229 ctl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 230 ctl &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); 231 sdhci_writew(host, ctl, SDHCI_CLOCK_CONTROL); 232 233 sdhci_milbeaut_bridge_reset(host, 1); 234 235 sdhci_milbeaut_bridge_init(host, rate); 236 sdhci_milbeaut_bridge_reset(host, 0); 237 238 sdhci_milbeaut_vendor_init(host); 239 } 240 241 static int sdhci_milbeaut_probe(struct platform_device *pdev) 242 { 243 struct sdhci_host *host; 244 struct device *dev = &pdev->dev; 245 struct resource *res; 246 int irq, ret = 0; 247 struct f_sdhost_priv *priv; 248 249 irq = platform_get_irq(pdev, 0); 250 if (irq < 0) { 251 dev_err(dev, "%s: no irq specified\n", __func__); 252 return irq; 253 } 254 255 host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv)); 256 if (IS_ERR(host)) 257 return PTR_ERR(host); 258 259 priv = sdhci_priv(host); 260 priv->dev = dev; 261 262 host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 263 SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 264 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 265 SDHCI_QUIRK_DELAY_AFTER_POWER; 266 host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE | 267 SDHCI_QUIRK2_TUNING_WORK_AROUND | 268 SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 269 270 priv->enable_cmd_dat_delay = device_property_read_bool(dev, 271 "fujitsu,cmd-dat-delay-select"); 272 273 ret = mmc_of_parse(host->mmc); 274 if (ret) 275 goto err; 276 277 platform_set_drvdata(pdev, host); 278 279 host->hw_name = "f_sdh30"; 280 host->ops = &sdhci_milbeaut_ops; 281 host->irq = irq; 282 283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 284 host->ioaddr = devm_ioremap_resource(&pdev->dev, res); 285 if (IS_ERR(host->ioaddr)) { 286 ret = PTR_ERR(host->ioaddr); 287 goto err; 288 } 289 290 if (dev_of_node(dev)) { 291 sdhci_get_of_property(pdev); 292 293 priv->clk_iface = devm_clk_get(&pdev->dev, "iface"); 294 if (IS_ERR(priv->clk_iface)) { 295 ret = PTR_ERR(priv->clk_iface); 296 goto err; 297 } 298 299 ret = clk_prepare_enable(priv->clk_iface); 300 if (ret) 301 goto err; 302 303 priv->clk = devm_clk_get(&pdev->dev, "core"); 304 if (IS_ERR(priv->clk)) { 305 ret = PTR_ERR(priv->clk); 306 goto err_clk; 307 } 308 309 ret = clk_prepare_enable(priv->clk); 310 if (ret) 311 goto err_clk; 312 } 313 314 sdhci_milbeaut_init(host); 315 316 ret = sdhci_add_host(host); 317 if (ret) 318 goto err_add_host; 319 320 return 0; 321 322 err_add_host: 323 clk_disable_unprepare(priv->clk); 324 err_clk: 325 clk_disable_unprepare(priv->clk_iface); 326 err: 327 sdhci_free_host(host); 328 return ret; 329 } 330 331 static int sdhci_milbeaut_remove(struct platform_device *pdev) 332 { 333 struct sdhci_host *host = platform_get_drvdata(pdev); 334 struct f_sdhost_priv *priv = sdhci_priv(host); 335 336 sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) == 337 0xffffffff); 338 339 clk_disable_unprepare(priv->clk_iface); 340 clk_disable_unprepare(priv->clk); 341 342 sdhci_free_host(host); 343 platform_set_drvdata(pdev, NULL); 344 345 return 0; 346 } 347 348 static struct platform_driver sdhci_milbeaut_driver = { 349 .driver = { 350 .name = "sdhci-milbeaut", 351 .of_match_table = of_match_ptr(mlb_dt_ids), 352 }, 353 .probe = sdhci_milbeaut_probe, 354 .remove = sdhci_milbeaut_remove, 355 }; 356 357 module_platform_driver(sdhci_milbeaut_driver); 358 359 MODULE_DESCRIPTION("MILBEAUT SD Card Controller driver"); 360 MODULE_AUTHOR("Takao Orito <orito.takao@socionext.com>"); 361 MODULE_LICENSE("GPL v2"); 362 MODULE_ALIAS("platform:sdhci-milbeaut"); 363