1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/mmc/sdhci-pci-data.h> 29 #include <linux/acpi.h> 30 #include <linux/dmi.h> 31 32 #ifdef CONFIG_X86 33 #include <asm/iosf_mbi.h> 34 #endif 35 36 #include "cqhci.h" 37 38 #include "sdhci.h" 39 #include "sdhci-pci.h" 40 41 static void sdhci_pci_hw_reset(struct sdhci_host *host); 42 43 #ifdef CONFIG_PM_SLEEP 44 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 45 { 46 mmc_pm_flag_t pm_flags = 0; 47 bool cap_cd_wake = false; 48 int i; 49 50 for (i = 0; i < chip->num_slots; i++) { 51 struct sdhci_pci_slot *slot = chip->slots[i]; 52 53 if (slot) { 54 pm_flags |= slot->host->mmc->pm_flags; 55 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 56 cap_cd_wake = true; 57 } 58 } 59 60 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 61 return device_wakeup_enable(&chip->pdev->dev); 62 else if (!cap_cd_wake) 63 return device_wakeup_disable(&chip->pdev->dev); 64 65 return 0; 66 } 67 68 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 69 { 70 int i, ret; 71 72 sdhci_pci_init_wakeup(chip); 73 74 for (i = 0; i < chip->num_slots; i++) { 75 struct sdhci_pci_slot *slot = chip->slots[i]; 76 struct sdhci_host *host; 77 78 if (!slot) 79 continue; 80 81 host = slot->host; 82 83 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 84 mmc_retune_needed(host->mmc); 85 86 ret = sdhci_suspend_host(host); 87 if (ret) 88 goto err_pci_suspend; 89 90 if (device_may_wakeup(&chip->pdev->dev)) 91 mmc_gpio_set_cd_wake(host->mmc, true); 92 } 93 94 return 0; 95 96 err_pci_suspend: 97 while (--i >= 0) 98 sdhci_resume_host(chip->slots[i]->host); 99 return ret; 100 } 101 102 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 103 { 104 struct sdhci_pci_slot *slot; 105 int i, ret; 106 107 for (i = 0; i < chip->num_slots; i++) { 108 slot = chip->slots[i]; 109 if (!slot) 110 continue; 111 112 ret = sdhci_resume_host(slot->host); 113 if (ret) 114 return ret; 115 116 mmc_gpio_set_cd_wake(slot->host->mmc, false); 117 } 118 119 return 0; 120 } 121 122 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 123 { 124 int ret; 125 126 ret = cqhci_suspend(chip->slots[0]->host->mmc); 127 if (ret) 128 return ret; 129 130 return sdhci_pci_suspend_host(chip); 131 } 132 133 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 134 { 135 int ret; 136 137 ret = sdhci_pci_resume_host(chip); 138 if (ret) 139 return ret; 140 141 return cqhci_resume(chip->slots[0]->host->mmc); 142 } 143 #endif 144 145 #ifdef CONFIG_PM 146 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 147 { 148 struct sdhci_pci_slot *slot; 149 struct sdhci_host *host; 150 int i, ret; 151 152 for (i = 0; i < chip->num_slots; i++) { 153 slot = chip->slots[i]; 154 if (!slot) 155 continue; 156 157 host = slot->host; 158 159 ret = sdhci_runtime_suspend_host(host); 160 if (ret) 161 goto err_pci_runtime_suspend; 162 163 if (chip->rpm_retune && 164 host->tuning_mode != SDHCI_TUNING_MODE_3) 165 mmc_retune_needed(host->mmc); 166 } 167 168 return 0; 169 170 err_pci_runtime_suspend: 171 while (--i >= 0) 172 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 173 return ret; 174 } 175 176 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 177 { 178 struct sdhci_pci_slot *slot; 179 int i, ret; 180 181 for (i = 0; i < chip->num_slots; i++) { 182 slot = chip->slots[i]; 183 if (!slot) 184 continue; 185 186 ret = sdhci_runtime_resume_host(slot->host, 0); 187 if (ret) 188 return ret; 189 } 190 191 return 0; 192 } 193 194 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 195 { 196 int ret; 197 198 ret = cqhci_suspend(chip->slots[0]->host->mmc); 199 if (ret) 200 return ret; 201 202 return sdhci_pci_runtime_suspend_host(chip); 203 } 204 205 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 206 { 207 int ret; 208 209 ret = sdhci_pci_runtime_resume_host(chip); 210 if (ret) 211 return ret; 212 213 return cqhci_resume(chip->slots[0]->host->mmc); 214 } 215 #endif 216 217 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 218 { 219 int cmd_error = 0; 220 int data_error = 0; 221 222 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 223 return intmask; 224 225 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 226 227 return 0; 228 } 229 230 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 231 { 232 sdhci_dumpregs(mmc_priv(mmc)); 233 } 234 235 /*****************************************************************************\ 236 * * 237 * Hardware specific quirk handling * 238 * * 239 \*****************************************************************************/ 240 241 static int ricoh_probe(struct sdhci_pci_chip *chip) 242 { 243 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 244 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 245 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 246 return 0; 247 } 248 249 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 250 { 251 slot->host->caps = 252 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) 253 & SDHCI_TIMEOUT_CLK_MASK) | 254 255 ((0x21 << SDHCI_CLOCK_BASE_SHIFT) 256 & SDHCI_CLOCK_BASE_MASK) | 257 258 SDHCI_TIMEOUT_CLK_UNIT | 259 SDHCI_CAN_VDD_330 | 260 SDHCI_CAN_DO_HISPD | 261 SDHCI_CAN_DO_SDMA; 262 return 0; 263 } 264 265 #ifdef CONFIG_PM_SLEEP 266 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 267 { 268 /* Apply a delay to allow controller to settle */ 269 /* Otherwise it becomes confused if card state changed 270 during suspend */ 271 msleep(500); 272 return sdhci_pci_resume_host(chip); 273 } 274 #endif 275 276 static const struct sdhci_pci_fixes sdhci_ricoh = { 277 .probe = ricoh_probe, 278 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 279 SDHCI_QUIRK_FORCE_DMA | 280 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 281 }; 282 283 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 284 .probe_slot = ricoh_mmc_probe_slot, 285 #ifdef CONFIG_PM_SLEEP 286 .resume = ricoh_mmc_resume, 287 #endif 288 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 289 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 290 SDHCI_QUIRK_NO_CARD_NO_RESET | 291 SDHCI_QUIRK_MISSING_CAPS 292 }; 293 294 static const struct sdhci_pci_fixes sdhci_ene_712 = { 295 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 296 SDHCI_QUIRK_BROKEN_DMA, 297 }; 298 299 static const struct sdhci_pci_fixes sdhci_ene_714 = { 300 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 301 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 302 SDHCI_QUIRK_BROKEN_DMA, 303 }; 304 305 static const struct sdhci_pci_fixes sdhci_cafe = { 306 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 307 SDHCI_QUIRK_NO_BUSY_IRQ | 308 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 309 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 310 }; 311 312 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 313 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 314 }; 315 316 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 317 { 318 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 319 return 0; 320 } 321 322 /* 323 * ADMA operation is disabled for Moorestown platform due to 324 * hardware bugs. 325 */ 326 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 327 { 328 /* 329 * slots number is fixed here for MRST as SDIO3/5 are never used and 330 * have hardware bugs. 331 */ 332 chip->num_slots = 1; 333 return 0; 334 } 335 336 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 337 { 338 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 339 return 0; 340 } 341 342 #ifdef CONFIG_PM 343 344 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 345 { 346 struct sdhci_pci_slot *slot = dev_id; 347 struct sdhci_host *host = slot->host; 348 349 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 350 return IRQ_HANDLED; 351 } 352 353 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 354 { 355 int err, irq, gpio = slot->cd_gpio; 356 357 slot->cd_gpio = -EINVAL; 358 slot->cd_irq = -EINVAL; 359 360 if (!gpio_is_valid(gpio)) 361 return; 362 363 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 364 if (err < 0) 365 goto out; 366 367 err = gpio_direction_input(gpio); 368 if (err < 0) 369 goto out_free; 370 371 irq = gpio_to_irq(gpio); 372 if (irq < 0) 373 goto out_free; 374 375 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 376 IRQF_TRIGGER_FALLING, "sd_cd", slot); 377 if (err) 378 goto out_free; 379 380 slot->cd_gpio = gpio; 381 slot->cd_irq = irq; 382 383 return; 384 385 out_free: 386 devm_gpio_free(&slot->chip->pdev->dev, gpio); 387 out: 388 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 389 } 390 391 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 392 { 393 if (slot->cd_irq >= 0) 394 free_irq(slot->cd_irq, slot); 395 } 396 397 #else 398 399 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 400 { 401 } 402 403 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 404 { 405 } 406 407 #endif 408 409 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 410 { 411 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 412 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 413 return 0; 414 } 415 416 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 417 { 418 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 419 return 0; 420 } 421 422 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 423 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 424 .probe_slot = mrst_hc_probe_slot, 425 }; 426 427 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 428 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 429 .probe = mrst_hc_probe, 430 }; 431 432 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 433 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 434 .allow_runtime_pm = true, 435 .own_cd_for_runtime_pm = true, 436 }; 437 438 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 440 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 441 .allow_runtime_pm = true, 442 .probe_slot = mfd_sdio_probe_slot, 443 }; 444 445 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 446 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 447 .allow_runtime_pm = true, 448 .probe_slot = mfd_emmc_probe_slot, 449 }; 450 451 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 452 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 453 .probe_slot = pch_hc_probe_slot, 454 }; 455 456 #ifdef CONFIG_X86 457 458 #define BYT_IOSF_SCCEP 0x63 459 #define BYT_IOSF_OCP_NETCTRL0 0x1078 460 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 461 462 static void byt_ocp_setting(struct pci_dev *pdev) 463 { 464 u32 val = 0; 465 466 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 467 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 468 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 469 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 470 return; 471 472 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 473 &val)) { 474 dev_err(&pdev->dev, "%s read error\n", __func__); 475 return; 476 } 477 478 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 479 return; 480 481 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 482 483 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 484 val)) { 485 dev_err(&pdev->dev, "%s write error\n", __func__); 486 return; 487 } 488 489 dev_dbg(&pdev->dev, "%s completed\n", __func__); 490 } 491 492 #else 493 494 static inline void byt_ocp_setting(struct pci_dev *pdev) 495 { 496 } 497 498 #endif 499 500 enum { 501 INTEL_DSM_FNS = 0, 502 INTEL_DSM_V18_SWITCH = 3, 503 INTEL_DSM_V33_SWITCH = 4, 504 INTEL_DSM_DRV_STRENGTH = 9, 505 INTEL_DSM_D3_RETUNE = 10, 506 }; 507 508 struct intel_host { 509 u32 dsm_fns; 510 int drv_strength; 511 bool d3_retune; 512 bool rpm_retune_ok; 513 u32 glk_rx_ctrl1; 514 u32 glk_tun_val; 515 }; 516 517 static const guid_t intel_dsm_guid = 518 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 519 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 520 521 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 522 unsigned int fn, u32 *result) 523 { 524 union acpi_object *obj; 525 int err = 0; 526 size_t len; 527 528 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 529 if (!obj) 530 return -EOPNOTSUPP; 531 532 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 533 err = -EINVAL; 534 goto out; 535 } 536 537 len = min_t(size_t, obj->buffer.length, 4); 538 539 *result = 0; 540 memcpy(result, obj->buffer.pointer, len); 541 out: 542 ACPI_FREE(obj); 543 544 return err; 545 } 546 547 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 548 unsigned int fn, u32 *result) 549 { 550 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 551 return -EOPNOTSUPP; 552 553 return __intel_dsm(intel_host, dev, fn, result); 554 } 555 556 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 557 struct mmc_host *mmc) 558 { 559 int err; 560 u32 val; 561 562 intel_host->d3_retune = true; 563 564 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 565 if (err) { 566 pr_debug("%s: DSM not supported, error %d\n", 567 mmc_hostname(mmc), err); 568 return; 569 } 570 571 pr_debug("%s: DSM function mask %#x\n", 572 mmc_hostname(mmc), intel_host->dsm_fns); 573 574 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 575 intel_host->drv_strength = err ? 0 : val; 576 577 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 578 intel_host->d3_retune = err ? true : !!val; 579 } 580 581 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 582 { 583 u8 reg; 584 585 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 586 reg |= 0x10; 587 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 588 /* For eMMC, minimum is 1us but give it 9us for good measure */ 589 udelay(9); 590 reg &= ~0x10; 591 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 592 /* For eMMC, minimum is 200us but give it 300us for good measure */ 593 usleep_range(300, 1000); 594 } 595 596 static int intel_select_drive_strength(struct mmc_card *card, 597 unsigned int max_dtr, int host_drv, 598 int card_drv, int *drv_type) 599 { 600 struct sdhci_host *host = mmc_priv(card->host); 601 struct sdhci_pci_slot *slot = sdhci_priv(host); 602 struct intel_host *intel_host = sdhci_pci_priv(slot); 603 604 return intel_host->drv_strength; 605 } 606 607 static int bxt_get_cd(struct mmc_host *mmc) 608 { 609 int gpio_cd = mmc_gpio_get_cd(mmc); 610 struct sdhci_host *host = mmc_priv(mmc); 611 unsigned long flags; 612 int ret = 0; 613 614 if (!gpio_cd) 615 return 0; 616 617 spin_lock_irqsave(&host->lock, flags); 618 619 if (host->flags & SDHCI_DEVICE_DEAD) 620 goto out; 621 622 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 623 out: 624 spin_unlock_irqrestore(&host->lock, flags); 625 626 return ret; 627 } 628 629 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 630 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 631 632 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 633 unsigned short vdd) 634 { 635 int cntr; 636 u8 reg; 637 638 sdhci_set_power(host, mode, vdd); 639 640 if (mode == MMC_POWER_OFF) 641 return; 642 643 /* 644 * Bus power might not enable after D3 -> D0 transition due to the 645 * present state not yet having propagated. Retry for up to 2ms. 646 */ 647 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 648 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 649 if (reg & SDHCI_POWER_ON) 650 break; 651 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 652 reg |= SDHCI_POWER_ON; 653 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 654 } 655 } 656 657 #define INTEL_HS400_ES_REG 0x78 658 #define INTEL_HS400_ES_BIT BIT(0) 659 660 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 661 struct mmc_ios *ios) 662 { 663 struct sdhci_host *host = mmc_priv(mmc); 664 u32 val; 665 666 val = sdhci_readl(host, INTEL_HS400_ES_REG); 667 if (ios->enhanced_strobe) 668 val |= INTEL_HS400_ES_BIT; 669 else 670 val &= ~INTEL_HS400_ES_BIT; 671 sdhci_writel(host, val, INTEL_HS400_ES_REG); 672 } 673 674 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 675 struct mmc_ios *ios) 676 { 677 struct device *dev = mmc_dev(mmc); 678 struct sdhci_host *host = mmc_priv(mmc); 679 struct sdhci_pci_slot *slot = sdhci_priv(host); 680 struct intel_host *intel_host = sdhci_pci_priv(slot); 681 unsigned int fn; 682 u32 result = 0; 683 int err; 684 685 err = sdhci_start_signal_voltage_switch(mmc, ios); 686 if (err) 687 return err; 688 689 switch (ios->signal_voltage) { 690 case MMC_SIGNAL_VOLTAGE_330: 691 fn = INTEL_DSM_V33_SWITCH; 692 break; 693 case MMC_SIGNAL_VOLTAGE_180: 694 fn = INTEL_DSM_V18_SWITCH; 695 break; 696 default: 697 return 0; 698 } 699 700 err = intel_dsm(intel_host, dev, fn, &result); 701 pr_debug("%s: %s DSM fn %u error %d result %u\n", 702 mmc_hostname(mmc), __func__, fn, err, result); 703 704 return 0; 705 } 706 707 static const struct sdhci_ops sdhci_intel_byt_ops = { 708 .set_clock = sdhci_set_clock, 709 .set_power = sdhci_intel_set_power, 710 .enable_dma = sdhci_pci_enable_dma, 711 .set_bus_width = sdhci_set_bus_width, 712 .reset = sdhci_reset, 713 .set_uhs_signaling = sdhci_set_uhs_signaling, 714 .hw_reset = sdhci_pci_hw_reset, 715 }; 716 717 static const struct sdhci_ops sdhci_intel_glk_ops = { 718 .set_clock = sdhci_set_clock, 719 .set_power = sdhci_intel_set_power, 720 .enable_dma = sdhci_pci_enable_dma, 721 .set_bus_width = sdhci_set_bus_width, 722 .reset = sdhci_reset, 723 .set_uhs_signaling = sdhci_set_uhs_signaling, 724 .hw_reset = sdhci_pci_hw_reset, 725 .irq = sdhci_cqhci_irq, 726 }; 727 728 static void byt_read_dsm(struct sdhci_pci_slot *slot) 729 { 730 struct intel_host *intel_host = sdhci_pci_priv(slot); 731 struct device *dev = &slot->chip->pdev->dev; 732 struct mmc_host *mmc = slot->host->mmc; 733 734 intel_dsm_init(intel_host, dev, mmc); 735 slot->chip->rpm_retune = intel_host->d3_retune; 736 } 737 738 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 739 { 740 int err = sdhci_execute_tuning(mmc, opcode); 741 struct sdhci_host *host = mmc_priv(mmc); 742 743 if (err) 744 return err; 745 746 /* 747 * Tuning can leave the IP in an active state (Buffer Read Enable bit 748 * set) which prevents the entry to low power states (i.e. S0i3). Data 749 * reset will clear it. 750 */ 751 sdhci_reset(host, SDHCI_RESET_DATA); 752 753 return 0; 754 } 755 756 static void byt_probe_slot(struct sdhci_pci_slot *slot) 757 { 758 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 759 struct device *dev = &slot->chip->pdev->dev; 760 struct mmc_host *mmc = slot->host->mmc; 761 762 byt_read_dsm(slot); 763 764 byt_ocp_setting(slot->chip->pdev); 765 766 ops->execute_tuning = intel_execute_tuning; 767 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 768 769 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 770 } 771 772 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 773 { 774 byt_probe_slot(slot); 775 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 776 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 777 MMC_CAP_CMD_DURING_TFR | 778 MMC_CAP_WAIT_WHILE_BUSY; 779 slot->hw_reset = sdhci_pci_int_hw_reset; 780 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 781 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 782 slot->host->mmc_host_ops.select_drive_strength = 783 intel_select_drive_strength; 784 return 0; 785 } 786 787 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 788 { 789 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 790 dmi_match(DMI_BIOS_VENDOR, "LENOVO"); 791 } 792 793 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 794 { 795 int ret = byt_emmc_probe_slot(slot); 796 797 if (!glk_broken_cqhci(slot)) 798 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 799 800 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 801 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 802 slot->host->mmc_host_ops.hs400_enhanced_strobe = 803 intel_hs400_enhanced_strobe; 804 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 805 } 806 807 return ret; 808 } 809 810 static const struct cqhci_host_ops glk_cqhci_ops = { 811 .enable = sdhci_cqe_enable, 812 .disable = sdhci_cqe_disable, 813 .dumpregs = sdhci_pci_dumpregs, 814 }; 815 816 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 817 { 818 struct device *dev = &slot->chip->pdev->dev; 819 struct sdhci_host *host = slot->host; 820 struct cqhci_host *cq_host; 821 bool dma64; 822 int ret; 823 824 ret = sdhci_setup_host(host); 825 if (ret) 826 return ret; 827 828 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 829 if (!cq_host) { 830 ret = -ENOMEM; 831 goto cleanup; 832 } 833 834 cq_host->mmio = host->ioaddr + 0x200; 835 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 836 cq_host->ops = &glk_cqhci_ops; 837 838 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 839 if (dma64) 840 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 841 842 ret = cqhci_init(cq_host, host->mmc, dma64); 843 if (ret) 844 goto cleanup; 845 846 ret = __sdhci_add_host(host); 847 if (ret) 848 goto cleanup; 849 850 return 0; 851 852 cleanup: 853 sdhci_cleanup_host(host); 854 return ret; 855 } 856 857 #ifdef CONFIG_PM 858 #define GLK_RX_CTRL1 0x834 859 #define GLK_TUN_VAL 0x840 860 #define GLK_PATH_PLL GENMASK(13, 8) 861 #define GLK_DLY GENMASK(6, 0) 862 /* Workaround firmware failing to restore the tuning value */ 863 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 864 { 865 struct sdhci_pci_slot *slot = chip->slots[0]; 866 struct intel_host *intel_host = sdhci_pci_priv(slot); 867 struct sdhci_host *host = slot->host; 868 u32 glk_rx_ctrl1; 869 u32 glk_tun_val; 870 u32 dly; 871 872 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 873 return; 874 875 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 876 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 877 878 if (susp) { 879 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 880 intel_host->glk_tun_val = glk_tun_val; 881 return; 882 } 883 884 if (!intel_host->glk_tun_val) 885 return; 886 887 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 888 intel_host->rpm_retune_ok = true; 889 return; 890 } 891 892 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 893 (intel_host->glk_tun_val << 1)); 894 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 895 return; 896 897 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 898 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 899 900 intel_host->rpm_retune_ok = true; 901 chip->rpm_retune = true; 902 mmc_retune_needed(host->mmc); 903 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 904 } 905 906 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 907 { 908 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 909 !chip->rpm_retune) 910 glk_rpm_retune_wa(chip, susp); 911 } 912 913 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 914 { 915 glk_rpm_retune_chk(chip, true); 916 917 return sdhci_cqhci_runtime_suspend(chip); 918 } 919 920 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 921 { 922 glk_rpm_retune_chk(chip, false); 923 924 return sdhci_cqhci_runtime_resume(chip); 925 } 926 #endif 927 928 #ifdef CONFIG_ACPI 929 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 930 { 931 acpi_status status; 932 unsigned long long max_freq; 933 934 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 935 "MXFQ", NULL, &max_freq); 936 if (ACPI_FAILURE(status)) { 937 dev_err(&slot->chip->pdev->dev, 938 "MXFQ not found in acpi table\n"); 939 return -EINVAL; 940 } 941 942 slot->host->mmc->f_max = max_freq * 1000000; 943 944 return 0; 945 } 946 #else 947 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 948 { 949 return 0; 950 } 951 #endif 952 953 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 954 { 955 int err; 956 957 byt_probe_slot(slot); 958 959 err = ni_set_max_freq(slot); 960 if (err) 961 return err; 962 963 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 964 MMC_CAP_WAIT_WHILE_BUSY; 965 return 0; 966 } 967 968 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 969 { 970 byt_probe_slot(slot); 971 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 972 MMC_CAP_WAIT_WHILE_BUSY; 973 return 0; 974 } 975 976 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 977 { 978 byt_probe_slot(slot); 979 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 980 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 981 slot->cd_idx = 0; 982 slot->cd_override_level = true; 983 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 984 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 985 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 986 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 987 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 988 989 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 990 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 991 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 992 993 return 0; 994 } 995 996 #ifdef CONFIG_PM_SLEEP 997 998 static int byt_resume(struct sdhci_pci_chip *chip) 999 { 1000 byt_ocp_setting(chip->pdev); 1001 1002 return sdhci_pci_resume_host(chip); 1003 } 1004 1005 #endif 1006 1007 #ifdef CONFIG_PM 1008 1009 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1010 { 1011 byt_ocp_setting(chip->pdev); 1012 1013 return sdhci_pci_runtime_resume_host(chip); 1014 } 1015 1016 #endif 1017 1018 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1019 #ifdef CONFIG_PM_SLEEP 1020 .resume = byt_resume, 1021 #endif 1022 #ifdef CONFIG_PM 1023 .runtime_resume = byt_runtime_resume, 1024 #endif 1025 .allow_runtime_pm = true, 1026 .probe_slot = byt_emmc_probe_slot, 1027 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1028 SDHCI_QUIRK_NO_LED, 1029 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1030 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1031 SDHCI_QUIRK2_STOP_WITH_TC, 1032 .ops = &sdhci_intel_byt_ops, 1033 .priv_size = sizeof(struct intel_host), 1034 }; 1035 1036 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1037 .allow_runtime_pm = true, 1038 .probe_slot = glk_emmc_probe_slot, 1039 .add_host = glk_emmc_add_host, 1040 #ifdef CONFIG_PM_SLEEP 1041 .suspend = sdhci_cqhci_suspend, 1042 .resume = sdhci_cqhci_resume, 1043 #endif 1044 #ifdef CONFIG_PM 1045 .runtime_suspend = glk_runtime_suspend, 1046 .runtime_resume = glk_runtime_resume, 1047 #endif 1048 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1049 SDHCI_QUIRK_NO_LED, 1050 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1051 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1052 SDHCI_QUIRK2_STOP_WITH_TC, 1053 .ops = &sdhci_intel_glk_ops, 1054 .priv_size = sizeof(struct intel_host), 1055 }; 1056 1057 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1058 #ifdef CONFIG_PM_SLEEP 1059 .resume = byt_resume, 1060 #endif 1061 #ifdef CONFIG_PM 1062 .runtime_resume = byt_runtime_resume, 1063 #endif 1064 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1065 SDHCI_QUIRK_NO_LED, 1066 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1067 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1068 .allow_runtime_pm = true, 1069 .probe_slot = ni_byt_sdio_probe_slot, 1070 .ops = &sdhci_intel_byt_ops, 1071 .priv_size = sizeof(struct intel_host), 1072 }; 1073 1074 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1075 #ifdef CONFIG_PM_SLEEP 1076 .resume = byt_resume, 1077 #endif 1078 #ifdef CONFIG_PM 1079 .runtime_resume = byt_runtime_resume, 1080 #endif 1081 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1082 SDHCI_QUIRK_NO_LED, 1083 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1084 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1085 .allow_runtime_pm = true, 1086 .probe_slot = byt_sdio_probe_slot, 1087 .ops = &sdhci_intel_byt_ops, 1088 .priv_size = sizeof(struct intel_host), 1089 }; 1090 1091 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1092 #ifdef CONFIG_PM_SLEEP 1093 .resume = byt_resume, 1094 #endif 1095 #ifdef CONFIG_PM 1096 .runtime_resume = byt_runtime_resume, 1097 #endif 1098 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1099 SDHCI_QUIRK_NO_LED, 1100 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1101 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1102 SDHCI_QUIRK2_STOP_WITH_TC, 1103 .allow_runtime_pm = true, 1104 .own_cd_for_runtime_pm = true, 1105 .probe_slot = byt_sd_probe_slot, 1106 .ops = &sdhci_intel_byt_ops, 1107 .priv_size = sizeof(struct intel_host), 1108 }; 1109 1110 /* Define Host controllers for Intel Merrifield platform */ 1111 #define INTEL_MRFLD_EMMC_0 0 1112 #define INTEL_MRFLD_EMMC_1 1 1113 #define INTEL_MRFLD_SD 2 1114 #define INTEL_MRFLD_SDIO 3 1115 1116 #ifdef CONFIG_ACPI 1117 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1118 { 1119 struct acpi_device *device, *child; 1120 1121 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1122 if (!device) 1123 return; 1124 1125 acpi_device_fix_up_power(device); 1126 list_for_each_entry(child, &device->children, node) 1127 if (child->status.present && child->status.enabled) 1128 acpi_device_fix_up_power(child); 1129 } 1130 #else 1131 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1132 #endif 1133 1134 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1135 { 1136 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1137 1138 switch (func) { 1139 case INTEL_MRFLD_EMMC_0: 1140 case INTEL_MRFLD_EMMC_1: 1141 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1142 MMC_CAP_8_BIT_DATA | 1143 MMC_CAP_1_8V_DDR; 1144 break; 1145 case INTEL_MRFLD_SD: 1146 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1147 break; 1148 case INTEL_MRFLD_SDIO: 1149 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1150 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1151 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1152 MMC_CAP_POWER_OFF_CARD; 1153 break; 1154 default: 1155 return -ENODEV; 1156 } 1157 1158 intel_mrfld_mmc_fix_up_power_slot(slot); 1159 return 0; 1160 } 1161 1162 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1163 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1164 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1165 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1166 .allow_runtime_pm = true, 1167 .probe_slot = intel_mrfld_mmc_probe_slot, 1168 }; 1169 1170 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1171 { 1172 u8 scratch; 1173 int ret; 1174 1175 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1176 if (ret) 1177 return ret; 1178 1179 /* 1180 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1181 * [bit 1:2] and enable over current debouncing [bit 6]. 1182 */ 1183 if (on) 1184 scratch |= 0x47; 1185 else 1186 scratch &= ~0x47; 1187 1188 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1189 } 1190 1191 static int jmicron_probe(struct sdhci_pci_chip *chip) 1192 { 1193 int ret; 1194 u16 mmcdev = 0; 1195 1196 if (chip->pdev->revision == 0) { 1197 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1198 SDHCI_QUIRK_32BIT_DMA_SIZE | 1199 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1200 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1201 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1202 } 1203 1204 /* 1205 * JMicron chips can have two interfaces to the same hardware 1206 * in order to work around limitations in Microsoft's driver. 1207 * We need to make sure we only bind to one of them. 1208 * 1209 * This code assumes two things: 1210 * 1211 * 1. The PCI code adds subfunctions in order. 1212 * 1213 * 2. The MMC interface has a lower subfunction number 1214 * than the SD interface. 1215 */ 1216 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1217 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1218 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1219 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1220 1221 if (mmcdev) { 1222 struct pci_dev *sd_dev; 1223 1224 sd_dev = NULL; 1225 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1226 mmcdev, sd_dev)) != NULL) { 1227 if ((PCI_SLOT(chip->pdev->devfn) == 1228 PCI_SLOT(sd_dev->devfn)) && 1229 (chip->pdev->bus == sd_dev->bus)) 1230 break; 1231 } 1232 1233 if (sd_dev) { 1234 pci_dev_put(sd_dev); 1235 dev_info(&chip->pdev->dev, "Refusing to bind to " 1236 "secondary interface.\n"); 1237 return -ENODEV; 1238 } 1239 } 1240 1241 /* 1242 * JMicron chips need a bit of a nudge to enable the power 1243 * output pins. 1244 */ 1245 ret = jmicron_pmos(chip, 1); 1246 if (ret) { 1247 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1248 return ret; 1249 } 1250 1251 /* quirk for unsable RO-detection on JM388 chips */ 1252 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1253 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1254 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1255 1256 return 0; 1257 } 1258 1259 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1260 { 1261 u8 scratch; 1262 1263 scratch = readb(host->ioaddr + 0xC0); 1264 1265 if (on) 1266 scratch |= 0x01; 1267 else 1268 scratch &= ~0x01; 1269 1270 writeb(scratch, host->ioaddr + 0xC0); 1271 } 1272 1273 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1274 { 1275 if (slot->chip->pdev->revision == 0) { 1276 u16 version; 1277 1278 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1279 version = (version & SDHCI_VENDOR_VER_MASK) >> 1280 SDHCI_VENDOR_VER_SHIFT; 1281 1282 /* 1283 * Older versions of the chip have lots of nasty glitches 1284 * in the ADMA engine. It's best just to avoid it 1285 * completely. 1286 */ 1287 if (version < 0xAC) 1288 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1289 } 1290 1291 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1292 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1293 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1294 MMC_VDD_29_30 | MMC_VDD_30_31 | 1295 MMC_VDD_165_195; /* allow 1.8V */ 1296 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1297 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1298 } 1299 1300 /* 1301 * The secondary interface requires a bit set to get the 1302 * interrupts. 1303 */ 1304 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1305 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1306 jmicron_enable_mmc(slot->host, 1); 1307 1308 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1309 1310 return 0; 1311 } 1312 1313 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1314 { 1315 if (dead) 1316 return; 1317 1318 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1319 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1320 jmicron_enable_mmc(slot->host, 0); 1321 } 1322 1323 #ifdef CONFIG_PM_SLEEP 1324 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1325 { 1326 int i, ret; 1327 1328 ret = sdhci_pci_suspend_host(chip); 1329 if (ret) 1330 return ret; 1331 1332 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1333 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1334 for (i = 0; i < chip->num_slots; i++) 1335 jmicron_enable_mmc(chip->slots[i]->host, 0); 1336 } 1337 1338 return 0; 1339 } 1340 1341 static int jmicron_resume(struct sdhci_pci_chip *chip) 1342 { 1343 int ret, i; 1344 1345 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1346 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1347 for (i = 0; i < chip->num_slots; i++) 1348 jmicron_enable_mmc(chip->slots[i]->host, 1); 1349 } 1350 1351 ret = jmicron_pmos(chip, 1); 1352 if (ret) { 1353 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1354 return ret; 1355 } 1356 1357 return sdhci_pci_resume_host(chip); 1358 } 1359 #endif 1360 1361 static const struct sdhci_pci_fixes sdhci_jmicron = { 1362 .probe = jmicron_probe, 1363 1364 .probe_slot = jmicron_probe_slot, 1365 .remove_slot = jmicron_remove_slot, 1366 1367 #ifdef CONFIG_PM_SLEEP 1368 .suspend = jmicron_suspend, 1369 .resume = jmicron_resume, 1370 #endif 1371 }; 1372 1373 /* SysKonnect CardBus2SDIO extra registers */ 1374 #define SYSKT_CTRL 0x200 1375 #define SYSKT_RDFIFO_STAT 0x204 1376 #define SYSKT_WRFIFO_STAT 0x208 1377 #define SYSKT_POWER_DATA 0x20c 1378 #define SYSKT_POWER_330 0xef 1379 #define SYSKT_POWER_300 0xf8 1380 #define SYSKT_POWER_184 0xcc 1381 #define SYSKT_POWER_CMD 0x20d 1382 #define SYSKT_POWER_START (1 << 7) 1383 #define SYSKT_POWER_STATUS 0x20e 1384 #define SYSKT_POWER_STATUS_OK (1 << 0) 1385 #define SYSKT_BOARD_REV 0x210 1386 #define SYSKT_CHIP_REV 0x211 1387 #define SYSKT_CONF_DATA 0x212 1388 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1389 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1390 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1391 1392 static int syskt_probe(struct sdhci_pci_chip *chip) 1393 { 1394 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1395 chip->pdev->class &= ~0x0000FF; 1396 chip->pdev->class |= PCI_SDHCI_IFDMA; 1397 } 1398 return 0; 1399 } 1400 1401 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1402 { 1403 int tm, ps; 1404 1405 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1406 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1407 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1408 "board rev %d.%d, chip rev %d.%d\n", 1409 board_rev >> 4, board_rev & 0xf, 1410 chip_rev >> 4, chip_rev & 0xf); 1411 if (chip_rev >= 0x20) 1412 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1413 1414 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1415 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1416 udelay(50); 1417 tm = 10; /* Wait max 1 ms */ 1418 do { 1419 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1420 if (ps & SYSKT_POWER_STATUS_OK) 1421 break; 1422 udelay(100); 1423 } while (--tm); 1424 if (!tm) { 1425 dev_err(&slot->chip->pdev->dev, 1426 "power regulator never stabilized"); 1427 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1428 return -ENODEV; 1429 } 1430 1431 return 0; 1432 } 1433 1434 static const struct sdhci_pci_fixes sdhci_syskt = { 1435 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1436 .probe = syskt_probe, 1437 .probe_slot = syskt_probe_slot, 1438 }; 1439 1440 static int via_probe(struct sdhci_pci_chip *chip) 1441 { 1442 if (chip->pdev->revision == 0x10) 1443 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1444 1445 return 0; 1446 } 1447 1448 static const struct sdhci_pci_fixes sdhci_via = { 1449 .probe = via_probe, 1450 }; 1451 1452 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1453 { 1454 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1455 return 0; 1456 } 1457 1458 static const struct sdhci_pci_fixes sdhci_rtsx = { 1459 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1460 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1461 SDHCI_QUIRK2_BROKEN_DDR50, 1462 .probe_slot = rtsx_probe_slot, 1463 }; 1464 1465 /*AMD chipset generation*/ 1466 enum amd_chipset_gen { 1467 AMD_CHIPSET_BEFORE_ML, 1468 AMD_CHIPSET_CZ, 1469 AMD_CHIPSET_NL, 1470 AMD_CHIPSET_UNKNOWN, 1471 }; 1472 1473 /* AMD registers */ 1474 #define AMD_SD_AUTO_PATTERN 0xB8 1475 #define AMD_MSLEEP_DURATION 4 1476 #define AMD_SD_MISC_CONTROL 0xD0 1477 #define AMD_MAX_TUNE_VALUE 0x0B 1478 #define AMD_AUTO_TUNE_SEL 0x10800 1479 #define AMD_FIFO_PTR 0x30 1480 #define AMD_BIT_MASK 0x1F 1481 1482 static void amd_tuning_reset(struct sdhci_host *host) 1483 { 1484 unsigned int val; 1485 1486 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1487 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1488 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1489 1490 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1491 val &= ~SDHCI_CTRL_EXEC_TUNING; 1492 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1493 } 1494 1495 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1496 { 1497 unsigned int val; 1498 1499 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1500 val &= ~AMD_BIT_MASK; 1501 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1502 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1503 } 1504 1505 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1506 { 1507 unsigned int val; 1508 1509 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1510 val |= AMD_FIFO_PTR; 1511 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1512 } 1513 1514 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1515 { 1516 struct sdhci_pci_slot *slot = sdhci_priv(host); 1517 struct pci_dev *pdev = slot->chip->pdev; 1518 u8 valid_win = 0; 1519 u8 valid_win_max = 0; 1520 u8 valid_win_end = 0; 1521 u8 ctrl, tune_around; 1522 1523 amd_tuning_reset(host); 1524 1525 for (tune_around = 0; tune_around < 12; tune_around++) { 1526 amd_config_tuning_phase(pdev, tune_around); 1527 1528 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1529 valid_win = 0; 1530 msleep(AMD_MSLEEP_DURATION); 1531 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1532 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1533 } else if (++valid_win > valid_win_max) { 1534 valid_win_max = valid_win; 1535 valid_win_end = tune_around; 1536 } 1537 } 1538 1539 if (!valid_win_max) { 1540 dev_err(&pdev->dev, "no tuning point found\n"); 1541 return -EIO; 1542 } 1543 1544 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1545 1546 amd_enable_manual_tuning(pdev); 1547 1548 host->mmc->retune_period = 0; 1549 1550 return 0; 1551 } 1552 1553 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1554 { 1555 struct sdhci_host *host = mmc_priv(mmc); 1556 1557 /* AMD requires custom HS200 tuning */ 1558 if (host->timing == MMC_TIMING_MMC_HS200) 1559 return amd_execute_tuning_hs200(host, opcode); 1560 1561 /* Otherwise perform standard SDHCI tuning */ 1562 return sdhci_execute_tuning(mmc, opcode); 1563 } 1564 1565 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1566 { 1567 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1568 1569 ops->execute_tuning = amd_execute_tuning; 1570 1571 return 0; 1572 } 1573 1574 static int amd_probe(struct sdhci_pci_chip *chip) 1575 { 1576 struct pci_dev *smbus_dev; 1577 enum amd_chipset_gen gen; 1578 1579 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1580 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1581 if (smbus_dev) { 1582 gen = AMD_CHIPSET_BEFORE_ML; 1583 } else { 1584 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1585 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1586 if (smbus_dev) { 1587 if (smbus_dev->revision < 0x51) 1588 gen = AMD_CHIPSET_CZ; 1589 else 1590 gen = AMD_CHIPSET_NL; 1591 } else { 1592 gen = AMD_CHIPSET_UNKNOWN; 1593 } 1594 } 1595 1596 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1597 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1598 1599 return 0; 1600 } 1601 1602 static u32 sdhci_read_present_state(struct sdhci_host *host) 1603 { 1604 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1605 } 1606 1607 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1608 { 1609 struct sdhci_pci_slot *slot = sdhci_priv(host); 1610 struct pci_dev *pdev = slot->chip->pdev; 1611 u32 present_state; 1612 1613 /* 1614 * SDHC 0x7906 requires a hard reset to clear all internal state. 1615 * Otherwise it can get into a bad state where the DATA lines are always 1616 * read as zeros. 1617 */ 1618 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1619 pci_clear_master(pdev); 1620 1621 pci_save_state(pdev); 1622 1623 pci_set_power_state(pdev, PCI_D3cold); 1624 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1625 pdev->current_state); 1626 pci_set_power_state(pdev, PCI_D0); 1627 1628 pci_restore_state(pdev); 1629 1630 /* 1631 * SDHCI_RESET_ALL says the card detect logic should not be 1632 * reset, but since we need to reset the entire controller 1633 * we should wait until the card detect logic has stabilized. 1634 * 1635 * This normally takes about 40ms. 1636 */ 1637 readx_poll_timeout( 1638 sdhci_read_present_state, 1639 host, 1640 present_state, 1641 present_state & SDHCI_CD_STABLE, 1642 10000, 1643 100000 1644 ); 1645 } 1646 1647 return sdhci_reset(host, mask); 1648 } 1649 1650 static const struct sdhci_ops amd_sdhci_pci_ops = { 1651 .set_clock = sdhci_set_clock, 1652 .enable_dma = sdhci_pci_enable_dma, 1653 .set_bus_width = sdhci_set_bus_width, 1654 .reset = amd_sdhci_reset, 1655 .set_uhs_signaling = sdhci_set_uhs_signaling, 1656 }; 1657 1658 static const struct sdhci_pci_fixes sdhci_amd = { 1659 .probe = amd_probe, 1660 .ops = &amd_sdhci_pci_ops, 1661 .probe_slot = amd_probe_slot, 1662 }; 1663 1664 static const struct pci_device_id pci_ids[] = { 1665 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1666 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1667 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1668 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1669 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1670 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1671 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1672 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1673 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1674 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1675 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1676 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1677 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1678 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1679 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1680 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1681 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1682 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1683 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1684 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1685 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1686 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1687 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1688 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1689 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1690 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1691 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1692 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1693 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1694 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1695 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1696 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1697 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1698 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1699 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1700 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1701 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1702 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1703 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1704 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1705 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1706 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1707 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1708 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1709 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1710 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1711 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1712 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1713 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1714 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1715 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1716 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1717 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1718 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1719 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1720 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1721 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1722 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1723 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1724 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1725 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1726 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1727 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1728 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1729 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1730 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1731 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1732 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1733 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1734 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1735 SDHCI_PCI_DEVICE(O2, 8120, o2), 1736 SDHCI_PCI_DEVICE(O2, 8220, o2), 1737 SDHCI_PCI_DEVICE(O2, 8221, o2), 1738 SDHCI_PCI_DEVICE(O2, 8320, o2), 1739 SDHCI_PCI_DEVICE(O2, 8321, o2), 1740 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1741 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1742 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1743 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1744 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1745 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1746 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1747 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1748 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1749 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1750 /* Generic SD host controller */ 1751 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1752 { /* end: all zeroes */ }, 1753 }; 1754 1755 MODULE_DEVICE_TABLE(pci, pci_ids); 1756 1757 /*****************************************************************************\ 1758 * * 1759 * SDHCI core callbacks * 1760 * * 1761 \*****************************************************************************/ 1762 1763 int sdhci_pci_enable_dma(struct sdhci_host *host) 1764 { 1765 struct sdhci_pci_slot *slot; 1766 struct pci_dev *pdev; 1767 1768 slot = sdhci_priv(host); 1769 pdev = slot->chip->pdev; 1770 1771 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1772 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1773 (host->flags & SDHCI_USE_SDMA)) { 1774 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1775 "doesn't fully claim to support it.\n"); 1776 } 1777 1778 pci_set_master(pdev); 1779 1780 return 0; 1781 } 1782 1783 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1784 { 1785 struct sdhci_pci_slot *slot = sdhci_priv(host); 1786 int rst_n_gpio = slot->rst_n_gpio; 1787 1788 if (!gpio_is_valid(rst_n_gpio)) 1789 return; 1790 gpio_set_value_cansleep(rst_n_gpio, 0); 1791 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1792 udelay(10); 1793 gpio_set_value_cansleep(rst_n_gpio, 1); 1794 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1795 usleep_range(300, 1000); 1796 } 1797 1798 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1799 { 1800 struct sdhci_pci_slot *slot = sdhci_priv(host); 1801 1802 if (slot->hw_reset) 1803 slot->hw_reset(host); 1804 } 1805 1806 static const struct sdhci_ops sdhci_pci_ops = { 1807 .set_clock = sdhci_set_clock, 1808 .enable_dma = sdhci_pci_enable_dma, 1809 .set_bus_width = sdhci_set_bus_width, 1810 .reset = sdhci_reset, 1811 .set_uhs_signaling = sdhci_set_uhs_signaling, 1812 .hw_reset = sdhci_pci_hw_reset, 1813 }; 1814 1815 /*****************************************************************************\ 1816 * * 1817 * Suspend/resume * 1818 * * 1819 \*****************************************************************************/ 1820 1821 #ifdef CONFIG_PM_SLEEP 1822 static int sdhci_pci_suspend(struct device *dev) 1823 { 1824 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1825 1826 if (!chip) 1827 return 0; 1828 1829 if (chip->fixes && chip->fixes->suspend) 1830 return chip->fixes->suspend(chip); 1831 1832 return sdhci_pci_suspend_host(chip); 1833 } 1834 1835 static int sdhci_pci_resume(struct device *dev) 1836 { 1837 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1838 1839 if (!chip) 1840 return 0; 1841 1842 if (chip->fixes && chip->fixes->resume) 1843 return chip->fixes->resume(chip); 1844 1845 return sdhci_pci_resume_host(chip); 1846 } 1847 #endif 1848 1849 #ifdef CONFIG_PM 1850 static int sdhci_pci_runtime_suspend(struct device *dev) 1851 { 1852 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1853 1854 if (!chip) 1855 return 0; 1856 1857 if (chip->fixes && chip->fixes->runtime_suspend) 1858 return chip->fixes->runtime_suspend(chip); 1859 1860 return sdhci_pci_runtime_suspend_host(chip); 1861 } 1862 1863 static int sdhci_pci_runtime_resume(struct device *dev) 1864 { 1865 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1866 1867 if (!chip) 1868 return 0; 1869 1870 if (chip->fixes && chip->fixes->runtime_resume) 1871 return chip->fixes->runtime_resume(chip); 1872 1873 return sdhci_pci_runtime_resume_host(chip); 1874 } 1875 #endif 1876 1877 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1878 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1879 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1880 sdhci_pci_runtime_resume, NULL) 1881 }; 1882 1883 /*****************************************************************************\ 1884 * * 1885 * Device probing/removal * 1886 * * 1887 \*****************************************************************************/ 1888 1889 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1890 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1891 int slotno) 1892 { 1893 struct sdhci_pci_slot *slot; 1894 struct sdhci_host *host; 1895 int ret, bar = first_bar + slotno; 1896 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1897 1898 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1899 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1900 return ERR_PTR(-ENODEV); 1901 } 1902 1903 if (pci_resource_len(pdev, bar) < 0x100) { 1904 dev_err(&pdev->dev, "Invalid iomem size. You may " 1905 "experience problems.\n"); 1906 } 1907 1908 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1909 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1910 return ERR_PTR(-ENODEV); 1911 } 1912 1913 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1914 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1915 return ERR_PTR(-ENODEV); 1916 } 1917 1918 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1919 if (IS_ERR(host)) { 1920 dev_err(&pdev->dev, "cannot allocate host\n"); 1921 return ERR_CAST(host); 1922 } 1923 1924 slot = sdhci_priv(host); 1925 1926 slot->chip = chip; 1927 slot->host = host; 1928 slot->rst_n_gpio = -EINVAL; 1929 slot->cd_gpio = -EINVAL; 1930 slot->cd_idx = -1; 1931 1932 /* Retrieve platform data if there is any */ 1933 if (*sdhci_pci_get_data) 1934 slot->data = sdhci_pci_get_data(pdev, slotno); 1935 1936 if (slot->data) { 1937 if (slot->data->setup) { 1938 ret = slot->data->setup(slot->data); 1939 if (ret) { 1940 dev_err(&pdev->dev, "platform setup failed\n"); 1941 goto free; 1942 } 1943 } 1944 slot->rst_n_gpio = slot->data->rst_n_gpio; 1945 slot->cd_gpio = slot->data->cd_gpio; 1946 } 1947 1948 host->hw_name = "PCI"; 1949 host->ops = chip->fixes && chip->fixes->ops ? 1950 chip->fixes->ops : 1951 &sdhci_pci_ops; 1952 host->quirks = chip->quirks; 1953 host->quirks2 = chip->quirks2; 1954 1955 host->irq = pdev->irq; 1956 1957 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1958 if (ret) { 1959 dev_err(&pdev->dev, "cannot request region\n"); 1960 goto cleanup; 1961 } 1962 1963 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1964 1965 if (chip->fixes && chip->fixes->probe_slot) { 1966 ret = chip->fixes->probe_slot(slot); 1967 if (ret) 1968 goto cleanup; 1969 } 1970 1971 if (gpio_is_valid(slot->rst_n_gpio)) { 1972 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1973 gpio_direction_output(slot->rst_n_gpio, 1); 1974 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1975 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1976 } else { 1977 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1978 slot->rst_n_gpio = -EINVAL; 1979 } 1980 } 1981 1982 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1983 host->mmc->slotno = slotno; 1984 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1985 1986 if (device_can_wakeup(&pdev->dev)) 1987 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1988 1989 if (host->mmc->caps & MMC_CAP_CD_WAKE) 1990 device_init_wakeup(&pdev->dev, true); 1991 1992 if (slot->cd_idx >= 0) { 1993 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 1994 slot->cd_override_level, 0); 1995 if (ret && ret != -EPROBE_DEFER) 1996 ret = mmc_gpiod_request_cd(host->mmc, NULL, 1997 slot->cd_idx, 1998 slot->cd_override_level, 1999 0); 2000 if (ret == -EPROBE_DEFER) 2001 goto remove; 2002 2003 if (ret) { 2004 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2005 slot->cd_idx = -1; 2006 } 2007 } 2008 2009 if (chip->fixes && chip->fixes->add_host) 2010 ret = chip->fixes->add_host(slot); 2011 else 2012 ret = sdhci_add_host(host); 2013 if (ret) 2014 goto remove; 2015 2016 sdhci_pci_add_own_cd(slot); 2017 2018 /* 2019 * Check if the chip needs a separate GPIO for card detect to wake up 2020 * from runtime suspend. If it is not there, don't allow runtime PM. 2021 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2022 */ 2023 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2024 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2025 chip->allow_runtime_pm = false; 2026 2027 return slot; 2028 2029 remove: 2030 if (chip->fixes && chip->fixes->remove_slot) 2031 chip->fixes->remove_slot(slot, 0); 2032 2033 cleanup: 2034 if (slot->data && slot->data->cleanup) 2035 slot->data->cleanup(slot->data); 2036 2037 free: 2038 sdhci_free_host(host); 2039 2040 return ERR_PTR(ret); 2041 } 2042 2043 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2044 { 2045 int dead; 2046 u32 scratch; 2047 2048 sdhci_pci_remove_own_cd(slot); 2049 2050 dead = 0; 2051 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2052 if (scratch == (u32)-1) 2053 dead = 1; 2054 2055 sdhci_remove_host(slot->host, dead); 2056 2057 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2058 slot->chip->fixes->remove_slot(slot, dead); 2059 2060 if (slot->data && slot->data->cleanup) 2061 slot->data->cleanup(slot->data); 2062 2063 sdhci_free_host(slot->host); 2064 } 2065 2066 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2067 { 2068 pm_suspend_ignore_children(dev, 1); 2069 pm_runtime_set_autosuspend_delay(dev, 50); 2070 pm_runtime_use_autosuspend(dev); 2071 pm_runtime_allow(dev); 2072 /* Stay active until mmc core scans for a card */ 2073 pm_runtime_put_noidle(dev); 2074 } 2075 2076 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2077 { 2078 pm_runtime_forbid(dev); 2079 pm_runtime_get_noresume(dev); 2080 } 2081 2082 static int sdhci_pci_probe(struct pci_dev *pdev, 2083 const struct pci_device_id *ent) 2084 { 2085 struct sdhci_pci_chip *chip; 2086 struct sdhci_pci_slot *slot; 2087 2088 u8 slots, first_bar; 2089 int ret, i; 2090 2091 BUG_ON(pdev == NULL); 2092 BUG_ON(ent == NULL); 2093 2094 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2095 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2096 2097 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2098 if (ret) 2099 return ret; 2100 2101 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2102 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2103 2104 BUG_ON(slots > MAX_SLOTS); 2105 2106 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2107 if (ret) 2108 return ret; 2109 2110 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2111 2112 if (first_bar > 5) { 2113 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2114 return -ENODEV; 2115 } 2116 2117 ret = pcim_enable_device(pdev); 2118 if (ret) 2119 return ret; 2120 2121 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2122 if (!chip) 2123 return -ENOMEM; 2124 2125 chip->pdev = pdev; 2126 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2127 if (chip->fixes) { 2128 chip->quirks = chip->fixes->quirks; 2129 chip->quirks2 = chip->fixes->quirks2; 2130 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2131 } 2132 chip->num_slots = slots; 2133 chip->pm_retune = true; 2134 chip->rpm_retune = true; 2135 2136 pci_set_drvdata(pdev, chip); 2137 2138 if (chip->fixes && chip->fixes->probe) { 2139 ret = chip->fixes->probe(chip); 2140 if (ret) 2141 return ret; 2142 } 2143 2144 slots = chip->num_slots; /* Quirk may have changed this */ 2145 2146 for (i = 0; i < slots; i++) { 2147 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2148 if (IS_ERR(slot)) { 2149 for (i--; i >= 0; i--) 2150 sdhci_pci_remove_slot(chip->slots[i]); 2151 return PTR_ERR(slot); 2152 } 2153 2154 chip->slots[i] = slot; 2155 } 2156 2157 if (chip->allow_runtime_pm) 2158 sdhci_pci_runtime_pm_allow(&pdev->dev); 2159 2160 return 0; 2161 } 2162 2163 static void sdhci_pci_remove(struct pci_dev *pdev) 2164 { 2165 int i; 2166 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2167 2168 if (chip->allow_runtime_pm) 2169 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2170 2171 for (i = 0; i < chip->num_slots; i++) 2172 sdhci_pci_remove_slot(chip->slots[i]); 2173 } 2174 2175 static struct pci_driver sdhci_driver = { 2176 .name = "sdhci-pci", 2177 .id_table = pci_ids, 2178 .probe = sdhci_pci_probe, 2179 .remove = sdhci_pci_remove, 2180 .driver = { 2181 .pm = &sdhci_pci_pm_ops 2182 }, 2183 }; 2184 2185 module_pci_driver(sdhci_driver); 2186 2187 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2188 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2189 MODULE_LICENSE("GPL"); 2190