xref: /linux/drivers/mmc/host/via-sdmmc.c (revision f86fd32d) 
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver
4  *  Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved.
5  */
6 
7 #include <linux/pci.h>
8 #include <linux/module.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/highmem.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 
14 #include <linux/mmc/host.h>
15 
16 #define DRV_NAME	"via_sdmmc"
17 
18 #define PCI_DEVICE_ID_VIA_9530	0x9530
19 
20 #define VIA_CRDR_SDC_OFF	0x200
21 #define VIA_CRDR_DDMA_OFF	0x400
22 #define VIA_CRDR_PCICTRL_OFF	0x600
23 
24 #define VIA_CRDR_MIN_CLOCK	375000
25 #define VIA_CRDR_MAX_CLOCK	48000000
26 
27 /*
28  * PCI registers
29  */
30 
31 #define VIA_CRDR_PCI_WORK_MODE	0x40
32 #define VIA_CRDR_PCI_DBG_MODE	0x41
33 
34 /*
35  * SDC MMIO Registers
36  */
37 
38 #define VIA_CRDR_SDCTRL			0x0
39 #define VIA_CRDR_SDCTRL_START		0x01
40 #define VIA_CRDR_SDCTRL_WRITE		0x04
41 #define VIA_CRDR_SDCTRL_SINGLE_WR	0x10
42 #define VIA_CRDR_SDCTRL_SINGLE_RD	0x20
43 #define VIA_CRDR_SDCTRL_MULTI_WR	0x30
44 #define VIA_CRDR_SDCTRL_MULTI_RD	0x40
45 #define VIA_CRDR_SDCTRL_STOP		0x70
46 
47 #define VIA_CRDR_SDCTRL_RSP_NONE	0x0
48 #define VIA_CRDR_SDCTRL_RSP_R1		0x10000
49 #define VIA_CRDR_SDCTRL_RSP_R2		0x20000
50 #define VIA_CRDR_SDCTRL_RSP_R3		0x30000
51 #define VIA_CRDR_SDCTRL_RSP_R1B		0x90000
52 
53 #define VIA_CRDR_SDCARG 	0x4
54 
55 #define VIA_CRDR_SDBUSMODE	0x8
56 #define VIA_CRDR_SDMODE_4BIT	0x02
57 #define VIA_CRDR_SDMODE_CLK_ON	0x40
58 
59 #define VIA_CRDR_SDBLKLEN	0xc
60 /*
61  * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048.
62  * Bit 11 - Bit 13 : Reserved.
63  * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design.
64  * INTEN : Enable SD host interrupt.
65  * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536.
66  */
67 #define VIA_CRDR_SDBLKLEN_GPIDET	0x2000
68 #define VIA_CRDR_SDBLKLEN_INTEN		0x8000
69 #define VIA_CRDR_MAX_BLOCK_COUNT	65536
70 #define VIA_CRDR_MAX_BLOCK_LENGTH	2048
71 
72 #define VIA_CRDR_SDRESP0	0x10
73 #define VIA_CRDR_SDRESP1	0x14
74 #define VIA_CRDR_SDRESP2	0x18
75 #define VIA_CRDR_SDRESP3	0x1c
76 
77 #define VIA_CRDR_SDCURBLKCNT	0x20
78 
79 #define VIA_CRDR_SDINTMASK	0x24
80 /*
81  * MBDIE : Multiple Blocks transfer Done Interrupt Enable
82  * BDDIE : Block Data transfer Done Interrupt Enable
83  * CIRIE : Card Insertion or Removal Interrupt Enable
84  * CRDIE : Command-Response transfer Done Interrupt Enable
85  * CRTOIE : Command-Response response TimeOut Interrupt Enable
86  * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable
87  * DTIE : Data access Timeout Interrupt Enable
88  * SCIE : reSponse CRC error Interrupt Enable
89  * RCIE : Read data CRC error Interrupt Enable
90  * WCIE : Write data CRC error Interrupt Enable
91  */
92 #define VIA_CRDR_SDINTMASK_MBDIE	0x10
93 #define VIA_CRDR_SDINTMASK_BDDIE	0x20
94 #define VIA_CRDR_SDINTMASK_CIRIE	0x80
95 #define VIA_CRDR_SDINTMASK_CRDIE	0x200
96 #define VIA_CRDR_SDINTMASK_CRTOIE	0x400
97 #define VIA_CRDR_SDINTMASK_ASCRDIE	0x800
98 #define VIA_CRDR_SDINTMASK_DTIE		0x1000
99 #define VIA_CRDR_SDINTMASK_SCIE		0x2000
100 #define VIA_CRDR_SDINTMASK_RCIE		0x4000
101 #define VIA_CRDR_SDINTMASK_WCIE		0x8000
102 
103 #define VIA_CRDR_SDACTIVE_INTMASK \
104 	(VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \
105 	| VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \
106 	| VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \
107 	| VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE)
108 
109 #define VIA_CRDR_SDSTATUS	0x28
110 /*
111  * CECC : Reserved
112  * WP : SD card Write Protect status
113  * SLOTD : Reserved
114  * SLOTG : SD SLOT status(Gpi pin status)
115  * MBD : Multiple Blocks transfer Done interrupt status
116  * BDD : Block Data transfer Done interrupt status
117  * CD : Reserved
118  * CIR : Card Insertion or Removal interrupt detected on GPI pin
119  * IO : Reserved
120  * CRD : Command-Response transfer Done interrupt status
121  * CRTO : Command-Response response TimeOut interrupt status
122  * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status
123  * DT : Data access Timeout interrupt status
124  * SC : reSponse CRC error interrupt status
125  * RC : Read data CRC error interrupt status
126  * WC : Write data CRC error interrupt status
127  */
128 #define VIA_CRDR_SDSTS_CECC		0x01
129 #define VIA_CRDR_SDSTS_WP		0x02
130 #define VIA_CRDR_SDSTS_SLOTD		0x04
131 #define VIA_CRDR_SDSTS_SLOTG		0x08
132 #define VIA_CRDR_SDSTS_MBD		0x10
133 #define VIA_CRDR_SDSTS_BDD		0x20
134 #define VIA_CRDR_SDSTS_CD		0x40
135 #define VIA_CRDR_SDSTS_CIR		0x80
136 #define VIA_CRDR_SDSTS_IO		0x100
137 #define VIA_CRDR_SDSTS_CRD		0x200
138 #define VIA_CRDR_SDSTS_CRTO		0x400
139 #define VIA_CRDR_SDSTS_ASCRDIE		0x800
140 #define VIA_CRDR_SDSTS_DT		0x1000
141 #define VIA_CRDR_SDSTS_SC		0x2000
142 #define VIA_CRDR_SDSTS_RC		0x4000
143 #define VIA_CRDR_SDSTS_WC		0x8000
144 
145 #define VIA_CRDR_SDSTS_IGN_MASK\
146 	(VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO)
147 #define VIA_CRDR_SDSTS_INT_MASK \
148 	(VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \
149 	| VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \
150 	| VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
151 	| VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
152 #define VIA_CRDR_SDSTS_W1C_MASK \
153 	(VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \
154 	| VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \
155 	| VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \
156 	| VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
157 #define  VIA_CRDR_SDSTS_CMD_MASK \
158 	(VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC)
159 #define  VIA_CRDR_SDSTS_DATA_MASK\
160 	(VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \
161 	| VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)
162 
163 #define VIA_CRDR_SDSTATUS2	0x2a
164 /*
165  * CFE : Enable SD host automatic Clock FReezing
166  */
167 #define VIA_CRDR_SDSTS_CFE		0x80
168 
169 #define VIA_CRDR_SDRSPTMO	0x2C
170 
171 #define VIA_CRDR_SDCLKSEL	0x30
172 
173 #define VIA_CRDR_SDEXTCTRL	0x34
174 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD	0x01
175 #define VIS_CRDR_SDEXTCTRL_SHIFT_9	0x02
176 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT	0x04
177 #define VIS_CRDR_SDEXTCTRL_RELD_BLK	0x08
178 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA	0x10
179 #define VIS_CRDR_SDEXTCTRL_BAD_DATA	0x20
180 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI	0x40
181 #define VIA_CRDR_SDEXTCTRL_HISPD	0x80
182 /* 0x38-0xFF reserved */
183 
184 /*
185  * Data DMA Control Registers
186  */
187 
188 #define VIA_CRDR_DMABASEADD	0x0
189 #define VIA_CRDR_DMACOUNTER	0x4
190 
191 #define VIA_CRDR_DMACTRL	0x8
192 /*
193  * DIR :Transaction Direction
194  * 0 : From card to memory
195  * 1 : From memory to card
196  */
197 #define VIA_CRDR_DMACTRL_DIR		0x100
198 #define VIA_CRDR_DMACTRL_ENIRQ		0x10000
199 #define VIA_CRDR_DMACTRL_SFTRST		0x1000000
200 
201 #define VIA_CRDR_DMASTS		0xc
202 
203 #define VIA_CRDR_DMASTART	0x10
204 /*0x14-0xFF reserved*/
205 
206 /*
207  * PCI Control Registers
208  */
209 
210 /*0x0 - 0x1 reserved*/
211 #define VIA_CRDR_PCICLKGATT	0x2
212 /*
213  * SFTRST :
214  * 0 : Soft reset all the controller and it will be de-asserted automatically
215  * 1 : Soft reset is de-asserted
216  */
217 #define VIA_CRDR_PCICLKGATT_SFTRST	0x01
218 /*
219  * 3V3 : Pad power select
220  * 0 : 1.8V
221  * 1 : 3.3V
222  * NOTE : No mater what the actual value should be, this bit always
223  * read as 0. This is a hardware bug.
224  */
225 #define VIA_CRDR_PCICLKGATT_3V3	0x10
226 /*
227  * PAD_PWRON : Pad Power on/off select
228  * 0 : Power off
229  * 1 : Power on
230   * NOTE : No mater what the actual value should be, this bit always
231  * read as 0. This is a hardware bug.
232  */
233 #define VIA_CRDR_PCICLKGATT_PAD_PWRON	0x20
234 
235 #define VIA_CRDR_PCISDCCLK	0x5
236 
237 #define VIA_CRDR_PCIDMACLK	0x7
238 #define VIA_CRDR_PCIDMACLK_SDC		0x2
239 
240 #define VIA_CRDR_PCIINTCTRL	0x8
241 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN	0x04
242 
243 #define VIA_CRDR_PCIINTSTATUS	0x9
244 #define VIA_CRDR_PCIINTSTATUS_SDC	0x04
245 
246 #define  VIA_CRDR_PCITMOCTRL	0xa
247 #define VIA_CRDR_PCITMOCTRL_NO		0x0
248 #define VIA_CRDR_PCITMOCTRL_32US	0x1
249 #define VIA_CRDR_PCITMOCTRL_256US	0x2
250 #define VIA_CRDR_PCITMOCTRL_1024US	0x3
251 #define VIA_CRDR_PCITMOCTRL_256MS	0x4
252 #define VIA_CRDR_PCITMOCTRL_512MS	0x5
253 #define VIA_CRDR_PCITMOCTRL_1024MS	0x6
254 
255 /*0xB-0xFF reserved*/
256 
257 enum PCI_HOST_CLK_CONTROL {
258 	PCI_CLK_375K = 0x03,
259 	PCI_CLK_8M = 0x04,
260 	PCI_CLK_12M = 0x00,
261 	PCI_CLK_16M = 0x05,
262 	PCI_CLK_24M = 0x01,
263 	PCI_CLK_33M = 0x06,
264 	PCI_CLK_48M = 0x02
265 };
266 
267 struct sdhcreg {
268 	u32 sdcontrol_reg;
269 	u32 sdcmdarg_reg;
270 	u32 sdbusmode_reg;
271 	u32 sdblklen_reg;
272 	u32 sdresp_reg[4];
273 	u32 sdcurblkcnt_reg;
274 	u32 sdintmask_reg;
275 	u32 sdstatus_reg;
276 	u32 sdrsptmo_reg;
277 	u32 sdclksel_reg;
278 	u32 sdextctrl_reg;
279 };
280 
281 struct pcictrlreg {
282 	u8 reserve[2];
283 	u8 pciclkgat_reg;
284 	u8 pcinfcclk_reg;
285 	u8 pcimscclk_reg;
286 	u8 pcisdclk_reg;
287 	u8 pcicaclk_reg;
288 	u8 pcidmaclk_reg;
289 	u8 pciintctrl_reg;
290 	u8 pciintstatus_reg;
291 	u8 pcitmoctrl_reg;
292 	u8 Resv;
293 };
294 
295 struct via_crdr_mmc_host {
296 	struct mmc_host *mmc;
297 	struct mmc_request *mrq;
298 	struct mmc_command *cmd;
299 	struct mmc_data *data;
300 
301 	void __iomem *mmiobase;
302 	void __iomem *sdhc_mmiobase;
303 	void __iomem *ddma_mmiobase;
304 	void __iomem *pcictrl_mmiobase;
305 
306 	struct pcictrlreg pm_pcictrl_reg;
307 	struct sdhcreg pm_sdhc_reg;
308 
309 	struct work_struct carddet_work;
310 	struct tasklet_struct finish_tasklet;
311 
312 	struct timer_list timer;
313 	spinlock_t lock;
314 	u8 power;
315 	int reject;
316 	unsigned int quirks;
317 };
318 
319 /* some devices need a very long delay for power to stabilize */
320 #define VIA_CRDR_QUIRK_300MS_PWRDELAY	0x0001
321 
322 static const struct pci_device_id via_ids[] = {
323 	{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530,
324 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
325 	{0,}
326 };
327 
328 MODULE_DEVICE_TABLE(pci, via_ids);
329 
330 static void via_print_sdchc(struct via_crdr_mmc_host *host)
331 {
332 	void __iomem *addrbase = host->sdhc_mmiobase;
333 
334 	pr_debug("SDC MMIO Registers:\n");
335 	pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n",
336 		 readl(addrbase + VIA_CRDR_SDCTRL),
337 		 readl(addrbase + VIA_CRDR_SDCARG),
338 		 readl(addrbase + VIA_CRDR_SDBUSMODE));
339 	pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n",
340 		 readl(addrbase + VIA_CRDR_SDBLKLEN),
341 		 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
342 		 readl(addrbase + VIA_CRDR_SDINTMASK));
343 	pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n",
344 		 readl(addrbase + VIA_CRDR_SDSTATUS),
345 		 readl(addrbase + VIA_CRDR_SDCLKSEL),
346 		 readl(addrbase + VIA_CRDR_SDEXTCTRL));
347 }
348 
349 static void via_print_pcictrl(struct via_crdr_mmc_host *host)
350 {
351 	void __iomem *addrbase = host->pcictrl_mmiobase;
352 
353 	pr_debug("PCI Control Registers:\n");
354 	pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n",
355 		 readb(addrbase + VIA_CRDR_PCICLKGATT),
356 		 readb(addrbase + VIA_CRDR_PCISDCCLK),
357 		 readb(addrbase + VIA_CRDR_PCIDMACLK));
358 	pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n",
359 		 readb(addrbase + VIA_CRDR_PCIINTCTRL),
360 		 readb(addrbase + VIA_CRDR_PCIINTSTATUS));
361 }
362 
363 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host)
364 {
365 	struct pcictrlreg *pm_pcictrl_reg;
366 	void __iomem *addrbase;
367 
368 	pm_pcictrl_reg = &(host->pm_pcictrl_reg);
369 	addrbase = host->pcictrl_mmiobase;
370 
371 	pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT);
372 	pm_pcictrl_reg->pciclkgat_reg |=
373 		VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
374 	pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK);
375 	pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK);
376 	pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL);
377 	pm_pcictrl_reg->pciintstatus_reg =
378 		readb(addrbase + VIA_CRDR_PCIINTSTATUS);
379 	pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL);
380 }
381 
382 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host)
383 {
384 	struct pcictrlreg *pm_pcictrl_reg;
385 	void __iomem *addrbase;
386 
387 	pm_pcictrl_reg = &(host->pm_pcictrl_reg);
388 	addrbase = host->pcictrl_mmiobase;
389 
390 	writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT);
391 	writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK);
392 	writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK);
393 	writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL);
394 	writeb(pm_pcictrl_reg->pciintstatus_reg,
395 		addrbase + VIA_CRDR_PCIINTSTATUS);
396 	writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL);
397 }
398 
399 static void via_save_sdcreg(struct via_crdr_mmc_host *host)
400 {
401 	struct sdhcreg *pm_sdhc_reg;
402 	void __iomem *addrbase;
403 
404 	pm_sdhc_reg = &(host->pm_sdhc_reg);
405 	addrbase = host->sdhc_mmiobase;
406 
407 	pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL);
408 	pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG);
409 	pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE);
410 	pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN);
411 	pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT);
412 	pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK);
413 	pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS);
414 	pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO);
415 	pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL);
416 	pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL);
417 }
418 
419 static void via_restore_sdcreg(struct via_crdr_mmc_host *host)
420 {
421 	struct sdhcreg *pm_sdhc_reg;
422 	void __iomem *addrbase;
423 
424 	pm_sdhc_reg = &(host->pm_sdhc_reg);
425 	addrbase = host->sdhc_mmiobase;
426 
427 	writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
428 	writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
429 	writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
430 	writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
431 	writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
432 	writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
433 	writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
434 	writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
435 	writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
436 	writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
437 }
438 
439 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost)
440 {
441 	if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY)
442 		msleep(300);
443 	else
444 		msleep(3);
445 }
446 
447 static void via_set_ddma(struct via_crdr_mmc_host *host,
448 			 dma_addr_t dmaaddr, u32 count, int dir, int enirq)
449 {
450 	void __iomem *addrbase;
451 	u32 ctrl_data = 0;
452 
453 	if (enirq)
454 		ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ;
455 
456 	if (dir)
457 		ctrl_data |= VIA_CRDR_DMACTRL_DIR;
458 
459 	addrbase = host->ddma_mmiobase;
460 
461 	writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
462 	writel(count, addrbase + VIA_CRDR_DMACOUNTER);
463 	writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
464 	writel(0x01, addrbase + VIA_CRDR_DMASTART);
465 
466 	/* It seems that our DMA can not work normally with 375kHz clock */
467 	/* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */
468 	addrbase = host->pcictrl_mmiobase;
469 	if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) {
470 		dev_info(host->mmc->parent, "forcing card speed to 8MHz\n");
471 		writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK);
472 	}
473 }
474 
475 static void via_sdc_preparedata(struct via_crdr_mmc_host *host,
476 				struct mmc_data *data)
477 {
478 	void __iomem *addrbase;
479 	u32 blk_reg;
480 	int count;
481 
482 	WARN_ON(host->data);
483 
484 	/* Sanity checks */
485 	BUG_ON(data->blksz > host->mmc->max_blk_size);
486 	BUG_ON(data->blocks > host->mmc->max_blk_count);
487 
488 	host->data = data;
489 
490 	count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
491 		((data->flags & MMC_DATA_READ) ?
492 		PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
493 	BUG_ON(count != 1);
494 
495 	via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg),
496 		(data->flags & MMC_DATA_WRITE) ? 1 : 0, 1);
497 
498 	addrbase = host->sdhc_mmiobase;
499 
500 	blk_reg = data->blksz - 1;
501 	blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
502 	blk_reg |= (data->blocks) << 16;
503 
504 	writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
505 }
506 
507 static void via_sdc_get_response(struct via_crdr_mmc_host *host,
508 				 struct mmc_command *cmd)
509 {
510 	void __iomem *addrbase = host->sdhc_mmiobase;
511 	u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0);
512 	u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1);
513 	u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2);
514 	u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3);
515 
516 	if (cmd->flags & MMC_RSP_136) {
517 		cmd->resp[0] = ((u8) (dwdata1)) |
518 		    (((u8) (dwdata0 >> 24)) << 8) |
519 		    (((u8) (dwdata0 >> 16)) << 16) |
520 		    (((u8) (dwdata0 >> 8)) << 24);
521 
522 		cmd->resp[1] = ((u8) (dwdata2)) |
523 		    (((u8) (dwdata1 >> 24)) << 8) |
524 		    (((u8) (dwdata1 >> 16)) << 16) |
525 		    (((u8) (dwdata1 >> 8)) << 24);
526 
527 		cmd->resp[2] = ((u8) (dwdata3)) |
528 		    (((u8) (dwdata2 >> 24)) << 8) |
529 		    (((u8) (dwdata2 >> 16)) << 16) |
530 		    (((u8) (dwdata2 >> 8)) << 24);
531 
532 		cmd->resp[3] = 0xff |
533 		    ((((u8) (dwdata3 >> 24))) << 8) |
534 		    (((u8) (dwdata3 >> 16)) << 16) |
535 		    (((u8) (dwdata3 >> 8)) << 24);
536 	} else {
537 		dwdata0 >>= 8;
538 		cmd->resp[0] = ((dwdata0 & 0xff) << 24) |
539 		    (((dwdata0 >> 8) & 0xff) << 16) |
540 		    (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff);
541 
542 		dwdata1 >>= 8;
543 		cmd->resp[1] = ((dwdata1 & 0xff) << 24) |
544 		    (((dwdata1 >> 8) & 0xff) << 16) |
545 		    (((dwdata1 >> 16) & 0xff) << 8);
546 	}
547 }
548 
549 static void via_sdc_send_command(struct via_crdr_mmc_host *host,
550 				 struct mmc_command *cmd)
551 {
552 	void __iomem *addrbase;
553 	struct mmc_data *data;
554 	u32 cmdctrl = 0;
555 
556 	WARN_ON(host->cmd);
557 
558 	data = cmd->data;
559 	mod_timer(&host->timer, jiffies + HZ);
560 	host->cmd = cmd;
561 
562 	/*Command index*/
563 	cmdctrl = cmd->opcode << 8;
564 
565 	/*Response type*/
566 	switch (mmc_resp_type(cmd)) {
567 	case MMC_RSP_NONE:
568 		cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE;
569 		break;
570 	case MMC_RSP_R1:
571 		cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1;
572 		break;
573 	case MMC_RSP_R1B:
574 		cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B;
575 		break;
576 	case MMC_RSP_R2:
577 		cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2;
578 		break;
579 	case MMC_RSP_R3:
580 		cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3;
581 		break;
582 	default:
583 		pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc));
584 		break;
585 	}
586 
587 	if (!(cmd->data))
588 		goto nodata;
589 
590 	via_sdc_preparedata(host, data);
591 
592 	/*Command control*/
593 	if (data->blocks > 1) {
594 		if (data->flags & MMC_DATA_WRITE) {
595 			cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
596 			cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR;
597 		} else {
598 			cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD;
599 		}
600 	} else {
601 		if (data->flags & MMC_DATA_WRITE) {
602 			cmdctrl |= VIA_CRDR_SDCTRL_WRITE;
603 			cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR;
604 		} else {
605 			cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD;
606 		}
607 	}
608 
609 nodata:
610 	if (cmd == host->mrq->stop)
611 		cmdctrl |= VIA_CRDR_SDCTRL_STOP;
612 
613 	cmdctrl |= VIA_CRDR_SDCTRL_START;
614 
615 	addrbase = host->sdhc_mmiobase;
616 	writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
617 	writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
618 }
619 
620 static void via_sdc_finish_data(struct via_crdr_mmc_host *host)
621 {
622 	struct mmc_data *data;
623 
624 	BUG_ON(!host->data);
625 
626 	data = host->data;
627 	host->data = NULL;
628 
629 	if (data->error)
630 		data->bytes_xfered = 0;
631 	else
632 		data->bytes_xfered = data->blocks * data->blksz;
633 
634 	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
635 		((data->flags & MMC_DATA_READ) ?
636 		PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
637 
638 	if (data->stop)
639 		via_sdc_send_command(host, data->stop);
640 	else
641 		tasklet_schedule(&host->finish_tasklet);
642 }
643 
644 static void via_sdc_finish_command(struct via_crdr_mmc_host *host)
645 {
646 	via_sdc_get_response(host, host->cmd);
647 
648 	host->cmd->error = 0;
649 
650 	if (!host->cmd->data)
651 		tasklet_schedule(&host->finish_tasklet);
652 
653 	host->cmd = NULL;
654 }
655 
656 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq)
657 {
658 	void __iomem *addrbase;
659 	struct via_crdr_mmc_host *host;
660 	unsigned long flags;
661 	u16 status;
662 
663 	host = mmc_priv(mmc);
664 
665 	spin_lock_irqsave(&host->lock, flags);
666 
667 	addrbase = host->pcictrl_mmiobase;
668 	writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
669 
670 	status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
671 	status &= VIA_CRDR_SDSTS_W1C_MASK;
672 	writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
673 
674 	WARN_ON(host->mrq != NULL);
675 	host->mrq = mrq;
676 
677 	status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
678 	if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) {
679 		host->mrq->cmd->error = -ENOMEDIUM;
680 		tasklet_schedule(&host->finish_tasklet);
681 	} else {
682 		via_sdc_send_command(host, mrq->cmd);
683 	}
684 
685 	spin_unlock_irqrestore(&host->lock, flags);
686 }
687 
688 static void via_sdc_set_power(struct via_crdr_mmc_host *host,
689 			      unsigned short power, unsigned int on)
690 {
691 	unsigned long flags;
692 	u8 gatt;
693 
694 	spin_lock_irqsave(&host->lock, flags);
695 
696 	host->power = (1 << power);
697 
698 	gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
699 	if (host->power == MMC_VDD_165_195)
700 		gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
701 	else
702 		gatt |= VIA_CRDR_PCICLKGATT_3V3;
703 	if (on)
704 		gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON;
705 	else
706 		gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
707 	writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
708 
709 	spin_unlock_irqrestore(&host->lock, flags);
710 
711 	via_pwron_sleep(host);
712 }
713 
714 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
715 {
716 	struct via_crdr_mmc_host *host;
717 	unsigned long flags;
718 	void __iomem *addrbase;
719 	u32 org_data, sdextctrl;
720 	u8 clock;
721 
722 	host = mmc_priv(mmc);
723 
724 	spin_lock_irqsave(&host->lock, flags);
725 
726 	addrbase = host->sdhc_mmiobase;
727 	org_data = readl(addrbase + VIA_CRDR_SDBUSMODE);
728 	sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL);
729 
730 	if (ios->bus_width == MMC_BUS_WIDTH_1)
731 		org_data &= ~VIA_CRDR_SDMODE_4BIT;
732 	else
733 		org_data |= VIA_CRDR_SDMODE_4BIT;
734 
735 	if (ios->power_mode == MMC_POWER_OFF)
736 		org_data &= ~VIA_CRDR_SDMODE_CLK_ON;
737 	else
738 		org_data |= VIA_CRDR_SDMODE_CLK_ON;
739 
740 	if (ios->timing == MMC_TIMING_SD_HS)
741 		sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD;
742 	else
743 		sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD;
744 
745 	writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
746 	writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
747 
748 	if (ios->clock >= 48000000)
749 		clock = PCI_CLK_48M;
750 	else if (ios->clock >= 33000000)
751 		clock = PCI_CLK_33M;
752 	else if (ios->clock >= 24000000)
753 		clock = PCI_CLK_24M;
754 	else if (ios->clock >= 16000000)
755 		clock = PCI_CLK_16M;
756 	else if (ios->clock >= 12000000)
757 		clock = PCI_CLK_12M;
758 	else if (ios->clock >=  8000000)
759 		clock = PCI_CLK_8M;
760 	else
761 		clock = PCI_CLK_375K;
762 
763 	addrbase = host->pcictrl_mmiobase;
764 	if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock)
765 		writeb(clock, addrbase + VIA_CRDR_PCISDCCLK);
766 
767 	spin_unlock_irqrestore(&host->lock, flags);
768 
769 	if (ios->power_mode != MMC_POWER_OFF)
770 		via_sdc_set_power(host, ios->vdd, 1);
771 	else
772 		via_sdc_set_power(host, ios->vdd, 0);
773 }
774 
775 static int via_sdc_get_ro(struct mmc_host *mmc)
776 {
777 	struct via_crdr_mmc_host *host;
778 	unsigned long flags;
779 	u16 status;
780 
781 	host = mmc_priv(mmc);
782 
783 	spin_lock_irqsave(&host->lock, flags);
784 
785 	status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS);
786 
787 	spin_unlock_irqrestore(&host->lock, flags);
788 
789 	return !(status & VIA_CRDR_SDSTS_WP);
790 }
791 
792 static const struct mmc_host_ops via_sdc_ops = {
793 	.request = via_sdc_request,
794 	.set_ios = via_sdc_set_ios,
795 	.get_ro = via_sdc_get_ro,
796 };
797 
798 static void via_reset_pcictrl(struct via_crdr_mmc_host *host)
799 {
800 	unsigned long flags;
801 	u8 gatt;
802 
803 	spin_lock_irqsave(&host->lock, flags);
804 
805 	via_save_pcictrlreg(host);
806 	via_save_sdcreg(host);
807 
808 	spin_unlock_irqrestore(&host->lock, flags);
809 
810 	gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
811 	if (host->power == MMC_VDD_165_195)
812 		gatt &= VIA_CRDR_PCICLKGATT_3V3;
813 	else
814 		gatt |= VIA_CRDR_PCICLKGATT_3V3;
815 	writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
816 	via_pwron_sleep(host);
817 	gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
818 	writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
819 	msleep(3);
820 
821 	spin_lock_irqsave(&host->lock, flags);
822 
823 	via_restore_pcictrlreg(host);
824 	via_restore_sdcreg(host);
825 
826 	spin_unlock_irqrestore(&host->lock, flags);
827 }
828 
829 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask)
830 {
831 	BUG_ON(intmask == 0);
832 
833 	if (!host->cmd) {
834 		pr_err("%s: Got command interrupt 0x%x even "
835 		       "though no command operation was in progress.\n",
836 		       mmc_hostname(host->mmc), intmask);
837 		return;
838 	}
839 
840 	if (intmask & VIA_CRDR_SDSTS_CRTO)
841 		host->cmd->error = -ETIMEDOUT;
842 	else if (intmask & VIA_CRDR_SDSTS_SC)
843 		host->cmd->error = -EILSEQ;
844 
845 	if (host->cmd->error)
846 		tasklet_schedule(&host->finish_tasklet);
847 	else if (intmask & VIA_CRDR_SDSTS_CRD)
848 		via_sdc_finish_command(host);
849 }
850 
851 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask)
852 {
853 	BUG_ON(intmask == 0);
854 
855 	if (intmask & VIA_CRDR_SDSTS_DT)
856 		host->data->error = -ETIMEDOUT;
857 	else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC))
858 		host->data->error = -EILSEQ;
859 
860 	via_sdc_finish_data(host);
861 }
862 
863 static irqreturn_t via_sdc_isr(int irq, void *dev_id)
864 {
865 	struct via_crdr_mmc_host *sdhost = dev_id;
866 	void __iomem *addrbase;
867 	u8 pci_status;
868 	u16 sd_status;
869 	irqreturn_t result;
870 
871 	if (!sdhost)
872 		return IRQ_NONE;
873 
874 	spin_lock(&sdhost->lock);
875 
876 	addrbase = sdhost->pcictrl_mmiobase;
877 	pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS);
878 	if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) {
879 		result = IRQ_NONE;
880 		goto out;
881 	}
882 
883 	addrbase = sdhost->sdhc_mmiobase;
884 	sd_status = readw(addrbase + VIA_CRDR_SDSTATUS);
885 	sd_status &= VIA_CRDR_SDSTS_INT_MASK;
886 	sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK;
887 	if (!sd_status) {
888 		result = IRQ_NONE;
889 		goto out;
890 	}
891 
892 	if (sd_status & VIA_CRDR_SDSTS_CIR) {
893 		writew(sd_status & VIA_CRDR_SDSTS_CIR,
894 			addrbase + VIA_CRDR_SDSTATUS);
895 
896 		schedule_work(&sdhost->carddet_work);
897 	}
898 
899 	sd_status &= ~VIA_CRDR_SDSTS_CIR;
900 	if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) {
901 		writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK,
902 			addrbase + VIA_CRDR_SDSTATUS);
903 		via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK);
904 	}
905 	if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) {
906 		writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK,
907 			addrbase + VIA_CRDR_SDSTATUS);
908 		via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK);
909 	}
910 
911 	sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK);
912 	if (sd_status) {
913 		pr_err("%s: Unexpected interrupt 0x%x\n",
914 		       mmc_hostname(sdhost->mmc), sd_status);
915 		writew(sd_status, addrbase + VIA_CRDR_SDSTATUS);
916 	}
917 
918 	result = IRQ_HANDLED;
919 
920 out:
921 	spin_unlock(&sdhost->lock);
922 
923 	return result;
924 }
925 
926 static void via_sdc_timeout(struct timer_list *t)
927 {
928 	struct via_crdr_mmc_host *sdhost;
929 	unsigned long flags;
930 
931 	sdhost = from_timer(sdhost, t, timer);
932 
933 	spin_lock_irqsave(&sdhost->lock, flags);
934 
935 	if (sdhost->mrq) {
936 		pr_err("%s: Timeout waiting for hardware interrupt."
937 		       "cmd:0x%x\n", mmc_hostname(sdhost->mmc),
938 		       sdhost->mrq->cmd->opcode);
939 
940 		if (sdhost->data) {
941 			writel(VIA_CRDR_DMACTRL_SFTRST,
942 				sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
943 			sdhost->data->error = -ETIMEDOUT;
944 			via_sdc_finish_data(sdhost);
945 		} else {
946 			if (sdhost->cmd)
947 				sdhost->cmd->error = -ETIMEDOUT;
948 			else
949 				sdhost->mrq->cmd->error = -ETIMEDOUT;
950 			tasklet_schedule(&sdhost->finish_tasklet);
951 		}
952 	}
953 
954 	spin_unlock_irqrestore(&sdhost->lock, flags);
955 }
956 
957 static void via_sdc_tasklet_finish(unsigned long param)
958 {
959 	struct via_crdr_mmc_host *host;
960 	unsigned long flags;
961 	struct mmc_request *mrq;
962 
963 	host = (struct via_crdr_mmc_host *)param;
964 
965 	spin_lock_irqsave(&host->lock, flags);
966 
967 	del_timer(&host->timer);
968 	mrq = host->mrq;
969 	host->mrq = NULL;
970 	host->cmd = NULL;
971 	host->data = NULL;
972 
973 	spin_unlock_irqrestore(&host->lock, flags);
974 
975 	mmc_request_done(host->mmc, mrq);
976 }
977 
978 static void via_sdc_card_detect(struct work_struct *work)
979 {
980 	struct via_crdr_mmc_host *host;
981 	void __iomem *addrbase;
982 	unsigned long flags;
983 	u16 status;
984 
985 	host = container_of(work, struct via_crdr_mmc_host, carddet_work);
986 
987 	addrbase = host->ddma_mmiobase;
988 	writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
989 
990 	spin_lock_irqsave(&host->lock, flags);
991 
992 	addrbase = host->pcictrl_mmiobase;
993 	writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK);
994 
995 	addrbase = host->sdhc_mmiobase;
996 	status = readw(addrbase + VIA_CRDR_SDSTATUS);
997 	if (!(status & VIA_CRDR_SDSTS_SLOTG)) {
998 		if (host->mrq) {
999 			pr_err("%s: Card removed during transfer!\n",
1000 			       mmc_hostname(host->mmc));
1001 			host->mrq->cmd->error = -ENOMEDIUM;
1002 			tasklet_schedule(&host->finish_tasklet);
1003 		}
1004 
1005 		spin_unlock_irqrestore(&host->lock, flags);
1006 
1007 		via_reset_pcictrl(host);
1008 
1009 		spin_lock_irqsave(&host->lock, flags);
1010 	}
1011 
1012 	spin_unlock_irqrestore(&host->lock, flags);
1013 
1014 	via_print_pcictrl(host);
1015 	via_print_sdchc(host);
1016 
1017 	mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1018 }
1019 
1020 static void via_init_mmc_host(struct via_crdr_mmc_host *host)
1021 {
1022 	struct mmc_host *mmc = host->mmc;
1023 	void __iomem *addrbase;
1024 	u32 lenreg;
1025 	u32 status;
1026 
1027 	timer_setup(&host->timer, via_sdc_timeout, 0);
1028 
1029 	spin_lock_init(&host->lock);
1030 
1031 	mmc->f_min = VIA_CRDR_MIN_CLOCK;
1032 	mmc->f_max = VIA_CRDR_MAX_CLOCK;
1033 	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1034 	mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
1035 	mmc->ops = &via_sdc_ops;
1036 
1037 	/*Hardware cannot do scatter lists*/
1038 	mmc->max_segs = 1;
1039 
1040 	mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH;
1041 	mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT;
1042 
1043 	mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
1044 	mmc->max_req_size = mmc->max_seg_size;
1045 
1046 	INIT_WORK(&host->carddet_work, via_sdc_card_detect);
1047 
1048 	tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish,
1049 		     (unsigned long)host);
1050 
1051 	addrbase = host->sdhc_mmiobase;
1052 	writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1053 	msleep(1);
1054 
1055 	lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1056 	writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1057 
1058 	status = readw(addrbase + VIA_CRDR_SDSTATUS);
1059 	status &= VIA_CRDR_SDSTS_W1C_MASK;
1060 	writew(status, addrbase + VIA_CRDR_SDSTATUS);
1061 
1062 	status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1063 	status |= VIA_CRDR_SDSTS_CFE;
1064 	writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1065 
1066 	writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL);
1067 
1068 	writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
1069 	msleep(1);
1070 }
1071 
1072 static int via_sd_probe(struct pci_dev *pcidev,
1073 				    const struct pci_device_id *id)
1074 {
1075 	struct mmc_host *mmc;
1076 	struct via_crdr_mmc_host *sdhost;
1077 	u32 base, len;
1078 	u8  gatt;
1079 	int ret;
1080 
1081 	pr_info(DRV_NAME
1082 		": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n",
1083 		pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1084 		(int)pcidev->revision);
1085 
1086 	ret = pci_enable_device(pcidev);
1087 	if (ret)
1088 		return ret;
1089 
1090 	ret = pci_request_regions(pcidev, DRV_NAME);
1091 	if (ret)
1092 		goto disable;
1093 
1094 	pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0);
1095 	pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0);
1096 
1097 	mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev);
1098 	if (!mmc) {
1099 		ret = -ENOMEM;
1100 		goto release;
1101 	}
1102 
1103 	sdhost = mmc_priv(mmc);
1104 	sdhost->mmc = mmc;
1105 	dev_set_drvdata(&pcidev->dev, sdhost);
1106 
1107 	len = pci_resource_len(pcidev, 0);
1108 	base = pci_resource_start(pcidev, 0);
1109 	sdhost->mmiobase = ioremap(base, len);
1110 	if (!sdhost->mmiobase) {
1111 		ret = -ENOMEM;
1112 		goto free_mmc_host;
1113 	}
1114 
1115 	sdhost->sdhc_mmiobase =
1116 		sdhost->mmiobase + VIA_CRDR_SDC_OFF;
1117 	sdhost->ddma_mmiobase =
1118 		sdhost->mmiobase + VIA_CRDR_DDMA_OFF;
1119 	sdhost->pcictrl_mmiobase =
1120 		sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF;
1121 
1122 	sdhost->power = MMC_VDD_165_195;
1123 
1124 	gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON;
1125 	writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1126 	via_pwron_sleep(sdhost);
1127 	gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1128 	writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1129 	msleep(3);
1130 
1131 	via_init_mmc_host(sdhost);
1132 
1133 	ret =
1134 	    request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME,
1135 			sdhost);
1136 	if (ret)
1137 		goto unmap;
1138 
1139 	writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN,
1140 	       sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1141 	writeb(VIA_CRDR_PCITMOCTRL_1024MS,
1142 	       sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL);
1143 
1144 	/* device-specific quirks */
1145 	if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
1146 	    pcidev->subsystem_device == 0x3891)
1147 		sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY;
1148 
1149 	mmc_add_host(mmc);
1150 
1151 	return 0;
1152 
1153 unmap:
1154 	iounmap(sdhost->mmiobase);
1155 free_mmc_host:
1156 	dev_set_drvdata(&pcidev->dev, NULL);
1157 	mmc_free_host(mmc);
1158 release:
1159 	pci_release_regions(pcidev);
1160 disable:
1161 	pci_disable_device(pcidev);
1162 
1163 	return ret;
1164 }
1165 
1166 static void via_sd_remove(struct pci_dev *pcidev)
1167 {
1168 	struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev);
1169 	unsigned long flags;
1170 	u8 gatt;
1171 
1172 	spin_lock_irqsave(&sdhost->lock, flags);
1173 
1174 	/* Ensure we don't accept more commands from mmc layer */
1175 	sdhost->reject = 1;
1176 
1177 	/* Disable generating further interrupts */
1178 	writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL);
1179 
1180 	if (sdhost->mrq) {
1181 		pr_err("%s: Controller removed during "
1182 			"transfer\n", mmc_hostname(sdhost->mmc));
1183 
1184 		/* make sure all DMA is stopped */
1185 		writel(VIA_CRDR_DMACTRL_SFTRST,
1186 			sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL);
1187 		sdhost->mrq->cmd->error = -ENOMEDIUM;
1188 		if (sdhost->mrq->stop)
1189 			sdhost->mrq->stop->error = -ENOMEDIUM;
1190 		tasklet_schedule(&sdhost->finish_tasklet);
1191 	}
1192 	spin_unlock_irqrestore(&sdhost->lock, flags);
1193 
1194 	mmc_remove_host(sdhost->mmc);
1195 
1196 	free_irq(pcidev->irq, sdhost);
1197 
1198 	del_timer_sync(&sdhost->timer);
1199 
1200 	tasklet_kill(&sdhost->finish_tasklet);
1201 
1202 	/* switch off power */
1203 	gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1204 	gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON;
1205 	writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1206 
1207 	iounmap(sdhost->mmiobase);
1208 	dev_set_drvdata(&pcidev->dev, NULL);
1209 	mmc_free_host(sdhost->mmc);
1210 	pci_release_regions(pcidev);
1211 	pci_disable_device(pcidev);
1212 
1213 	pr_info(DRV_NAME
1214 		": VIA SDMMC controller at %s [%04x:%04x] has been removed\n",
1215 		pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1216 }
1217 
1218 #ifdef CONFIG_PM
1219 
1220 static void via_init_sdc_pm(struct via_crdr_mmc_host *host)
1221 {
1222 	struct sdhcreg *pm_sdhcreg;
1223 	void __iomem *addrbase;
1224 	u32 lenreg;
1225 	u16 status;
1226 
1227 	pm_sdhcreg = &(host->pm_sdhc_reg);
1228 	addrbase = host->sdhc_mmiobase;
1229 
1230 	writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
1231 
1232 	lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN;
1233 	writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
1234 
1235 	status = readw(addrbase + VIA_CRDR_SDSTATUS);
1236 	status &= VIA_CRDR_SDSTS_W1C_MASK;
1237 	writew(status, addrbase + VIA_CRDR_SDSTATUS);
1238 
1239 	status = readw(addrbase + VIA_CRDR_SDSTATUS2);
1240 	status |= VIA_CRDR_SDSTS_CFE;
1241 	writew(status, addrbase + VIA_CRDR_SDSTATUS2);
1242 
1243 	writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
1244 	writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
1245 	writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
1246 	writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
1247 	writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
1248 	writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
1249 
1250 	via_print_pcictrl(host);
1251 	via_print_sdchc(host);
1252 }
1253 
1254 static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state)
1255 {
1256 	struct via_crdr_mmc_host *host;
1257 
1258 	host = pci_get_drvdata(pcidev);
1259 
1260 	via_save_pcictrlreg(host);
1261 	via_save_sdcreg(host);
1262 
1263 	pci_save_state(pcidev);
1264 	pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1265 	pci_disable_device(pcidev);
1266 	pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1267 
1268 	return 0;
1269 }
1270 
1271 static int via_sd_resume(struct pci_dev *pcidev)
1272 {
1273 	struct via_crdr_mmc_host *sdhost;
1274 	int ret = 0;
1275 	u8 gatt;
1276 
1277 	sdhost = pci_get_drvdata(pcidev);
1278 
1279 	gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON;
1280 	if (sdhost->power == MMC_VDD_165_195)
1281 		gatt &= ~VIA_CRDR_PCICLKGATT_3V3;
1282 	else
1283 		gatt |= VIA_CRDR_PCICLKGATT_3V3;
1284 	writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1285 	via_pwron_sleep(sdhost);
1286 	gatt |= VIA_CRDR_PCICLKGATT_SFTRST;
1287 	writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT);
1288 	msleep(3);
1289 
1290 	msleep(100);
1291 
1292 	pci_set_power_state(pcidev, PCI_D0);
1293 	pci_restore_state(pcidev);
1294 	ret = pci_enable_device(pcidev);
1295 	if (ret)
1296 		return ret;
1297 
1298 	via_restore_pcictrlreg(sdhost);
1299 	via_init_sdc_pm(sdhost);
1300 
1301 	return ret;
1302 }
1303 
1304 #else /* CONFIG_PM */
1305 
1306 #define via_sd_suspend NULL
1307 #define via_sd_resume NULL
1308 
1309 #endif /* CONFIG_PM */
1310 
1311 static struct pci_driver via_sd_driver = {
1312 	.name = DRV_NAME,
1313 	.id_table = via_ids,
1314 	.probe = via_sd_probe,
1315 	.remove = via_sd_remove,
1316 	.suspend = via_sd_suspend,
1317 	.resume = via_sd_resume,
1318 };
1319 
1320 module_pci_driver(via_sd_driver);
1321 
1322 MODULE_LICENSE("GPL");
1323 MODULE_AUTHOR("VIA Technologies Inc.");
1324 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver");
1325