1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // flexcan.c - FLEXCAN CAN controller driver 4 // 5 // Copyright (c) 2005-2006 Varma Electronics Oy 6 // Copyright (c) 2009 Sascha Hauer, Pengutronix 7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> 8 // Copyright (c) 2014 David Jander, Protonic Holland 9 // 10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com> 11 12 #include <dt-bindings/firmware/imx/rsrc.h> 13 #include <linux/bitfield.h> 14 #include <linux/can.h> 15 #include <linux/can/dev.h> 16 #include <linux/can/error.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/firmware/imx/sci.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/module.h> 24 #include <linux/netdevice.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/platform_device.h> 29 #include <linux/can/platform/flexcan.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/regmap.h> 32 #include <linux/regulator/consumer.h> 33 34 #include "flexcan.h" 35 36 #define DRV_NAME "flexcan" 37 38 /* 8 for RX fifo and 2 error handling */ 39 #define FLEXCAN_NAPI_WEIGHT (8 + 2) 40 41 /* FLEXCAN module configuration register (CANMCR) bits */ 42 #define FLEXCAN_MCR_MDIS BIT(31) 43 #define FLEXCAN_MCR_FRZ BIT(30) 44 #define FLEXCAN_MCR_FEN BIT(29) 45 #define FLEXCAN_MCR_HALT BIT(28) 46 #define FLEXCAN_MCR_NOT_RDY BIT(27) 47 #define FLEXCAN_MCR_WAK_MSK BIT(26) 48 #define FLEXCAN_MCR_SOFTRST BIT(25) 49 #define FLEXCAN_MCR_FRZ_ACK BIT(24) 50 #define FLEXCAN_MCR_SUPV BIT(23) 51 #define FLEXCAN_MCR_SLF_WAK BIT(22) 52 #define FLEXCAN_MCR_WRN_EN BIT(21) 53 #define FLEXCAN_MCR_LPM_ACK BIT(20) 54 #define FLEXCAN_MCR_WAK_SRC BIT(19) 55 #define FLEXCAN_MCR_DOZE BIT(18) 56 #define FLEXCAN_MCR_SRX_DIS BIT(17) 57 #define FLEXCAN_MCR_IRMQ BIT(16) 58 #define FLEXCAN_MCR_LPRIO_EN BIT(13) 59 #define FLEXCAN_MCR_AEN BIT(12) 60 #define FLEXCAN_MCR_FDEN BIT(11) 61 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */ 62 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f) 63 #define FLEXCAN_MCR_IDAM_A (0x0 << 8) 64 #define FLEXCAN_MCR_IDAM_B (0x1 << 8) 65 #define FLEXCAN_MCR_IDAM_C (0x2 << 8) 66 #define FLEXCAN_MCR_IDAM_D (0x3 << 8) 67 68 /* FLEXCAN control register (CANCTRL) bits */ 69 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 70 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 71 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 72 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 73 #define FLEXCAN_CTRL_BOFF_MSK BIT(15) 74 #define FLEXCAN_CTRL_ERR_MSK BIT(14) 75 #define FLEXCAN_CTRL_CLK_SRC BIT(13) 76 #define FLEXCAN_CTRL_LPB BIT(12) 77 #define FLEXCAN_CTRL_TWRN_MSK BIT(11) 78 #define FLEXCAN_CTRL_RWRN_MSK BIT(10) 79 #define FLEXCAN_CTRL_SMP BIT(7) 80 #define FLEXCAN_CTRL_BOFF_REC BIT(6) 81 #define FLEXCAN_CTRL_TSYN BIT(5) 82 #define FLEXCAN_CTRL_LBUF BIT(4) 83 #define FLEXCAN_CTRL_LOM BIT(3) 84 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 85 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 86 #define FLEXCAN_CTRL_ERR_STATE \ 87 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 88 FLEXCAN_CTRL_BOFF_MSK) 89 #define FLEXCAN_CTRL_ERR_ALL \ 90 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 91 92 /* FLEXCAN control register 2 (CTRL2) bits */ 93 #define FLEXCAN_CTRL2_ECRWRE BIT(29) 94 #define FLEXCAN_CTRL2_WRMFRZ BIT(28) 95 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24) 96 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19) 97 #define FLEXCAN_CTRL2_MRP BIT(18) 98 #define FLEXCAN_CTRL2_RRS BIT(17) 99 #define FLEXCAN_CTRL2_EACEN BIT(16) 100 #define FLEXCAN_CTRL2_ISOCANFDEN BIT(12) 101 102 /* FLEXCAN memory error control register (MECR) bits */ 103 #define FLEXCAN_MECR_ECRWRDIS BIT(31) 104 #define FLEXCAN_MECR_HANCEI_MSK BIT(19) 105 #define FLEXCAN_MECR_FANCEI_MSK BIT(18) 106 #define FLEXCAN_MECR_CEI_MSK BIT(16) 107 #define FLEXCAN_MECR_HAERRIE BIT(15) 108 #define FLEXCAN_MECR_FAERRIE BIT(14) 109 #define FLEXCAN_MECR_EXTERRIE BIT(13) 110 #define FLEXCAN_MECR_RERRDIS BIT(9) 111 #define FLEXCAN_MECR_ECCDIS BIT(8) 112 #define FLEXCAN_MECR_NCEFAFRZ BIT(7) 113 114 /* FLEXCAN error and status register (ESR) bits */ 115 #define FLEXCAN_ESR_TWRN_INT BIT(17) 116 #define FLEXCAN_ESR_RWRN_INT BIT(16) 117 #define FLEXCAN_ESR_BIT1_ERR BIT(15) 118 #define FLEXCAN_ESR_BIT0_ERR BIT(14) 119 #define FLEXCAN_ESR_ACK_ERR BIT(13) 120 #define FLEXCAN_ESR_CRC_ERR BIT(12) 121 #define FLEXCAN_ESR_FRM_ERR BIT(11) 122 #define FLEXCAN_ESR_STF_ERR BIT(10) 123 #define FLEXCAN_ESR_TX_WRN BIT(9) 124 #define FLEXCAN_ESR_RX_WRN BIT(8) 125 #define FLEXCAN_ESR_IDLE BIT(7) 126 #define FLEXCAN_ESR_TXRX BIT(6) 127 #define FLEXCAN_EST_FLT_CONF_SHIFT (4) 128 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 129 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 130 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 131 #define FLEXCAN_ESR_BOFF_INT BIT(2) 132 #define FLEXCAN_ESR_ERR_INT BIT(1) 133 #define FLEXCAN_ESR_WAK_INT BIT(0) 134 #define FLEXCAN_ESR_ERR_BUS \ 135 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 136 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 137 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 138 #define FLEXCAN_ESR_ERR_STATE \ 139 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 140 #define FLEXCAN_ESR_ERR_ALL \ 141 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 142 #define FLEXCAN_ESR_ALL_INT \ 143 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 144 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 145 146 /* FLEXCAN Bit Timing register (CBT) bits */ 147 #define FLEXCAN_CBT_BTF BIT(31) 148 #define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21) 149 #define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16) 150 #define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10) 151 #define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5) 152 #define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0) 153 154 /* FLEXCAN FD control register (FDCTRL) bits */ 155 #define FLEXCAN_FDCTRL_FDRATE BIT(31) 156 #define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19) 157 #define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16) 158 #define FLEXCAN_FDCTRL_MBDSR_8 0x0 159 #define FLEXCAN_FDCTRL_MBDSR_12 0x1 160 #define FLEXCAN_FDCTRL_MBDSR_32 0x2 161 #define FLEXCAN_FDCTRL_MBDSR_64 0x3 162 #define FLEXCAN_FDCTRL_TDCEN BIT(15) 163 #define FLEXCAN_FDCTRL_TDCFAIL BIT(14) 164 #define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8) 165 #define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0) 166 167 /* FLEXCAN FD Bit Timing register (FDCBT) bits */ 168 #define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20) 169 #define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16) 170 #define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10) 171 #define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5) 172 #define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0) 173 174 /* FLEXCAN interrupt flag register (IFLAG) bits */ 175 /* Errata ERR005829 step7: Reserve first valid MB */ 176 #define FLEXCAN_TX_MB_RESERVED_RX_FIFO 8 177 #define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX 0 178 #define FLEXCAN_RX_MB_RX_MAILBOX_FIRST (FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1) 179 #define FLEXCAN_IFLAG_MB(x) BIT_ULL(x) 180 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 181 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 182 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 183 184 /* FLEXCAN message buffers */ 185 #define FLEXCAN_MB_CODE_MASK (0xf << 24) 186 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24) 187 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) 188 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) 189 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) 190 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24) 191 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) 192 193 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) 194 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) 195 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) 196 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) 197 198 #define FLEXCAN_MB_CNT_EDL BIT(31) 199 #define FLEXCAN_MB_CNT_BRS BIT(30) 200 #define FLEXCAN_MB_CNT_ESI BIT(29) 201 #define FLEXCAN_MB_CNT_SRR BIT(22) 202 #define FLEXCAN_MB_CNT_IDE BIT(21) 203 #define FLEXCAN_MB_CNT_RTR BIT(20) 204 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 205 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 206 207 #define FLEXCAN_TIMEOUT_US (250) 208 209 /* Structure of the message buffer */ 210 struct flexcan_mb { 211 u32 can_ctrl; 212 u32 can_id; 213 u32 data[]; 214 }; 215 216 /* Structure of the hardware registers */ 217 struct flexcan_regs { 218 u32 mcr; /* 0x00 */ 219 u32 ctrl; /* 0x04 - Not affected by Soft Reset */ 220 u32 timer; /* 0x08 */ 221 u32 tcr; /* 0x0c */ 222 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */ 223 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */ 224 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */ 225 u32 ecr; /* 0x1c */ 226 u32 esr; /* 0x20 */ 227 u32 imask2; /* 0x24 */ 228 u32 imask1; /* 0x28 */ 229 u32 iflag2; /* 0x2c */ 230 u32 iflag1; /* 0x30 */ 231 union { /* 0x34 */ 232 u32 gfwr_mx28; /* MX28, MX53 */ 233 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */ 234 }; 235 u32 esr2; /* 0x38 */ 236 u32 imeur; /* 0x3c */ 237 u32 lrfr; /* 0x40 */ 238 u32 crcr; /* 0x44 */ 239 u32 rxfgmask; /* 0x48 */ 240 u32 rxfir; /* 0x4c - Not affected by Soft Reset */ 241 u32 cbt; /* 0x50 - Not affected by Soft Reset */ 242 u32 _reserved2; /* 0x54 */ 243 u32 dbg1; /* 0x58 */ 244 u32 dbg2; /* 0x5c */ 245 u32 _reserved3[8]; /* 0x60 */ 246 struct_group(init, 247 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */ 248 /* FIFO-mode: 249 * MB 250 * 0x080...0x08f 0 RX message buffer 251 * 0x090...0x0df 1-5 reserved 252 * 0x0e0...0x0ff 6-7 8 entry ID table 253 * (mx25, mx28, mx35, mx53) 254 * 0x0e0...0x2df 6-7..37 8..128 entry ID table 255 * size conf'ed via ctrl2::RFFN 256 * (mx6, vf610) 257 */ 258 u32 _reserved4[256]; /* 0x480 */ 259 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */ 260 u32 _reserved5[24]; /* 0x980 */ 261 u32 gfwr_mx6; /* 0x9e0 - MX6 */ 262 u32 _reserved6[39]; /* 0x9e4 */ 263 u32 _rxfir[6]; /* 0xa80 */ 264 u32 _reserved8[2]; /* 0xa98 */ 265 u32 _rxmgmask; /* 0xaa0 */ 266 u32 _rxfgmask; /* 0xaa4 */ 267 u32 _rx14mask; /* 0xaa8 */ 268 u32 _rx15mask; /* 0xaac */ 269 u32 tx_smb[4]; /* 0xab0 */ 270 u32 rx_smb0[4]; /* 0xac0 */ 271 u32 rx_smb1[4]; /* 0xad0 */ 272 ); 273 u32 mecr; /* 0xae0 */ 274 u32 erriar; /* 0xae4 */ 275 u32 erridpr; /* 0xae8 */ 276 u32 errippr; /* 0xaec */ 277 u32 rerrar; /* 0xaf0 */ 278 u32 rerrdr; /* 0xaf4 */ 279 u32 rerrsynr; /* 0xaf8 */ 280 u32 errsr; /* 0xafc */ 281 u32 _reserved7[64]; /* 0xb00 */ 282 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */ 283 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */ 284 u32 fdcrc; /* 0xc08 */ 285 u32 _reserved9[199]; /* 0xc0c */ 286 struct_group(init_fd, 287 u32 tx_smb_fd[18]; /* 0xf28 */ 288 u32 rx_smb0_fd[18]; /* 0xf70 */ 289 u32 rx_smb1_fd[18]; /* 0xfb8 */ 290 ); 291 }; 292 293 static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8); 294 295 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = { 296 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE | 297 FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 | 298 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 299 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 300 }; 301 302 static const struct flexcan_devtype_data fsl_p1010_devtype_data = { 303 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE | 304 FLEXCAN_QUIRK_BROKEN_PERR_STATE | 305 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN | 306 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 307 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 308 }; 309 310 static const struct flexcan_devtype_data fsl_imx25_devtype_data = { 311 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE | 312 FLEXCAN_QUIRK_BROKEN_PERR_STATE | 313 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 314 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 315 }; 316 317 static const struct flexcan_devtype_data fsl_imx28_devtype_data = { 318 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE | 319 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 320 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 321 }; 322 323 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = { 324 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 325 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 326 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR | 327 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 328 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 329 }; 330 331 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = { 332 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 333 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 334 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW | 335 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 336 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 337 }; 338 339 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = { 340 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 341 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 342 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR | 343 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC | 344 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 345 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 346 }; 347 348 static const struct flexcan_devtype_data fsl_vf610_devtype_data = { 349 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 350 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 351 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC | 352 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 353 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 354 }; 355 356 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = { 357 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 358 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX | 359 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 360 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 361 }; 362 363 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = { 364 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 365 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 366 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD | 367 FLEXCAN_QUIRK_SUPPORT_ECC | 368 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 369 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 370 }; 371 372 static const struct can_bittiming_const flexcan_bittiming_const = { 373 .name = DRV_NAME, 374 .tseg1_min = 4, 375 .tseg1_max = 16, 376 .tseg2_min = 2, 377 .tseg2_max = 8, 378 .sjw_max = 4, 379 .brp_min = 1, 380 .brp_max = 256, 381 .brp_inc = 1, 382 }; 383 384 static const struct can_bittiming_const flexcan_fd_bittiming_const = { 385 .name = DRV_NAME, 386 .tseg1_min = 2, 387 .tseg1_max = 96, 388 .tseg2_min = 2, 389 .tseg2_max = 32, 390 .sjw_max = 16, 391 .brp_min = 1, 392 .brp_max = 1024, 393 .brp_inc = 1, 394 }; 395 396 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = { 397 .name = DRV_NAME, 398 .tseg1_min = 2, 399 .tseg1_max = 39, 400 .tseg2_min = 2, 401 .tseg2_max = 8, 402 .sjw_max = 4, 403 .brp_min = 1, 404 .brp_max = 1024, 405 .brp_inc = 1, 406 }; 407 408 /* FlexCAN module is essentially modelled as a little-endian IP in most 409 * SoCs, i.e the registers as well as the message buffer areas are 410 * implemented in a little-endian fashion. 411 * 412 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN 413 * module in a big-endian fashion (i.e the registers as well as the 414 * message buffer areas are implemented in a big-endian way). 415 * 416 * In addition, the FlexCAN module can be found on SoCs having ARM or 417 * PPC cores. So, we need to abstract off the register read/write 418 * functions, ensuring that these cater to all the combinations of module 419 * endianness and underlying CPU endianness. 420 */ 421 static inline u32 flexcan_read_be(void __iomem *addr) 422 { 423 return ioread32be(addr); 424 } 425 426 static inline void flexcan_write_be(u32 val, void __iomem *addr) 427 { 428 iowrite32be(val, addr); 429 } 430 431 static inline u32 flexcan_read_le(void __iomem *addr) 432 { 433 return ioread32(addr); 434 } 435 436 static inline void flexcan_write_le(u32 val, void __iomem *addr) 437 { 438 iowrite32(val, addr); 439 } 440 441 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv, 442 u8 mb_index) 443 { 444 u8 bank_size; 445 bool bank; 446 447 if (WARN_ON(mb_index >= priv->mb_count)) 448 return NULL; 449 450 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size; 451 452 bank = mb_index >= bank_size; 453 if (bank) 454 mb_index -= bank_size; 455 456 return (struct flexcan_mb __iomem *) 457 (&priv->regs->mb[bank][priv->mb_size * mb_index]); 458 } 459 460 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv) 461 { 462 struct flexcan_regs __iomem *regs = priv->regs; 463 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 464 465 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 466 udelay(10); 467 468 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 469 return -ETIMEDOUT; 470 471 return 0; 472 } 473 474 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv) 475 { 476 struct flexcan_regs __iomem *regs = priv->regs; 477 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 478 479 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 480 udelay(10); 481 482 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) 483 return -ETIMEDOUT; 484 485 return 0; 486 } 487 488 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable) 489 { 490 struct flexcan_regs __iomem *regs = priv->regs; 491 u32 reg_mcr; 492 493 reg_mcr = priv->read(®s->mcr); 494 495 if (enable) 496 reg_mcr |= FLEXCAN_MCR_WAK_MSK; 497 else 498 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK; 499 500 priv->write(reg_mcr, ®s->mcr); 501 } 502 503 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled) 504 { 505 u8 idx = priv->scu_idx; 506 u32 rsrc_id, val; 507 508 rsrc_id = IMX_SC_R_CAN(idx); 509 510 if (enabled) 511 val = 1; 512 else 513 val = 0; 514 515 /* stop mode request via scu firmware */ 516 return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id, 517 IMX_SC_C_IPG_STOP, val); 518 } 519 520 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv) 521 { 522 struct flexcan_regs __iomem *regs = priv->regs; 523 u32 reg_mcr; 524 int ret; 525 526 reg_mcr = priv->read(®s->mcr); 527 reg_mcr |= FLEXCAN_MCR_SLF_WAK; 528 priv->write(reg_mcr, ®s->mcr); 529 530 /* enable stop request */ 531 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) { 532 ret = flexcan_stop_mode_enable_scfw(priv, true); 533 if (ret < 0) 534 return ret; 535 } else { 536 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, 537 1 << priv->stm.req_bit, 1 << priv->stm.req_bit); 538 } 539 540 return flexcan_low_power_enter_ack(priv); 541 } 542 543 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv) 544 { 545 struct flexcan_regs __iomem *regs = priv->regs; 546 u32 reg_mcr; 547 int ret; 548 549 /* remove stop request */ 550 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) { 551 ret = flexcan_stop_mode_enable_scfw(priv, false); 552 if (ret < 0) 553 return ret; 554 } else { 555 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, 556 1 << priv->stm.req_bit, 0); 557 } 558 559 reg_mcr = priv->read(®s->mcr); 560 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK; 561 priv->write(reg_mcr, ®s->mcr); 562 563 return flexcan_low_power_exit_ack(priv); 564 } 565 566 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv) 567 { 568 struct flexcan_regs __iomem *regs = priv->regs; 569 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK); 570 571 priv->write(reg_ctrl, ®s->ctrl); 572 } 573 574 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv) 575 { 576 struct flexcan_regs __iomem *regs = priv->regs; 577 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK); 578 579 priv->write(reg_ctrl, ®s->ctrl); 580 } 581 582 static int flexcan_clks_enable(const struct flexcan_priv *priv) 583 { 584 int err = 0; 585 586 if (priv->clk_ipg) { 587 err = clk_prepare_enable(priv->clk_ipg); 588 if (err) 589 return err; 590 } 591 592 if (priv->clk_per) { 593 err = clk_prepare_enable(priv->clk_per); 594 if (err) 595 clk_disable_unprepare(priv->clk_ipg); 596 } 597 598 return err; 599 } 600 601 static void flexcan_clks_disable(const struct flexcan_priv *priv) 602 { 603 clk_disable_unprepare(priv->clk_per); 604 clk_disable_unprepare(priv->clk_ipg); 605 } 606 607 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) 608 { 609 if (!priv->reg_xceiver) 610 return 0; 611 612 return regulator_enable(priv->reg_xceiver); 613 } 614 615 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) 616 { 617 if (!priv->reg_xceiver) 618 return 0; 619 620 return regulator_disable(priv->reg_xceiver); 621 } 622 623 static int flexcan_chip_enable(struct flexcan_priv *priv) 624 { 625 struct flexcan_regs __iomem *regs = priv->regs; 626 u32 reg; 627 628 reg = priv->read(®s->mcr); 629 reg &= ~FLEXCAN_MCR_MDIS; 630 priv->write(reg, ®s->mcr); 631 632 return flexcan_low_power_exit_ack(priv); 633 } 634 635 static int flexcan_chip_disable(struct flexcan_priv *priv) 636 { 637 struct flexcan_regs __iomem *regs = priv->regs; 638 u32 reg; 639 640 reg = priv->read(®s->mcr); 641 reg |= FLEXCAN_MCR_MDIS; 642 priv->write(reg, ®s->mcr); 643 644 return flexcan_low_power_enter_ack(priv); 645 } 646 647 static int flexcan_chip_freeze(struct flexcan_priv *priv) 648 { 649 struct flexcan_regs __iomem *regs = priv->regs; 650 unsigned int timeout; 651 u32 bitrate = priv->can.bittiming.bitrate; 652 u32 reg; 653 654 if (bitrate) 655 timeout = 1000 * 1000 * 10 / bitrate; 656 else 657 timeout = FLEXCAN_TIMEOUT_US / 10; 658 659 reg = priv->read(®s->mcr); 660 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT; 661 priv->write(reg, ®s->mcr); 662 663 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 664 udelay(100); 665 666 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 667 return -ETIMEDOUT; 668 669 return 0; 670 } 671 672 static int flexcan_chip_unfreeze(struct flexcan_priv *priv) 673 { 674 struct flexcan_regs __iomem *regs = priv->regs; 675 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 676 u32 reg; 677 678 reg = priv->read(®s->mcr); 679 reg &= ~FLEXCAN_MCR_HALT; 680 priv->write(reg, ®s->mcr); 681 682 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 683 udelay(10); 684 685 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) 686 return -ETIMEDOUT; 687 688 return 0; 689 } 690 691 static int flexcan_chip_softreset(struct flexcan_priv *priv) 692 { 693 struct flexcan_regs __iomem *regs = priv->regs; 694 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 695 696 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 697 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) 698 udelay(10); 699 700 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST) 701 return -ETIMEDOUT; 702 703 return 0; 704 } 705 706 static int __flexcan_get_berr_counter(const struct net_device *dev, 707 struct can_berr_counter *bec) 708 { 709 const struct flexcan_priv *priv = netdev_priv(dev); 710 struct flexcan_regs __iomem *regs = priv->regs; 711 u32 reg = priv->read(®s->ecr); 712 713 bec->txerr = (reg >> 0) & 0xff; 714 bec->rxerr = (reg >> 8) & 0xff; 715 716 return 0; 717 } 718 719 static int flexcan_get_berr_counter(const struct net_device *dev, 720 struct can_berr_counter *bec) 721 { 722 const struct flexcan_priv *priv = netdev_priv(dev); 723 int err; 724 725 err = pm_runtime_resume_and_get(priv->dev); 726 if (err < 0) 727 return err; 728 729 err = __flexcan_get_berr_counter(dev, bec); 730 731 pm_runtime_put(priv->dev); 732 733 return err; 734 } 735 736 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 737 { 738 const struct flexcan_priv *priv = netdev_priv(dev); 739 struct canfd_frame *cfd = (struct canfd_frame *)skb->data; 740 u32 can_id; 741 u32 data; 742 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16); 743 int i; 744 745 if (can_dev_dropped_skb(dev, skb)) 746 return NETDEV_TX_OK; 747 748 netif_stop_queue(dev); 749 750 if (cfd->can_id & CAN_EFF_FLAG) { 751 can_id = cfd->can_id & CAN_EFF_MASK; 752 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 753 } else { 754 can_id = (cfd->can_id & CAN_SFF_MASK) << 18; 755 } 756 757 if (cfd->can_id & CAN_RTR_FLAG) 758 ctrl |= FLEXCAN_MB_CNT_RTR; 759 760 if (can_is_canfd_skb(skb)) { 761 ctrl |= FLEXCAN_MB_CNT_EDL; 762 763 if (cfd->flags & CANFD_BRS) 764 ctrl |= FLEXCAN_MB_CNT_BRS; 765 } 766 767 for (i = 0; i < cfd->len; i += sizeof(u32)) { 768 data = be32_to_cpup((__be32 *)&cfd->data[i]); 769 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]); 770 } 771 772 can_put_echo_skb(skb, dev, 0, 0); 773 774 priv->write(can_id, &priv->tx_mb->can_id); 775 priv->write(ctrl, &priv->tx_mb->can_ctrl); 776 777 /* Errata ERR005829 step8: 778 * Write twice INACTIVE(0x8) code to first MB. 779 */ 780 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 781 &priv->tx_mb_reserved->can_ctrl); 782 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 783 &priv->tx_mb_reserved->can_ctrl); 784 785 return NETDEV_TX_OK; 786 } 787 788 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr) 789 { 790 struct flexcan_priv *priv = netdev_priv(dev); 791 struct flexcan_regs __iomem *regs = priv->regs; 792 struct sk_buff *skb; 793 struct can_frame *cf; 794 bool rx_errors = false, tx_errors = false; 795 u32 timestamp; 796 int err; 797 798 timestamp = priv->read(®s->timer) << 16; 799 800 skb = alloc_can_err_skb(dev, &cf); 801 if (unlikely(!skb)) 802 return; 803 804 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 805 806 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 807 netdev_dbg(dev, "BIT1_ERR irq\n"); 808 cf->data[2] |= CAN_ERR_PROT_BIT1; 809 tx_errors = true; 810 } 811 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 812 netdev_dbg(dev, "BIT0_ERR irq\n"); 813 cf->data[2] |= CAN_ERR_PROT_BIT0; 814 tx_errors = true; 815 } 816 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 817 netdev_dbg(dev, "ACK_ERR irq\n"); 818 cf->can_id |= CAN_ERR_ACK; 819 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 820 tx_errors = true; 821 } 822 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 823 netdev_dbg(dev, "CRC_ERR irq\n"); 824 cf->data[2] |= CAN_ERR_PROT_BIT; 825 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 826 rx_errors = true; 827 } 828 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 829 netdev_dbg(dev, "FRM_ERR irq\n"); 830 cf->data[2] |= CAN_ERR_PROT_FORM; 831 rx_errors = true; 832 } 833 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 834 netdev_dbg(dev, "STF_ERR irq\n"); 835 cf->data[2] |= CAN_ERR_PROT_STUFF; 836 rx_errors = true; 837 } 838 839 priv->can.can_stats.bus_error++; 840 if (rx_errors) 841 dev->stats.rx_errors++; 842 if (tx_errors) 843 dev->stats.tx_errors++; 844 845 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 846 if (err) 847 dev->stats.rx_fifo_errors++; 848 } 849 850 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr) 851 { 852 struct flexcan_priv *priv = netdev_priv(dev); 853 struct flexcan_regs __iomem *regs = priv->regs; 854 struct sk_buff *skb; 855 struct can_frame *cf; 856 enum can_state new_state, rx_state, tx_state; 857 int flt; 858 struct can_berr_counter bec; 859 u32 timestamp; 860 int err; 861 862 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 863 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 864 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ? 865 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; 866 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ? 867 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; 868 new_state = max(tx_state, rx_state); 869 } else { 870 __flexcan_get_berr_counter(dev, &bec); 871 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ? 872 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF; 873 rx_state = bec.rxerr >= bec.txerr ? new_state : 0; 874 tx_state = bec.rxerr <= bec.txerr ? new_state : 0; 875 } 876 877 /* state hasn't changed */ 878 if (likely(new_state == priv->can.state)) 879 return; 880 881 timestamp = priv->read(®s->timer) << 16; 882 883 skb = alloc_can_err_skb(dev, &cf); 884 if (unlikely(!skb)) 885 return; 886 887 can_change_state(dev, cf, tx_state, rx_state); 888 889 if (unlikely(new_state == CAN_STATE_BUS_OFF)) 890 can_bus_off(dev); 891 892 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 893 if (err) 894 dev->stats.rx_fifo_errors++; 895 } 896 897 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask) 898 { 899 u64 reg = 0; 900 901 if (upper_32_bits(mask)) 902 reg = (u64)priv->read(addr - 4) << 32; 903 if (lower_32_bits(mask)) 904 reg |= priv->read(addr); 905 906 return reg & mask; 907 } 908 909 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr) 910 { 911 if (upper_32_bits(val)) 912 priv->write(upper_32_bits(val), addr - 4); 913 if (lower_32_bits(val)) 914 priv->write(lower_32_bits(val), addr); 915 } 916 917 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv) 918 { 919 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask); 920 } 921 922 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv) 923 { 924 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask); 925 } 926 927 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload) 928 { 929 return container_of(offload, struct flexcan_priv, offload); 930 } 931 932 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload, 933 unsigned int n, u32 *timestamp, 934 bool drop) 935 { 936 struct flexcan_priv *priv = rx_offload_to_priv(offload); 937 struct flexcan_regs __iomem *regs = priv->regs; 938 struct flexcan_mb __iomem *mb; 939 struct sk_buff *skb; 940 struct canfd_frame *cfd; 941 u32 reg_ctrl, reg_id, reg_iflag1; 942 int i; 943 944 mb = flexcan_get_mb(priv, n); 945 946 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 947 u32 code; 948 949 do { 950 reg_ctrl = priv->read(&mb->can_ctrl); 951 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT); 952 953 /* is this MB empty? */ 954 code = reg_ctrl & FLEXCAN_MB_CODE_MASK; 955 if ((code != FLEXCAN_MB_CODE_RX_FULL) && 956 (code != FLEXCAN_MB_CODE_RX_OVERRUN)) 957 return NULL; 958 959 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) { 960 /* This MB was overrun, we lost data */ 961 offload->dev->stats.rx_over_errors++; 962 offload->dev->stats.rx_errors++; 963 } 964 } else { 965 reg_iflag1 = priv->read(®s->iflag1); 966 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE)) 967 return NULL; 968 969 reg_ctrl = priv->read(&mb->can_ctrl); 970 } 971 972 if (unlikely(drop)) { 973 skb = ERR_PTR(-ENOBUFS); 974 goto mark_as_read; 975 } 976 977 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) 978 skb = alloc_canfd_skb(offload->dev, &cfd); 979 else 980 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd); 981 if (unlikely(!skb)) { 982 skb = ERR_PTR(-ENOMEM); 983 goto mark_as_read; 984 } 985 986 /* increase timstamp to full 32 bit */ 987 *timestamp = reg_ctrl << 16; 988 989 reg_id = priv->read(&mb->can_id); 990 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 991 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 992 else 993 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK; 994 995 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) { 996 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf); 997 998 if (reg_ctrl & FLEXCAN_MB_CNT_BRS) 999 cfd->flags |= CANFD_BRS; 1000 } else { 1001 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf); 1002 1003 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 1004 cfd->can_id |= CAN_RTR_FLAG; 1005 } 1006 1007 if (reg_ctrl & FLEXCAN_MB_CNT_ESI) 1008 cfd->flags |= CANFD_ESI; 1009 1010 for (i = 0; i < cfd->len; i += sizeof(u32)) { 1011 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)])); 1012 *(__be32 *)(cfd->data + i) = data; 1013 } 1014 1015 mark_as_read: 1016 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) 1017 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1); 1018 else 1019 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 1020 1021 /* Read the Free Running Timer. It is optional but recommended 1022 * to unlock Mailbox as soon as possible and make it available 1023 * for reception. 1024 */ 1025 priv->read(®s->timer); 1026 1027 return skb; 1028 } 1029 1030 static irqreturn_t flexcan_irq(int irq, void *dev_id) 1031 { 1032 struct net_device *dev = dev_id; 1033 struct net_device_stats *stats = &dev->stats; 1034 struct flexcan_priv *priv = netdev_priv(dev); 1035 struct flexcan_regs __iomem *regs = priv->regs; 1036 irqreturn_t handled = IRQ_NONE; 1037 u64 reg_iflag_tx; 1038 u32 reg_esr; 1039 enum can_state last_state = priv->can.state; 1040 1041 /* reception interrupt */ 1042 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 1043 u64 reg_iflag_rx; 1044 int ret; 1045 1046 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) { 1047 handled = IRQ_HANDLED; 1048 ret = can_rx_offload_irq_offload_timestamp(&priv->offload, 1049 reg_iflag_rx); 1050 if (!ret) 1051 break; 1052 } 1053 } else { 1054 u32 reg_iflag1; 1055 1056 reg_iflag1 = priv->read(®s->iflag1); 1057 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) { 1058 handled = IRQ_HANDLED; 1059 can_rx_offload_irq_offload_fifo(&priv->offload); 1060 } 1061 1062 /* FIFO overflow interrupt */ 1063 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 1064 handled = IRQ_HANDLED; 1065 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, 1066 ®s->iflag1); 1067 dev->stats.rx_over_errors++; 1068 dev->stats.rx_errors++; 1069 } 1070 } 1071 1072 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv); 1073 1074 /* transmission complete interrupt */ 1075 if (reg_iflag_tx & priv->tx_mask) { 1076 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl); 1077 1078 handled = IRQ_HANDLED; 1079 stats->tx_bytes += 1080 can_rx_offload_get_echo_skb(&priv->offload, 0, 1081 reg_ctrl << 16, NULL); 1082 stats->tx_packets++; 1083 1084 /* after sending a RTR frame MB is in RX mode */ 1085 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 1086 &priv->tx_mb->can_ctrl); 1087 flexcan_write64(priv, priv->tx_mask, ®s->iflag1); 1088 netif_wake_queue(dev); 1089 } 1090 1091 reg_esr = priv->read(®s->esr); 1092 1093 /* ACK all bus error, state change and wake IRQ sources */ 1094 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) { 1095 handled = IRQ_HANDLED; 1096 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr); 1097 } 1098 1099 /* state change interrupt or broken error state quirk fix is enabled */ 1100 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) || 1101 (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE | 1102 FLEXCAN_QUIRK_BROKEN_PERR_STATE))) 1103 flexcan_irq_state(dev, reg_esr); 1104 1105 /* bus error IRQ - handle if bus error reporting is activated */ 1106 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) && 1107 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1108 flexcan_irq_bus_err(dev, reg_esr); 1109 1110 /* availability of error interrupt among state transitions in case 1111 * bus error reporting is de-activated and 1112 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled: 1113 * +--------------------------------------------------------------+ 1114 * | +----------------------------------------------+ [stopped / | 1115 * | | | sleeping] -+ 1116 * +-+-> active <-> warning <-> passive -> bus off -+ 1117 * ___________^^^^^^^^^^^^_______________________________ 1118 * disabled(1) enabled disabled 1119 * 1120 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled 1121 */ 1122 if ((last_state != priv->can.state) && 1123 (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) && 1124 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 1125 switch (priv->can.state) { 1126 case CAN_STATE_ERROR_ACTIVE: 1127 if (priv->devtype_data.quirks & 1128 FLEXCAN_QUIRK_BROKEN_WERR_STATE) 1129 flexcan_error_irq_enable(priv); 1130 else 1131 flexcan_error_irq_disable(priv); 1132 break; 1133 1134 case CAN_STATE_ERROR_WARNING: 1135 flexcan_error_irq_enable(priv); 1136 break; 1137 1138 case CAN_STATE_ERROR_PASSIVE: 1139 case CAN_STATE_BUS_OFF: 1140 flexcan_error_irq_disable(priv); 1141 break; 1142 1143 default: 1144 break; 1145 } 1146 } 1147 1148 if (handled) 1149 can_rx_offload_irq_finish(&priv->offload); 1150 1151 return handled; 1152 } 1153 1154 static void flexcan_set_bittiming_ctrl(const struct net_device *dev) 1155 { 1156 const struct flexcan_priv *priv = netdev_priv(dev); 1157 const struct can_bittiming *bt = &priv->can.bittiming; 1158 struct flexcan_regs __iomem *regs = priv->regs; 1159 u32 reg; 1160 1161 reg = priv->read(®s->ctrl); 1162 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 1163 FLEXCAN_CTRL_RJW(0x3) | 1164 FLEXCAN_CTRL_PSEG1(0x7) | 1165 FLEXCAN_CTRL_PSEG2(0x7) | 1166 FLEXCAN_CTRL_PROPSEG(0x7)); 1167 1168 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 1169 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 1170 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 1171 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 1172 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 1173 1174 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); 1175 priv->write(reg, ®s->ctrl); 1176 1177 /* print chip status */ 1178 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 1179 priv->read(®s->mcr), priv->read(®s->ctrl)); 1180 } 1181 1182 static void flexcan_set_bittiming_cbt(const struct net_device *dev) 1183 { 1184 struct flexcan_priv *priv = netdev_priv(dev); 1185 struct can_bittiming *bt = &priv->can.bittiming; 1186 struct can_bittiming *dbt = &priv->can.data_bittiming; 1187 struct flexcan_regs __iomem *regs = priv->regs; 1188 u32 reg_cbt, reg_fdctrl; 1189 1190 /* CBT */ 1191 /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit 1192 * long. The can_calc_bittiming() tries to divide the tseg1 1193 * equally between phase_seg1 and prop_seg, which may not fit 1194 * in CBT register. Therefore, if phase_seg1 is more than 1195 * possible value, increase prop_seg and decrease phase_seg1. 1196 */ 1197 if (bt->phase_seg1 > 0x20) { 1198 bt->prop_seg += (bt->phase_seg1 - 0x20); 1199 bt->phase_seg1 = 0x20; 1200 } 1201 1202 reg_cbt = FLEXCAN_CBT_BTF | 1203 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) | 1204 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) | 1205 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) | 1206 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) | 1207 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1); 1208 1209 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt); 1210 priv->write(reg_cbt, ®s->cbt); 1211 1212 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1213 u32 reg_fdcbt, reg_ctrl2; 1214 1215 if (bt->brp != dbt->brp) 1216 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n", 1217 dbt->brp, bt->brp); 1218 1219 /* FDCBT */ 1220 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is 1221 * 5 bit long. The can_calc_bittiming tries to divide 1222 * the tseg1 equally between phase_seg1 and prop_seg, 1223 * which may not fit in FDCBT register. Therefore, if 1224 * phase_seg1 is more than possible value, increase 1225 * prop_seg and decrease phase_seg1 1226 */ 1227 if (dbt->phase_seg1 > 0x8) { 1228 dbt->prop_seg += (dbt->phase_seg1 - 0x8); 1229 dbt->phase_seg1 = 0x8; 1230 } 1231 1232 reg_fdcbt = priv->read(®s->fdcbt); 1233 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) | 1234 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) | 1235 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) | 1236 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) | 1237 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7)); 1238 1239 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) | 1240 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) | 1241 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) | 1242 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) | 1243 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1); 1244 1245 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt); 1246 priv->write(reg_fdcbt, ®s->fdcbt); 1247 1248 /* CTRL2 */ 1249 reg_ctrl2 = priv->read(®s->ctrl2); 1250 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN; 1251 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) 1252 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN; 1253 1254 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2); 1255 priv->write(reg_ctrl2, ®s->ctrl2); 1256 } 1257 1258 /* FDCTRL */ 1259 reg_fdctrl = priv->read(®s->fdctrl); 1260 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE | 1261 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f)); 1262 1263 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1264 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE; 1265 1266 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1267 /* TDC must be disabled for Loop Back mode */ 1268 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN; 1269 } else { 1270 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN | 1271 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 1272 ((dbt->phase_seg1 - 1) + 1273 dbt->prop_seg + 2) * 1274 ((dbt->brp - 1 ) + 1)); 1275 } 1276 } 1277 1278 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl); 1279 priv->write(reg_fdctrl, ®s->fdctrl); 1280 1281 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n", 1282 __func__, 1283 priv->read(®s->mcr), priv->read(®s->ctrl), 1284 priv->read(®s->ctrl2), priv->read(®s->fdctrl), 1285 priv->read(®s->cbt), priv->read(®s->fdcbt)); 1286 } 1287 1288 static void flexcan_set_bittiming(struct net_device *dev) 1289 { 1290 const struct flexcan_priv *priv = netdev_priv(dev); 1291 struct flexcan_regs __iomem *regs = priv->regs; 1292 u32 reg; 1293 1294 reg = priv->read(®s->ctrl); 1295 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP | 1296 FLEXCAN_CTRL_LOM); 1297 1298 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 1299 reg |= FLEXCAN_CTRL_LPB; 1300 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1301 reg |= FLEXCAN_CTRL_LOM; 1302 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 1303 reg |= FLEXCAN_CTRL_SMP; 1304 1305 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); 1306 priv->write(reg, ®s->ctrl); 1307 1308 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) 1309 return flexcan_set_bittiming_cbt(dev); 1310 else 1311 return flexcan_set_bittiming_ctrl(dev); 1312 } 1313 1314 static void flexcan_ram_init(struct net_device *dev) 1315 { 1316 struct flexcan_priv *priv = netdev_priv(dev); 1317 struct flexcan_regs __iomem *regs = priv->regs; 1318 u32 reg_ctrl2; 1319 1320 /* 11.8.3.13 Detection and correction of memory errors: 1321 * CTRL2[WRMFRZ] grants write access to all memory positions 1322 * that require initialization, ranging from 0x080 to 0xADF 1323 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled. 1324 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers 1325 * need to be initialized as well. MCR[RFEN] must not be set 1326 * during memory initialization. 1327 */ 1328 reg_ctrl2 = priv->read(®s->ctrl2); 1329 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ; 1330 priv->write(reg_ctrl2, ®s->ctrl2); 1331 1332 memset_io(®s->init, 0, sizeof(regs->init)); 1333 1334 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1335 memset_io(®s->init_fd, 0, sizeof(regs->init_fd)); 1336 1337 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ; 1338 priv->write(reg_ctrl2, ®s->ctrl2); 1339 } 1340 1341 static int flexcan_rx_offload_setup(struct net_device *dev) 1342 { 1343 struct flexcan_priv *priv = netdev_priv(dev); 1344 int err; 1345 1346 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1347 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN; 1348 else 1349 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN; 1350 1351 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16) 1352 priv->mb_count = 16; 1353 else 1354 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) + 1355 (sizeof(priv->regs->mb[1]) / priv->mb_size); 1356 1357 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) 1358 priv->tx_mb_reserved = 1359 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX); 1360 else 1361 priv->tx_mb_reserved = 1362 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO); 1363 priv->tx_mb_idx = priv->mb_count - 1; 1364 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx); 1365 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx); 1366 1367 priv->offload.mailbox_read = flexcan_mailbox_read; 1368 1369 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 1370 priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST; 1371 priv->offload.mb_last = priv->mb_count - 2; 1372 1373 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last, 1374 priv->offload.mb_first); 1375 err = can_rx_offload_add_timestamp(dev, &priv->offload); 1376 } else { 1377 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | 1378 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE; 1379 err = can_rx_offload_add_fifo(dev, &priv->offload, 1380 FLEXCAN_NAPI_WEIGHT); 1381 } 1382 1383 return err; 1384 } 1385 1386 static void flexcan_chip_interrupts_enable(const struct net_device *dev) 1387 { 1388 const struct flexcan_priv *priv = netdev_priv(dev); 1389 struct flexcan_regs __iomem *regs = priv->regs; 1390 u64 reg_imask; 1391 1392 disable_irq(dev->irq); 1393 priv->write(priv->reg_ctrl_default, ®s->ctrl); 1394 reg_imask = priv->rx_mask | priv->tx_mask; 1395 priv->write(upper_32_bits(reg_imask), ®s->imask2); 1396 priv->write(lower_32_bits(reg_imask), ®s->imask1); 1397 enable_irq(dev->irq); 1398 } 1399 1400 static void flexcan_chip_interrupts_disable(const struct net_device *dev) 1401 { 1402 const struct flexcan_priv *priv = netdev_priv(dev); 1403 struct flexcan_regs __iomem *regs = priv->regs; 1404 1405 priv->write(0, ®s->imask2); 1406 priv->write(0, ®s->imask1); 1407 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 1408 ®s->ctrl); 1409 } 1410 1411 /* flexcan_chip_start 1412 * 1413 * this functions is entered with clocks enabled 1414 * 1415 */ 1416 static int flexcan_chip_start(struct net_device *dev) 1417 { 1418 struct flexcan_priv *priv = netdev_priv(dev); 1419 struct flexcan_regs __iomem *regs = priv->regs; 1420 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr; 1421 int err, i; 1422 struct flexcan_mb __iomem *mb; 1423 1424 /* enable module */ 1425 err = flexcan_chip_enable(priv); 1426 if (err) 1427 return err; 1428 1429 /* soft reset */ 1430 err = flexcan_chip_softreset(priv); 1431 if (err) 1432 goto out_chip_disable; 1433 1434 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC) 1435 flexcan_ram_init(dev); 1436 1437 flexcan_set_bittiming(dev); 1438 1439 /* set freeze, halt */ 1440 err = flexcan_chip_freeze(priv); 1441 if (err) 1442 goto out_chip_disable; 1443 1444 /* MCR 1445 * 1446 * only supervisor access 1447 * enable warning int 1448 * enable individual RX masking 1449 * choose format C 1450 * set max mailbox number 1451 */ 1452 reg_mcr = priv->read(®s->mcr); 1453 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); 1454 reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | 1455 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx); 1456 1457 /* MCR 1458 * 1459 * FIFO: 1460 * - disable for mailbox mode 1461 * - enable for FIFO mode 1462 */ 1463 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) 1464 reg_mcr &= ~FLEXCAN_MCR_FEN; 1465 else 1466 reg_mcr |= FLEXCAN_MCR_FEN; 1467 1468 /* MCR 1469 * 1470 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be 1471 * asserted because this will impede the self reception 1472 * of a transmitted message. This is not documented in 1473 * earlier versions of flexcan block guide. 1474 * 1475 * Self Reception: 1476 * - enable Self Reception for loopback mode 1477 * (by clearing "Self Reception Disable" bit) 1478 * - disable for normal operation 1479 */ 1480 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 1481 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS; 1482 else 1483 reg_mcr |= FLEXCAN_MCR_SRX_DIS; 1484 1485 /* MCR - CAN-FD */ 1486 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1487 reg_mcr |= FLEXCAN_MCR_FDEN; 1488 else 1489 reg_mcr &= ~FLEXCAN_MCR_FDEN; 1490 1491 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 1492 priv->write(reg_mcr, ®s->mcr); 1493 1494 /* CTRL 1495 * 1496 * disable timer sync feature 1497 * 1498 * disable auto busoff recovery 1499 * transmit lowest buffer first 1500 * 1501 * enable tx and rx warning interrupt 1502 * enable bus off interrupt 1503 * (== FLEXCAN_CTRL_ERR_STATE) 1504 */ 1505 reg_ctrl = priv->read(®s->ctrl); 1506 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 1507 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 1508 FLEXCAN_CTRL_ERR_STATE; 1509 1510 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 1511 * on most Flexcan cores, too. Otherwise we don't get 1512 * any error warning or passive interrupts. 1513 */ 1514 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE || 1515 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 1516 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 1517 else 1518 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK; 1519 1520 /* save for later use */ 1521 priv->reg_ctrl_default = reg_ctrl; 1522 /* leave interrupts disabled for now */ 1523 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL; 1524 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 1525 priv->write(reg_ctrl, ®s->ctrl); 1526 1527 if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) { 1528 reg_ctrl2 = priv->read(®s->ctrl2); 1529 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS; 1530 priv->write(reg_ctrl2, ®s->ctrl2); 1531 } 1532 1533 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) { 1534 u32 reg_fdctrl; 1535 1536 reg_fdctrl = priv->read(®s->fdctrl); 1537 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) | 1538 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3)); 1539 1540 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1541 reg_fdctrl |= 1542 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 1543 FLEXCAN_FDCTRL_MBDSR_64) | 1544 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 1545 FLEXCAN_FDCTRL_MBDSR_64); 1546 } else { 1547 reg_fdctrl |= 1548 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 1549 FLEXCAN_FDCTRL_MBDSR_8) | 1550 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 1551 FLEXCAN_FDCTRL_MBDSR_8); 1552 } 1553 1554 netdev_dbg(dev, "%s: writing fdctrl=0x%08x", 1555 __func__, reg_fdctrl); 1556 priv->write(reg_fdctrl, ®s->fdctrl); 1557 } 1558 1559 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 1560 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) { 1561 mb = flexcan_get_mb(priv, i); 1562 priv->write(FLEXCAN_MB_CODE_RX_EMPTY, 1563 &mb->can_ctrl); 1564 } 1565 } else { 1566 /* clear and invalidate unused mailboxes first */ 1567 for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) { 1568 mb = flexcan_get_mb(priv, i); 1569 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE, 1570 &mb->can_ctrl); 1571 } 1572 } 1573 1574 /* Errata ERR005829: mark first TX mailbox as INACTIVE */ 1575 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 1576 &priv->tx_mb_reserved->can_ctrl); 1577 1578 /* mark TX mailbox as INACTIVE */ 1579 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 1580 &priv->tx_mb->can_ctrl); 1581 1582 /* acceptance mask/acceptance code (accept everything) */ 1583 priv->write(0x0, ®s->rxgmask); 1584 priv->write(0x0, ®s->rx14mask); 1585 priv->write(0x0, ®s->rx15mask); 1586 1587 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG) 1588 priv->write(0x0, ®s->rxfgmask); 1589 1590 /* clear acceptance filters */ 1591 for (i = 0; i < priv->mb_count; i++) 1592 priv->write(0, ®s->rximr[i]); 1593 1594 /* On Vybrid, disable non-correctable errors interrupt and 1595 * freeze mode. It still can correct the correctable errors 1596 * when HW supports ECC. 1597 * 1598 * This also works around errata e5295 which generates false 1599 * positive memory errors and put the device in freeze mode. 1600 */ 1601 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) { 1602 /* Follow the protocol as described in "Detection 1603 * and Correction of Memory Errors" to write to 1604 * MECR register (step 1 - 5) 1605 * 1606 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1 1607 * 2. set CTRL2[ECRWRE] 1608 */ 1609 reg_ctrl2 = priv->read(®s->ctrl2); 1610 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE; 1611 priv->write(reg_ctrl2, ®s->ctrl2); 1612 1613 /* 3. clear MECR[ECRWRDIS] */ 1614 reg_mecr = priv->read(®s->mecr); 1615 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS; 1616 priv->write(reg_mecr, ®s->mecr); 1617 1618 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */ 1619 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK | 1620 FLEXCAN_MECR_FANCEI_MSK); 1621 priv->write(reg_mecr, ®s->mecr); 1622 1623 /* 5. after configuration done, lock MECR by either 1624 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE] 1625 */ 1626 reg_mecr |= FLEXCAN_MECR_ECRWRDIS; 1627 priv->write(reg_mecr, ®s->mecr); 1628 1629 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE; 1630 priv->write(reg_ctrl2, ®s->ctrl2); 1631 } 1632 1633 /* synchronize with the can bus */ 1634 err = flexcan_chip_unfreeze(priv); 1635 if (err) 1636 goto out_chip_disable; 1637 1638 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1639 1640 /* print chip status */ 1641 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 1642 priv->read(®s->mcr), priv->read(®s->ctrl)); 1643 1644 return 0; 1645 1646 out_chip_disable: 1647 flexcan_chip_disable(priv); 1648 return err; 1649 } 1650 1651 /* __flexcan_chip_stop 1652 * 1653 * this function is entered with clocks enabled 1654 */ 1655 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error) 1656 { 1657 struct flexcan_priv *priv = netdev_priv(dev); 1658 int err; 1659 1660 /* freeze + disable module */ 1661 err = flexcan_chip_freeze(priv); 1662 if (err && !disable_on_error) 1663 return err; 1664 err = flexcan_chip_disable(priv); 1665 if (err && !disable_on_error) 1666 goto out_chip_unfreeze; 1667 1668 priv->can.state = CAN_STATE_STOPPED; 1669 1670 return 0; 1671 1672 out_chip_unfreeze: 1673 flexcan_chip_unfreeze(priv); 1674 1675 return err; 1676 } 1677 1678 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev) 1679 { 1680 return __flexcan_chip_stop(dev, true); 1681 } 1682 1683 static inline int flexcan_chip_stop(struct net_device *dev) 1684 { 1685 return __flexcan_chip_stop(dev, false); 1686 } 1687 1688 static int flexcan_open(struct net_device *dev) 1689 { 1690 struct flexcan_priv *priv = netdev_priv(dev); 1691 int err; 1692 1693 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) && 1694 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) { 1695 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n"); 1696 return -EINVAL; 1697 } 1698 1699 err = pm_runtime_resume_and_get(priv->dev); 1700 if (err < 0) 1701 return err; 1702 1703 err = open_candev(dev); 1704 if (err) 1705 goto out_runtime_put; 1706 1707 err = flexcan_transceiver_enable(priv); 1708 if (err) 1709 goto out_close; 1710 1711 err = flexcan_rx_offload_setup(dev); 1712 if (err) 1713 goto out_transceiver_disable; 1714 1715 err = flexcan_chip_start(dev); 1716 if (err) 1717 goto out_can_rx_offload_del; 1718 1719 can_rx_offload_enable(&priv->offload); 1720 1721 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 1722 if (err) 1723 goto out_can_rx_offload_disable; 1724 1725 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) { 1726 err = request_irq(priv->irq_boff, 1727 flexcan_irq, IRQF_SHARED, dev->name, dev); 1728 if (err) 1729 goto out_free_irq; 1730 1731 err = request_irq(priv->irq_err, 1732 flexcan_irq, IRQF_SHARED, dev->name, dev); 1733 if (err) 1734 goto out_free_irq_boff; 1735 } 1736 1737 flexcan_chip_interrupts_enable(dev); 1738 1739 netif_start_queue(dev); 1740 1741 return 0; 1742 1743 out_free_irq_boff: 1744 free_irq(priv->irq_boff, dev); 1745 out_free_irq: 1746 free_irq(dev->irq, dev); 1747 out_can_rx_offload_disable: 1748 can_rx_offload_disable(&priv->offload); 1749 flexcan_chip_stop(dev); 1750 out_can_rx_offload_del: 1751 can_rx_offload_del(&priv->offload); 1752 out_transceiver_disable: 1753 flexcan_transceiver_disable(priv); 1754 out_close: 1755 close_candev(dev); 1756 out_runtime_put: 1757 pm_runtime_put(priv->dev); 1758 1759 return err; 1760 } 1761 1762 static int flexcan_close(struct net_device *dev) 1763 { 1764 struct flexcan_priv *priv = netdev_priv(dev); 1765 1766 netif_stop_queue(dev); 1767 flexcan_chip_interrupts_disable(dev); 1768 1769 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) { 1770 free_irq(priv->irq_err, dev); 1771 free_irq(priv->irq_boff, dev); 1772 } 1773 1774 free_irq(dev->irq, dev); 1775 can_rx_offload_disable(&priv->offload); 1776 flexcan_chip_stop_disable_on_error(dev); 1777 1778 can_rx_offload_del(&priv->offload); 1779 flexcan_transceiver_disable(priv); 1780 close_candev(dev); 1781 1782 pm_runtime_put(priv->dev); 1783 1784 return 0; 1785 } 1786 1787 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 1788 { 1789 int err; 1790 1791 switch (mode) { 1792 case CAN_MODE_START: 1793 err = flexcan_chip_start(dev); 1794 if (err) 1795 return err; 1796 1797 flexcan_chip_interrupts_enable(dev); 1798 1799 netif_wake_queue(dev); 1800 break; 1801 1802 default: 1803 return -EOPNOTSUPP; 1804 } 1805 1806 return 0; 1807 } 1808 1809 static const struct net_device_ops flexcan_netdev_ops = { 1810 .ndo_open = flexcan_open, 1811 .ndo_stop = flexcan_close, 1812 .ndo_start_xmit = flexcan_start_xmit, 1813 .ndo_change_mtu = can_change_mtu, 1814 }; 1815 1816 static int register_flexcandev(struct net_device *dev) 1817 { 1818 struct flexcan_priv *priv = netdev_priv(dev); 1819 struct flexcan_regs __iomem *regs = priv->regs; 1820 u32 reg, err; 1821 1822 err = flexcan_clks_enable(priv); 1823 if (err) 1824 return err; 1825 1826 /* select "bus clock", chip must be disabled */ 1827 err = flexcan_chip_disable(priv); 1828 if (err) 1829 goto out_clks_disable; 1830 1831 reg = priv->read(®s->ctrl); 1832 if (priv->clk_src) 1833 reg |= FLEXCAN_CTRL_CLK_SRC; 1834 else 1835 reg &= ~FLEXCAN_CTRL_CLK_SRC; 1836 priv->write(reg, ®s->ctrl); 1837 1838 err = flexcan_chip_enable(priv); 1839 if (err) 1840 goto out_chip_disable; 1841 1842 /* set freeze, halt */ 1843 err = flexcan_chip_freeze(priv); 1844 if (err) 1845 goto out_chip_disable; 1846 1847 /* activate FIFO, restrict register access */ 1848 reg = priv->read(®s->mcr); 1849 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 1850 priv->write(reg, ®s->mcr); 1851 1852 /* Currently we only support newer versions of this core 1853 * featuring a RX hardware FIFO (although this driver doesn't 1854 * make use of it on some cores). Older cores, found on some 1855 * Coldfire derivates are not tested. 1856 */ 1857 reg = priv->read(®s->mcr); 1858 if (!(reg & FLEXCAN_MCR_FEN)) { 1859 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 1860 err = -ENODEV; 1861 goto out_chip_disable; 1862 } 1863 1864 err = register_candev(dev); 1865 if (err) 1866 goto out_chip_disable; 1867 1868 /* Disable core and let pm_runtime_put() disable the clocks. 1869 * If CONFIG_PM is not enabled, the clocks will stay powered. 1870 */ 1871 flexcan_chip_disable(priv); 1872 pm_runtime_put(priv->dev); 1873 1874 return 0; 1875 1876 out_chip_disable: 1877 flexcan_chip_disable(priv); 1878 out_clks_disable: 1879 flexcan_clks_disable(priv); 1880 return err; 1881 } 1882 1883 static void unregister_flexcandev(struct net_device *dev) 1884 { 1885 unregister_candev(dev); 1886 } 1887 1888 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev) 1889 { 1890 struct net_device *dev = platform_get_drvdata(pdev); 1891 struct device_node *np = pdev->dev.of_node; 1892 struct device_node *gpr_np; 1893 struct flexcan_priv *priv; 1894 phandle phandle; 1895 u32 out_val[3]; 1896 int ret; 1897 1898 if (!np) 1899 return -EINVAL; 1900 1901 /* stop mode property format is: 1902 * <&gpr req_gpr req_bit>. 1903 */ 1904 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 1905 ARRAY_SIZE(out_val)); 1906 if (ret) { 1907 dev_dbg(&pdev->dev, "no stop-mode property\n"); 1908 return ret; 1909 } 1910 phandle = *out_val; 1911 1912 gpr_np = of_find_node_by_phandle(phandle); 1913 if (!gpr_np) { 1914 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n"); 1915 return -ENODEV; 1916 } 1917 1918 priv = netdev_priv(dev); 1919 priv->stm.gpr = syscon_node_to_regmap(gpr_np); 1920 if (IS_ERR(priv->stm.gpr)) { 1921 dev_dbg(&pdev->dev, "could not find gpr regmap\n"); 1922 ret = PTR_ERR(priv->stm.gpr); 1923 goto out_put_node; 1924 } 1925 1926 priv->stm.req_gpr = out_val[1]; 1927 priv->stm.req_bit = out_val[2]; 1928 1929 dev_dbg(&pdev->dev, 1930 "gpr %s req_gpr=0x02%x req_bit=%u\n", 1931 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit); 1932 1933 return 0; 1934 1935 out_put_node: 1936 of_node_put(gpr_np); 1937 return ret; 1938 } 1939 1940 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev) 1941 { 1942 struct net_device *dev = platform_get_drvdata(pdev); 1943 struct flexcan_priv *priv; 1944 u8 scu_idx; 1945 int ret; 1946 1947 ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx); 1948 if (ret < 0) { 1949 dev_dbg(&pdev->dev, "failed to get scu index\n"); 1950 return ret; 1951 } 1952 1953 priv = netdev_priv(dev); 1954 priv->scu_idx = scu_idx; 1955 1956 /* this function could be deferred probe, return -EPROBE_DEFER */ 1957 return imx_scu_get_handle(&priv->sc_ipc_handle); 1958 } 1959 1960 /* flexcan_setup_stop_mode - Setup stop mode for wakeup 1961 * 1962 * Return: = 0 setup stop mode successfully or doesn't support this feature 1963 * < 0 fail to setup stop mode (could be deferred probe) 1964 */ 1965 static int flexcan_setup_stop_mode(struct platform_device *pdev) 1966 { 1967 struct net_device *dev = platform_get_drvdata(pdev); 1968 struct flexcan_priv *priv; 1969 int ret; 1970 1971 priv = netdev_priv(dev); 1972 1973 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) 1974 ret = flexcan_setup_stop_mode_scfw(pdev); 1975 else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) 1976 ret = flexcan_setup_stop_mode_gpr(pdev); 1977 else 1978 /* return 0 directly if doesn't support stop mode feature */ 1979 return 0; 1980 1981 if (ret) 1982 return ret; 1983 1984 device_set_wakeup_capable(&pdev->dev, true); 1985 1986 if (of_property_read_bool(pdev->dev.of_node, "wakeup-source")) 1987 device_set_wakeup_enable(&pdev->dev, true); 1988 1989 return 0; 1990 } 1991 1992 static const struct of_device_id flexcan_of_match[] = { 1993 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, }, 1994 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, }, 1995 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 1996 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 1997 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, }, 1998 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, }, 1999 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, }, 2000 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 2001 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, }, 2002 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, }, 2003 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, }, 2004 { /* sentinel */ }, 2005 }; 2006 MODULE_DEVICE_TABLE(of, flexcan_of_match); 2007 2008 static const struct platform_device_id flexcan_id_table[] = { 2009 { 2010 .name = "flexcan-mcf5441x", 2011 .driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data, 2012 }, { 2013 /* sentinel */ 2014 }, 2015 }; 2016 MODULE_DEVICE_TABLE(platform, flexcan_id_table); 2017 2018 static int flexcan_probe(struct platform_device *pdev) 2019 { 2020 const struct of_device_id *of_id; 2021 const struct flexcan_devtype_data *devtype_data; 2022 struct net_device *dev; 2023 struct flexcan_priv *priv; 2024 struct regulator *reg_xceiver; 2025 struct clk *clk_ipg = NULL, *clk_per = NULL; 2026 struct flexcan_regs __iomem *regs; 2027 struct flexcan_platform_data *pdata; 2028 int err, irq; 2029 u8 clk_src = 1; 2030 u32 clock_freq = 0; 2031 2032 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver"); 2033 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) 2034 return -EPROBE_DEFER; 2035 else if (PTR_ERR(reg_xceiver) == -ENODEV) 2036 reg_xceiver = NULL; 2037 else if (IS_ERR(reg_xceiver)) 2038 return PTR_ERR(reg_xceiver); 2039 2040 if (pdev->dev.of_node) { 2041 of_property_read_u32(pdev->dev.of_node, 2042 "clock-frequency", &clock_freq); 2043 of_property_read_u8(pdev->dev.of_node, 2044 "fsl,clk-source", &clk_src); 2045 } else { 2046 pdata = dev_get_platdata(&pdev->dev); 2047 if (pdata) { 2048 clock_freq = pdata->clock_frequency; 2049 clk_src = pdata->clk_src; 2050 } 2051 } 2052 2053 if (!clock_freq) { 2054 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2055 if (IS_ERR(clk_ipg)) { 2056 dev_err(&pdev->dev, "no ipg clock defined\n"); 2057 return PTR_ERR(clk_ipg); 2058 } 2059 2060 clk_per = devm_clk_get(&pdev->dev, "per"); 2061 if (IS_ERR(clk_per)) { 2062 dev_err(&pdev->dev, "no per clock defined\n"); 2063 return PTR_ERR(clk_per); 2064 } 2065 clock_freq = clk_get_rate(clk_per); 2066 } 2067 2068 irq = platform_get_irq(pdev, 0); 2069 if (irq <= 0) 2070 return -ENODEV; 2071 2072 regs = devm_platform_ioremap_resource(pdev, 0); 2073 if (IS_ERR(regs)) 2074 return PTR_ERR(regs); 2075 2076 of_id = of_match_device(flexcan_of_match, &pdev->dev); 2077 if (of_id) 2078 devtype_data = of_id->data; 2079 else if (platform_get_device_id(pdev)->driver_data) 2080 devtype_data = (struct flexcan_devtype_data *) 2081 platform_get_device_id(pdev)->driver_data; 2082 else 2083 return -ENODEV; 2084 2085 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) && 2086 !((devtype_data->quirks & 2087 (FLEXCAN_QUIRK_USE_RX_MAILBOX | 2088 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 2089 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | 2090 FLEXCAN_QUIRK_SUPPORT_RX_FIFO)) == 2091 (FLEXCAN_QUIRK_USE_RX_MAILBOX | 2092 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 2093 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR))) { 2094 dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n"); 2095 return -EINVAL; 2096 } 2097 2098 if ((devtype_data->quirks & 2099 (FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 2100 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)) == 2101 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR) { 2102 dev_err(&pdev->dev, 2103 "Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n", 2104 devtype_data->quirks); 2105 return -EINVAL; 2106 } 2107 2108 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 2109 if (!dev) 2110 return -ENOMEM; 2111 2112 platform_set_drvdata(pdev, dev); 2113 SET_NETDEV_DEV(dev, &pdev->dev); 2114 2115 dev->netdev_ops = &flexcan_netdev_ops; 2116 dev->ethtool_ops = &flexcan_ethtool_ops; 2117 dev->irq = irq; 2118 dev->flags |= IFF_ECHO; 2119 2120 priv = netdev_priv(dev); 2121 priv->devtype_data = *devtype_data; 2122 2123 if (of_property_read_bool(pdev->dev.of_node, "big-endian") || 2124 priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) { 2125 priv->read = flexcan_read_be; 2126 priv->write = flexcan_write_be; 2127 } else { 2128 priv->read = flexcan_read_le; 2129 priv->write = flexcan_write_le; 2130 } 2131 2132 priv->dev = &pdev->dev; 2133 priv->can.clock.freq = clock_freq; 2134 priv->can.do_set_mode = flexcan_set_mode; 2135 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 2136 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 2137 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 2138 CAN_CTRLMODE_BERR_REPORTING; 2139 priv->regs = regs; 2140 priv->clk_ipg = clk_ipg; 2141 priv->clk_per = clk_per; 2142 priv->clk_src = clk_src; 2143 priv->reg_xceiver = reg_xceiver; 2144 2145 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) { 2146 priv->irq_boff = platform_get_irq(pdev, 1); 2147 if (priv->irq_boff <= 0) { 2148 err = -ENODEV; 2149 goto failed_platform_get_irq; 2150 } 2151 priv->irq_err = platform_get_irq(pdev, 2); 2152 if (priv->irq_err <= 0) { 2153 err = -ENODEV; 2154 goto failed_platform_get_irq; 2155 } 2156 } 2157 2158 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) { 2159 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | 2160 CAN_CTRLMODE_FD_NON_ISO; 2161 priv->can.bittiming_const = &flexcan_fd_bittiming_const; 2162 priv->can.data_bittiming_const = 2163 &flexcan_fd_data_bittiming_const; 2164 } else { 2165 priv->can.bittiming_const = &flexcan_bittiming_const; 2166 } 2167 2168 pm_runtime_get_noresume(&pdev->dev); 2169 pm_runtime_set_active(&pdev->dev); 2170 pm_runtime_enable(&pdev->dev); 2171 2172 err = register_flexcandev(dev); 2173 if (err) { 2174 dev_err(&pdev->dev, "registering netdev failed\n"); 2175 goto failed_register; 2176 } 2177 2178 err = flexcan_setup_stop_mode(pdev); 2179 if (err < 0) { 2180 dev_err_probe(&pdev->dev, err, "setup stop mode failed\n"); 2181 goto failed_setup_stop_mode; 2182 } 2183 2184 of_can_transceiver(dev); 2185 2186 return 0; 2187 2188 failed_setup_stop_mode: 2189 unregister_flexcandev(dev); 2190 failed_register: 2191 pm_runtime_put_noidle(&pdev->dev); 2192 pm_runtime_disable(&pdev->dev); 2193 failed_platform_get_irq: 2194 free_candev(dev); 2195 return err; 2196 } 2197 2198 static int flexcan_remove(struct platform_device *pdev) 2199 { 2200 struct net_device *dev = platform_get_drvdata(pdev); 2201 2202 device_set_wakeup_enable(&pdev->dev, false); 2203 device_set_wakeup_capable(&pdev->dev, false); 2204 unregister_flexcandev(dev); 2205 pm_runtime_disable(&pdev->dev); 2206 free_candev(dev); 2207 2208 return 0; 2209 } 2210 2211 static int __maybe_unused flexcan_suspend(struct device *device) 2212 { 2213 struct net_device *dev = dev_get_drvdata(device); 2214 struct flexcan_priv *priv = netdev_priv(dev); 2215 int err; 2216 2217 if (netif_running(dev)) { 2218 /* if wakeup is enabled, enter stop mode 2219 * else enter disabled mode. 2220 */ 2221 if (device_may_wakeup(device)) { 2222 enable_irq_wake(dev->irq); 2223 err = flexcan_enter_stop_mode(priv); 2224 if (err) 2225 return err; 2226 } else { 2227 err = flexcan_chip_stop(dev); 2228 if (err) 2229 return err; 2230 2231 flexcan_chip_interrupts_disable(dev); 2232 2233 err = pinctrl_pm_select_sleep_state(device); 2234 if (err) 2235 return err; 2236 } 2237 netif_stop_queue(dev); 2238 netif_device_detach(dev); 2239 } 2240 priv->can.state = CAN_STATE_SLEEPING; 2241 2242 return 0; 2243 } 2244 2245 static int __maybe_unused flexcan_resume(struct device *device) 2246 { 2247 struct net_device *dev = dev_get_drvdata(device); 2248 struct flexcan_priv *priv = netdev_priv(dev); 2249 int err; 2250 2251 priv->can.state = CAN_STATE_ERROR_ACTIVE; 2252 if (netif_running(dev)) { 2253 netif_device_attach(dev); 2254 netif_start_queue(dev); 2255 if (device_may_wakeup(device)) { 2256 disable_irq_wake(dev->irq); 2257 err = flexcan_exit_stop_mode(priv); 2258 if (err) 2259 return err; 2260 } else { 2261 err = pinctrl_pm_select_default_state(device); 2262 if (err) 2263 return err; 2264 2265 err = flexcan_chip_start(dev); 2266 if (err) 2267 return err; 2268 2269 flexcan_chip_interrupts_enable(dev); 2270 } 2271 } 2272 2273 return 0; 2274 } 2275 2276 static int __maybe_unused flexcan_runtime_suspend(struct device *device) 2277 { 2278 struct net_device *dev = dev_get_drvdata(device); 2279 struct flexcan_priv *priv = netdev_priv(dev); 2280 2281 flexcan_clks_disable(priv); 2282 2283 return 0; 2284 } 2285 2286 static int __maybe_unused flexcan_runtime_resume(struct device *device) 2287 { 2288 struct net_device *dev = dev_get_drvdata(device); 2289 struct flexcan_priv *priv = netdev_priv(dev); 2290 2291 return flexcan_clks_enable(priv); 2292 } 2293 2294 static int __maybe_unused flexcan_noirq_suspend(struct device *device) 2295 { 2296 struct net_device *dev = dev_get_drvdata(device); 2297 struct flexcan_priv *priv = netdev_priv(dev); 2298 2299 if (netif_running(dev)) { 2300 int err; 2301 2302 if (device_may_wakeup(device)) 2303 flexcan_enable_wakeup_irq(priv, true); 2304 2305 err = pm_runtime_force_suspend(device); 2306 if (err) 2307 return err; 2308 } 2309 2310 return 0; 2311 } 2312 2313 static int __maybe_unused flexcan_noirq_resume(struct device *device) 2314 { 2315 struct net_device *dev = dev_get_drvdata(device); 2316 struct flexcan_priv *priv = netdev_priv(dev); 2317 2318 if (netif_running(dev)) { 2319 int err; 2320 2321 err = pm_runtime_force_resume(device); 2322 if (err) 2323 return err; 2324 2325 if (device_may_wakeup(device)) 2326 flexcan_enable_wakeup_irq(priv, false); 2327 } 2328 2329 return 0; 2330 } 2331 2332 static const struct dev_pm_ops flexcan_pm_ops = { 2333 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume) 2334 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL) 2335 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume) 2336 }; 2337 2338 static struct platform_driver flexcan_driver = { 2339 .driver = { 2340 .name = DRV_NAME, 2341 .pm = &flexcan_pm_ops, 2342 .of_match_table = flexcan_of_match, 2343 }, 2344 .probe = flexcan_probe, 2345 .remove = flexcan_remove, 2346 .id_table = flexcan_id_table, 2347 }; 2348 2349 module_platform_driver(flexcan_driver); 2350 2351 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 2352 "Marc Kleine-Budde <kernel@pengutronix.de>"); 2353 MODULE_LICENSE("GPL v2"); 2354 MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 2355