1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver 4 // 5 // Copyright (c) 2019, 2020, 2021 Pengutronix, 6 // Marc Kleine-Budde <kernel@pengutronix.de> 7 // 8 // Based on: 9 // 10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface 11 // 12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org> 13 // 14 15 #include <asm/unaligned.h> 16 #include <linux/bitfield.h> 17 #include <linux/clk.h> 18 #include <linux/device.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/module.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/property.h> 23 24 #include "mcp251xfd.h" 25 26 #define DEVICE_NAME "mcp251xfd" 27 28 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = { 29 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG | 30 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX | 31 MCP251XFD_QUIRK_ECC, 32 .model = MCP251XFD_MODEL_MCP2517FD, 33 }; 34 35 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = { 36 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 37 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 38 .model = MCP251XFD_MODEL_MCP2518FD, 39 }; 40 41 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = { 42 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 43 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 44 .model = MCP251XFD_MODEL_MCP251863, 45 }; 46 47 /* Autodetect model, start with CRC enabled. */ 48 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = { 49 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 50 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 51 .model = MCP251XFD_MODEL_MCP251XFD, 52 }; 53 54 static const struct can_bittiming_const mcp251xfd_bittiming_const = { 55 .name = DEVICE_NAME, 56 .tseg1_min = 2, 57 .tseg1_max = 256, 58 .tseg2_min = 1, 59 .tseg2_max = 128, 60 .sjw_max = 128, 61 .brp_min = 1, 62 .brp_max = 256, 63 .brp_inc = 1, 64 }; 65 66 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = { 67 .name = DEVICE_NAME, 68 .tseg1_min = 1, 69 .tseg1_max = 32, 70 .tseg2_min = 1, 71 .tseg2_max = 16, 72 .sjw_max = 16, 73 .brp_min = 1, 74 .brp_max = 256, 75 .brp_inc = 1, 76 }; 77 78 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model) 79 { 80 switch (model) { 81 case MCP251XFD_MODEL_MCP2517FD: 82 return "MCP2517FD"; 83 case MCP251XFD_MODEL_MCP2518FD: 84 return "MCP2518FD"; 85 case MCP251XFD_MODEL_MCP251863: 86 return "MCP251863"; 87 case MCP251XFD_MODEL_MCP251XFD: 88 return "MCP251xFD"; 89 } 90 91 return "<unknown>"; 92 } 93 94 static inline const char * 95 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv) 96 { 97 return __mcp251xfd_get_model_str(priv->devtype_data.model); 98 } 99 100 static const char *mcp251xfd_get_mode_str(const u8 mode) 101 { 102 switch (mode) { 103 case MCP251XFD_REG_CON_MODE_MIXED: 104 return "Mixed (CAN FD/CAN 2.0)"; 105 case MCP251XFD_REG_CON_MODE_SLEEP: 106 return "Sleep"; 107 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK: 108 return "Internal Loopback"; 109 case MCP251XFD_REG_CON_MODE_LISTENONLY: 110 return "Listen Only"; 111 case MCP251XFD_REG_CON_MODE_CONFIG: 112 return "Configuration"; 113 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK: 114 return "External Loopback"; 115 case MCP251XFD_REG_CON_MODE_CAN2_0: 116 return "CAN 2.0"; 117 case MCP251XFD_REG_CON_MODE_RESTRICTED: 118 return "Restricted Operation"; 119 } 120 121 return "<unknown>"; 122 } 123 124 static const char * 125 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference) 126 { 127 switch (~osc & osc_reference & 128 (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) { 129 case MCP251XFD_REG_OSC_PLLRDY: 130 return "PLL"; 131 case MCP251XFD_REG_OSC_OSCRDY: 132 return "Oscillator"; 133 case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY: 134 return "Oscillator/PLL"; 135 } 136 137 return "<unknown>"; 138 } 139 140 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv) 141 { 142 if (!priv->reg_vdd) 143 return 0; 144 145 return regulator_enable(priv->reg_vdd); 146 } 147 148 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv) 149 { 150 if (!priv->reg_vdd) 151 return 0; 152 153 return regulator_disable(priv->reg_vdd); 154 } 155 156 static inline int 157 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv) 158 { 159 if (!priv->reg_xceiver) 160 return 0; 161 162 return regulator_enable(priv->reg_xceiver); 163 } 164 165 static inline int 166 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv) 167 { 168 if (!priv->reg_xceiver) 169 return 0; 170 171 return regulator_disable(priv->reg_xceiver); 172 } 173 174 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv) 175 { 176 int err; 177 178 err = clk_prepare_enable(priv->clk); 179 if (err) 180 return err; 181 182 err = mcp251xfd_vdd_enable(priv); 183 if (err) 184 clk_disable_unprepare(priv->clk); 185 186 /* Wait for oscillator stabilisation time after power up */ 187 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US, 188 2 * MCP251XFD_OSC_STAB_SLEEP_US); 189 190 return err; 191 } 192 193 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv) 194 { 195 int err; 196 197 err = mcp251xfd_vdd_disable(priv); 198 if (err) 199 return err; 200 201 clk_disable_unprepare(priv->clk); 202 203 return 0; 204 } 205 206 static inline bool mcp251xfd_reg_invalid(u32 reg) 207 { 208 return reg == 0x0 || reg == 0xffffffff; 209 } 210 211 static inline int 212 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode) 213 { 214 u32 val; 215 int err; 216 217 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val); 218 if (err) 219 return err; 220 221 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val); 222 223 return 0; 224 } 225 226 static int 227 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 228 const u8 mode_req, bool nowait) 229 { 230 u32 con = 0, con_reqop, osc = 0; 231 u8 mode; 232 int err; 233 234 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req); 235 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON, 236 MCP251XFD_REG_CON_REQOP_MASK, con_reqop); 237 if (err == -EBADMSG) { 238 netdev_err(priv->ndev, 239 "Failed to set Requested Operation Mode.\n"); 240 241 return -ENODEV; 242 } else if (err) { 243 return err; 244 } 245 246 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait) 247 return 0; 248 249 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con, 250 !mcp251xfd_reg_invalid(con) && 251 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, 252 con) == mode_req, 253 MCP251XFD_POLL_SLEEP_US, 254 MCP251XFD_POLL_TIMEOUT_US); 255 if (err != -ETIMEDOUT && err != -EBADMSG) 256 return err; 257 258 /* Ignore return value. 259 * Print below error messages, even if this fails. 260 */ 261 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 262 263 if (mcp251xfd_reg_invalid(con)) { 264 netdev_err(priv->ndev, 265 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n", 266 con, osc); 267 268 return -ENODEV; 269 } 270 271 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con); 272 netdev_err(priv->ndev, 273 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n", 274 mcp251xfd_get_mode_str(mode_req), mode_req, 275 mcp251xfd_get_mode_str(mode), mode, 276 con, osc); 277 278 return -ETIMEDOUT; 279 } 280 281 static inline int 282 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 283 const u8 mode_req) 284 { 285 return __mcp251xfd_chip_set_mode(priv, mode_req, false); 286 } 287 288 static inline int __maybe_unused 289 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv, 290 const u8 mode_req) 291 { 292 return __mcp251xfd_chip_set_mode(priv, mode_req, true); 293 } 294 295 static int 296 mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv, 297 u32 osc_reference, u32 osc_mask) 298 { 299 u32 osc; 300 int err; 301 302 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc, 303 !mcp251xfd_reg_invalid(osc) && 304 (osc & osc_mask) == osc_reference, 305 MCP251XFD_OSC_STAB_SLEEP_US, 306 MCP251XFD_OSC_STAB_TIMEOUT_US); 307 if (err != -ETIMEDOUT) 308 return err; 309 310 if (mcp251xfd_reg_invalid(osc)) { 311 netdev_err(priv->ndev, 312 "Failed to read Oscillator Configuration Register (osc=0x%08x).\n", 313 osc); 314 return -ENODEV; 315 } 316 317 netdev_err(priv->ndev, 318 "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n", 319 mcp251xfd_get_osc_str(osc, osc_reference), 320 osc, osc_reference, osc_mask); 321 322 return -ETIMEDOUT; 323 } 324 325 static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv) 326 { 327 u32 osc, osc_reference, osc_mask; 328 int err; 329 330 /* For normal sleep on MCP2517FD and MCP2518FD, clearing 331 * "Oscillator Disable" will wake the chip. For low power mode 332 * on MCP2518FD, asserting the chip select will wake the 333 * chip. Writing to the Oscillator register will wake it in 334 * both cases. 335 */ 336 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 337 MCP251XFD_REG_OSC_CLKODIV_10); 338 339 /* We cannot check for the PLL ready bit (either set or 340 * unset), as the PLL might be enabled. This can happen if the 341 * system reboots, while the mcp251xfd stays powered. 342 */ 343 osc_reference = MCP251XFD_REG_OSC_OSCRDY; 344 osc_mask = MCP251XFD_REG_OSC_OSCRDY; 345 346 /* If the controller is in Sleep Mode the following write only 347 * removes the "Oscillator Disable" bit and powers it up. All 348 * other bits are unaffected. 349 */ 350 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 351 if (err) 352 return err; 353 354 /* Sometimes the PLL is stuck enabled, the controller never 355 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our 356 * caller takes care of retry. 357 */ 358 return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); 359 } 360 361 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv) 362 { 363 if (priv->pll_enable) { 364 u32 osc; 365 int err; 366 367 /* Turn off PLL */ 368 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 369 MCP251XFD_REG_OSC_CLKODIV_10); 370 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 371 if (err) 372 netdev_err(priv->ndev, 373 "Failed to disable PLL.\n"); 374 375 priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow; 376 } 377 378 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); 379 } 380 381 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv) 382 { 383 const __be16 cmd = mcp251xfd_cmd_reset(); 384 int err; 385 386 /* The Set Mode and SPI Reset command only works if the 387 * controller is not in Sleep Mode. 388 */ 389 err = mcp251xfd_chip_wake(priv); 390 if (err) 391 return err; 392 393 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); 394 if (err) 395 return err; 396 397 /* spi_write_then_read() works with non DMA-safe buffers */ 398 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0); 399 } 400 401 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv) 402 { 403 u32 osc_reference, osc_mask; 404 u8 mode; 405 int err; 406 407 /* Check for reset defaults of OSC reg. 408 * This will take care of stabilization period. 409 */ 410 osc_reference = MCP251XFD_REG_OSC_OSCRDY | 411 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 412 MCP251XFD_REG_OSC_CLKODIV_10); 413 osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY; 414 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); 415 if (err) 416 return err; 417 418 err = mcp251xfd_chip_get_mode(priv, &mode); 419 if (err) 420 return err; 421 422 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) { 423 netdev_info(priv->ndev, 424 "Controller not in Config Mode after reset, but in %s Mode (%u).\n", 425 mcp251xfd_get_mode_str(mode), mode); 426 return -ETIMEDOUT; 427 } 428 429 return 0; 430 } 431 432 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv) 433 { 434 int err, i; 435 436 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) { 437 if (i) 438 netdev_info(priv->ndev, 439 "Retrying to reset controller.\n"); 440 441 err = mcp251xfd_chip_softreset_do(priv); 442 if (err == -ETIMEDOUT) 443 continue; 444 if (err) 445 return err; 446 447 err = mcp251xfd_chip_softreset_check(priv); 448 if (err == -ETIMEDOUT) 449 continue; 450 if (err) 451 return err; 452 453 return 0; 454 } 455 456 return err; 457 } 458 459 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv) 460 { 461 u32 osc, osc_reference, osc_mask; 462 int err; 463 464 /* Activate Low Power Mode on Oscillator Disable. This only 465 * works on the MCP2518FD. The MCP2517FD will go into normal 466 * Sleep Mode instead. 467 */ 468 osc = MCP251XFD_REG_OSC_LPMEN | 469 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 470 MCP251XFD_REG_OSC_CLKODIV_10); 471 osc_reference = MCP251XFD_REG_OSC_OSCRDY; 472 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY; 473 474 if (priv->pll_enable) { 475 osc |= MCP251XFD_REG_OSC_PLLEN; 476 osc_reference |= MCP251XFD_REG_OSC_PLLRDY; 477 } 478 479 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 480 if (err) 481 return err; 482 483 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); 484 if (err) 485 return err; 486 487 priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast; 488 489 return 0; 490 } 491 492 static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv) 493 { 494 /* Set Time Base Counter Prescaler to 1. 495 * 496 * This means an overflow of the 32 bit Time Base Counter 497 * register at 40 MHz every 107 seconds. 498 */ 499 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON, 500 MCP251XFD_REG_TSCON_TBCEN); 501 } 502 503 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv) 504 { 505 const struct can_bittiming *bt = &priv->can.bittiming; 506 const struct can_bittiming *dbt = &priv->can.data_bittiming; 507 u32 val = 0; 508 s8 tdco; 509 int err; 510 511 /* CAN Control Register 512 * 513 * - no transmit bandwidth sharing 514 * - config mode 515 * - disable transmit queue 516 * - store in transmit FIFO event 517 * - transition to restricted operation mode on system error 518 * - ESI is transmitted recessive when ESI of message is high or 519 * CAN controller error passive 520 * - restricted retransmission attempts, 521 * use TQXCON_TXAT and FIFOCON_TXAT 522 * - wake-up filter bits T11FILTER 523 * - use CAN bus line filter for wakeup 524 * - protocol exception is treated as a form error 525 * - Do not compare data bytes 526 */ 527 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, 528 MCP251XFD_REG_CON_MODE_CONFIG) | 529 MCP251XFD_REG_CON_STEF | 530 MCP251XFD_REG_CON_ESIGM | 531 MCP251XFD_REG_CON_RTXAT | 532 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK, 533 MCP251XFD_REG_CON_WFT_T11FILTER) | 534 MCP251XFD_REG_CON_WAKFIL | 535 MCP251XFD_REG_CON_PXEDIS; 536 537 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) 538 val |= MCP251XFD_REG_CON_ISOCRCEN; 539 540 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val); 541 if (err) 542 return err; 543 544 /* Nominal Bit Time */ 545 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) | 546 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK, 547 bt->prop_seg + bt->phase_seg1 - 1) | 548 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK, 549 bt->phase_seg2 - 1) | 550 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1); 551 552 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val); 553 if (err) 554 return err; 555 556 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) 557 return 0; 558 559 /* Data Bit Time */ 560 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) | 561 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK, 562 dbt->prop_seg + dbt->phase_seg1 - 1) | 563 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK, 564 dbt->phase_seg2 - 1) | 565 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1); 566 567 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val); 568 if (err) 569 return err; 570 571 /* Transmitter Delay Compensation */ 572 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1), 573 -64, 63); 574 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, 575 MCP251XFD_REG_TDC_TDCMOD_AUTO) | 576 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco); 577 578 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val); 579 } 580 581 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv) 582 { 583 u32 val; 584 585 if (!priv->rx_int) 586 return 0; 587 588 /* Configure GPIOs: 589 * - PIN0: GPIO Input 590 * - PIN1: GPIO Input/RX Interrupt 591 * 592 * PIN1 must be Input, otherwise there is a glitch on the 593 * rx-INT line. It happens between setting the PIN as output 594 * (in the first byte of the SPI transfer) and configuring the 595 * PIN as interrupt (in the last byte of the SPI transfer). 596 */ 597 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 | 598 MCP251XFD_REG_IOCON_TRIS0; 599 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 600 } 601 602 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv) 603 { 604 u32 val; 605 606 if (!priv->rx_int) 607 return 0; 608 609 /* Configure GPIOs: 610 * - PIN0: GPIO Input 611 * - PIN1: GPIO Input 612 */ 613 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 | 614 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0; 615 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 616 } 617 618 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv) 619 { 620 struct mcp251xfd_ecc *ecc = &priv->ecc; 621 void *ram; 622 u32 val = 0; 623 int err; 624 625 ecc->ecc_stat = 0; 626 627 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC) 628 val = MCP251XFD_REG_ECCCON_ECCEN; 629 630 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 631 MCP251XFD_REG_ECCCON_ECCEN, val); 632 if (err) 633 return err; 634 635 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL); 636 if (!ram) 637 return -ENOMEM; 638 639 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram, 640 MCP251XFD_RAM_SIZE); 641 kfree(ram); 642 643 return err; 644 } 645 646 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv) 647 { 648 u8 mode; 649 650 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 651 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK; 652 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 653 mode = MCP251XFD_REG_CON_MODE_LISTENONLY; 654 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 655 mode = MCP251XFD_REG_CON_MODE_MIXED; 656 else 657 mode = MCP251XFD_REG_CON_MODE_CAN2_0; 658 659 return mode; 660 } 661 662 static int 663 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv, 664 bool nowait) 665 { 666 u8 mode; 667 668 mode = mcp251xfd_get_normal_mode(priv); 669 670 return __mcp251xfd_chip_set_mode(priv, mode, nowait); 671 } 672 673 static inline int 674 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv) 675 { 676 return __mcp251xfd_chip_set_normal_mode(priv, false); 677 } 678 679 static inline int 680 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv) 681 { 682 return __mcp251xfd_chip_set_normal_mode(priv, true); 683 } 684 685 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv) 686 { 687 u32 val; 688 int err; 689 690 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE; 691 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val); 692 if (err) 693 return err; 694 695 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 696 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val); 697 if (err) 698 return err; 699 700 val = MCP251XFD_REG_INT_CERRIE | 701 MCP251XFD_REG_INT_SERRIE | 702 MCP251XFD_REG_INT_RXOVIE | 703 MCP251XFD_REG_INT_TXATIE | 704 MCP251XFD_REG_INT_SPICRCIE | 705 MCP251XFD_REG_INT_ECCIE | 706 MCP251XFD_REG_INT_TEFIE | 707 MCP251XFD_REG_INT_MODIE | 708 MCP251XFD_REG_INT_RXIE; 709 710 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 711 val |= MCP251XFD_REG_INT_IVMIE; 712 713 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val); 714 } 715 716 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv) 717 { 718 int err; 719 u32 mask; 720 721 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0); 722 if (err) 723 return err; 724 725 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 726 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 727 mask, 0x0); 728 if (err) 729 return err; 730 731 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0); 732 } 733 734 static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv, 735 const enum can_state state) 736 { 737 priv->can.state = state; 738 739 mcp251xfd_chip_interrupts_disable(priv); 740 mcp251xfd_chip_rx_int_disable(priv); 741 mcp251xfd_chip_sleep(priv); 742 } 743 744 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv) 745 { 746 int err; 747 748 err = mcp251xfd_chip_softreset(priv); 749 if (err) 750 goto out_chip_stop; 751 752 err = mcp251xfd_chip_clock_init(priv); 753 if (err) 754 goto out_chip_stop; 755 756 err = mcp251xfd_chip_timestamp_init(priv); 757 if (err) 758 goto out_chip_stop; 759 760 err = mcp251xfd_set_bittiming(priv); 761 if (err) 762 goto out_chip_stop; 763 764 err = mcp251xfd_chip_rx_int_enable(priv); 765 if (err) 766 goto out_chip_stop; 767 768 err = mcp251xfd_chip_ecc_init(priv); 769 if (err) 770 goto out_chip_stop; 771 772 err = mcp251xfd_ring_init(priv); 773 if (err) 774 goto out_chip_stop; 775 776 err = mcp251xfd_chip_fifo_init(priv); 777 if (err) 778 goto out_chip_stop; 779 780 priv->can.state = CAN_STATE_ERROR_ACTIVE; 781 782 err = mcp251xfd_chip_set_normal_mode(priv); 783 if (err) 784 goto out_chip_stop; 785 786 return 0; 787 788 out_chip_stop: 789 mcp251xfd_dump(priv); 790 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 791 792 return err; 793 } 794 795 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode) 796 { 797 struct mcp251xfd_priv *priv = netdev_priv(ndev); 798 int err; 799 800 switch (mode) { 801 case CAN_MODE_START: 802 err = mcp251xfd_chip_start(priv); 803 if (err) 804 return err; 805 806 err = mcp251xfd_chip_interrupts_enable(priv); 807 if (err) { 808 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 809 return err; 810 } 811 812 netif_wake_queue(ndev); 813 break; 814 815 default: 816 return -EOPNOTSUPP; 817 } 818 819 return 0; 820 } 821 822 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev, 823 struct can_berr_counter *bec) 824 { 825 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 826 u32 trec; 827 int err; 828 829 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 830 if (err) 831 return err; 832 833 if (trec & MCP251XFD_REG_TREC_TXBO) 834 bec->txerr = 256; 835 else 836 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec); 837 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec); 838 839 return 0; 840 } 841 842 static int mcp251xfd_get_berr_counter(const struct net_device *ndev, 843 struct can_berr_counter *bec) 844 { 845 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 846 847 /* Avoid waking up the controller if the interface is down */ 848 if (!(ndev->flags & IFF_UP)) 849 return 0; 850 851 /* The controller is powered down during Bus Off, use saved 852 * bec values. 853 */ 854 if (priv->can.state == CAN_STATE_BUS_OFF) { 855 *bec = priv->bec; 856 return 0; 857 } 858 859 return __mcp251xfd_get_berr_counter(ndev, bec); 860 } 861 862 static struct sk_buff * 863 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv, 864 struct can_frame **cf, u32 *timestamp) 865 { 866 struct sk_buff *skb; 867 int err; 868 869 err = mcp251xfd_get_timestamp(priv, timestamp); 870 if (err) 871 return NULL; 872 873 skb = alloc_can_err_skb(priv->ndev, cf); 874 if (skb) 875 mcp251xfd_skb_set_timestamp(priv, skb, *timestamp); 876 877 return skb; 878 } 879 880 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv) 881 { 882 struct net_device_stats *stats = &priv->ndev->stats; 883 struct mcp251xfd_rx_ring *ring; 884 struct sk_buff *skb; 885 struct can_frame *cf; 886 u32 timestamp, rxovif; 887 int err, i; 888 889 stats->rx_over_errors++; 890 stats->rx_errors++; 891 892 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif); 893 if (err) 894 return err; 895 896 mcp251xfd_for_each_rx_ring(priv, ring, i) { 897 if (!(rxovif & BIT(ring->fifo_nr))) 898 continue; 899 900 /* If SERRIF is active, there was a RX MAB overflow. */ 901 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) { 902 if (net_ratelimit()) 903 netdev_dbg(priv->ndev, 904 "RX-%d: MAB overflow detected.\n", 905 ring->nr); 906 } else { 907 if (net_ratelimit()) 908 netdev_dbg(priv->ndev, 909 "RX-%d: FIFO overflow.\n", 910 ring->nr); 911 } 912 913 err = regmap_update_bits(priv->map_reg, 914 MCP251XFD_REG_FIFOSTA(ring->fifo_nr), 915 MCP251XFD_REG_FIFOSTA_RXOVIF, 916 0x0); 917 if (err) 918 return err; 919 } 920 921 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 922 if (!skb) 923 return 0; 924 925 cf->can_id |= CAN_ERR_CRTL; 926 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 927 928 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 929 if (err) 930 stats->rx_fifo_errors++; 931 932 return 0; 933 } 934 935 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv) 936 { 937 netdev_info(priv->ndev, "%s\n", __func__); 938 939 return 0; 940 } 941 942 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv) 943 { 944 struct net_device_stats *stats = &priv->ndev->stats; 945 u32 bdiag1, timestamp; 946 struct sk_buff *skb; 947 struct can_frame *cf = NULL; 948 int err; 949 950 err = mcp251xfd_get_timestamp(priv, ×tamp); 951 if (err) 952 return err; 953 954 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1); 955 if (err) 956 return err; 957 958 /* Write 0s to clear error bits, don't write 1s to non active 959 * bits, as they will be set. 960 */ 961 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0); 962 if (err) 963 return err; 964 965 priv->can.can_stats.bus_error++; 966 967 skb = alloc_can_err_skb(priv->ndev, &cf); 968 if (cf) 969 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 970 971 /* Controller misconfiguration */ 972 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM)) 973 netdev_err(priv->ndev, 974 "recv'd DLC is larger than PLSIZE of FIFO element."); 975 976 /* RX errors */ 977 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR | 978 MCP251XFD_REG_BDIAG1_NCRCERR)) { 979 netdev_dbg(priv->ndev, "CRC error\n"); 980 981 stats->rx_errors++; 982 if (cf) 983 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 984 } 985 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR | 986 MCP251XFD_REG_BDIAG1_NSTUFERR)) { 987 netdev_dbg(priv->ndev, "Stuff error\n"); 988 989 stats->rx_errors++; 990 if (cf) 991 cf->data[2] |= CAN_ERR_PROT_STUFF; 992 } 993 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR | 994 MCP251XFD_REG_BDIAG1_NFORMERR)) { 995 netdev_dbg(priv->ndev, "Format error\n"); 996 997 stats->rx_errors++; 998 if (cf) 999 cf->data[2] |= CAN_ERR_PROT_FORM; 1000 } 1001 1002 /* TX errors */ 1003 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) { 1004 netdev_dbg(priv->ndev, "NACK error\n"); 1005 1006 stats->tx_errors++; 1007 if (cf) { 1008 cf->can_id |= CAN_ERR_ACK; 1009 cf->data[2] |= CAN_ERR_PROT_TX; 1010 } 1011 } 1012 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR | 1013 MCP251XFD_REG_BDIAG1_NBIT1ERR)) { 1014 netdev_dbg(priv->ndev, "Bit1 error\n"); 1015 1016 stats->tx_errors++; 1017 if (cf) 1018 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1; 1019 } 1020 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR | 1021 MCP251XFD_REG_BDIAG1_NBIT0ERR)) { 1022 netdev_dbg(priv->ndev, "Bit0 error\n"); 1023 1024 stats->tx_errors++; 1025 if (cf) 1026 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0; 1027 } 1028 1029 if (!cf) 1030 return 0; 1031 1032 mcp251xfd_skb_set_timestamp(priv, skb, timestamp); 1033 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 1034 if (err) 1035 stats->rx_fifo_errors++; 1036 1037 return 0; 1038 } 1039 1040 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv) 1041 { 1042 struct net_device_stats *stats = &priv->ndev->stats; 1043 struct sk_buff *skb; 1044 struct can_frame *cf = NULL; 1045 enum can_state new_state, rx_state, tx_state; 1046 u32 trec, timestamp; 1047 int err; 1048 1049 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 1050 if (err) 1051 return err; 1052 1053 if (trec & MCP251XFD_REG_TREC_TXBO) 1054 tx_state = CAN_STATE_BUS_OFF; 1055 else if (trec & MCP251XFD_REG_TREC_TXBP) 1056 tx_state = CAN_STATE_ERROR_PASSIVE; 1057 else if (trec & MCP251XFD_REG_TREC_TXWARN) 1058 tx_state = CAN_STATE_ERROR_WARNING; 1059 else 1060 tx_state = CAN_STATE_ERROR_ACTIVE; 1061 1062 if (trec & MCP251XFD_REG_TREC_RXBP) 1063 rx_state = CAN_STATE_ERROR_PASSIVE; 1064 else if (trec & MCP251XFD_REG_TREC_RXWARN) 1065 rx_state = CAN_STATE_ERROR_WARNING; 1066 else 1067 rx_state = CAN_STATE_ERROR_ACTIVE; 1068 1069 new_state = max(tx_state, rx_state); 1070 if (new_state == priv->can.state) 1071 return 0; 1072 1073 /* The skb allocation might fail, but can_change_state() 1074 * handles cf == NULL. 1075 */ 1076 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 1077 can_change_state(priv->ndev, cf, tx_state, rx_state); 1078 1079 if (new_state == CAN_STATE_BUS_OFF) { 1080 /* As we're going to switch off the chip now, let's 1081 * save the error counters and return them to 1082 * userspace, if do_get_berr_counter() is called while 1083 * the chip is in Bus Off. 1084 */ 1085 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec); 1086 if (err) 1087 return err; 1088 1089 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF); 1090 can_bus_off(priv->ndev); 1091 } 1092 1093 if (!skb) 1094 return 0; 1095 1096 if (new_state != CAN_STATE_BUS_OFF) { 1097 struct can_berr_counter bec; 1098 1099 err = mcp251xfd_get_berr_counter(priv->ndev, &bec); 1100 if (err) 1101 return err; 1102 cf->data[6] = bec.txerr; 1103 cf->data[7] = bec.rxerr; 1104 } 1105 1106 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 1107 if (err) 1108 stats->rx_fifo_errors++; 1109 1110 return 0; 1111 } 1112 1113 static int 1114 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode) 1115 { 1116 const u8 mode_reference = mcp251xfd_get_normal_mode(priv); 1117 u8 mode; 1118 int err; 1119 1120 err = mcp251xfd_chip_get_mode(priv, &mode); 1121 if (err) 1122 return err; 1123 1124 if (mode == mode_reference) { 1125 netdev_dbg(priv->ndev, 1126 "Controller changed into %s Mode (%u).\n", 1127 mcp251xfd_get_mode_str(mode), mode); 1128 return 0; 1129 } 1130 1131 /* According to MCP2517FD errata DS80000792B 1., during a TX 1132 * MAB underflow, the controller will transition to Restricted 1133 * Operation Mode or Listen Only Mode (depending on SERR2LOM). 1134 * 1135 * However this is not always the case. If SERR2LOM is 1136 * configured for Restricted Operation Mode (SERR2LOM not set) 1137 * the MCP2517FD will sometimes transition to Listen Only Mode 1138 * first. When polling this bit we see that it will transition 1139 * to Restricted Operation Mode shortly after. 1140 */ 1141 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) && 1142 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED || 1143 mode == MCP251XFD_REG_CON_MODE_LISTENONLY)) 1144 netdev_dbg(priv->ndev, 1145 "Controller changed into %s Mode (%u).\n", 1146 mcp251xfd_get_mode_str(mode), mode); 1147 else 1148 netdev_err(priv->ndev, 1149 "Controller changed into %s Mode (%u).\n", 1150 mcp251xfd_get_mode_str(mode), mode); 1151 1152 /* After the application requests Normal mode, the controller 1153 * will automatically attempt to retransmit the message that 1154 * caused the TX MAB underflow. 1155 * 1156 * However, if there is an ECC error in the TX-RAM, we first 1157 * have to reload the tx-object before requesting Normal 1158 * mode. This is done later in mcp251xfd_handle_eccif(). 1159 */ 1160 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) { 1161 *set_normal_mode = true; 1162 return 0; 1163 } 1164 1165 return mcp251xfd_chip_set_normal_mode_nowait(priv); 1166 } 1167 1168 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv) 1169 { 1170 struct mcp251xfd_ecc *ecc = &priv->ecc; 1171 struct net_device_stats *stats = &priv->ndev->stats; 1172 bool handled = false; 1173 1174 /* TX MAB underflow 1175 * 1176 * According to MCP2517FD Errata DS80000792B 1. a TX MAB 1177 * underflow is indicated by SERRIF and MODIF. 1178 * 1179 * In addition to the effects mentioned in the Errata, there 1180 * are Bus Errors due to the aborted CAN frame, so a IVMIF 1181 * will be seen as well. 1182 * 1183 * Sometimes there is an ECC error in the TX-RAM, which leads 1184 * to a TX MAB underflow. 1185 * 1186 * However, probably due to a race condition, there is no 1187 * associated MODIF pending. 1188 * 1189 * Further, there are situations, where the SERRIF is caused 1190 * by an ECC error in the TX-RAM, but not even the ECCIF is 1191 * set. This only seems to happen _after_ the first occurrence 1192 * of a ECCIF (which is tracked in ecc->cnt). 1193 * 1194 * Treat all as a known system errors.. 1195 */ 1196 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF && 1197 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) || 1198 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1199 ecc->cnt) { 1200 const char *msg; 1201 1202 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1203 ecc->cnt) 1204 msg = "TX MAB underflow due to ECC error detected."; 1205 else 1206 msg = "TX MAB underflow detected."; 1207 1208 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) 1209 netdev_dbg(priv->ndev, "%s\n", msg); 1210 else 1211 netdev_info(priv->ndev, "%s\n", msg); 1212 1213 stats->tx_aborted_errors++; 1214 stats->tx_errors++; 1215 handled = true; 1216 } 1217 1218 /* RX MAB overflow 1219 * 1220 * According to MCP2517FD Errata DS80000792B 1. a RX MAB 1221 * overflow is indicated by SERRIF. 1222 * 1223 * In addition to the effects mentioned in the Errata, (most 1224 * of the times) a RXOVIF is raised, if the FIFO that is being 1225 * received into has the RXOVIE activated (and we have enabled 1226 * RXOVIE on all FIFOs). 1227 * 1228 * Sometimes there is no RXOVIF just a RXIF is pending. 1229 * 1230 * Treat all as a known system errors.. 1231 */ 1232 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF || 1233 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) { 1234 stats->rx_dropped++; 1235 handled = true; 1236 } 1237 1238 if (!handled) 1239 netdev_err(priv->ndev, 1240 "Unhandled System Error Interrupt (intf=0x%08x)!\n", 1241 priv->regs_status.intf); 1242 1243 return 0; 1244 } 1245 1246 static int 1247 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr) 1248 { 1249 struct mcp251xfd_tx_ring *tx_ring = priv->tx; 1250 struct mcp251xfd_ecc *ecc = &priv->ecc; 1251 struct mcp251xfd_tx_obj *tx_obj; 1252 u8 chip_tx_tail, tx_tail, offset; 1253 u16 addr; 1254 int err; 1255 1256 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat); 1257 1258 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail); 1259 if (err) 1260 return err; 1261 1262 tx_tail = mcp251xfd_get_tx_tail(tx_ring); 1263 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1); 1264 1265 /* Bail out if one of the following is met: 1266 * - tx_tail information is inconsistent 1267 * - for mcp2517fd: offset not 0 1268 * - for mcp2518fd: offset not 0 or 1 1269 */ 1270 if (chip_tx_tail != tx_tail || 1271 !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) || 1272 mcp251xfd_is_251863(priv))))) { 1273 netdev_err(priv->ndev, 1274 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n", 1275 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail, 1276 offset); 1277 return -EINVAL; 1278 } 1279 1280 netdev_info(priv->ndev, 1281 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n", 1282 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ? 1283 "Single" : "Double", 1284 addr, nr, tx_ring->tail, tx_tail, offset); 1285 1286 /* reload tx_obj into controller RAM ... */ 1287 tx_obj = &tx_ring->obj[nr]; 1288 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1); 1289 if (err) 1290 return err; 1291 1292 /* ... and trigger retransmit */ 1293 return mcp251xfd_chip_set_normal_mode(priv); 1294 } 1295 1296 static int 1297 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode) 1298 { 1299 struct mcp251xfd_ecc *ecc = &priv->ecc; 1300 const char *msg; 1301 bool in_tx_ram; 1302 u32 ecc_stat; 1303 u16 addr; 1304 u8 nr; 1305 int err; 1306 1307 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat); 1308 if (err) 1309 return err; 1310 1311 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT, 1312 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat); 1313 if (err) 1314 return err; 1315 1316 /* Check if ECC error occurred in TX-RAM */ 1317 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat); 1318 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr); 1319 if (!err) 1320 in_tx_ram = true; 1321 else if (err == -ENOENT) 1322 in_tx_ram = false; 1323 else 1324 return err; 1325 1326 /* Errata Reference: 1327 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2. 1328 * 1329 * ECC single error correction does not work in all cases: 1330 * 1331 * Fix/Work Around: 1332 * Enable single error correction and double error detection 1333 * interrupts by setting SECIE and DEDIE. Handle SECIF as a 1334 * detection interrupt and do not rely on the error 1335 * correction. Instead, handle both interrupts as a 1336 * notification that the RAM word at ERRADDR was corrupted. 1337 */ 1338 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF) 1339 msg = "Single ECC Error detected at address"; 1340 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF) 1341 msg = "Double ECC Error detected at address"; 1342 else 1343 return -EINVAL; 1344 1345 if (!in_tx_ram) { 1346 ecc->ecc_stat = 0; 1347 1348 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr); 1349 } else { 1350 /* Re-occurring error? */ 1351 if (ecc->ecc_stat == ecc_stat) { 1352 ecc->cnt++; 1353 } else { 1354 ecc->ecc_stat = ecc_stat; 1355 ecc->cnt = 1; 1356 } 1357 1358 netdev_info(priv->ndev, 1359 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n", 1360 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : ""); 1361 1362 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX) 1363 return mcp251xfd_handle_eccif_recover(priv, nr); 1364 } 1365 1366 if (set_normal_mode) 1367 return mcp251xfd_chip_set_normal_mode_nowait(priv); 1368 1369 return 0; 1370 } 1371 1372 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv) 1373 { 1374 int err; 1375 u32 crc; 1376 1377 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc); 1378 if (err) 1379 return err; 1380 1381 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC, 1382 MCP251XFD_REG_CRC_IF_MASK, 1383 ~crc); 1384 if (err) 1385 return err; 1386 1387 if (crc & MCP251XFD_REG_CRC_FERRIF) 1388 netdev_notice(priv->ndev, "CRC write command format error.\n"); 1389 else if (crc & MCP251XFD_REG_CRC_CRCERRIF) 1390 netdev_notice(priv->ndev, 1391 "CRC write error detected. CRC=0x%04lx.\n", 1392 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc)); 1393 1394 return 0; 1395 } 1396 1397 static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv) 1398 { 1399 const int val_bytes = regmap_get_val_bytes(priv->map_reg); 1400 size_t len; 1401 1402 if (priv->rx_ring_num == 1) 1403 len = sizeof(priv->regs_status.intf); 1404 else 1405 len = sizeof(priv->regs_status); 1406 1407 return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT, 1408 &priv->regs_status, len / val_bytes); 1409 } 1410 1411 #define mcp251xfd_handle(priv, irq, ...) \ 1412 ({ \ 1413 struct mcp251xfd_priv *_priv = (priv); \ 1414 int err; \ 1415 \ 1416 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \ 1417 if (err) \ 1418 netdev_err(_priv->ndev, \ 1419 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \ 1420 __stringify(irq), err); \ 1421 err; \ 1422 }) 1423 1424 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id) 1425 { 1426 struct mcp251xfd_priv *priv = dev_id; 1427 irqreturn_t handled = IRQ_NONE; 1428 int err; 1429 1430 if (priv->rx_int) 1431 do { 1432 int rx_pending; 1433 1434 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 1435 if (!rx_pending) 1436 break; 1437 1438 /* Assume 1st RX-FIFO pending, if other FIFOs 1439 * are pending the main IRQ handler will take 1440 * care. 1441 */ 1442 priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr); 1443 err = mcp251xfd_handle(priv, rxif); 1444 if (err) 1445 goto out_fail; 1446 1447 handled = IRQ_HANDLED; 1448 1449 /* We don't know which RX-FIFO is pending, but only 1450 * handle the 1st RX-FIFO. Leave loop here if we have 1451 * more than 1 RX-FIFO to avoid starvation. 1452 */ 1453 } while (priv->rx_ring_num == 1); 1454 1455 do { 1456 u32 intf_pending, intf_pending_clearable; 1457 bool set_normal_mode = false; 1458 1459 err = mcp251xfd_read_regs_status(priv); 1460 if (err) 1461 goto out_fail; 1462 1463 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK, 1464 priv->regs_status.intf) & 1465 FIELD_GET(MCP251XFD_REG_INT_IE_MASK, 1466 priv->regs_status.intf); 1467 1468 if (!(intf_pending)) { 1469 can_rx_offload_threaded_irq_finish(&priv->offload); 1470 return handled; 1471 } 1472 1473 /* Some interrupts must be ACKed in the 1474 * MCP251XFD_REG_INT register. 1475 * - First ACK then handle, to avoid lost-IRQ race 1476 * condition on fast re-occurring interrupts. 1477 * - Write "0" to clear active IRQs, "1" to all other, 1478 * to avoid r/m/w race condition on the 1479 * MCP251XFD_REG_INT register. 1480 */ 1481 intf_pending_clearable = intf_pending & 1482 MCP251XFD_REG_INT_IF_CLEARABLE_MASK; 1483 if (intf_pending_clearable) { 1484 err = regmap_update_bits(priv->map_reg, 1485 MCP251XFD_REG_INT, 1486 MCP251XFD_REG_INT_IF_MASK, 1487 ~intf_pending_clearable); 1488 if (err) 1489 goto out_fail; 1490 } 1491 1492 if (intf_pending & MCP251XFD_REG_INT_MODIF) { 1493 err = mcp251xfd_handle(priv, modif, &set_normal_mode); 1494 if (err) 1495 goto out_fail; 1496 } 1497 1498 if (intf_pending & MCP251XFD_REG_INT_RXIF) { 1499 err = mcp251xfd_handle(priv, rxif); 1500 if (err) 1501 goto out_fail; 1502 } 1503 1504 if (intf_pending & MCP251XFD_REG_INT_TEFIF) { 1505 err = mcp251xfd_handle(priv, tefif); 1506 if (err) 1507 goto out_fail; 1508 } 1509 1510 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) { 1511 err = mcp251xfd_handle(priv, rxovif); 1512 if (err) 1513 goto out_fail; 1514 } 1515 1516 if (intf_pending & MCP251XFD_REG_INT_TXATIF) { 1517 err = mcp251xfd_handle(priv, txatif); 1518 if (err) 1519 goto out_fail; 1520 } 1521 1522 if (intf_pending & MCP251XFD_REG_INT_IVMIF) { 1523 err = mcp251xfd_handle(priv, ivmif); 1524 if (err) 1525 goto out_fail; 1526 } 1527 1528 if (intf_pending & MCP251XFD_REG_INT_SERRIF) { 1529 err = mcp251xfd_handle(priv, serrif); 1530 if (err) 1531 goto out_fail; 1532 } 1533 1534 if (intf_pending & MCP251XFD_REG_INT_ECCIF) { 1535 err = mcp251xfd_handle(priv, eccif, set_normal_mode); 1536 if (err) 1537 goto out_fail; 1538 } 1539 1540 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) { 1541 err = mcp251xfd_handle(priv, spicrcif); 1542 if (err) 1543 goto out_fail; 1544 } 1545 1546 /* On the MCP2527FD and MCP2518FD, we don't get a 1547 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX 1548 * ERROR_ACTIVE. 1549 */ 1550 if (intf_pending & MCP251XFD_REG_INT_CERRIF || 1551 priv->can.state > CAN_STATE_ERROR_ACTIVE) { 1552 err = mcp251xfd_handle(priv, cerrif); 1553 if (err) 1554 goto out_fail; 1555 1556 /* In Bus Off we completely shut down the 1557 * controller. Every subsequent register read 1558 * will read bogus data, and if 1559 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC 1560 * check will fail, too. So leave IRQ handler 1561 * directly. 1562 */ 1563 if (priv->can.state == CAN_STATE_BUS_OFF) { 1564 can_rx_offload_threaded_irq_finish(&priv->offload); 1565 return IRQ_HANDLED; 1566 } 1567 } 1568 1569 handled = IRQ_HANDLED; 1570 } while (1); 1571 1572 out_fail: 1573 can_rx_offload_threaded_irq_finish(&priv->offload); 1574 1575 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n", 1576 err, priv->regs_status.intf); 1577 mcp251xfd_dump(priv); 1578 mcp251xfd_chip_interrupts_disable(priv); 1579 mcp251xfd_timestamp_stop(priv); 1580 1581 return handled; 1582 } 1583 1584 static int mcp251xfd_open(struct net_device *ndev) 1585 { 1586 struct mcp251xfd_priv *priv = netdev_priv(ndev); 1587 const struct spi_device *spi = priv->spi; 1588 int err; 1589 1590 err = open_candev(ndev); 1591 if (err) 1592 return err; 1593 1594 err = pm_runtime_resume_and_get(ndev->dev.parent); 1595 if (err) 1596 goto out_close_candev; 1597 1598 err = mcp251xfd_ring_alloc(priv); 1599 if (err) 1600 goto out_pm_runtime_put; 1601 1602 err = mcp251xfd_transceiver_enable(priv); 1603 if (err) 1604 goto out_mcp251xfd_ring_free; 1605 1606 err = mcp251xfd_chip_start(priv); 1607 if (err) 1608 goto out_transceiver_disable; 1609 1610 mcp251xfd_timestamp_init(priv); 1611 clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 1612 can_rx_offload_enable(&priv->offload); 1613 1614 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq, 1615 IRQF_SHARED | IRQF_ONESHOT, 1616 dev_name(&spi->dev), priv); 1617 if (err) 1618 goto out_can_rx_offload_disable; 1619 1620 err = mcp251xfd_chip_interrupts_enable(priv); 1621 if (err) 1622 goto out_free_irq; 1623 1624 netif_start_queue(ndev); 1625 1626 return 0; 1627 1628 out_free_irq: 1629 free_irq(spi->irq, priv); 1630 out_can_rx_offload_disable: 1631 can_rx_offload_disable(&priv->offload); 1632 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 1633 mcp251xfd_timestamp_stop(priv); 1634 out_transceiver_disable: 1635 mcp251xfd_transceiver_disable(priv); 1636 out_mcp251xfd_ring_free: 1637 mcp251xfd_ring_free(priv); 1638 out_pm_runtime_put: 1639 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1640 pm_runtime_put(ndev->dev.parent); 1641 out_close_candev: 1642 close_candev(ndev); 1643 1644 return err; 1645 } 1646 1647 static int mcp251xfd_stop(struct net_device *ndev) 1648 { 1649 struct mcp251xfd_priv *priv = netdev_priv(ndev); 1650 1651 netif_stop_queue(ndev); 1652 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 1653 hrtimer_cancel(&priv->rx_irq_timer); 1654 hrtimer_cancel(&priv->tx_irq_timer); 1655 mcp251xfd_chip_interrupts_disable(priv); 1656 free_irq(ndev->irq, priv); 1657 can_rx_offload_disable(&priv->offload); 1658 mcp251xfd_timestamp_stop(priv); 1659 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1660 mcp251xfd_transceiver_disable(priv); 1661 mcp251xfd_ring_free(priv); 1662 close_candev(ndev); 1663 1664 pm_runtime_put(ndev->dev.parent); 1665 1666 return 0; 1667 } 1668 1669 static const struct net_device_ops mcp251xfd_netdev_ops = { 1670 .ndo_open = mcp251xfd_open, 1671 .ndo_stop = mcp251xfd_stop, 1672 .ndo_start_xmit = mcp251xfd_start_xmit, 1673 .ndo_change_mtu = can_change_mtu, 1674 }; 1675 1676 static void 1677 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv) 1678 { 1679 const struct spi_device *spi = priv->spi; 1680 const struct spi_controller *ctlr = spi->controller; 1681 1682 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX) 1683 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX; 1684 } 1685 1686 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv) 1687 { 1688 const struct net_device *ndev = priv->ndev; 1689 const struct mcp251xfd_devtype_data *devtype_data; 1690 u32 osc; 1691 int err; 1692 1693 /* The OSC_LPMEN is only supported on MCP2518FD, so use it to 1694 * autodetect the model. 1695 */ 1696 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC, 1697 MCP251XFD_REG_OSC_LPMEN, 1698 MCP251XFD_REG_OSC_LPMEN); 1699 if (err) 1700 return err; 1701 1702 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 1703 if (err) 1704 return err; 1705 1706 if (osc & MCP251XFD_REG_OSC_LPMEN) 1707 devtype_data = &mcp251xfd_devtype_data_mcp2518fd; 1708 else 1709 devtype_data = &mcp251xfd_devtype_data_mcp2517fd; 1710 1711 if (!mcp251xfd_is_251XFD(priv) && 1712 priv->devtype_data.model != devtype_data->model) { 1713 netdev_info(ndev, 1714 "Detected %s, but firmware specifies a %s. Fixing up.\n", 1715 __mcp251xfd_get_model_str(devtype_data->model), 1716 mcp251xfd_get_model_str(priv)); 1717 } 1718 priv->devtype_data = *devtype_data; 1719 1720 /* We need to preserve the Half Duplex Quirk. */ 1721 mcp251xfd_register_quirks(priv); 1722 1723 /* Re-init regmap with quirks of detected model. */ 1724 return mcp251xfd_regmap_init(priv); 1725 } 1726 1727 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv) 1728 { 1729 int err, rx_pending; 1730 1731 if (!priv->rx_int) 1732 return 0; 1733 1734 err = mcp251xfd_chip_rx_int_enable(priv); 1735 if (err) 1736 return err; 1737 1738 /* Check if RX_INT is properly working. The RX_INT should not 1739 * be active after a softreset. 1740 */ 1741 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 1742 1743 err = mcp251xfd_chip_rx_int_disable(priv); 1744 if (err) 1745 return err; 1746 1747 if (!rx_pending) 1748 return 0; 1749 1750 netdev_info(priv->ndev, 1751 "RX_INT active after softreset, disabling RX_INT support.\n"); 1752 devm_gpiod_put(&priv->spi->dev, priv->rx_int); 1753 priv->rx_int = NULL; 1754 1755 return 0; 1756 } 1757 1758 static int 1759 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id, 1760 u32 *effective_speed_hz_slow, 1761 u32 *effective_speed_hz_fast) 1762 { 1763 struct mcp251xfd_map_buf_nocrc *buf_rx; 1764 struct mcp251xfd_map_buf_nocrc *buf_tx; 1765 struct spi_transfer xfer[2] = { }; 1766 int err; 1767 1768 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL); 1769 if (!buf_rx) 1770 return -ENOMEM; 1771 1772 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL); 1773 if (!buf_tx) { 1774 err = -ENOMEM; 1775 goto out_kfree_buf_rx; 1776 } 1777 1778 xfer[0].tx_buf = buf_tx; 1779 xfer[0].len = sizeof(buf_tx->cmd); 1780 xfer[0].speed_hz = priv->spi_max_speed_hz_slow; 1781 xfer[1].rx_buf = buf_rx->data; 1782 xfer[1].len = sizeof(*dev_id); 1783 xfer[1].speed_hz = priv->spi_max_speed_hz_fast; 1784 1785 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID); 1786 1787 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer)); 1788 if (err) 1789 goto out_kfree_buf_tx; 1790 1791 *dev_id = get_unaligned_le32(buf_rx->data); 1792 *effective_speed_hz_slow = xfer[0].effective_speed_hz; 1793 *effective_speed_hz_fast = xfer[1].effective_speed_hz; 1794 1795 out_kfree_buf_tx: 1796 kfree(buf_tx); 1797 out_kfree_buf_rx: 1798 kfree(buf_rx); 1799 1800 return err; 1801 } 1802 1803 #define MCP251XFD_QUIRK_ACTIVE(quirk) \ 1804 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-') 1805 1806 static int 1807 mcp251xfd_register_done(const struct mcp251xfd_priv *priv) 1808 { 1809 u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast; 1810 unsigned long clk_rate; 1811 int err; 1812 1813 err = mcp251xfd_register_get_dev_id(priv, &dev_id, 1814 &effective_speed_hz_slow, 1815 &effective_speed_hz_fast); 1816 if (err) 1817 return err; 1818 1819 clk_rate = clk_get_rate(priv->clk); 1820 1821 netdev_info(priv->ndev, 1822 "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n", 1823 mcp251xfd_get_model_str(priv), 1824 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id), 1825 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id), 1826 priv->rx_int ? '+' : '-', 1827 priv->pll_enable ? '+' : '-', 1828 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN), 1829 MCP251XFD_QUIRK_ACTIVE(CRC_REG), 1830 MCP251XFD_QUIRK_ACTIVE(CRC_RX), 1831 MCP251XFD_QUIRK_ACTIVE(CRC_TX), 1832 MCP251XFD_QUIRK_ACTIVE(ECC), 1833 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX), 1834 clk_rate / 1000000, 1835 clk_rate % 1000000 / 1000 / 10, 1836 priv->can.clock.freq / 1000000, 1837 priv->can.clock.freq % 1000000 / 1000 / 10, 1838 priv->spi_max_speed_hz_orig / 1000000, 1839 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10, 1840 priv->spi_max_speed_hz_slow / 1000000, 1841 priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10, 1842 effective_speed_hz_slow / 1000000, 1843 effective_speed_hz_slow % 1000000 / 1000 / 10, 1844 priv->spi_max_speed_hz_fast / 1000000, 1845 priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10, 1846 effective_speed_hz_fast / 1000000, 1847 effective_speed_hz_fast % 1000000 / 1000 / 10); 1848 1849 return 0; 1850 } 1851 1852 static int mcp251xfd_register(struct mcp251xfd_priv *priv) 1853 { 1854 struct net_device *ndev = priv->ndev; 1855 int err; 1856 1857 err = mcp251xfd_clks_and_vdd_enable(priv); 1858 if (err) 1859 return err; 1860 1861 pm_runtime_get_noresume(ndev->dev.parent); 1862 err = pm_runtime_set_active(ndev->dev.parent); 1863 if (err) 1864 goto out_runtime_put_noidle; 1865 pm_runtime_enable(ndev->dev.parent); 1866 1867 mcp251xfd_register_quirks(priv); 1868 1869 err = mcp251xfd_chip_softreset(priv); 1870 if (err == -ENODEV) 1871 goto out_runtime_disable; 1872 if (err) 1873 goto out_chip_sleep; 1874 1875 err = mcp251xfd_chip_clock_init(priv); 1876 if (err == -ENODEV) 1877 goto out_runtime_disable; 1878 if (err) 1879 goto out_chip_sleep; 1880 1881 err = mcp251xfd_register_chip_detect(priv); 1882 if (err) 1883 goto out_chip_sleep; 1884 1885 err = mcp251xfd_register_check_rx_int(priv); 1886 if (err) 1887 goto out_chip_sleep; 1888 1889 mcp251xfd_ethtool_init(priv); 1890 1891 err = register_candev(ndev); 1892 if (err) 1893 goto out_chip_sleep; 1894 1895 err = mcp251xfd_register_done(priv); 1896 if (err) 1897 goto out_unregister_candev; 1898 1899 /* Put controller into sleep mode and let pm_runtime_put() 1900 * disable the clocks and vdd. If CONFIG_PM is not enabled, 1901 * the clocks and vdd will stay powered. 1902 */ 1903 err = mcp251xfd_chip_sleep(priv); 1904 if (err) 1905 goto out_unregister_candev; 1906 1907 pm_runtime_put(ndev->dev.parent); 1908 1909 return 0; 1910 1911 out_unregister_candev: 1912 unregister_candev(ndev); 1913 out_chip_sleep: 1914 mcp251xfd_chip_sleep(priv); 1915 out_runtime_disable: 1916 pm_runtime_disable(ndev->dev.parent); 1917 out_runtime_put_noidle: 1918 pm_runtime_put_noidle(ndev->dev.parent); 1919 mcp251xfd_clks_and_vdd_disable(priv); 1920 1921 return err; 1922 } 1923 1924 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv) 1925 { 1926 struct net_device *ndev = priv->ndev; 1927 1928 unregister_candev(ndev); 1929 1930 if (pm_runtime_enabled(ndev->dev.parent)) 1931 pm_runtime_disable(ndev->dev.parent); 1932 else 1933 mcp251xfd_clks_and_vdd_disable(priv); 1934 } 1935 1936 static const struct of_device_id mcp251xfd_of_match[] = { 1937 { 1938 .compatible = "microchip,mcp2517fd", 1939 .data = &mcp251xfd_devtype_data_mcp2517fd, 1940 }, { 1941 .compatible = "microchip,mcp2518fd", 1942 .data = &mcp251xfd_devtype_data_mcp2518fd, 1943 }, { 1944 .compatible = "microchip,mcp251863", 1945 .data = &mcp251xfd_devtype_data_mcp251863, 1946 }, { 1947 .compatible = "microchip,mcp251xfd", 1948 .data = &mcp251xfd_devtype_data_mcp251xfd, 1949 }, { 1950 /* sentinel */ 1951 }, 1952 }; 1953 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match); 1954 1955 static const struct spi_device_id mcp251xfd_id_table[] = { 1956 { 1957 .name = "mcp2517fd", 1958 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd, 1959 }, { 1960 .name = "mcp2518fd", 1961 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd, 1962 }, { 1963 .name = "mcp251863", 1964 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863, 1965 }, { 1966 .name = "mcp251xfd", 1967 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd, 1968 }, { 1969 /* sentinel */ 1970 }, 1971 }; 1972 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table); 1973 1974 static int mcp251xfd_probe(struct spi_device *spi) 1975 { 1976 const void *match; 1977 struct net_device *ndev; 1978 struct mcp251xfd_priv *priv; 1979 struct gpio_desc *rx_int; 1980 struct regulator *reg_vdd, *reg_xceiver; 1981 struct clk *clk; 1982 bool pll_enable = false; 1983 u32 freq = 0; 1984 int err; 1985 1986 if (!spi->irq) 1987 return dev_err_probe(&spi->dev, -ENXIO, 1988 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n"); 1989 1990 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int", 1991 GPIOD_IN); 1992 if (IS_ERR(rx_int)) 1993 return dev_err_probe(&spi->dev, PTR_ERR(rx_int), 1994 "Failed to get RX-INT!\n"); 1995 1996 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd"); 1997 if (PTR_ERR(reg_vdd) == -ENODEV) 1998 reg_vdd = NULL; 1999 else if (IS_ERR(reg_vdd)) 2000 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd), 2001 "Failed to get VDD regulator!\n"); 2002 2003 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 2004 if (PTR_ERR(reg_xceiver) == -ENODEV) 2005 reg_xceiver = NULL; 2006 else if (IS_ERR(reg_xceiver)) 2007 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver), 2008 "Failed to get Transceiver regulator!\n"); 2009 2010 clk = devm_clk_get_optional(&spi->dev, NULL); 2011 if (IS_ERR(clk)) 2012 return dev_err_probe(&spi->dev, PTR_ERR(clk), 2013 "Failed to get Oscillator (clock)!\n"); 2014 if (clk) { 2015 freq = clk_get_rate(clk); 2016 } else { 2017 err = device_property_read_u32(&spi->dev, "clock-frequency", 2018 &freq); 2019 if (err) 2020 return dev_err_probe(&spi->dev, err, 2021 "Failed to get clock-frequency!\n"); 2022 } 2023 2024 /* Sanity check */ 2025 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN || 2026 freq > MCP251XFD_SYSCLOCK_HZ_MAX) { 2027 dev_err(&spi->dev, 2028 "Oscillator frequency (%u Hz) is too low or high.\n", 2029 freq); 2030 return -ERANGE; 2031 } 2032 2033 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER) 2034 pll_enable = true; 2035 2036 ndev = alloc_candev(sizeof(struct mcp251xfd_priv), 2037 MCP251XFD_TX_OBJ_NUM_MAX); 2038 if (!ndev) 2039 return -ENOMEM; 2040 2041 SET_NETDEV_DEV(ndev, &spi->dev); 2042 2043 ndev->netdev_ops = &mcp251xfd_netdev_ops; 2044 ndev->irq = spi->irq; 2045 ndev->flags |= IFF_ECHO; 2046 2047 priv = netdev_priv(ndev); 2048 spi_set_drvdata(spi, priv); 2049 priv->can.clock.freq = freq; 2050 if (pll_enable) 2051 priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER; 2052 priv->can.do_set_mode = mcp251xfd_set_mode; 2053 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter; 2054 priv->can.bittiming_const = &mcp251xfd_bittiming_const; 2055 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const; 2056 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 2057 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING | 2058 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO | 2059 CAN_CTRLMODE_CC_LEN8_DLC; 2060 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 2061 priv->ndev = ndev; 2062 priv->spi = spi; 2063 priv->rx_int = rx_int; 2064 priv->clk = clk; 2065 priv->pll_enable = pll_enable; 2066 priv->reg_vdd = reg_vdd; 2067 priv->reg_xceiver = reg_xceiver; 2068 2069 match = device_get_match_data(&spi->dev); 2070 if (match) 2071 priv->devtype_data = *(struct mcp251xfd_devtype_data *)match; 2072 else 2073 priv->devtype_data = *(struct mcp251xfd_devtype_data *) 2074 spi_get_device_id(spi)->driver_data; 2075 2076 /* Errata Reference: 2077 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4. 2078 * 2079 * The SPI can write corrupted data to the RAM at fast SPI 2080 * speeds: 2081 * 2082 * Simultaneous activity on the CAN bus while writing data to 2083 * RAM via the SPI interface, with high SCK frequency, can 2084 * lead to corrupted data being written to RAM. 2085 * 2086 * Fix/Work Around: 2087 * Ensure that FSCK is less than or equal to 0.85 * 2088 * (FSYSCLK/2). 2089 * 2090 * Known good combinations are: 2091 * 2092 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config 2093 * 2094 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> 2095 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> 2096 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default 2097 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default 2098 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default 2099 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT> 2100 * 2101 */ 2102 priv->spi_max_speed_hz_orig = spi->max_speed_hz; 2103 priv->spi_max_speed_hz_slow = min(spi->max_speed_hz, 2104 freq / 2 / 1000 * 850); 2105 if (priv->pll_enable) 2106 priv->spi_max_speed_hz_fast = min(spi->max_speed_hz, 2107 freq * 2108 MCP251XFD_OSC_PLL_MULTIPLIER / 2109 2 / 1000 * 850); 2110 else 2111 priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow; 2112 spi->max_speed_hz = priv->spi_max_speed_hz_slow; 2113 spi->bits_per_word = 8; 2114 spi->rt = true; 2115 err = spi_setup(spi); 2116 if (err) 2117 goto out_free_candev; 2118 2119 err = mcp251xfd_regmap_init(priv); 2120 if (err) 2121 goto out_free_candev; 2122 2123 err = can_rx_offload_add_manual(ndev, &priv->offload, 2124 MCP251XFD_NAPI_WEIGHT); 2125 if (err) 2126 goto out_free_candev; 2127 2128 err = mcp251xfd_register(priv); 2129 if (err) { 2130 dev_err_probe(&spi->dev, err, "Failed to detect %s.\n", 2131 mcp251xfd_get_model_str(priv)); 2132 goto out_can_rx_offload_del; 2133 } 2134 2135 return 0; 2136 2137 out_can_rx_offload_del: 2138 can_rx_offload_del(&priv->offload); 2139 out_free_candev: 2140 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 2141 2142 free_candev(ndev); 2143 2144 return err; 2145 } 2146 2147 static void mcp251xfd_remove(struct spi_device *spi) 2148 { 2149 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 2150 struct net_device *ndev = priv->ndev; 2151 2152 can_rx_offload_del(&priv->offload); 2153 mcp251xfd_unregister(priv); 2154 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 2155 free_candev(ndev); 2156 } 2157 2158 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device) 2159 { 2160 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 2161 2162 return mcp251xfd_clks_and_vdd_disable(priv); 2163 } 2164 2165 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device) 2166 { 2167 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 2168 2169 return mcp251xfd_clks_and_vdd_enable(priv); 2170 } 2171 2172 static const struct dev_pm_ops mcp251xfd_pm_ops = { 2173 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend, 2174 mcp251xfd_runtime_resume, NULL) 2175 }; 2176 2177 static struct spi_driver mcp251xfd_driver = { 2178 .driver = { 2179 .name = DEVICE_NAME, 2180 .pm = &mcp251xfd_pm_ops, 2181 .of_match_table = mcp251xfd_of_match, 2182 }, 2183 .probe = mcp251xfd_probe, 2184 .remove = mcp251xfd_remove, 2185 .id_table = mcp251xfd_id_table, 2186 }; 2187 module_spi_driver(mcp251xfd_driver); 2188 2189 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 2190 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver"); 2191 MODULE_LICENSE("GPL v2"); 2192