1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Microchip KSZ9477 register definitions 4 * 5 * Copyright (C) 2017-2018 Microchip Technology Inc. 6 */ 7 8 #ifndef __KSZ9477_REGS_H 9 #define __KSZ9477_REGS_H 10 11 #define KS_PRIO_M 0x7 12 #define KS_PRIO_S 4 13 14 /* 0 - Operation */ 15 #define REG_CHIP_ID0__1 0x0000 16 17 #define REG_CHIP_ID1__1 0x0001 18 19 #define FAMILY_ID 0x95 20 #define FAMILY_ID_94 0x94 21 #define FAMILY_ID_95 0x95 22 #define FAMILY_ID_85 0x85 23 #define FAMILY_ID_98 0x98 24 #define FAMILY_ID_88 0x88 25 26 #define REG_CHIP_ID2__1 0x0002 27 28 #define CHIP_ID_66 0x66 29 #define CHIP_ID_67 0x67 30 #define CHIP_ID_77 0x77 31 #define CHIP_ID_93 0x93 32 #define CHIP_ID_96 0x96 33 #define CHIP_ID_97 0x97 34 35 #define REG_CHIP_ID3__1 0x0003 36 37 #define SWITCH_REVISION_M 0x0F 38 #define SWITCH_REVISION_S 4 39 #define SWITCH_RESET 0x01 40 41 #define REG_SW_PME_CTRL 0x0006 42 43 #define PME_ENABLE BIT(1) 44 #define PME_POLARITY BIT(0) 45 46 #define REG_GLOBAL_OPTIONS 0x000F 47 48 #define SW_GIGABIT_ABLE BIT(6) 49 #define SW_REDUNDANCY_ABLE BIT(5) 50 #define SW_AVB_ABLE BIT(4) 51 #define SW_9567_RL_5_2 0xC 52 #define SW_9477_SL_5_2 0xD 53 54 #define SW_9896_GL_5_1 0xB 55 #define SW_9896_RL_5_1 0x8 56 #define SW_9896_SL_5_1 0x9 57 58 #define SW_9895_GL_4_1 0x7 59 #define SW_9895_RL_4_1 0x4 60 #define SW_9895_SL_4_1 0x5 61 62 #define SW_9896_RL_4_2 0x6 63 64 #define SW_9893_RL_2_1 0x0 65 #define SW_9893_SL_2_1 0x1 66 #define SW_9893_GL_2_1 0x3 67 68 #define SW_QW_ABLE BIT(5) 69 #define SW_9893_RN_2_1 0xC 70 71 #define REG_SW_INT_STATUS__4 0x0010 72 #define REG_SW_INT_MASK__4 0x0014 73 74 #define LUE_INT BIT(31) 75 #define TRIG_TS_INT BIT(30) 76 #define APB_TIMEOUT_INT BIT(29) 77 78 #define SWITCH_INT_MASK (TRIG_TS_INT | APB_TIMEOUT_INT) 79 80 #define REG_SW_PORT_INT_STATUS__4 0x0018 81 #define REG_SW_PORT_INT_MASK__4 0x001C 82 #define REG_SW_PHY_INT_STATUS 0x0020 83 #define REG_SW_PHY_INT_ENABLE 0x0024 84 85 /* 1 - Global */ 86 #define REG_SW_GLOBAL_SERIAL_CTRL_0 0x0100 87 #define SW_SPARE_REG_2 BIT(7) 88 #define SW_SPARE_REG_1 BIT(6) 89 #define SW_SPARE_REG_0 BIT(5) 90 #define SW_BIG_ENDIAN BIT(4) 91 #define SPI_AUTO_EDGE_DETECTION BIT(1) 92 #define SPI_CLOCK_OUT_RISING_EDGE BIT(0) 93 94 #define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103 95 #define SW_ENABLE_REFCLKO BIT(1) 96 #define SW_REFCLKO_IS_125MHZ BIT(0) 97 98 #define REG_SW_IBA__4 0x0104 99 100 #define SW_IBA_ENABLE BIT(31) 101 #define SW_IBA_DA_MATCH BIT(30) 102 #define SW_IBA_INIT BIT(29) 103 #define SW_IBA_QID_M 0xF 104 #define SW_IBA_QID_S 22 105 #define SW_IBA_PORT_M 0x2F 106 #define SW_IBA_PORT_S 16 107 #define SW_IBA_FRAME_TPID_M 0xFFFF 108 109 #define REG_SW_APB_TIMEOUT_ADDR__4 0x0108 110 111 #define APB_TIMEOUT_ACKNOWLEDGE BIT(31) 112 113 #define REG_SW_IBA_SYNC__1 0x010C 114 115 #define REG_SW_IBA_STATUS__4 0x0110 116 117 #define SW_IBA_REQ BIT(31) 118 #define SW_IBA_RESP BIT(30) 119 #define SW_IBA_DA_MISMATCH BIT(14) 120 #define SW_IBA_FMT_MISMATCH BIT(13) 121 #define SW_IBA_CODE_ERROR BIT(12) 122 #define SW_IBA_CMD_ERROR BIT(11) 123 #define SW_IBA_CMD_LOC_M (BIT(6) - 1) 124 125 #define REG_SW_IBA_STATES__4 0x0114 126 127 #define SW_IBA_BUF_STATE_S 30 128 #define SW_IBA_CMD_STATE_S 28 129 #define SW_IBA_RESP_STATE_S 26 130 #define SW_IBA_STATE_M 0x3 131 #define SW_IBA_PACKET_SIZE_M 0x7F 132 #define SW_IBA_PACKET_SIZE_S 16 133 #define SW_IBA_FMT_ID_M 0xFFFF 134 135 #define REG_SW_IBA_RESULT__4 0x0118 136 137 #define SW_IBA_SIZE_S 24 138 139 #define SW_IBA_RETRY_CNT_M (BIT(5) - 1) 140 141 /* 2 - PHY */ 142 #define REG_SW_POWER_MANAGEMENT_CTRL 0x0201 143 144 #define SW_PLL_POWER_DOWN BIT(5) 145 #define SW_POWER_DOWN_MODE 0x3 146 #define SW_ENERGY_DETECTION 1 147 #define SW_SOFT_POWER_DOWN 2 148 #define SW_POWER_SAVING 3 149 150 /* 3 - Operation Control */ 151 #define REG_SW_OPERATION 0x0300 152 153 #define SW_DOUBLE_TAG BIT(7) 154 #define SW_RESET BIT(1) 155 156 #define REG_SW_MTU__2 0x0308 157 #define REG_SW_MTU_MASK GENMASK(13, 0) 158 159 #define REG_SW_ISP_TPID__2 0x030A 160 161 #define REG_SW_HSR_TPID__2 0x030C 162 163 #define REG_AVB_STRATEGY__2 0x030E 164 165 #define SW_SHAPING_CREDIT_ACCT BIT(1) 166 #define SW_POLICING_CREDIT_ACCT BIT(0) 167 168 #define REG_SW_LUE_CTRL_0 0x0310 169 170 #define SW_VLAN_ENABLE BIT(7) 171 #define SW_DROP_INVALID_VID BIT(6) 172 #define SW_AGE_CNT_M GENMASK(5, 3) 173 #define SW_AGE_CNT_S 3 174 #define SW_AGE_PERIOD_10_8_M GENMASK(10, 8) 175 #define SW_RESV_MCAST_ENABLE BIT(2) 176 #define SW_HASH_OPTION_M 0x03 177 #define SW_HASH_OPTION_CRC 1 178 #define SW_HASH_OPTION_XOR 2 179 #define SW_HASH_OPTION_DIRECT 3 180 181 #define REG_SW_LUE_CTRL_1 0x0311 182 183 #define UNICAST_LEARN_DISABLE BIT(7) 184 #define SW_SRC_ADDR_FILTER BIT(6) 185 #define SW_FLUSH_STP_TABLE BIT(5) 186 #define SW_FLUSH_MSTP_TABLE BIT(4) 187 #define SW_FWD_MCAST_SRC_ADDR BIT(3) 188 #define SW_AGING_ENABLE BIT(2) 189 #define SW_FAST_AGING BIT(1) 190 #define SW_LINK_AUTO_AGING BIT(0) 191 192 #define REG_SW_LUE_CTRL_2 0x0312 193 194 #define SW_TRAP_DOUBLE_TAG BIT(6) 195 #define SW_EGRESS_VLAN_FILTER_DYN BIT(5) 196 #define SW_EGRESS_VLAN_FILTER_STA BIT(4) 197 #define SW_FLUSH_OPTION_M 0x3 198 #define SW_FLUSH_OPTION_S 2 199 #define SW_FLUSH_OPTION_DYN_MAC 1 200 #define SW_FLUSH_OPTION_STA_MAC 2 201 #define SW_FLUSH_OPTION_BOTH 3 202 #define SW_PRIO_M 0x3 203 #define SW_PRIO_DA 0 204 #define SW_PRIO_SA 1 205 #define SW_PRIO_HIGHEST_DA_SA 2 206 #define SW_PRIO_LOWEST_DA_SA 3 207 208 #define REG_SW_LUE_CTRL_3 0x0313 209 #define SW_AGE_PERIOD_7_0_M GENMASK(7, 0) 210 211 #define REG_SW_LUE_INT_STATUS 0x0314 212 #define REG_SW_LUE_INT_ENABLE 0x0315 213 214 #define LEARN_FAIL_INT BIT(2) 215 #define ALMOST_FULL_INT BIT(1) 216 #define WRITE_FAIL_INT BIT(0) 217 218 #define REG_SW_LUE_INDEX_0__2 0x0316 219 220 #define ENTRY_INDEX_M 0x0FFF 221 222 #define REG_SW_LUE_INDEX_1__2 0x0318 223 224 #define FAIL_INDEX_M 0x03FF 225 226 #define REG_SW_LUE_INDEX_2__2 0x031A 227 228 #define REG_SW_LUE_UNK_UCAST_CTRL__4 0x0320 229 230 #define SW_UNK_UCAST_ENABLE BIT(31) 231 232 #define REG_SW_LUE_UNK_MCAST_CTRL__4 0x0324 233 234 #define SW_UNK_MCAST_ENABLE BIT(31) 235 236 #define REG_SW_LUE_UNK_VID_CTRL__4 0x0328 237 238 #define SW_UNK_VID_ENABLE BIT(31) 239 240 #define REG_SW_MAC_CTRL_0 0x0330 241 242 #define SW_NEW_BACKOFF BIT(7) 243 #define SW_CHECK_LENGTH BIT(3) 244 #define SW_PAUSE_UNH_MODE BIT(1) 245 #define SW_AGGR_BACKOFF BIT(0) 246 247 #define REG_SW_MAC_CTRL_1 0x0331 248 249 #define SW_BACK_PRESSURE BIT(5) 250 #define FAIR_FLOW_CTRL BIT(4) 251 #define NO_EXC_COLLISION_DROP BIT(3) 252 #define SW_JUMBO_PACKET BIT(2) 253 #define SW_LEGAL_PACKET_DISABLE BIT(1) 254 #define SW_PASS_SHORT_FRAME BIT(0) 255 256 #define REG_SW_MAC_CTRL_2 0x0332 257 258 #define SW_REPLACE_VID BIT(3) 259 260 #define REG_SW_MAC_CTRL_3 0x0333 261 262 #define REG_SW_MAC_CTRL_4 0x0334 263 264 #define SW_PASS_PAUSE BIT(3) 265 266 #define REG_SW_MAC_CTRL_5 0x0335 267 268 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3) 269 270 #define REG_SW_MAC_CTRL_6 0x0336 271 272 #define SW_MIB_COUNTER_FLUSH BIT(7) 273 #define SW_MIB_COUNTER_FREEZE BIT(6) 274 275 #define REG_SW_MAC_802_1P_MAP_0 0x0338 276 #define REG_SW_MAC_802_1P_MAP_1 0x0339 277 #define REG_SW_MAC_802_1P_MAP_2 0x033A 278 #define REG_SW_MAC_802_1P_MAP_3 0x033B 279 280 #define SW_802_1P_MAP_M KS_PRIO_M 281 #define SW_802_1P_MAP_S KS_PRIO_S 282 283 #define REG_SW_MAC_ISP_CTRL 0x033C 284 285 #define REG_SW_MAC_TOS_CTRL 0x033E 286 287 #define SW_TOS_DSCP_REMARK BIT(1) 288 #define SW_TOS_DSCP_REMAP BIT(0) 289 290 #define REG_SW_MAC_TOS_PRIO_0 0x0340 291 #define REG_SW_MAC_TOS_PRIO_1 0x0341 292 #define REG_SW_MAC_TOS_PRIO_2 0x0342 293 #define REG_SW_MAC_TOS_PRIO_3 0x0343 294 #define REG_SW_MAC_TOS_PRIO_4 0x0344 295 #define REG_SW_MAC_TOS_PRIO_5 0x0345 296 #define REG_SW_MAC_TOS_PRIO_6 0x0346 297 #define REG_SW_MAC_TOS_PRIO_7 0x0347 298 #define REG_SW_MAC_TOS_PRIO_8 0x0348 299 #define REG_SW_MAC_TOS_PRIO_9 0x0349 300 #define REG_SW_MAC_TOS_PRIO_10 0x034A 301 #define REG_SW_MAC_TOS_PRIO_11 0x034B 302 #define REG_SW_MAC_TOS_PRIO_12 0x034C 303 #define REG_SW_MAC_TOS_PRIO_13 0x034D 304 #define REG_SW_MAC_TOS_PRIO_14 0x034E 305 #define REG_SW_MAC_TOS_PRIO_15 0x034F 306 #define REG_SW_MAC_TOS_PRIO_16 0x0350 307 #define REG_SW_MAC_TOS_PRIO_17 0x0351 308 #define REG_SW_MAC_TOS_PRIO_18 0x0352 309 #define REG_SW_MAC_TOS_PRIO_19 0x0353 310 #define REG_SW_MAC_TOS_PRIO_20 0x0354 311 #define REG_SW_MAC_TOS_PRIO_21 0x0355 312 #define REG_SW_MAC_TOS_PRIO_22 0x0356 313 #define REG_SW_MAC_TOS_PRIO_23 0x0357 314 #define REG_SW_MAC_TOS_PRIO_24 0x0358 315 #define REG_SW_MAC_TOS_PRIO_25 0x0359 316 #define REG_SW_MAC_TOS_PRIO_26 0x035A 317 #define REG_SW_MAC_TOS_PRIO_27 0x035B 318 #define REG_SW_MAC_TOS_PRIO_28 0x035C 319 #define REG_SW_MAC_TOS_PRIO_29 0x035D 320 #define REG_SW_MAC_TOS_PRIO_30 0x035E 321 #define REG_SW_MAC_TOS_PRIO_31 0x035F 322 323 #define REG_SW_MRI_CTRL_0 0x0370 324 325 #define SW_IGMP_SNOOP BIT(6) 326 #define SW_IPV6_MLD_OPTION BIT(3) 327 #define SW_IPV6_MLD_SNOOP BIT(2) 328 #define SW_MIRROR_RX_TX BIT(0) 329 330 #define REG_SW_CLASS_D_IP_CTRL__4 0x0374 331 332 #define SW_CLASS_D_IP_ENABLE BIT(31) 333 334 #define REG_SW_MRI_CTRL_8 0x0378 335 336 #define SW_NO_COLOR_S 6 337 #define SW_RED_COLOR_S 4 338 #define SW_YELLOW_COLOR_S 2 339 #define SW_GREEN_COLOR_S 0 340 #define SW_COLOR_M 0x3 341 342 #define REG_SW_QM_CTRL__4 0x0390 343 344 #define PRIO_SCHEME_SELECT_M KS_PRIO_M 345 #define PRIO_SCHEME_SELECT_S 6 346 #define PRIO_MAP_3_HI 0 347 #define PRIO_MAP_2_HI 2 348 #define PRIO_MAP_0_LO 3 349 #define UNICAST_VLAN_BOUNDARY BIT(1) 350 351 #define REG_SW_EEE_QM_CTRL__2 0x03C0 352 353 #define REG_SW_EEE_TXQ_WAIT_TIME__2 0x03C2 354 355 /* 4 - */ 356 #define REG_SW_VLAN_ENTRY__4 0x0400 357 358 #define VLAN_VALID BIT(31) 359 #define VLAN_FORWARD_OPTION BIT(27) 360 #define VLAN_PRIO_M KS_PRIO_M 361 #define VLAN_PRIO_S 24 362 #define VLAN_MSTP_M 0x7 363 #define VLAN_MSTP_S 12 364 #define VLAN_FID_M 0x7F 365 366 #define REG_SW_VLAN_ENTRY_UNTAG__4 0x0404 367 #define REG_SW_VLAN_ENTRY_PORTS__4 0x0408 368 369 #define REG_SW_VLAN_ENTRY_INDEX__2 0x040C 370 371 #define VLAN_INDEX_M 0x0FFF 372 373 #define REG_SW_VLAN_CTRL 0x040E 374 375 #define VLAN_START BIT(7) 376 #define VLAN_ACTION 0x3 377 #define VLAN_WRITE 1 378 #define VLAN_READ 2 379 #define VLAN_CLEAR 3 380 381 #define REG_SW_ALU_INDEX_0 0x0410 382 383 #define ALU_FID_INDEX_S 16 384 #define ALU_MAC_ADDR_HI 0xFFFF 385 386 #define REG_SW_ALU_INDEX_1 0x0414 387 388 #define ALU_DIRECT_INDEX_M (BIT(12) - 1) 389 390 #define REG_SW_ALU_CTRL__4 0x0418 391 392 #define ALU_VALID_CNT_M (BIT(14) - 1) 393 #define ALU_VALID_CNT_S 16 394 #define ALU_START BIT(7) 395 #define ALU_VALID BIT(6) 396 #define ALU_DIRECT BIT(2) 397 #define ALU_ACTION 0x3 398 #define ALU_WRITE 1 399 #define ALU_READ 2 400 #define ALU_SEARCH 3 401 402 #define REG_SW_ALU_STAT_CTRL__4 0x041C 403 404 #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1) 405 #define ALU_STAT_START BIT(7) 406 #define ALU_RESV_MCAST_ADDR BIT(1) 407 408 #define REG_SW_ALU_VAL_A 0x0420 409 410 #define ALU_V_STATIC_VALID BIT(31) 411 #define ALU_V_SRC_FILTER BIT(30) 412 #define ALU_V_DST_FILTER BIT(29) 413 #define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1) 414 #define ALU_V_PRIO_AGE_CNT_S 26 415 #define ALU_V_MSTP_M 0x7 416 417 #define REG_SW_ALU_VAL_B 0x0424 418 419 #define ALU_V_OVERRIDE BIT(31) 420 #define ALU_V_USE_FID BIT(30) 421 #define ALU_V_PORT_MAP (BIT(24) - 1) 422 423 #define REG_SW_ALU_VAL_C 0x0428 424 425 #define ALU_V_FID_M (BIT(16) - 1) 426 #define ALU_V_FID_S 16 427 #define ALU_V_MAC_ADDR_HI 0xFFFF 428 429 #define REG_SW_ALU_VAL_D 0x042C 430 431 #define REG_HSR_ALU_INDEX_0 0x0440 432 433 #define REG_HSR_ALU_INDEX_1 0x0444 434 435 #define HSR_DST_MAC_INDEX_LO_S 16 436 #define HSR_SRC_MAC_INDEX_HI 0xFFFF 437 438 #define REG_HSR_ALU_INDEX_2 0x0448 439 440 #define HSR_INDEX_MAX BIT(9) 441 #define HSR_DIRECT_INDEX_M (HSR_INDEX_MAX - 1) 442 443 #define REG_HSR_ALU_INDEX_3 0x044C 444 445 #define HSR_PATH_INDEX_M (BIT(4) - 1) 446 447 #define REG_HSR_ALU_CTRL__4 0x0450 448 449 #define HSR_VALID_CNT_M (BIT(14) - 1) 450 #define HSR_VALID_CNT_S 16 451 #define HSR_START BIT(7) 452 #define HSR_VALID BIT(6) 453 #define HSR_SEARCH_END BIT(5) 454 #define HSR_DIRECT BIT(2) 455 #define HSR_ACTION 0x3 456 #define HSR_WRITE 1 457 #define HSR_READ 2 458 #define HSR_SEARCH 3 459 460 #define REG_HSR_ALU_VAL_A 0x0454 461 462 #define HSR_V_STATIC_VALID BIT(31) 463 #define HSR_V_AGE_CNT_M (BIT(3) - 1) 464 #define HSR_V_AGE_CNT_S 26 465 #define HSR_V_PATH_ID_M (BIT(4) - 1) 466 467 #define REG_HSR_ALU_VAL_B 0x0458 468 469 #define REG_HSR_ALU_VAL_C 0x045C 470 471 #define HSR_V_DST_MAC_ADDR_LO_S 16 472 #define HSR_V_SRC_MAC_ADDR_HI 0xFFFF 473 474 #define REG_HSR_ALU_VAL_D 0x0460 475 476 #define REG_HSR_ALU_VAL_E 0x0464 477 478 #define HSR_V_START_SEQ_1_S 16 479 #define HSR_V_START_SEQ_2_S 0 480 481 #define REG_HSR_ALU_VAL_F 0x0468 482 483 #define HSR_V_EXP_SEQ_1_S 16 484 #define HSR_V_EXP_SEQ_2_S 0 485 486 #define REG_HSR_ALU_VAL_G 0x046C 487 488 #define HSR_V_SEQ_CNT_1_S 16 489 #define HSR_V_SEQ_CNT_2_S 0 490 491 #define HSR_V_SEQ_M (BIT(16) - 1) 492 493 /* 5 - PTP Clock */ 494 #define REG_PTP_CLK_CTRL 0x0500 495 496 #define PTP_STEP_ADJ BIT(6) 497 #define PTP_STEP_DIR BIT(5) 498 #define PTP_READ_TIME BIT(4) 499 #define PTP_LOAD_TIME BIT(3) 500 #define PTP_CLK_ADJ_ENABLE BIT(2) 501 #define PTP_CLK_ENABLE BIT(1) 502 #define PTP_CLK_RESET BIT(0) 503 504 #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502 505 506 #define PTP_RTC_SUB_NANOSEC_M 0x0007 507 508 #define REG_PTP_RTC_NANOSEC 0x0504 509 #define REG_PTP_RTC_NANOSEC_H 0x0504 510 #define REG_PTP_RTC_NANOSEC_L 0x0506 511 512 #define REG_PTP_RTC_SEC 0x0508 513 #define REG_PTP_RTC_SEC_H 0x0508 514 #define REG_PTP_RTC_SEC_L 0x050A 515 516 #define REG_PTP_SUBNANOSEC_RATE 0x050C 517 #define REG_PTP_SUBNANOSEC_RATE_H 0x050C 518 519 #define PTP_RATE_DIR BIT(31) 520 #define PTP_TMP_RATE_ENABLE BIT(30) 521 522 #define REG_PTP_SUBNANOSEC_RATE_L 0x050E 523 524 #define REG_PTP_RATE_DURATION 0x0510 525 #define REG_PTP_RATE_DURATION_H 0x0510 526 #define REG_PTP_RATE_DURATION_L 0x0512 527 528 #define REG_PTP_MSG_CONF1 0x0514 529 530 #define PTP_802_1AS BIT(7) 531 #define PTP_ENABLE BIT(6) 532 #define PTP_ETH_ENABLE BIT(5) 533 #define PTP_IPV4_UDP_ENABLE BIT(4) 534 #define PTP_IPV6_UDP_ENABLE BIT(3) 535 #define PTP_TC_P2P BIT(2) 536 #define PTP_MASTER BIT(1) 537 #define PTP_1STEP BIT(0) 538 539 #define REG_PTP_MSG_CONF2 0x0516 540 541 #define PTP_UNICAST_ENABLE BIT(12) 542 #define PTP_ALTERNATE_MASTER BIT(11) 543 #define PTP_ALL_HIGH_PRIO BIT(10) 544 #define PTP_SYNC_CHECK BIT(9) 545 #define PTP_DELAY_CHECK BIT(8) 546 #define PTP_PDELAY_CHECK BIT(7) 547 #define PTP_DROP_SYNC_DELAY_REQ BIT(5) 548 #define PTP_DOMAIN_CHECK BIT(4) 549 #define PTP_UDP_CHECKSUM BIT(2) 550 551 #define REG_PTP_DOMAIN_VERSION 0x0518 552 #define PTP_VERSION_M 0xFF00 553 #define PTP_DOMAIN_M 0x00FF 554 555 #define REG_PTP_UNIT_INDEX__4 0x0520 556 557 #define PTP_UNIT_M 0xF 558 559 #define PTP_GPIO_INDEX_S 16 560 #define PTP_TSI_INDEX_S 8 561 #define PTP_TOU_INDEX_S 0 562 563 #define REG_PTP_TRIG_STATUS__4 0x0524 564 565 #define TRIG_ERROR_S 16 566 #define TRIG_DONE_S 0 567 568 #define REG_PTP_INT_STATUS__4 0x0528 569 570 #define TRIG_INT_S 16 571 #define TS_INT_S 0 572 573 #define TRIG_UNIT_M 0x7 574 #define TS_UNIT_M 0x3 575 576 #define REG_PTP_CTRL_STAT__4 0x052C 577 578 #define GPIO_IN BIT(7) 579 #define GPIO_OUT BIT(6) 580 #define TS_INT_ENABLE BIT(5) 581 #define TRIG_ACTIVE BIT(4) 582 #define TRIG_ENABLE BIT(3) 583 #define TRIG_RESET BIT(2) 584 #define TS_ENABLE BIT(1) 585 #define TS_RESET BIT(0) 586 587 #define GPIO_CTRL_M (GPIO_IN | GPIO_OUT) 588 589 #define TRIG_CTRL_M \ 590 (TRIG_ACTIVE | TRIG_ENABLE | TRIG_RESET) 591 592 #define TS_CTRL_M \ 593 (TS_INT_ENABLE | TS_ENABLE | TS_RESET) 594 595 #define REG_TRIG_TARGET_NANOSEC 0x0530 596 #define REG_TRIG_TARGET_SEC 0x0534 597 598 #define REG_TRIG_CTRL__4 0x0538 599 600 #define TRIG_CASCADE_ENABLE BIT(31) 601 #define TRIG_CASCADE_TAIL BIT(30) 602 #define TRIG_CASCADE_UPS_M 0xF 603 #define TRIG_CASCADE_UPS_S 26 604 #define TRIG_NOW BIT(25) 605 #define TRIG_NOTIFY BIT(24) 606 #define TRIG_EDGE BIT(23) 607 #define TRIG_PATTERN_S 20 608 #define TRIG_PATTERN_M 0x7 609 #define TRIG_NEG_EDGE 0 610 #define TRIG_POS_EDGE 1 611 #define TRIG_NEG_PULSE 2 612 #define TRIG_POS_PULSE 3 613 #define TRIG_NEG_PERIOD 4 614 #define TRIG_POS_PERIOD 5 615 #define TRIG_REG_OUTPUT 6 616 #define TRIG_GPO_S 16 617 #define TRIG_GPO_M 0xF 618 #define TRIG_CASCADE_ITERATE_CNT_M 0xFFFF 619 620 #define REG_TRIG_CYCLE_WIDTH 0x053C 621 622 #define REG_TRIG_CYCLE_CNT 0x0540 623 624 #define TRIG_CYCLE_CNT_M 0xFFFF 625 #define TRIG_CYCLE_CNT_S 16 626 #define TRIG_BIT_PATTERN_M 0xFFFF 627 628 #define REG_TRIG_ITERATE_TIME 0x0544 629 630 #define REG_TRIG_PULSE_WIDTH__4 0x0548 631 632 #define TRIG_PULSE_WIDTH_M 0x00FFFFFF 633 634 #define REG_TS_CTRL_STAT__4 0x0550 635 636 #define TS_EVENT_DETECT_M 0xF 637 #define TS_EVENT_DETECT_S 17 638 #define TS_EVENT_OVERFLOW BIT(16) 639 #define TS_GPI_M 0xF 640 #define TS_GPI_S 8 641 #define TS_DETECT_RISE BIT(7) 642 #define TS_DETECT_FALL BIT(6) 643 #define TS_DETECT_S 6 644 #define TS_CASCADE_TAIL BIT(5) 645 #define TS_CASCADE_UPS_M 0xF 646 #define TS_CASCADE_UPS_S 1 647 #define TS_CASCADE_ENABLE BIT(0) 648 649 #define DETECT_RISE (TS_DETECT_RISE >> TS_DETECT_S) 650 #define DETECT_FALL (TS_DETECT_FALL >> TS_DETECT_S) 651 652 #define REG_TS_EVENT_0_NANOSEC 0x0554 653 #define REG_TS_EVENT_0_SEC 0x0558 654 #define REG_TS_EVENT_0_SUB_NANOSEC 0x055C 655 656 #define REG_TS_EVENT_1_NANOSEC 0x0560 657 #define REG_TS_EVENT_1_SEC 0x0564 658 #define REG_TS_EVENT_1_SUB_NANOSEC 0x0568 659 660 #define REG_TS_EVENT_2_NANOSEC 0x056C 661 #define REG_TS_EVENT_2_SEC 0x0570 662 #define REG_TS_EVENT_2_SUB_NANOSEC 0x0574 663 664 #define REG_TS_EVENT_3_NANOSEC 0x0578 665 #define REG_TS_EVENT_3_SEC 0x057C 666 #define REG_TS_EVENT_3_SUB_NANOSEC 0x0580 667 668 #define REG_TS_EVENT_4_NANOSEC 0x0584 669 #define REG_TS_EVENT_4_SEC 0x0588 670 #define REG_TS_EVENT_4_SUB_NANOSEC 0x058C 671 672 #define REG_TS_EVENT_5_NANOSEC 0x0590 673 #define REG_TS_EVENT_5_SEC 0x0594 674 #define REG_TS_EVENT_5_SUB_NANOSEC 0x0598 675 676 #define REG_TS_EVENT_6_NANOSEC 0x059C 677 #define REG_TS_EVENT_6_SEC 0x05A0 678 #define REG_TS_EVENT_6_SUB_NANOSEC 0x05A4 679 680 #define REG_TS_EVENT_7_NANOSEC 0x05A8 681 #define REG_TS_EVENT_7_SEC 0x05AC 682 #define REG_TS_EVENT_7_SUB_NANOSEC 0x05B0 683 684 #define TS_EVENT_EDGE_M 0x1 685 #define TS_EVENT_EDGE_S 30 686 #define TS_EVENT_NANOSEC_M (BIT(30) - 1) 687 688 #define TS_EVENT_SUB_NANOSEC_M 0x7 689 690 #define TS_EVENT_SAMPLE \ 691 (REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC) 692 693 #define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12)) 694 695 #define REG_GLOBAL_RR_INDEX__1 0x0600 696 697 /* DLR */ 698 #define REG_DLR_SRC_PORT__4 0x0604 699 700 #define DLR_SRC_PORT_UNICAST BIT(31) 701 #define DLR_SRC_PORT_M 0x3 702 #define DLR_SRC_PORT_BOTH 0 703 #define DLR_SRC_PORT_EACH 1 704 705 #define REG_DLR_IP_ADDR__4 0x0608 706 707 #define REG_DLR_CTRL__1 0x0610 708 709 #define DLR_RESET_SEQ_ID BIT(3) 710 #define DLR_BACKUP_AUTO_ON BIT(2) 711 #define DLR_BEACON_TX_ENABLE BIT(1) 712 #define DLR_ASSIST_ENABLE BIT(0) 713 714 #define REG_DLR_STATE__1 0x0611 715 716 #define DLR_NODE_STATE_M 0x3 717 #define DLR_NODE_STATE_S 1 718 #define DLR_NODE_STATE_IDLE 0 719 #define DLR_NODE_STATE_FAULT 1 720 #define DLR_NODE_STATE_NORMAL 2 721 #define DLR_RING_STATE_FAULT 0 722 #define DLR_RING_STATE_NORMAL 1 723 724 #define REG_DLR_PRECEDENCE__1 0x0612 725 726 #define REG_DLR_BEACON_INTERVAL__4 0x0614 727 728 #define REG_DLR_BEACON_TIMEOUT__4 0x0618 729 730 #define REG_DLR_TIMEOUT_WINDOW__4 0x061C 731 732 #define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1) 733 734 #define REG_DLR_VLAN_ID__2 0x0620 735 736 #define DLR_VLAN_ID_M (BIT(12) - 1) 737 738 #define REG_DLR_DEST_ADDR_0 0x0622 739 #define REG_DLR_DEST_ADDR_1 0x0623 740 #define REG_DLR_DEST_ADDR_2 0x0624 741 #define REG_DLR_DEST_ADDR_3 0x0625 742 #define REG_DLR_DEST_ADDR_4 0x0626 743 #define REG_DLR_DEST_ADDR_5 0x0627 744 745 #define REG_DLR_PORT_MAP__4 0x0628 746 747 #define REG_DLR_CLASS__1 0x062C 748 749 #define DLR_FRAME_QID_M 0x3 750 751 /* HSR */ 752 #define REG_HSR_PORT_MAP__4 0x0640 753 754 #define REG_HSR_ALU_CTRL_0__1 0x0644 755 756 #define HSR_DUPLICATE_DISCARD BIT(7) 757 #define HSR_NODE_UNICAST BIT(6) 758 #define HSR_AGE_CNT_DEFAULT_M 0x7 759 #define HSR_AGE_CNT_DEFAULT_S 3 760 #define HSR_LEARN_MCAST_DISABLE BIT(2) 761 #define HSR_HASH_OPTION_M 0x3 762 #define HSR_HASH_DISABLE 0 763 #define HSR_HASH_UPPER_BITS 1 764 #define HSR_HASH_LOWER_BITS 2 765 #define HSR_HASH_XOR_BOTH_BITS 3 766 767 #define REG_HSR_ALU_CTRL_1__1 0x0645 768 769 #define HSR_LEARN_UCAST_DISABLE BIT(7) 770 #define HSR_FLUSH_TABLE BIT(5) 771 #define HSR_PROC_MCAST_SRC BIT(3) 772 #define HSR_AGING_ENABLE BIT(2) 773 774 #define REG_HSR_ALU_CTRL_2__2 0x0646 775 776 #define REG_HSR_ALU_AGE_PERIOD__4 0x0648 777 778 #define REG_HSR_ALU_INT_STATUS__1 0x064C 779 #define REG_HSR_ALU_INT_MASK__1 0x064D 780 781 #define HSR_WINDOW_OVERFLOW_INT BIT(3) 782 #define HSR_LEARN_FAIL_INT BIT(2) 783 #define HSR_ALMOST_FULL_INT BIT(1) 784 #define HSR_WRITE_FAIL_INT BIT(0) 785 786 #define REG_HSR_ALU_ENTRY_0__2 0x0650 787 788 #define HSR_ENTRY_INDEX_M (BIT(10) - 1) 789 #define HSR_FAIL_INDEX_M (BIT(8) - 1) 790 791 #define REG_HSR_ALU_ENTRY_1__2 0x0652 792 793 #define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1) 794 795 #define REG_HSR_ALU_ENTRY_3__2 0x0654 796 797 #define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1) 798 799 /* 0 - Operation */ 800 #define REG_PORT_DEFAULT_VID 0x0000 801 802 #define REG_PORT_CUSTOM_VID 0x0002 803 #define REG_PORT_AVB_SR_1_VID 0x0004 804 #define REG_PORT_AVB_SR_2_VID 0x0006 805 806 #define REG_PORT_AVB_SR_1_TYPE 0x0008 807 #define REG_PORT_AVB_SR_2_TYPE 0x000A 808 809 #define REG_PORT_PME_STATUS 0x0013 810 #define REG_PORT_PME_CTRL 0x0017 811 812 #define PME_WOL_MAGICPKT BIT(2) 813 #define PME_WOL_LINKUP BIT(1) 814 #define PME_WOL_ENERGY BIT(0) 815 816 #define REG_PORT_INT_STATUS 0x001B 817 #define REG_PORT_INT_MASK 0x001F 818 819 #define PORT_SGMII_INT BIT(3) 820 #define PORT_PTP_INT BIT(2) 821 #define PORT_PHY_INT BIT(1) 822 #define PORT_ACL_INT BIT(0) 823 824 #define PORT_INT_MASK \ 825 (PORT_SGMII_INT | PORT_PTP_INT | PORT_PHY_INT | PORT_ACL_INT) 826 827 #define REG_PORT_CTRL_0 0x0020 828 829 #define PORT_MAC_LOOPBACK BIT(7) 830 #define PORT_FORCE_TX_FLOW_CTRL BIT(4) 831 #define PORT_FORCE_RX_FLOW_CTRL BIT(3) 832 #define PORT_TAIL_TAG_ENABLE BIT(2) 833 #define PORT_QUEUE_SPLIT_MASK GENMASK(1, 0) 834 #define PORT_EIGHT_QUEUE 0x3 835 #define PORT_FOUR_QUEUE 0x2 836 #define PORT_TWO_QUEUE 0x1 837 #define PORT_SINGLE_QUEUE 0x0 838 839 #define REG_PORT_CTRL_1 0x0021 840 841 #define PORT_SRP_ENABLE 0x3 842 843 #define REG_PORT_STATUS_0 0x0030 844 845 #define PORT_INTF_SPEED_M 0x3 846 #define PORT_INTF_SPEED_S 3 847 #define PORT_INTF_FULL_DUPLEX BIT(2) 848 #define PORT_TX_FLOW_CTRL BIT(1) 849 #define PORT_RX_FLOW_CTRL BIT(0) 850 851 #define REG_PORT_STATUS_1 0x0034 852 853 /* 1 - PHY */ 854 #define REG_PORT_PHY_CTRL 0x0100 855 856 #define PORT_PHY_RESET BIT(15) 857 #define PORT_PHY_LOOPBACK BIT(14) 858 #define PORT_SPEED_100MBIT BIT(13) 859 #define PORT_AUTO_NEG_ENABLE BIT(12) 860 #define PORT_POWER_DOWN BIT(11) 861 #define PORT_ISOLATE BIT(10) 862 #define PORT_AUTO_NEG_RESTART BIT(9) 863 #define PORT_FULL_DUPLEX BIT(8) 864 #define PORT_COLLISION_TEST BIT(7) 865 #define PORT_SPEED_1000MBIT BIT(6) 866 867 #define REG_PORT_PHY_STATUS 0x0102 868 869 #define PORT_100BT4_CAPABLE BIT(15) 870 #define PORT_100BTX_FD_CAPABLE BIT(14) 871 #define PORT_100BTX_CAPABLE BIT(13) 872 #define PORT_10BT_FD_CAPABLE BIT(12) 873 #define PORT_10BT_CAPABLE BIT(11) 874 #define PORT_EXTENDED_STATUS BIT(8) 875 #define PORT_MII_SUPPRESS_CAPABLE BIT(6) 876 #define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5) 877 #define PORT_REMOTE_FAULT BIT(4) 878 #define PORT_AUTO_NEG_CAPABLE BIT(3) 879 #define PORT_LINK_STATUS BIT(2) 880 #define PORT_JABBER_DETECT BIT(1) 881 #define PORT_EXTENDED_CAPABILITY BIT(0) 882 883 #define REG_PORT_PHY_ID_HI 0x0104 884 #define REG_PORT_PHY_ID_LO 0x0106 885 886 #define KSZ9477_ID_HI 0x0022 887 #define KSZ9477_ID_LO 0x1622 888 889 #define REG_PORT_PHY_AUTO_NEGOTIATION 0x0108 890 891 #define PORT_AUTO_NEG_NEXT_PAGE BIT(15) 892 #define PORT_AUTO_NEG_REMOTE_FAULT BIT(13) 893 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(11) 894 #define PORT_AUTO_NEG_SYM_PAUSE BIT(10) 895 #define PORT_AUTO_NEG_100BT4 BIT(9) 896 #define PORT_AUTO_NEG_100BTX_FD BIT(8) 897 #define PORT_AUTO_NEG_100BTX BIT(7) 898 #define PORT_AUTO_NEG_10BT_FD BIT(6) 899 #define PORT_AUTO_NEG_10BT BIT(5) 900 #define PORT_AUTO_NEG_SELECTOR 0x001F 901 #define PORT_AUTO_NEG_802_3 0x0001 902 903 #define PORT_AUTO_NEG_PAUSE \ 904 (PORT_AUTO_NEG_ASYM_PAUSE | PORT_AUTO_NEG_SYM_PAUSE) 905 906 #define REG_PORT_PHY_REMOTE_CAPABILITY 0x010A 907 908 #define PORT_REMOTE_NEXT_PAGE BIT(15) 909 #define PORT_REMOTE_ACKNOWLEDGE BIT(14) 910 #define PORT_REMOTE_REMOTE_FAULT BIT(13) 911 #define PORT_REMOTE_ASYM_PAUSE BIT(11) 912 #define PORT_REMOTE_SYM_PAUSE BIT(10) 913 #define PORT_REMOTE_100BTX_FD BIT(8) 914 #define PORT_REMOTE_100BTX BIT(7) 915 #define PORT_REMOTE_10BT_FD BIT(6) 916 #define PORT_REMOTE_10BT BIT(5) 917 918 #define REG_PORT_PHY_1000_CTRL 0x0112 919 920 #define PORT_AUTO_NEG_MANUAL BIT(12) 921 #define PORT_AUTO_NEG_MASTER BIT(11) 922 #define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10) 923 #define PORT_AUTO_NEG_1000BT_FD BIT(9) 924 #define PORT_AUTO_NEG_1000BT BIT(8) 925 926 #define REG_PORT_PHY_1000_STATUS 0x0114 927 928 #define PORT_MASTER_FAULT BIT(15) 929 #define PORT_LOCAL_MASTER BIT(14) 930 #define PORT_LOCAL_RX_OK BIT(13) 931 #define PORT_REMOTE_RX_OK BIT(12) 932 #define PORT_REMOTE_1000BT_FD BIT(11) 933 #define PORT_REMOTE_1000BT BIT(10) 934 #define PORT_REMOTE_IDLE_CNT_M 0x0F 935 936 #define PORT_PHY_1000_STATIC_STATUS \ 937 (PORT_LOCAL_RX_OK | \ 938 PORT_REMOTE_RX_OK | \ 939 PORT_REMOTE_1000BT_FD | \ 940 PORT_REMOTE_1000BT) 941 942 #define REG_PORT_PHY_MMD_SETUP 0x011A 943 944 #define PORT_MMD_OP_MODE_M 0x3 945 #define PORT_MMD_OP_MODE_S 14 946 #define PORT_MMD_OP_INDEX 0 947 #define PORT_MMD_OP_DATA_NO_INCR 1 948 #define PORT_MMD_OP_DATA_INCR_RW 2 949 #define PORT_MMD_OP_DATA_INCR_W 3 950 #define PORT_MMD_DEVICE_ID_M 0x1F 951 952 #define MMD_SETUP(mode, dev) \ 953 (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev)) 954 955 #define REG_PORT_PHY_MMD_INDEX_DATA 0x011C 956 957 #define MMD_DEVICE_ID_DSP 1 958 959 #define MMD_DSP_SQI_CHAN_A 0xAC 960 #define MMD_DSP_SQI_CHAN_B 0xAD 961 #define MMD_DSP_SQI_CHAN_C 0xAE 962 #define MMD_DSP_SQI_CHAN_D 0xAF 963 964 #define DSP_SQI_ERR_DETECTED BIT(15) 965 #define DSP_SQI_AVG_ERR 0x7FFF 966 967 #define MMD_DEVICE_ID_COMMON 2 968 969 #define MMD_DEVICE_ID_EEE_ADV 7 970 971 #define MMD_EEE_ADV 0x3C 972 #define EEE_ADV_100MBIT BIT(1) 973 #define EEE_ADV_1GBIT BIT(2) 974 975 #define MMD_EEE_LP_ADV 0x3D 976 #define MMD_EEE_MSG_CODE 0x3F 977 978 #define MMD_DEVICE_ID_AFED 0x1C 979 980 #define REG_PORT_PHY_EXTENDED_STATUS 0x011E 981 982 #define PORT_100BTX_FD_ABLE BIT(15) 983 #define PORT_100BTX_ABLE BIT(14) 984 #define PORT_10BT_FD_ABLE BIT(13) 985 #define PORT_10BT_ABLE BIT(12) 986 987 #define REG_PORT_SGMII_ADDR__4 0x0200 988 #define PORT_SGMII_AUTO_INCR BIT(23) 989 #define PORT_SGMII_DEVICE_ID_M 0x1F 990 #define PORT_SGMII_DEVICE_ID_S 16 991 #define PORT_SGMII_ADDR_M (BIT(21) - 1) 992 993 #define REG_PORT_SGMII_DATA__4 0x0204 994 #define PORT_SGMII_DATA_M (BIT(16) - 1) 995 996 #define MMD_DEVICE_ID_PMA 0x01 997 #define MMD_DEVICE_ID_PCS 0x03 998 #define MMD_DEVICE_ID_PHY_XS 0x04 999 #define MMD_DEVICE_ID_DTE_XS 0x05 1000 #define MMD_DEVICE_ID_AN 0x07 1001 #define MMD_DEVICE_ID_VENDOR_CTRL 0x1E 1002 #define MMD_DEVICE_ID_VENDOR_MII 0x1F 1003 1004 #define SR_MII MMD_DEVICE_ID_VENDOR_MII 1005 1006 #define MMD_SR_MII_CTRL 0x0000 1007 1008 #define SR_MII_RESET BIT(15) 1009 #define SR_MII_LOOPBACK BIT(14) 1010 #define SR_MII_SPEED_100MBIT BIT(13) 1011 #define SR_MII_AUTO_NEG_ENABLE BIT(12) 1012 #define SR_MII_POWER_DOWN BIT(11) 1013 #define SR_MII_AUTO_NEG_RESTART BIT(9) 1014 #define SR_MII_FULL_DUPLEX BIT(8) 1015 #define SR_MII_SPEED_1000MBIT BIT(6) 1016 1017 #define MMD_SR_MII_STATUS 0x0001 1018 #define MMD_SR_MII_ID_1 0x0002 1019 #define MMD_SR_MII_ID_2 0x0003 1020 #define MMD_SR_MII_AUTO_NEGOTIATION 0x0004 1021 1022 #define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15) 1023 #define SR_MII_AUTO_NEG_REMOTE_FAULT_M 0x3 1024 #define SR_MII_AUTO_NEG_REMOTE_FAULT_S 12 1025 #define SR_MII_AUTO_NEG_NO_ERROR 0 1026 #define SR_MII_AUTO_NEG_OFFLINE 1 1027 #define SR_MII_AUTO_NEG_LINK_FAILURE 2 1028 #define SR_MII_AUTO_NEG_ERROR 3 1029 #define SR_MII_AUTO_NEG_PAUSE_M 0x3 1030 #define SR_MII_AUTO_NEG_PAUSE_S 7 1031 #define SR_MII_AUTO_NEG_NO_PAUSE 0 1032 #define SR_MII_AUTO_NEG_ASYM_PAUSE_TX 1 1033 #define SR_MII_AUTO_NEG_SYM_PAUSE 2 1034 #define SR_MII_AUTO_NEG_ASYM_PAUSE_RX 3 1035 #define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6) 1036 #define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5) 1037 1038 #define MMD_SR_MII_REMOTE_CAPABILITY 0x0005 1039 #define MMD_SR_MII_AUTO_NEG_EXP 0x0006 1040 #define MMD_SR_MII_AUTO_NEG_EXT 0x000F 1041 1042 #define MMD_SR_MII_DIGITAL_CTRL_1 0x8000 1043 1044 #define MMD_SR_MII_AUTO_NEG_CTRL 0x8001 1045 1046 #define SR_MII_8_BIT BIT(8) 1047 #define SR_MII_SGMII_LINK_UP BIT(4) 1048 #define SR_MII_TX_CFG_PHY_MASTER BIT(3) 1049 #define SR_MII_PCS_MODE_M 0x3 1050 #define SR_MII_PCS_MODE_S 1 1051 #define SR_MII_PCS_SGMII 2 1052 #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0) 1053 1054 #define MMD_SR_MII_AUTO_NEG_STATUS 0x8002 1055 1056 #define SR_MII_STAT_LINK_UP BIT(4) 1057 #define SR_MII_STAT_M 0x3 1058 #define SR_MII_STAT_S 2 1059 #define SR_MII_STAT_10_MBPS 0 1060 #define SR_MII_STAT_100_MBPS 1 1061 #define SR_MII_STAT_1000_MBPS 2 1062 #define SR_MII_STAT_FULL_DUPLEX BIT(1) 1063 1064 #define MMD_SR_MII_PHY_CTRL 0x80A0 1065 1066 #define SR_MII_PHY_LANE_SEL_M 0xF 1067 #define SR_MII_PHY_LANE_SEL_S 8 1068 #define SR_MII_PHY_WRITE BIT(1) 1069 #define SR_MII_PHY_START_BUSY BIT(0) 1070 1071 #define MMD_SR_MII_PHY_ADDR 0x80A1 1072 1073 #define SR_MII_PHY_ADDR_M (BIT(16) - 1) 1074 1075 #define MMD_SR_MII_PHY_DATA 0x80A2 1076 1077 #define SR_MII_PHY_DATA_M (BIT(16) - 1) 1078 1079 #define SR_MII_PHY_JTAG_CHIP_ID_HI 0x000C 1080 #define SR_MII_PHY_JTAG_CHIP_ID_LO 0x000D 1081 1082 #define REG_PORT_PHY_REMOTE_LB_LED 0x0122 1083 1084 #define PORT_REMOTE_LOOPBACK BIT(8) 1085 #define PORT_LED_SELECT (3 << 6) 1086 #define PORT_LED_CTRL (3 << 4) 1087 #define PORT_LED_CTRL_TEST BIT(3) 1088 #define PORT_10BT_PREAMBLE BIT(2) 1089 #define PORT_LINK_MD_10BT_ENABLE BIT(1) 1090 #define PORT_LINK_MD_PASS BIT(0) 1091 1092 #define REG_PORT_PHY_LINK_MD 0x0124 1093 1094 #define PORT_START_CABLE_DIAG BIT(15) 1095 #define PORT_TX_DISABLE BIT(14) 1096 #define PORT_CABLE_DIAG_PAIR_M 0x3 1097 #define PORT_CABLE_DIAG_PAIR_S 12 1098 #define PORT_CABLE_DIAG_SELECT_M 0x3 1099 #define PORT_CABLE_DIAG_SELECT_S 10 1100 #define PORT_CABLE_DIAG_RESULT_M 0x3 1101 #define PORT_CABLE_DIAG_RESULT_S 8 1102 #define PORT_CABLE_STAT_NORMAL 0 1103 #define PORT_CABLE_STAT_OPEN 1 1104 #define PORT_CABLE_STAT_SHORT 2 1105 #define PORT_CABLE_STAT_FAILED 3 1106 #define PORT_CABLE_FAULT_COUNTER 0x00FF 1107 1108 #define REG_PORT_PHY_PMA_STATUS 0x0126 1109 1110 #define PORT_1000_LINK_GOOD BIT(1) 1111 #define PORT_100_LINK_GOOD BIT(0) 1112 1113 #define REG_PORT_PHY_DIGITAL_STATUS 0x0128 1114 1115 #define PORT_LINK_DETECT BIT(14) 1116 #define PORT_SIGNAL_DETECT BIT(13) 1117 #define PORT_PHY_STAT_MDI BIT(12) 1118 #define PORT_PHY_STAT_MASTER BIT(11) 1119 1120 #define REG_PORT_PHY_RXER_COUNTER 0x012A 1121 1122 #define REG_PORT_PHY_INT_ENABLE 0x0136 1123 #define REG_PORT_PHY_INT_STATUS 0x0137 1124 1125 #define JABBER_INT BIT(7) 1126 #define RX_ERR_INT BIT(6) 1127 #define PAGE_RX_INT BIT(5) 1128 #define PARALLEL_DETECT_FAULT_INT BIT(4) 1129 #define LINK_PARTNER_ACK_INT BIT(3) 1130 #define LINK_DOWN_INT BIT(2) 1131 #define REMOTE_FAULT_INT BIT(1) 1132 #define LINK_UP_INT BIT(0) 1133 1134 #define REG_PORT_PHY_DIGITAL_DEBUG_1 0x0138 1135 1136 #define PORT_REG_CLK_SPEED_25_MHZ BIT(14) 1137 #define PORT_PHY_FORCE_MDI BIT(7) 1138 #define PORT_PHY_AUTO_MDIX_DISABLE BIT(6) 1139 1140 /* Same as PORT_PHY_LOOPBACK */ 1141 #define PORT_PHY_PCS_LOOPBACK BIT(0) 1142 1143 #define REG_PORT_PHY_DIGITAL_DEBUG_2 0x013A 1144 1145 #define REG_PORT_PHY_DIGITAL_DEBUG_3 0x013C 1146 1147 #define PORT_100BT_FIXED_LATENCY BIT(15) 1148 1149 #define REG_PORT_PHY_PHY_CTRL 0x013E 1150 1151 #define PORT_INT_PIN_HIGH BIT(14) 1152 #define PORT_ENABLE_JABBER BIT(9) 1153 #define PORT_STAT_SPEED_1000MBIT BIT(6) 1154 #define PORT_STAT_SPEED_100MBIT BIT(5) 1155 #define PORT_STAT_SPEED_10MBIT BIT(4) 1156 #define PORT_STAT_FULL_DUPLEX BIT(3) 1157 1158 /* Same as PORT_PHY_STAT_MASTER */ 1159 #define PORT_STAT_MASTER BIT(2) 1160 #define PORT_RESET BIT(1) 1161 #define PORT_LINK_STATUS_FAIL BIT(0) 1162 1163 /* 3 - xMII */ 1164 #define PORT_SGMII_SEL BIT(7) 1165 #define PORT_GRXC_ENABLE BIT(0) 1166 1167 #define PORT_RMII_CLK_SEL BIT(7) 1168 #define PORT_MII_SEL_EDGE BIT(5) 1169 1170 /* 4 - MAC */ 1171 #define REG_PORT_MAC_CTRL_0 0x0400 1172 1173 #define PORT_BROADCAST_STORM BIT(1) 1174 #define PORT_JUMBO_FRAME BIT(0) 1175 1176 #define REG_PORT_MAC_CTRL_1 0x0401 1177 1178 #define PORT_BACK_PRESSURE BIT(3) 1179 #define PORT_PASS_ALL BIT(0) 1180 1181 #define REG_PORT_MAC_CTRL_2 0x0402 1182 1183 #define PORT_100BT_EEE_DISABLE BIT(7) 1184 #define PORT_1000BT_EEE_DISABLE BIT(6) 1185 1186 #define REG_PORT_MAC_IN_RATE_LIMIT 0x0403 1187 1188 #define PORT_IN_PORT_BASED_S 6 1189 #define PORT_RATE_PACKET_BASED_S 5 1190 #define PORT_IN_FLOW_CTRL_S 4 1191 #define PORT_COUNT_IFG_S 1 1192 #define PORT_COUNT_PREAMBLE_S 0 1193 #define PORT_IN_PORT_BASED BIT(6) 1194 #define PORT_IN_PACKET_BASED BIT(5) 1195 #define PORT_IN_FLOW_CTRL BIT(4) 1196 #define PORT_IN_LIMIT_MODE_M 0x3 1197 #define PORT_IN_LIMIT_MODE_S 2 1198 #define PORT_IN_ALL 0 1199 #define PORT_IN_UNICAST 1 1200 #define PORT_IN_MULTICAST 2 1201 #define PORT_IN_BROADCAST 3 1202 #define PORT_COUNT_IFG BIT(1) 1203 #define PORT_COUNT_PREAMBLE BIT(0) 1204 1205 #define REG_PORT_IN_RATE_0 0x0410 1206 #define REG_PORT_IN_RATE_1 0x0411 1207 #define REG_PORT_IN_RATE_2 0x0412 1208 #define REG_PORT_IN_RATE_3 0x0413 1209 #define REG_PORT_IN_RATE_4 0x0414 1210 #define REG_PORT_IN_RATE_5 0x0415 1211 #define REG_PORT_IN_RATE_6 0x0416 1212 #define REG_PORT_IN_RATE_7 0x0417 1213 1214 #define REG_PORT_OUT_RATE_0 0x0420 1215 #define REG_PORT_OUT_RATE_1 0x0421 1216 #define REG_PORT_OUT_RATE_2 0x0422 1217 #define REG_PORT_OUT_RATE_3 0x0423 1218 1219 #define PORT_RATE_LIMIT_M (BIT(7) - 1) 1220 1221 /* 5 - MIB Counters */ 1222 #define REG_PORT_MIB_CTRL_STAT__4 0x0500 1223 1224 #define MIB_COUNTER_READ BIT(25) 1225 #define MIB_COUNTER_FLUSH_FREEZE BIT(24) 1226 #define MIB_COUNTER_INDEX_M (BIT(8) - 1) 1227 #define MIB_COUNTER_INDEX_S 16 1228 #define MIB_COUNTER_DATA_HI_M 0xF 1229 1230 #define REG_PORT_MIB_DATA 0x0504 1231 1232 /* 6 - ACL */ 1233 #define REG_PORT_ACL_0 0x0600 1234 1235 #define ACL_FIRST_RULE_M 0xF 1236 1237 #define REG_PORT_ACL_1 0x0601 1238 1239 #define ACL_MODE_M 0x3 1240 #define ACL_MODE_S 4 1241 #define ACL_MODE_DISABLE 0 1242 #define ACL_MODE_LAYER_2 1 1243 #define ACL_MODE_LAYER_3 2 1244 #define ACL_MODE_LAYER_4 3 1245 #define ACL_ENABLE_M 0x3 1246 #define ACL_ENABLE_S 2 1247 #define ACL_ENABLE_2_COUNT 0 1248 #define ACL_ENABLE_2_TYPE 1 1249 #define ACL_ENABLE_2_MAC 2 1250 #define ACL_ENABLE_2_BOTH 3 1251 #define ACL_ENABLE_3_IP 1 1252 #define ACL_ENABLE_3_SRC_DST_COMP 2 1253 #define ACL_ENABLE_4_PROTOCOL 0 1254 #define ACL_ENABLE_4_TCP_PORT_COMP 1 1255 #define ACL_ENABLE_4_UDP_PORT_COMP 2 1256 #define ACL_ENABLE_4_TCP_SEQN_COMP 3 1257 #define ACL_SRC BIT(1) 1258 #define ACL_EQUAL BIT(0) 1259 1260 #define REG_PORT_ACL_2 0x0602 1261 #define REG_PORT_ACL_3 0x0603 1262 1263 #define ACL_MAX_PORT 0xFFFF 1264 1265 #define REG_PORT_ACL_4 0x0604 1266 #define REG_PORT_ACL_5 0x0605 1267 1268 #define ACL_MIN_PORT 0xFFFF 1269 #define ACL_IP_ADDR 0xFFFFFFFF 1270 #define ACL_TCP_SEQNUM 0xFFFFFFFF 1271 1272 #define REG_PORT_ACL_6 0x0606 1273 1274 #define ACL_RESERVED 0xF8 1275 #define ACL_PORT_MODE_M 0x3 1276 #define ACL_PORT_MODE_S 1 1277 #define ACL_PORT_MODE_DISABLE 0 1278 #define ACL_PORT_MODE_EITHER 1 1279 #define ACL_PORT_MODE_IN_RANGE 2 1280 #define ACL_PORT_MODE_OUT_OF_RANGE 3 1281 1282 #define REG_PORT_ACL_7 0x0607 1283 1284 #define ACL_TCP_FLAG_ENABLE BIT(0) 1285 1286 #define REG_PORT_ACL_8 0x0608 1287 1288 #define ACL_TCP_FLAG_M 0xFF 1289 1290 #define REG_PORT_ACL_9 0x0609 1291 1292 #define ACL_TCP_FLAG 0xFF 1293 #define ACL_ETH_TYPE 0xFFFF 1294 #define ACL_IP_M 0xFFFFFFFF 1295 1296 #define REG_PORT_ACL_A 0x060A 1297 1298 #define ACL_PRIO_MODE_M 0x3 1299 #define ACL_PRIO_MODE_S 6 1300 #define ACL_PRIO_MODE_DISABLE 0 1301 #define ACL_PRIO_MODE_HIGHER 1 1302 #define ACL_PRIO_MODE_LOWER 2 1303 #define ACL_PRIO_MODE_REPLACE 3 1304 #define ACL_PRIO_M KS_PRIO_M 1305 #define ACL_PRIO_S 3 1306 #define ACL_VLAN_PRIO_REPLACE BIT(2) 1307 #define ACL_VLAN_PRIO_M KS_PRIO_M 1308 #define ACL_VLAN_PRIO_HI_M 0x3 1309 1310 #define REG_PORT_ACL_B 0x060B 1311 1312 #define ACL_VLAN_PRIO_LO_M 0x8 1313 #define ACL_VLAN_PRIO_S 7 1314 #define ACL_MAP_MODE_M 0x3 1315 #define ACL_MAP_MODE_S 5 1316 #define ACL_MAP_MODE_DISABLE 0 1317 #define ACL_MAP_MODE_OR 1 1318 #define ACL_MAP_MODE_AND 2 1319 #define ACL_MAP_MODE_REPLACE 3 1320 1321 #define ACL_CNT_M (BIT(11) - 1) 1322 #define ACL_CNT_S 5 1323 1324 #define REG_PORT_ACL_C 0x060C 1325 1326 #define REG_PORT_ACL_D 0x060D 1327 #define ACL_MSEC_UNIT BIT(6) 1328 #define ACL_INTR_MODE BIT(5) 1329 #define ACL_PORT_MAP 0x7F 1330 1331 #define REG_PORT_ACL_E 0x060E 1332 #define REG_PORT_ACL_F 0x060F 1333 1334 #define REG_PORT_ACL_BYTE_EN_MSB 0x0610 1335 #define REG_PORT_ACL_BYTE_EN_LSB 0x0611 1336 1337 #define ACL_ACTION_START 0xA 1338 #define ACL_ACTION_LEN 4 1339 #define ACL_INTR_CNT_START 0xD 1340 #define ACL_RULESET_START 0xE 1341 #define ACL_RULESET_LEN 2 1342 #define ACL_TABLE_LEN 16 1343 1344 #define ACL_ACTION_ENABLE 0x003C 1345 #define ACL_MATCH_ENABLE 0x7FC3 1346 #define ACL_RULESET_ENABLE 0x8003 1347 #define ACL_BYTE_ENABLE 0xFFFF 1348 1349 #define REG_PORT_ACL_CTRL_0 0x0612 1350 1351 #define PORT_ACL_WRITE_DONE BIT(6) 1352 #define PORT_ACL_READ_DONE BIT(5) 1353 #define PORT_ACL_WRITE BIT(4) 1354 #define PORT_ACL_INDEX_M 0xF 1355 1356 #define REG_PORT_ACL_CTRL_1 0x0613 1357 1358 /* 8 - Classification and Policing */ 1359 #define REG_PORT_MRI_MIRROR_CTRL 0x0800 1360 1361 #define PORT_MIRROR_RX BIT(6) 1362 #define PORT_MIRROR_TX BIT(5) 1363 #define PORT_MIRROR_SNIFFER BIT(1) 1364 1365 #define REG_PORT_MRI_PRIO_CTRL 0x0801 1366 1367 #define PORT_HIGHEST_PRIO BIT(7) 1368 #define PORT_OR_PRIO BIT(6) 1369 #define PORT_MAC_PRIO_ENABLE BIT(4) 1370 #define PORT_VLAN_PRIO_ENABLE BIT(3) 1371 #define PORT_802_1P_PRIO_ENABLE BIT(2) 1372 #define PORT_DIFFSERV_PRIO_ENABLE BIT(1) 1373 #define PORT_ACL_PRIO_ENABLE BIT(0) 1374 1375 #define REG_PORT_MRI_MAC_CTRL 0x0802 1376 1377 #define PORT_USER_PRIO_CEILING BIT(7) 1378 #define PORT_DROP_NON_VLAN BIT(4) 1379 #define PORT_DROP_TAG BIT(3) 1380 #define PORT_BASED_PRIO_M KS_PRIO_M 1381 #define PORT_BASED_PRIO_S 0 1382 1383 #define REG_PORT_MRI_AUTHEN_CTRL 0x0803 1384 1385 #define PORT_ACL_ENABLE BIT(2) 1386 #define PORT_AUTHEN_MODE 0x3 1387 #define PORT_AUTHEN_PASS 0 1388 #define PORT_AUTHEN_BLOCK 1 1389 #define PORT_AUTHEN_TRAP 2 1390 1391 #define REG_PORT_MRI_INDEX__4 0x0804 1392 1393 #define MRI_INDEX_P_M 0x7 1394 #define MRI_INDEX_P_S 16 1395 #define MRI_INDEX_Q_M 0x3 1396 #define MRI_INDEX_Q_S 0 1397 1398 #define REG_PORT_MRI_TC_MAP__4 0x0808 1399 1400 #define PORT_TC_MAP_M 0xf 1401 #define PORT_TC_MAP_S 4 1402 1403 #define REG_PORT_MRI_POLICE_CTRL__4 0x080C 1404 1405 #define POLICE_DROP_ALL BIT(10) 1406 #define POLICE_PACKET_TYPE_M 0x3 1407 #define POLICE_PACKET_TYPE_S 8 1408 #define POLICE_PACKET_DROPPED 0 1409 #define POLICE_PACKET_GREEN 1 1410 #define POLICE_PACKET_YELLOW 2 1411 #define POLICE_PACKET_RED 3 1412 #define PORT_BASED_POLICING BIT(7) 1413 #define NON_DSCP_COLOR_M 0x3 1414 #define NON_DSCP_COLOR_S 5 1415 #define COLOR_MARK_ENABLE BIT(4) 1416 #define COLOR_REMAP_ENABLE BIT(3) 1417 #define POLICE_DROP_SRP BIT(2) 1418 #define POLICE_COLOR_NOT_AWARE BIT(1) 1419 #define POLICE_ENABLE BIT(0) 1420 1421 #define REG_PORT_POLICE_COLOR_0__4 0x0810 1422 #define REG_PORT_POLICE_COLOR_1__4 0x0814 1423 #define REG_PORT_POLICE_COLOR_2__4 0x0818 1424 #define REG_PORT_POLICE_COLOR_3__4 0x081C 1425 1426 #define POLICE_COLOR_MAP_S 2 1427 #define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1) 1428 1429 #define REG_PORT_POLICE_RATE__4 0x0820 1430 1431 #define POLICE_CIR_S 16 1432 #define POLICE_PIR_S 0 1433 1434 #define REG_PORT_POLICE_BURST_SIZE__4 0x0824 1435 1436 #define POLICE_BURST_SIZE_M 0x3FFF 1437 #define POLICE_CBS_S 16 1438 #define POLICE_PBS_S 0 1439 1440 #define REG_PORT_WRED_PM_CTRL_0__4 0x0830 1441 1442 #define WRED_PM_CTRL_M (BIT(11) - 1) 1443 1444 #define WRED_PM_MAX_THRESHOLD_S 16 1445 #define WRED_PM_MIN_THRESHOLD_S 0 1446 1447 #define REG_PORT_WRED_PM_CTRL_1__4 0x0834 1448 1449 #define WRED_PM_MULTIPLIER_S 16 1450 #define WRED_PM_AVG_QUEUE_SIZE_S 0 1451 1452 #define REG_PORT_WRED_QUEUE_CTRL_0__4 0x0840 1453 #define REG_PORT_WRED_QUEUE_CTRL_1__4 0x0844 1454 1455 #define REG_PORT_WRED_QUEUE_PMON__4 0x0848 1456 1457 #define WRED_RANDOM_DROP_ENABLE BIT(31) 1458 #define WRED_PMON_FLUSH BIT(30) 1459 #define WRED_DROP_GYR_DISABLE BIT(29) 1460 #define WRED_DROP_YR_DISABLE BIT(28) 1461 #define WRED_DROP_R_DISABLE BIT(27) 1462 #define WRED_DROP_ALL BIT(26) 1463 #define WRED_PMON_M (BIT(24) - 1) 1464 1465 /* 9 - Shaping */ 1466 1467 #define REG_PORT_MTI_QUEUE_CTRL_0__4 0x0904 1468 1469 #define MTI_PVID_REPLACE BIT(0) 1470 1471 #define REG_PORT_MTI_CREDIT_INCREMENT 0x091A 1472 1473 /* A - QM */ 1474 1475 #define REG_PORT_QM_CTRL__4 0x0A00 1476 1477 #define PORT_QM_DROP_PRIO_M 0x3 1478 1479 #define REG_PORT_VLAN_MEMBERSHIP__4 0x0A04 1480 1481 #define REG_PORT_QM_QUEUE_INDEX__4 0x0A08 1482 1483 #define PORT_QM_QUEUE_INDEX_S 24 1484 #define PORT_QM_BURST_SIZE_S 16 1485 #define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1) 1486 1487 #define REG_PORT_QM_WATER_MARK__4 0x0A0C 1488 1489 #define PORT_QM_HI_WATER_MARK_S 16 1490 #define PORT_QM_LO_WATER_MARK_S 0 1491 #define PORT_QM_WATER_MARK_M (BIT(11) - 1) 1492 1493 #define REG_PORT_QM_TX_CNT_0__4 0x0A10 1494 1495 #define PORT_QM_TX_CNT_USED_S 0 1496 #define PORT_QM_TX_CNT_M (BIT(11) - 1) 1497 1498 #define REG_PORT_QM_TX_CNT_1__4 0x0A14 1499 1500 #define PORT_QM_TX_CNT_CALCULATED_S 16 1501 #define PORT_QM_TX_CNT_AVAIL_S 0 1502 1503 /* B - LUE */ 1504 #define REG_PORT_LUE_CTRL 0x0B00 1505 1506 #define PORT_VLAN_LOOKUP_VID_0 BIT(7) 1507 #define PORT_INGRESS_FILTER BIT(6) 1508 #define PORT_DISCARD_NON_VID BIT(5) 1509 #define PORT_MAC_BASED_802_1X BIT(4) 1510 #define PORT_SRC_ADDR_FILTER BIT(3) 1511 1512 #define REG_PORT_LUE_MSTP_INDEX 0x0B01 1513 1514 #define REG_PORT_LUE_MSTP_STATE 0x0B04 1515 1516 /* C - PTP */ 1517 1518 #define REG_PTP_PORT_RX_DELAY__2 0x0C00 1519 #define REG_PTP_PORT_TX_DELAY__2 0x0C02 1520 #define REG_PTP_PORT_ASYM_DELAY__2 0x0C04 1521 1522 #define REG_PTP_PORT_XDELAY_TS 0x0C08 1523 #define REG_PTP_PORT_XDELAY_TS_H 0x0C08 1524 #define REG_PTP_PORT_XDELAY_TS_L 0x0C0A 1525 1526 #define REG_PTP_PORT_SYNC_TS 0x0C0C 1527 #define REG_PTP_PORT_SYNC_TS_H 0x0C0C 1528 #define REG_PTP_PORT_SYNC_TS_L 0x0C0E 1529 1530 #define REG_PTP_PORT_PDRESP_TS 0x0C10 1531 #define REG_PTP_PORT_PDRESP_TS_H 0x0C10 1532 #define REG_PTP_PORT_PDRESP_TS_L 0x0C12 1533 1534 #define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14 1535 #define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16 1536 1537 #define PTP_PORT_SYNC_INT BIT(15) 1538 #define PTP_PORT_XDELAY_REQ_INT BIT(14) 1539 #define PTP_PORT_PDELAY_RESP_INT BIT(13) 1540 1541 #define REG_PTP_PORT_LINK_DELAY__4 0x0C18 1542 1543 #define PRIO_QUEUES 4 1544 #define RX_PRIO_QUEUES 8 1545 1546 #define KS_PRIO_IN_REG 2 1547 1548 #define TOTAL_PORT_NUM 7 1549 1550 #define KSZ9477_COUNTER_NUM 0x20 1551 #define TOTAL_KSZ9477_COUNTER_NUM (KSZ9477_COUNTER_NUM + 2 + 2) 1552 1553 #define SWITCH_COUNTER_NUM KSZ9477_COUNTER_NUM 1554 #define TOTAL_SWITCH_COUNTER_NUM TOTAL_KSZ9477_COUNTER_NUM 1555 1556 #define P_BCAST_STORM_CTRL REG_PORT_MAC_CTRL_0 1557 #define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL 1558 #define P_MIRROR_CTRL REG_PORT_MRI_MIRROR_CTRL 1559 #define P_PHY_CTRL REG_PORT_PHY_CTRL 1560 #define P_RATE_LIMIT_CTRL REG_PORT_MAC_IN_RATE_LIMIT 1561 1562 #define S_LINK_AGING_CTRL REG_SW_LUE_CTRL_1 1563 #define S_MIRROR_CTRL REG_SW_MRI_CTRL_0 1564 #define S_REPLACE_VID_CTRL REG_SW_MAC_CTRL_2 1565 #define S_802_1P_PRIO_CTRL REG_SW_MAC_802_1P_MAP_0 1566 #define S_TOS_PRIO_CTRL REG_SW_MAC_TOS_PRIO_0 1567 #define S_FLUSH_TABLE_CTRL REG_SW_LUE_CTRL_1 1568 1569 #define SW_FLUSH_DYN_MAC_TABLE SW_FLUSH_MSTP_TABLE 1570 1571 #define MAX_TIMESTAMP_UNIT 2 1572 #define MAX_TRIG_UNIT 3 1573 #define MAX_TIMESTAMP_EVENT_UNIT 8 1574 #define MAX_GPIO 4 1575 1576 #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1) 1577 #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1) 1578 1579 #endif /* KSZ9477_REGS_H */ 1580