1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 snprintf(chip->irq_name, sizeof(chip->irq_name), 344 "mv88e6xxx-%s", dev_name(chip->dev)); 345 346 mv88e6xxx_reg_unlock(chip); 347 err = request_threaded_irq(chip->irq, NULL, 348 mv88e6xxx_g1_irq_thread_fn, 349 IRQF_ONESHOT | IRQF_SHARED, 350 chip->irq_name, chip); 351 mv88e6xxx_reg_lock(chip); 352 if (err) 353 mv88e6xxx_g1_irq_free_common(chip); 354 355 return err; 356 } 357 358 static void mv88e6xxx_irq_poll(struct kthread_work *work) 359 { 360 struct mv88e6xxx_chip *chip = container_of(work, 361 struct mv88e6xxx_chip, 362 irq_poll_work.work); 363 mv88e6xxx_g1_irq_thread_work(chip); 364 365 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 366 msecs_to_jiffies(100)); 367 } 368 369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 370 { 371 int err; 372 373 err = mv88e6xxx_g1_irq_setup_common(chip); 374 if (err) 375 return err; 376 377 kthread_init_delayed_work(&chip->irq_poll_work, 378 mv88e6xxx_irq_poll); 379 380 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 381 if (IS_ERR(chip->kworker)) 382 return PTR_ERR(chip->kworker); 383 384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 385 msecs_to_jiffies(100)); 386 387 return 0; 388 } 389 390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 391 { 392 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 393 kthread_destroy_worker(chip->kworker); 394 395 mv88e6xxx_reg_lock(chip); 396 mv88e6xxx_g1_irq_free_common(chip); 397 mv88e6xxx_reg_unlock(chip); 398 } 399 400 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 401 int speed, int duplex, int pause, 402 phy_interface_t mode) 403 { 404 struct phylink_link_state state; 405 int err; 406 407 if (!chip->info->ops->port_set_link) 408 return 0; 409 410 if (!chip->info->ops->port_link_state) 411 return 0; 412 413 err = chip->info->ops->port_link_state(chip, port, &state); 414 if (err) 415 return err; 416 417 /* Has anything actually changed? We don't expect the 418 * interface mode to change without one of the other 419 * parameters also changing 420 */ 421 if (state.link == link && 422 state.speed == speed && 423 state.duplex == duplex && 424 (state.interface == mode || 425 state.interface == PHY_INTERFACE_MODE_NA)) 426 return 0; 427 428 /* Port's MAC control must not be changed unless the link is down */ 429 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 430 if (err) 431 return err; 432 433 if (chip->info->ops->port_set_speed) { 434 err = chip->info->ops->port_set_speed(chip, port, speed); 435 if (err && err != -EOPNOTSUPP) 436 goto restore_link; 437 } 438 439 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 440 mode = chip->info->ops->port_max_speed_mode(port); 441 442 if (chip->info->ops->port_set_pause) { 443 err = chip->info->ops->port_set_pause(chip, port, pause); 444 if (err) 445 goto restore_link; 446 } 447 448 if (chip->info->ops->port_set_duplex) { 449 err = chip->info->ops->port_set_duplex(chip, port, duplex); 450 if (err && err != -EOPNOTSUPP) 451 goto restore_link; 452 } 453 454 if (chip->info->ops->port_set_rgmii_delay) { 455 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 456 if (err && err != -EOPNOTSUPP) 457 goto restore_link; 458 } 459 460 if (chip->info->ops->port_set_cmode) { 461 err = chip->info->ops->port_set_cmode(chip, port, mode); 462 if (err && err != -EOPNOTSUPP) 463 goto restore_link; 464 } 465 466 err = 0; 467 restore_link: 468 if (chip->info->ops->port_set_link(chip, port, link)) 469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 470 471 return err; 472 } 473 474 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 475 { 476 struct mv88e6xxx_chip *chip = ds->priv; 477 478 return port < chip->info->num_internal_phys; 479 } 480 481 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 482 unsigned long *mask, 483 struct phylink_link_state *state) 484 { 485 if (!phy_interface_mode_is_8023z(state->interface)) { 486 /* 10M and 100M are only supported in non-802.3z mode */ 487 phylink_set(mask, 10baseT_Half); 488 phylink_set(mask, 10baseT_Full); 489 phylink_set(mask, 100baseT_Half); 490 phylink_set(mask, 100baseT_Full); 491 } 492 } 493 494 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 495 unsigned long *mask, 496 struct phylink_link_state *state) 497 { 498 /* FIXME: if the port is in 1000Base-X mode, then it only supports 499 * 1000M FD speeds. In this case, CMODE will indicate 5. 500 */ 501 phylink_set(mask, 1000baseT_Full); 502 phylink_set(mask, 1000baseX_Full); 503 504 mv88e6065_phylink_validate(chip, port, mask, state); 505 } 506 507 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 508 unsigned long *mask, 509 struct phylink_link_state *state) 510 { 511 if (port >= 5) 512 phylink_set(mask, 2500baseX_Full); 513 514 /* No ethtool bits for 200Mbps */ 515 phylink_set(mask, 1000baseT_Full); 516 phylink_set(mask, 1000baseX_Full); 517 518 mv88e6065_phylink_validate(chip, port, mask, state); 519 } 520 521 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 522 unsigned long *mask, 523 struct phylink_link_state *state) 524 { 525 /* No ethtool bits for 200Mbps */ 526 phylink_set(mask, 1000baseT_Full); 527 phylink_set(mask, 1000baseX_Full); 528 529 mv88e6065_phylink_validate(chip, port, mask, state); 530 } 531 532 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 533 unsigned long *mask, 534 struct phylink_link_state *state) 535 { 536 if (port >= 9) { 537 phylink_set(mask, 2500baseX_Full); 538 phylink_set(mask, 2500baseT_Full); 539 } 540 541 /* No ethtool bits for 200Mbps */ 542 phylink_set(mask, 1000baseT_Full); 543 phylink_set(mask, 1000baseX_Full); 544 545 mv88e6065_phylink_validate(chip, port, mask, state); 546 } 547 548 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 549 unsigned long *mask, 550 struct phylink_link_state *state) 551 { 552 if (port >= 9) { 553 phylink_set(mask, 10000baseT_Full); 554 phylink_set(mask, 10000baseKR_Full); 555 } 556 557 mv88e6390_phylink_validate(chip, port, mask, state); 558 } 559 560 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 561 unsigned long *supported, 562 struct phylink_link_state *state) 563 { 564 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 565 struct mv88e6xxx_chip *chip = ds->priv; 566 567 /* Allow all the expected bits */ 568 phylink_set(mask, Autoneg); 569 phylink_set(mask, Pause); 570 phylink_set_port_modes(mask); 571 572 if (chip->info->ops->phylink_validate) 573 chip->info->ops->phylink_validate(chip, port, mask, state); 574 575 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 576 bitmap_and(state->advertising, state->advertising, mask, 577 __ETHTOOL_LINK_MODE_MASK_NBITS); 578 579 /* We can only operate at 2500BaseX or 1000BaseX. If requested 580 * to advertise both, only report advertising at 2500BaseX. 581 */ 582 phylink_helper_basex_speed(state); 583 } 584 585 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 586 struct phylink_link_state *state) 587 { 588 struct mv88e6xxx_chip *chip = ds->priv; 589 int err; 590 591 mv88e6xxx_reg_lock(chip); 592 if (chip->info->ops->port_link_state) 593 err = chip->info->ops->port_link_state(chip, port, state); 594 else 595 err = -EOPNOTSUPP; 596 mv88e6xxx_reg_unlock(chip); 597 598 return err; 599 } 600 601 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 602 unsigned int mode, 603 const struct phylink_link_state *state) 604 { 605 struct mv88e6xxx_chip *chip = ds->priv; 606 int speed, duplex, link, pause, err; 607 608 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 609 return; 610 611 if (mode == MLO_AN_FIXED) { 612 link = LINK_FORCED_UP; 613 speed = state->speed; 614 duplex = state->duplex; 615 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 616 link = state->link; 617 speed = state->speed; 618 duplex = state->duplex; 619 } else { 620 speed = SPEED_UNFORCED; 621 duplex = DUPLEX_UNFORCED; 622 link = LINK_UNFORCED; 623 } 624 pause = !!phylink_test(state->advertising, Pause); 625 626 mv88e6xxx_reg_lock(chip); 627 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 628 state->interface); 629 mv88e6xxx_reg_unlock(chip); 630 631 if (err && err != -EOPNOTSUPP) 632 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 633 } 634 635 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 636 { 637 struct mv88e6xxx_chip *chip = ds->priv; 638 int err; 639 640 mv88e6xxx_reg_lock(chip); 641 err = chip->info->ops->port_set_link(chip, port, link); 642 mv88e6xxx_reg_unlock(chip); 643 644 if (err) 645 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 646 } 647 648 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 649 unsigned int mode, 650 phy_interface_t interface) 651 { 652 if (mode == MLO_AN_FIXED) 653 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 654 } 655 656 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 657 unsigned int mode, phy_interface_t interface, 658 struct phy_device *phydev) 659 { 660 if (mode == MLO_AN_FIXED) 661 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 662 } 663 664 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 665 { 666 if (!chip->info->ops->stats_snapshot) 667 return -EOPNOTSUPP; 668 669 return chip->info->ops->stats_snapshot(chip, port); 670 } 671 672 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 673 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 674 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 675 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 676 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 677 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 678 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 679 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 680 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 681 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 682 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 683 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 684 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 685 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 686 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 687 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 688 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 689 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 690 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 691 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 692 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 693 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 694 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 695 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 696 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 697 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 698 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 699 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 700 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 701 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 702 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 703 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 704 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 705 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 706 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 707 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 708 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 709 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 710 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 711 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 712 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 713 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 714 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 715 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 716 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 717 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 718 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 719 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 720 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 721 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 722 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 723 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 724 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 725 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 726 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 727 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 728 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 729 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 730 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 731 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 732 }; 733 734 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 735 struct mv88e6xxx_hw_stat *s, 736 int port, u16 bank1_select, 737 u16 histogram) 738 { 739 u32 low; 740 u32 high = 0; 741 u16 reg = 0; 742 int err; 743 u64 value; 744 745 switch (s->type) { 746 case STATS_TYPE_PORT: 747 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 748 if (err) 749 return U64_MAX; 750 751 low = reg; 752 if (s->size == 4) { 753 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 754 if (err) 755 return U64_MAX; 756 low |= ((u32)reg) << 16; 757 } 758 break; 759 case STATS_TYPE_BANK1: 760 reg = bank1_select; 761 /* fall through */ 762 case STATS_TYPE_BANK0: 763 reg |= s->reg | histogram; 764 mv88e6xxx_g1_stats_read(chip, reg, &low); 765 if (s->size == 8) 766 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 767 break; 768 default: 769 return U64_MAX; 770 } 771 value = (((u64)high) << 32) | low; 772 return value; 773 } 774 775 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 776 uint8_t *data, int types) 777 { 778 struct mv88e6xxx_hw_stat *stat; 779 int i, j; 780 781 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 782 stat = &mv88e6xxx_hw_stats[i]; 783 if (stat->type & types) { 784 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 785 ETH_GSTRING_LEN); 786 j++; 787 } 788 } 789 790 return j; 791 } 792 793 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 794 uint8_t *data) 795 { 796 return mv88e6xxx_stats_get_strings(chip, data, 797 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 798 } 799 800 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 801 uint8_t *data) 802 { 803 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 804 } 805 806 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 807 uint8_t *data) 808 { 809 return mv88e6xxx_stats_get_strings(chip, data, 810 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 811 } 812 813 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 814 "atu_member_violation", 815 "atu_miss_violation", 816 "atu_full_violation", 817 "vtu_member_violation", 818 "vtu_miss_violation", 819 }; 820 821 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 822 { 823 unsigned int i; 824 825 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 826 strlcpy(data + i * ETH_GSTRING_LEN, 827 mv88e6xxx_atu_vtu_stats_strings[i], 828 ETH_GSTRING_LEN); 829 } 830 831 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 832 u32 stringset, uint8_t *data) 833 { 834 struct mv88e6xxx_chip *chip = ds->priv; 835 int count = 0; 836 837 if (stringset != ETH_SS_STATS) 838 return; 839 840 mv88e6xxx_reg_lock(chip); 841 842 if (chip->info->ops->stats_get_strings) 843 count = chip->info->ops->stats_get_strings(chip, data); 844 845 if (chip->info->ops->serdes_get_strings) { 846 data += count * ETH_GSTRING_LEN; 847 count = chip->info->ops->serdes_get_strings(chip, port, data); 848 } 849 850 data += count * ETH_GSTRING_LEN; 851 mv88e6xxx_atu_vtu_get_strings(data); 852 853 mv88e6xxx_reg_unlock(chip); 854 } 855 856 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 857 int types) 858 { 859 struct mv88e6xxx_hw_stat *stat; 860 int i, j; 861 862 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 863 stat = &mv88e6xxx_hw_stats[i]; 864 if (stat->type & types) 865 j++; 866 } 867 return j; 868 } 869 870 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 871 { 872 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 873 STATS_TYPE_PORT); 874 } 875 876 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 877 { 878 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 879 } 880 881 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 882 { 883 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 884 STATS_TYPE_BANK1); 885 } 886 887 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 888 { 889 struct mv88e6xxx_chip *chip = ds->priv; 890 int serdes_count = 0; 891 int count = 0; 892 893 if (sset != ETH_SS_STATS) 894 return 0; 895 896 mv88e6xxx_reg_lock(chip); 897 if (chip->info->ops->stats_get_sset_count) 898 count = chip->info->ops->stats_get_sset_count(chip); 899 if (count < 0) 900 goto out; 901 902 if (chip->info->ops->serdes_get_sset_count) 903 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 904 port); 905 if (serdes_count < 0) { 906 count = serdes_count; 907 goto out; 908 } 909 count += serdes_count; 910 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 911 912 out: 913 mv88e6xxx_reg_unlock(chip); 914 915 return count; 916 } 917 918 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 919 uint64_t *data, int types, 920 u16 bank1_select, u16 histogram) 921 { 922 struct mv88e6xxx_hw_stat *stat; 923 int i, j; 924 925 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 926 stat = &mv88e6xxx_hw_stats[i]; 927 if (stat->type & types) { 928 mv88e6xxx_reg_lock(chip); 929 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 930 bank1_select, 931 histogram); 932 mv88e6xxx_reg_unlock(chip); 933 934 j++; 935 } 936 } 937 return j; 938 } 939 940 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 941 uint64_t *data) 942 { 943 return mv88e6xxx_stats_get_stats(chip, port, data, 944 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 945 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 946 } 947 948 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 949 uint64_t *data) 950 { 951 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 952 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 953 } 954 955 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 956 uint64_t *data) 957 { 958 return mv88e6xxx_stats_get_stats(chip, port, data, 959 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 960 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 961 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 962 } 963 964 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 965 uint64_t *data) 966 { 967 return mv88e6xxx_stats_get_stats(chip, port, data, 968 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 969 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 970 0); 971 } 972 973 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 974 uint64_t *data) 975 { 976 *data++ = chip->ports[port].atu_member_violation; 977 *data++ = chip->ports[port].atu_miss_violation; 978 *data++ = chip->ports[port].atu_full_violation; 979 *data++ = chip->ports[port].vtu_member_violation; 980 *data++ = chip->ports[port].vtu_miss_violation; 981 } 982 983 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 984 uint64_t *data) 985 { 986 int count = 0; 987 988 if (chip->info->ops->stats_get_stats) 989 count = chip->info->ops->stats_get_stats(chip, port, data); 990 991 mv88e6xxx_reg_lock(chip); 992 if (chip->info->ops->serdes_get_stats) { 993 data += count; 994 count = chip->info->ops->serdes_get_stats(chip, port, data); 995 } 996 data += count; 997 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 998 mv88e6xxx_reg_unlock(chip); 999 } 1000 1001 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1002 uint64_t *data) 1003 { 1004 struct mv88e6xxx_chip *chip = ds->priv; 1005 int ret; 1006 1007 mv88e6xxx_reg_lock(chip); 1008 1009 ret = mv88e6xxx_stats_snapshot(chip, port); 1010 mv88e6xxx_reg_unlock(chip); 1011 1012 if (ret < 0) 1013 return; 1014 1015 mv88e6xxx_get_stats(chip, port, data); 1016 1017 } 1018 1019 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1020 { 1021 return 32 * sizeof(u16); 1022 } 1023 1024 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1025 struct ethtool_regs *regs, void *_p) 1026 { 1027 struct mv88e6xxx_chip *chip = ds->priv; 1028 int err; 1029 u16 reg; 1030 u16 *p = _p; 1031 int i; 1032 1033 regs->version = chip->info->prod_num; 1034 1035 memset(p, 0xff, 32 * sizeof(u16)); 1036 1037 mv88e6xxx_reg_lock(chip); 1038 1039 for (i = 0; i < 32; i++) { 1040 1041 err = mv88e6xxx_port_read(chip, port, i, ®); 1042 if (!err) 1043 p[i] = reg; 1044 } 1045 1046 mv88e6xxx_reg_unlock(chip); 1047 } 1048 1049 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1050 struct ethtool_eee *e) 1051 { 1052 /* Nothing to do on the port's MAC */ 1053 return 0; 1054 } 1055 1056 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1057 struct ethtool_eee *e) 1058 { 1059 /* Nothing to do on the port's MAC */ 1060 return 0; 1061 } 1062 1063 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1064 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1065 { 1066 struct dsa_switch *ds = chip->ds; 1067 struct dsa_switch_tree *dst = ds->dst; 1068 struct net_device *br; 1069 struct dsa_port *dp; 1070 bool found = false; 1071 u16 pvlan; 1072 1073 list_for_each_entry(dp, &dst->ports, list) { 1074 if (dp->ds->index == dev && dp->index == port) { 1075 found = true; 1076 break; 1077 } 1078 } 1079 1080 /* Prevent frames from unknown switch or port */ 1081 if (!found) 1082 return 0; 1083 1084 /* Frames from DSA links and CPU ports can egress any local port */ 1085 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1086 return mv88e6xxx_port_mask(chip); 1087 1088 br = dp->bridge_dev; 1089 pvlan = 0; 1090 1091 /* Frames from user ports can egress any local DSA links and CPU ports, 1092 * as well as any local member of their bridge group. 1093 */ 1094 list_for_each_entry(dp, &dst->ports, list) 1095 if (dp->ds == ds && 1096 (dp->type == DSA_PORT_TYPE_CPU || 1097 dp->type == DSA_PORT_TYPE_DSA || 1098 (br && dp->bridge_dev == br))) 1099 pvlan |= BIT(dp->index); 1100 1101 return pvlan; 1102 } 1103 1104 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1105 { 1106 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1107 1108 /* prevent frames from going back out of the port they came in on */ 1109 output_ports &= ~BIT(port); 1110 1111 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1112 } 1113 1114 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1115 u8 state) 1116 { 1117 struct mv88e6xxx_chip *chip = ds->priv; 1118 int err; 1119 1120 mv88e6xxx_reg_lock(chip); 1121 err = mv88e6xxx_port_set_state(chip, port, state); 1122 mv88e6xxx_reg_unlock(chip); 1123 1124 if (err) 1125 dev_err(ds->dev, "p%d: failed to update state\n", port); 1126 } 1127 1128 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1129 { 1130 int err; 1131 1132 if (chip->info->ops->ieee_pri_map) { 1133 err = chip->info->ops->ieee_pri_map(chip); 1134 if (err) 1135 return err; 1136 } 1137 1138 if (chip->info->ops->ip_pri_map) { 1139 err = chip->info->ops->ip_pri_map(chip); 1140 if (err) 1141 return err; 1142 } 1143 1144 return 0; 1145 } 1146 1147 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1148 { 1149 struct dsa_switch *ds = chip->ds; 1150 int target, port; 1151 int err; 1152 1153 if (!chip->info->global2_addr) 1154 return 0; 1155 1156 /* Initialize the routing port to the 32 possible target devices */ 1157 for (target = 0; target < 32; target++) { 1158 port = dsa_routing_port(ds, target); 1159 if (port == ds->num_ports) 1160 port = 0x1f; 1161 1162 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1163 if (err) 1164 return err; 1165 } 1166 1167 if (chip->info->ops->set_cascade_port) { 1168 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1169 err = chip->info->ops->set_cascade_port(chip, port); 1170 if (err) 1171 return err; 1172 } 1173 1174 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1175 if (err) 1176 return err; 1177 1178 return 0; 1179 } 1180 1181 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1182 { 1183 /* Clear all trunk masks and mapping */ 1184 if (chip->info->global2_addr) 1185 return mv88e6xxx_g2_trunk_clear(chip); 1186 1187 return 0; 1188 } 1189 1190 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1191 { 1192 if (chip->info->ops->rmu_disable) 1193 return chip->info->ops->rmu_disable(chip); 1194 1195 return 0; 1196 } 1197 1198 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1199 { 1200 if (chip->info->ops->pot_clear) 1201 return chip->info->ops->pot_clear(chip); 1202 1203 return 0; 1204 } 1205 1206 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1207 { 1208 if (chip->info->ops->mgmt_rsvd2cpu) 1209 return chip->info->ops->mgmt_rsvd2cpu(chip); 1210 1211 return 0; 1212 } 1213 1214 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1215 { 1216 int err; 1217 1218 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1219 if (err) 1220 return err; 1221 1222 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1223 if (err) 1224 return err; 1225 1226 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1227 } 1228 1229 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1230 { 1231 int port; 1232 int err; 1233 1234 if (!chip->info->ops->irl_init_all) 1235 return 0; 1236 1237 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1238 /* Disable ingress rate limiting by resetting all per port 1239 * ingress rate limit resources to their initial state. 1240 */ 1241 err = chip->info->ops->irl_init_all(chip, port); 1242 if (err) 1243 return err; 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1250 { 1251 if (chip->info->ops->set_switch_mac) { 1252 u8 addr[ETH_ALEN]; 1253 1254 eth_random_addr(addr); 1255 1256 return chip->info->ops->set_switch_mac(chip, addr); 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1263 { 1264 u16 pvlan = 0; 1265 1266 if (!mv88e6xxx_has_pvt(chip)) 1267 return 0; 1268 1269 /* Skip the local source device, which uses in-chip port VLAN */ 1270 if (dev != chip->ds->index) 1271 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1272 1273 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1274 } 1275 1276 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1277 { 1278 int dev, port; 1279 int err; 1280 1281 if (!mv88e6xxx_has_pvt(chip)) 1282 return 0; 1283 1284 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1285 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1286 */ 1287 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1288 if (err) 1289 return err; 1290 1291 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1292 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1293 err = mv88e6xxx_pvt_map(chip, dev, port); 1294 if (err) 1295 return err; 1296 } 1297 } 1298 1299 return 0; 1300 } 1301 1302 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1303 { 1304 struct mv88e6xxx_chip *chip = ds->priv; 1305 int err; 1306 1307 mv88e6xxx_reg_lock(chip); 1308 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1309 mv88e6xxx_reg_unlock(chip); 1310 1311 if (err) 1312 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1313 } 1314 1315 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1316 { 1317 if (!chip->info->max_vid) 1318 return 0; 1319 1320 return mv88e6xxx_g1_vtu_flush(chip); 1321 } 1322 1323 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1324 struct mv88e6xxx_vtu_entry *entry) 1325 { 1326 if (!chip->info->ops->vtu_getnext) 1327 return -EOPNOTSUPP; 1328 1329 return chip->info->ops->vtu_getnext(chip, entry); 1330 } 1331 1332 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1333 struct mv88e6xxx_vtu_entry *entry) 1334 { 1335 if (!chip->info->ops->vtu_loadpurge) 1336 return -EOPNOTSUPP; 1337 1338 return chip->info->ops->vtu_loadpurge(chip, entry); 1339 } 1340 1341 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1342 { 1343 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1344 struct mv88e6xxx_vtu_entry vlan; 1345 int i, err; 1346 1347 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1348 1349 /* Set every FID bit used by the (un)bridged ports */ 1350 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1351 err = mv88e6xxx_port_get_fid(chip, i, fid); 1352 if (err) 1353 return err; 1354 1355 set_bit(*fid, fid_bitmap); 1356 } 1357 1358 /* Set every FID bit used by the VLAN entries */ 1359 vlan.vid = chip->info->max_vid; 1360 vlan.valid = false; 1361 1362 do { 1363 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1364 if (err) 1365 return err; 1366 1367 if (!vlan.valid) 1368 break; 1369 1370 set_bit(vlan.fid, fid_bitmap); 1371 } while (vlan.vid < chip->info->max_vid); 1372 1373 /* The reset value 0x000 is used to indicate that multiple address 1374 * databases are not needed. Return the next positive available. 1375 */ 1376 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1377 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1378 return -ENOSPC; 1379 1380 /* Clear the database */ 1381 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1382 } 1383 1384 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 1385 { 1386 if (chip->info->ops->atu_get_hash) 1387 return chip->info->ops->atu_get_hash(chip, hash); 1388 1389 return -EOPNOTSUPP; 1390 } 1391 1392 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 1393 { 1394 if (chip->info->ops->atu_set_hash) 1395 return chip->info->ops->atu_set_hash(chip, hash); 1396 1397 return -EOPNOTSUPP; 1398 } 1399 1400 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1401 u16 vid_begin, u16 vid_end) 1402 { 1403 struct mv88e6xxx_chip *chip = ds->priv; 1404 struct mv88e6xxx_vtu_entry vlan; 1405 int i, err; 1406 1407 /* DSA and CPU ports have to be members of multiple vlans */ 1408 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1409 return 0; 1410 1411 if (!vid_begin) 1412 return -EOPNOTSUPP; 1413 1414 vlan.vid = vid_begin - 1; 1415 vlan.valid = false; 1416 1417 do { 1418 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1419 if (err) 1420 return err; 1421 1422 if (!vlan.valid) 1423 break; 1424 1425 if (vlan.vid > vid_end) 1426 break; 1427 1428 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1429 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1430 continue; 1431 1432 if (!dsa_to_port(ds, i)->slave) 1433 continue; 1434 1435 if (vlan.member[i] == 1436 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1437 continue; 1438 1439 if (dsa_to_port(ds, i)->bridge_dev == 1440 dsa_to_port(ds, port)->bridge_dev) 1441 break; /* same bridge, check next VLAN */ 1442 1443 if (!dsa_to_port(ds, i)->bridge_dev) 1444 continue; 1445 1446 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1447 port, vlan.vid, i, 1448 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1449 return -EOPNOTSUPP; 1450 } 1451 } while (vlan.vid < vid_end); 1452 1453 return 0; 1454 } 1455 1456 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1457 bool vlan_filtering) 1458 { 1459 struct mv88e6xxx_chip *chip = ds->priv; 1460 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1461 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1462 int err; 1463 1464 if (!chip->info->max_vid) 1465 return -EOPNOTSUPP; 1466 1467 mv88e6xxx_reg_lock(chip); 1468 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1469 mv88e6xxx_reg_unlock(chip); 1470 1471 return err; 1472 } 1473 1474 static int 1475 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1476 const struct switchdev_obj_port_vlan *vlan) 1477 { 1478 struct mv88e6xxx_chip *chip = ds->priv; 1479 int err; 1480 1481 if (!chip->info->max_vid) 1482 return -EOPNOTSUPP; 1483 1484 /* If the requested port doesn't belong to the same bridge as the VLAN 1485 * members, do not support it (yet) and fallback to software VLAN. 1486 */ 1487 mv88e6xxx_reg_lock(chip); 1488 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1489 vlan->vid_end); 1490 mv88e6xxx_reg_unlock(chip); 1491 1492 /* We don't need any dynamic resource from the kernel (yet), 1493 * so skip the prepare phase. 1494 */ 1495 return err; 1496 } 1497 1498 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1499 const unsigned char *addr, u16 vid, 1500 u8 state) 1501 { 1502 struct mv88e6xxx_atu_entry entry; 1503 struct mv88e6xxx_vtu_entry vlan; 1504 u16 fid; 1505 int err; 1506 1507 /* Null VLAN ID corresponds to the port private database */ 1508 if (vid == 0) { 1509 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1510 if (err) 1511 return err; 1512 } else { 1513 vlan.vid = vid - 1; 1514 vlan.valid = false; 1515 1516 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1517 if (err) 1518 return err; 1519 1520 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1521 if (vlan.vid != vid || !vlan.valid) 1522 return -EOPNOTSUPP; 1523 1524 fid = vlan.fid; 1525 } 1526 1527 entry.state = 0; 1528 ether_addr_copy(entry.mac, addr); 1529 eth_addr_dec(entry.mac); 1530 1531 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1532 if (err) 1533 return err; 1534 1535 /* Initialize a fresh ATU entry if it isn't found */ 1536 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1537 memset(&entry, 0, sizeof(entry)); 1538 ether_addr_copy(entry.mac, addr); 1539 } 1540 1541 /* Purge the ATU entry only if no port is using it anymore */ 1542 if (!state) { 1543 entry.portvec &= ~BIT(port); 1544 if (!entry.portvec) 1545 entry.state = 0; 1546 } else { 1547 entry.portvec |= BIT(port); 1548 entry.state = state; 1549 } 1550 1551 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1552 } 1553 1554 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1555 const struct mv88e6xxx_policy *policy) 1556 { 1557 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1558 enum mv88e6xxx_policy_action action = policy->action; 1559 const u8 *addr = policy->addr; 1560 u16 vid = policy->vid; 1561 u8 state; 1562 int err; 1563 int id; 1564 1565 if (!chip->info->ops->port_set_policy) 1566 return -EOPNOTSUPP; 1567 1568 switch (mapping) { 1569 case MV88E6XXX_POLICY_MAPPING_DA: 1570 case MV88E6XXX_POLICY_MAPPING_SA: 1571 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1572 state = 0; /* Dissociate the port and address */ 1573 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1574 is_multicast_ether_addr(addr)) 1575 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1576 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1577 is_unicast_ether_addr(addr)) 1578 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1579 else 1580 return -EOPNOTSUPP; 1581 1582 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1583 state); 1584 if (err) 1585 return err; 1586 break; 1587 default: 1588 return -EOPNOTSUPP; 1589 } 1590 1591 /* Skip the port's policy clearing if the mapping is still in use */ 1592 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1593 idr_for_each_entry(&chip->policies, policy, id) 1594 if (policy->port == port && 1595 policy->mapping == mapping && 1596 policy->action != action) 1597 return 0; 1598 1599 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1600 } 1601 1602 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1603 struct ethtool_rx_flow_spec *fs) 1604 { 1605 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1606 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1607 enum mv88e6xxx_policy_mapping mapping; 1608 enum mv88e6xxx_policy_action action; 1609 struct mv88e6xxx_policy *policy; 1610 u16 vid = 0; 1611 u8 *addr; 1612 int err; 1613 int id; 1614 1615 if (fs->location != RX_CLS_LOC_ANY) 1616 return -EINVAL; 1617 1618 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1619 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1620 else 1621 return -EOPNOTSUPP; 1622 1623 switch (fs->flow_type & ~FLOW_EXT) { 1624 case ETHER_FLOW: 1625 if (!is_zero_ether_addr(mac_mask->h_dest) && 1626 is_zero_ether_addr(mac_mask->h_source)) { 1627 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1628 addr = mac_entry->h_dest; 1629 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1630 !is_zero_ether_addr(mac_mask->h_source)) { 1631 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1632 addr = mac_entry->h_source; 1633 } else { 1634 /* Cannot support DA and SA mapping in the same rule */ 1635 return -EOPNOTSUPP; 1636 } 1637 break; 1638 default: 1639 return -EOPNOTSUPP; 1640 } 1641 1642 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1643 if (fs->m_ext.vlan_tci != 0xffff) 1644 return -EOPNOTSUPP; 1645 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1646 } 1647 1648 idr_for_each_entry(&chip->policies, policy, id) { 1649 if (policy->port == port && policy->mapping == mapping && 1650 policy->action == action && policy->vid == vid && 1651 ether_addr_equal(policy->addr, addr)) 1652 return -EEXIST; 1653 } 1654 1655 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1656 if (!policy) 1657 return -ENOMEM; 1658 1659 fs->location = 0; 1660 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1661 GFP_KERNEL); 1662 if (err) { 1663 devm_kfree(chip->dev, policy); 1664 return err; 1665 } 1666 1667 memcpy(&policy->fs, fs, sizeof(*fs)); 1668 ether_addr_copy(policy->addr, addr); 1669 policy->mapping = mapping; 1670 policy->action = action; 1671 policy->port = port; 1672 policy->vid = vid; 1673 1674 err = mv88e6xxx_policy_apply(chip, port, policy); 1675 if (err) { 1676 idr_remove(&chip->policies, fs->location); 1677 devm_kfree(chip->dev, policy); 1678 return err; 1679 } 1680 1681 return 0; 1682 } 1683 1684 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1685 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1686 { 1687 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1688 struct mv88e6xxx_chip *chip = ds->priv; 1689 struct mv88e6xxx_policy *policy; 1690 int err; 1691 int id; 1692 1693 mv88e6xxx_reg_lock(chip); 1694 1695 switch (rxnfc->cmd) { 1696 case ETHTOOL_GRXCLSRLCNT: 1697 rxnfc->data = 0; 1698 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1699 rxnfc->rule_cnt = 0; 1700 idr_for_each_entry(&chip->policies, policy, id) 1701 if (policy->port == port) 1702 rxnfc->rule_cnt++; 1703 err = 0; 1704 break; 1705 case ETHTOOL_GRXCLSRULE: 1706 err = -ENOENT; 1707 policy = idr_find(&chip->policies, fs->location); 1708 if (policy) { 1709 memcpy(fs, &policy->fs, sizeof(*fs)); 1710 err = 0; 1711 } 1712 break; 1713 case ETHTOOL_GRXCLSRLALL: 1714 rxnfc->data = 0; 1715 rxnfc->rule_cnt = 0; 1716 idr_for_each_entry(&chip->policies, policy, id) 1717 if (policy->port == port) 1718 rule_locs[rxnfc->rule_cnt++] = id; 1719 err = 0; 1720 break; 1721 default: 1722 err = -EOPNOTSUPP; 1723 break; 1724 } 1725 1726 mv88e6xxx_reg_unlock(chip); 1727 1728 return err; 1729 } 1730 1731 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1732 struct ethtool_rxnfc *rxnfc) 1733 { 1734 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1735 struct mv88e6xxx_chip *chip = ds->priv; 1736 struct mv88e6xxx_policy *policy; 1737 int err; 1738 1739 mv88e6xxx_reg_lock(chip); 1740 1741 switch (rxnfc->cmd) { 1742 case ETHTOOL_SRXCLSRLINS: 1743 err = mv88e6xxx_policy_insert(chip, port, fs); 1744 break; 1745 case ETHTOOL_SRXCLSRLDEL: 1746 err = -ENOENT; 1747 policy = idr_remove(&chip->policies, fs->location); 1748 if (policy) { 1749 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1750 err = mv88e6xxx_policy_apply(chip, port, policy); 1751 devm_kfree(chip->dev, policy); 1752 } 1753 break; 1754 default: 1755 err = -EOPNOTSUPP; 1756 break; 1757 } 1758 1759 mv88e6xxx_reg_unlock(chip); 1760 1761 return err; 1762 } 1763 1764 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1765 u16 vid) 1766 { 1767 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1768 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1769 1770 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1771 } 1772 1773 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1774 { 1775 int port; 1776 int err; 1777 1778 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1779 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1780 if (err) 1781 return err; 1782 } 1783 1784 return 0; 1785 } 1786 1787 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1788 u16 vid, u8 member) 1789 { 1790 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1791 struct mv88e6xxx_vtu_entry vlan; 1792 int i, err; 1793 1794 if (!vid) 1795 return -EOPNOTSUPP; 1796 1797 vlan.vid = vid - 1; 1798 vlan.valid = false; 1799 1800 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1801 if (err) 1802 return err; 1803 1804 if (vlan.vid != vid || !vlan.valid) { 1805 memset(&vlan, 0, sizeof(vlan)); 1806 1807 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1808 if (err) 1809 return err; 1810 1811 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1812 if (i == port) 1813 vlan.member[i] = member; 1814 else 1815 vlan.member[i] = non_member; 1816 1817 vlan.vid = vid; 1818 vlan.valid = true; 1819 1820 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1821 if (err) 1822 return err; 1823 1824 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1825 if (err) 1826 return err; 1827 } else if (vlan.member[port] != member) { 1828 vlan.member[port] = member; 1829 1830 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1831 if (err) 1832 return err; 1833 } else { 1834 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1835 port, vid); 1836 } 1837 1838 return 0; 1839 } 1840 1841 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1842 const struct switchdev_obj_port_vlan *vlan) 1843 { 1844 struct mv88e6xxx_chip *chip = ds->priv; 1845 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1846 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1847 u8 member; 1848 u16 vid; 1849 1850 if (!chip->info->max_vid) 1851 return; 1852 1853 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1854 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1855 else if (untagged) 1856 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1857 else 1858 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1859 1860 mv88e6xxx_reg_lock(chip); 1861 1862 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1863 if (mv88e6xxx_port_vlan_join(chip, port, vid, member)) 1864 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1865 vid, untagged ? 'u' : 't'); 1866 1867 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1868 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1869 vlan->vid_end); 1870 1871 mv88e6xxx_reg_unlock(chip); 1872 } 1873 1874 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1875 int port, u16 vid) 1876 { 1877 struct mv88e6xxx_vtu_entry vlan; 1878 int i, err; 1879 1880 if (!vid) 1881 return -EOPNOTSUPP; 1882 1883 vlan.vid = vid - 1; 1884 vlan.valid = false; 1885 1886 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1887 if (err) 1888 return err; 1889 1890 /* If the VLAN doesn't exist in hardware or the port isn't a member, 1891 * tell switchdev that this VLAN is likely handled in software. 1892 */ 1893 if (vlan.vid != vid || !vlan.valid || 1894 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1895 return -EOPNOTSUPP; 1896 1897 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1898 1899 /* keep the VLAN unless all ports are excluded */ 1900 vlan.valid = false; 1901 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1902 if (vlan.member[i] != 1903 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1904 vlan.valid = true; 1905 break; 1906 } 1907 } 1908 1909 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1910 if (err) 1911 return err; 1912 1913 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1914 } 1915 1916 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1917 const struct switchdev_obj_port_vlan *vlan) 1918 { 1919 struct mv88e6xxx_chip *chip = ds->priv; 1920 u16 pvid, vid; 1921 int err = 0; 1922 1923 if (!chip->info->max_vid) 1924 return -EOPNOTSUPP; 1925 1926 mv88e6xxx_reg_lock(chip); 1927 1928 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1929 if (err) 1930 goto unlock; 1931 1932 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1933 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 1934 if (err) 1935 goto unlock; 1936 1937 if (vid == pvid) { 1938 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1939 if (err) 1940 goto unlock; 1941 } 1942 } 1943 1944 unlock: 1945 mv88e6xxx_reg_unlock(chip); 1946 1947 return err; 1948 } 1949 1950 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1951 const unsigned char *addr, u16 vid) 1952 { 1953 struct mv88e6xxx_chip *chip = ds->priv; 1954 int err; 1955 1956 mv88e6xxx_reg_lock(chip); 1957 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1958 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1959 mv88e6xxx_reg_unlock(chip); 1960 1961 return err; 1962 } 1963 1964 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1965 const unsigned char *addr, u16 vid) 1966 { 1967 struct mv88e6xxx_chip *chip = ds->priv; 1968 int err; 1969 1970 mv88e6xxx_reg_lock(chip); 1971 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 1972 mv88e6xxx_reg_unlock(chip); 1973 1974 return err; 1975 } 1976 1977 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1978 u16 fid, u16 vid, int port, 1979 dsa_fdb_dump_cb_t *cb, void *data) 1980 { 1981 struct mv88e6xxx_atu_entry addr; 1982 bool is_static; 1983 int err; 1984 1985 addr.state = 0; 1986 eth_broadcast_addr(addr.mac); 1987 1988 do { 1989 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1990 if (err) 1991 return err; 1992 1993 if (!addr.state) 1994 break; 1995 1996 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1997 continue; 1998 1999 if (!is_unicast_ether_addr(addr.mac)) 2000 continue; 2001 2002 is_static = (addr.state == 2003 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2004 err = cb(addr.mac, vid, is_static, data); 2005 if (err) 2006 return err; 2007 } while (!is_broadcast_ether_addr(addr.mac)); 2008 2009 return err; 2010 } 2011 2012 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2013 dsa_fdb_dump_cb_t *cb, void *data) 2014 { 2015 struct mv88e6xxx_vtu_entry vlan; 2016 u16 fid; 2017 int err; 2018 2019 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2020 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2021 if (err) 2022 return err; 2023 2024 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2025 if (err) 2026 return err; 2027 2028 /* Dump VLANs' Filtering Information Databases */ 2029 vlan.vid = chip->info->max_vid; 2030 vlan.valid = false; 2031 2032 do { 2033 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2034 if (err) 2035 return err; 2036 2037 if (!vlan.valid) 2038 break; 2039 2040 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2041 cb, data); 2042 if (err) 2043 return err; 2044 } while (vlan.vid < chip->info->max_vid); 2045 2046 return err; 2047 } 2048 2049 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2050 dsa_fdb_dump_cb_t *cb, void *data) 2051 { 2052 struct mv88e6xxx_chip *chip = ds->priv; 2053 int err; 2054 2055 mv88e6xxx_reg_lock(chip); 2056 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2057 mv88e6xxx_reg_unlock(chip); 2058 2059 return err; 2060 } 2061 2062 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2063 struct net_device *br) 2064 { 2065 struct dsa_switch *ds = chip->ds; 2066 struct dsa_switch_tree *dst = ds->dst; 2067 struct dsa_port *dp; 2068 int err; 2069 2070 list_for_each_entry(dp, &dst->ports, list) { 2071 if (dp->bridge_dev == br) { 2072 if (dp->ds == ds) { 2073 /* This is a local bridge group member, 2074 * remap its Port VLAN Map. 2075 */ 2076 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2077 if (err) 2078 return err; 2079 } else { 2080 /* This is an external bridge group member, 2081 * remap its cross-chip Port VLAN Table entry. 2082 */ 2083 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2084 dp->index); 2085 if (err) 2086 return err; 2087 } 2088 } 2089 } 2090 2091 return 0; 2092 } 2093 2094 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2095 struct net_device *br) 2096 { 2097 struct mv88e6xxx_chip *chip = ds->priv; 2098 int err; 2099 2100 mv88e6xxx_reg_lock(chip); 2101 err = mv88e6xxx_bridge_map(chip, br); 2102 mv88e6xxx_reg_unlock(chip); 2103 2104 return err; 2105 } 2106 2107 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2108 struct net_device *br) 2109 { 2110 struct mv88e6xxx_chip *chip = ds->priv; 2111 2112 mv88e6xxx_reg_lock(chip); 2113 if (mv88e6xxx_bridge_map(chip, br) || 2114 mv88e6xxx_port_vlan_map(chip, port)) 2115 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2116 mv88e6xxx_reg_unlock(chip); 2117 } 2118 2119 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 2120 int port, struct net_device *br) 2121 { 2122 struct mv88e6xxx_chip *chip = ds->priv; 2123 int err; 2124 2125 mv88e6xxx_reg_lock(chip); 2126 err = mv88e6xxx_pvt_map(chip, dev, port); 2127 mv88e6xxx_reg_unlock(chip); 2128 2129 return err; 2130 } 2131 2132 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 2133 int port, struct net_device *br) 2134 { 2135 struct mv88e6xxx_chip *chip = ds->priv; 2136 2137 mv88e6xxx_reg_lock(chip); 2138 if (mv88e6xxx_pvt_map(chip, dev, port)) 2139 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2140 mv88e6xxx_reg_unlock(chip); 2141 } 2142 2143 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2144 { 2145 if (chip->info->ops->reset) 2146 return chip->info->ops->reset(chip); 2147 2148 return 0; 2149 } 2150 2151 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2152 { 2153 struct gpio_desc *gpiod = chip->reset; 2154 2155 /* If there is a GPIO connected to the reset pin, toggle it */ 2156 if (gpiod) { 2157 gpiod_set_value_cansleep(gpiod, 1); 2158 usleep_range(10000, 20000); 2159 gpiod_set_value_cansleep(gpiod, 0); 2160 usleep_range(10000, 20000); 2161 } 2162 } 2163 2164 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2165 { 2166 int i, err; 2167 2168 /* Set all ports to the Disabled state */ 2169 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2170 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2171 if (err) 2172 return err; 2173 } 2174 2175 /* Wait for transmit queues to drain, 2176 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2177 */ 2178 usleep_range(2000, 4000); 2179 2180 return 0; 2181 } 2182 2183 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2184 { 2185 int err; 2186 2187 err = mv88e6xxx_disable_ports(chip); 2188 if (err) 2189 return err; 2190 2191 mv88e6xxx_hardware_reset(chip); 2192 2193 return mv88e6xxx_software_reset(chip); 2194 } 2195 2196 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2197 enum mv88e6xxx_frame_mode frame, 2198 enum mv88e6xxx_egress_mode egress, u16 etype) 2199 { 2200 int err; 2201 2202 if (!chip->info->ops->port_set_frame_mode) 2203 return -EOPNOTSUPP; 2204 2205 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2206 if (err) 2207 return err; 2208 2209 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2210 if (err) 2211 return err; 2212 2213 if (chip->info->ops->port_set_ether_type) 2214 return chip->info->ops->port_set_ether_type(chip, port, etype); 2215 2216 return 0; 2217 } 2218 2219 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2220 { 2221 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2222 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2223 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2224 } 2225 2226 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2227 { 2228 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2229 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2230 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2231 } 2232 2233 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2234 { 2235 return mv88e6xxx_set_port_mode(chip, port, 2236 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2237 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2238 ETH_P_EDSA); 2239 } 2240 2241 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2242 { 2243 if (dsa_is_dsa_port(chip->ds, port)) 2244 return mv88e6xxx_set_port_mode_dsa(chip, port); 2245 2246 if (dsa_is_user_port(chip->ds, port)) 2247 return mv88e6xxx_set_port_mode_normal(chip, port); 2248 2249 /* Setup CPU port mode depending on its supported tag format */ 2250 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2251 return mv88e6xxx_set_port_mode_dsa(chip, port); 2252 2253 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2254 return mv88e6xxx_set_port_mode_edsa(chip, port); 2255 2256 return -EINVAL; 2257 } 2258 2259 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2260 { 2261 bool message = dsa_is_dsa_port(chip->ds, port); 2262 2263 return mv88e6xxx_port_set_message_port(chip, port, message); 2264 } 2265 2266 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2267 { 2268 struct dsa_switch *ds = chip->ds; 2269 bool flood; 2270 2271 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2272 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2273 if (chip->info->ops->port_set_egress_floods) 2274 return chip->info->ops->port_set_egress_floods(chip, port, 2275 flood, flood); 2276 2277 return 0; 2278 } 2279 2280 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2281 { 2282 struct mv88e6xxx_port *mvp = dev_id; 2283 struct mv88e6xxx_chip *chip = mvp->chip; 2284 irqreturn_t ret = IRQ_NONE; 2285 int port = mvp->port; 2286 u8 lane; 2287 2288 mv88e6xxx_reg_lock(chip); 2289 lane = mv88e6xxx_serdes_get_lane(chip, port); 2290 if (lane) 2291 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2292 mv88e6xxx_reg_unlock(chip); 2293 2294 return ret; 2295 } 2296 2297 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2298 u8 lane) 2299 { 2300 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2301 unsigned int irq; 2302 int err; 2303 2304 /* Nothing to request if this SERDES port has no IRQ */ 2305 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2306 if (!irq) 2307 return 0; 2308 2309 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2310 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2311 2312 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2313 mv88e6xxx_reg_unlock(chip); 2314 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2315 IRQF_ONESHOT, dev_id->serdes_irq_name, 2316 dev_id); 2317 mv88e6xxx_reg_lock(chip); 2318 if (err) 2319 return err; 2320 2321 dev_id->serdes_irq = irq; 2322 2323 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2324 } 2325 2326 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2327 u8 lane) 2328 { 2329 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2330 unsigned int irq = dev_id->serdes_irq; 2331 int err; 2332 2333 /* Nothing to free if no IRQ has been requested */ 2334 if (!irq) 2335 return 0; 2336 2337 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2338 2339 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2340 mv88e6xxx_reg_unlock(chip); 2341 free_irq(irq, dev_id); 2342 mv88e6xxx_reg_lock(chip); 2343 2344 dev_id->serdes_irq = 0; 2345 2346 return err; 2347 } 2348 2349 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2350 bool on) 2351 { 2352 u8 lane; 2353 int err; 2354 2355 lane = mv88e6xxx_serdes_get_lane(chip, port); 2356 if (!lane) 2357 return 0; 2358 2359 if (on) { 2360 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2361 if (err) 2362 return err; 2363 2364 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2365 } else { 2366 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2367 if (err) 2368 return err; 2369 2370 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2371 } 2372 2373 return err; 2374 } 2375 2376 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2377 { 2378 struct dsa_switch *ds = chip->ds; 2379 int upstream_port; 2380 int err; 2381 2382 upstream_port = dsa_upstream_port(ds, port); 2383 if (chip->info->ops->port_set_upstream_port) { 2384 err = chip->info->ops->port_set_upstream_port(chip, port, 2385 upstream_port); 2386 if (err) 2387 return err; 2388 } 2389 2390 if (port == upstream_port) { 2391 if (chip->info->ops->set_cpu_port) { 2392 err = chip->info->ops->set_cpu_port(chip, 2393 upstream_port); 2394 if (err) 2395 return err; 2396 } 2397 2398 if (chip->info->ops->set_egress_port) { 2399 err = chip->info->ops->set_egress_port(chip, 2400 MV88E6XXX_EGRESS_DIR_INGRESS, 2401 upstream_port); 2402 if (err) 2403 return err; 2404 2405 err = chip->info->ops->set_egress_port(chip, 2406 MV88E6XXX_EGRESS_DIR_EGRESS, 2407 upstream_port); 2408 if (err) 2409 return err; 2410 } 2411 } 2412 2413 return 0; 2414 } 2415 2416 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2417 { 2418 struct dsa_switch *ds = chip->ds; 2419 int err; 2420 u16 reg; 2421 2422 chip->ports[port].chip = chip; 2423 chip->ports[port].port = port; 2424 2425 /* MAC Forcing register: don't force link, speed, duplex or flow control 2426 * state to any particular values on physical ports, but force the CPU 2427 * port and all DSA ports to their maximum bandwidth and full duplex. 2428 */ 2429 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2430 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2431 SPEED_MAX, DUPLEX_FULL, 2432 PAUSE_OFF, 2433 PHY_INTERFACE_MODE_NA); 2434 else 2435 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2436 SPEED_UNFORCED, DUPLEX_UNFORCED, 2437 PAUSE_ON, 2438 PHY_INTERFACE_MODE_NA); 2439 if (err) 2440 return err; 2441 2442 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2443 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2444 * tunneling, determine priority by looking at 802.1p and IP 2445 * priority fields (IP prio has precedence), and set STP state 2446 * to Forwarding. 2447 * 2448 * If this is the CPU link, use DSA or EDSA tagging depending 2449 * on which tagging mode was configured. 2450 * 2451 * If this is a link to another switch, use DSA tagging mode. 2452 * 2453 * If this is the upstream port for this switch, enable 2454 * forwarding of unknown unicasts and multicasts. 2455 */ 2456 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2457 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2458 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2459 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2460 if (err) 2461 return err; 2462 2463 err = mv88e6xxx_setup_port_mode(chip, port); 2464 if (err) 2465 return err; 2466 2467 err = mv88e6xxx_setup_egress_floods(chip, port); 2468 if (err) 2469 return err; 2470 2471 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2472 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2473 * untagged frames on this port, do a destination address lookup on all 2474 * received packets as usual, disable ARP mirroring and don't send a 2475 * copy of all transmitted/received frames on this port to the CPU. 2476 */ 2477 err = mv88e6xxx_port_set_map_da(chip, port); 2478 if (err) 2479 return err; 2480 2481 err = mv88e6xxx_setup_upstream_port(chip, port); 2482 if (err) 2483 return err; 2484 2485 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2486 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2487 if (err) 2488 return err; 2489 2490 if (chip->info->ops->port_set_jumbo_size) { 2491 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2492 if (err) 2493 return err; 2494 } 2495 2496 /* Port Association Vector: when learning source addresses 2497 * of packets, add the address to the address database using 2498 * a port bitmap that has only the bit for this port set and 2499 * the other bits clear. 2500 */ 2501 reg = 1 << port; 2502 /* Disable learning for CPU port */ 2503 if (dsa_is_cpu_port(ds, port)) 2504 reg = 0; 2505 2506 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2507 reg); 2508 if (err) 2509 return err; 2510 2511 /* Egress rate control 2: disable egress rate control. */ 2512 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2513 0x0000); 2514 if (err) 2515 return err; 2516 2517 if (chip->info->ops->port_pause_limit) { 2518 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2519 if (err) 2520 return err; 2521 } 2522 2523 if (chip->info->ops->port_disable_learn_limit) { 2524 err = chip->info->ops->port_disable_learn_limit(chip, port); 2525 if (err) 2526 return err; 2527 } 2528 2529 if (chip->info->ops->port_disable_pri_override) { 2530 err = chip->info->ops->port_disable_pri_override(chip, port); 2531 if (err) 2532 return err; 2533 } 2534 2535 if (chip->info->ops->port_tag_remap) { 2536 err = chip->info->ops->port_tag_remap(chip, port); 2537 if (err) 2538 return err; 2539 } 2540 2541 if (chip->info->ops->port_egress_rate_limiting) { 2542 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2543 if (err) 2544 return err; 2545 } 2546 2547 if (chip->info->ops->port_setup_message_port) { 2548 err = chip->info->ops->port_setup_message_port(chip, port); 2549 if (err) 2550 return err; 2551 } 2552 2553 /* Port based VLAN map: give each port the same default address 2554 * database, and allow bidirectional communication between the 2555 * CPU and DSA port(s), and the other ports. 2556 */ 2557 err = mv88e6xxx_port_set_fid(chip, port, 0); 2558 if (err) 2559 return err; 2560 2561 err = mv88e6xxx_port_vlan_map(chip, port); 2562 if (err) 2563 return err; 2564 2565 /* Default VLAN ID and priority: don't set a default VLAN 2566 * ID, and set the default packet priority to zero. 2567 */ 2568 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2569 } 2570 2571 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2572 struct phy_device *phydev) 2573 { 2574 struct mv88e6xxx_chip *chip = ds->priv; 2575 int err; 2576 2577 mv88e6xxx_reg_lock(chip); 2578 err = mv88e6xxx_serdes_power(chip, port, true); 2579 mv88e6xxx_reg_unlock(chip); 2580 2581 return err; 2582 } 2583 2584 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2585 { 2586 struct mv88e6xxx_chip *chip = ds->priv; 2587 2588 mv88e6xxx_reg_lock(chip); 2589 if (mv88e6xxx_serdes_power(chip, port, false)) 2590 dev_err(chip->dev, "failed to power off SERDES\n"); 2591 mv88e6xxx_reg_unlock(chip); 2592 } 2593 2594 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2595 unsigned int ageing_time) 2596 { 2597 struct mv88e6xxx_chip *chip = ds->priv; 2598 int err; 2599 2600 mv88e6xxx_reg_lock(chip); 2601 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2602 mv88e6xxx_reg_unlock(chip); 2603 2604 return err; 2605 } 2606 2607 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2608 { 2609 int err; 2610 2611 /* Initialize the statistics unit */ 2612 if (chip->info->ops->stats_set_histogram) { 2613 err = chip->info->ops->stats_set_histogram(chip); 2614 if (err) 2615 return err; 2616 } 2617 2618 return mv88e6xxx_g1_stats_clear(chip); 2619 } 2620 2621 /* Check if the errata has already been applied. */ 2622 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2623 { 2624 int port; 2625 int err; 2626 u16 val; 2627 2628 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2629 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2630 if (err) { 2631 dev_err(chip->dev, 2632 "Error reading hidden register: %d\n", err); 2633 return false; 2634 } 2635 if (val != 0x01c0) 2636 return false; 2637 } 2638 2639 return true; 2640 } 2641 2642 /* The 6390 copper ports have an errata which require poking magic 2643 * values into undocumented hidden registers and then performing a 2644 * software reset. 2645 */ 2646 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2647 { 2648 int port; 2649 int err; 2650 2651 if (mv88e6390_setup_errata_applied(chip)) 2652 return 0; 2653 2654 /* Set the ports into blocking mode */ 2655 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2656 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2657 if (err) 2658 return err; 2659 } 2660 2661 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2662 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2663 if (err) 2664 return err; 2665 } 2666 2667 return mv88e6xxx_software_reset(chip); 2668 } 2669 2670 enum mv88e6xxx_devlink_param_id { 2671 MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 2672 MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2673 }; 2674 2675 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id, 2676 struct devlink_param_gset_ctx *ctx) 2677 { 2678 struct mv88e6xxx_chip *chip = ds->priv; 2679 int err; 2680 2681 mv88e6xxx_reg_lock(chip); 2682 2683 switch (id) { 2684 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2685 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8); 2686 break; 2687 default: 2688 err = -EOPNOTSUPP; 2689 break; 2690 } 2691 2692 mv88e6xxx_reg_unlock(chip); 2693 2694 return err; 2695 } 2696 2697 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id, 2698 struct devlink_param_gset_ctx *ctx) 2699 { 2700 struct mv88e6xxx_chip *chip = ds->priv; 2701 int err; 2702 2703 mv88e6xxx_reg_lock(chip); 2704 2705 switch (id) { 2706 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2707 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8); 2708 break; 2709 default: 2710 err = -EOPNOTSUPP; 2711 break; 2712 } 2713 2714 mv88e6xxx_reg_unlock(chip); 2715 2716 return err; 2717 } 2718 2719 static const struct devlink_param mv88e6xxx_devlink_params[] = { 2720 DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2721 "ATU_hash", DEVLINK_PARAM_TYPE_U8, 2722 BIT(DEVLINK_PARAM_CMODE_RUNTIME)), 2723 }; 2724 2725 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds) 2726 { 2727 return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params, 2728 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2729 } 2730 2731 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds) 2732 { 2733 dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params, 2734 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2735 } 2736 2737 enum mv88e6xxx_devlink_resource_id { 2738 MV88E6XXX_RESOURCE_ID_ATU, 2739 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2740 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2741 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2742 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2743 }; 2744 2745 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip, 2746 u16 bin) 2747 { 2748 u16 occupancy = 0; 2749 int err; 2750 2751 mv88e6xxx_reg_lock(chip); 2752 2753 err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL, 2754 bin); 2755 if (err) { 2756 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); 2757 goto unlock; 2758 } 2759 2760 err = mv88e6xxx_g1_atu_get_next(chip, 0); 2761 if (err) { 2762 dev_err(chip->dev, "failed to perform ATU get next\n"); 2763 goto unlock; 2764 } 2765 2766 err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy); 2767 if (err) { 2768 dev_err(chip->dev, "failed to get ATU stats\n"); 2769 goto unlock; 2770 } 2771 2772 unlock: 2773 mv88e6xxx_reg_unlock(chip); 2774 2775 return occupancy; 2776 } 2777 2778 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv) 2779 { 2780 struct mv88e6xxx_chip *chip = priv; 2781 2782 return mv88e6xxx_devlink_atu_bin_get(chip, 2783 MV88E6XXX_G2_ATU_STATS_BIN_0); 2784 } 2785 2786 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv) 2787 { 2788 struct mv88e6xxx_chip *chip = priv; 2789 2790 return mv88e6xxx_devlink_atu_bin_get(chip, 2791 MV88E6XXX_G2_ATU_STATS_BIN_1); 2792 } 2793 2794 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv) 2795 { 2796 struct mv88e6xxx_chip *chip = priv; 2797 2798 return mv88e6xxx_devlink_atu_bin_get(chip, 2799 MV88E6XXX_G2_ATU_STATS_BIN_2); 2800 } 2801 2802 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv) 2803 { 2804 struct mv88e6xxx_chip *chip = priv; 2805 2806 return mv88e6xxx_devlink_atu_bin_get(chip, 2807 MV88E6XXX_G2_ATU_STATS_BIN_3); 2808 } 2809 2810 static u64 mv88e6xxx_devlink_atu_get(void *priv) 2811 { 2812 return mv88e6xxx_devlink_atu_bin_0_get(priv) + 2813 mv88e6xxx_devlink_atu_bin_1_get(priv) + 2814 mv88e6xxx_devlink_atu_bin_2_get(priv) + 2815 mv88e6xxx_devlink_atu_bin_3_get(priv); 2816 } 2817 2818 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds) 2819 { 2820 struct devlink_resource_size_params size_params; 2821 struct mv88e6xxx_chip *chip = ds->priv; 2822 int err; 2823 2824 devlink_resource_size_params_init(&size_params, 2825 mv88e6xxx_num_macs(chip), 2826 mv88e6xxx_num_macs(chip), 2827 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2828 2829 err = dsa_devlink_resource_register(ds, "ATU", 2830 mv88e6xxx_num_macs(chip), 2831 MV88E6XXX_RESOURCE_ID_ATU, 2832 DEVLINK_RESOURCE_ID_PARENT_TOP, 2833 &size_params); 2834 if (err) 2835 goto out; 2836 2837 devlink_resource_size_params_init(&size_params, 2838 mv88e6xxx_num_macs(chip) / 4, 2839 mv88e6xxx_num_macs(chip) / 4, 2840 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2841 2842 err = dsa_devlink_resource_register(ds, "ATU_bin_0", 2843 mv88e6xxx_num_macs(chip) / 4, 2844 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2845 MV88E6XXX_RESOURCE_ID_ATU, 2846 &size_params); 2847 if (err) 2848 goto out; 2849 2850 err = dsa_devlink_resource_register(ds, "ATU_bin_1", 2851 mv88e6xxx_num_macs(chip) / 4, 2852 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2853 MV88E6XXX_RESOURCE_ID_ATU, 2854 &size_params); 2855 if (err) 2856 goto out; 2857 2858 err = dsa_devlink_resource_register(ds, "ATU_bin_2", 2859 mv88e6xxx_num_macs(chip) / 4, 2860 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2861 MV88E6XXX_RESOURCE_ID_ATU, 2862 &size_params); 2863 if (err) 2864 goto out; 2865 2866 err = dsa_devlink_resource_register(ds, "ATU_bin_3", 2867 mv88e6xxx_num_macs(chip) / 4, 2868 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2869 MV88E6XXX_RESOURCE_ID_ATU, 2870 &size_params); 2871 if (err) 2872 goto out; 2873 2874 dsa_devlink_resource_occ_get_register(ds, 2875 MV88E6XXX_RESOURCE_ID_ATU, 2876 mv88e6xxx_devlink_atu_get, 2877 chip); 2878 2879 dsa_devlink_resource_occ_get_register(ds, 2880 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2881 mv88e6xxx_devlink_atu_bin_0_get, 2882 chip); 2883 2884 dsa_devlink_resource_occ_get_register(ds, 2885 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2886 mv88e6xxx_devlink_atu_bin_1_get, 2887 chip); 2888 2889 dsa_devlink_resource_occ_get_register(ds, 2890 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2891 mv88e6xxx_devlink_atu_bin_2_get, 2892 chip); 2893 2894 dsa_devlink_resource_occ_get_register(ds, 2895 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2896 mv88e6xxx_devlink_atu_bin_3_get, 2897 chip); 2898 2899 return 0; 2900 2901 out: 2902 dsa_devlink_resources_unregister(ds); 2903 return err; 2904 } 2905 2906 static void mv88e6xxx_teardown(struct dsa_switch *ds) 2907 { 2908 mv88e6xxx_teardown_devlink_params(ds); 2909 dsa_devlink_resources_unregister(ds); 2910 } 2911 2912 static int mv88e6xxx_setup(struct dsa_switch *ds) 2913 { 2914 struct mv88e6xxx_chip *chip = ds->priv; 2915 u8 cmode; 2916 int err; 2917 int i; 2918 2919 chip->ds = ds; 2920 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2921 2922 mv88e6xxx_reg_lock(chip); 2923 2924 if (chip->info->ops->setup_errata) { 2925 err = chip->info->ops->setup_errata(chip); 2926 if (err) 2927 goto unlock; 2928 } 2929 2930 /* Cache the cmode of each port. */ 2931 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2932 if (chip->info->ops->port_get_cmode) { 2933 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2934 if (err) 2935 goto unlock; 2936 2937 chip->ports[i].cmode = cmode; 2938 } 2939 } 2940 2941 /* Setup Switch Port Registers */ 2942 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2943 if (dsa_is_unused_port(ds, i)) 2944 continue; 2945 2946 /* Prevent the use of an invalid port. */ 2947 if (mv88e6xxx_is_invalid_port(chip, i)) { 2948 dev_err(chip->dev, "port %d is invalid\n", i); 2949 err = -EINVAL; 2950 goto unlock; 2951 } 2952 2953 err = mv88e6xxx_setup_port(chip, i); 2954 if (err) 2955 goto unlock; 2956 } 2957 2958 err = mv88e6xxx_irl_setup(chip); 2959 if (err) 2960 goto unlock; 2961 2962 err = mv88e6xxx_mac_setup(chip); 2963 if (err) 2964 goto unlock; 2965 2966 err = mv88e6xxx_phy_setup(chip); 2967 if (err) 2968 goto unlock; 2969 2970 err = mv88e6xxx_vtu_setup(chip); 2971 if (err) 2972 goto unlock; 2973 2974 err = mv88e6xxx_pvt_setup(chip); 2975 if (err) 2976 goto unlock; 2977 2978 err = mv88e6xxx_atu_setup(chip); 2979 if (err) 2980 goto unlock; 2981 2982 err = mv88e6xxx_broadcast_setup(chip, 0); 2983 if (err) 2984 goto unlock; 2985 2986 err = mv88e6xxx_pot_setup(chip); 2987 if (err) 2988 goto unlock; 2989 2990 err = mv88e6xxx_rmu_setup(chip); 2991 if (err) 2992 goto unlock; 2993 2994 err = mv88e6xxx_rsvd2cpu_setup(chip); 2995 if (err) 2996 goto unlock; 2997 2998 err = mv88e6xxx_trunk_setup(chip); 2999 if (err) 3000 goto unlock; 3001 3002 err = mv88e6xxx_devmap_setup(chip); 3003 if (err) 3004 goto unlock; 3005 3006 err = mv88e6xxx_pri_setup(chip); 3007 if (err) 3008 goto unlock; 3009 3010 /* Setup PTP Hardware Clock and timestamping */ 3011 if (chip->info->ptp_support) { 3012 err = mv88e6xxx_ptp_setup(chip); 3013 if (err) 3014 goto unlock; 3015 3016 err = mv88e6xxx_hwtstamp_setup(chip); 3017 if (err) 3018 goto unlock; 3019 } 3020 3021 err = mv88e6xxx_stats_setup(chip); 3022 if (err) 3023 goto unlock; 3024 3025 unlock: 3026 mv88e6xxx_reg_unlock(chip); 3027 3028 if (err) 3029 return err; 3030 3031 /* Have to be called without holding the register lock, since 3032 * they take the devlink lock, and we later take the locks in 3033 * the reverse order when getting/setting parameters or 3034 * resource occupancy. 3035 */ 3036 err = mv88e6xxx_setup_devlink_resources(ds); 3037 if (err) 3038 return err; 3039 3040 err = mv88e6xxx_setup_devlink_params(ds); 3041 if (err) 3042 dsa_devlink_resources_unregister(ds); 3043 3044 return err; 3045 } 3046 3047 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3048 { 3049 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3050 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3051 u16 val; 3052 int err; 3053 3054 if (!chip->info->ops->phy_read) 3055 return -EOPNOTSUPP; 3056 3057 mv88e6xxx_reg_lock(chip); 3058 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3059 mv88e6xxx_reg_unlock(chip); 3060 3061 if (reg == MII_PHYSID2) { 3062 /* Some internal PHYs don't have a model number. */ 3063 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3064 /* Then there is the 6165 family. It gets is 3065 * PHYs correct. But it can also have two 3066 * SERDES interfaces in the PHY address 3067 * space. And these don't have a model 3068 * number. But they are not PHYs, so we don't 3069 * want to give them something a PHY driver 3070 * will recognise. 3071 * 3072 * Use the mv88e6390 family model number 3073 * instead, for anything which really could be 3074 * a PHY, 3075 */ 3076 if (!(val & 0x3f0)) 3077 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3078 } 3079 3080 return err ? err : val; 3081 } 3082 3083 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3084 { 3085 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3086 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3087 int err; 3088 3089 if (!chip->info->ops->phy_write) 3090 return -EOPNOTSUPP; 3091 3092 mv88e6xxx_reg_lock(chip); 3093 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3094 mv88e6xxx_reg_unlock(chip); 3095 3096 return err; 3097 } 3098 3099 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3100 struct device_node *np, 3101 bool external) 3102 { 3103 static int index; 3104 struct mv88e6xxx_mdio_bus *mdio_bus; 3105 struct mii_bus *bus; 3106 int err; 3107 3108 if (external) { 3109 mv88e6xxx_reg_lock(chip); 3110 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3111 mv88e6xxx_reg_unlock(chip); 3112 3113 if (err) 3114 return err; 3115 } 3116 3117 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3118 if (!bus) 3119 return -ENOMEM; 3120 3121 mdio_bus = bus->priv; 3122 mdio_bus->bus = bus; 3123 mdio_bus->chip = chip; 3124 INIT_LIST_HEAD(&mdio_bus->list); 3125 mdio_bus->external = external; 3126 3127 if (np) { 3128 bus->name = np->full_name; 3129 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3130 } else { 3131 bus->name = "mv88e6xxx SMI"; 3132 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3133 } 3134 3135 bus->read = mv88e6xxx_mdio_read; 3136 bus->write = mv88e6xxx_mdio_write; 3137 bus->parent = chip->dev; 3138 3139 if (!external) { 3140 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3141 if (err) 3142 return err; 3143 } 3144 3145 err = of_mdiobus_register(bus, np); 3146 if (err) { 3147 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3148 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3149 return err; 3150 } 3151 3152 if (external) 3153 list_add_tail(&mdio_bus->list, &chip->mdios); 3154 else 3155 list_add(&mdio_bus->list, &chip->mdios); 3156 3157 return 0; 3158 } 3159 3160 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 3161 { .compatible = "marvell,mv88e6xxx-mdio-external", 3162 .data = (void *)true }, 3163 { }, 3164 }; 3165 3166 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3167 3168 { 3169 struct mv88e6xxx_mdio_bus *mdio_bus; 3170 struct mii_bus *bus; 3171 3172 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3173 bus = mdio_bus->bus; 3174 3175 if (!mdio_bus->external) 3176 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3177 3178 mdiobus_unregister(bus); 3179 } 3180 } 3181 3182 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3183 struct device_node *np) 3184 { 3185 const struct of_device_id *match; 3186 struct device_node *child; 3187 int err; 3188 3189 /* Always register one mdio bus for the internal/default mdio 3190 * bus. This maybe represented in the device tree, but is 3191 * optional. 3192 */ 3193 child = of_get_child_by_name(np, "mdio"); 3194 err = mv88e6xxx_mdio_register(chip, child, false); 3195 if (err) 3196 return err; 3197 3198 /* Walk the device tree, and see if there are any other nodes 3199 * which say they are compatible with the external mdio 3200 * bus. 3201 */ 3202 for_each_available_child_of_node(np, child) { 3203 match = of_match_node(mv88e6xxx_mdio_external_match, child); 3204 if (match) { 3205 err = mv88e6xxx_mdio_register(chip, child, true); 3206 if (err) { 3207 mv88e6xxx_mdios_unregister(chip); 3208 of_node_put(child); 3209 return err; 3210 } 3211 } 3212 } 3213 3214 return 0; 3215 } 3216 3217 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3218 { 3219 struct mv88e6xxx_chip *chip = ds->priv; 3220 3221 return chip->eeprom_len; 3222 } 3223 3224 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3225 struct ethtool_eeprom *eeprom, u8 *data) 3226 { 3227 struct mv88e6xxx_chip *chip = ds->priv; 3228 int err; 3229 3230 if (!chip->info->ops->get_eeprom) 3231 return -EOPNOTSUPP; 3232 3233 mv88e6xxx_reg_lock(chip); 3234 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3235 mv88e6xxx_reg_unlock(chip); 3236 3237 if (err) 3238 return err; 3239 3240 eeprom->magic = 0xc3ec4951; 3241 3242 return 0; 3243 } 3244 3245 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3246 struct ethtool_eeprom *eeprom, u8 *data) 3247 { 3248 struct mv88e6xxx_chip *chip = ds->priv; 3249 int err; 3250 3251 if (!chip->info->ops->set_eeprom) 3252 return -EOPNOTSUPP; 3253 3254 if (eeprom->magic != 0xc3ec4951) 3255 return -EINVAL; 3256 3257 mv88e6xxx_reg_lock(chip); 3258 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3259 mv88e6xxx_reg_unlock(chip); 3260 3261 return err; 3262 } 3263 3264 static const struct mv88e6xxx_ops mv88e6085_ops = { 3265 /* MV88E6XXX_FAMILY_6097 */ 3266 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3267 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3268 .irl_init_all = mv88e6352_g2_irl_init_all, 3269 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3270 .phy_read = mv88e6185_phy_ppu_read, 3271 .phy_write = mv88e6185_phy_ppu_write, 3272 .port_set_link = mv88e6xxx_port_set_link, 3273 .port_set_duplex = mv88e6xxx_port_set_duplex, 3274 .port_set_speed = mv88e6185_port_set_speed, 3275 .port_tag_remap = mv88e6095_port_tag_remap, 3276 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3277 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3278 .port_set_ether_type = mv88e6351_port_set_ether_type, 3279 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3280 .port_pause_limit = mv88e6097_port_pause_limit, 3281 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3282 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3283 .port_link_state = mv88e6352_port_link_state, 3284 .port_get_cmode = mv88e6185_port_get_cmode, 3285 .port_setup_message_port = mv88e6xxx_setup_message_port, 3286 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3287 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3288 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3289 .stats_get_strings = mv88e6095_stats_get_strings, 3290 .stats_get_stats = mv88e6095_stats_get_stats, 3291 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3292 .set_egress_port = mv88e6095_g1_set_egress_port, 3293 .watchdog_ops = &mv88e6097_watchdog_ops, 3294 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3295 .pot_clear = mv88e6xxx_g2_pot_clear, 3296 .ppu_enable = mv88e6185_g1_ppu_enable, 3297 .ppu_disable = mv88e6185_g1_ppu_disable, 3298 .reset = mv88e6185_g1_reset, 3299 .rmu_disable = mv88e6085_g1_rmu_disable, 3300 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3301 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3302 .phylink_validate = mv88e6185_phylink_validate, 3303 }; 3304 3305 static const struct mv88e6xxx_ops mv88e6095_ops = { 3306 /* MV88E6XXX_FAMILY_6095 */ 3307 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3308 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3309 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3310 .phy_read = mv88e6185_phy_ppu_read, 3311 .phy_write = mv88e6185_phy_ppu_write, 3312 .port_set_link = mv88e6xxx_port_set_link, 3313 .port_set_duplex = mv88e6xxx_port_set_duplex, 3314 .port_set_speed = mv88e6185_port_set_speed, 3315 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3316 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3317 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3318 .port_link_state = mv88e6185_port_link_state, 3319 .port_get_cmode = mv88e6185_port_get_cmode, 3320 .port_setup_message_port = mv88e6xxx_setup_message_port, 3321 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3322 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3323 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3324 .stats_get_strings = mv88e6095_stats_get_strings, 3325 .stats_get_stats = mv88e6095_stats_get_stats, 3326 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3327 .ppu_enable = mv88e6185_g1_ppu_enable, 3328 .ppu_disable = mv88e6185_g1_ppu_disable, 3329 .reset = mv88e6185_g1_reset, 3330 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3331 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3332 .phylink_validate = mv88e6185_phylink_validate, 3333 }; 3334 3335 static const struct mv88e6xxx_ops mv88e6097_ops = { 3336 /* MV88E6XXX_FAMILY_6097 */ 3337 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3338 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3339 .irl_init_all = mv88e6352_g2_irl_init_all, 3340 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3341 .phy_read = mv88e6xxx_g2_smi_phy_read, 3342 .phy_write = mv88e6xxx_g2_smi_phy_write, 3343 .port_set_link = mv88e6xxx_port_set_link, 3344 .port_set_duplex = mv88e6xxx_port_set_duplex, 3345 .port_set_speed = mv88e6185_port_set_speed, 3346 .port_tag_remap = mv88e6095_port_tag_remap, 3347 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3348 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3349 .port_set_ether_type = mv88e6351_port_set_ether_type, 3350 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3351 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3352 .port_pause_limit = mv88e6097_port_pause_limit, 3353 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3354 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3355 .port_link_state = mv88e6352_port_link_state, 3356 .port_get_cmode = mv88e6185_port_get_cmode, 3357 .port_setup_message_port = mv88e6xxx_setup_message_port, 3358 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3359 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3360 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3361 .stats_get_strings = mv88e6095_stats_get_strings, 3362 .stats_get_stats = mv88e6095_stats_get_stats, 3363 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3364 .set_egress_port = mv88e6095_g1_set_egress_port, 3365 .watchdog_ops = &mv88e6097_watchdog_ops, 3366 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3367 .pot_clear = mv88e6xxx_g2_pot_clear, 3368 .reset = mv88e6352_g1_reset, 3369 .rmu_disable = mv88e6085_g1_rmu_disable, 3370 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3371 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3372 .phylink_validate = mv88e6185_phylink_validate, 3373 }; 3374 3375 static const struct mv88e6xxx_ops mv88e6123_ops = { 3376 /* MV88E6XXX_FAMILY_6165 */ 3377 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3378 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3379 .irl_init_all = mv88e6352_g2_irl_init_all, 3380 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3381 .phy_read = mv88e6xxx_g2_smi_phy_read, 3382 .phy_write = mv88e6xxx_g2_smi_phy_write, 3383 .port_set_link = mv88e6xxx_port_set_link, 3384 .port_set_duplex = mv88e6xxx_port_set_duplex, 3385 .port_set_speed = mv88e6185_port_set_speed, 3386 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3387 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3388 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3389 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3390 .port_link_state = mv88e6352_port_link_state, 3391 .port_get_cmode = mv88e6185_port_get_cmode, 3392 .port_setup_message_port = mv88e6xxx_setup_message_port, 3393 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3394 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3395 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3396 .stats_get_strings = mv88e6095_stats_get_strings, 3397 .stats_get_stats = mv88e6095_stats_get_stats, 3398 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3399 .set_egress_port = mv88e6095_g1_set_egress_port, 3400 .watchdog_ops = &mv88e6097_watchdog_ops, 3401 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3402 .pot_clear = mv88e6xxx_g2_pot_clear, 3403 .reset = mv88e6352_g1_reset, 3404 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3405 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3406 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3407 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3408 .phylink_validate = mv88e6185_phylink_validate, 3409 }; 3410 3411 static const struct mv88e6xxx_ops mv88e6131_ops = { 3412 /* MV88E6XXX_FAMILY_6185 */ 3413 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3414 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3415 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3416 .phy_read = mv88e6185_phy_ppu_read, 3417 .phy_write = mv88e6185_phy_ppu_write, 3418 .port_set_link = mv88e6xxx_port_set_link, 3419 .port_set_duplex = mv88e6xxx_port_set_duplex, 3420 .port_set_speed = mv88e6185_port_set_speed, 3421 .port_tag_remap = mv88e6095_port_tag_remap, 3422 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3423 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3424 .port_set_ether_type = mv88e6351_port_set_ether_type, 3425 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3426 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3427 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3428 .port_pause_limit = mv88e6097_port_pause_limit, 3429 .port_set_pause = mv88e6185_port_set_pause, 3430 .port_link_state = mv88e6352_port_link_state, 3431 .port_get_cmode = mv88e6185_port_get_cmode, 3432 .port_setup_message_port = mv88e6xxx_setup_message_port, 3433 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3434 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3435 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3436 .stats_get_strings = mv88e6095_stats_get_strings, 3437 .stats_get_stats = mv88e6095_stats_get_stats, 3438 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3439 .set_egress_port = mv88e6095_g1_set_egress_port, 3440 .watchdog_ops = &mv88e6097_watchdog_ops, 3441 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3442 .ppu_enable = mv88e6185_g1_ppu_enable, 3443 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3444 .ppu_disable = mv88e6185_g1_ppu_disable, 3445 .reset = mv88e6185_g1_reset, 3446 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3447 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3448 .phylink_validate = mv88e6185_phylink_validate, 3449 }; 3450 3451 static const struct mv88e6xxx_ops mv88e6141_ops = { 3452 /* MV88E6XXX_FAMILY_6341 */ 3453 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3454 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3455 .irl_init_all = mv88e6352_g2_irl_init_all, 3456 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3457 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3458 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3459 .phy_read = mv88e6xxx_g2_smi_phy_read, 3460 .phy_write = mv88e6xxx_g2_smi_phy_write, 3461 .port_set_link = mv88e6xxx_port_set_link, 3462 .port_set_duplex = mv88e6xxx_port_set_duplex, 3463 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3464 .port_set_speed = mv88e6341_port_set_speed, 3465 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3466 .port_tag_remap = mv88e6095_port_tag_remap, 3467 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3468 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3469 .port_set_ether_type = mv88e6351_port_set_ether_type, 3470 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3471 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3472 .port_pause_limit = mv88e6097_port_pause_limit, 3473 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3474 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3475 .port_link_state = mv88e6352_port_link_state, 3476 .port_get_cmode = mv88e6352_port_get_cmode, 3477 .port_set_cmode = mv88e6341_port_set_cmode, 3478 .port_setup_message_port = mv88e6xxx_setup_message_port, 3479 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3480 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3481 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3482 .stats_get_strings = mv88e6320_stats_get_strings, 3483 .stats_get_stats = mv88e6390_stats_get_stats, 3484 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3485 .set_egress_port = mv88e6390_g1_set_egress_port, 3486 .watchdog_ops = &mv88e6390_watchdog_ops, 3487 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3488 .pot_clear = mv88e6xxx_g2_pot_clear, 3489 .reset = mv88e6352_g1_reset, 3490 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3491 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3492 .serdes_power = mv88e6390_serdes_power, 3493 .serdes_get_lane = mv88e6341_serdes_get_lane, 3494 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3495 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3496 .serdes_irq_status = mv88e6390_serdes_irq_status, 3497 .gpio_ops = &mv88e6352_gpio_ops, 3498 .phylink_validate = mv88e6341_phylink_validate, 3499 }; 3500 3501 static const struct mv88e6xxx_ops mv88e6161_ops = { 3502 /* MV88E6XXX_FAMILY_6165 */ 3503 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3504 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3505 .irl_init_all = mv88e6352_g2_irl_init_all, 3506 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3507 .phy_read = mv88e6xxx_g2_smi_phy_read, 3508 .phy_write = mv88e6xxx_g2_smi_phy_write, 3509 .port_set_link = mv88e6xxx_port_set_link, 3510 .port_set_duplex = mv88e6xxx_port_set_duplex, 3511 .port_set_speed = mv88e6185_port_set_speed, 3512 .port_tag_remap = mv88e6095_port_tag_remap, 3513 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3514 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3515 .port_set_ether_type = mv88e6351_port_set_ether_type, 3516 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3517 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3518 .port_pause_limit = mv88e6097_port_pause_limit, 3519 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3520 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3521 .port_link_state = mv88e6352_port_link_state, 3522 .port_get_cmode = mv88e6185_port_get_cmode, 3523 .port_setup_message_port = mv88e6xxx_setup_message_port, 3524 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3525 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3526 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3527 .stats_get_strings = mv88e6095_stats_get_strings, 3528 .stats_get_stats = mv88e6095_stats_get_stats, 3529 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3530 .set_egress_port = mv88e6095_g1_set_egress_port, 3531 .watchdog_ops = &mv88e6097_watchdog_ops, 3532 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3533 .pot_clear = mv88e6xxx_g2_pot_clear, 3534 .reset = mv88e6352_g1_reset, 3535 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3536 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3537 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3538 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3539 .avb_ops = &mv88e6165_avb_ops, 3540 .ptp_ops = &mv88e6165_ptp_ops, 3541 .phylink_validate = mv88e6185_phylink_validate, 3542 }; 3543 3544 static const struct mv88e6xxx_ops mv88e6165_ops = { 3545 /* MV88E6XXX_FAMILY_6165 */ 3546 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3547 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3548 .irl_init_all = mv88e6352_g2_irl_init_all, 3549 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3550 .phy_read = mv88e6165_phy_read, 3551 .phy_write = mv88e6165_phy_write, 3552 .port_set_link = mv88e6xxx_port_set_link, 3553 .port_set_duplex = mv88e6xxx_port_set_duplex, 3554 .port_set_speed = mv88e6185_port_set_speed, 3555 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3556 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3557 .port_link_state = mv88e6352_port_link_state, 3558 .port_get_cmode = mv88e6185_port_get_cmode, 3559 .port_setup_message_port = mv88e6xxx_setup_message_port, 3560 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3561 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3562 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3563 .stats_get_strings = mv88e6095_stats_get_strings, 3564 .stats_get_stats = mv88e6095_stats_get_stats, 3565 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3566 .set_egress_port = mv88e6095_g1_set_egress_port, 3567 .watchdog_ops = &mv88e6097_watchdog_ops, 3568 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3569 .pot_clear = mv88e6xxx_g2_pot_clear, 3570 .reset = mv88e6352_g1_reset, 3571 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3572 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3573 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3574 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3575 .avb_ops = &mv88e6165_avb_ops, 3576 .ptp_ops = &mv88e6165_ptp_ops, 3577 .phylink_validate = mv88e6185_phylink_validate, 3578 }; 3579 3580 static const struct mv88e6xxx_ops mv88e6171_ops = { 3581 /* MV88E6XXX_FAMILY_6351 */ 3582 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3583 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3584 .irl_init_all = mv88e6352_g2_irl_init_all, 3585 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3586 .phy_read = mv88e6xxx_g2_smi_phy_read, 3587 .phy_write = mv88e6xxx_g2_smi_phy_write, 3588 .port_set_link = mv88e6xxx_port_set_link, 3589 .port_set_duplex = mv88e6xxx_port_set_duplex, 3590 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3591 .port_set_speed = mv88e6185_port_set_speed, 3592 .port_tag_remap = mv88e6095_port_tag_remap, 3593 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3594 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3595 .port_set_ether_type = mv88e6351_port_set_ether_type, 3596 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3598 .port_pause_limit = mv88e6097_port_pause_limit, 3599 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3600 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3601 .port_link_state = mv88e6352_port_link_state, 3602 .port_get_cmode = mv88e6352_port_get_cmode, 3603 .port_setup_message_port = mv88e6xxx_setup_message_port, 3604 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3605 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3606 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3607 .stats_get_strings = mv88e6095_stats_get_strings, 3608 .stats_get_stats = mv88e6095_stats_get_stats, 3609 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3610 .set_egress_port = mv88e6095_g1_set_egress_port, 3611 .watchdog_ops = &mv88e6097_watchdog_ops, 3612 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3613 .pot_clear = mv88e6xxx_g2_pot_clear, 3614 .reset = mv88e6352_g1_reset, 3615 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3616 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3617 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3618 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3619 .phylink_validate = mv88e6185_phylink_validate, 3620 }; 3621 3622 static const struct mv88e6xxx_ops mv88e6172_ops = { 3623 /* MV88E6XXX_FAMILY_6352 */ 3624 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3625 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3626 .irl_init_all = mv88e6352_g2_irl_init_all, 3627 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3628 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3629 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3630 .phy_read = mv88e6xxx_g2_smi_phy_read, 3631 .phy_write = mv88e6xxx_g2_smi_phy_write, 3632 .port_set_link = mv88e6xxx_port_set_link, 3633 .port_set_duplex = mv88e6xxx_port_set_duplex, 3634 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3635 .port_set_speed = mv88e6352_port_set_speed, 3636 .port_tag_remap = mv88e6095_port_tag_remap, 3637 .port_set_policy = mv88e6352_port_set_policy, 3638 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3639 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3640 .port_set_ether_type = mv88e6351_port_set_ether_type, 3641 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3642 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3643 .port_pause_limit = mv88e6097_port_pause_limit, 3644 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3645 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3646 .port_link_state = mv88e6352_port_link_state, 3647 .port_get_cmode = mv88e6352_port_get_cmode, 3648 .port_setup_message_port = mv88e6xxx_setup_message_port, 3649 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3650 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3651 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3652 .stats_get_strings = mv88e6095_stats_get_strings, 3653 .stats_get_stats = mv88e6095_stats_get_stats, 3654 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3655 .set_egress_port = mv88e6095_g1_set_egress_port, 3656 .watchdog_ops = &mv88e6097_watchdog_ops, 3657 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3658 .pot_clear = mv88e6xxx_g2_pot_clear, 3659 .reset = mv88e6352_g1_reset, 3660 .rmu_disable = mv88e6352_g1_rmu_disable, 3661 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3662 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3663 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3664 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3665 .serdes_get_lane = mv88e6352_serdes_get_lane, 3666 .serdes_power = mv88e6352_serdes_power, 3667 .gpio_ops = &mv88e6352_gpio_ops, 3668 .phylink_validate = mv88e6352_phylink_validate, 3669 }; 3670 3671 static const struct mv88e6xxx_ops mv88e6175_ops = { 3672 /* MV88E6XXX_FAMILY_6351 */ 3673 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3674 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3675 .irl_init_all = mv88e6352_g2_irl_init_all, 3676 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3677 .phy_read = mv88e6xxx_g2_smi_phy_read, 3678 .phy_write = mv88e6xxx_g2_smi_phy_write, 3679 .port_set_link = mv88e6xxx_port_set_link, 3680 .port_set_duplex = mv88e6xxx_port_set_duplex, 3681 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3682 .port_set_speed = mv88e6185_port_set_speed, 3683 .port_tag_remap = mv88e6095_port_tag_remap, 3684 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3685 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3686 .port_set_ether_type = mv88e6351_port_set_ether_type, 3687 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3688 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3689 .port_pause_limit = mv88e6097_port_pause_limit, 3690 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3691 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3692 .port_link_state = mv88e6352_port_link_state, 3693 .port_get_cmode = mv88e6352_port_get_cmode, 3694 .port_setup_message_port = mv88e6xxx_setup_message_port, 3695 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3696 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3697 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3698 .stats_get_strings = mv88e6095_stats_get_strings, 3699 .stats_get_stats = mv88e6095_stats_get_stats, 3700 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3701 .set_egress_port = mv88e6095_g1_set_egress_port, 3702 .watchdog_ops = &mv88e6097_watchdog_ops, 3703 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3704 .pot_clear = mv88e6xxx_g2_pot_clear, 3705 .reset = mv88e6352_g1_reset, 3706 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3707 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3708 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3709 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3710 .phylink_validate = mv88e6185_phylink_validate, 3711 }; 3712 3713 static const struct mv88e6xxx_ops mv88e6176_ops = { 3714 /* MV88E6XXX_FAMILY_6352 */ 3715 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3716 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3717 .irl_init_all = mv88e6352_g2_irl_init_all, 3718 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3719 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3720 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3721 .phy_read = mv88e6xxx_g2_smi_phy_read, 3722 .phy_write = mv88e6xxx_g2_smi_phy_write, 3723 .port_set_link = mv88e6xxx_port_set_link, 3724 .port_set_duplex = mv88e6xxx_port_set_duplex, 3725 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3726 .port_set_speed = mv88e6352_port_set_speed, 3727 .port_tag_remap = mv88e6095_port_tag_remap, 3728 .port_set_policy = mv88e6352_port_set_policy, 3729 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3730 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3731 .port_set_ether_type = mv88e6351_port_set_ether_type, 3732 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3733 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3734 .port_pause_limit = mv88e6097_port_pause_limit, 3735 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3736 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3737 .port_link_state = mv88e6352_port_link_state, 3738 .port_get_cmode = mv88e6352_port_get_cmode, 3739 .port_setup_message_port = mv88e6xxx_setup_message_port, 3740 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3741 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3742 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3743 .stats_get_strings = mv88e6095_stats_get_strings, 3744 .stats_get_stats = mv88e6095_stats_get_stats, 3745 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3746 .set_egress_port = mv88e6095_g1_set_egress_port, 3747 .watchdog_ops = &mv88e6097_watchdog_ops, 3748 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3749 .pot_clear = mv88e6xxx_g2_pot_clear, 3750 .reset = mv88e6352_g1_reset, 3751 .rmu_disable = mv88e6352_g1_rmu_disable, 3752 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3753 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3754 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3755 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3756 .serdes_get_lane = mv88e6352_serdes_get_lane, 3757 .serdes_power = mv88e6352_serdes_power, 3758 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3759 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3760 .serdes_irq_status = mv88e6352_serdes_irq_status, 3761 .gpio_ops = &mv88e6352_gpio_ops, 3762 .phylink_validate = mv88e6352_phylink_validate, 3763 }; 3764 3765 static const struct mv88e6xxx_ops mv88e6185_ops = { 3766 /* MV88E6XXX_FAMILY_6185 */ 3767 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3768 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3769 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3770 .phy_read = mv88e6185_phy_ppu_read, 3771 .phy_write = mv88e6185_phy_ppu_write, 3772 .port_set_link = mv88e6xxx_port_set_link, 3773 .port_set_duplex = mv88e6xxx_port_set_duplex, 3774 .port_set_speed = mv88e6185_port_set_speed, 3775 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3776 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3777 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3778 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3779 .port_set_pause = mv88e6185_port_set_pause, 3780 .port_link_state = mv88e6185_port_link_state, 3781 .port_get_cmode = mv88e6185_port_get_cmode, 3782 .port_setup_message_port = mv88e6xxx_setup_message_port, 3783 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3784 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3785 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3786 .stats_get_strings = mv88e6095_stats_get_strings, 3787 .stats_get_stats = mv88e6095_stats_get_stats, 3788 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3789 .set_egress_port = mv88e6095_g1_set_egress_port, 3790 .watchdog_ops = &mv88e6097_watchdog_ops, 3791 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3792 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3793 .ppu_enable = mv88e6185_g1_ppu_enable, 3794 .ppu_disable = mv88e6185_g1_ppu_disable, 3795 .reset = mv88e6185_g1_reset, 3796 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3797 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3798 .phylink_validate = mv88e6185_phylink_validate, 3799 }; 3800 3801 static const struct mv88e6xxx_ops mv88e6190_ops = { 3802 /* MV88E6XXX_FAMILY_6390 */ 3803 .setup_errata = mv88e6390_setup_errata, 3804 .irl_init_all = mv88e6390_g2_irl_init_all, 3805 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3806 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3807 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3808 .phy_read = mv88e6xxx_g2_smi_phy_read, 3809 .phy_write = mv88e6xxx_g2_smi_phy_write, 3810 .port_set_link = mv88e6xxx_port_set_link, 3811 .port_set_duplex = mv88e6xxx_port_set_duplex, 3812 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3813 .port_set_speed = mv88e6390_port_set_speed, 3814 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3815 .port_tag_remap = mv88e6390_port_tag_remap, 3816 .port_set_policy = mv88e6352_port_set_policy, 3817 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3818 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3819 .port_set_ether_type = mv88e6351_port_set_ether_type, 3820 .port_pause_limit = mv88e6390_port_pause_limit, 3821 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3822 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3823 .port_link_state = mv88e6352_port_link_state, 3824 .port_get_cmode = mv88e6352_port_get_cmode, 3825 .port_set_cmode = mv88e6390_port_set_cmode, 3826 .port_setup_message_port = mv88e6xxx_setup_message_port, 3827 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3828 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3829 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3830 .stats_get_strings = mv88e6320_stats_get_strings, 3831 .stats_get_stats = mv88e6390_stats_get_stats, 3832 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3833 .set_egress_port = mv88e6390_g1_set_egress_port, 3834 .watchdog_ops = &mv88e6390_watchdog_ops, 3835 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3836 .pot_clear = mv88e6xxx_g2_pot_clear, 3837 .reset = mv88e6352_g1_reset, 3838 .rmu_disable = mv88e6390_g1_rmu_disable, 3839 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3840 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3841 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3842 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3843 .serdes_power = mv88e6390_serdes_power, 3844 .serdes_get_lane = mv88e6390_serdes_get_lane, 3845 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3846 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3847 .serdes_irq_status = mv88e6390_serdes_irq_status, 3848 .serdes_get_strings = mv88e6390_serdes_get_strings, 3849 .serdes_get_stats = mv88e6390_serdes_get_stats, 3850 .phylink_validate = mv88e6390_phylink_validate, 3851 .gpio_ops = &mv88e6352_gpio_ops, 3852 .phylink_validate = mv88e6390_phylink_validate, 3853 }; 3854 3855 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3856 /* MV88E6XXX_FAMILY_6390 */ 3857 .setup_errata = mv88e6390_setup_errata, 3858 .irl_init_all = mv88e6390_g2_irl_init_all, 3859 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3860 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3861 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3862 .phy_read = mv88e6xxx_g2_smi_phy_read, 3863 .phy_write = mv88e6xxx_g2_smi_phy_write, 3864 .port_set_link = mv88e6xxx_port_set_link, 3865 .port_set_duplex = mv88e6xxx_port_set_duplex, 3866 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3867 .port_set_speed = mv88e6390x_port_set_speed, 3868 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3869 .port_tag_remap = mv88e6390_port_tag_remap, 3870 .port_set_policy = mv88e6352_port_set_policy, 3871 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3872 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3873 .port_set_ether_type = mv88e6351_port_set_ether_type, 3874 .port_pause_limit = mv88e6390_port_pause_limit, 3875 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3876 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3877 .port_link_state = mv88e6352_port_link_state, 3878 .port_get_cmode = mv88e6352_port_get_cmode, 3879 .port_set_cmode = mv88e6390x_port_set_cmode, 3880 .port_setup_message_port = mv88e6xxx_setup_message_port, 3881 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3882 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3883 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3884 .stats_get_strings = mv88e6320_stats_get_strings, 3885 .stats_get_stats = mv88e6390_stats_get_stats, 3886 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3887 .set_egress_port = mv88e6390_g1_set_egress_port, 3888 .watchdog_ops = &mv88e6390_watchdog_ops, 3889 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3890 .pot_clear = mv88e6xxx_g2_pot_clear, 3891 .reset = mv88e6352_g1_reset, 3892 .rmu_disable = mv88e6390_g1_rmu_disable, 3893 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3894 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3895 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3896 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3897 .serdes_power = mv88e6390_serdes_power, 3898 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3899 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3900 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3901 .serdes_irq_status = mv88e6390_serdes_irq_status, 3902 .serdes_get_strings = mv88e6390_serdes_get_strings, 3903 .serdes_get_stats = mv88e6390_serdes_get_stats, 3904 .phylink_validate = mv88e6390_phylink_validate, 3905 .gpio_ops = &mv88e6352_gpio_ops, 3906 .phylink_validate = mv88e6390x_phylink_validate, 3907 }; 3908 3909 static const struct mv88e6xxx_ops mv88e6191_ops = { 3910 /* MV88E6XXX_FAMILY_6390 */ 3911 .setup_errata = mv88e6390_setup_errata, 3912 .irl_init_all = mv88e6390_g2_irl_init_all, 3913 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3914 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3915 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3916 .phy_read = mv88e6xxx_g2_smi_phy_read, 3917 .phy_write = mv88e6xxx_g2_smi_phy_write, 3918 .port_set_link = mv88e6xxx_port_set_link, 3919 .port_set_duplex = mv88e6xxx_port_set_duplex, 3920 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3921 .port_set_speed = mv88e6390_port_set_speed, 3922 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3923 .port_tag_remap = mv88e6390_port_tag_remap, 3924 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3925 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3926 .port_set_ether_type = mv88e6351_port_set_ether_type, 3927 .port_pause_limit = mv88e6390_port_pause_limit, 3928 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3929 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3930 .port_link_state = mv88e6352_port_link_state, 3931 .port_get_cmode = mv88e6352_port_get_cmode, 3932 .port_set_cmode = mv88e6390_port_set_cmode, 3933 .port_setup_message_port = mv88e6xxx_setup_message_port, 3934 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3935 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3936 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3937 .stats_get_strings = mv88e6320_stats_get_strings, 3938 .stats_get_stats = mv88e6390_stats_get_stats, 3939 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3940 .set_egress_port = mv88e6390_g1_set_egress_port, 3941 .watchdog_ops = &mv88e6390_watchdog_ops, 3942 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3943 .pot_clear = mv88e6xxx_g2_pot_clear, 3944 .reset = mv88e6352_g1_reset, 3945 .rmu_disable = mv88e6390_g1_rmu_disable, 3946 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3947 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3948 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3949 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3950 .serdes_power = mv88e6390_serdes_power, 3951 .serdes_get_lane = mv88e6390_serdes_get_lane, 3952 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3953 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3954 .serdes_irq_status = mv88e6390_serdes_irq_status, 3955 .serdes_get_strings = mv88e6390_serdes_get_strings, 3956 .serdes_get_stats = mv88e6390_serdes_get_stats, 3957 .phylink_validate = mv88e6390_phylink_validate, 3958 .avb_ops = &mv88e6390_avb_ops, 3959 .ptp_ops = &mv88e6352_ptp_ops, 3960 .phylink_validate = mv88e6390_phylink_validate, 3961 }; 3962 3963 static const struct mv88e6xxx_ops mv88e6240_ops = { 3964 /* MV88E6XXX_FAMILY_6352 */ 3965 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3966 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3967 .irl_init_all = mv88e6352_g2_irl_init_all, 3968 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3969 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3970 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3971 .phy_read = mv88e6xxx_g2_smi_phy_read, 3972 .phy_write = mv88e6xxx_g2_smi_phy_write, 3973 .port_set_link = mv88e6xxx_port_set_link, 3974 .port_set_duplex = mv88e6xxx_port_set_duplex, 3975 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3976 .port_set_speed = mv88e6352_port_set_speed, 3977 .port_tag_remap = mv88e6095_port_tag_remap, 3978 .port_set_policy = mv88e6352_port_set_policy, 3979 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3980 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3981 .port_set_ether_type = mv88e6351_port_set_ether_type, 3982 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3983 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3984 .port_pause_limit = mv88e6097_port_pause_limit, 3985 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3986 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3987 .port_link_state = mv88e6352_port_link_state, 3988 .port_get_cmode = mv88e6352_port_get_cmode, 3989 .port_setup_message_port = mv88e6xxx_setup_message_port, 3990 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3991 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3992 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3993 .stats_get_strings = mv88e6095_stats_get_strings, 3994 .stats_get_stats = mv88e6095_stats_get_stats, 3995 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3996 .set_egress_port = mv88e6095_g1_set_egress_port, 3997 .watchdog_ops = &mv88e6097_watchdog_ops, 3998 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3999 .pot_clear = mv88e6xxx_g2_pot_clear, 4000 .reset = mv88e6352_g1_reset, 4001 .rmu_disable = mv88e6352_g1_rmu_disable, 4002 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4003 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4004 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4005 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4006 .serdes_get_lane = mv88e6352_serdes_get_lane, 4007 .serdes_power = mv88e6352_serdes_power, 4008 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4009 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4010 .serdes_irq_status = mv88e6352_serdes_irq_status, 4011 .gpio_ops = &mv88e6352_gpio_ops, 4012 .avb_ops = &mv88e6352_avb_ops, 4013 .ptp_ops = &mv88e6352_ptp_ops, 4014 .phylink_validate = mv88e6352_phylink_validate, 4015 }; 4016 4017 static const struct mv88e6xxx_ops mv88e6250_ops = { 4018 /* MV88E6XXX_FAMILY_6250 */ 4019 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4020 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4021 .irl_init_all = mv88e6352_g2_irl_init_all, 4022 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4023 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4024 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4025 .phy_read = mv88e6xxx_g2_smi_phy_read, 4026 .phy_write = mv88e6xxx_g2_smi_phy_write, 4027 .port_set_link = mv88e6xxx_port_set_link, 4028 .port_set_duplex = mv88e6xxx_port_set_duplex, 4029 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4030 .port_set_speed = mv88e6250_port_set_speed, 4031 .port_tag_remap = mv88e6095_port_tag_remap, 4032 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4033 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4034 .port_set_ether_type = mv88e6351_port_set_ether_type, 4035 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4036 .port_pause_limit = mv88e6097_port_pause_limit, 4037 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4038 .port_link_state = mv88e6250_port_link_state, 4039 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4040 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4041 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4042 .stats_get_strings = mv88e6250_stats_get_strings, 4043 .stats_get_stats = mv88e6250_stats_get_stats, 4044 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4045 .set_egress_port = mv88e6095_g1_set_egress_port, 4046 .watchdog_ops = &mv88e6250_watchdog_ops, 4047 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4048 .pot_clear = mv88e6xxx_g2_pot_clear, 4049 .reset = mv88e6250_g1_reset, 4050 .vtu_getnext = mv88e6250_g1_vtu_getnext, 4051 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 4052 .avb_ops = &mv88e6352_avb_ops, 4053 .ptp_ops = &mv88e6250_ptp_ops, 4054 .phylink_validate = mv88e6065_phylink_validate, 4055 }; 4056 4057 static const struct mv88e6xxx_ops mv88e6290_ops = { 4058 /* MV88E6XXX_FAMILY_6390 */ 4059 .setup_errata = mv88e6390_setup_errata, 4060 .irl_init_all = mv88e6390_g2_irl_init_all, 4061 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4062 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4063 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4064 .phy_read = mv88e6xxx_g2_smi_phy_read, 4065 .phy_write = mv88e6xxx_g2_smi_phy_write, 4066 .port_set_link = mv88e6xxx_port_set_link, 4067 .port_set_duplex = mv88e6xxx_port_set_duplex, 4068 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4069 .port_set_speed = mv88e6390_port_set_speed, 4070 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4071 .port_tag_remap = mv88e6390_port_tag_remap, 4072 .port_set_policy = mv88e6352_port_set_policy, 4073 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4074 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4075 .port_set_ether_type = mv88e6351_port_set_ether_type, 4076 .port_pause_limit = mv88e6390_port_pause_limit, 4077 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4078 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4079 .port_link_state = mv88e6352_port_link_state, 4080 .port_get_cmode = mv88e6352_port_get_cmode, 4081 .port_set_cmode = mv88e6390_port_set_cmode, 4082 .port_setup_message_port = mv88e6xxx_setup_message_port, 4083 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4084 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4085 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4086 .stats_get_strings = mv88e6320_stats_get_strings, 4087 .stats_get_stats = mv88e6390_stats_get_stats, 4088 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4089 .set_egress_port = mv88e6390_g1_set_egress_port, 4090 .watchdog_ops = &mv88e6390_watchdog_ops, 4091 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4092 .pot_clear = mv88e6xxx_g2_pot_clear, 4093 .reset = mv88e6352_g1_reset, 4094 .rmu_disable = mv88e6390_g1_rmu_disable, 4095 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4096 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4097 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4098 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4099 .serdes_power = mv88e6390_serdes_power, 4100 .serdes_get_lane = mv88e6390_serdes_get_lane, 4101 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4102 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4103 .serdes_irq_status = mv88e6390_serdes_irq_status, 4104 .serdes_get_strings = mv88e6390_serdes_get_strings, 4105 .serdes_get_stats = mv88e6390_serdes_get_stats, 4106 .phylink_validate = mv88e6390_phylink_validate, 4107 .gpio_ops = &mv88e6352_gpio_ops, 4108 .avb_ops = &mv88e6390_avb_ops, 4109 .ptp_ops = &mv88e6352_ptp_ops, 4110 .phylink_validate = mv88e6390_phylink_validate, 4111 }; 4112 4113 static const struct mv88e6xxx_ops mv88e6320_ops = { 4114 /* MV88E6XXX_FAMILY_6320 */ 4115 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4116 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4117 .irl_init_all = mv88e6352_g2_irl_init_all, 4118 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4119 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4120 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4121 .phy_read = mv88e6xxx_g2_smi_phy_read, 4122 .phy_write = mv88e6xxx_g2_smi_phy_write, 4123 .port_set_link = mv88e6xxx_port_set_link, 4124 .port_set_duplex = mv88e6xxx_port_set_duplex, 4125 .port_set_speed = mv88e6185_port_set_speed, 4126 .port_tag_remap = mv88e6095_port_tag_remap, 4127 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4128 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4129 .port_set_ether_type = mv88e6351_port_set_ether_type, 4130 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4131 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4132 .port_pause_limit = mv88e6097_port_pause_limit, 4133 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4134 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4135 .port_link_state = mv88e6352_port_link_state, 4136 .port_get_cmode = mv88e6352_port_get_cmode, 4137 .port_setup_message_port = mv88e6xxx_setup_message_port, 4138 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4139 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4140 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4141 .stats_get_strings = mv88e6320_stats_get_strings, 4142 .stats_get_stats = mv88e6320_stats_get_stats, 4143 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4144 .set_egress_port = mv88e6095_g1_set_egress_port, 4145 .watchdog_ops = &mv88e6390_watchdog_ops, 4146 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4147 .pot_clear = mv88e6xxx_g2_pot_clear, 4148 .reset = mv88e6352_g1_reset, 4149 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4150 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4151 .gpio_ops = &mv88e6352_gpio_ops, 4152 .avb_ops = &mv88e6352_avb_ops, 4153 .ptp_ops = &mv88e6352_ptp_ops, 4154 .phylink_validate = mv88e6185_phylink_validate, 4155 }; 4156 4157 static const struct mv88e6xxx_ops mv88e6321_ops = { 4158 /* MV88E6XXX_FAMILY_6320 */ 4159 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4160 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4161 .irl_init_all = mv88e6352_g2_irl_init_all, 4162 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4163 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4164 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4165 .phy_read = mv88e6xxx_g2_smi_phy_read, 4166 .phy_write = mv88e6xxx_g2_smi_phy_write, 4167 .port_set_link = mv88e6xxx_port_set_link, 4168 .port_set_duplex = mv88e6xxx_port_set_duplex, 4169 .port_set_speed = mv88e6185_port_set_speed, 4170 .port_tag_remap = mv88e6095_port_tag_remap, 4171 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4172 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4173 .port_set_ether_type = mv88e6351_port_set_ether_type, 4174 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4175 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4176 .port_pause_limit = mv88e6097_port_pause_limit, 4177 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4178 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4179 .port_link_state = mv88e6352_port_link_state, 4180 .port_get_cmode = mv88e6352_port_get_cmode, 4181 .port_setup_message_port = mv88e6xxx_setup_message_port, 4182 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4183 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4184 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4185 .stats_get_strings = mv88e6320_stats_get_strings, 4186 .stats_get_stats = mv88e6320_stats_get_stats, 4187 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4188 .set_egress_port = mv88e6095_g1_set_egress_port, 4189 .watchdog_ops = &mv88e6390_watchdog_ops, 4190 .reset = mv88e6352_g1_reset, 4191 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4192 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4193 .gpio_ops = &mv88e6352_gpio_ops, 4194 .avb_ops = &mv88e6352_avb_ops, 4195 .ptp_ops = &mv88e6352_ptp_ops, 4196 .phylink_validate = mv88e6185_phylink_validate, 4197 }; 4198 4199 static const struct mv88e6xxx_ops mv88e6341_ops = { 4200 /* MV88E6XXX_FAMILY_6341 */ 4201 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4202 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4203 .irl_init_all = mv88e6352_g2_irl_init_all, 4204 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4205 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4206 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4207 .phy_read = mv88e6xxx_g2_smi_phy_read, 4208 .phy_write = mv88e6xxx_g2_smi_phy_write, 4209 .port_set_link = mv88e6xxx_port_set_link, 4210 .port_set_duplex = mv88e6xxx_port_set_duplex, 4211 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4212 .port_set_speed = mv88e6341_port_set_speed, 4213 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4214 .port_tag_remap = mv88e6095_port_tag_remap, 4215 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4216 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4217 .port_set_ether_type = mv88e6351_port_set_ether_type, 4218 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4219 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4220 .port_pause_limit = mv88e6097_port_pause_limit, 4221 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4222 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4223 .port_link_state = mv88e6352_port_link_state, 4224 .port_get_cmode = mv88e6352_port_get_cmode, 4225 .port_set_cmode = mv88e6341_port_set_cmode, 4226 .port_setup_message_port = mv88e6xxx_setup_message_port, 4227 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4228 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4229 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4230 .stats_get_strings = mv88e6320_stats_get_strings, 4231 .stats_get_stats = mv88e6390_stats_get_stats, 4232 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4233 .set_egress_port = mv88e6390_g1_set_egress_port, 4234 .watchdog_ops = &mv88e6390_watchdog_ops, 4235 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4236 .pot_clear = mv88e6xxx_g2_pot_clear, 4237 .reset = mv88e6352_g1_reset, 4238 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4239 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4240 .serdes_power = mv88e6390_serdes_power, 4241 .serdes_get_lane = mv88e6341_serdes_get_lane, 4242 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4243 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4244 .serdes_irq_status = mv88e6390_serdes_irq_status, 4245 .gpio_ops = &mv88e6352_gpio_ops, 4246 .avb_ops = &mv88e6390_avb_ops, 4247 .ptp_ops = &mv88e6352_ptp_ops, 4248 .phylink_validate = mv88e6341_phylink_validate, 4249 }; 4250 4251 static const struct mv88e6xxx_ops mv88e6350_ops = { 4252 /* MV88E6XXX_FAMILY_6351 */ 4253 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4254 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4255 .irl_init_all = mv88e6352_g2_irl_init_all, 4256 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4257 .phy_read = mv88e6xxx_g2_smi_phy_read, 4258 .phy_write = mv88e6xxx_g2_smi_phy_write, 4259 .port_set_link = mv88e6xxx_port_set_link, 4260 .port_set_duplex = mv88e6xxx_port_set_duplex, 4261 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4262 .port_set_speed = mv88e6185_port_set_speed, 4263 .port_tag_remap = mv88e6095_port_tag_remap, 4264 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4265 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4266 .port_set_ether_type = mv88e6351_port_set_ether_type, 4267 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4268 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4269 .port_pause_limit = mv88e6097_port_pause_limit, 4270 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4271 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4272 .port_link_state = mv88e6352_port_link_state, 4273 .port_get_cmode = mv88e6352_port_get_cmode, 4274 .port_setup_message_port = mv88e6xxx_setup_message_port, 4275 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4276 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4277 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4278 .stats_get_strings = mv88e6095_stats_get_strings, 4279 .stats_get_stats = mv88e6095_stats_get_stats, 4280 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4281 .set_egress_port = mv88e6095_g1_set_egress_port, 4282 .watchdog_ops = &mv88e6097_watchdog_ops, 4283 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4284 .pot_clear = mv88e6xxx_g2_pot_clear, 4285 .reset = mv88e6352_g1_reset, 4286 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4287 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4288 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4289 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4290 .phylink_validate = mv88e6185_phylink_validate, 4291 }; 4292 4293 static const struct mv88e6xxx_ops mv88e6351_ops = { 4294 /* MV88E6XXX_FAMILY_6351 */ 4295 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4296 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4297 .irl_init_all = mv88e6352_g2_irl_init_all, 4298 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4299 .phy_read = mv88e6xxx_g2_smi_phy_read, 4300 .phy_write = mv88e6xxx_g2_smi_phy_write, 4301 .port_set_link = mv88e6xxx_port_set_link, 4302 .port_set_duplex = mv88e6xxx_port_set_duplex, 4303 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4304 .port_set_speed = mv88e6185_port_set_speed, 4305 .port_tag_remap = mv88e6095_port_tag_remap, 4306 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4307 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4308 .port_set_ether_type = mv88e6351_port_set_ether_type, 4309 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4310 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4311 .port_pause_limit = mv88e6097_port_pause_limit, 4312 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4313 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4314 .port_link_state = mv88e6352_port_link_state, 4315 .port_get_cmode = mv88e6352_port_get_cmode, 4316 .port_setup_message_port = mv88e6xxx_setup_message_port, 4317 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4318 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4319 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4320 .stats_get_strings = mv88e6095_stats_get_strings, 4321 .stats_get_stats = mv88e6095_stats_get_stats, 4322 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4323 .set_egress_port = mv88e6095_g1_set_egress_port, 4324 .watchdog_ops = &mv88e6097_watchdog_ops, 4325 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4326 .pot_clear = mv88e6xxx_g2_pot_clear, 4327 .reset = mv88e6352_g1_reset, 4328 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4329 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4330 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4331 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4332 .avb_ops = &mv88e6352_avb_ops, 4333 .ptp_ops = &mv88e6352_ptp_ops, 4334 .phylink_validate = mv88e6185_phylink_validate, 4335 }; 4336 4337 static const struct mv88e6xxx_ops mv88e6352_ops = { 4338 /* MV88E6XXX_FAMILY_6352 */ 4339 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4340 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4341 .irl_init_all = mv88e6352_g2_irl_init_all, 4342 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4343 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4344 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4345 .phy_read = mv88e6xxx_g2_smi_phy_read, 4346 .phy_write = mv88e6xxx_g2_smi_phy_write, 4347 .port_set_link = mv88e6xxx_port_set_link, 4348 .port_set_duplex = mv88e6xxx_port_set_duplex, 4349 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4350 .port_set_speed = mv88e6352_port_set_speed, 4351 .port_tag_remap = mv88e6095_port_tag_remap, 4352 .port_set_policy = mv88e6352_port_set_policy, 4353 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4354 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4355 .port_set_ether_type = mv88e6351_port_set_ether_type, 4356 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4357 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4358 .port_pause_limit = mv88e6097_port_pause_limit, 4359 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4360 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4361 .port_link_state = mv88e6352_port_link_state, 4362 .port_get_cmode = mv88e6352_port_get_cmode, 4363 .port_setup_message_port = mv88e6xxx_setup_message_port, 4364 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4365 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4366 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4367 .stats_get_strings = mv88e6095_stats_get_strings, 4368 .stats_get_stats = mv88e6095_stats_get_stats, 4369 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4370 .set_egress_port = mv88e6095_g1_set_egress_port, 4371 .watchdog_ops = &mv88e6097_watchdog_ops, 4372 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4373 .pot_clear = mv88e6xxx_g2_pot_clear, 4374 .reset = mv88e6352_g1_reset, 4375 .rmu_disable = mv88e6352_g1_rmu_disable, 4376 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4377 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4378 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4379 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4380 .serdes_get_lane = mv88e6352_serdes_get_lane, 4381 .serdes_power = mv88e6352_serdes_power, 4382 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4383 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4384 .serdes_irq_status = mv88e6352_serdes_irq_status, 4385 .gpio_ops = &mv88e6352_gpio_ops, 4386 .avb_ops = &mv88e6352_avb_ops, 4387 .ptp_ops = &mv88e6352_ptp_ops, 4388 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4389 .serdes_get_strings = mv88e6352_serdes_get_strings, 4390 .serdes_get_stats = mv88e6352_serdes_get_stats, 4391 .phylink_validate = mv88e6352_phylink_validate, 4392 }; 4393 4394 static const struct mv88e6xxx_ops mv88e6390_ops = { 4395 /* MV88E6XXX_FAMILY_6390 */ 4396 .setup_errata = mv88e6390_setup_errata, 4397 .irl_init_all = mv88e6390_g2_irl_init_all, 4398 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4399 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4400 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4401 .phy_read = mv88e6xxx_g2_smi_phy_read, 4402 .phy_write = mv88e6xxx_g2_smi_phy_write, 4403 .port_set_link = mv88e6xxx_port_set_link, 4404 .port_set_duplex = mv88e6xxx_port_set_duplex, 4405 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4406 .port_set_speed = mv88e6390_port_set_speed, 4407 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4408 .port_tag_remap = mv88e6390_port_tag_remap, 4409 .port_set_policy = mv88e6352_port_set_policy, 4410 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4411 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4412 .port_set_ether_type = mv88e6351_port_set_ether_type, 4413 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4414 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4415 .port_pause_limit = mv88e6390_port_pause_limit, 4416 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4417 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4418 .port_link_state = mv88e6352_port_link_state, 4419 .port_get_cmode = mv88e6352_port_get_cmode, 4420 .port_set_cmode = mv88e6390_port_set_cmode, 4421 .port_setup_message_port = mv88e6xxx_setup_message_port, 4422 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4423 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4424 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4425 .stats_get_strings = mv88e6320_stats_get_strings, 4426 .stats_get_stats = mv88e6390_stats_get_stats, 4427 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4428 .set_egress_port = mv88e6390_g1_set_egress_port, 4429 .watchdog_ops = &mv88e6390_watchdog_ops, 4430 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4431 .pot_clear = mv88e6xxx_g2_pot_clear, 4432 .reset = mv88e6352_g1_reset, 4433 .rmu_disable = mv88e6390_g1_rmu_disable, 4434 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4435 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4436 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4437 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4438 .serdes_power = mv88e6390_serdes_power, 4439 .serdes_get_lane = mv88e6390_serdes_get_lane, 4440 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4441 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4442 .serdes_irq_status = mv88e6390_serdes_irq_status, 4443 .gpio_ops = &mv88e6352_gpio_ops, 4444 .avb_ops = &mv88e6390_avb_ops, 4445 .ptp_ops = &mv88e6352_ptp_ops, 4446 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4447 .serdes_get_strings = mv88e6390_serdes_get_strings, 4448 .serdes_get_stats = mv88e6390_serdes_get_stats, 4449 .phylink_validate = mv88e6390_phylink_validate, 4450 }; 4451 4452 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4453 /* MV88E6XXX_FAMILY_6390 */ 4454 .setup_errata = mv88e6390_setup_errata, 4455 .irl_init_all = mv88e6390_g2_irl_init_all, 4456 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4457 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4458 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4459 .phy_read = mv88e6xxx_g2_smi_phy_read, 4460 .phy_write = mv88e6xxx_g2_smi_phy_write, 4461 .port_set_link = mv88e6xxx_port_set_link, 4462 .port_set_duplex = mv88e6xxx_port_set_duplex, 4463 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4464 .port_set_speed = mv88e6390x_port_set_speed, 4465 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4466 .port_tag_remap = mv88e6390_port_tag_remap, 4467 .port_set_policy = mv88e6352_port_set_policy, 4468 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4469 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4470 .port_set_ether_type = mv88e6351_port_set_ether_type, 4471 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4472 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4473 .port_pause_limit = mv88e6390_port_pause_limit, 4474 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4475 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4476 .port_link_state = mv88e6352_port_link_state, 4477 .port_get_cmode = mv88e6352_port_get_cmode, 4478 .port_set_cmode = mv88e6390x_port_set_cmode, 4479 .port_setup_message_port = mv88e6xxx_setup_message_port, 4480 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4481 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4482 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4483 .stats_get_strings = mv88e6320_stats_get_strings, 4484 .stats_get_stats = mv88e6390_stats_get_stats, 4485 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4486 .set_egress_port = mv88e6390_g1_set_egress_port, 4487 .watchdog_ops = &mv88e6390_watchdog_ops, 4488 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4489 .pot_clear = mv88e6xxx_g2_pot_clear, 4490 .reset = mv88e6352_g1_reset, 4491 .rmu_disable = mv88e6390_g1_rmu_disable, 4492 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4493 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4494 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4495 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4496 .serdes_power = mv88e6390_serdes_power, 4497 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4498 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4499 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4500 .serdes_irq_status = mv88e6390_serdes_irq_status, 4501 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4502 .serdes_get_strings = mv88e6390_serdes_get_strings, 4503 .serdes_get_stats = mv88e6390_serdes_get_stats, 4504 .gpio_ops = &mv88e6352_gpio_ops, 4505 .avb_ops = &mv88e6390_avb_ops, 4506 .ptp_ops = &mv88e6352_ptp_ops, 4507 .phylink_validate = mv88e6390x_phylink_validate, 4508 }; 4509 4510 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4511 [MV88E6085] = { 4512 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4513 .family = MV88E6XXX_FAMILY_6097, 4514 .name = "Marvell 88E6085", 4515 .num_databases = 4096, 4516 .num_macs = 8192, 4517 .num_ports = 10, 4518 .num_internal_phys = 5, 4519 .max_vid = 4095, 4520 .port_base_addr = 0x10, 4521 .phy_base_addr = 0x0, 4522 .global1_addr = 0x1b, 4523 .global2_addr = 0x1c, 4524 .age_time_coeff = 15000, 4525 .g1_irqs = 8, 4526 .g2_irqs = 10, 4527 .atu_move_port_mask = 0xf, 4528 .pvt = true, 4529 .multi_chip = true, 4530 .tag_protocol = DSA_TAG_PROTO_DSA, 4531 .ops = &mv88e6085_ops, 4532 }, 4533 4534 [MV88E6095] = { 4535 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4536 .family = MV88E6XXX_FAMILY_6095, 4537 .name = "Marvell 88E6095/88E6095F", 4538 .num_databases = 256, 4539 .num_macs = 8192, 4540 .num_ports = 11, 4541 .num_internal_phys = 0, 4542 .max_vid = 4095, 4543 .port_base_addr = 0x10, 4544 .phy_base_addr = 0x0, 4545 .global1_addr = 0x1b, 4546 .global2_addr = 0x1c, 4547 .age_time_coeff = 15000, 4548 .g1_irqs = 8, 4549 .atu_move_port_mask = 0xf, 4550 .multi_chip = true, 4551 .tag_protocol = DSA_TAG_PROTO_DSA, 4552 .ops = &mv88e6095_ops, 4553 }, 4554 4555 [MV88E6097] = { 4556 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4557 .family = MV88E6XXX_FAMILY_6097, 4558 .name = "Marvell 88E6097/88E6097F", 4559 .num_databases = 4096, 4560 .num_macs = 8192, 4561 .num_ports = 11, 4562 .num_internal_phys = 8, 4563 .max_vid = 4095, 4564 .port_base_addr = 0x10, 4565 .phy_base_addr = 0x0, 4566 .global1_addr = 0x1b, 4567 .global2_addr = 0x1c, 4568 .age_time_coeff = 15000, 4569 .g1_irqs = 8, 4570 .g2_irqs = 10, 4571 .atu_move_port_mask = 0xf, 4572 .pvt = true, 4573 .multi_chip = true, 4574 .tag_protocol = DSA_TAG_PROTO_EDSA, 4575 .ops = &mv88e6097_ops, 4576 }, 4577 4578 [MV88E6123] = { 4579 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4580 .family = MV88E6XXX_FAMILY_6165, 4581 .name = "Marvell 88E6123", 4582 .num_databases = 4096, 4583 .num_macs = 1024, 4584 .num_ports = 3, 4585 .num_internal_phys = 5, 4586 .max_vid = 4095, 4587 .port_base_addr = 0x10, 4588 .phy_base_addr = 0x0, 4589 .global1_addr = 0x1b, 4590 .global2_addr = 0x1c, 4591 .age_time_coeff = 15000, 4592 .g1_irqs = 9, 4593 .g2_irqs = 10, 4594 .atu_move_port_mask = 0xf, 4595 .pvt = true, 4596 .multi_chip = true, 4597 .tag_protocol = DSA_TAG_PROTO_EDSA, 4598 .ops = &mv88e6123_ops, 4599 }, 4600 4601 [MV88E6131] = { 4602 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4603 .family = MV88E6XXX_FAMILY_6185, 4604 .name = "Marvell 88E6131", 4605 .num_databases = 256, 4606 .num_macs = 8192, 4607 .num_ports = 8, 4608 .num_internal_phys = 0, 4609 .max_vid = 4095, 4610 .port_base_addr = 0x10, 4611 .phy_base_addr = 0x0, 4612 .global1_addr = 0x1b, 4613 .global2_addr = 0x1c, 4614 .age_time_coeff = 15000, 4615 .g1_irqs = 9, 4616 .atu_move_port_mask = 0xf, 4617 .multi_chip = true, 4618 .tag_protocol = DSA_TAG_PROTO_DSA, 4619 .ops = &mv88e6131_ops, 4620 }, 4621 4622 [MV88E6141] = { 4623 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4624 .family = MV88E6XXX_FAMILY_6341, 4625 .name = "Marvell 88E6141", 4626 .num_databases = 4096, 4627 .num_macs = 2048, 4628 .num_ports = 6, 4629 .num_internal_phys = 5, 4630 .num_gpio = 11, 4631 .max_vid = 4095, 4632 .port_base_addr = 0x10, 4633 .phy_base_addr = 0x10, 4634 .global1_addr = 0x1b, 4635 .global2_addr = 0x1c, 4636 .age_time_coeff = 3750, 4637 .atu_move_port_mask = 0x1f, 4638 .g1_irqs = 9, 4639 .g2_irqs = 10, 4640 .pvt = true, 4641 .multi_chip = true, 4642 .tag_protocol = DSA_TAG_PROTO_EDSA, 4643 .ops = &mv88e6141_ops, 4644 }, 4645 4646 [MV88E6161] = { 4647 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4648 .family = MV88E6XXX_FAMILY_6165, 4649 .name = "Marvell 88E6161", 4650 .num_databases = 4096, 4651 .num_macs = 1024, 4652 .num_ports = 6, 4653 .num_internal_phys = 5, 4654 .max_vid = 4095, 4655 .port_base_addr = 0x10, 4656 .phy_base_addr = 0x0, 4657 .global1_addr = 0x1b, 4658 .global2_addr = 0x1c, 4659 .age_time_coeff = 15000, 4660 .g1_irqs = 9, 4661 .g2_irqs = 10, 4662 .atu_move_port_mask = 0xf, 4663 .pvt = true, 4664 .multi_chip = true, 4665 .tag_protocol = DSA_TAG_PROTO_EDSA, 4666 .ptp_support = true, 4667 .ops = &mv88e6161_ops, 4668 }, 4669 4670 [MV88E6165] = { 4671 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4672 .family = MV88E6XXX_FAMILY_6165, 4673 .name = "Marvell 88E6165", 4674 .num_databases = 4096, 4675 .num_macs = 8192, 4676 .num_ports = 6, 4677 .num_internal_phys = 0, 4678 .max_vid = 4095, 4679 .port_base_addr = 0x10, 4680 .phy_base_addr = 0x0, 4681 .global1_addr = 0x1b, 4682 .global2_addr = 0x1c, 4683 .age_time_coeff = 15000, 4684 .g1_irqs = 9, 4685 .g2_irqs = 10, 4686 .atu_move_port_mask = 0xf, 4687 .pvt = true, 4688 .multi_chip = true, 4689 .tag_protocol = DSA_TAG_PROTO_DSA, 4690 .ptp_support = true, 4691 .ops = &mv88e6165_ops, 4692 }, 4693 4694 [MV88E6171] = { 4695 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4696 .family = MV88E6XXX_FAMILY_6351, 4697 .name = "Marvell 88E6171", 4698 .num_databases = 4096, 4699 .num_macs = 8192, 4700 .num_ports = 7, 4701 .num_internal_phys = 5, 4702 .max_vid = 4095, 4703 .port_base_addr = 0x10, 4704 .phy_base_addr = 0x0, 4705 .global1_addr = 0x1b, 4706 .global2_addr = 0x1c, 4707 .age_time_coeff = 15000, 4708 .g1_irqs = 9, 4709 .g2_irqs = 10, 4710 .atu_move_port_mask = 0xf, 4711 .pvt = true, 4712 .multi_chip = true, 4713 .tag_protocol = DSA_TAG_PROTO_EDSA, 4714 .ops = &mv88e6171_ops, 4715 }, 4716 4717 [MV88E6172] = { 4718 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4719 .family = MV88E6XXX_FAMILY_6352, 4720 .name = "Marvell 88E6172", 4721 .num_databases = 4096, 4722 .num_macs = 8192, 4723 .num_ports = 7, 4724 .num_internal_phys = 5, 4725 .num_gpio = 15, 4726 .max_vid = 4095, 4727 .port_base_addr = 0x10, 4728 .phy_base_addr = 0x0, 4729 .global1_addr = 0x1b, 4730 .global2_addr = 0x1c, 4731 .age_time_coeff = 15000, 4732 .g1_irqs = 9, 4733 .g2_irqs = 10, 4734 .atu_move_port_mask = 0xf, 4735 .pvt = true, 4736 .multi_chip = true, 4737 .tag_protocol = DSA_TAG_PROTO_EDSA, 4738 .ops = &mv88e6172_ops, 4739 }, 4740 4741 [MV88E6175] = { 4742 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4743 .family = MV88E6XXX_FAMILY_6351, 4744 .name = "Marvell 88E6175", 4745 .num_databases = 4096, 4746 .num_macs = 8192, 4747 .num_ports = 7, 4748 .num_internal_phys = 5, 4749 .max_vid = 4095, 4750 .port_base_addr = 0x10, 4751 .phy_base_addr = 0x0, 4752 .global1_addr = 0x1b, 4753 .global2_addr = 0x1c, 4754 .age_time_coeff = 15000, 4755 .g1_irqs = 9, 4756 .g2_irqs = 10, 4757 .atu_move_port_mask = 0xf, 4758 .pvt = true, 4759 .multi_chip = true, 4760 .tag_protocol = DSA_TAG_PROTO_EDSA, 4761 .ops = &mv88e6175_ops, 4762 }, 4763 4764 [MV88E6176] = { 4765 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4766 .family = MV88E6XXX_FAMILY_6352, 4767 .name = "Marvell 88E6176", 4768 .num_databases = 4096, 4769 .num_macs = 8192, 4770 .num_ports = 7, 4771 .num_internal_phys = 5, 4772 .num_gpio = 15, 4773 .max_vid = 4095, 4774 .port_base_addr = 0x10, 4775 .phy_base_addr = 0x0, 4776 .global1_addr = 0x1b, 4777 .global2_addr = 0x1c, 4778 .age_time_coeff = 15000, 4779 .g1_irqs = 9, 4780 .g2_irqs = 10, 4781 .atu_move_port_mask = 0xf, 4782 .pvt = true, 4783 .multi_chip = true, 4784 .tag_protocol = DSA_TAG_PROTO_EDSA, 4785 .ops = &mv88e6176_ops, 4786 }, 4787 4788 [MV88E6185] = { 4789 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4790 .family = MV88E6XXX_FAMILY_6185, 4791 .name = "Marvell 88E6185", 4792 .num_databases = 256, 4793 .num_macs = 8192, 4794 .num_ports = 10, 4795 .num_internal_phys = 0, 4796 .max_vid = 4095, 4797 .port_base_addr = 0x10, 4798 .phy_base_addr = 0x0, 4799 .global1_addr = 0x1b, 4800 .global2_addr = 0x1c, 4801 .age_time_coeff = 15000, 4802 .g1_irqs = 8, 4803 .atu_move_port_mask = 0xf, 4804 .multi_chip = true, 4805 .tag_protocol = DSA_TAG_PROTO_EDSA, 4806 .ops = &mv88e6185_ops, 4807 }, 4808 4809 [MV88E6190] = { 4810 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4811 .family = MV88E6XXX_FAMILY_6390, 4812 .name = "Marvell 88E6190", 4813 .num_databases = 4096, 4814 .num_macs = 16384, 4815 .num_ports = 11, /* 10 + Z80 */ 4816 .num_internal_phys = 9, 4817 .num_gpio = 16, 4818 .max_vid = 8191, 4819 .port_base_addr = 0x0, 4820 .phy_base_addr = 0x0, 4821 .global1_addr = 0x1b, 4822 .global2_addr = 0x1c, 4823 .tag_protocol = DSA_TAG_PROTO_DSA, 4824 .age_time_coeff = 3750, 4825 .g1_irqs = 9, 4826 .g2_irqs = 14, 4827 .pvt = true, 4828 .multi_chip = true, 4829 .atu_move_port_mask = 0x1f, 4830 .ops = &mv88e6190_ops, 4831 }, 4832 4833 [MV88E6190X] = { 4834 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4835 .family = MV88E6XXX_FAMILY_6390, 4836 .name = "Marvell 88E6190X", 4837 .num_databases = 4096, 4838 .num_macs = 16384, 4839 .num_ports = 11, /* 10 + Z80 */ 4840 .num_internal_phys = 9, 4841 .num_gpio = 16, 4842 .max_vid = 8191, 4843 .port_base_addr = 0x0, 4844 .phy_base_addr = 0x0, 4845 .global1_addr = 0x1b, 4846 .global2_addr = 0x1c, 4847 .age_time_coeff = 3750, 4848 .g1_irqs = 9, 4849 .g2_irqs = 14, 4850 .atu_move_port_mask = 0x1f, 4851 .pvt = true, 4852 .multi_chip = true, 4853 .tag_protocol = DSA_TAG_PROTO_DSA, 4854 .ops = &mv88e6190x_ops, 4855 }, 4856 4857 [MV88E6191] = { 4858 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4859 .family = MV88E6XXX_FAMILY_6390, 4860 .name = "Marvell 88E6191", 4861 .num_databases = 4096, 4862 .num_macs = 16384, 4863 .num_ports = 11, /* 10 + Z80 */ 4864 .num_internal_phys = 9, 4865 .max_vid = 8191, 4866 .port_base_addr = 0x0, 4867 .phy_base_addr = 0x0, 4868 .global1_addr = 0x1b, 4869 .global2_addr = 0x1c, 4870 .age_time_coeff = 3750, 4871 .g1_irqs = 9, 4872 .g2_irqs = 14, 4873 .atu_move_port_mask = 0x1f, 4874 .pvt = true, 4875 .multi_chip = true, 4876 .tag_protocol = DSA_TAG_PROTO_DSA, 4877 .ptp_support = true, 4878 .ops = &mv88e6191_ops, 4879 }, 4880 4881 [MV88E6220] = { 4882 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4883 .family = MV88E6XXX_FAMILY_6250, 4884 .name = "Marvell 88E6220", 4885 .num_databases = 64, 4886 4887 /* Ports 2-4 are not routed to pins 4888 * => usable ports 0, 1, 5, 6 4889 */ 4890 .num_ports = 7, 4891 .num_internal_phys = 2, 4892 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4893 .max_vid = 4095, 4894 .port_base_addr = 0x08, 4895 .phy_base_addr = 0x00, 4896 .global1_addr = 0x0f, 4897 .global2_addr = 0x07, 4898 .age_time_coeff = 15000, 4899 .g1_irqs = 9, 4900 .g2_irqs = 10, 4901 .atu_move_port_mask = 0xf, 4902 .dual_chip = true, 4903 .tag_protocol = DSA_TAG_PROTO_DSA, 4904 .ptp_support = true, 4905 .ops = &mv88e6250_ops, 4906 }, 4907 4908 [MV88E6240] = { 4909 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4910 .family = MV88E6XXX_FAMILY_6352, 4911 .name = "Marvell 88E6240", 4912 .num_databases = 4096, 4913 .num_macs = 8192, 4914 .num_ports = 7, 4915 .num_internal_phys = 5, 4916 .num_gpio = 15, 4917 .max_vid = 4095, 4918 .port_base_addr = 0x10, 4919 .phy_base_addr = 0x0, 4920 .global1_addr = 0x1b, 4921 .global2_addr = 0x1c, 4922 .age_time_coeff = 15000, 4923 .g1_irqs = 9, 4924 .g2_irqs = 10, 4925 .atu_move_port_mask = 0xf, 4926 .pvt = true, 4927 .multi_chip = true, 4928 .tag_protocol = DSA_TAG_PROTO_EDSA, 4929 .ptp_support = true, 4930 .ops = &mv88e6240_ops, 4931 }, 4932 4933 [MV88E6250] = { 4934 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4935 .family = MV88E6XXX_FAMILY_6250, 4936 .name = "Marvell 88E6250", 4937 .num_databases = 64, 4938 .num_ports = 7, 4939 .num_internal_phys = 5, 4940 .max_vid = 4095, 4941 .port_base_addr = 0x08, 4942 .phy_base_addr = 0x00, 4943 .global1_addr = 0x0f, 4944 .global2_addr = 0x07, 4945 .age_time_coeff = 15000, 4946 .g1_irqs = 9, 4947 .g2_irqs = 10, 4948 .atu_move_port_mask = 0xf, 4949 .dual_chip = true, 4950 .tag_protocol = DSA_TAG_PROTO_DSA, 4951 .ptp_support = true, 4952 .ops = &mv88e6250_ops, 4953 }, 4954 4955 [MV88E6290] = { 4956 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4957 .family = MV88E6XXX_FAMILY_6390, 4958 .name = "Marvell 88E6290", 4959 .num_databases = 4096, 4960 .num_ports = 11, /* 10 + Z80 */ 4961 .num_internal_phys = 9, 4962 .num_gpio = 16, 4963 .max_vid = 8191, 4964 .port_base_addr = 0x0, 4965 .phy_base_addr = 0x0, 4966 .global1_addr = 0x1b, 4967 .global2_addr = 0x1c, 4968 .age_time_coeff = 3750, 4969 .g1_irqs = 9, 4970 .g2_irqs = 14, 4971 .atu_move_port_mask = 0x1f, 4972 .pvt = true, 4973 .multi_chip = true, 4974 .tag_protocol = DSA_TAG_PROTO_DSA, 4975 .ptp_support = true, 4976 .ops = &mv88e6290_ops, 4977 }, 4978 4979 [MV88E6320] = { 4980 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4981 .family = MV88E6XXX_FAMILY_6320, 4982 .name = "Marvell 88E6320", 4983 .num_databases = 4096, 4984 .num_macs = 8192, 4985 .num_ports = 7, 4986 .num_internal_phys = 5, 4987 .num_gpio = 15, 4988 .max_vid = 4095, 4989 .port_base_addr = 0x10, 4990 .phy_base_addr = 0x0, 4991 .global1_addr = 0x1b, 4992 .global2_addr = 0x1c, 4993 .age_time_coeff = 15000, 4994 .g1_irqs = 8, 4995 .g2_irqs = 10, 4996 .atu_move_port_mask = 0xf, 4997 .pvt = true, 4998 .multi_chip = true, 4999 .tag_protocol = DSA_TAG_PROTO_EDSA, 5000 .ptp_support = true, 5001 .ops = &mv88e6320_ops, 5002 }, 5003 5004 [MV88E6321] = { 5005 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5006 .family = MV88E6XXX_FAMILY_6320, 5007 .name = "Marvell 88E6321", 5008 .num_databases = 4096, 5009 .num_macs = 8192, 5010 .num_ports = 7, 5011 .num_internal_phys = 5, 5012 .num_gpio = 15, 5013 .max_vid = 4095, 5014 .port_base_addr = 0x10, 5015 .phy_base_addr = 0x0, 5016 .global1_addr = 0x1b, 5017 .global2_addr = 0x1c, 5018 .age_time_coeff = 15000, 5019 .g1_irqs = 8, 5020 .g2_irqs = 10, 5021 .atu_move_port_mask = 0xf, 5022 .multi_chip = true, 5023 .tag_protocol = DSA_TAG_PROTO_EDSA, 5024 .ptp_support = true, 5025 .ops = &mv88e6321_ops, 5026 }, 5027 5028 [MV88E6341] = { 5029 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5030 .family = MV88E6XXX_FAMILY_6341, 5031 .name = "Marvell 88E6341", 5032 .num_databases = 4096, 5033 .num_macs = 2048, 5034 .num_internal_phys = 5, 5035 .num_ports = 6, 5036 .num_gpio = 11, 5037 .max_vid = 4095, 5038 .port_base_addr = 0x10, 5039 .phy_base_addr = 0x10, 5040 .global1_addr = 0x1b, 5041 .global2_addr = 0x1c, 5042 .age_time_coeff = 3750, 5043 .atu_move_port_mask = 0x1f, 5044 .g1_irqs = 9, 5045 .g2_irqs = 10, 5046 .pvt = true, 5047 .multi_chip = true, 5048 .tag_protocol = DSA_TAG_PROTO_EDSA, 5049 .ptp_support = true, 5050 .ops = &mv88e6341_ops, 5051 }, 5052 5053 [MV88E6350] = { 5054 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5055 .family = MV88E6XXX_FAMILY_6351, 5056 .name = "Marvell 88E6350", 5057 .num_databases = 4096, 5058 .num_macs = 8192, 5059 .num_ports = 7, 5060 .num_internal_phys = 5, 5061 .max_vid = 4095, 5062 .port_base_addr = 0x10, 5063 .phy_base_addr = 0x0, 5064 .global1_addr = 0x1b, 5065 .global2_addr = 0x1c, 5066 .age_time_coeff = 15000, 5067 .g1_irqs = 9, 5068 .g2_irqs = 10, 5069 .atu_move_port_mask = 0xf, 5070 .pvt = true, 5071 .multi_chip = true, 5072 .tag_protocol = DSA_TAG_PROTO_EDSA, 5073 .ops = &mv88e6350_ops, 5074 }, 5075 5076 [MV88E6351] = { 5077 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5078 .family = MV88E6XXX_FAMILY_6351, 5079 .name = "Marvell 88E6351", 5080 .num_databases = 4096, 5081 .num_macs = 8192, 5082 .num_ports = 7, 5083 .num_internal_phys = 5, 5084 .max_vid = 4095, 5085 .port_base_addr = 0x10, 5086 .phy_base_addr = 0x0, 5087 .global1_addr = 0x1b, 5088 .global2_addr = 0x1c, 5089 .age_time_coeff = 15000, 5090 .g1_irqs = 9, 5091 .g2_irqs = 10, 5092 .atu_move_port_mask = 0xf, 5093 .pvt = true, 5094 .multi_chip = true, 5095 .tag_protocol = DSA_TAG_PROTO_EDSA, 5096 .ops = &mv88e6351_ops, 5097 }, 5098 5099 [MV88E6352] = { 5100 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5101 .family = MV88E6XXX_FAMILY_6352, 5102 .name = "Marvell 88E6352", 5103 .num_databases = 4096, 5104 .num_macs = 8192, 5105 .num_ports = 7, 5106 .num_internal_phys = 5, 5107 .num_gpio = 15, 5108 .max_vid = 4095, 5109 .port_base_addr = 0x10, 5110 .phy_base_addr = 0x0, 5111 .global1_addr = 0x1b, 5112 .global2_addr = 0x1c, 5113 .age_time_coeff = 15000, 5114 .g1_irqs = 9, 5115 .g2_irqs = 10, 5116 .atu_move_port_mask = 0xf, 5117 .pvt = true, 5118 .multi_chip = true, 5119 .tag_protocol = DSA_TAG_PROTO_EDSA, 5120 .ptp_support = true, 5121 .ops = &mv88e6352_ops, 5122 }, 5123 [MV88E6390] = { 5124 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5125 .family = MV88E6XXX_FAMILY_6390, 5126 .name = "Marvell 88E6390", 5127 .num_databases = 4096, 5128 .num_macs = 16384, 5129 .num_ports = 11, /* 10 + Z80 */ 5130 .num_internal_phys = 9, 5131 .num_gpio = 16, 5132 .max_vid = 8191, 5133 .port_base_addr = 0x0, 5134 .phy_base_addr = 0x0, 5135 .global1_addr = 0x1b, 5136 .global2_addr = 0x1c, 5137 .age_time_coeff = 3750, 5138 .g1_irqs = 9, 5139 .g2_irqs = 14, 5140 .atu_move_port_mask = 0x1f, 5141 .pvt = true, 5142 .multi_chip = true, 5143 .tag_protocol = DSA_TAG_PROTO_DSA, 5144 .ptp_support = true, 5145 .ops = &mv88e6390_ops, 5146 }, 5147 [MV88E6390X] = { 5148 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5149 .family = MV88E6XXX_FAMILY_6390, 5150 .name = "Marvell 88E6390X", 5151 .num_databases = 4096, 5152 .num_macs = 16384, 5153 .num_ports = 11, /* 10 + Z80 */ 5154 .num_internal_phys = 9, 5155 .num_gpio = 16, 5156 .max_vid = 8191, 5157 .port_base_addr = 0x0, 5158 .phy_base_addr = 0x0, 5159 .global1_addr = 0x1b, 5160 .global2_addr = 0x1c, 5161 .age_time_coeff = 3750, 5162 .g1_irqs = 9, 5163 .g2_irqs = 14, 5164 .atu_move_port_mask = 0x1f, 5165 .pvt = true, 5166 .multi_chip = true, 5167 .tag_protocol = DSA_TAG_PROTO_DSA, 5168 .ptp_support = true, 5169 .ops = &mv88e6390x_ops, 5170 }, 5171 }; 5172 5173 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5174 { 5175 int i; 5176 5177 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5178 if (mv88e6xxx_table[i].prod_num == prod_num) 5179 return &mv88e6xxx_table[i]; 5180 5181 return NULL; 5182 } 5183 5184 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5185 { 5186 const struct mv88e6xxx_info *info; 5187 unsigned int prod_num, rev; 5188 u16 id; 5189 int err; 5190 5191 mv88e6xxx_reg_lock(chip); 5192 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5193 mv88e6xxx_reg_unlock(chip); 5194 if (err) 5195 return err; 5196 5197 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5198 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5199 5200 info = mv88e6xxx_lookup_info(prod_num); 5201 if (!info) 5202 return -ENODEV; 5203 5204 /* Update the compatible info with the probed one */ 5205 chip->info = info; 5206 5207 err = mv88e6xxx_g2_require(chip); 5208 if (err) 5209 return err; 5210 5211 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5212 chip->info->prod_num, chip->info->name, rev); 5213 5214 return 0; 5215 } 5216 5217 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5218 { 5219 struct mv88e6xxx_chip *chip; 5220 5221 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5222 if (!chip) 5223 return NULL; 5224 5225 chip->dev = dev; 5226 5227 mutex_init(&chip->reg_lock); 5228 INIT_LIST_HEAD(&chip->mdios); 5229 idr_init(&chip->policies); 5230 5231 return chip; 5232 } 5233 5234 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5235 int port, 5236 enum dsa_tag_protocol m) 5237 { 5238 struct mv88e6xxx_chip *chip = ds->priv; 5239 5240 return chip->info->tag_protocol; 5241 } 5242 5243 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 5244 const struct switchdev_obj_port_mdb *mdb) 5245 { 5246 /* We don't need any dynamic resource from the kernel (yet), 5247 * so skip the prepare phase. 5248 */ 5249 5250 return 0; 5251 } 5252 5253 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5254 const struct switchdev_obj_port_mdb *mdb) 5255 { 5256 struct mv88e6xxx_chip *chip = ds->priv; 5257 5258 mv88e6xxx_reg_lock(chip); 5259 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5260 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 5261 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 5262 port); 5263 mv88e6xxx_reg_unlock(chip); 5264 } 5265 5266 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5267 const struct switchdev_obj_port_mdb *mdb) 5268 { 5269 struct mv88e6xxx_chip *chip = ds->priv; 5270 int err; 5271 5272 mv88e6xxx_reg_lock(chip); 5273 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5274 mv88e6xxx_reg_unlock(chip); 5275 5276 return err; 5277 } 5278 5279 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5280 struct dsa_mall_mirror_tc_entry *mirror, 5281 bool ingress) 5282 { 5283 enum mv88e6xxx_egress_direction direction = ingress ? 5284 MV88E6XXX_EGRESS_DIR_INGRESS : 5285 MV88E6XXX_EGRESS_DIR_EGRESS; 5286 struct mv88e6xxx_chip *chip = ds->priv; 5287 bool other_mirrors = false; 5288 int i; 5289 int err; 5290 5291 if (!chip->info->ops->set_egress_port) 5292 return -EOPNOTSUPP; 5293 5294 mutex_lock(&chip->reg_lock); 5295 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5296 mirror->to_local_port) { 5297 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5298 other_mirrors |= ingress ? 5299 chip->ports[i].mirror_ingress : 5300 chip->ports[i].mirror_egress; 5301 5302 /* Can't change egress port when other mirror is active */ 5303 if (other_mirrors) { 5304 err = -EBUSY; 5305 goto out; 5306 } 5307 5308 err = chip->info->ops->set_egress_port(chip, 5309 direction, 5310 mirror->to_local_port); 5311 if (err) 5312 goto out; 5313 } 5314 5315 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5316 out: 5317 mutex_unlock(&chip->reg_lock); 5318 5319 return err; 5320 } 5321 5322 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5323 struct dsa_mall_mirror_tc_entry *mirror) 5324 { 5325 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5326 MV88E6XXX_EGRESS_DIR_INGRESS : 5327 MV88E6XXX_EGRESS_DIR_EGRESS; 5328 struct mv88e6xxx_chip *chip = ds->priv; 5329 bool other_mirrors = false; 5330 int i; 5331 5332 mutex_lock(&chip->reg_lock); 5333 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5334 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5335 5336 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5337 other_mirrors |= mirror->ingress ? 5338 chip->ports[i].mirror_ingress : 5339 chip->ports[i].mirror_egress; 5340 5341 /* Reset egress port when no other mirror is active */ 5342 if (!other_mirrors) { 5343 if (chip->info->ops->set_egress_port(chip, 5344 direction, 5345 dsa_upstream_port(ds, 5346 port))) 5347 dev_err(ds->dev, "failed to set egress port\n"); 5348 } 5349 5350 mutex_unlock(&chip->reg_lock); 5351 } 5352 5353 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5354 bool unicast, bool multicast) 5355 { 5356 struct mv88e6xxx_chip *chip = ds->priv; 5357 int err = -EOPNOTSUPP; 5358 5359 mv88e6xxx_reg_lock(chip); 5360 if (chip->info->ops->port_set_egress_floods) 5361 err = chip->info->ops->port_set_egress_floods(chip, port, 5362 unicast, 5363 multicast); 5364 mv88e6xxx_reg_unlock(chip); 5365 5366 return err; 5367 } 5368 5369 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5370 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5371 .setup = mv88e6xxx_setup, 5372 .teardown = mv88e6xxx_teardown, 5373 .phylink_validate = mv88e6xxx_validate, 5374 .phylink_mac_link_state = mv88e6xxx_link_state, 5375 .phylink_mac_config = mv88e6xxx_mac_config, 5376 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5377 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5378 .get_strings = mv88e6xxx_get_strings, 5379 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5380 .get_sset_count = mv88e6xxx_get_sset_count, 5381 .port_enable = mv88e6xxx_port_enable, 5382 .port_disable = mv88e6xxx_port_disable, 5383 .get_mac_eee = mv88e6xxx_get_mac_eee, 5384 .set_mac_eee = mv88e6xxx_set_mac_eee, 5385 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5386 .get_eeprom = mv88e6xxx_get_eeprom, 5387 .set_eeprom = mv88e6xxx_set_eeprom, 5388 .get_regs_len = mv88e6xxx_get_regs_len, 5389 .get_regs = mv88e6xxx_get_regs, 5390 .get_rxnfc = mv88e6xxx_get_rxnfc, 5391 .set_rxnfc = mv88e6xxx_set_rxnfc, 5392 .set_ageing_time = mv88e6xxx_set_ageing_time, 5393 .port_bridge_join = mv88e6xxx_port_bridge_join, 5394 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5395 .port_egress_floods = mv88e6xxx_port_egress_floods, 5396 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5397 .port_fast_age = mv88e6xxx_port_fast_age, 5398 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5399 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 5400 .port_vlan_add = mv88e6xxx_port_vlan_add, 5401 .port_vlan_del = mv88e6xxx_port_vlan_del, 5402 .port_fdb_add = mv88e6xxx_port_fdb_add, 5403 .port_fdb_del = mv88e6xxx_port_fdb_del, 5404 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5405 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 5406 .port_mdb_add = mv88e6xxx_port_mdb_add, 5407 .port_mdb_del = mv88e6xxx_port_mdb_del, 5408 .port_mirror_add = mv88e6xxx_port_mirror_add, 5409 .port_mirror_del = mv88e6xxx_port_mirror_del, 5410 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5411 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5412 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5413 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5414 .port_txtstamp = mv88e6xxx_port_txtstamp, 5415 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5416 .get_ts_info = mv88e6xxx_get_ts_info, 5417 .devlink_param_get = mv88e6xxx_devlink_param_get, 5418 .devlink_param_set = mv88e6xxx_devlink_param_set, 5419 }; 5420 5421 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5422 { 5423 struct device *dev = chip->dev; 5424 struct dsa_switch *ds; 5425 5426 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5427 if (!ds) 5428 return -ENOMEM; 5429 5430 ds->dev = dev; 5431 ds->num_ports = mv88e6xxx_num_ports(chip); 5432 ds->priv = chip; 5433 ds->dev = dev; 5434 ds->ops = &mv88e6xxx_switch_ops; 5435 ds->ageing_time_min = chip->info->age_time_coeff; 5436 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5437 5438 dev_set_drvdata(dev, ds); 5439 5440 return dsa_register_switch(ds); 5441 } 5442 5443 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5444 { 5445 dsa_unregister_switch(chip->ds); 5446 } 5447 5448 static const void *pdata_device_get_match_data(struct device *dev) 5449 { 5450 const struct of_device_id *matches = dev->driver->of_match_table; 5451 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5452 5453 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5454 matches++) { 5455 if (!strcmp(pdata->compatible, matches->compatible)) 5456 return matches->data; 5457 } 5458 return NULL; 5459 } 5460 5461 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5462 * would be lost after a power cycle so prevent it to be suspended. 5463 */ 5464 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5465 { 5466 return -EOPNOTSUPP; 5467 } 5468 5469 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5470 { 5471 return 0; 5472 } 5473 5474 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5475 5476 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5477 { 5478 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5479 const struct mv88e6xxx_info *compat_info = NULL; 5480 struct device *dev = &mdiodev->dev; 5481 struct device_node *np = dev->of_node; 5482 struct mv88e6xxx_chip *chip; 5483 int port; 5484 int err; 5485 5486 if (!np && !pdata) 5487 return -EINVAL; 5488 5489 if (np) 5490 compat_info = of_device_get_match_data(dev); 5491 5492 if (pdata) { 5493 compat_info = pdata_device_get_match_data(dev); 5494 5495 if (!pdata->netdev) 5496 return -EINVAL; 5497 5498 for (port = 0; port < DSA_MAX_PORTS; port++) { 5499 if (!(pdata->enabled_ports & (1 << port))) 5500 continue; 5501 if (strcmp(pdata->cd.port_names[port], "cpu")) 5502 continue; 5503 pdata->cd.netdev[port] = &pdata->netdev->dev; 5504 break; 5505 } 5506 } 5507 5508 if (!compat_info) 5509 return -EINVAL; 5510 5511 chip = mv88e6xxx_alloc_chip(dev); 5512 if (!chip) { 5513 err = -ENOMEM; 5514 goto out; 5515 } 5516 5517 chip->info = compat_info; 5518 5519 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5520 if (err) 5521 goto out; 5522 5523 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5524 if (IS_ERR(chip->reset)) { 5525 err = PTR_ERR(chip->reset); 5526 goto out; 5527 } 5528 if (chip->reset) 5529 usleep_range(1000, 2000); 5530 5531 err = mv88e6xxx_detect(chip); 5532 if (err) 5533 goto out; 5534 5535 mv88e6xxx_phy_init(chip); 5536 5537 if (chip->info->ops->get_eeprom) { 5538 if (np) 5539 of_property_read_u32(np, "eeprom-length", 5540 &chip->eeprom_len); 5541 else 5542 chip->eeprom_len = pdata->eeprom_len; 5543 } 5544 5545 mv88e6xxx_reg_lock(chip); 5546 err = mv88e6xxx_switch_reset(chip); 5547 mv88e6xxx_reg_unlock(chip); 5548 if (err) 5549 goto out; 5550 5551 if (np) { 5552 chip->irq = of_irq_get(np, 0); 5553 if (chip->irq == -EPROBE_DEFER) { 5554 err = chip->irq; 5555 goto out; 5556 } 5557 } 5558 5559 if (pdata) 5560 chip->irq = pdata->irq; 5561 5562 /* Has to be performed before the MDIO bus is created, because 5563 * the PHYs will link their interrupts to these interrupt 5564 * controllers 5565 */ 5566 mv88e6xxx_reg_lock(chip); 5567 if (chip->irq > 0) 5568 err = mv88e6xxx_g1_irq_setup(chip); 5569 else 5570 err = mv88e6xxx_irq_poll_setup(chip); 5571 mv88e6xxx_reg_unlock(chip); 5572 5573 if (err) 5574 goto out; 5575 5576 if (chip->info->g2_irqs > 0) { 5577 err = mv88e6xxx_g2_irq_setup(chip); 5578 if (err) 5579 goto out_g1_irq; 5580 } 5581 5582 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5583 if (err) 5584 goto out_g2_irq; 5585 5586 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5587 if (err) 5588 goto out_g1_atu_prob_irq; 5589 5590 err = mv88e6xxx_mdios_register(chip, np); 5591 if (err) 5592 goto out_g1_vtu_prob_irq; 5593 5594 err = mv88e6xxx_register_switch(chip); 5595 if (err) 5596 goto out_mdio; 5597 5598 return 0; 5599 5600 out_mdio: 5601 mv88e6xxx_mdios_unregister(chip); 5602 out_g1_vtu_prob_irq: 5603 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5604 out_g1_atu_prob_irq: 5605 mv88e6xxx_g1_atu_prob_irq_free(chip); 5606 out_g2_irq: 5607 if (chip->info->g2_irqs > 0) 5608 mv88e6xxx_g2_irq_free(chip); 5609 out_g1_irq: 5610 if (chip->irq > 0) 5611 mv88e6xxx_g1_irq_free(chip); 5612 else 5613 mv88e6xxx_irq_poll_free(chip); 5614 out: 5615 if (pdata) 5616 dev_put(pdata->netdev); 5617 5618 return err; 5619 } 5620 5621 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5622 { 5623 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5624 struct mv88e6xxx_chip *chip = ds->priv; 5625 5626 if (chip->info->ptp_support) { 5627 mv88e6xxx_hwtstamp_free(chip); 5628 mv88e6xxx_ptp_free(chip); 5629 } 5630 5631 mv88e6xxx_phy_destroy(chip); 5632 mv88e6xxx_unregister_switch(chip); 5633 mv88e6xxx_mdios_unregister(chip); 5634 5635 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5636 mv88e6xxx_g1_atu_prob_irq_free(chip); 5637 5638 if (chip->info->g2_irqs > 0) 5639 mv88e6xxx_g2_irq_free(chip); 5640 5641 if (chip->irq > 0) 5642 mv88e6xxx_g1_irq_free(chip); 5643 else 5644 mv88e6xxx_irq_poll_free(chip); 5645 } 5646 5647 static const struct of_device_id mv88e6xxx_of_match[] = { 5648 { 5649 .compatible = "marvell,mv88e6085", 5650 .data = &mv88e6xxx_table[MV88E6085], 5651 }, 5652 { 5653 .compatible = "marvell,mv88e6190", 5654 .data = &mv88e6xxx_table[MV88E6190], 5655 }, 5656 { 5657 .compatible = "marvell,mv88e6250", 5658 .data = &mv88e6xxx_table[MV88E6250], 5659 }, 5660 { /* sentinel */ }, 5661 }; 5662 5663 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5664 5665 static struct mdio_driver mv88e6xxx_driver = { 5666 .probe = mv88e6xxx_probe, 5667 .remove = mv88e6xxx_remove, 5668 .mdiodrv.driver = { 5669 .name = "mv88e6085", 5670 .of_match_table = mv88e6xxx_of_match, 5671 .pm = &mv88e6xxx_pm_ops, 5672 }, 5673 }; 5674 5675 mdio_module_driver(mv88e6xxx_driver); 5676 5677 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5678 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5679 MODULE_LICENSE("GPL"); 5680