1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP 4 */ 5 #include <linux/fsl/enetc_mdio.h> 6 #include <soc/mscc/ocelot_qsys.h> 7 #include <soc/mscc/ocelot_vcap.h> 8 #include <soc/mscc/ocelot_ana.h> 9 #include <soc/mscc/ocelot_ptp.h> 10 #include <soc/mscc/ocelot_sys.h> 11 #include <net/tc_act/tc_gate.h> 12 #include <soc/mscc/ocelot.h> 13 #include <linux/dsa/ocelot.h> 14 #include <linux/pcs-lynx.h> 15 #include <net/pkt_sched.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/pci.h> 19 #include <linux/time.h> 20 #include "felix.h" 21 22 #define VSC9959_NUM_PORTS 6 23 24 #define VSC9959_TAS_GCL_ENTRY_MAX 63 25 #define VSC9959_TAS_MIN_GATE_LEN_NS 33 26 #define VSC9959_VCAP_POLICER_BASE 63 27 #define VSC9959_VCAP_POLICER_MAX 383 28 #define VSC9959_SWITCH_PCI_BAR 4 29 #define VSC9959_IMDIO_PCI_BAR 0 30 31 #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 32 OCELOT_PORT_MODE_QSGMII | \ 33 OCELOT_PORT_MODE_1000BASEX | \ 34 OCELOT_PORT_MODE_2500BASEX | \ 35 OCELOT_PORT_MODE_USXGMII) 36 37 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 38 VSC9959_PORT_MODE_SERDES, 39 VSC9959_PORT_MODE_SERDES, 40 VSC9959_PORT_MODE_SERDES, 41 VSC9959_PORT_MODE_SERDES, 42 OCELOT_PORT_MODE_INTERNAL, 43 OCELOT_PORT_MODE_INTERNAL, 44 }; 45 46 static const u32 vsc9959_ana_regmap[] = { 47 REG(ANA_ADVLEARN, 0x0089a0), 48 REG(ANA_VLANMASK, 0x0089a4), 49 REG_RESERVED(ANA_PORT_B_DOMAIN), 50 REG(ANA_ANAGEFIL, 0x0089ac), 51 REG(ANA_ANEVENTS, 0x0089b0), 52 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 53 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 54 REG(ANA_ISOLATED_PORTS, 0x0089c8), 55 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 56 REG(ANA_AUTOAGE, 0x0089d0), 57 REG(ANA_MACTOPTIONS, 0x0089d4), 58 REG(ANA_LEARNDISC, 0x0089d8), 59 REG(ANA_AGENCTRL, 0x0089dc), 60 REG(ANA_MIRRORPORTS, 0x0089e0), 61 REG(ANA_EMIRRORPORTS, 0x0089e4), 62 REG(ANA_FLOODING, 0x0089e8), 63 REG(ANA_FLOODING_IPMC, 0x008a08), 64 REG(ANA_SFLOW_CFG, 0x008a0c), 65 REG(ANA_PORT_MODE, 0x008a28), 66 REG(ANA_CUT_THRU_CFG, 0x008a48), 67 REG(ANA_PGID_PGID, 0x008400), 68 REG(ANA_TABLES_ANMOVED, 0x007f1c), 69 REG(ANA_TABLES_MACHDATA, 0x007f20), 70 REG(ANA_TABLES_MACLDATA, 0x007f24), 71 REG(ANA_TABLES_STREAMDATA, 0x007f28), 72 REG(ANA_TABLES_MACACCESS, 0x007f2c), 73 REG(ANA_TABLES_MACTINDX, 0x007f30), 74 REG(ANA_TABLES_VLANACCESS, 0x007f34), 75 REG(ANA_TABLES_VLANTIDX, 0x007f38), 76 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 77 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 78 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 79 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 80 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 81 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 82 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 83 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 84 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 85 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 86 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 87 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 88 REG(ANA_MSTI_STATE, 0x008600), 89 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 90 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 91 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 92 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 93 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 94 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 95 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 96 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 97 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 98 REG(ANA_SG_STATUS_REG_1, 0x008980), 99 REG(ANA_SG_STATUS_REG_2, 0x008984), 100 REG(ANA_SG_STATUS_REG_3, 0x008988), 101 REG(ANA_PORT_VLAN_CFG, 0x007800), 102 REG(ANA_PORT_DROP_CFG, 0x007804), 103 REG(ANA_PORT_QOS_CFG, 0x007808), 104 REG(ANA_PORT_VCAP_CFG, 0x00780c), 105 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 106 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 107 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 108 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 109 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 110 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 111 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 112 REG(ANA_PORT_PORT_CFG, 0x007870), 113 REG(ANA_PORT_POL_CFG, 0x007874), 114 REG(ANA_PORT_PTP_CFG, 0x007878), 115 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 116 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 117 REG(ANA_PORT_SFID_CFG, 0x007884), 118 REG(ANA_PFC_PFC_CFG, 0x008800), 119 REG_RESERVED(ANA_PFC_PFC_TIMER), 120 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 121 REG_RESERVED(ANA_IPT_IPT), 122 REG_RESERVED(ANA_PPT_PPT), 123 REG_RESERVED(ANA_FID_MAP_FID_MAP), 124 REG(ANA_AGGR_CFG, 0x008a68), 125 REG(ANA_CPUQ_CFG, 0x008a6c), 126 REG_RESERVED(ANA_CPUQ_CFG2), 127 REG(ANA_CPUQ_8021_CFG, 0x008a74), 128 REG(ANA_DSCP_CFG, 0x008ab4), 129 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 130 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 131 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 132 REG_RESERVED(ANA_VRAP_CFG), 133 REG_RESERVED(ANA_VRAP_HDR_DATA), 134 REG_RESERVED(ANA_VRAP_HDR_MASK), 135 REG(ANA_DISCARD_CFG, 0x008c40), 136 REG(ANA_FID_CFG, 0x008c44), 137 REG(ANA_POL_PIR_CFG, 0x004000), 138 REG(ANA_POL_CIR_CFG, 0x004004), 139 REG(ANA_POL_MODE_CFG, 0x004008), 140 REG(ANA_POL_PIR_STATE, 0x00400c), 141 REG(ANA_POL_CIR_STATE, 0x004010), 142 REG_RESERVED(ANA_POL_STATE), 143 REG(ANA_POL_FLOWC, 0x008c48), 144 REG(ANA_POL_HYST, 0x008cb4), 145 REG_RESERVED(ANA_POL_MISC_CFG), 146 }; 147 148 static const u32 vsc9959_qs_regmap[] = { 149 REG(QS_XTR_GRP_CFG, 0x000000), 150 REG(QS_XTR_RD, 0x000008), 151 REG(QS_XTR_FRM_PRUNING, 0x000010), 152 REG(QS_XTR_FLUSH, 0x000018), 153 REG(QS_XTR_DATA_PRESENT, 0x00001c), 154 REG(QS_XTR_CFG, 0x000020), 155 REG(QS_INJ_GRP_CFG, 0x000024), 156 REG(QS_INJ_WR, 0x00002c), 157 REG(QS_INJ_CTRL, 0x000034), 158 REG(QS_INJ_STATUS, 0x00003c), 159 REG(QS_INJ_ERR, 0x000040), 160 REG_RESERVED(QS_INH_DBG), 161 }; 162 163 static const u32 vsc9959_vcap_regmap[] = { 164 /* VCAP_CORE_CFG */ 165 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 166 REG(VCAP_CORE_MV_CFG, 0x000004), 167 /* VCAP_CORE_CACHE */ 168 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 169 REG(VCAP_CACHE_MASK_DAT, 0x000108), 170 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 171 REG(VCAP_CACHE_CNT_DAT, 0x000308), 172 REG(VCAP_CACHE_TG_DAT, 0x000388), 173 /* VCAP_CONST */ 174 REG(VCAP_CONST_VCAP_VER, 0x000398), 175 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 176 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 177 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 178 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 179 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 180 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 181 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 182 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 183 REG(VCAP_CONST_IF_CNT, 0x0003bc), 184 }; 185 186 static const u32 vsc9959_qsys_regmap[] = { 187 REG(QSYS_PORT_MODE, 0x00f460), 188 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 189 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 190 REG(QSYS_EEE_CFG, 0x00f4a0), 191 REG(QSYS_EEE_THRES, 0x00f4b8), 192 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 193 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 194 REG(QSYS_SW_STATUS, 0x00f4c4), 195 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 196 REG_RESERVED(QSYS_PAD_CFG), 197 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 198 REG_RESERVED(QSYS_QMAP), 199 REG_RESERVED(QSYS_ISDX_SGRP), 200 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 201 REG(QSYS_TFRM_MISC, 0x00f50c), 202 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 203 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 204 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 205 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 206 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 207 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 208 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 209 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 210 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 211 REG(QSYS_RED_PROFILE, 0x00f534), 212 REG(QSYS_RES_QOS_MODE, 0x00f574), 213 REG(QSYS_RES_CFG, 0x00c000), 214 REG(QSYS_RES_STAT, 0x00c004), 215 REG(QSYS_EGR_DROP_MODE, 0x00f578), 216 REG(QSYS_EQ_CTRL, 0x00f57c), 217 REG_RESERVED(QSYS_EVENTS_CORE), 218 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 219 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 220 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 221 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 222 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 223 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 224 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 225 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 226 REG(QSYS_PREEMPTION_CFG, 0x00f664), 227 REG(QSYS_CIR_CFG, 0x000000), 228 REG(QSYS_EIR_CFG, 0x000004), 229 REG(QSYS_SE_CFG, 0x000008), 230 REG(QSYS_SE_DWRR_CFG, 0x00000c), 231 REG_RESERVED(QSYS_SE_CONNECT), 232 REG(QSYS_SE_DLB_SENSE, 0x000040), 233 REG(QSYS_CIR_STATE, 0x000044), 234 REG(QSYS_EIR_STATE, 0x000048), 235 REG_RESERVED(QSYS_SE_STATE), 236 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 237 REG(QSYS_TAG_CONFIG, 0x00f680), 238 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 239 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 240 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 241 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 242 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 243 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 244 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 245 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 246 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 247 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 248 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 249 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 250 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 251 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 252 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 253 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 254 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 255 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 256 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 257 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 258 }; 259 260 static const u32 vsc9959_rew_regmap[] = { 261 REG(REW_PORT_VLAN_CFG, 0x000000), 262 REG(REW_TAG_CFG, 0x000004), 263 REG(REW_PORT_CFG, 0x000008), 264 REG(REW_DSCP_CFG, 0x00000c), 265 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 266 REG(REW_PTP_CFG, 0x000050), 267 REG(REW_PTP_DLY1_CFG, 0x000054), 268 REG(REW_RED_TAG_CFG, 0x000058), 269 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 270 REG(REW_DSCP_REMAP_CFG, 0x000510), 271 REG_RESERVED(REW_STAT_CFG), 272 REG_RESERVED(REW_REW_STICKY), 273 REG_RESERVED(REW_PPT), 274 }; 275 276 static const u32 vsc9959_sys_regmap[] = { 277 REG(SYS_COUNT_RX_OCTETS, 0x000000), 278 REG(SYS_COUNT_RX_UNICAST, 0x000004), 279 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 280 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 281 REG(SYS_COUNT_RX_SHORTS, 0x000010), 282 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 283 REG(SYS_COUNT_RX_JABBERS, 0x000018), 284 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 285 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 286 REG(SYS_COUNT_RX_64, 0x000024), 287 REG(SYS_COUNT_RX_65_127, 0x000028), 288 REG(SYS_COUNT_RX_128_255, 0x00002c), 289 REG(SYS_COUNT_RX_256_511, 0x000030), 290 REG(SYS_COUNT_RX_512_1023, 0x000034), 291 REG(SYS_COUNT_RX_1024_1526, 0x000038), 292 REG(SYS_COUNT_RX_1527_MAX, 0x00003c), 293 REG(SYS_COUNT_RX_PAUSE, 0x000040), 294 REG(SYS_COUNT_RX_CONTROL, 0x000044), 295 REG(SYS_COUNT_RX_LONGS, 0x000048), 296 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), 297 REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), 298 REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), 299 REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), 300 REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), 301 REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), 302 REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), 303 REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), 304 REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), 305 REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), 306 REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), 307 REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), 308 REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), 309 REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), 310 REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), 311 REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), 312 REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), 313 REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), 314 REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), 315 REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), 316 REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), 317 REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), 318 REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), 319 REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), 320 REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), 321 REG(SYS_COUNT_TX_OCTETS, 0x000200), 322 REG(SYS_COUNT_TX_UNICAST, 0x000204), 323 REG(SYS_COUNT_TX_MULTICAST, 0x000208), 324 REG(SYS_COUNT_TX_BROADCAST, 0x00020c), 325 REG(SYS_COUNT_TX_COLLISION, 0x000210), 326 REG(SYS_COUNT_TX_DROPS, 0x000214), 327 REG(SYS_COUNT_TX_PAUSE, 0x000218), 328 REG(SYS_COUNT_TX_64, 0x00021c), 329 REG(SYS_COUNT_TX_65_127, 0x000220), 330 REG(SYS_COUNT_TX_128_255, 0x000224), 331 REG(SYS_COUNT_TX_256_511, 0x000228), 332 REG(SYS_COUNT_TX_512_1023, 0x00022c), 333 REG(SYS_COUNT_TX_1024_1526, 0x000230), 334 REG(SYS_COUNT_TX_1527_MAX, 0x000234), 335 REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238), 336 REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c), 337 REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240), 338 REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244), 339 REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248), 340 REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c), 341 REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250), 342 REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254), 343 REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258), 344 REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c), 345 REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260), 346 REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264), 347 REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268), 348 REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c), 349 REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270), 350 REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274), 351 REG(SYS_COUNT_TX_AGED, 0x000278), 352 REG(SYS_COUNT_DROP_LOCAL, 0x000400), 353 REG(SYS_COUNT_DROP_TAIL, 0x000404), 354 REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408), 355 REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c), 356 REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410), 357 REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414), 358 REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418), 359 REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c), 360 REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420), 361 REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424), 362 REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428), 363 REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c), 364 REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430), 365 REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434), 366 REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438), 367 REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c), 368 REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440), 369 REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444), 370 REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800), 371 REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804), 372 REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808), 373 REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c), 374 REG(SYS_RESET_CFG, 0x000e00), 375 REG(SYS_SR_ETYPE_CFG, 0x000e04), 376 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 377 REG(SYS_PORT_MODE, 0x000e0c), 378 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 379 REG(SYS_FRM_AGING, 0x000e44), 380 REG(SYS_STAT_CFG, 0x000e48), 381 REG(SYS_SW_STATUS, 0x000e4c), 382 REG_RESERVED(SYS_MISC_CFG), 383 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 384 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 385 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 386 REG(SYS_PAUSE_CFG, 0x000ea0), 387 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 388 REG(SYS_ATOP, 0x000ec0), 389 REG(SYS_ATOP_TOT_CFG, 0x000edc), 390 REG(SYS_MAC_FC_CFG, 0x000ee0), 391 REG(SYS_MMGT, 0x000ef8), 392 REG_RESERVED(SYS_MMGT_FAST), 393 REG_RESERVED(SYS_EVENTS_DIF), 394 REG_RESERVED(SYS_EVENTS_CORE), 395 REG(SYS_PTP_STATUS, 0x000f14), 396 REG(SYS_PTP_TXSTAMP, 0x000f18), 397 REG(SYS_PTP_NXT, 0x000f1c), 398 REG(SYS_PTP_CFG, 0x000f20), 399 REG(SYS_RAM_INIT, 0x000f24), 400 REG_RESERVED(SYS_CM_ADDR), 401 REG_RESERVED(SYS_CM_DATA_WR), 402 REG_RESERVED(SYS_CM_DATA_RD), 403 REG_RESERVED(SYS_CM_OP), 404 REG_RESERVED(SYS_CM_DATA), 405 }; 406 407 static const u32 vsc9959_ptp_regmap[] = { 408 REG(PTP_PIN_CFG, 0x000000), 409 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 410 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 411 REG(PTP_PIN_TOD_NSEC, 0x00000c), 412 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 413 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 414 REG(PTP_CFG_MISC, 0x0000a0), 415 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 416 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 417 }; 418 419 static const u32 vsc9959_gcb_regmap[] = { 420 REG(GCB_SOFT_RST, 0x000004), 421 }; 422 423 static const u32 vsc9959_dev_gmii_regmap[] = { 424 REG(DEV_CLOCK_CFG, 0x0), 425 REG(DEV_PORT_MISC, 0x4), 426 REG(DEV_EVENTS, 0x8), 427 REG(DEV_EEE_CFG, 0xc), 428 REG(DEV_RX_PATH_DELAY, 0x10), 429 REG(DEV_TX_PATH_DELAY, 0x14), 430 REG(DEV_PTP_PREDICT_CFG, 0x18), 431 REG(DEV_MAC_ENA_CFG, 0x1c), 432 REG(DEV_MAC_MODE_CFG, 0x20), 433 REG(DEV_MAC_MAXLEN_CFG, 0x24), 434 REG(DEV_MAC_TAGS_CFG, 0x28), 435 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 436 REG(DEV_MAC_IFG_CFG, 0x30), 437 REG(DEV_MAC_HDX_CFG, 0x34), 438 REG(DEV_MAC_DBG_CFG, 0x38), 439 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 440 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 441 REG(DEV_MAC_STICKY, 0x44), 442 REG_RESERVED(PCS1G_CFG), 443 REG_RESERVED(PCS1G_MODE_CFG), 444 REG_RESERVED(PCS1G_SD_CFG), 445 REG_RESERVED(PCS1G_ANEG_CFG), 446 REG_RESERVED(PCS1G_ANEG_NP_CFG), 447 REG_RESERVED(PCS1G_LB_CFG), 448 REG_RESERVED(PCS1G_DBG_CFG), 449 REG_RESERVED(PCS1G_CDET_CFG), 450 REG_RESERVED(PCS1G_ANEG_STATUS), 451 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 452 REG_RESERVED(PCS1G_LINK_STATUS), 453 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 454 REG_RESERVED(PCS1G_STICKY), 455 REG_RESERVED(PCS1G_DEBUG_STATUS), 456 REG_RESERVED(PCS1G_LPI_CFG), 457 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 458 REG_RESERVED(PCS1G_LPI_STATUS), 459 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 460 REG_RESERVED(PCS1G_TSTPAT_STATUS), 461 REG_RESERVED(DEV_PCS_FX100_CFG), 462 REG_RESERVED(DEV_PCS_FX100_STATUS), 463 }; 464 465 static const u32 *vsc9959_regmap[TARGET_MAX] = { 466 [ANA] = vsc9959_ana_regmap, 467 [QS] = vsc9959_qs_regmap, 468 [QSYS] = vsc9959_qsys_regmap, 469 [REW] = vsc9959_rew_regmap, 470 [SYS] = vsc9959_sys_regmap, 471 [S0] = vsc9959_vcap_regmap, 472 [S1] = vsc9959_vcap_regmap, 473 [S2] = vsc9959_vcap_regmap, 474 [PTP] = vsc9959_ptp_regmap, 475 [GCB] = vsc9959_gcb_regmap, 476 [DEV_GMII] = vsc9959_dev_gmii_regmap, 477 }; 478 479 /* Addresses are relative to the PCI device's base address */ 480 static const struct resource vsc9959_resources[] = { 481 DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"), 482 DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"), 483 DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"), 484 DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"), 485 DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"), 486 DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"), 487 DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"), 488 DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"), 489 DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"), 490 DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"), 491 DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"), 492 DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"), 493 DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"), 494 DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"), 495 DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"), 496 DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"), 497 }; 498 499 static const char * const vsc9959_resource_names[TARGET_MAX] = { 500 [SYS] = "sys", 501 [REW] = "rew", 502 [S0] = "s0", 503 [S1] = "s1", 504 [S2] = "s2", 505 [GCB] = "devcpu_gcb", 506 [QS] = "qs", 507 [PTP] = "ptp", 508 [QSYS] = "qsys", 509 [ANA] = "ana", 510 }; 511 512 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 513 * SGMII/QSGMII MAC PCS can be found. 514 */ 515 static const struct resource vsc9959_imdio_res = 516 DEFINE_RES_MEM_NAMED(0x8030, 0x8040, "imdio"); 517 518 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 519 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 520 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 521 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 522 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 523 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 524 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 525 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 526 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 527 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 528 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 529 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 530 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 531 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 532 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 533 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 534 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 535 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 536 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 537 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 538 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 539 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 540 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 541 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 542 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 543 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 544 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 545 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 546 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 547 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 548 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 549 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 550 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 551 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 552 /* Replicated per number of ports (7), register size 4 per port */ 553 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 554 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 555 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 556 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 557 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 558 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 559 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 560 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 561 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 562 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 563 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 564 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 565 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 566 }; 567 568 static const struct vcap_field vsc9959_vcap_es0_keys[] = { 569 [VCAP_ES0_EGR_PORT] = { 0, 3}, 570 [VCAP_ES0_IGR_PORT] = { 3, 3}, 571 [VCAP_ES0_RSV] = { 6, 2}, 572 [VCAP_ES0_L2_MC] = { 8, 1}, 573 [VCAP_ES0_L2_BC] = { 9, 1}, 574 [VCAP_ES0_VID] = { 10, 12}, 575 [VCAP_ES0_DP] = { 22, 1}, 576 [VCAP_ES0_PCP] = { 23, 3}, 577 }; 578 579 static const struct vcap_field vsc9959_vcap_es0_actions[] = { 580 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 581 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 582 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 583 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 584 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 585 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 586 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 587 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 588 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 589 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 590 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 591 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 592 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 593 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 594 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 595 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 596 [VCAP_ES0_ACT_RSV] = { 49, 23}, 597 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 598 }; 599 600 static const struct vcap_field vsc9959_vcap_is1_keys[] = { 601 [VCAP_IS1_HK_TYPE] = { 0, 1}, 602 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 603 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 604 [VCAP_IS1_HK_RSV] = { 10, 9}, 605 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 606 [VCAP_IS1_HK_L2_MC] = { 20, 1}, 607 [VCAP_IS1_HK_L2_BC] = { 21, 1}, 608 [VCAP_IS1_HK_IP_MC] = { 22, 1}, 609 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 610 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 611 [VCAP_IS1_HK_TPID] = { 25, 1}, 612 [VCAP_IS1_HK_VID] = { 26, 12}, 613 [VCAP_IS1_HK_DEI] = { 38, 1}, 614 [VCAP_IS1_HK_PCP] = { 39, 3}, 615 /* Specific Fields for IS1 Half Key S1_NORMAL */ 616 [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 617 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 618 [VCAP_IS1_HK_ETYPE] = { 91, 16}, 619 [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 620 [VCAP_IS1_HK_IP4] = {108, 1}, 621 /* Layer-3 Information */ 622 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 623 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 624 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 625 [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 626 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 627 /* Layer-4 Information */ 628 [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 629 [VCAP_IS1_HK_TCP] = {151, 1}, 630 [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 631 [VCAP_IS1_HK_L4_RNG] = {168, 8}, 632 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 633 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 634 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 635 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 636 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 637 [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 638 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 639 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 640 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 641 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 642 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 643 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 644 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 645 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 646 [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 647 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 648 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 649 }; 650 651 static const struct vcap_field vsc9959_vcap_is1_actions[] = { 652 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 653 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 654 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 655 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 656 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 657 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 658 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 659 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 660 [VCAP_IS1_ACT_RSV] = { 29, 9}, 661 /* The fields below are incorrectly shifted by 2 in the manual */ 662 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 663 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 664 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 665 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 666 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 667 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 668 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 669 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 670 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 671 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 672 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 673 }; 674 675 static struct vcap_field vsc9959_vcap_is2_keys[] = { 676 /* Common: 41 bits */ 677 [VCAP_IS2_TYPE] = { 0, 4}, 678 [VCAP_IS2_HK_FIRST] = { 4, 1}, 679 [VCAP_IS2_HK_PAG] = { 5, 8}, 680 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 681 [VCAP_IS2_HK_RSV2] = { 20, 1}, 682 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 683 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 684 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 685 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 686 [VCAP_IS2_HK_VID] = { 25, 12}, 687 [VCAP_IS2_HK_DEI] = { 37, 1}, 688 [VCAP_IS2_HK_PCP] = { 38, 3}, 689 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 690 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 691 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 692 /* MAC_ETYPE (TYPE=000) */ 693 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 694 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 695 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 696 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 697 /* MAC_LLC (TYPE=001) */ 698 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 699 /* MAC_SNAP (TYPE=010) */ 700 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 701 /* MAC_ARP (TYPE=011) */ 702 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 703 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 704 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 705 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 706 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 707 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 708 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 709 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 710 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 711 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 712 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 713 /* IP4_TCP_UDP / IP4_OTHER common */ 714 [VCAP_IS2_HK_IP4] = { 41, 1}, 715 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 716 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 717 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 718 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 719 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 720 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 721 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 722 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 723 /* IP4_TCP_UDP (TYPE=100) */ 724 [VCAP_IS2_HK_TCP] = {119, 1}, 725 [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 726 [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 727 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 728 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 729 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 730 [VCAP_IS2_HK_L4_FIN] = {162, 1}, 731 [VCAP_IS2_HK_L4_SYN] = {163, 1}, 732 [VCAP_IS2_HK_L4_RST] = {164, 1}, 733 [VCAP_IS2_HK_L4_PSH] = {165, 1}, 734 [VCAP_IS2_HK_L4_ACK] = {166, 1}, 735 [VCAP_IS2_HK_L4_URG] = {167, 1}, 736 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 737 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 738 /* IP4_OTHER (TYPE=101) */ 739 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 740 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 741 /* IP6_STD (TYPE=110) */ 742 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 743 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 744 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 745 /* OAM (TYPE=111) */ 746 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 747 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 748 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 749 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 750 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 751 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 752 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 753 }; 754 755 static struct vcap_field vsc9959_vcap_is2_actions[] = { 756 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 757 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 758 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 759 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 760 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 761 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 762 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 763 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 764 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 765 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 766 [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 767 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 768 [VCAP_IS2_ACT_RSV] = { 36, 2}, 769 [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 770 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 771 }; 772 773 static struct vcap_props vsc9959_vcap_props[] = { 774 [VCAP_ES0] = { 775 .action_type_width = 0, 776 .action_table = { 777 [ES0_ACTION_TYPE_NORMAL] = { 778 .width = 72, /* HIT_STICKY not included */ 779 .count = 1, 780 }, 781 }, 782 .target = S0, 783 .keys = vsc9959_vcap_es0_keys, 784 .actions = vsc9959_vcap_es0_actions, 785 }, 786 [VCAP_IS1] = { 787 .action_type_width = 0, 788 .action_table = { 789 [IS1_ACTION_TYPE_NORMAL] = { 790 .width = 78, /* HIT_STICKY not included */ 791 .count = 4, 792 }, 793 }, 794 .target = S1, 795 .keys = vsc9959_vcap_is1_keys, 796 .actions = vsc9959_vcap_is1_actions, 797 }, 798 [VCAP_IS2] = { 799 .action_type_width = 1, 800 .action_table = { 801 [IS2_ACTION_TYPE_NORMAL] = { 802 .width = 44, 803 .count = 2 804 }, 805 [IS2_ACTION_TYPE_SMAC_SIP] = { 806 .width = 6, 807 .count = 4 808 }, 809 }, 810 .target = S2, 811 .keys = vsc9959_vcap_is2_keys, 812 .actions = vsc9959_vcap_is2_actions, 813 }, 814 }; 815 816 static const struct ptp_clock_info vsc9959_ptp_caps = { 817 .owner = THIS_MODULE, 818 .name = "felix ptp", 819 .max_adj = 0x7fffffff, 820 .n_alarm = 0, 821 .n_ext_ts = 0, 822 .n_per_out = OCELOT_PTP_PINS_NUM, 823 .n_pins = OCELOT_PTP_PINS_NUM, 824 .pps = 0, 825 .gettime64 = ocelot_ptp_gettime64, 826 .settime64 = ocelot_ptp_settime64, 827 .adjtime = ocelot_ptp_adjtime, 828 .adjfine = ocelot_ptp_adjfine, 829 .verify = ocelot_ptp_verify, 830 .enable = ocelot_ptp_enable, 831 }; 832 833 #define VSC9959_INIT_TIMEOUT 50000 834 #define VSC9959_GCB_RST_SLEEP 100 835 #define VSC9959_SYS_RAMINIT_SLEEP 80 836 837 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 838 { 839 int val; 840 841 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 842 843 return val; 844 } 845 846 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 847 { 848 return ocelot_read(ocelot, SYS_RAM_INIT); 849 } 850 851 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 852 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 853 */ 854 static int vsc9959_reset(struct ocelot *ocelot) 855 { 856 int val, err; 857 858 /* soft-reset the switch core */ 859 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 860 861 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 862 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 863 if (err) { 864 dev_err(ocelot->dev, "timeout: switch core reset\n"); 865 return err; 866 } 867 868 /* initialize switch mem ~40us */ 869 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 870 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 871 VSC9959_SYS_RAMINIT_SLEEP, 872 VSC9959_INIT_TIMEOUT); 873 if (err) { 874 dev_err(ocelot->dev, "timeout: switch sram init\n"); 875 return err; 876 } 877 878 /* enable switch core */ 879 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 880 881 return 0; 882 } 883 884 /* Watermark encode 885 * Bit 8: Unit; 0:1, 1:16 886 * Bit 7-0: Value to be multiplied with unit 887 */ 888 static u16 vsc9959_wm_enc(u16 value) 889 { 890 WARN_ON(value >= 16 * BIT(8)); 891 892 if (value >= BIT(8)) 893 return BIT(8) | (value / 16); 894 895 return value; 896 } 897 898 static u16 vsc9959_wm_dec(u16 wm) 899 { 900 WARN_ON(wm & ~GENMASK(8, 0)); 901 902 if (wm & BIT(8)) 903 return (wm & GENMASK(7, 0)) * 16; 904 905 return wm; 906 } 907 908 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 909 { 910 *inuse = (val & GENMASK(23, 12)) >> 12; 911 *maxuse = val & GENMASK(11, 0); 912 } 913 914 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 915 { 916 struct pci_dev *pdev = to_pci_dev(ocelot->dev); 917 struct felix *felix = ocelot_to_felix(ocelot); 918 struct enetc_mdio_priv *mdio_priv; 919 struct device *dev = ocelot->dev; 920 resource_size_t imdio_base; 921 void __iomem *imdio_regs; 922 struct resource res; 923 struct enetc_hw *hw; 924 struct mii_bus *bus; 925 int port; 926 int rc; 927 928 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 929 sizeof(struct phylink_pcs *), 930 GFP_KERNEL); 931 if (!felix->pcs) { 932 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 933 return -ENOMEM; 934 } 935 936 imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 937 938 memcpy(&res, &vsc9959_imdio_res, sizeof(res)); 939 res.start += imdio_base; 940 res.end += imdio_base; 941 942 imdio_regs = devm_ioremap_resource(dev, &res); 943 if (IS_ERR(imdio_regs)) 944 return PTR_ERR(imdio_regs); 945 946 hw = enetc_hw_alloc(dev, imdio_regs); 947 if (IS_ERR(hw)) { 948 dev_err(dev, "failed to allocate ENETC HW structure\n"); 949 return PTR_ERR(hw); 950 } 951 952 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 953 if (!bus) 954 return -ENOMEM; 955 956 bus->name = "VSC9959 internal MDIO bus"; 957 bus->read = enetc_mdio_read; 958 bus->write = enetc_mdio_write; 959 bus->parent = dev; 960 mdio_priv = bus->priv; 961 mdio_priv->hw = hw; 962 /* This gets added to imdio_regs, which already maps addresses 963 * starting with the proper offset. 964 */ 965 mdio_priv->mdio_base = 0; 966 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 967 968 /* Needed in order to initialize the bus mutex lock */ 969 rc = mdiobus_register(bus); 970 if (rc < 0) { 971 dev_err(dev, "failed to register MDIO bus\n"); 972 mdiobus_free(bus); 973 return rc; 974 } 975 976 felix->imdio = bus; 977 978 for (port = 0; port < felix->info->num_ports; port++) { 979 struct ocelot_port *ocelot_port = ocelot->ports[port]; 980 struct phylink_pcs *phylink_pcs; 981 struct mdio_device *mdio_device; 982 983 if (dsa_is_unused_port(felix->ds, port)) 984 continue; 985 986 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 987 continue; 988 989 mdio_device = mdio_device_create(felix->imdio, port); 990 if (IS_ERR(mdio_device)) 991 continue; 992 993 phylink_pcs = lynx_pcs_create(mdio_device); 994 if (!phylink_pcs) { 995 mdio_device_free(mdio_device); 996 continue; 997 } 998 999 felix->pcs[port] = phylink_pcs; 1000 1001 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1002 } 1003 1004 return 0; 1005 } 1006 1007 static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1008 { 1009 struct felix *felix = ocelot_to_felix(ocelot); 1010 int port; 1011 1012 for (port = 0; port < ocelot->num_phys_ports; port++) { 1013 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1014 struct mdio_device *mdio_device; 1015 1016 if (!phylink_pcs) 1017 continue; 1018 1019 mdio_device = lynx_get_mdio_device(phylink_pcs); 1020 mdio_device_free(mdio_device); 1021 lynx_pcs_destroy(phylink_pcs); 1022 } 1023 mdiobus_unregister(felix->imdio); 1024 mdiobus_free(felix->imdio); 1025 } 1026 1027 /* The switch considers any frame (regardless of size) as eligible for 1028 * transmission if the traffic class gate is open for at least 33 ns. 1029 * Overruns are prevented by cropping an interval at the end of the gate time 1030 * slot for which egress scheduling is blocked, but we need to still keep 33 ns 1031 * available for one packet to be transmitted, otherwise the port tc will hang. 1032 * This function returns the size of a gate interval that remains available for 1033 * setting the guard band, after reserving the space for one egress frame. 1034 */ 1035 static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns) 1036 { 1037 /* Gate always open */ 1038 if (gate_len_ns == U64_MAX) 1039 return U64_MAX; 1040 1041 return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC; 1042 } 1043 1044 /* Extract shortest continuous gate open intervals in ns for each traffic class 1045 * of a cyclic tc-taprio schedule. If a gate is always open, the duration is 1046 * considered U64_MAX. If the gate is always closed, it is considered 0. 1047 */ 1048 static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, 1049 u64 min_gate_len[OCELOT_NUM_TC]) 1050 { 1051 struct tc_taprio_sched_entry *entry; 1052 u64 gate_len[OCELOT_NUM_TC]; 1053 u8 gates_ever_opened = 0; 1054 int tc, i, n; 1055 1056 /* Initialize arrays */ 1057 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1058 min_gate_len[tc] = U64_MAX; 1059 gate_len[tc] = 0; 1060 } 1061 1062 /* If we don't have taprio, consider all gates as permanently open */ 1063 if (!taprio) 1064 return; 1065 1066 n = taprio->num_entries; 1067 1068 /* Walk through the gate list twice to determine the length 1069 * of consecutively open gates for a traffic class, including 1070 * open gates that wrap around. We are just interested in the 1071 * minimum window size, and this doesn't change what the 1072 * minimum is (if the gate never closes, min_gate_len will 1073 * remain U64_MAX). 1074 */ 1075 for (i = 0; i < 2 * n; i++) { 1076 entry = &taprio->entries[i % n]; 1077 1078 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1079 if (entry->gate_mask & BIT(tc)) { 1080 gate_len[tc] += entry->interval; 1081 gates_ever_opened |= BIT(tc); 1082 } else { 1083 /* Gate closes now, record a potential new 1084 * minimum and reinitialize length 1085 */ 1086 if (min_gate_len[tc] > gate_len[tc] && 1087 gate_len[tc]) 1088 min_gate_len[tc] = gate_len[tc]; 1089 gate_len[tc] = 0; 1090 } 1091 } 1092 } 1093 1094 /* min_gate_len[tc] actually tracks minimum *open* gate time, so for 1095 * permanently closed gates, min_gate_len[tc] will still be U64_MAX. 1096 * Therefore they are currently indistinguishable from permanently 1097 * open gates. Overwrite the gate len with 0 when we know they're 1098 * actually permanently closed, i.e. after the loop above. 1099 */ 1100 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 1101 if (!(gates_ever_opened & BIT(tc))) 1102 min_gate_len[tc] = 0; 1103 } 1104 1105 /* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ, 1106 * so we need to spell out the register access to each traffic class in helper 1107 * functions, to simplify callers 1108 */ 1109 static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc, 1110 u32 max_sdu) 1111 { 1112 switch (tc) { 1113 case 0: 1114 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, 1115 port); 1116 break; 1117 case 1: 1118 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, 1119 port); 1120 break; 1121 case 2: 1122 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, 1123 port); 1124 break; 1125 case 3: 1126 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, 1127 port); 1128 break; 1129 case 4: 1130 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, 1131 port); 1132 break; 1133 case 5: 1134 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, 1135 port); 1136 break; 1137 case 6: 1138 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, 1139 port); 1140 break; 1141 case 7: 1142 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, 1143 port); 1144 break; 1145 } 1146 } 1147 1148 static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc) 1149 { 1150 switch (tc) { 1151 case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port); 1152 case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port); 1153 case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port); 1154 case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port); 1155 case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port); 1156 case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port); 1157 case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port); 1158 case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port); 1159 default: 1160 return 0; 1161 } 1162 } 1163 1164 static u32 vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload *taprio, int tc) 1165 { 1166 if (!taprio || !taprio->max_sdu[tc]) 1167 return 0; 1168 1169 return taprio->max_sdu[tc] + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN; 1170 } 1171 1172 /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the 1173 * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU 1174 * values (the default value is 1518). Also, for traffic class windows smaller 1175 * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame 1176 * dropping, such that these won't hang the port, as they will never be sent. 1177 */ 1178 static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) 1179 { 1180 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1181 struct tc_taprio_qopt_offload *taprio; 1182 u64 min_gate_len[OCELOT_NUM_TC]; 1183 int speed, picos_per_byte; 1184 u64 needed_bit_time_ps; 1185 u32 val, maxlen; 1186 u8 tas_speed; 1187 int tc; 1188 1189 lockdep_assert_held(&ocelot->tas_lock); 1190 1191 taprio = ocelot_port->taprio; 1192 1193 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 1194 tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); 1195 1196 switch (tas_speed) { 1197 case OCELOT_SPEED_10: 1198 speed = SPEED_10; 1199 break; 1200 case OCELOT_SPEED_100: 1201 speed = SPEED_100; 1202 break; 1203 case OCELOT_SPEED_1000: 1204 speed = SPEED_1000; 1205 break; 1206 case OCELOT_SPEED_2500: 1207 speed = SPEED_2500; 1208 break; 1209 default: 1210 return; 1211 } 1212 1213 picos_per_byte = (USEC_PER_SEC * 8) / speed; 1214 1215 val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG); 1216 /* MAXLEN_CFG accounts automatically for VLAN. We need to include it 1217 * manually in the bit time calculation, plus the preamble and SFD. 1218 */ 1219 maxlen = val + 2 * VLAN_HLEN; 1220 /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, 1221 * 4 octets FCS, 12 octets IFG. 1222 */ 1223 needed_bit_time_ps = (maxlen + 24) * picos_per_byte; 1224 1225 dev_dbg(ocelot->dev, 1226 "port %d: max frame size %d needs %llu ps at speed %d\n", 1227 port, maxlen, needed_bit_time_ps, speed); 1228 1229 vsc9959_tas_min_gate_lengths(taprio, min_gate_len); 1230 1231 mutex_lock(&ocelot->fwd_domain_lock); 1232 1233 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1234 u32 requested_max_sdu = vsc9959_tas_tc_max_sdu(taprio, tc); 1235 u64 remaining_gate_len_ps; 1236 u32 max_sdu; 1237 1238 remaining_gate_len_ps = 1239 vsc9959_tas_remaining_gate_len_ps(min_gate_len[tc]); 1240 1241 if (remaining_gate_len_ps > needed_bit_time_ps) { 1242 /* Setting QMAXSDU_CFG to 0 disables oversized frame 1243 * dropping. 1244 */ 1245 max_sdu = requested_max_sdu; 1246 dev_dbg(ocelot->dev, 1247 "port %d tc %d min gate len %llu" 1248 ", sending all frames\n", 1249 port, tc, min_gate_len[tc]); 1250 } else { 1251 /* If traffic class doesn't support a full MTU sized 1252 * frame, make sure to enable oversize frame dropping 1253 * for frames larger than the smallest that would fit. 1254 * 1255 * However, the exact same register, QSYS_QMAXSDU_CFG_*, 1256 * controls not only oversized frame dropping, but also 1257 * per-tc static guard band lengths, so it reduces the 1258 * useful gate interval length. Therefore, be careful 1259 * to calculate a guard band (and therefore max_sdu) 1260 * that still leaves 33 ns available in the time slot. 1261 */ 1262 max_sdu = div_u64(remaining_gate_len_ps, picos_per_byte); 1263 /* A TC gate may be completely closed, which is a 1264 * special case where all packets are oversized. 1265 * Any limit smaller than 64 octets accomplishes this 1266 */ 1267 if (!max_sdu) 1268 max_sdu = 1; 1269 /* Take L1 overhead into account, but just don't allow 1270 * max_sdu to go negative or to 0. Here we use 20 1271 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS 1272 * octets as part of packet size. 1273 */ 1274 if (max_sdu > 20) 1275 max_sdu -= 20; 1276 1277 if (requested_max_sdu && requested_max_sdu < max_sdu) 1278 max_sdu = requested_max_sdu; 1279 1280 dev_info(ocelot->dev, 1281 "port %d tc %d min gate length %llu" 1282 " ns not enough for max frame size %d at %d" 1283 " Mbps, dropping frames over %d" 1284 " octets including FCS\n", 1285 port, tc, min_gate_len[tc], maxlen, speed, 1286 max_sdu); 1287 } 1288 1289 vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu); 1290 } 1291 1292 ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); 1293 1294 ocelot->ops->cut_through_fwd(ocelot); 1295 1296 mutex_unlock(&ocelot->fwd_domain_lock); 1297 } 1298 1299 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1300 u32 speed) 1301 { 1302 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1303 u8 tas_speed; 1304 1305 switch (speed) { 1306 case SPEED_10: 1307 tas_speed = OCELOT_SPEED_10; 1308 break; 1309 case SPEED_100: 1310 tas_speed = OCELOT_SPEED_100; 1311 break; 1312 case SPEED_1000: 1313 tas_speed = OCELOT_SPEED_1000; 1314 break; 1315 case SPEED_2500: 1316 tas_speed = OCELOT_SPEED_2500; 1317 break; 1318 default: 1319 tas_speed = OCELOT_SPEED_1000; 1320 break; 1321 } 1322 1323 mutex_lock(&ocelot->tas_lock); 1324 1325 ocelot_rmw_rix(ocelot, 1326 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1327 QSYS_TAG_CONFIG_LINK_SPEED_M, 1328 QSYS_TAG_CONFIG, port); 1329 1330 if (ocelot_port->taprio) 1331 vsc9959_tas_guard_bands_update(ocelot, port); 1332 1333 mutex_unlock(&ocelot->tas_lock); 1334 } 1335 1336 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1337 u64 cycle_time, 1338 struct timespec64 *new_base_ts) 1339 { 1340 struct timespec64 ts; 1341 ktime_t new_base_time; 1342 ktime_t current_time; 1343 1344 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1345 current_time = timespec64_to_ktime(ts); 1346 new_base_time = base_time; 1347 1348 if (base_time < current_time) { 1349 u64 nr_of_cycles = current_time - base_time; 1350 1351 do_div(nr_of_cycles, cycle_time); 1352 new_base_time += cycle_time * (nr_of_cycles + 1); 1353 } 1354 1355 *new_base_ts = ktime_to_timespec64(new_base_time); 1356 } 1357 1358 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1359 { 1360 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1361 } 1362 1363 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1364 struct tc_taprio_sched_entry *entry) 1365 { 1366 ocelot_write(ocelot, 1367 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1368 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1369 QSYS_GCL_CFG_REG_1); 1370 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1371 } 1372 1373 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1374 struct tc_taprio_qopt_offload *taprio) 1375 { 1376 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1377 struct timespec64 base_ts; 1378 int ret, i; 1379 u32 val; 1380 1381 mutex_lock(&ocelot->tas_lock); 1382 1383 if (!taprio->enable) { 1384 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1385 QSYS_TAG_CONFIG, port); 1386 1387 taprio_offload_free(ocelot_port->taprio); 1388 ocelot_port->taprio = NULL; 1389 1390 vsc9959_tas_guard_bands_update(ocelot, port); 1391 1392 mutex_unlock(&ocelot->tas_lock); 1393 return 0; 1394 } 1395 1396 if (taprio->cycle_time > NSEC_PER_SEC || 1397 taprio->cycle_time_extension >= NSEC_PER_SEC) { 1398 ret = -EINVAL; 1399 goto err; 1400 } 1401 1402 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { 1403 ret = -ERANGE; 1404 goto err; 1405 } 1406 1407 /* Enable guard band. The switch will schedule frames without taking 1408 * their length into account. Thus we'll always need to enable the 1409 * guard band which reserves the time of a maximum sized frame at the 1410 * end of the time window. 1411 * 1412 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1413 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1414 * operate on the port number. 1415 */ 1416 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1417 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1418 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1419 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1420 QSYS_TAS_PARAM_CFG_CTRL); 1421 1422 /* Hardware errata - Admin config could not be overwritten if 1423 * config is pending, need reset the TAS module 1424 */ 1425 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1426 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { 1427 ret = -EBUSY; 1428 goto err; 1429 } 1430 1431 ocelot_rmw_rix(ocelot, 1432 QSYS_TAG_CONFIG_ENABLE | 1433 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1434 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1435 QSYS_TAG_CONFIG_ENABLE | 1436 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1437 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1438 QSYS_TAG_CONFIG, port); 1439 1440 vsc9959_new_base_time(ocelot, taprio->base_time, 1441 taprio->cycle_time, &base_ts); 1442 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1443 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1444 val = upper_32_bits(base_ts.tv_sec); 1445 ocelot_write(ocelot, 1446 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1447 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1448 QSYS_PARAM_CFG_REG_3); 1449 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1450 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1451 1452 for (i = 0; i < taprio->num_entries; i++) 1453 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1454 1455 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1456 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1457 QSYS_TAS_PARAM_CFG_CTRL); 1458 1459 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1460 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1461 10, 100000); 1462 if (ret) 1463 goto err; 1464 1465 ocelot_port->taprio = taprio_offload_get(taprio); 1466 vsc9959_tas_guard_bands_update(ocelot, port); 1467 1468 err: 1469 mutex_unlock(&ocelot->tas_lock); 1470 1471 return ret; 1472 } 1473 1474 static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) 1475 { 1476 struct tc_taprio_qopt_offload *taprio; 1477 struct ocelot_port *ocelot_port; 1478 struct timespec64 base_ts; 1479 int port; 1480 u32 val; 1481 1482 mutex_lock(&ocelot->tas_lock); 1483 1484 for (port = 0; port < ocelot->num_phys_ports; port++) { 1485 ocelot_port = ocelot->ports[port]; 1486 taprio = ocelot_port->taprio; 1487 if (!taprio) 1488 continue; 1489 1490 ocelot_rmw(ocelot, 1491 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), 1492 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, 1493 QSYS_TAS_PARAM_CFG_CTRL); 1494 1495 /* Disable time-aware shaper */ 1496 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1497 QSYS_TAG_CONFIG, port); 1498 1499 vsc9959_new_base_time(ocelot, taprio->base_time, 1500 taprio->cycle_time, &base_ts); 1501 1502 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1503 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), 1504 QSYS_PARAM_CFG_REG_2); 1505 val = upper_32_bits(base_ts.tv_sec); 1506 ocelot_rmw(ocelot, 1507 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), 1508 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, 1509 QSYS_PARAM_CFG_REG_3); 1510 1511 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1512 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1513 QSYS_TAS_PARAM_CFG_CTRL); 1514 1515 /* Re-enable time-aware shaper */ 1516 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, 1517 QSYS_TAG_CONFIG_ENABLE, 1518 QSYS_TAG_CONFIG, port); 1519 } 1520 mutex_unlock(&ocelot->tas_lock); 1521 } 1522 1523 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1524 struct tc_cbs_qopt_offload *cbs_qopt) 1525 { 1526 struct ocelot *ocelot = ds->priv; 1527 int port_ix = port * 8 + cbs_qopt->queue; 1528 u32 rate, burst; 1529 1530 if (cbs_qopt->queue >= ds->num_tx_queues) 1531 return -EINVAL; 1532 1533 if (!cbs_qopt->enable) { 1534 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1535 QSYS_CIR_CFG_CIR_BURST(0), 1536 QSYS_CIR_CFG, port_ix); 1537 1538 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1539 QSYS_SE_CFG, port_ix); 1540 1541 return 0; 1542 } 1543 1544 /* Rate unit is 100 kbps */ 1545 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1546 /* Avoid using zero rate */ 1547 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1548 /* Burst unit is 4kB */ 1549 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1550 /* Avoid using zero burst size */ 1551 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1552 ocelot_write_gix(ocelot, 1553 QSYS_CIR_CFG_CIR_RATE(rate) | 1554 QSYS_CIR_CFG_CIR_BURST(burst), 1555 QSYS_CIR_CFG, 1556 port_ix); 1557 1558 ocelot_rmw_gix(ocelot, 1559 QSYS_SE_CFG_SE_FRM_MODE(0) | 1560 QSYS_SE_CFG_SE_AVB_ENA, 1561 QSYS_SE_CFG_SE_AVB_ENA | 1562 QSYS_SE_CFG_SE_FRM_MODE_M, 1563 QSYS_SE_CFG, 1564 port_ix); 1565 1566 return 0; 1567 } 1568 1569 static int vsc9959_qos_query_caps(struct tc_query_caps_base *base) 1570 { 1571 switch (base->type) { 1572 case TC_SETUP_QDISC_TAPRIO: { 1573 struct tc_taprio_caps *caps = base->caps; 1574 1575 caps->supports_queue_max_sdu = true; 1576 1577 return 0; 1578 } 1579 default: 1580 return -EOPNOTSUPP; 1581 } 1582 } 1583 1584 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1585 enum tc_setup_type type, 1586 void *type_data) 1587 { 1588 struct ocelot *ocelot = ds->priv; 1589 1590 switch (type) { 1591 case TC_QUERY_CAPS: 1592 return vsc9959_qos_query_caps(type_data); 1593 case TC_SETUP_QDISC_TAPRIO: 1594 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1595 case TC_SETUP_QDISC_CBS: 1596 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1597 default: 1598 return -EOPNOTSUPP; 1599 } 1600 } 1601 1602 #define VSC9959_PSFP_SFID_MAX 175 1603 #define VSC9959_PSFP_GATE_ID_MAX 183 1604 #define VSC9959_PSFP_POLICER_BASE 63 1605 #define VSC9959_PSFP_POLICER_MAX 383 1606 #define VSC9959_PSFP_GATE_LIST_NUM 4 1607 #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 1608 1609 struct felix_stream { 1610 struct list_head list; 1611 unsigned long id; 1612 bool dummy; 1613 int ports; 1614 int port; 1615 u8 dmac[ETH_ALEN]; 1616 u16 vid; 1617 s8 prio; 1618 u8 sfid_valid; 1619 u8 ssid_valid; 1620 u32 sfid; 1621 u32 ssid; 1622 }; 1623 1624 struct felix_stream_filter_counters { 1625 u64 match; 1626 u64 not_pass_gate; 1627 u64 not_pass_sdu; 1628 u64 red; 1629 }; 1630 1631 struct felix_stream_filter { 1632 struct felix_stream_filter_counters stats; 1633 struct list_head list; 1634 refcount_t refcount; 1635 u32 index; 1636 u8 enable; 1637 int portmask; 1638 u8 sg_valid; 1639 u32 sgid; 1640 u8 fm_valid; 1641 u32 fmid; 1642 u8 prio_valid; 1643 u8 prio; 1644 u32 maxsdu; 1645 }; 1646 1647 struct felix_stream_gate { 1648 u32 index; 1649 u8 enable; 1650 u8 ipv_valid; 1651 u8 init_ipv; 1652 u64 basetime; 1653 u64 cycletime; 1654 u64 cycletime_ext; 1655 u32 num_entries; 1656 struct action_gate_entry entries[]; 1657 }; 1658 1659 struct felix_stream_gate_entry { 1660 struct list_head list; 1661 refcount_t refcount; 1662 u32 index; 1663 }; 1664 1665 static int vsc9959_stream_identify(struct flow_cls_offload *f, 1666 struct felix_stream *stream) 1667 { 1668 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 1669 struct flow_dissector *dissector = rule->match.dissector; 1670 1671 if (dissector->used_keys & 1672 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 1673 BIT(FLOW_DISSECTOR_KEY_BASIC) | 1674 BIT(FLOW_DISSECTOR_KEY_VLAN) | 1675 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 1676 return -EOPNOTSUPP; 1677 1678 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1679 struct flow_match_eth_addrs match; 1680 1681 flow_rule_match_eth_addrs(rule, &match); 1682 ether_addr_copy(stream->dmac, match.key->dst); 1683 if (!is_zero_ether_addr(match.mask->src)) 1684 return -EOPNOTSUPP; 1685 } else { 1686 return -EOPNOTSUPP; 1687 } 1688 1689 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 1690 struct flow_match_vlan match; 1691 1692 flow_rule_match_vlan(rule, &match); 1693 if (match.mask->vlan_priority) 1694 stream->prio = match.key->vlan_priority; 1695 else 1696 stream->prio = -1; 1697 1698 if (!match.mask->vlan_id) 1699 return -EOPNOTSUPP; 1700 stream->vid = match.key->vlan_id; 1701 } else { 1702 return -EOPNOTSUPP; 1703 } 1704 1705 stream->id = f->cookie; 1706 1707 return 0; 1708 } 1709 1710 static int vsc9959_mact_stream_set(struct ocelot *ocelot, 1711 struct felix_stream *stream, 1712 struct netlink_ext_ack *extack) 1713 { 1714 enum macaccess_entry_type type; 1715 int ret, sfid, ssid; 1716 u32 vid, dst_idx; 1717 u8 mac[ETH_ALEN]; 1718 1719 ether_addr_copy(mac, stream->dmac); 1720 vid = stream->vid; 1721 1722 /* Stream identification desn't support to add a stream with non 1723 * existent MAC (The MAC entry has not been learned in MAC table). 1724 */ 1725 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 1726 if (ret) { 1727 if (extack) 1728 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 1729 return -EOPNOTSUPP; 1730 } 1731 1732 if ((stream->sfid_valid || stream->ssid_valid) && 1733 type == ENTRYTYPE_NORMAL) 1734 type = ENTRYTYPE_LOCKED; 1735 1736 sfid = stream->sfid_valid ? stream->sfid : -1; 1737 ssid = stream->ssid_valid ? stream->ssid : -1; 1738 1739 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 1740 sfid, ssid); 1741 1742 return ret; 1743 } 1744 1745 static struct felix_stream * 1746 vsc9959_stream_table_lookup(struct list_head *stream_list, 1747 struct felix_stream *stream) 1748 { 1749 struct felix_stream *tmp; 1750 1751 list_for_each_entry(tmp, stream_list, list) 1752 if (ether_addr_equal(tmp->dmac, stream->dmac) && 1753 tmp->vid == stream->vid) 1754 return tmp; 1755 1756 return NULL; 1757 } 1758 1759 static int vsc9959_stream_table_add(struct ocelot *ocelot, 1760 struct list_head *stream_list, 1761 struct felix_stream *stream, 1762 struct netlink_ext_ack *extack) 1763 { 1764 struct felix_stream *stream_entry; 1765 int ret; 1766 1767 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 1768 if (!stream_entry) 1769 return -ENOMEM; 1770 1771 if (!stream->dummy) { 1772 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 1773 if (ret) { 1774 kfree(stream_entry); 1775 return ret; 1776 } 1777 } 1778 1779 list_add_tail(&stream_entry->list, stream_list); 1780 1781 return 0; 1782 } 1783 1784 static struct felix_stream * 1785 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 1786 { 1787 struct felix_stream *tmp; 1788 1789 list_for_each_entry(tmp, stream_list, list) 1790 if (tmp->id == id) 1791 return tmp; 1792 1793 return NULL; 1794 } 1795 1796 static void vsc9959_stream_table_del(struct ocelot *ocelot, 1797 struct felix_stream *stream) 1798 { 1799 if (!stream->dummy) 1800 vsc9959_mact_stream_set(ocelot, stream, NULL); 1801 1802 list_del(&stream->list); 1803 kfree(stream); 1804 } 1805 1806 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 1807 { 1808 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 1809 } 1810 1811 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 1812 struct felix_stream_filter *sfi) 1813 { 1814 u32 val; 1815 1816 if (sfi->index > VSC9959_PSFP_SFID_MAX) 1817 return -EINVAL; 1818 1819 if (!sfi->enable) { 1820 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1821 ANA_TABLES_SFIDTIDX); 1822 1823 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 1824 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 1825 1826 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1827 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1828 10, 100000); 1829 } 1830 1831 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 1832 sfi->fmid > VSC9959_PSFP_POLICER_MAX) 1833 return -EINVAL; 1834 1835 ocelot_write(ocelot, 1836 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 1837 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 1838 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 1839 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 1840 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1841 ANA_TABLES_SFIDTIDX); 1842 1843 ocelot_write(ocelot, 1844 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 1845 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 1846 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 1847 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1848 ANA_TABLES_SFIDACCESS); 1849 1850 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1851 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1852 10, 100000); 1853 } 1854 1855 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 1856 { 1857 u32 val; 1858 1859 ocelot_rmw(ocelot, 1860 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1861 ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1862 ANA_TABLES_SFIDTIDX); 1863 1864 ocelot_write(ocelot, 1865 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1866 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1867 ANA_TABLES_SFID_MASK); 1868 1869 ocelot_rmw(ocelot, 1870 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1871 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1872 ANA_TABLES_SFIDACCESS); 1873 1874 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1875 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1876 10, 100000); 1877 } 1878 1879 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1880 struct felix_stream_filter *sfi, 1881 struct list_head *pos) 1882 { 1883 struct felix_stream_filter *sfi_entry; 1884 int ret; 1885 1886 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 1887 if (!sfi_entry) 1888 return -ENOMEM; 1889 1890 refcount_set(&sfi_entry->refcount, 1); 1891 1892 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 1893 if (ret) { 1894 kfree(sfi_entry); 1895 return ret; 1896 } 1897 1898 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1899 1900 list_add(&sfi_entry->list, pos); 1901 1902 return 0; 1903 } 1904 1905 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 1906 struct felix_stream_filter *sfi) 1907 { 1908 struct list_head *pos, *q, *last; 1909 struct felix_stream_filter *tmp; 1910 struct ocelot_psfp_list *psfp; 1911 u32 insert = 0; 1912 1913 psfp = &ocelot->psfp; 1914 last = &psfp->sfi_list; 1915 1916 list_for_each_safe(pos, q, &psfp->sfi_list) { 1917 tmp = list_entry(pos, struct felix_stream_filter, list); 1918 if (sfi->sg_valid == tmp->sg_valid && 1919 sfi->fm_valid == tmp->fm_valid && 1920 sfi->portmask == tmp->portmask && 1921 tmp->sgid == sfi->sgid && 1922 tmp->fmid == sfi->fmid) { 1923 sfi->index = tmp->index; 1924 refcount_inc(&tmp->refcount); 1925 return 0; 1926 } 1927 /* Make sure that the index is increasing in order. */ 1928 if (tmp->index == insert) { 1929 last = pos; 1930 insert++; 1931 } 1932 } 1933 sfi->index = insert; 1934 1935 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1936 } 1937 1938 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 1939 struct felix_stream_filter *sfi, 1940 struct felix_stream_filter *sfi2) 1941 { 1942 struct felix_stream_filter *tmp; 1943 struct list_head *pos, *q, *last; 1944 struct ocelot_psfp_list *psfp; 1945 u32 insert = 0; 1946 int ret; 1947 1948 psfp = &ocelot->psfp; 1949 last = &psfp->sfi_list; 1950 1951 list_for_each_safe(pos, q, &psfp->sfi_list) { 1952 tmp = list_entry(pos, struct felix_stream_filter, list); 1953 /* Make sure that the index is increasing in order. */ 1954 if (tmp->index >= insert + 2) 1955 break; 1956 1957 insert = tmp->index + 1; 1958 last = pos; 1959 } 1960 sfi->index = insert; 1961 1962 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1963 if (ret) 1964 return ret; 1965 1966 sfi2->index = insert + 1; 1967 1968 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 1969 } 1970 1971 static struct felix_stream_filter * 1972 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 1973 { 1974 struct felix_stream_filter *tmp; 1975 1976 list_for_each_entry(tmp, sfi_list, list) 1977 if (tmp->index == index) 1978 return tmp; 1979 1980 return NULL; 1981 } 1982 1983 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 1984 { 1985 struct felix_stream_filter *tmp, *n; 1986 struct ocelot_psfp_list *psfp; 1987 u8 z; 1988 1989 psfp = &ocelot->psfp; 1990 1991 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 1992 if (tmp->index == index) { 1993 z = refcount_dec_and_test(&tmp->refcount); 1994 if (z) { 1995 tmp->enable = 0; 1996 vsc9959_psfp_sfi_set(ocelot, tmp); 1997 list_del(&tmp->list); 1998 kfree(tmp); 1999 } 2000 break; 2001 } 2002 } 2003 2004 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 2005 struct felix_stream_gate *sgi) 2006 { 2007 sgi->index = entry->hw_index; 2008 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 2009 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 2010 sgi->basetime = entry->gate.basetime; 2011 sgi->cycletime = entry->gate.cycletime; 2012 sgi->num_entries = entry->gate.num_entries; 2013 sgi->enable = 1; 2014 2015 memcpy(sgi->entries, entry->gate.entries, 2016 entry->gate.num_entries * sizeof(struct action_gate_entry)); 2017 } 2018 2019 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 2020 { 2021 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 2022 } 2023 2024 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 2025 struct felix_stream_gate *sgi) 2026 { 2027 struct action_gate_entry *e; 2028 struct timespec64 base_ts; 2029 u32 interval_sum = 0; 2030 u32 val; 2031 int i; 2032 2033 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 2034 return -EINVAL; 2035 2036 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 2037 ANA_SG_ACCESS_CTRL); 2038 2039 if (!sgi->enable) { 2040 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 2041 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2042 ANA_SG_CONFIG_REG_3_GATE_ENABLE, 2043 ANA_SG_CONFIG_REG_3); 2044 2045 return 0; 2046 } 2047 2048 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 2049 sgi->cycletime > NSEC_PER_SEC) 2050 return -EINVAL; 2051 2052 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 2053 return -EINVAL; 2054 2055 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 2056 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 2057 val = lower_32_bits(base_ts.tv_sec); 2058 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 2059 2060 val = upper_32_bits(base_ts.tv_sec); 2061 ocelot_write(ocelot, 2062 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 2063 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 2064 ANA_SG_CONFIG_REG_3_GATE_ENABLE | 2065 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 2066 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2067 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 2068 ANA_SG_CONFIG_REG_3); 2069 2070 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 2071 2072 e = sgi->entries; 2073 for (i = 0; i < sgi->num_entries; i++) { 2074 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 2075 2076 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 2077 (e[i].gate_state ? 2078 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 2079 ANA_SG_GCL_GS_CONFIG, i); 2080 2081 interval_sum += e[i].interval; 2082 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 2083 } 2084 2085 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2086 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2087 ANA_SG_ACCESS_CTRL); 2088 2089 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 2090 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 2091 10, 100000); 2092 } 2093 2094 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 2095 struct felix_stream_gate *sgi) 2096 { 2097 struct felix_stream_gate_entry *tmp; 2098 struct ocelot_psfp_list *psfp; 2099 int ret; 2100 2101 psfp = &ocelot->psfp; 2102 2103 list_for_each_entry(tmp, &psfp->sgi_list, list) 2104 if (tmp->index == sgi->index) { 2105 refcount_inc(&tmp->refcount); 2106 return 0; 2107 } 2108 2109 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 2110 if (!tmp) 2111 return -ENOMEM; 2112 2113 ret = vsc9959_psfp_sgi_set(ocelot, sgi); 2114 if (ret) { 2115 kfree(tmp); 2116 return ret; 2117 } 2118 2119 tmp->index = sgi->index; 2120 refcount_set(&tmp->refcount, 1); 2121 list_add_tail(&tmp->list, &psfp->sgi_list); 2122 2123 return 0; 2124 } 2125 2126 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 2127 u32 index) 2128 { 2129 struct felix_stream_gate_entry *tmp, *n; 2130 struct felix_stream_gate sgi = {0}; 2131 struct ocelot_psfp_list *psfp; 2132 u8 z; 2133 2134 psfp = &ocelot->psfp; 2135 2136 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 2137 if (tmp->index == index) { 2138 z = refcount_dec_and_test(&tmp->refcount); 2139 if (z) { 2140 sgi.index = index; 2141 sgi.enable = 0; 2142 vsc9959_psfp_sgi_set(ocelot, &sgi); 2143 list_del(&tmp->list); 2144 kfree(tmp); 2145 } 2146 break; 2147 } 2148 } 2149 2150 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 2151 struct flow_cls_offload *f) 2152 { 2153 struct netlink_ext_ack *extack = f->common.extack; 2154 struct felix_stream_filter old_sfi, *sfi_entry; 2155 struct felix_stream_filter sfi = {0}; 2156 const struct flow_action_entry *a; 2157 struct felix_stream *stream_entry; 2158 struct felix_stream stream = {0}; 2159 struct felix_stream_gate *sgi; 2160 struct ocelot_psfp_list *psfp; 2161 struct ocelot_policer pol; 2162 int ret, i, size; 2163 u64 rate, burst; 2164 u32 index; 2165 2166 psfp = &ocelot->psfp; 2167 2168 ret = vsc9959_stream_identify(f, &stream); 2169 if (ret) { 2170 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 2171 return ret; 2172 } 2173 2174 mutex_lock(&psfp->lock); 2175 2176 flow_action_for_each(i, a, &f->rule->action) { 2177 switch (a->id) { 2178 case FLOW_ACTION_GATE: 2179 size = struct_size(sgi, entries, a->gate.num_entries); 2180 sgi = kzalloc(size, GFP_KERNEL); 2181 if (!sgi) { 2182 ret = -ENOMEM; 2183 goto err; 2184 } 2185 vsc9959_psfp_parse_gate(a, sgi); 2186 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 2187 if (ret) { 2188 kfree(sgi); 2189 goto err; 2190 } 2191 sfi.sg_valid = 1; 2192 sfi.sgid = sgi->index; 2193 kfree(sgi); 2194 break; 2195 case FLOW_ACTION_POLICE: 2196 index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 2197 if (index > VSC9959_PSFP_POLICER_MAX) { 2198 ret = -EINVAL; 2199 goto err; 2200 } 2201 2202 rate = a->police.rate_bytes_ps; 2203 burst = rate * PSCHED_NS2TICKS(a->police.burst); 2204 pol = (struct ocelot_policer) { 2205 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 2206 .rate = div_u64(rate, 1000) * 8, 2207 }; 2208 ret = ocelot_vcap_policer_add(ocelot, index, &pol); 2209 if (ret) 2210 goto err; 2211 2212 sfi.fm_valid = 1; 2213 sfi.fmid = index; 2214 sfi.maxsdu = a->police.mtu; 2215 break; 2216 default: 2217 mutex_unlock(&psfp->lock); 2218 return -EOPNOTSUPP; 2219 } 2220 } 2221 2222 stream.ports = BIT(port); 2223 stream.port = port; 2224 2225 sfi.portmask = stream.ports; 2226 sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 2227 sfi.prio = (sfi.prio_valid ? stream.prio : 0); 2228 sfi.enable = 1; 2229 2230 /* Check if stream is set. */ 2231 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 2232 if (stream_entry) { 2233 if (stream_entry->ports & BIT(port)) { 2234 NL_SET_ERR_MSG_MOD(extack, 2235 "The stream is added on this port"); 2236 ret = -EEXIST; 2237 goto err; 2238 } 2239 2240 if (stream_entry->ports != BIT(stream_entry->port)) { 2241 NL_SET_ERR_MSG_MOD(extack, 2242 "The stream is added on two ports"); 2243 ret = -EEXIST; 2244 goto err; 2245 } 2246 2247 stream_entry->ports |= BIT(port); 2248 stream.ports = stream_entry->ports; 2249 2250 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2251 stream_entry->sfid); 2252 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2253 2254 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2255 2256 old_sfi.portmask = stream_entry->ports; 2257 sfi.portmask = stream.ports; 2258 2259 if (stream_entry->port > port) { 2260 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2261 &old_sfi); 2262 stream_entry->dummy = true; 2263 } else { 2264 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2265 &sfi); 2266 stream.dummy = true; 2267 } 2268 if (ret) 2269 goto err; 2270 2271 stream_entry->sfid = old_sfi.index; 2272 } else { 2273 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 2274 if (ret) 2275 goto err; 2276 } 2277 2278 stream.sfid = sfi.index; 2279 stream.sfid_valid = 1; 2280 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 2281 &stream, extack); 2282 if (ret) { 2283 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 2284 goto err; 2285 } 2286 2287 mutex_unlock(&psfp->lock); 2288 2289 return 0; 2290 2291 err: 2292 if (sfi.sg_valid) 2293 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 2294 2295 if (sfi.fm_valid) 2296 ocelot_vcap_policer_del(ocelot, sfi.fmid); 2297 2298 mutex_unlock(&psfp->lock); 2299 2300 return ret; 2301 } 2302 2303 static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 2304 struct flow_cls_offload *f) 2305 { 2306 struct felix_stream *stream, tmp, *stream_entry; 2307 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2308 static struct felix_stream_filter *sfi; 2309 2310 mutex_lock(&psfp->lock); 2311 2312 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2313 if (!stream) { 2314 mutex_unlock(&psfp->lock); 2315 return -ENOMEM; 2316 } 2317 2318 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2319 if (!sfi) { 2320 mutex_unlock(&psfp->lock); 2321 return -ENOMEM; 2322 } 2323 2324 if (sfi->sg_valid) 2325 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 2326 2327 if (sfi->fm_valid) 2328 ocelot_vcap_policer_del(ocelot, sfi->fmid); 2329 2330 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 2331 2332 memcpy(&tmp, stream, sizeof(tmp)); 2333 2334 stream->sfid_valid = 0; 2335 vsc9959_stream_table_del(ocelot, stream); 2336 2337 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2338 if (stream_entry) { 2339 stream_entry->ports = BIT(stream_entry->port); 2340 if (stream_entry->dummy) { 2341 stream_entry->dummy = false; 2342 vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2343 } 2344 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2345 stream_entry->ports); 2346 } 2347 2348 mutex_unlock(&psfp->lock); 2349 2350 return 0; 2351 } 2352 2353 static void vsc9959_update_sfid_stats(struct ocelot *ocelot, 2354 struct felix_stream_filter *sfi) 2355 { 2356 struct felix_stream_filter_counters *s = &sfi->stats; 2357 u32 match, not_pass_gate, not_pass_sdu, red; 2358 u32 sfid = sfi->index; 2359 2360 lockdep_assert_held(&ocelot->stat_view_lock); 2361 2362 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(sfid), 2363 SYS_STAT_CFG_STAT_VIEW_M, 2364 SYS_STAT_CFG); 2365 2366 match = ocelot_read(ocelot, SYS_COUNT_SF_MATCHING_FRAMES); 2367 not_pass_gate = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_FRAMES); 2368 not_pass_sdu = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_SDU); 2369 red = ocelot_read(ocelot, SYS_COUNT_SF_RED_FRAMES); 2370 2371 /* Clear the PSFP counter. */ 2372 ocelot_write(ocelot, 2373 SYS_STAT_CFG_STAT_VIEW(sfid) | 2374 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 2375 SYS_STAT_CFG); 2376 2377 s->match += match; 2378 s->not_pass_gate += not_pass_gate; 2379 s->not_pass_sdu += not_pass_sdu; 2380 s->red += red; 2381 } 2382 2383 /* Caller must hold &ocelot->stat_view_lock */ 2384 static void vsc9959_update_stats(struct ocelot *ocelot) 2385 { 2386 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2387 struct felix_stream_filter *sfi; 2388 2389 mutex_lock(&psfp->lock); 2390 2391 list_for_each_entry(sfi, &psfp->sfi_list, list) 2392 vsc9959_update_sfid_stats(ocelot, sfi); 2393 2394 mutex_unlock(&psfp->lock); 2395 } 2396 2397 static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 2398 struct flow_cls_offload *f, 2399 struct flow_stats *stats) 2400 { 2401 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2402 struct felix_stream_filter_counters *s; 2403 static struct felix_stream_filter *sfi; 2404 struct felix_stream *stream; 2405 2406 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2407 if (!stream) 2408 return -ENOMEM; 2409 2410 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2411 if (!sfi) 2412 return -EINVAL; 2413 2414 mutex_lock(&ocelot->stat_view_lock); 2415 2416 vsc9959_update_sfid_stats(ocelot, sfi); 2417 2418 s = &sfi->stats; 2419 stats->pkts = s->match; 2420 stats->drops = s->not_pass_gate + s->not_pass_sdu + s->red; 2421 2422 memset(s, 0, sizeof(*s)); 2423 2424 mutex_unlock(&ocelot->stat_view_lock); 2425 2426 return 0; 2427 } 2428 2429 static void vsc9959_psfp_init(struct ocelot *ocelot) 2430 { 2431 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2432 2433 INIT_LIST_HEAD(&psfp->stream_list); 2434 INIT_LIST_HEAD(&psfp->sfi_list); 2435 INIT_LIST_HEAD(&psfp->sgi_list); 2436 mutex_init(&psfp->lock); 2437 } 2438 2439 /* When using cut-through forwarding and the egress port runs at a higher data 2440 * rate than the ingress port, the packet currently under transmission would 2441 * suffer an underrun since it would be transmitted faster than it is received. 2442 * The Felix switch implementation of cut-through forwarding does not check in 2443 * hardware whether this condition is satisfied or not, so we must restrict the 2444 * list of ports that have cut-through forwarding enabled on egress to only be 2445 * the ports operating at the lowest link speed within their respective 2446 * forwarding domain. 2447 */ 2448 static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 2449 { 2450 struct felix *felix = ocelot_to_felix(ocelot); 2451 struct dsa_switch *ds = felix->ds; 2452 int tc, port, other_port; 2453 2454 lockdep_assert_held(&ocelot->fwd_domain_lock); 2455 2456 for (port = 0; port < ocelot->num_phys_ports; port++) { 2457 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2458 int min_speed = ocelot_port->speed; 2459 unsigned long mask = 0; 2460 u32 tmp, val = 0; 2461 2462 /* Disable cut-through on ports that are down */ 2463 if (ocelot_port->speed <= 0) 2464 goto set; 2465 2466 if (dsa_is_cpu_port(ds, port)) { 2467 /* Ocelot switches forward from the NPI port towards 2468 * any port, regardless of it being in the NPI port's 2469 * forwarding domain or not. 2470 */ 2471 mask = dsa_user_ports(ds); 2472 } else { 2473 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2474 mask &= ~BIT(port); 2475 if (ocelot->npi >= 0) 2476 mask |= BIT(ocelot->npi); 2477 else 2478 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 2479 port); 2480 } 2481 2482 /* Calculate the minimum link speed, among the ports that are 2483 * up, of this source port's forwarding domain. 2484 */ 2485 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 2486 struct ocelot_port *other_ocelot_port; 2487 2488 other_ocelot_port = ocelot->ports[other_port]; 2489 if (other_ocelot_port->speed <= 0) 2490 continue; 2491 2492 if (min_speed > other_ocelot_port->speed) 2493 min_speed = other_ocelot_port->speed; 2494 } 2495 2496 /* Enable cut-through forwarding for all traffic classes that 2497 * don't have oversized dropping enabled, since this check is 2498 * bypassed in cut-through mode. 2499 */ 2500 if (ocelot_port->speed == min_speed) { 2501 val = GENMASK(7, 0); 2502 2503 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 2504 if (vsc9959_port_qmaxsdu_get(ocelot, port, tc)) 2505 val &= ~BIT(tc); 2506 } 2507 2508 set: 2509 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 2510 if (tmp == val) 2511 continue; 2512 2513 dev_dbg(ocelot->dev, 2514 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n", 2515 port, mask, ocelot_port->speed, min_speed, 2516 val ? "enabling" : "disabling", val); 2517 2518 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 2519 } 2520 } 2521 2522 static const struct ocelot_ops vsc9959_ops = { 2523 .reset = vsc9959_reset, 2524 .wm_enc = vsc9959_wm_enc, 2525 .wm_dec = vsc9959_wm_dec, 2526 .wm_stat = vsc9959_wm_stat, 2527 .port_to_netdev = felix_port_to_netdev, 2528 .netdev_to_port = felix_netdev_to_port, 2529 .psfp_init = vsc9959_psfp_init, 2530 .psfp_filter_add = vsc9959_psfp_filter_add, 2531 .psfp_filter_del = vsc9959_psfp_filter_del, 2532 .psfp_stats_get = vsc9959_psfp_stats_get, 2533 .cut_through_fwd = vsc9959_cut_through_fwd, 2534 .tas_clock_adjust = vsc9959_tas_clock_adjust, 2535 .update_stats = vsc9959_update_stats, 2536 }; 2537 2538 static const struct felix_info felix_info_vsc9959 = { 2539 .resources = vsc9959_resources, 2540 .num_resources = ARRAY_SIZE(vsc9959_resources), 2541 .resource_names = vsc9959_resource_names, 2542 .regfields = vsc9959_regfields, 2543 .map = vsc9959_regmap, 2544 .ops = &vsc9959_ops, 2545 .vcap = vsc9959_vcap_props, 2546 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 2547 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 2548 .vcap_pol_base2 = 0, 2549 .vcap_pol_max2 = 0, 2550 .num_mact_rows = 2048, 2551 .num_ports = VSC9959_NUM_PORTS, 2552 .num_tx_queues = OCELOT_NUM_TC, 2553 .quirk_no_xtr_irq = true, 2554 .ptp_caps = &vsc9959_ptp_caps, 2555 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2556 .mdio_bus_free = vsc9959_mdio_bus_free, 2557 .port_modes = vsc9959_port_modes, 2558 .port_setup_tc = vsc9959_port_setup_tc, 2559 .port_sched_speed_set = vsc9959_sched_speed_set, 2560 .tas_guard_bands_update = vsc9959_tas_guard_bands_update, 2561 }; 2562 2563 static irqreturn_t felix_irq_handler(int irq, void *data) 2564 { 2565 struct ocelot *ocelot = (struct ocelot *)data; 2566 2567 /* The INTB interrupt is used for both PTP TX timestamp interrupt 2568 * and preemption status change interrupt on each port. 2569 * 2570 * - Get txtstamp if have 2571 * - TODO: handle preemption. Without handling it, driver may get 2572 * interrupt storm. 2573 */ 2574 2575 ocelot_get_txtstamp(ocelot); 2576 2577 return IRQ_HANDLED; 2578 } 2579 2580 static int felix_pci_probe(struct pci_dev *pdev, 2581 const struct pci_device_id *id) 2582 { 2583 struct dsa_switch *ds; 2584 struct ocelot *ocelot; 2585 struct felix *felix; 2586 int err; 2587 2588 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2589 dev_info(&pdev->dev, "device is disabled, skipping\n"); 2590 return -ENODEV; 2591 } 2592 2593 err = pci_enable_device(pdev); 2594 if (err) { 2595 dev_err(&pdev->dev, "device enable failed\n"); 2596 goto err_pci_enable; 2597 } 2598 2599 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2600 if (!felix) { 2601 err = -ENOMEM; 2602 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2603 goto err_alloc_felix; 2604 } 2605 2606 pci_set_drvdata(pdev, felix); 2607 ocelot = &felix->ocelot; 2608 ocelot->dev = &pdev->dev; 2609 ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2610 felix->info = &felix_info_vsc9959; 2611 felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2612 2613 pci_set_master(pdev); 2614 2615 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2616 &felix_irq_handler, IRQF_ONESHOT, 2617 "felix-intb", ocelot); 2618 if (err) { 2619 dev_err(&pdev->dev, "Failed to request irq\n"); 2620 goto err_alloc_irq; 2621 } 2622 2623 ocelot->ptp = 1; 2624 2625 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2626 if (!ds) { 2627 err = -ENOMEM; 2628 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2629 goto err_alloc_ds; 2630 } 2631 2632 ds->dev = &pdev->dev; 2633 ds->num_ports = felix->info->num_ports; 2634 ds->num_tx_queues = felix->info->num_tx_queues; 2635 ds->ops = &felix_switch_ops; 2636 ds->priv = ocelot; 2637 felix->ds = ds; 2638 felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2639 2640 err = dsa_register_switch(ds); 2641 if (err) { 2642 dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n"); 2643 goto err_register_ds; 2644 } 2645 2646 return 0; 2647 2648 err_register_ds: 2649 kfree(ds); 2650 err_alloc_ds: 2651 err_alloc_irq: 2652 kfree(felix); 2653 err_alloc_felix: 2654 pci_disable_device(pdev); 2655 err_pci_enable: 2656 return err; 2657 } 2658 2659 static void felix_pci_remove(struct pci_dev *pdev) 2660 { 2661 struct felix *felix = pci_get_drvdata(pdev); 2662 2663 if (!felix) 2664 return; 2665 2666 dsa_unregister_switch(felix->ds); 2667 2668 kfree(felix->ds); 2669 kfree(felix); 2670 2671 pci_disable_device(pdev); 2672 } 2673 2674 static void felix_pci_shutdown(struct pci_dev *pdev) 2675 { 2676 struct felix *felix = pci_get_drvdata(pdev); 2677 2678 if (!felix) 2679 return; 2680 2681 dsa_switch_shutdown(felix->ds); 2682 2683 pci_set_drvdata(pdev, NULL); 2684 } 2685 2686 static struct pci_device_id felix_ids[] = { 2687 { 2688 /* NXP LS1028A */ 2689 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2690 }, 2691 { 0, } 2692 }; 2693 MODULE_DEVICE_TABLE(pci, felix_ids); 2694 2695 static struct pci_driver felix_vsc9959_pci_driver = { 2696 .name = "mscc_felix", 2697 .id_table = felix_ids, 2698 .probe = felix_pci_probe, 2699 .remove = felix_pci_remove, 2700 .shutdown = felix_pci_shutdown, 2701 }; 2702 module_pci_driver(felix_vsc9959_pci_driver); 2703 2704 MODULE_DESCRIPTION("Felix Switch driver"); 2705 MODULE_LICENSE("GPL v2"); 2706