1 // SPDX-License-Identifier: GPL-2.0 2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. 3 * 4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk> 5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk> 6 * 7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4 8 * integrated PHYs for the user facing ports, and an extension interface which 9 * can be connected to the CPU - or another PHY - via either MII, RMII, or 10 * RGMII. The switch is configured via the Realtek Simple Management Interface 11 * (SMI), which uses the MDIO/MDC lines. 12 * 13 * Below is a simplified block diagram of the chip and its relevant interfaces. 14 * 15 * .-----------------------------------. 16 * | | 17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC | 18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC | 19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC | 20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC | 21 * | | 22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension | 23 * | interface 1 GMAC 1 | 24 * | | 25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ | 26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ | 27 * | ~RTL8365MB ~~~ | 28 * | ~GXXXC TAIWAN~ | 29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ | 30 * | | 31 * Interrupt <----------> Link UP/DOWN events | 32 * controller | | 33 * '-----------------------------------' 34 * 35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the 36 * kernel. Netdevices are created for the user ports, as are PHY devices for 37 * their integrated PHYs. The device tree firmware should also specify the link 38 * partner of the extension port - either via a fixed-link or other phy-handle. 39 * See the device tree bindings for more detailed information. Note that the 40 * driver has only been tested with a fixed-link, but in principle it should not 41 * matter. 42 * 43 * NOTE: Currently, only the RGMII interface is implemented in this driver. 44 * 45 * The interrupt line is asserted on link UP/DOWN events. The driver creates a 46 * custom irqchip to handle this interrupt and demultiplex the events by reading 47 * the status registers via SMI. Interrupts are then propagated to the relevant 48 * PHY device. 49 * 50 * The EEPROM contains initial register values which the chip will read over I2C 51 * upon hardware reset. It is also possible to omit the EEPROM. In both cases, 52 * the driver will manually reprogram some registers using jam tables to reach 53 * an initial state defined by the vendor driver. 54 * 55 * This Linux driver is written based on an OS-agnostic vendor driver from 56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt 57 * source tree under the name rtl8367c. The vendor driver claims to support a 58 * number of similar switch controllers from Realtek, but the only hardware we 59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under 60 * the name RTL8367C. Although one wishes that the 'C' stood for some kind of 61 * common hardware revision, there exist examples of chips with the suffix -VC 62 * which are explicitly not supported by the rtl8367c driver and which instead 63 * require the rtl8367d vendor driver. With all this uncertainty, the driver has 64 * been modestly named rtl8365mb. Future implementors may wish to rename things 65 * accordingly. 66 * 67 * In the same family of chips, some carry up to 8 user ports and up to 2 68 * extension ports. Where possible this driver tries to make things generic, but 69 * more work must be done to support these configurations. According to 70 * documentation from Realtek, the family should include the following chips: 71 * 72 * - RTL8363NB 73 * - RTL8363NB-VB 74 * - RTL8363SC 75 * - RTL8363SC-VB 76 * - RTL8364NB 77 * - RTL8364NB-VB 78 * - RTL8365MB-VC 79 * - RTL8366SC 80 * - RTL8367RB-VB 81 * - RTL8367SB 82 * - RTL8367S 83 * - RTL8370MB 84 * - RTL8310SR 85 * 86 * Some of the register logic for these additional chips has been skipped over 87 * while implementing this driver. It is therefore not possible to assume that 88 * things will work out-of-the-box for other chips, and a careful review of the 89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be 90 * one of the simpler chips. 91 */ 92 93 #include <linux/bitfield.h> 94 #include <linux/bitops.h> 95 #include <linux/interrupt.h> 96 #include <linux/irqdomain.h> 97 #include <linux/mutex.h> 98 #include <linux/of_irq.h> 99 #include <linux/regmap.h> 100 #include <linux/if_bridge.h> 101 #include <linux/if_vlan.h> 102 103 #include "realtek.h" 104 #include "realtek-smi.h" 105 #include "realtek-mdio.h" 106 #include "rtl83xx.h" 107 108 /* Family-specific data and limits */ 109 #define RTL8365MB_PHYADDRMAX 7 110 #define RTL8365MB_NUM_PHYREGS 32 111 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) 112 #define RTL8365MB_MAX_NUM_PORTS 11 113 #define RTL8365MB_MAX_NUM_EXTINTS 3 114 #define RTL8365MB_LEARN_LIMIT_MAX 2112 115 116 /* Chip identification registers */ 117 #define RTL8365MB_CHIP_ID_REG 0x1300 118 119 #define RTL8365MB_CHIP_VER_REG 0x1301 120 121 #define RTL8365MB_MAGIC_REG 0x13C2 122 #define RTL8365MB_MAGIC_VALUE 0x0249 123 124 /* Chip reset register */ 125 #define RTL8365MB_CHIP_RESET_REG 0x1322 126 #define RTL8365MB_CHIP_RESET_SW_MASK 0x0002 127 #define RTL8365MB_CHIP_RESET_HW_MASK 0x0001 128 129 /* Interrupt polarity register */ 130 #define RTL8365MB_INTR_POLARITY_REG 0x1100 131 #define RTL8365MB_INTR_POLARITY_MASK 0x0001 132 #define RTL8365MB_INTR_POLARITY_HIGH 0 133 #define RTL8365MB_INTR_POLARITY_LOW 1 134 135 /* Interrupt control/status register - enable/check specific interrupt types */ 136 #define RTL8365MB_INTR_CTRL_REG 0x1101 137 #define RTL8365MB_INTR_STATUS_REG 0x1102 138 #define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000 139 #define RTL8365MB_INTR_SLIENT_START_MASK 0x0800 140 #define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200 141 #define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100 142 #define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080 143 #define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040 144 #define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020 145 #define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010 146 #define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008 147 #define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004 148 #define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002 149 #define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001 150 #define RTL8365MB_INTR_ALL_MASK \ 151 (RTL8365MB_INTR_SLIENT_START_2_MASK | \ 152 RTL8365MB_INTR_SLIENT_START_MASK | \ 153 RTL8365MB_INTR_ACL_ACTION_MASK | \ 154 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \ 155 RTL8365MB_INTR_INTERRUPT_8051_MASK | \ 156 RTL8365MB_INTR_LOOP_DETECTION_MASK | \ 157 RTL8365MB_INTR_GREEN_TIMER_MASK | \ 158 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \ 159 RTL8365MB_INTR_SPEED_CHANGE_MASK | \ 160 RTL8365MB_INTR_LEARN_OVER_MASK | \ 161 RTL8365MB_INTR_METER_EXCEEDED_MASK | \ 162 RTL8365MB_INTR_LINK_CHANGE_MASK) 163 164 /* Per-port interrupt type status registers */ 165 #define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106 166 #define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF 167 168 #define RTL8365MB_PORT_LINKUP_IND_REG 0x1107 169 #define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF 170 171 /* PHY indirect access registers */ 172 #define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00 173 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 174 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0 175 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1 176 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 177 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 178 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01 179 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 180 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) 181 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) 182 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) 183 #define RTL8365MB_PHY_BASE 0x2000 184 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 185 #define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 186 187 /* PHY OCP address prefix register */ 188 #define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15 189 #define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 190 #define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 191 192 /* The PHY OCP addresses of PHY registers 0~31 start here */ 193 #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 194 195 /* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */ 196 #define RTL8365MB_EXT_PORT_MODE_DISABLE 0 197 #define RTL8365MB_EXT_PORT_MODE_RGMII 1 198 #define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 199 #define RTL8365MB_EXT_PORT_MODE_MII_PHY 3 200 #define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4 201 #define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5 202 #define RTL8365MB_EXT_PORT_MODE_GMII 6 203 #define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7 204 #define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8 205 #define RTL8365MB_EXT_PORT_MODE_SGMII 9 206 #define RTL8365MB_EXT_PORT_MODE_HSGMII 10 207 #define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11 208 #define RTL8365MB_EXT_PORT_MODE_1000X 12 209 #define RTL8365MB_EXT_PORT_MODE_100FX 13 210 211 /* External interface mode configuration registers 0~1 */ 212 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT0,EXT1 */ 213 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */ 214 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \ 215 ((_extint) <= 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \ 216 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \ 217 0x0) 218 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \ 219 (0xF << (((_extint) % 2))) 220 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \ 221 (((_extint) % 2) * 4) 222 223 /* External interface RGMII TX/RX delay configuration registers 0~2 */ 224 #define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */ 225 #define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */ 226 #define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */ 227 #define RTL8365MB_EXT_RGMXF_REG(_extint) \ 228 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \ 229 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \ 230 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \ 231 0x0) 232 #define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007 233 #define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008 234 235 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */ 236 #define RTL8365MB_PORT_SPEED_10M 0 237 #define RTL8365MB_PORT_SPEED_100M 1 238 #define RTL8365MB_PORT_SPEED_1000M 2 239 240 /* External interface force configuration registers 0~2 */ 241 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */ 242 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */ 243 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */ 244 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \ 245 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \ 246 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \ 247 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \ 248 0x0) 249 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 250 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 251 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 252 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 253 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 254 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 255 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 256 257 /* CPU port mask register - controls which ports are treated as CPU ports */ 258 #define RTL8365MB_CPU_PORT_MASK_REG 0x1219 259 #define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF 260 261 /* CPU control register */ 262 #define RTL8365MB_CPU_CTRL_REG 0x121A 263 #define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 264 #define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200 265 #define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 266 #define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040 267 #define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038 268 #define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006 269 #define RTL8365MB_CPU_CTRL_EN_MASK 0x0001 270 271 /* Maximum packet length register */ 272 #define RTL8365MB_CFG0_MAX_LEN_REG 0x088C 273 #define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF 274 #define RTL8365MB_CFG0_MAX_LEN_MAX 0x3FFF 275 276 /* Port learning limit registers */ 277 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 278 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \ 279 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) 280 281 /* Port isolation (forwarding mask) registers */ 282 #define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2 283 #define RTL8365MB_PORT_ISOLATION_REG(_physport) \ 284 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport)) 285 #define RTL8365MB_PORT_ISOLATION_MASK 0x07FF 286 287 /* MSTP port state registers - indexed by tree instance */ 288 #define RTL8365MB_MSTI_CTRL_BASE 0x0A00 289 #define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \ 290 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) 291 #define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) 292 #define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ 293 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) 294 295 /* MIB counter value registers */ 296 #define RTL8365MB_MIB_COUNTER_BASE 0x1000 297 #define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x)) 298 299 /* MIB counter address register */ 300 #define RTL8365MB_MIB_ADDRESS_REG 0x1004 301 #define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C 302 #define RTL8365MB_MIB_ADDRESS(_p, _x) \ 303 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) 304 305 #define RTL8365MB_MIB_CTRL0_REG 0x1005 306 #define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002 307 #define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001 308 309 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed 310 * to block. On the other hand, accessing MIB counters absolutely requires us to 311 * block. The solution is thus to schedule work which polls the MIB counters 312 * asynchronously and updates some private data, which the callback can then 313 * fetch atomically. Three seconds should be a good enough polling interval. 314 */ 315 #define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ) 316 317 enum rtl8365mb_mib_counter_index { 318 RTL8365MB_MIB_ifInOctets, 319 RTL8365MB_MIB_dot3StatsFCSErrors, 320 RTL8365MB_MIB_dot3StatsSymbolErrors, 321 RTL8365MB_MIB_dot3InPauseFrames, 322 RTL8365MB_MIB_dot3ControlInUnknownOpcodes, 323 RTL8365MB_MIB_etherStatsFragments, 324 RTL8365MB_MIB_etherStatsJabbers, 325 RTL8365MB_MIB_ifInUcastPkts, 326 RTL8365MB_MIB_etherStatsDropEvents, 327 RTL8365MB_MIB_ifInMulticastPkts, 328 RTL8365MB_MIB_ifInBroadcastPkts, 329 RTL8365MB_MIB_inMldChecksumError, 330 RTL8365MB_MIB_inIgmpChecksumError, 331 RTL8365MB_MIB_inMldSpecificQuery, 332 RTL8365MB_MIB_inMldGeneralQuery, 333 RTL8365MB_MIB_inIgmpSpecificQuery, 334 RTL8365MB_MIB_inIgmpGeneralQuery, 335 RTL8365MB_MIB_inMldLeaves, 336 RTL8365MB_MIB_inIgmpLeaves, 337 RTL8365MB_MIB_etherStatsOctets, 338 RTL8365MB_MIB_etherStatsUnderSizePkts, 339 RTL8365MB_MIB_etherOversizeStats, 340 RTL8365MB_MIB_etherStatsPkts64Octets, 341 RTL8365MB_MIB_etherStatsPkts65to127Octets, 342 RTL8365MB_MIB_etherStatsPkts128to255Octets, 343 RTL8365MB_MIB_etherStatsPkts256to511Octets, 344 RTL8365MB_MIB_etherStatsPkts512to1023Octets, 345 RTL8365MB_MIB_etherStatsPkts1024to1518Octets, 346 RTL8365MB_MIB_ifOutOctets, 347 RTL8365MB_MIB_dot3StatsSingleCollisionFrames, 348 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames, 349 RTL8365MB_MIB_dot3StatsDeferredTransmissions, 350 RTL8365MB_MIB_dot3StatsLateCollisions, 351 RTL8365MB_MIB_etherStatsCollisions, 352 RTL8365MB_MIB_dot3StatsExcessiveCollisions, 353 RTL8365MB_MIB_dot3OutPauseFrames, 354 RTL8365MB_MIB_ifOutDiscards, 355 RTL8365MB_MIB_dot1dTpPortInDiscards, 356 RTL8365MB_MIB_ifOutUcastPkts, 357 RTL8365MB_MIB_ifOutMulticastPkts, 358 RTL8365MB_MIB_ifOutBroadcastPkts, 359 RTL8365MB_MIB_outOampduPkts, 360 RTL8365MB_MIB_inOampduPkts, 361 RTL8365MB_MIB_inIgmpJoinsSuccess, 362 RTL8365MB_MIB_inIgmpJoinsFail, 363 RTL8365MB_MIB_inMldJoinsSuccess, 364 RTL8365MB_MIB_inMldJoinsFail, 365 RTL8365MB_MIB_inReportSuppressionDrop, 366 RTL8365MB_MIB_inLeaveSuppressionDrop, 367 RTL8365MB_MIB_outIgmpReports, 368 RTL8365MB_MIB_outIgmpLeaves, 369 RTL8365MB_MIB_outIgmpGeneralQuery, 370 RTL8365MB_MIB_outIgmpSpecificQuery, 371 RTL8365MB_MIB_outMldReports, 372 RTL8365MB_MIB_outMldLeaves, 373 RTL8365MB_MIB_outMldGeneralQuery, 374 RTL8365MB_MIB_outMldSpecificQuery, 375 RTL8365MB_MIB_inKnownMulticastPkts, 376 RTL8365MB_MIB_END, 377 }; 378 379 struct rtl8365mb_mib_counter { 380 u32 offset; 381 u32 length; 382 const char *name; 383 }; 384 385 #define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \ 386 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name } 387 388 static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = { 389 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets), 390 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), 391 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), 392 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), 393 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), 394 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), 395 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), 396 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), 397 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), 398 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), 399 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), 400 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), 401 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), 402 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), 403 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), 404 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), 405 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), 406 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves), 407 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), 408 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), 409 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), 410 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), 411 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), 412 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), 413 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), 414 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), 415 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), 416 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), 417 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets), 418 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), 419 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), 420 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), 421 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), 422 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), 423 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), 424 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), 425 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), 426 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), 427 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), 428 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), 429 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), 430 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts), 431 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts), 432 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), 433 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), 434 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), 435 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), 436 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), 437 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), 438 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports), 439 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), 440 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), 441 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), 442 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports), 443 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves), 444 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), 445 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), 446 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), 447 }; 448 449 static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END); 450 451 struct rtl8365mb_jam_tbl_entry { 452 u16 reg; 453 u16 val; 454 }; 455 456 /* Lifted from the vendor driver sources */ 457 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { 458 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 }, 459 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA }, 460 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 }, 461 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F }, 462 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 }, 463 { 0x13F0, 0x0000 }, 464 }; 465 466 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = { 467 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 }, 468 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E }, 469 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 }, 470 { 0x1D32, 0x0002 }, 471 }; 472 473 enum rtl8365mb_phy_interface_mode { 474 RTL8365MB_PHY_INTERFACE_MODE_INVAL = 0, 475 RTL8365MB_PHY_INTERFACE_MODE_INTERNAL = BIT(0), 476 RTL8365MB_PHY_INTERFACE_MODE_MII = BIT(1), 477 RTL8365MB_PHY_INTERFACE_MODE_TMII = BIT(2), 478 RTL8365MB_PHY_INTERFACE_MODE_RMII = BIT(3), 479 RTL8365MB_PHY_INTERFACE_MODE_RGMII = BIT(4), 480 RTL8365MB_PHY_INTERFACE_MODE_SGMII = BIT(5), 481 RTL8365MB_PHY_INTERFACE_MODE_HSGMII = BIT(6), 482 }; 483 484 /** 485 * struct rtl8365mb_extint - external interface info 486 * @port: the port with an external interface 487 * @id: the external interface ID, which is either 0, 1, or 2 488 * @supported_interfaces: a bitmask of supported PHY interface modes 489 * 490 * Represents a mapping: port -> { id, supported_interfaces }. To be embedded 491 * in &struct rtl8365mb_chip_info for every port with an external interface. 492 */ 493 struct rtl8365mb_extint { 494 int port; 495 int id; 496 unsigned int supported_interfaces; 497 }; 498 499 /** 500 * struct rtl8365mb_chip_info - static chip-specific info 501 * @name: human-readable chip name 502 * @chip_id: chip identifier 503 * @chip_ver: chip silicon revision 504 * @extints: available external interfaces 505 * @jam_table: chip-specific initialization jam table 506 * @jam_size: size of the chip's jam table 507 * 508 * These data are specific to a given chip in the family of switches supported 509 * by this driver. When adding support for another chip in the family, a new 510 * chip info should be added to the rtl8365mb_chip_infos array. 511 */ 512 struct rtl8365mb_chip_info { 513 const char *name; 514 u32 chip_id; 515 u32 chip_ver; 516 const struct rtl8365mb_extint extints[RTL8365MB_MAX_NUM_EXTINTS]; 517 const struct rtl8365mb_jam_tbl_entry *jam_table; 518 size_t jam_size; 519 }; 520 521 /* Chip info for each supported switch in the family */ 522 #define PHY_INTF(_mode) (RTL8365MB_PHY_INTERFACE_MODE_ ## _mode) 523 static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = { 524 { 525 .name = "RTL8365MB-VC", 526 .chip_id = 0x6367, 527 .chip_ver = 0x0040, 528 .extints = { 529 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | 530 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 531 }, 532 .jam_table = rtl8365mb_init_jam_8365mb_vc, 533 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 534 }, 535 { 536 .name = "RTL8367S", 537 .chip_id = 0x6367, 538 .chip_ver = 0x00A0, 539 .extints = { 540 { 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) }, 541 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | 542 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 543 }, 544 .jam_table = rtl8365mb_init_jam_8365mb_vc, 545 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 546 }, 547 { 548 .name = "RTL8367RB-VB", 549 .chip_id = 0x6367, 550 .chip_ver = 0x0020, 551 .extints = { 552 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | 553 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 554 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | 555 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 556 }, 557 .jam_table = rtl8365mb_init_jam_8365mb_vc, 558 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 559 }, 560 }; 561 562 enum rtl8365mb_stp_state { 563 RTL8365MB_STP_STATE_DISABLED = 0, 564 RTL8365MB_STP_STATE_BLOCKING = 1, 565 RTL8365MB_STP_STATE_LEARNING = 2, 566 RTL8365MB_STP_STATE_FORWARDING = 3, 567 }; 568 569 enum rtl8365mb_cpu_insert { 570 RTL8365MB_CPU_INSERT_TO_ALL = 0, 571 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1, 572 RTL8365MB_CPU_INSERT_TO_NONE = 2, 573 }; 574 575 enum rtl8365mb_cpu_position { 576 RTL8365MB_CPU_POS_AFTER_SA = 0, 577 RTL8365MB_CPU_POS_BEFORE_CRC = 1, 578 }; 579 580 enum rtl8365mb_cpu_format { 581 RTL8365MB_CPU_FORMAT_8BYTES = 0, 582 RTL8365MB_CPU_FORMAT_4BYTES = 1, 583 }; 584 585 enum rtl8365mb_cpu_rxlen { 586 RTL8365MB_CPU_RXLEN_72BYTES = 0, 587 RTL8365MB_CPU_RXLEN_64BYTES = 1, 588 }; 589 590 /** 591 * struct rtl8365mb_cpu - CPU port configuration 592 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames 593 * @mask: port mask of ports that parse should parse CPU tags 594 * @trap_port: forward trapped frames to this port 595 * @insert: CPU tag insertion mode in switch->CPU frames 596 * @position: position of CPU tag in frame 597 * @rx_length: minimum CPU RX length 598 * @format: CPU tag format 599 * 600 * Represents the CPU tagging and CPU port configuration of the switch. These 601 * settings are configurable at runtime. 602 */ 603 struct rtl8365mb_cpu { 604 bool enable; 605 u32 mask; 606 u32 trap_port; 607 enum rtl8365mb_cpu_insert insert; 608 enum rtl8365mb_cpu_position position; 609 enum rtl8365mb_cpu_rxlen rx_length; 610 enum rtl8365mb_cpu_format format; 611 }; 612 613 /** 614 * struct rtl8365mb_port - private per-port data 615 * @priv: pointer to parent realtek_priv data 616 * @index: DSA port index, same as dsa_port::index 617 * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic 618 * access via rtl8365mb_get_stats64 619 * @stats_lock: protect the stats structure during read/update 620 * @mib_work: delayed work for polling MIB counters 621 */ 622 struct rtl8365mb_port { 623 struct realtek_priv *priv; 624 unsigned int index; 625 struct rtnl_link_stats64 stats; 626 spinlock_t stats_lock; 627 struct delayed_work mib_work; 628 }; 629 630 /** 631 * struct rtl8365mb - driver private data 632 * @priv: pointer to parent realtek_priv data 633 * @irq: registered IRQ or zero 634 * @chip_info: chip-specific info about the attached switch 635 * @cpu: CPU tagging and CPU port configuration for this chip 636 * @mib_lock: prevent concurrent reads of MIB counters 637 * @ports: per-port data 638 * 639 * Private data for this driver. 640 */ 641 struct rtl8365mb { 642 struct realtek_priv *priv; 643 int irq; 644 const struct rtl8365mb_chip_info *chip_info; 645 struct rtl8365mb_cpu cpu; 646 struct mutex mib_lock; 647 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; 648 }; 649 650 static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) 651 { 652 u32 val; 653 654 return regmap_read_poll_timeout(priv->map_nolock, 655 RTL8365MB_INDIRECT_ACCESS_STATUS_REG, 656 val, !val, 10, 100); 657 } 658 659 static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, 660 u32 ocp_addr) 661 { 662 u32 val; 663 int ret; 664 665 /* Set OCP prefix */ 666 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); 667 ret = regmap_update_bits( 668 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG, 669 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, 670 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); 671 if (ret) 672 return ret; 673 674 /* Set PHY register address */ 675 val = RTL8365MB_PHY_BASE; 676 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); 677 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, 678 ocp_addr >> 1); 679 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, 680 ocp_addr >> 6); 681 ret = regmap_write(priv->map_nolock, 682 RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val); 683 if (ret) 684 return ret; 685 686 return 0; 687 } 688 689 static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, 690 u32 ocp_addr, u16 *data) 691 { 692 u32 val; 693 int ret; 694 695 rtl83xx_lock(priv); 696 697 ret = rtl8365mb_phy_poll_busy(priv); 698 if (ret) 699 goto out; 700 701 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 702 if (ret) 703 goto out; 704 705 /* Execute read operation */ 706 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 707 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 708 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 709 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ); 710 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 711 val); 712 if (ret) 713 goto out; 714 715 ret = rtl8365mb_phy_poll_busy(priv); 716 if (ret) 717 goto out; 718 719 /* Get PHY register data */ 720 ret = regmap_read(priv->map_nolock, 721 RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val); 722 if (ret) 723 goto out; 724 725 *data = val & 0xFFFF; 726 727 out: 728 rtl83xx_unlock(priv); 729 730 return ret; 731 } 732 733 static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, 734 u32 ocp_addr, u16 data) 735 { 736 u32 val; 737 int ret; 738 739 rtl83xx_lock(priv); 740 741 ret = rtl8365mb_phy_poll_busy(priv); 742 if (ret) 743 goto out; 744 745 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 746 if (ret) 747 goto out; 748 749 /* Set PHY register data */ 750 ret = regmap_write(priv->map_nolock, 751 RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data); 752 if (ret) 753 goto out; 754 755 /* Execute write operation */ 756 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 757 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 758 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 759 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE); 760 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 761 val); 762 if (ret) 763 goto out; 764 765 ret = rtl8365mb_phy_poll_busy(priv); 766 if (ret) 767 goto out; 768 769 out: 770 rtl83xx_unlock(priv); 771 772 return 0; 773 } 774 775 static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum) 776 { 777 u32 ocp_addr; 778 u16 val; 779 int ret; 780 781 if (phy > RTL8365MB_PHYADDRMAX) 782 return -EINVAL; 783 784 if (regnum > RTL8365MB_PHYREGMAX) 785 return -EINVAL; 786 787 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 788 789 ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); 790 if (ret) { 791 dev_err(priv->dev, 792 "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy, 793 regnum, ocp_addr, ret); 794 return ret; 795 } 796 797 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n", 798 phy, regnum, ocp_addr, val); 799 800 return val; 801 } 802 803 static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum, 804 u16 val) 805 { 806 u32 ocp_addr; 807 int ret; 808 809 if (phy > RTL8365MB_PHYADDRMAX) 810 return -EINVAL; 811 812 if (regnum > RTL8365MB_PHYREGMAX) 813 return -EINVAL; 814 815 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 816 817 ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); 818 if (ret) { 819 dev_err(priv->dev, 820 "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy, 821 regnum, ocp_addr, ret); 822 return ret; 823 } 824 825 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n", 826 phy, regnum, ocp_addr, val); 827 828 return 0; 829 } 830 831 static const struct rtl8365mb_extint * 832 rtl8365mb_get_port_extint(struct realtek_priv *priv, int port) 833 { 834 struct rtl8365mb *mb = priv->chip_data; 835 int i; 836 837 for (i = 0; i < RTL8365MB_MAX_NUM_EXTINTS; i++) { 838 const struct rtl8365mb_extint *extint = 839 &mb->chip_info->extints[i]; 840 841 if (!extint->supported_interfaces) 842 continue; 843 844 if (extint->port == port) 845 return extint; 846 } 847 848 return NULL; 849 } 850 851 static enum dsa_tag_protocol 852 rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, 853 enum dsa_tag_protocol mp) 854 { 855 struct realtek_priv *priv = ds->priv; 856 struct rtl8365mb_cpu *cpu; 857 struct rtl8365mb *mb; 858 859 mb = priv->chip_data; 860 cpu = &mb->cpu; 861 862 if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC) 863 return DSA_TAG_PROTO_RTL8_4T; 864 865 return DSA_TAG_PROTO_RTL8_4; 866 } 867 868 static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, 869 phy_interface_t interface) 870 { 871 const struct rtl8365mb_extint *extint = 872 rtl8365mb_get_port_extint(priv, port); 873 struct dsa_switch *ds = &priv->ds; 874 struct device_node *dn; 875 struct dsa_port *dp; 876 int tx_delay = 0; 877 int rx_delay = 0; 878 u32 val; 879 int ret; 880 881 if (!extint) 882 return -ENODEV; 883 884 dp = dsa_to_port(ds, port); 885 dn = dp->dn; 886 887 /* Set the RGMII TX/RX delay 888 * 889 * The Realtek vendor driver indicates the following possible 890 * configuration settings: 891 * 892 * TX delay: 893 * 0 = no delay, 1 = 2 ns delay 894 * RX delay: 895 * 0 = no delay, 7 = maximum delay 896 * Each step is approximately 0.3 ns, so the maximum delay is about 897 * 2.1 ns. 898 * 899 * The vendor driver also states that this must be configured *before* 900 * forcing the external interface into a particular mode, which is done 901 * in the rtl8365mb_phylink_mac_link_{up,down} functions. 902 * 903 * Only configure an RGMII TX (resp. RX) delay if the 904 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is 905 * specified. We ignore the detail of the RGMII interface mode 906 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only 907 * property. 908 */ 909 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) { 910 val = val / 1000; /* convert to ns */ 911 912 if (val == 0 || val == 2) 913 tx_delay = val / 2; 914 else 915 dev_warn(priv->dev, 916 "RGMII TX delay must be 0 or 2 ns\n"); 917 } 918 919 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) { 920 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */ 921 922 if (val <= 7) 923 rx_delay = val; 924 else 925 dev_warn(priv->dev, 926 "RGMII RX delay must be 0 to 2.1 ns\n"); 927 } 928 929 ret = regmap_update_bits( 930 priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id), 931 RTL8365MB_EXT_RGMXF_TXDELAY_MASK | 932 RTL8365MB_EXT_RGMXF_RXDELAY_MASK, 933 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | 934 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay)); 935 if (ret) 936 return ret; 937 938 ret = regmap_update_bits( 939 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id), 940 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id), 941 RTL8365MB_EXT_PORT_MODE_RGMII 942 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( 943 extint->id)); 944 if (ret) 945 return ret; 946 947 return 0; 948 } 949 950 static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, 951 bool link, int speed, int duplex, 952 bool tx_pause, bool rx_pause) 953 { 954 const struct rtl8365mb_extint *extint = 955 rtl8365mb_get_port_extint(priv, port); 956 u32 r_tx_pause; 957 u32 r_rx_pause; 958 u32 r_duplex; 959 u32 r_speed; 960 u32 r_link; 961 int val; 962 int ret; 963 964 if (!extint) 965 return -ENODEV; 966 967 if (link) { 968 /* Force the link up with the desired configuration */ 969 r_link = 1; 970 r_rx_pause = rx_pause ? 1 : 0; 971 r_tx_pause = tx_pause ? 1 : 0; 972 973 if (speed == SPEED_1000) { 974 r_speed = RTL8365MB_PORT_SPEED_1000M; 975 } else if (speed == SPEED_100) { 976 r_speed = RTL8365MB_PORT_SPEED_100M; 977 } else if (speed == SPEED_10) { 978 r_speed = RTL8365MB_PORT_SPEED_10M; 979 } else { 980 dev_err(priv->dev, "unsupported port speed %s\n", 981 phy_speed_to_str(speed)); 982 return -EINVAL; 983 } 984 985 if (duplex == DUPLEX_FULL) { 986 r_duplex = 1; 987 } else if (duplex == DUPLEX_HALF) { 988 r_duplex = 0; 989 } else { 990 dev_err(priv->dev, "unsupported duplex %s\n", 991 phy_duplex_to_str(duplex)); 992 return -EINVAL; 993 } 994 } else { 995 /* Force the link down and reset any programmed configuration */ 996 r_link = 0; 997 r_tx_pause = 0; 998 r_rx_pause = 0; 999 r_speed = 0; 1000 r_duplex = 0; 1001 } 1002 1003 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | 1004 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, 1005 r_tx_pause) | 1006 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, 1007 r_rx_pause) | 1008 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | 1009 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, 1010 r_duplex) | 1011 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); 1012 ret = regmap_write(priv->map, 1013 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id), 1014 val); 1015 if (ret) 1016 return ret; 1017 1018 return 0; 1019 } 1020 1021 static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port, 1022 struct phylink_config *config) 1023 { 1024 const struct rtl8365mb_extint *extint = 1025 rtl8365mb_get_port_extint(ds->priv, port); 1026 1027 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 1028 MAC_10 | MAC_100 | MAC_1000FD; 1029 1030 if (!extint) { 1031 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1032 config->supported_interfaces); 1033 1034 /* GMII is the default interface mode for phylib, so 1035 * we have to support it for ports with integrated PHY. 1036 */ 1037 __set_bit(PHY_INTERFACE_MODE_GMII, 1038 config->supported_interfaces); 1039 return; 1040 } 1041 1042 /* Populate according to the modes supported by _this driver_, 1043 * not necessarily the modes supported by the hardware, some of 1044 * which remain unimplemented. 1045 */ 1046 1047 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII) 1048 phy_interface_set_rgmii(config->supported_interfaces); 1049 } 1050 1051 static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, 1052 unsigned int mode, 1053 const struct phylink_link_state *state) 1054 { 1055 struct realtek_priv *priv = ds->priv; 1056 int ret; 1057 1058 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) { 1059 dev_err(priv->dev, 1060 "port %d supports only conventional PHY or fixed-link\n", 1061 port); 1062 return; 1063 } 1064 1065 if (phy_interface_mode_is_rgmii(state->interface)) { 1066 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); 1067 if (ret) 1068 dev_err(priv->dev, 1069 "failed to configure RGMII mode on port %d: %d\n", 1070 port, ret); 1071 return; 1072 } 1073 1074 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also 1075 * supports 1076 */ 1077 } 1078 1079 static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, 1080 unsigned int mode, 1081 phy_interface_t interface) 1082 { 1083 struct realtek_priv *priv = ds->priv; 1084 struct rtl8365mb_port *p; 1085 struct rtl8365mb *mb; 1086 int ret; 1087 1088 mb = priv->chip_data; 1089 p = &mb->ports[port]; 1090 cancel_delayed_work_sync(&p->mib_work); 1091 1092 if (phy_interface_mode_is_rgmii(interface)) { 1093 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0, 1094 false, false); 1095 if (ret) 1096 dev_err(priv->dev, 1097 "failed to reset forced mode on port %d: %d\n", 1098 port, ret); 1099 1100 return; 1101 } 1102 } 1103 1104 static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, 1105 unsigned int mode, 1106 phy_interface_t interface, 1107 struct phy_device *phydev, int speed, 1108 int duplex, bool tx_pause, 1109 bool rx_pause) 1110 { 1111 struct realtek_priv *priv = ds->priv; 1112 struct rtl8365mb_port *p; 1113 struct rtl8365mb *mb; 1114 int ret; 1115 1116 mb = priv->chip_data; 1117 p = &mb->ports[port]; 1118 schedule_delayed_work(&p->mib_work, 0); 1119 1120 if (phy_interface_mode_is_rgmii(interface)) { 1121 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed, 1122 duplex, tx_pause, 1123 rx_pause); 1124 if (ret) 1125 dev_err(priv->dev, 1126 "failed to force mode on port %d: %d\n", port, 1127 ret); 1128 1129 return; 1130 } 1131 } 1132 1133 static int rtl8365mb_port_change_mtu(struct dsa_switch *ds, int port, 1134 int new_mtu) 1135 { 1136 struct realtek_priv *priv = ds->priv; 1137 int frame_size; 1138 1139 /* When a new MTU is set, DSA always sets the CPU port's MTU to the 1140 * largest MTU of the user ports. Because the switch only has a global 1141 * RX length register, only allowing CPU port here is enough. 1142 */ 1143 if (!dsa_is_cpu_port(ds, port)) 1144 return 0; 1145 1146 frame_size = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 1147 1148 dev_dbg(priv->dev, "changing mtu to %d (frame size: %d)\n", 1149 new_mtu, frame_size); 1150 1151 return regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, 1152 RTL8365MB_CFG0_MAX_LEN_MASK, 1153 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1154 frame_size)); 1155 } 1156 1157 static int rtl8365mb_port_max_mtu(struct dsa_switch *ds, int port) 1158 { 1159 return RTL8365MB_CFG0_MAX_LEN_MAX - VLAN_ETH_HLEN - ETH_FCS_LEN; 1160 } 1161 1162 static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, 1163 u8 state) 1164 { 1165 struct realtek_priv *priv = ds->priv; 1166 enum rtl8365mb_stp_state val; 1167 int msti = 0; 1168 1169 switch (state) { 1170 case BR_STATE_DISABLED: 1171 val = RTL8365MB_STP_STATE_DISABLED; 1172 break; 1173 case BR_STATE_BLOCKING: 1174 case BR_STATE_LISTENING: 1175 val = RTL8365MB_STP_STATE_BLOCKING; 1176 break; 1177 case BR_STATE_LEARNING: 1178 val = RTL8365MB_STP_STATE_LEARNING; 1179 break; 1180 case BR_STATE_FORWARDING: 1181 val = RTL8365MB_STP_STATE_FORWARDING; 1182 break; 1183 default: 1184 dev_err(priv->dev, "invalid STP state: %u\n", state); 1185 return; 1186 } 1187 1188 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), 1189 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port), 1190 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); 1191 } 1192 1193 static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, 1194 bool enable) 1195 { 1196 /* Enable/disable learning by limiting the number of L2 addresses the 1197 * port can learn. Realtek documentation states that a limit of zero 1198 * disables learning. When enabling learning, set it to the chip's 1199 * maximum. 1200 */ 1201 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), 1202 enable ? RTL8365MB_LEARN_LIMIT_MAX : 0); 1203 } 1204 1205 static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, 1206 u32 mask) 1207 { 1208 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); 1209 } 1210 1211 static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, 1212 u32 offset, u32 length, u64 *mibvalue) 1213 { 1214 u64 tmpvalue = 0; 1215 u32 val; 1216 int ret; 1217 int i; 1218 1219 /* The MIB address is an SRAM address. We request a particular address 1220 * and then poll the control register before reading the value from some 1221 * counter registers. 1222 */ 1223 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, 1224 RTL8365MB_MIB_ADDRESS(port, offset)); 1225 if (ret) 1226 return ret; 1227 1228 /* Poll for completion */ 1229 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, 1230 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK), 1231 10, 100); 1232 if (ret) 1233 return ret; 1234 1235 /* Presumably this indicates a MIB counter read failure */ 1236 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK) 1237 return -EIO; 1238 1239 /* There are four MIB counter registers each holding a 16 bit word of a 1240 * MIB counter. Depending on the offset, we should read from the upper 1241 * two or lower two registers. In case the MIB counter is 4 words, we 1242 * read from all four registers. 1243 */ 1244 if (length == 4) 1245 offset = 3; 1246 else 1247 offset = (offset + 1) % 4; 1248 1249 /* Read the MIB counter 16 bits at a time */ 1250 for (i = 0; i < length; i++) { 1251 ret = regmap_read(priv->map, 1252 RTL8365MB_MIB_COUNTER_REG(offset - i), &val); 1253 if (ret) 1254 return ret; 1255 1256 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF); 1257 } 1258 1259 /* Only commit the result if no error occurred */ 1260 *mibvalue = tmpvalue; 1261 1262 return 0; 1263 } 1264 1265 static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1266 { 1267 struct realtek_priv *priv = ds->priv; 1268 struct rtl8365mb *mb; 1269 int ret; 1270 int i; 1271 1272 mb = priv->chip_data; 1273 1274 mutex_lock(&mb->mib_lock); 1275 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1276 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1277 1278 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1279 mib->length, &data[i]); 1280 if (ret) { 1281 dev_err(priv->dev, 1282 "failed to read port %d counters: %d\n", port, 1283 ret); 1284 break; 1285 } 1286 } 1287 mutex_unlock(&mb->mib_lock); 1288 } 1289 1290 static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) 1291 { 1292 int i; 1293 1294 if (stringset != ETH_SS_STATS) 1295 return; 1296 1297 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1298 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1299 ethtool_puts(&data, mib->name); 1300 } 1301 } 1302 1303 static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset) 1304 { 1305 if (sset != ETH_SS_STATS) 1306 return -EOPNOTSUPP; 1307 1308 return RTL8365MB_MIB_END; 1309 } 1310 1311 static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port, 1312 struct ethtool_eth_phy_stats *phy_stats) 1313 { 1314 struct realtek_priv *priv = ds->priv; 1315 struct rtl8365mb_mib_counter *mib; 1316 struct rtl8365mb *mb; 1317 1318 mb = priv->chip_data; 1319 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors]; 1320 1321 mutex_lock(&mb->mib_lock); 1322 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1323 &phy_stats->SymbolErrorDuringCarrier); 1324 mutex_unlock(&mb->mib_lock); 1325 } 1326 1327 static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, 1328 struct ethtool_eth_mac_stats *mac_stats) 1329 { 1330 u64 cnt[RTL8365MB_MIB_END] = { 1331 [RTL8365MB_MIB_ifOutOctets] = 1, 1332 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1333 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1334 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1335 [RTL8365MB_MIB_dot3OutPauseFrames] = 1, 1336 [RTL8365MB_MIB_ifOutDiscards] = 1, 1337 [RTL8365MB_MIB_ifInOctets] = 1, 1338 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1339 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1340 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1341 [RTL8365MB_MIB_dot3InPauseFrames] = 1, 1342 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1, 1343 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1, 1344 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1345 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1, 1346 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1347 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1, 1348 1349 }; 1350 struct realtek_priv *priv = ds->priv; 1351 struct rtl8365mb *mb; 1352 int ret; 1353 int i; 1354 1355 mb = priv->chip_data; 1356 1357 mutex_lock(&mb->mib_lock); 1358 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1359 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1360 1361 /* Only fetch required MIB counters (marked = 1 above) */ 1362 if (!cnt[i]) 1363 continue; 1364 1365 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1366 mib->length, &cnt[i]); 1367 if (ret) 1368 break; 1369 } 1370 mutex_unlock(&mb->mib_lock); 1371 1372 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into 1373 * IEEE 802.3 Managed Objects. This is not always completely faithful, 1374 * but we try out best. See RFC 3635 for a detailed treatment of the 1375 * subject. 1376 */ 1377 1378 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1379 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1380 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] + 1381 cnt[RTL8365MB_MIB_dot3OutPauseFrames] - 1382 cnt[RTL8365MB_MIB_ifOutDiscards]; 1383 mac_stats->SingleCollisionFrames = 1384 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames]; 1385 mac_stats->MultipleCollisionFrames = 1386 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames]; 1387 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1388 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1389 cnt[RTL8365MB_MIB_ifInBroadcastPkts] + 1390 cnt[RTL8365MB_MIB_dot3InPauseFrames]; 1391 mac_stats->FrameCheckSequenceErrors = 1392 cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1393 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] - 1394 18 * mac_stats->FramesTransmittedOK; 1395 mac_stats->FramesWithDeferredXmissions = 1396 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions]; 1397 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1398 mac_stats->FramesAbortedDueToXSColls = 1399 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions]; 1400 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] - 1401 18 * mac_stats->FramesReceivedOK; 1402 mac_stats->MulticastFramesXmittedOK = 1403 cnt[RTL8365MB_MIB_ifOutMulticastPkts]; 1404 mac_stats->BroadcastFramesXmittedOK = 1405 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1406 mac_stats->MulticastFramesReceivedOK = 1407 cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1408 mac_stats->BroadcastFramesReceivedOK = 1409 cnt[RTL8365MB_MIB_ifInBroadcastPkts]; 1410 } 1411 1412 static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port, 1413 struct ethtool_eth_ctrl_stats *ctrl_stats) 1414 { 1415 struct realtek_priv *priv = ds->priv; 1416 struct rtl8365mb_mib_counter *mib; 1417 struct rtl8365mb *mb; 1418 1419 mb = priv->chip_data; 1420 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes]; 1421 1422 mutex_lock(&mb->mib_lock); 1423 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1424 &ctrl_stats->UnsupportedOpcodesReceived); 1425 mutex_unlock(&mb->mib_lock); 1426 } 1427 1428 static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) 1429 { 1430 u64 cnt[RTL8365MB_MIB_END] = { 1431 [RTL8365MB_MIB_ifOutOctets] = 1, 1432 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1433 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1434 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1435 [RTL8365MB_MIB_ifOutDiscards] = 1, 1436 [RTL8365MB_MIB_ifInOctets] = 1, 1437 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1438 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1439 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1440 [RTL8365MB_MIB_etherStatsDropEvents] = 1, 1441 [RTL8365MB_MIB_etherStatsCollisions] = 1, 1442 [RTL8365MB_MIB_etherStatsFragments] = 1, 1443 [RTL8365MB_MIB_etherStatsJabbers] = 1, 1444 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1445 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1446 }; 1447 struct rtl8365mb *mb = priv->chip_data; 1448 struct rtnl_link_stats64 *stats; 1449 int ret; 1450 int i; 1451 1452 stats = &mb->ports[port].stats; 1453 1454 mutex_lock(&mb->mib_lock); 1455 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1456 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i]; 1457 1458 /* Only fetch required MIB counters (marked = 1 above) */ 1459 if (!cnt[i]) 1460 continue; 1461 1462 ret = rtl8365mb_mib_counter_read(priv, port, c->offset, 1463 c->length, &cnt[i]); 1464 if (ret) 1465 break; 1466 } 1467 mutex_unlock(&mb->mib_lock); 1468 1469 /* Don't update statistics if there was an error reading the counters */ 1470 if (ret) 1471 return; 1472 1473 spin_lock(&mb->ports[port].stats_lock); 1474 1475 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1476 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1477 cnt[RTL8365MB_MIB_ifInBroadcastPkts] - 1478 cnt[RTL8365MB_MIB_ifOutDiscards]; 1479 1480 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1481 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1482 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1483 1484 /* if{In,Out}Octets includes FCS - remove it */ 1485 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets; 1486 stats->tx_bytes = 1487 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets; 1488 1489 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents]; 1490 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards]; 1491 1492 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1493 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions]; 1494 1495 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] + 1496 cnt[RTL8365MB_MIB_etherStatsJabbers]; 1497 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1498 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors; 1499 1500 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards]; 1501 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1502 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors; 1503 1504 spin_unlock(&mb->ports[port].stats_lock); 1505 } 1506 1507 static void rtl8365mb_stats_poll(struct work_struct *work) 1508 { 1509 struct rtl8365mb_port *p = container_of(to_delayed_work(work), 1510 struct rtl8365mb_port, 1511 mib_work); 1512 struct realtek_priv *priv = p->priv; 1513 1514 rtl8365mb_stats_update(priv, p->index); 1515 1516 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); 1517 } 1518 1519 static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, 1520 struct rtnl_link_stats64 *s) 1521 { 1522 struct realtek_priv *priv = ds->priv; 1523 struct rtl8365mb_port *p; 1524 struct rtl8365mb *mb; 1525 1526 mb = priv->chip_data; 1527 p = &mb->ports[port]; 1528 1529 spin_lock(&p->stats_lock); 1530 memcpy(s, &p->stats, sizeof(*s)); 1531 spin_unlock(&p->stats_lock); 1532 } 1533 1534 static void rtl8365mb_stats_setup(struct realtek_priv *priv) 1535 { 1536 struct rtl8365mb *mb = priv->chip_data; 1537 struct dsa_switch *ds = &priv->ds; 1538 int i; 1539 1540 /* Per-chip global mutex to protect MIB counter access, since doing 1541 * so requires accessing a series of registers in a particular order. 1542 */ 1543 mutex_init(&mb->mib_lock); 1544 1545 for (i = 0; i < priv->num_ports; i++) { 1546 struct rtl8365mb_port *p = &mb->ports[i]; 1547 1548 if (dsa_is_unused_port(ds, i)) 1549 continue; 1550 1551 /* Per-port spinlock to protect the stats64 data */ 1552 spin_lock_init(&p->stats_lock); 1553 1554 /* This work polls the MIB counters and keeps the stats64 data 1555 * up-to-date. 1556 */ 1557 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll); 1558 } 1559 } 1560 1561 static void rtl8365mb_stats_teardown(struct realtek_priv *priv) 1562 { 1563 struct rtl8365mb *mb = priv->chip_data; 1564 struct dsa_switch *ds = &priv->ds; 1565 int i; 1566 1567 for (i = 0; i < priv->num_ports; i++) { 1568 struct rtl8365mb_port *p = &mb->ports[i]; 1569 1570 if (dsa_is_unused_port(ds, i)) 1571 continue; 1572 1573 cancel_delayed_work_sync(&p->mib_work); 1574 } 1575 } 1576 1577 static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, 1578 u32 *val) 1579 { 1580 int ret; 1581 1582 ret = regmap_read(priv->map, reg, val); 1583 if (ret) 1584 return ret; 1585 1586 return regmap_write(priv->map, reg, *val); 1587 } 1588 1589 static irqreturn_t rtl8365mb_irq(int irq, void *data) 1590 { 1591 struct realtek_priv *priv = data; 1592 unsigned long line_changes = 0; 1593 u32 stat; 1594 int line; 1595 int ret; 1596 1597 ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG, 1598 &stat); 1599 if (ret) 1600 goto out_error; 1601 1602 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) { 1603 u32 linkdown_ind; 1604 u32 linkup_ind; 1605 u32 val; 1606 1607 ret = rtl8365mb_get_and_clear_status_reg( 1608 priv, RTL8365MB_PORT_LINKUP_IND_REG, &val); 1609 if (ret) 1610 goto out_error; 1611 1612 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val); 1613 1614 ret = rtl8365mb_get_and_clear_status_reg( 1615 priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); 1616 if (ret) 1617 goto out_error; 1618 1619 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val); 1620 1621 line_changes = linkup_ind | linkdown_ind; 1622 } 1623 1624 if (!line_changes) 1625 goto out_none; 1626 1627 for_each_set_bit(line, &line_changes, priv->num_ports) { 1628 int child_irq = irq_find_mapping(priv->irqdomain, line); 1629 1630 handle_nested_irq(child_irq); 1631 } 1632 1633 return IRQ_HANDLED; 1634 1635 out_error: 1636 dev_err(priv->dev, "failed to read interrupt status: %d\n", ret); 1637 1638 out_none: 1639 return IRQ_NONE; 1640 } 1641 1642 static struct irq_chip rtl8365mb_irq_chip = { 1643 .name = "rtl8365mb", 1644 /* The hardware doesn't support masking IRQs on a per-port basis */ 1645 }; 1646 1647 static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq, 1648 irq_hw_number_t hwirq) 1649 { 1650 irq_set_chip_data(irq, domain->host_data); 1651 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq); 1652 irq_set_nested_thread(irq, 1); 1653 irq_set_noprobe(irq); 1654 1655 return 0; 1656 } 1657 1658 static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq) 1659 { 1660 irq_set_nested_thread(irq, 0); 1661 irq_set_chip_and_handler(irq, NULL, NULL); 1662 irq_set_chip_data(irq, NULL); 1663 } 1664 1665 static const struct irq_domain_ops rtl8365mb_irqdomain_ops = { 1666 .map = rtl8365mb_irq_map, 1667 .unmap = rtl8365mb_irq_unmap, 1668 .xlate = irq_domain_xlate_onecell, 1669 }; 1670 1671 static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable) 1672 { 1673 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, 1674 RTL8365MB_INTR_LINK_CHANGE_MASK, 1675 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK, 1676 enable ? 1 : 0)); 1677 } 1678 1679 static int rtl8365mb_irq_enable(struct realtek_priv *priv) 1680 { 1681 return rtl8365mb_set_irq_enable(priv, true); 1682 } 1683 1684 static int rtl8365mb_irq_disable(struct realtek_priv *priv) 1685 { 1686 return rtl8365mb_set_irq_enable(priv, false); 1687 } 1688 1689 static int rtl8365mb_irq_setup(struct realtek_priv *priv) 1690 { 1691 struct rtl8365mb *mb = priv->chip_data; 1692 struct device_node *intc; 1693 u32 irq_trig; 1694 int virq; 1695 int irq; 1696 u32 val; 1697 int ret; 1698 int i; 1699 1700 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); 1701 if (!intc) { 1702 dev_err(priv->dev, "missing child interrupt-controller node\n"); 1703 return -EINVAL; 1704 } 1705 1706 /* rtl8365mb IRQs cascade off this one */ 1707 irq = of_irq_get(intc, 0); 1708 if (irq <= 0) { 1709 if (irq != -EPROBE_DEFER) 1710 dev_err(priv->dev, "failed to get parent irq: %d\n", 1711 irq); 1712 ret = irq ? irq : -EINVAL; 1713 goto out_put_node; 1714 } 1715 1716 priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports, 1717 &rtl8365mb_irqdomain_ops, priv); 1718 if (!priv->irqdomain) { 1719 dev_err(priv->dev, "failed to add irq domain\n"); 1720 ret = -ENOMEM; 1721 goto out_put_node; 1722 } 1723 1724 for (i = 0; i < priv->num_ports; i++) { 1725 virq = irq_create_mapping(priv->irqdomain, i); 1726 if (!virq) { 1727 dev_err(priv->dev, 1728 "failed to create irq domain mapping\n"); 1729 ret = -EINVAL; 1730 goto out_remove_irqdomain; 1731 } 1732 1733 irq_set_parent(virq, irq); 1734 } 1735 1736 /* Configure chip interrupt signal polarity */ 1737 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1738 switch (irq_trig) { 1739 case IRQF_TRIGGER_RISING: 1740 case IRQF_TRIGGER_HIGH: 1741 val = RTL8365MB_INTR_POLARITY_HIGH; 1742 break; 1743 case IRQF_TRIGGER_FALLING: 1744 case IRQF_TRIGGER_LOW: 1745 val = RTL8365MB_INTR_POLARITY_LOW; 1746 break; 1747 default: 1748 dev_err(priv->dev, "unsupported irq trigger type %u\n", 1749 irq_trig); 1750 ret = -EINVAL; 1751 goto out_remove_irqdomain; 1752 } 1753 1754 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, 1755 RTL8365MB_INTR_POLARITY_MASK, 1756 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val)); 1757 if (ret) 1758 goto out_remove_irqdomain; 1759 1760 /* Disable the interrupt in case the chip has it enabled on reset */ 1761 ret = rtl8365mb_irq_disable(priv); 1762 if (ret) 1763 goto out_remove_irqdomain; 1764 1765 /* Clear the interrupt status register */ 1766 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, 1767 RTL8365MB_INTR_ALL_MASK); 1768 if (ret) 1769 goto out_remove_irqdomain; 1770 1771 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, 1772 "rtl8365mb", priv); 1773 if (ret) { 1774 dev_err(priv->dev, "failed to request irq: %d\n", ret); 1775 goto out_remove_irqdomain; 1776 } 1777 1778 /* Store the irq so that we know to free it during teardown */ 1779 mb->irq = irq; 1780 1781 ret = rtl8365mb_irq_enable(priv); 1782 if (ret) 1783 goto out_free_irq; 1784 1785 of_node_put(intc); 1786 1787 return 0; 1788 1789 out_free_irq: 1790 free_irq(mb->irq, priv); 1791 mb->irq = 0; 1792 1793 out_remove_irqdomain: 1794 for (i = 0; i < priv->num_ports; i++) { 1795 virq = irq_find_mapping(priv->irqdomain, i); 1796 irq_dispose_mapping(virq); 1797 } 1798 1799 irq_domain_remove(priv->irqdomain); 1800 priv->irqdomain = NULL; 1801 1802 out_put_node: 1803 of_node_put(intc); 1804 1805 return ret; 1806 } 1807 1808 static void rtl8365mb_irq_teardown(struct realtek_priv *priv) 1809 { 1810 struct rtl8365mb *mb = priv->chip_data; 1811 int virq; 1812 int i; 1813 1814 if (mb->irq) { 1815 free_irq(mb->irq, priv); 1816 mb->irq = 0; 1817 } 1818 1819 if (priv->irqdomain) { 1820 for (i = 0; i < priv->num_ports; i++) { 1821 virq = irq_find_mapping(priv->irqdomain, i); 1822 irq_dispose_mapping(virq); 1823 } 1824 1825 irq_domain_remove(priv->irqdomain); 1826 priv->irqdomain = NULL; 1827 } 1828 } 1829 1830 static int rtl8365mb_cpu_config(struct realtek_priv *priv) 1831 { 1832 struct rtl8365mb *mb = priv->chip_data; 1833 struct rtl8365mb_cpu *cpu = &mb->cpu; 1834 u32 val; 1835 int ret; 1836 1837 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, 1838 RTL8365MB_CPU_PORT_MASK_MASK, 1839 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK, 1840 cpu->mask)); 1841 if (ret) 1842 return ret; 1843 1844 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | 1845 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | 1846 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | 1847 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | 1848 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | 1849 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) | 1850 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK, 1851 cpu->trap_port >> 3 & 0x1); 1852 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); 1853 if (ret) 1854 return ret; 1855 1856 return 0; 1857 } 1858 1859 static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds, 1860 enum dsa_tag_protocol proto) 1861 { 1862 struct realtek_priv *priv = ds->priv; 1863 struct rtl8365mb_cpu *cpu; 1864 struct rtl8365mb *mb; 1865 1866 mb = priv->chip_data; 1867 cpu = &mb->cpu; 1868 1869 switch (proto) { 1870 case DSA_TAG_PROTO_RTL8_4: 1871 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; 1872 cpu->position = RTL8365MB_CPU_POS_AFTER_SA; 1873 break; 1874 case DSA_TAG_PROTO_RTL8_4T: 1875 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; 1876 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC; 1877 break; 1878 /* The switch also supports a 4-byte format, similar to rtl4a but with 1879 * the same 0x04 8-bit version and probably 8-bit port source/dest. 1880 * There is no public doc about it. Not supported yet and it will probably 1881 * never be. 1882 */ 1883 default: 1884 return -EPROTONOSUPPORT; 1885 } 1886 1887 return rtl8365mb_cpu_config(priv); 1888 } 1889 1890 static int rtl8365mb_switch_init(struct realtek_priv *priv) 1891 { 1892 struct rtl8365mb *mb = priv->chip_data; 1893 const struct rtl8365mb_chip_info *ci; 1894 int ret; 1895 int i; 1896 1897 ci = mb->chip_info; 1898 1899 /* Do any chip-specific init jam before getting to the common stuff */ 1900 if (ci->jam_table) { 1901 for (i = 0; i < ci->jam_size; i++) { 1902 ret = regmap_write(priv->map, ci->jam_table[i].reg, 1903 ci->jam_table[i].val); 1904 if (ret) 1905 return ret; 1906 } 1907 } 1908 1909 /* Common init jam */ 1910 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) { 1911 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, 1912 rtl8365mb_init_jam_common[i].val); 1913 if (ret) 1914 return ret; 1915 } 1916 1917 return 0; 1918 } 1919 1920 static int rtl8365mb_reset_chip(struct realtek_priv *priv) 1921 { 1922 u32 val; 1923 1924 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, 1925 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1)); 1926 1927 /* Realtek documentation says the chip needs 1 second to reset. Sleep 1928 * for 100 ms before accessing any registers to prevent ACK timeouts. 1929 */ 1930 msleep(100); 1931 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, 1932 !(val & RTL8365MB_CHIP_RESET_HW_MASK), 1933 20000, 1e6); 1934 } 1935 1936 static int rtl8365mb_setup(struct dsa_switch *ds) 1937 { 1938 struct realtek_priv *priv = ds->priv; 1939 struct rtl8365mb_cpu *cpu; 1940 struct dsa_port *cpu_dp; 1941 struct rtl8365mb *mb; 1942 int ret; 1943 int i; 1944 1945 mb = priv->chip_data; 1946 cpu = &mb->cpu; 1947 1948 ret = rtl8365mb_reset_chip(priv); 1949 if (ret) { 1950 dev_err(priv->dev, "failed to reset chip: %d\n", ret); 1951 goto out_error; 1952 } 1953 1954 /* Configure switch to vendor-defined initial state */ 1955 ret = rtl8365mb_switch_init(priv); 1956 if (ret) { 1957 dev_err(priv->dev, "failed to initialize switch: %d\n", ret); 1958 goto out_error; 1959 } 1960 1961 /* Set up cascading IRQs */ 1962 ret = rtl8365mb_irq_setup(priv); 1963 if (ret == -EPROBE_DEFER) 1964 return ret; 1965 else if (ret) 1966 dev_info(priv->dev, "no interrupt support\n"); 1967 1968 /* Configure CPU tagging */ 1969 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 1970 cpu->mask |= BIT(cpu_dp->index); 1971 1972 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS) 1973 cpu->trap_port = cpu_dp->index; 1974 } 1975 cpu->enable = cpu->mask > 0; 1976 ret = rtl8365mb_cpu_config(priv); 1977 if (ret) 1978 goto out_teardown_irq; 1979 1980 /* Configure ports */ 1981 for (i = 0; i < priv->num_ports; i++) { 1982 struct rtl8365mb_port *p = &mb->ports[i]; 1983 1984 if (dsa_is_unused_port(ds, i)) 1985 continue; 1986 1987 /* Forward only to the CPU */ 1988 ret = rtl8365mb_port_set_isolation(priv, i, cpu->mask); 1989 if (ret) 1990 goto out_teardown_irq; 1991 1992 /* Disable learning */ 1993 ret = rtl8365mb_port_set_learning(priv, i, false); 1994 if (ret) 1995 goto out_teardown_irq; 1996 1997 /* Set the initial STP state of all ports to DISABLED, otherwise 1998 * ports will still forward frames to the CPU despite being 1999 * administratively down by default. 2000 */ 2001 rtl8365mb_port_stp_state_set(ds, i, BR_STATE_DISABLED); 2002 2003 /* Set up per-port private data */ 2004 p->priv = priv; 2005 p->index = i; 2006 } 2007 2008 ret = rtl8365mb_port_change_mtu(ds, cpu->trap_port, ETH_DATA_LEN); 2009 if (ret) 2010 goto out_teardown_irq; 2011 2012 ret = rtl83xx_setup_user_mdio(ds); 2013 if (ret) { 2014 dev_err(priv->dev, "could not set up MDIO bus\n"); 2015 goto out_teardown_irq; 2016 } 2017 2018 /* Start statistics counter polling */ 2019 rtl8365mb_stats_setup(priv); 2020 2021 return 0; 2022 2023 out_teardown_irq: 2024 rtl8365mb_irq_teardown(priv); 2025 2026 out_error: 2027 return ret; 2028 } 2029 2030 static void rtl8365mb_teardown(struct dsa_switch *ds) 2031 { 2032 struct realtek_priv *priv = ds->priv; 2033 2034 rtl8365mb_stats_teardown(priv); 2035 rtl8365mb_irq_teardown(priv); 2036 } 2037 2038 static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) 2039 { 2040 int ret; 2041 2042 /* For some reason we have to write a magic value to an arbitrary 2043 * register whenever accessing the chip ID/version registers. 2044 */ 2045 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE); 2046 if (ret) 2047 return ret; 2048 2049 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id); 2050 if (ret) 2051 return ret; 2052 2053 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver); 2054 if (ret) 2055 return ret; 2056 2057 /* Reset magic register */ 2058 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0); 2059 if (ret) 2060 return ret; 2061 2062 return 0; 2063 } 2064 2065 static int rtl8365mb_detect(struct realtek_priv *priv) 2066 { 2067 struct rtl8365mb *mb = priv->chip_data; 2068 u32 chip_id; 2069 u32 chip_ver; 2070 int ret; 2071 int i; 2072 2073 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); 2074 if (ret) { 2075 dev_err(priv->dev, "failed to read chip id and version: %d\n", 2076 ret); 2077 return ret; 2078 } 2079 2080 for (i = 0; i < ARRAY_SIZE(rtl8365mb_chip_infos); i++) { 2081 const struct rtl8365mb_chip_info *ci = &rtl8365mb_chip_infos[i]; 2082 2083 if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) { 2084 mb->chip_info = ci; 2085 break; 2086 } 2087 } 2088 2089 if (!mb->chip_info) { 2090 dev_err(priv->dev, 2091 "unrecognized switch (id=0x%04x, ver=0x%04x)", chip_id, 2092 chip_ver); 2093 return -ENODEV; 2094 } 2095 2096 dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name); 2097 2098 priv->num_ports = RTL8365MB_MAX_NUM_PORTS; 2099 mb->priv = priv; 2100 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS; 2101 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; 2102 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA; 2103 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; 2104 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES; 2105 2106 return 0; 2107 } 2108 2109 static const struct dsa_switch_ops rtl8365mb_switch_ops = { 2110 .get_tag_protocol = rtl8365mb_get_tag_protocol, 2111 .change_tag_protocol = rtl8365mb_change_tag_protocol, 2112 .setup = rtl8365mb_setup, 2113 .teardown = rtl8365mb_teardown, 2114 .phylink_get_caps = rtl8365mb_phylink_get_caps, 2115 .phylink_mac_config = rtl8365mb_phylink_mac_config, 2116 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, 2117 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up, 2118 .port_stp_state_set = rtl8365mb_port_stp_state_set, 2119 .get_strings = rtl8365mb_get_strings, 2120 .get_ethtool_stats = rtl8365mb_get_ethtool_stats, 2121 .get_sset_count = rtl8365mb_get_sset_count, 2122 .get_eth_phy_stats = rtl8365mb_get_phy_stats, 2123 .get_eth_mac_stats = rtl8365mb_get_mac_stats, 2124 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, 2125 .get_stats64 = rtl8365mb_get_stats64, 2126 .port_change_mtu = rtl8365mb_port_change_mtu, 2127 .port_max_mtu = rtl8365mb_port_max_mtu, 2128 }; 2129 2130 static const struct realtek_ops rtl8365mb_ops = { 2131 .detect = rtl8365mb_detect, 2132 .phy_read = rtl8365mb_phy_read, 2133 .phy_write = rtl8365mb_phy_write, 2134 }; 2135 2136 const struct realtek_variant rtl8365mb_variant = { 2137 .ds_ops = &rtl8365mb_switch_ops, 2138 .ops = &rtl8365mb_ops, 2139 .clk_delay = 10, 2140 .cmd_read = 0xb9, 2141 .cmd_write = 0xb8, 2142 .chip_data_sz = sizeof(struct rtl8365mb), 2143 }; 2144 2145 static const struct of_device_id rtl8365mb_of_match[] = { 2146 { .compatible = "realtek,rtl8365mb", .data = &rtl8365mb_variant, }, 2147 { /* sentinel */ }, 2148 }; 2149 MODULE_DEVICE_TABLE(of, rtl8365mb_of_match); 2150 2151 static struct platform_driver rtl8365mb_smi_driver = { 2152 .driver = { 2153 .name = "rtl8365mb-smi", 2154 .of_match_table = rtl8365mb_of_match, 2155 }, 2156 .probe = realtek_smi_probe, 2157 .remove_new = realtek_smi_remove, 2158 .shutdown = realtek_smi_shutdown, 2159 }; 2160 2161 static struct mdio_driver rtl8365mb_mdio_driver = { 2162 .mdiodrv.driver = { 2163 .name = "rtl8365mb-mdio", 2164 .of_match_table = rtl8365mb_of_match, 2165 }, 2166 .probe = realtek_mdio_probe, 2167 .remove = realtek_mdio_remove, 2168 .shutdown = realtek_mdio_shutdown, 2169 }; 2170 2171 static int rtl8365mb_init(void) 2172 { 2173 int ret; 2174 2175 ret = realtek_mdio_driver_register(&rtl8365mb_mdio_driver); 2176 if (ret) 2177 return ret; 2178 2179 ret = realtek_smi_driver_register(&rtl8365mb_smi_driver); 2180 if (ret) { 2181 realtek_mdio_driver_unregister(&rtl8365mb_mdio_driver); 2182 return ret; 2183 } 2184 2185 return 0; 2186 } 2187 module_init(rtl8365mb_init); 2188 2189 static void __exit rtl8365mb_exit(void) 2190 { 2191 realtek_smi_driver_unregister(&rtl8365mb_smi_driver); 2192 realtek_mdio_driver_unregister(&rtl8365mb_mdio_driver); 2193 } 2194 module_exit(rtl8365mb_exit); 2195 2196 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>"); 2197 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch"); 2198 MODULE_LICENSE("GPL"); 2199 MODULE_IMPORT_NS(REALTEK_DSA); 2200