1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2531c4f89SJeff Kirsher #ifndef _ACENIC_H_
3531c4f89SJeff Kirsher #define _ACENIC_H_
4531c4f89SJeff Kirsher #include <linux/interrupt.h>
5531c4f89SJeff Kirsher
6531c4f89SJeff Kirsher
7531c4f89SJeff Kirsher /*
8531c4f89SJeff Kirsher * Generate TX index update each time, when TX ring is closed.
9531c4f89SJeff Kirsher * Normally, this is not useful, because results in more dma (and irqs
10531c4f89SJeff Kirsher * without TX_COAL_INTS_ONLY).
11531c4f89SJeff Kirsher */
12531c4f89SJeff Kirsher #define USE_TX_COAL_NOW 0
13531c4f89SJeff Kirsher
14531c4f89SJeff Kirsher /*
15531c4f89SJeff Kirsher * Addressing:
16531c4f89SJeff Kirsher *
17531c4f89SJeff Kirsher * The Tigon uses 64-bit host addresses, regardless of their actual
18531c4f89SJeff Kirsher * length, and it expects a big-endian format. For 32 bit systems the
19531c4f89SJeff Kirsher * upper 32 bits of the address are simply ignored (zero), however for
20531c4f89SJeff Kirsher * little endian 64 bit systems (Alpha) this looks strange with the
21531c4f89SJeff Kirsher * two parts of the address word being swapped.
22531c4f89SJeff Kirsher *
23531c4f89SJeff Kirsher * The addresses are split in two 32 bit words for all architectures
24531c4f89SJeff Kirsher * as some of them are in PCI shared memory and it is necessary to use
25531c4f89SJeff Kirsher * readl/writel to access them.
26531c4f89SJeff Kirsher *
27531c4f89SJeff Kirsher * The addressing code is derived from Pete Wyckoff's work, but
28531c4f89SJeff Kirsher * modified to deal properly with readl/writel usage.
29531c4f89SJeff Kirsher */
30531c4f89SJeff Kirsher
31531c4f89SJeff Kirsher struct ace_regs {
32531c4f89SJeff Kirsher u32 pad0[16]; /* PCI control registers */
33531c4f89SJeff Kirsher
34531c4f89SJeff Kirsher u32 HostCtrl; /* 0x40 */
35531c4f89SJeff Kirsher u32 LocalCtrl;
36531c4f89SJeff Kirsher
37531c4f89SJeff Kirsher u32 pad1[2];
38531c4f89SJeff Kirsher
39531c4f89SJeff Kirsher u32 MiscCfg; /* 0x50 */
40531c4f89SJeff Kirsher
41531c4f89SJeff Kirsher u32 pad2[2];
42531c4f89SJeff Kirsher
43531c4f89SJeff Kirsher u32 PciState;
44531c4f89SJeff Kirsher
45531c4f89SJeff Kirsher u32 pad3[2]; /* 0x60 */
46531c4f89SJeff Kirsher
47531c4f89SJeff Kirsher u32 WinBase;
48531c4f89SJeff Kirsher u32 WinData;
49531c4f89SJeff Kirsher
50531c4f89SJeff Kirsher u32 pad4[12]; /* 0x70 */
51531c4f89SJeff Kirsher
52531c4f89SJeff Kirsher u32 DmaWriteState; /* 0xa0 */
53531c4f89SJeff Kirsher u32 pad5[3];
54531c4f89SJeff Kirsher u32 DmaReadState; /* 0xb0 */
55531c4f89SJeff Kirsher
56531c4f89SJeff Kirsher u32 pad6[26];
57531c4f89SJeff Kirsher
58531c4f89SJeff Kirsher u32 AssistState;
59531c4f89SJeff Kirsher
60531c4f89SJeff Kirsher u32 pad7[8]; /* 0x120 */
61531c4f89SJeff Kirsher
62531c4f89SJeff Kirsher u32 CpuCtrl; /* 0x140 */
63531c4f89SJeff Kirsher u32 Pc;
64531c4f89SJeff Kirsher
65531c4f89SJeff Kirsher u32 pad8[3];
66531c4f89SJeff Kirsher
67531c4f89SJeff Kirsher u32 SramAddr; /* 0x154 */
68531c4f89SJeff Kirsher u32 SramData;
69531c4f89SJeff Kirsher
70531c4f89SJeff Kirsher u32 pad9[49];
71531c4f89SJeff Kirsher
72531c4f89SJeff Kirsher u32 MacRxState; /* 0x220 */
73531c4f89SJeff Kirsher
74531c4f89SJeff Kirsher u32 pad10[7];
75531c4f89SJeff Kirsher
76531c4f89SJeff Kirsher u32 CpuBCtrl; /* 0x240 */
77531c4f89SJeff Kirsher u32 PcB;
78531c4f89SJeff Kirsher
79531c4f89SJeff Kirsher u32 pad11[3];
80531c4f89SJeff Kirsher
81531c4f89SJeff Kirsher u32 SramBAddr; /* 0x254 */
82531c4f89SJeff Kirsher u32 SramBData;
83531c4f89SJeff Kirsher
84531c4f89SJeff Kirsher u32 pad12[105];
85531c4f89SJeff Kirsher
86531c4f89SJeff Kirsher u32 pad13[32]; /* 0x400 */
87531c4f89SJeff Kirsher u32 Stats[32];
88531c4f89SJeff Kirsher
89531c4f89SJeff Kirsher u32 Mb0Hi; /* 0x500 */
90531c4f89SJeff Kirsher u32 Mb0Lo;
91531c4f89SJeff Kirsher u32 Mb1Hi;
92531c4f89SJeff Kirsher u32 CmdPrd;
93531c4f89SJeff Kirsher u32 Mb2Hi;
94531c4f89SJeff Kirsher u32 TxPrd;
95531c4f89SJeff Kirsher u32 Mb3Hi;
96531c4f89SJeff Kirsher u32 RxStdPrd;
97531c4f89SJeff Kirsher u32 Mb4Hi;
98531c4f89SJeff Kirsher u32 RxJumboPrd;
99531c4f89SJeff Kirsher u32 Mb5Hi;
100531c4f89SJeff Kirsher u32 RxMiniPrd;
101531c4f89SJeff Kirsher u32 Mb6Hi;
102531c4f89SJeff Kirsher u32 Mb6Lo;
103531c4f89SJeff Kirsher u32 Mb7Hi;
104531c4f89SJeff Kirsher u32 Mb7Lo;
105531c4f89SJeff Kirsher u32 Mb8Hi;
106531c4f89SJeff Kirsher u32 Mb8Lo;
107531c4f89SJeff Kirsher u32 Mb9Hi;
108531c4f89SJeff Kirsher u32 Mb9Lo;
109531c4f89SJeff Kirsher u32 MbAHi;
110531c4f89SJeff Kirsher u32 MbALo;
111531c4f89SJeff Kirsher u32 MbBHi;
112531c4f89SJeff Kirsher u32 MbBLo;
113531c4f89SJeff Kirsher u32 MbCHi;
114531c4f89SJeff Kirsher u32 MbCLo;
115531c4f89SJeff Kirsher u32 MbDHi;
116531c4f89SJeff Kirsher u32 MbDLo;
117531c4f89SJeff Kirsher u32 MbEHi;
118531c4f89SJeff Kirsher u32 MbELo;
119531c4f89SJeff Kirsher u32 MbFHi;
120531c4f89SJeff Kirsher u32 MbFLo;
121531c4f89SJeff Kirsher
122531c4f89SJeff Kirsher u32 pad14[32];
123531c4f89SJeff Kirsher
124531c4f89SJeff Kirsher u32 MacAddrHi; /* 0x600 */
125531c4f89SJeff Kirsher u32 MacAddrLo;
126531c4f89SJeff Kirsher u32 InfoPtrHi;
127531c4f89SJeff Kirsher u32 InfoPtrLo;
128531c4f89SJeff Kirsher u32 MultiCastHi; /* 0x610 */
129531c4f89SJeff Kirsher u32 MultiCastLo;
130531c4f89SJeff Kirsher u32 ModeStat;
131531c4f89SJeff Kirsher u32 DmaReadCfg;
132531c4f89SJeff Kirsher u32 DmaWriteCfg; /* 0x620 */
133531c4f89SJeff Kirsher u32 TxBufRat;
134531c4f89SJeff Kirsher u32 EvtCsm;
135531c4f89SJeff Kirsher u32 CmdCsm;
136531c4f89SJeff Kirsher u32 TuneRxCoalTicks;/* 0x630 */
137531c4f89SJeff Kirsher u32 TuneTxCoalTicks;
138531c4f89SJeff Kirsher u32 TuneStatTicks;
139531c4f89SJeff Kirsher u32 TuneMaxTxDesc;
140531c4f89SJeff Kirsher u32 TuneMaxRxDesc; /* 0x640 */
141531c4f89SJeff Kirsher u32 TuneTrace;
142531c4f89SJeff Kirsher u32 TuneLink;
143531c4f89SJeff Kirsher u32 TuneFastLink;
144531c4f89SJeff Kirsher u32 TracePtr; /* 0x650 */
145531c4f89SJeff Kirsher u32 TraceStrt;
146531c4f89SJeff Kirsher u32 TraceLen;
147531c4f89SJeff Kirsher u32 IfIdx;
148531c4f89SJeff Kirsher u32 IfMtu; /* 0x660 */
149531c4f89SJeff Kirsher u32 MaskInt;
150531c4f89SJeff Kirsher u32 GigLnkState;
151531c4f89SJeff Kirsher u32 FastLnkState;
152531c4f89SJeff Kirsher u32 pad16[4]; /* 0x670 */
153531c4f89SJeff Kirsher u32 RxRetCsm; /* 0x680 */
154531c4f89SJeff Kirsher
155531c4f89SJeff Kirsher u32 pad17[31];
156531c4f89SJeff Kirsher
157531c4f89SJeff Kirsher u32 CmdRng[64]; /* 0x700 */
158531c4f89SJeff Kirsher u32 Window[0x200];
159531c4f89SJeff Kirsher };
160531c4f89SJeff Kirsher
161531c4f89SJeff Kirsher
162531c4f89SJeff Kirsher typedef struct {
163531c4f89SJeff Kirsher u32 addrhi;
164531c4f89SJeff Kirsher u32 addrlo;
165531c4f89SJeff Kirsher } aceaddr;
166531c4f89SJeff Kirsher
167531c4f89SJeff Kirsher
168531c4f89SJeff Kirsher #define ACE_WINDOW_SIZE 0x800
169531c4f89SJeff Kirsher
170531c4f89SJeff Kirsher #define ACE_JUMBO_MTU 9000
171531c4f89SJeff Kirsher #define ACE_STD_MTU 1500
172531c4f89SJeff Kirsher
173531c4f89SJeff Kirsher #define ACE_TRACE_SIZE 0x8000
174531c4f89SJeff Kirsher
175531c4f89SJeff Kirsher /*
176531c4f89SJeff Kirsher * Host control register bits.
177531c4f89SJeff Kirsher */
178531c4f89SJeff Kirsher
179531c4f89SJeff Kirsher #define IN_INT 0x01
180531c4f89SJeff Kirsher #define CLR_INT 0x02
181531c4f89SJeff Kirsher #define HW_RESET 0x08
182531c4f89SJeff Kirsher #define BYTE_SWAP 0x10
183531c4f89SJeff Kirsher #define WORD_SWAP 0x20
184531c4f89SJeff Kirsher #define MASK_INTS 0x40
185531c4f89SJeff Kirsher
186531c4f89SJeff Kirsher /*
187531c4f89SJeff Kirsher * Local control register bits.
188531c4f89SJeff Kirsher */
189531c4f89SJeff Kirsher
190531c4f89SJeff Kirsher #define EEPROM_DATA_IN 0x800000
191531c4f89SJeff Kirsher #define EEPROM_DATA_OUT 0x400000
192531c4f89SJeff Kirsher #define EEPROM_WRITE_ENABLE 0x200000
193531c4f89SJeff Kirsher #define EEPROM_CLK_OUT 0x100000
194531c4f89SJeff Kirsher
195531c4f89SJeff Kirsher #define EEPROM_BASE 0xa0000000
196531c4f89SJeff Kirsher
197531c4f89SJeff Kirsher #define EEPROM_WRITE_SELECT 0xa0
198531c4f89SJeff Kirsher #define EEPROM_READ_SELECT 0xa1
199531c4f89SJeff Kirsher
200531c4f89SJeff Kirsher #define SRAM_BANK_512K 0x200
201531c4f89SJeff Kirsher
202531c4f89SJeff Kirsher
203531c4f89SJeff Kirsher /*
204531c4f89SJeff Kirsher * udelay() values for when clocking the eeprom
205531c4f89SJeff Kirsher */
206531c4f89SJeff Kirsher #define ACE_SHORT_DELAY 2
207531c4f89SJeff Kirsher #define ACE_LONG_DELAY 4
208531c4f89SJeff Kirsher
209531c4f89SJeff Kirsher
210531c4f89SJeff Kirsher /*
211531c4f89SJeff Kirsher * Misc Config bits
212531c4f89SJeff Kirsher */
213531c4f89SJeff Kirsher
214531c4f89SJeff Kirsher #define SYNC_SRAM_TIMING 0x100000
215531c4f89SJeff Kirsher
216531c4f89SJeff Kirsher
217531c4f89SJeff Kirsher /*
218531c4f89SJeff Kirsher * CPU state bits.
219531c4f89SJeff Kirsher */
220531c4f89SJeff Kirsher
221531c4f89SJeff Kirsher #define CPU_RESET 0x01
222531c4f89SJeff Kirsher #define CPU_TRACE 0x02
223531c4f89SJeff Kirsher #define CPU_PROM_FAILED 0x10
224531c4f89SJeff Kirsher #define CPU_HALT 0x00010000
225531c4f89SJeff Kirsher #define CPU_HALTED 0xffff0000
226531c4f89SJeff Kirsher
227531c4f89SJeff Kirsher
228531c4f89SJeff Kirsher /*
229531c4f89SJeff Kirsher * PCI State bits.
230531c4f89SJeff Kirsher */
231531c4f89SJeff Kirsher
232531c4f89SJeff Kirsher #define DMA_READ_MAX_4 0x04
233531c4f89SJeff Kirsher #define DMA_READ_MAX_16 0x08
234531c4f89SJeff Kirsher #define DMA_READ_MAX_32 0x0c
235531c4f89SJeff Kirsher #define DMA_READ_MAX_64 0x10
236531c4f89SJeff Kirsher #define DMA_READ_MAX_128 0x14
237531c4f89SJeff Kirsher #define DMA_READ_MAX_256 0x18
238531c4f89SJeff Kirsher #define DMA_READ_MAX_1K 0x1c
239531c4f89SJeff Kirsher #define DMA_WRITE_MAX_4 0x20
240531c4f89SJeff Kirsher #define DMA_WRITE_MAX_16 0x40
241531c4f89SJeff Kirsher #define DMA_WRITE_MAX_32 0x60
242531c4f89SJeff Kirsher #define DMA_WRITE_MAX_64 0x80
243531c4f89SJeff Kirsher #define DMA_WRITE_MAX_128 0xa0
244531c4f89SJeff Kirsher #define DMA_WRITE_MAX_256 0xc0
245531c4f89SJeff Kirsher #define DMA_WRITE_MAX_1K 0xe0
246531c4f89SJeff Kirsher #define DMA_READ_WRITE_MASK 0xfc
247531c4f89SJeff Kirsher #define MEM_READ_MULTIPLE 0x00020000
248531c4f89SJeff Kirsher #define PCI_66MHZ 0x00080000
249531c4f89SJeff Kirsher #define PCI_32BIT 0x00100000
250531c4f89SJeff Kirsher #define DMA_WRITE_ALL_ALIGN 0x00800000
251531c4f89SJeff Kirsher #define READ_CMD_MEM 0x06000000
252531c4f89SJeff Kirsher #define WRITE_CMD_MEM 0x70000000
253531c4f89SJeff Kirsher
254531c4f89SJeff Kirsher
255531c4f89SJeff Kirsher /*
256531c4f89SJeff Kirsher * Mode status
257531c4f89SJeff Kirsher */
258531c4f89SJeff Kirsher
259531c4f89SJeff Kirsher #define ACE_BYTE_SWAP_BD 0x02
260531c4f89SJeff Kirsher #define ACE_WORD_SWAP_BD 0x04 /* not actually used */
261531c4f89SJeff Kirsher #define ACE_WARN 0x08
262531c4f89SJeff Kirsher #define ACE_BYTE_SWAP_DMA 0x10
263531c4f89SJeff Kirsher #define ACE_NO_JUMBO_FRAG 0x200
264531c4f89SJeff Kirsher #define ACE_FATAL 0x40000000
265531c4f89SJeff Kirsher
266531c4f89SJeff Kirsher
267531c4f89SJeff Kirsher /*
268531c4f89SJeff Kirsher * DMA config
269531c4f89SJeff Kirsher */
270531c4f89SJeff Kirsher
271531c4f89SJeff Kirsher #define DMA_THRESH_1W 0x10
272531c4f89SJeff Kirsher #define DMA_THRESH_2W 0x20
273531c4f89SJeff Kirsher #define DMA_THRESH_4W 0x40
274531c4f89SJeff Kirsher #define DMA_THRESH_8W 0x80
275531c4f89SJeff Kirsher #define DMA_THRESH_16W 0x100
276531c4f89SJeff Kirsher #define DMA_THRESH_32W 0x0 /* not described in doc, but exists. */
277531c4f89SJeff Kirsher
278531c4f89SJeff Kirsher
279531c4f89SJeff Kirsher /*
280531c4f89SJeff Kirsher * Tuning parameters
281531c4f89SJeff Kirsher */
282531c4f89SJeff Kirsher
283531c4f89SJeff Kirsher #define TICKS_PER_SEC 1000000
284531c4f89SJeff Kirsher
285531c4f89SJeff Kirsher
286531c4f89SJeff Kirsher /*
287531c4f89SJeff Kirsher * Link bits
288531c4f89SJeff Kirsher */
289531c4f89SJeff Kirsher
290531c4f89SJeff Kirsher #define LNK_PREF 0x00008000
291531c4f89SJeff Kirsher #define LNK_10MB 0x00010000
292531c4f89SJeff Kirsher #define LNK_100MB 0x00020000
293531c4f89SJeff Kirsher #define LNK_1000MB 0x00040000
294531c4f89SJeff Kirsher #define LNK_FULL_DUPLEX 0x00080000
295531c4f89SJeff Kirsher #define LNK_HALF_DUPLEX 0x00100000
296531c4f89SJeff Kirsher #define LNK_TX_FLOW_CTL_Y 0x00200000
297531c4f89SJeff Kirsher #define LNK_NEG_ADVANCED 0x00400000
298531c4f89SJeff Kirsher #define LNK_RX_FLOW_CTL_Y 0x00800000
299531c4f89SJeff Kirsher #define LNK_NIC 0x01000000
300531c4f89SJeff Kirsher #define LNK_JAM 0x02000000
301531c4f89SJeff Kirsher #define LNK_JUMBO 0x04000000
302531c4f89SJeff Kirsher #define LNK_ALTEON 0x08000000
303531c4f89SJeff Kirsher #define LNK_NEG_FCTL 0x10000000
304531c4f89SJeff Kirsher #define LNK_NEGOTIATE 0x20000000
305531c4f89SJeff Kirsher #define LNK_ENABLE 0x40000000
306531c4f89SJeff Kirsher #define LNK_UP 0x80000000
307531c4f89SJeff Kirsher
308531c4f89SJeff Kirsher
309531c4f89SJeff Kirsher /*
310531c4f89SJeff Kirsher * Event definitions
311531c4f89SJeff Kirsher */
312531c4f89SJeff Kirsher
313531c4f89SJeff Kirsher #define EVT_RING_ENTRIES 256
314531c4f89SJeff Kirsher #define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
315531c4f89SJeff Kirsher
316531c4f89SJeff Kirsher struct event {
317531c4f89SJeff Kirsher #ifdef __LITTLE_ENDIAN_BITFIELD
318531c4f89SJeff Kirsher u32 idx:12;
319531c4f89SJeff Kirsher u32 code:12;
320531c4f89SJeff Kirsher u32 evt:8;
321531c4f89SJeff Kirsher #else
322531c4f89SJeff Kirsher u32 evt:8;
323531c4f89SJeff Kirsher u32 code:12;
324531c4f89SJeff Kirsher u32 idx:12;
325531c4f89SJeff Kirsher #endif
326531c4f89SJeff Kirsher u32 pad;
327531c4f89SJeff Kirsher };
328531c4f89SJeff Kirsher
329531c4f89SJeff Kirsher
330531c4f89SJeff Kirsher /*
331531c4f89SJeff Kirsher * Events
332531c4f89SJeff Kirsher */
333531c4f89SJeff Kirsher
334531c4f89SJeff Kirsher #define E_FW_RUNNING 0x01
335531c4f89SJeff Kirsher #define E_STATS_UPDATED 0x04
336531c4f89SJeff Kirsher
337531c4f89SJeff Kirsher #define E_STATS_UPDATE 0x04
338531c4f89SJeff Kirsher
339531c4f89SJeff Kirsher #define E_LNK_STATE 0x06
340531c4f89SJeff Kirsher #define E_C_LINK_UP 0x01
341531c4f89SJeff Kirsher #define E_C_LINK_DOWN 0x02
342531c4f89SJeff Kirsher #define E_C_LINK_10_100 0x03
343531c4f89SJeff Kirsher
344531c4f89SJeff Kirsher #define E_ERROR 0x07
345531c4f89SJeff Kirsher #define E_C_ERR_INVAL_CMD 0x01
346531c4f89SJeff Kirsher #define E_C_ERR_UNIMP_CMD 0x02
347531c4f89SJeff Kirsher #define E_C_ERR_BAD_CFG 0x03
348531c4f89SJeff Kirsher
349531c4f89SJeff Kirsher #define E_MCAST_LIST 0x08
350531c4f89SJeff Kirsher #define E_C_MCAST_ADDR_ADD 0x01
351531c4f89SJeff Kirsher #define E_C_MCAST_ADDR_DEL 0x02
352531c4f89SJeff Kirsher
353531c4f89SJeff Kirsher #define E_RESET_JUMBO_RNG 0x09
354531c4f89SJeff Kirsher
355531c4f89SJeff Kirsher
356531c4f89SJeff Kirsher /*
357531c4f89SJeff Kirsher * Commands
358531c4f89SJeff Kirsher */
359531c4f89SJeff Kirsher
360531c4f89SJeff Kirsher #define CMD_RING_ENTRIES 64
361531c4f89SJeff Kirsher
362531c4f89SJeff Kirsher struct cmd {
363531c4f89SJeff Kirsher #ifdef __LITTLE_ENDIAN_BITFIELD
364531c4f89SJeff Kirsher u32 idx:12;
365531c4f89SJeff Kirsher u32 code:12;
366531c4f89SJeff Kirsher u32 evt:8;
367531c4f89SJeff Kirsher #else
368531c4f89SJeff Kirsher u32 evt:8;
369531c4f89SJeff Kirsher u32 code:12;
370531c4f89SJeff Kirsher u32 idx:12;
371531c4f89SJeff Kirsher #endif
372531c4f89SJeff Kirsher };
373531c4f89SJeff Kirsher
374531c4f89SJeff Kirsher
375531c4f89SJeff Kirsher #define C_HOST_STATE 0x01
376531c4f89SJeff Kirsher #define C_C_STACK_UP 0x01
377531c4f89SJeff Kirsher #define C_C_STACK_DOWN 0x02
378531c4f89SJeff Kirsher
379531c4f89SJeff Kirsher #define C_FDR_FILTERING 0x02
380531c4f89SJeff Kirsher #define C_C_FDR_FILT_ENABLE 0x01
381531c4f89SJeff Kirsher #define C_C_FDR_FILT_DISABLE 0x02
382531c4f89SJeff Kirsher
383531c4f89SJeff Kirsher #define C_SET_RX_PRD_IDX 0x03
384531c4f89SJeff Kirsher #define C_UPDATE_STATS 0x04
385531c4f89SJeff Kirsher #define C_RESET_JUMBO_RNG 0x05
386531c4f89SJeff Kirsher #define C_ADD_MULTICAST_ADDR 0x08
387531c4f89SJeff Kirsher #define C_DEL_MULTICAST_ADDR 0x09
388531c4f89SJeff Kirsher
389531c4f89SJeff Kirsher #define C_SET_PROMISC_MODE 0x0a
390531c4f89SJeff Kirsher #define C_C_PROMISC_ENABLE 0x01
391531c4f89SJeff Kirsher #define C_C_PROMISC_DISABLE 0x02
392531c4f89SJeff Kirsher
393531c4f89SJeff Kirsher #define C_LNK_NEGOTIATION 0x0b
394531c4f89SJeff Kirsher #define C_C_NEGOTIATE_BOTH 0x00
395531c4f89SJeff Kirsher #define C_C_NEGOTIATE_GIG 0x01
396531c4f89SJeff Kirsher #define C_C_NEGOTIATE_10_100 0x02
397531c4f89SJeff Kirsher
398531c4f89SJeff Kirsher #define C_SET_MAC_ADDR 0x0c
399531c4f89SJeff Kirsher #define C_CLEAR_PROFILE 0x0d
400531c4f89SJeff Kirsher
401531c4f89SJeff Kirsher #define C_SET_MULTICAST_MODE 0x0e
402531c4f89SJeff Kirsher #define C_C_MCAST_ENABLE 0x01
403531c4f89SJeff Kirsher #define C_C_MCAST_DISABLE 0x02
404531c4f89SJeff Kirsher
405531c4f89SJeff Kirsher #define C_CLEAR_STATS 0x0f
406531c4f89SJeff Kirsher #define C_SET_RX_JUMBO_PRD_IDX 0x10
407531c4f89SJeff Kirsher #define C_REFRESH_STATS 0x11
408531c4f89SJeff Kirsher
409531c4f89SJeff Kirsher
410531c4f89SJeff Kirsher /*
411531c4f89SJeff Kirsher * Descriptor flags
412531c4f89SJeff Kirsher */
413531c4f89SJeff Kirsher #define BD_FLG_TCP_UDP_SUM 0x01
414531c4f89SJeff Kirsher #define BD_FLG_IP_SUM 0x02
415531c4f89SJeff Kirsher #define BD_FLG_END 0x04
416531c4f89SJeff Kirsher #define BD_FLG_MORE 0x08
417531c4f89SJeff Kirsher #define BD_FLG_JUMBO 0x10
418531c4f89SJeff Kirsher #define BD_FLG_UCAST 0x20
419531c4f89SJeff Kirsher #define BD_FLG_MCAST 0x40
420531c4f89SJeff Kirsher #define BD_FLG_BCAST 0x60
421531c4f89SJeff Kirsher #define BD_FLG_TYP_MASK 0x60
422531c4f89SJeff Kirsher #define BD_FLG_IP_FRAG 0x80
423531c4f89SJeff Kirsher #define BD_FLG_IP_FRAG_END 0x100
424531c4f89SJeff Kirsher #define BD_FLG_VLAN_TAG 0x200
425531c4f89SJeff Kirsher #define BD_FLG_FRAME_ERROR 0x400
426531c4f89SJeff Kirsher #define BD_FLG_COAL_NOW 0x800
427531c4f89SJeff Kirsher #define BD_FLG_MINI 0x1000
428531c4f89SJeff Kirsher
429531c4f89SJeff Kirsher
430531c4f89SJeff Kirsher /*
431531c4f89SJeff Kirsher * Ring Control block flags
432531c4f89SJeff Kirsher */
433531c4f89SJeff Kirsher #define RCB_FLG_TCP_UDP_SUM 0x01
434531c4f89SJeff Kirsher #define RCB_FLG_IP_SUM 0x02
435531c4f89SJeff Kirsher #define RCB_FLG_NO_PSEUDO_HDR 0x08
436531c4f89SJeff Kirsher #define RCB_FLG_VLAN_ASSIST 0x10
437531c4f89SJeff Kirsher #define RCB_FLG_COAL_INT_ONLY 0x20
438531c4f89SJeff Kirsher #define RCB_FLG_TX_HOST_RING 0x40
439531c4f89SJeff Kirsher #define RCB_FLG_IEEE_SNAP_SUM 0x80
440531c4f89SJeff Kirsher #define RCB_FLG_EXT_RX_BD 0x100
441531c4f89SJeff Kirsher #define RCB_FLG_RNG_DISABLE 0x200
442531c4f89SJeff Kirsher
443531c4f89SJeff Kirsher
444531c4f89SJeff Kirsher /*
445531c4f89SJeff Kirsher * TX ring - maximum TX ring entries for Tigon I's is 128
446531c4f89SJeff Kirsher */
447531c4f89SJeff Kirsher #define MAX_TX_RING_ENTRIES 256
448531c4f89SJeff Kirsher #define TIGON_I_TX_RING_ENTRIES 128
449531c4f89SJeff Kirsher #define TX_RING_SIZE (MAX_TX_RING_ENTRIES * sizeof(struct tx_desc))
450531c4f89SJeff Kirsher #define TX_RING_BASE 0x3800
451531c4f89SJeff Kirsher
452531c4f89SJeff Kirsher struct tx_desc{
453531c4f89SJeff Kirsher aceaddr addr;
454531c4f89SJeff Kirsher u32 flagsize;
455531c4f89SJeff Kirsher #if 0
456531c4f89SJeff Kirsher /*
457531c4f89SJeff Kirsher * This is in PCI shared mem and must be accessed with readl/writel
458531c4f89SJeff Kirsher * real layout is:
459531c4f89SJeff Kirsher */
460531c4f89SJeff Kirsher #if __LITTLE_ENDIAN
461531c4f89SJeff Kirsher u16 flags;
462531c4f89SJeff Kirsher u16 size;
463531c4f89SJeff Kirsher u16 vlan;
464531c4f89SJeff Kirsher u16 reserved;
465531c4f89SJeff Kirsher #else
466531c4f89SJeff Kirsher u16 size;
467531c4f89SJeff Kirsher u16 flags;
468531c4f89SJeff Kirsher u16 reserved;
469531c4f89SJeff Kirsher u16 vlan;
470531c4f89SJeff Kirsher #endif
471531c4f89SJeff Kirsher #endif
472531c4f89SJeff Kirsher u32 vlanres;
473531c4f89SJeff Kirsher };
474531c4f89SJeff Kirsher
475531c4f89SJeff Kirsher
476531c4f89SJeff Kirsher #define RX_STD_RING_ENTRIES 512
477531c4f89SJeff Kirsher #define RX_STD_RING_SIZE (RX_STD_RING_ENTRIES * sizeof(struct rx_desc))
478531c4f89SJeff Kirsher
479531c4f89SJeff Kirsher #define RX_JUMBO_RING_ENTRIES 256
480531c4f89SJeff Kirsher #define RX_JUMBO_RING_SIZE (RX_JUMBO_RING_ENTRIES *sizeof(struct rx_desc))
481531c4f89SJeff Kirsher
482531c4f89SJeff Kirsher #define RX_MINI_RING_ENTRIES 1024
483531c4f89SJeff Kirsher #define RX_MINI_RING_SIZE (RX_MINI_RING_ENTRIES *sizeof(struct rx_desc))
484531c4f89SJeff Kirsher
485531c4f89SJeff Kirsher #define RX_RETURN_RING_ENTRIES 2048
486531c4f89SJeff Kirsher #define RX_RETURN_RING_SIZE (RX_MAX_RETURN_RING_ENTRIES * \
487531c4f89SJeff Kirsher sizeof(struct rx_desc))
488531c4f89SJeff Kirsher
489531c4f89SJeff Kirsher struct rx_desc{
490531c4f89SJeff Kirsher aceaddr addr;
491531c4f89SJeff Kirsher #ifdef __LITTLE_ENDIAN
492531c4f89SJeff Kirsher u16 size;
493531c4f89SJeff Kirsher u16 idx;
494531c4f89SJeff Kirsher #else
495531c4f89SJeff Kirsher u16 idx;
496531c4f89SJeff Kirsher u16 size;
497531c4f89SJeff Kirsher #endif
498531c4f89SJeff Kirsher #ifdef __LITTLE_ENDIAN
499531c4f89SJeff Kirsher u16 flags;
500531c4f89SJeff Kirsher u16 type;
501531c4f89SJeff Kirsher #else
502531c4f89SJeff Kirsher u16 type;
503531c4f89SJeff Kirsher u16 flags;
504531c4f89SJeff Kirsher #endif
505531c4f89SJeff Kirsher #ifdef __LITTLE_ENDIAN
506531c4f89SJeff Kirsher u16 tcp_udp_csum;
507531c4f89SJeff Kirsher u16 ip_csum;
508531c4f89SJeff Kirsher #else
509531c4f89SJeff Kirsher u16 ip_csum;
510531c4f89SJeff Kirsher u16 tcp_udp_csum;
511531c4f89SJeff Kirsher #endif
512531c4f89SJeff Kirsher #ifdef __LITTLE_ENDIAN
513531c4f89SJeff Kirsher u16 vlan;
514531c4f89SJeff Kirsher u16 err_flags;
515531c4f89SJeff Kirsher #else
516531c4f89SJeff Kirsher u16 err_flags;
517531c4f89SJeff Kirsher u16 vlan;
518531c4f89SJeff Kirsher #endif
519531c4f89SJeff Kirsher u32 reserved;
520531c4f89SJeff Kirsher u32 opague;
521531c4f89SJeff Kirsher };
522531c4f89SJeff Kirsher
523531c4f89SJeff Kirsher
524531c4f89SJeff Kirsher /*
525531c4f89SJeff Kirsher * This struct is shared with the NIC firmware.
526531c4f89SJeff Kirsher */
527531c4f89SJeff Kirsher struct ring_ctrl {
528531c4f89SJeff Kirsher aceaddr rngptr;
529531c4f89SJeff Kirsher #ifdef __LITTLE_ENDIAN
530531c4f89SJeff Kirsher u16 flags;
531531c4f89SJeff Kirsher u16 max_len;
532531c4f89SJeff Kirsher #else
533531c4f89SJeff Kirsher u16 max_len;
534531c4f89SJeff Kirsher u16 flags;
535531c4f89SJeff Kirsher #endif
536531c4f89SJeff Kirsher u32 pad;
537531c4f89SJeff Kirsher };
538531c4f89SJeff Kirsher
539531c4f89SJeff Kirsher
540531c4f89SJeff Kirsher struct ace_mac_stats {
541531c4f89SJeff Kirsher u32 excess_colls;
542531c4f89SJeff Kirsher u32 coll_1;
543531c4f89SJeff Kirsher u32 coll_2;
544531c4f89SJeff Kirsher u32 coll_3;
545531c4f89SJeff Kirsher u32 coll_4;
546531c4f89SJeff Kirsher u32 coll_5;
547531c4f89SJeff Kirsher u32 coll_6;
548531c4f89SJeff Kirsher u32 coll_7;
549531c4f89SJeff Kirsher u32 coll_8;
550531c4f89SJeff Kirsher u32 coll_9;
551531c4f89SJeff Kirsher u32 coll_10;
552531c4f89SJeff Kirsher u32 coll_11;
553531c4f89SJeff Kirsher u32 coll_12;
554531c4f89SJeff Kirsher u32 coll_13;
555531c4f89SJeff Kirsher u32 coll_14;
556531c4f89SJeff Kirsher u32 coll_15;
557531c4f89SJeff Kirsher u32 late_coll;
558531c4f89SJeff Kirsher u32 defers;
559531c4f89SJeff Kirsher u32 crc_err;
560531c4f89SJeff Kirsher u32 underrun;
561531c4f89SJeff Kirsher u32 crs_err;
562531c4f89SJeff Kirsher u32 pad[3];
563531c4f89SJeff Kirsher u32 drop_ula;
564531c4f89SJeff Kirsher u32 drop_mc;
565531c4f89SJeff Kirsher u32 drop_fc;
566531c4f89SJeff Kirsher u32 drop_space;
567531c4f89SJeff Kirsher u32 coll;
568531c4f89SJeff Kirsher u32 kept_bc;
569531c4f89SJeff Kirsher u32 kept_mc;
570531c4f89SJeff Kirsher u32 kept_uc;
571531c4f89SJeff Kirsher };
572531c4f89SJeff Kirsher
573531c4f89SJeff Kirsher
574531c4f89SJeff Kirsher struct ace_info {
575531c4f89SJeff Kirsher union {
576531c4f89SJeff Kirsher u32 stats[256];
577531c4f89SJeff Kirsher } s;
578531c4f89SJeff Kirsher struct ring_ctrl evt_ctrl;
579531c4f89SJeff Kirsher struct ring_ctrl cmd_ctrl;
580531c4f89SJeff Kirsher struct ring_ctrl tx_ctrl;
581531c4f89SJeff Kirsher struct ring_ctrl rx_std_ctrl;
582531c4f89SJeff Kirsher struct ring_ctrl rx_jumbo_ctrl;
583531c4f89SJeff Kirsher struct ring_ctrl rx_mini_ctrl;
584531c4f89SJeff Kirsher struct ring_ctrl rx_return_ctrl;
585531c4f89SJeff Kirsher aceaddr evt_prd_ptr;
586531c4f89SJeff Kirsher aceaddr rx_ret_prd_ptr;
587531c4f89SJeff Kirsher aceaddr tx_csm_ptr;
588531c4f89SJeff Kirsher aceaddr stats2_ptr;
589531c4f89SJeff Kirsher };
590531c4f89SJeff Kirsher
591531c4f89SJeff Kirsher
592531c4f89SJeff Kirsher struct ring_info {
593531c4f89SJeff Kirsher struct sk_buff *skb;
594531c4f89SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping);
595531c4f89SJeff Kirsher };
596531c4f89SJeff Kirsher
597531c4f89SJeff Kirsher
598531c4f89SJeff Kirsher /*
599531c4f89SJeff Kirsher * Funny... As soon as we add maplen on alpha, it starts to work
600531c4f89SJeff Kirsher * much slower. Hmm... is it because struct does not fit to one cacheline?
601531c4f89SJeff Kirsher * So, split tx_ring_info.
602531c4f89SJeff Kirsher */
603531c4f89SJeff Kirsher struct tx_ring_info {
604531c4f89SJeff Kirsher struct sk_buff *skb;
605531c4f89SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapping);
606531c4f89SJeff Kirsher DEFINE_DMA_UNMAP_LEN(maplen);
607531c4f89SJeff Kirsher };
608531c4f89SJeff Kirsher
609531c4f89SJeff Kirsher
610531c4f89SJeff Kirsher /*
611531c4f89SJeff Kirsher * struct ace_skb holding the rings of skb's. This is an awful lot of
612531c4f89SJeff Kirsher * pointers, but I don't see any other smart mode to do this in an
613531c4f89SJeff Kirsher * efficient manner ;-(
614531c4f89SJeff Kirsher */
615531c4f89SJeff Kirsher struct ace_skb
616531c4f89SJeff Kirsher {
617531c4f89SJeff Kirsher struct tx_ring_info tx_skbuff[MAX_TX_RING_ENTRIES];
618531c4f89SJeff Kirsher struct ring_info rx_std_skbuff[RX_STD_RING_ENTRIES];
619531c4f89SJeff Kirsher struct ring_info rx_mini_skbuff[RX_MINI_RING_ENTRIES];
620531c4f89SJeff Kirsher struct ring_info rx_jumbo_skbuff[RX_JUMBO_RING_ENTRIES];
621531c4f89SJeff Kirsher };
622531c4f89SJeff Kirsher
623531c4f89SJeff Kirsher
624531c4f89SJeff Kirsher /*
625531c4f89SJeff Kirsher * Struct private for the AceNIC.
626531c4f89SJeff Kirsher *
627531c4f89SJeff Kirsher * Elements are grouped so variables used by the tx handling goes
628531c4f89SJeff Kirsher * together, and will go into the same cache lines etc. in order to
629531c4f89SJeff Kirsher * avoid cache line contention between the rx and tx handling on SMP.
630531c4f89SJeff Kirsher *
631531c4f89SJeff Kirsher * Frequently accessed variables are put at the beginning of the
632531c4f89SJeff Kirsher * struct to help the compiler generate better/shorter code.
633531c4f89SJeff Kirsher */
634531c4f89SJeff Kirsher struct ace_private
635531c4f89SJeff Kirsher {
636*9c59cc79SAllen Pais struct net_device *ndev; /* backpointer */
637531c4f89SJeff Kirsher struct ace_info *info;
638531c4f89SJeff Kirsher struct ace_regs __iomem *regs; /* register base */
639531c4f89SJeff Kirsher struct ace_skb *skb;
640531c4f89SJeff Kirsher dma_addr_t info_dma; /* 32/64 bit */
641531c4f89SJeff Kirsher
642531c4f89SJeff Kirsher int version, link;
643531c4f89SJeff Kirsher int promisc, mcast_all;
644531c4f89SJeff Kirsher
645531c4f89SJeff Kirsher /*
646531c4f89SJeff Kirsher * TX elements
647531c4f89SJeff Kirsher */
648531c4f89SJeff Kirsher struct tx_desc *tx_ring;
649531c4f89SJeff Kirsher u32 tx_prd;
650531c4f89SJeff Kirsher volatile u32 tx_ret_csm;
651531c4f89SJeff Kirsher int tx_ring_entries;
652531c4f89SJeff Kirsher
653531c4f89SJeff Kirsher /*
654531c4f89SJeff Kirsher * RX elements
655531c4f89SJeff Kirsher */
656531c4f89SJeff Kirsher unsigned long std_refill_busy
657531c4f89SJeff Kirsher __attribute__ ((aligned (SMP_CACHE_BYTES)));
658531c4f89SJeff Kirsher unsigned long mini_refill_busy, jumbo_refill_busy;
659531c4f89SJeff Kirsher atomic_t cur_rx_bufs;
660531c4f89SJeff Kirsher atomic_t cur_mini_bufs;
661531c4f89SJeff Kirsher atomic_t cur_jumbo_bufs;
662531c4f89SJeff Kirsher u32 rx_std_skbprd, rx_mini_skbprd, rx_jumbo_skbprd;
663531c4f89SJeff Kirsher u32 cur_rx;
664531c4f89SJeff Kirsher
665531c4f89SJeff Kirsher struct rx_desc *rx_std_ring;
666531c4f89SJeff Kirsher struct rx_desc *rx_jumbo_ring;
667531c4f89SJeff Kirsher struct rx_desc *rx_mini_ring;
668531c4f89SJeff Kirsher struct rx_desc *rx_return_ring;
669531c4f89SJeff Kirsher
670531c4f89SJeff Kirsher int tasklet_pending, jumbo;
671531c4f89SJeff Kirsher struct tasklet_struct ace_tasklet;
672531c4f89SJeff Kirsher
673531c4f89SJeff Kirsher struct event *evt_ring;
674531c4f89SJeff Kirsher
675531c4f89SJeff Kirsher volatile u32 *evt_prd, *rx_ret_prd, *tx_csm;
676531c4f89SJeff Kirsher
677531c4f89SJeff Kirsher dma_addr_t tx_ring_dma; /* 32/64 bit */
678531c4f89SJeff Kirsher dma_addr_t rx_ring_base_dma;
679531c4f89SJeff Kirsher dma_addr_t evt_ring_dma;
680531c4f89SJeff Kirsher dma_addr_t evt_prd_dma, rx_ret_prd_dma, tx_csm_dma;
681531c4f89SJeff Kirsher
682531c4f89SJeff Kirsher unsigned char *trace_buf;
683531c4f89SJeff Kirsher struct pci_dev *pdev;
684531c4f89SJeff Kirsher struct net_device *next;
685531c4f89SJeff Kirsher volatile int fw_running;
686531c4f89SJeff Kirsher int board_idx;
687531c4f89SJeff Kirsher u16 pci_command;
688531c4f89SJeff Kirsher u8 pci_latency;
689531c4f89SJeff Kirsher const char *name;
690531c4f89SJeff Kirsher #ifdef INDEX_DEBUG
691531c4f89SJeff Kirsher spinlock_t debug_lock
692531c4f89SJeff Kirsher __attribute__ ((aligned (SMP_CACHE_BYTES)));
693531c4f89SJeff Kirsher u32 last_tx, last_std_rx, last_mini_rx;
694531c4f89SJeff Kirsher #endif
695531c4f89SJeff Kirsher u8 firmware_major;
696531c4f89SJeff Kirsher u8 firmware_minor;
697531c4f89SJeff Kirsher u8 firmware_fix;
698531c4f89SJeff Kirsher u32 firmware_start;
699531c4f89SJeff Kirsher };
700531c4f89SJeff Kirsher
701531c4f89SJeff Kirsher
702531c4f89SJeff Kirsher #define TX_RESERVED MAX_SKB_FRAGS
703531c4f89SJeff Kirsher
tx_space(struct ace_private * ap,u32 csm,u32 prd)704531c4f89SJeff Kirsher static inline int tx_space (struct ace_private *ap, u32 csm, u32 prd)
705531c4f89SJeff Kirsher {
706531c4f89SJeff Kirsher return (csm - prd - 1) & (ACE_TX_RING_ENTRIES(ap) - 1);
707531c4f89SJeff Kirsher }
708531c4f89SJeff Kirsher
709531c4f89SJeff Kirsher #define tx_free(ap) tx_space((ap)->tx_ret_csm, (ap)->tx_prd, ap)
710531c4f89SJeff Kirsher #define tx_ring_full(ap, csm, prd) (tx_space(ap, csm, prd) <= TX_RESERVED)
711531c4f89SJeff Kirsher
set_aceaddr(aceaddr * aa,dma_addr_t addr)712531c4f89SJeff Kirsher static inline void set_aceaddr(aceaddr *aa, dma_addr_t addr)
713531c4f89SJeff Kirsher {
714531c4f89SJeff Kirsher u64 baddr = (u64) addr;
715531c4f89SJeff Kirsher aa->addrlo = baddr & 0xffffffff;
716531c4f89SJeff Kirsher aa->addrhi = baddr >> 32;
717531c4f89SJeff Kirsher wmb();
718531c4f89SJeff Kirsher }
719531c4f89SJeff Kirsher
720531c4f89SJeff Kirsher
ace_set_txprd(struct ace_regs __iomem * regs,struct ace_private * ap,u32 value)721531c4f89SJeff Kirsher static inline void ace_set_txprd(struct ace_regs __iomem *regs,
722531c4f89SJeff Kirsher struct ace_private *ap, u32 value)
723531c4f89SJeff Kirsher {
724531c4f89SJeff Kirsher #ifdef INDEX_DEBUG
725531c4f89SJeff Kirsher unsigned long flags;
726531c4f89SJeff Kirsher spin_lock_irqsave(&ap->debug_lock, flags);
727531c4f89SJeff Kirsher writel(value, ®s->TxPrd);
728531c4f89SJeff Kirsher if (value == ap->last_tx)
729531c4f89SJeff Kirsher printk(KERN_ERR "AceNIC RACE ALERT! writing identical value "
730531c4f89SJeff Kirsher "to tx producer (%i)\n", value);
731531c4f89SJeff Kirsher ap->last_tx = value;
732531c4f89SJeff Kirsher spin_unlock_irqrestore(&ap->debug_lock, flags);
733531c4f89SJeff Kirsher #else
734531c4f89SJeff Kirsher writel(value, ®s->TxPrd);
735531c4f89SJeff Kirsher #endif
736531c4f89SJeff Kirsher wmb();
737531c4f89SJeff Kirsher }
738531c4f89SJeff Kirsher
739531c4f89SJeff Kirsher
ace_mask_irq(struct net_device * dev)740531c4f89SJeff Kirsher static inline void ace_mask_irq(struct net_device *dev)
741531c4f89SJeff Kirsher {
742531c4f89SJeff Kirsher struct ace_private *ap = netdev_priv(dev);
743531c4f89SJeff Kirsher struct ace_regs __iomem *regs = ap->regs;
744531c4f89SJeff Kirsher
745531c4f89SJeff Kirsher if (ACE_IS_TIGON_I(ap))
746531c4f89SJeff Kirsher writel(1, ®s->MaskInt);
747531c4f89SJeff Kirsher else
748531c4f89SJeff Kirsher writel(readl(®s->HostCtrl) | MASK_INTS, ®s->HostCtrl);
749531c4f89SJeff Kirsher
750531c4f89SJeff Kirsher ace_sync_irq(dev->irq);
751531c4f89SJeff Kirsher }
752531c4f89SJeff Kirsher
753531c4f89SJeff Kirsher
ace_unmask_irq(struct net_device * dev)754531c4f89SJeff Kirsher static inline void ace_unmask_irq(struct net_device *dev)
755531c4f89SJeff Kirsher {
756531c4f89SJeff Kirsher struct ace_private *ap = netdev_priv(dev);
757531c4f89SJeff Kirsher struct ace_regs __iomem *regs = ap->regs;
758531c4f89SJeff Kirsher
759531c4f89SJeff Kirsher if (ACE_IS_TIGON_I(ap))
760531c4f89SJeff Kirsher writel(0, ®s->MaskInt);
761531c4f89SJeff Kirsher else
762531c4f89SJeff Kirsher writel(readl(®s->HostCtrl) & ~MASK_INTS, ®s->HostCtrl);
763531c4f89SJeff Kirsher }
764531c4f89SJeff Kirsher
765531c4f89SJeff Kirsher
766531c4f89SJeff Kirsher /*
767531c4f89SJeff Kirsher * Prototypes
768531c4f89SJeff Kirsher */
769531c4f89SJeff Kirsher static int ace_init(struct net_device *dev);
770531c4f89SJeff Kirsher static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs);
771531c4f89SJeff Kirsher static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs);
772531c4f89SJeff Kirsher static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs);
773531c4f89SJeff Kirsher static irqreturn_t ace_interrupt(int irq, void *dev_id);
774531c4f89SJeff Kirsher static int ace_load_firmware(struct net_device *dev);
775531c4f89SJeff Kirsher static int ace_open(struct net_device *dev);
776531c4f89SJeff Kirsher static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
777531c4f89SJeff Kirsher struct net_device *dev);
778531c4f89SJeff Kirsher static int ace_close(struct net_device *dev);
779*9c59cc79SAllen Pais static void ace_tasklet(struct tasklet_struct *t);
780531c4f89SJeff Kirsher static void ace_dump_trace(struct ace_private *ap);
781531c4f89SJeff Kirsher static void ace_set_multicast_list(struct net_device *dev);
782531c4f89SJeff Kirsher static int ace_change_mtu(struct net_device *dev, int new_mtu);
783531c4f89SJeff Kirsher static int ace_set_mac_addr(struct net_device *dev, void *p);
784531c4f89SJeff Kirsher static void ace_set_rxtx_parms(struct net_device *dev, int jumbo);
785531c4f89SJeff Kirsher static int ace_allocate_descriptors(struct net_device *dev);
786531c4f89SJeff Kirsher static void ace_free_descriptors(struct net_device *dev);
787531c4f89SJeff Kirsher static void ace_init_cleanup(struct net_device *dev);
788531c4f89SJeff Kirsher static struct net_device_stats *ace_get_stats(struct net_device *dev);
789531c4f89SJeff Kirsher static int read_eeprom_byte(struct net_device *dev, unsigned long offset);
790531c4f89SJeff Kirsher
791531c4f89SJeff Kirsher #endif /* _ACENIC_H_ */
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