1 /* 2 * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef _ENA_ADMIN_H_ 33 #define _ENA_ADMIN_H_ 34 35 36 enum ena_admin_aq_opcode { 37 ENA_ADMIN_CREATE_SQ = 1, 38 ENA_ADMIN_DESTROY_SQ = 2, 39 ENA_ADMIN_CREATE_CQ = 3, 40 ENA_ADMIN_DESTROY_CQ = 4, 41 ENA_ADMIN_GET_FEATURE = 8, 42 ENA_ADMIN_SET_FEATURE = 9, 43 ENA_ADMIN_GET_STATS = 11, 44 }; 45 46 enum ena_admin_aq_completion_status { 47 ENA_ADMIN_SUCCESS = 0, 48 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 49 ENA_ADMIN_BAD_OPCODE = 2, 50 ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 51 ENA_ADMIN_MALFORMED_REQUEST = 4, 52 /* Additional status is provided in ACQ entry extended_status */ 53 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 54 ENA_ADMIN_UNKNOWN_ERROR = 6, 55 ENA_ADMIN_RESOURCE_BUSY = 7, 56 }; 57 58 enum ena_admin_aq_feature_id { 59 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 60 ENA_ADMIN_MAX_QUEUES_NUM = 2, 61 ENA_ADMIN_HW_HINTS = 3, 62 ENA_ADMIN_LLQ = 4, 63 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 64 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 65 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, 66 ENA_ADMIN_MTU = 14, 67 ENA_ADMIN_RSS_HASH_INPUT = 18, 68 ENA_ADMIN_INTERRUPT_MODERATION = 20, 69 ENA_ADMIN_AENQ_CONFIG = 26, 70 ENA_ADMIN_LINK_CONFIG = 27, 71 ENA_ADMIN_HOST_ATTR_CONFIG = 28, 72 ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 73 }; 74 75 enum ena_admin_placement_policy_type { 76 /* descriptors and headers are in host memory */ 77 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 78 /* descriptors and headers are in device memory (a.k.a Low Latency 79 * Queue) 80 */ 81 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 82 }; 83 84 enum ena_admin_link_types { 85 ENA_ADMIN_LINK_SPEED_1G = 0x1, 86 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 87 ENA_ADMIN_LINK_SPEED_5G = 0x4, 88 ENA_ADMIN_LINK_SPEED_10G = 0x8, 89 ENA_ADMIN_LINK_SPEED_25G = 0x10, 90 ENA_ADMIN_LINK_SPEED_40G = 0x20, 91 ENA_ADMIN_LINK_SPEED_50G = 0x40, 92 ENA_ADMIN_LINK_SPEED_100G = 0x80, 93 ENA_ADMIN_LINK_SPEED_200G = 0x100, 94 ENA_ADMIN_LINK_SPEED_400G = 0x200, 95 }; 96 97 enum ena_admin_completion_policy_type { 98 /* completion queue entry for each sq descriptor */ 99 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 100 /* completion queue entry upon request in sq descriptor */ 101 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 102 /* current queue head pointer is updated in OS memory upon sq 103 * descriptor request 104 */ 105 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 106 /* current queue head pointer is updated in OS memory for each sq 107 * descriptor 108 */ 109 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 110 }; 111 112 /* basic stats return ena_admin_basic_stats while extanded stats return a 113 * buffer (string format) with additional statistics per queue and per 114 * device id 115 */ 116 enum ena_admin_get_stats_type { 117 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 118 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 119 }; 120 121 enum ena_admin_get_stats_scope { 122 ENA_ADMIN_SPECIFIC_QUEUE = 0, 123 ENA_ADMIN_ETH_TRAFFIC = 1, 124 }; 125 126 struct ena_admin_aq_common_desc { 127 /* 11:0 : command_id 128 * 15:12 : reserved12 129 */ 130 u16 command_id; 131 132 /* as appears in ena_admin_aq_opcode */ 133 u8 opcode; 134 135 /* 0 : phase 136 * 1 : ctrl_data - control buffer address valid 137 * 2 : ctrl_data_indirect - control buffer address 138 * points to list of pages with addresses of control 139 * buffers 140 * 7:3 : reserved3 141 */ 142 u8 flags; 143 }; 144 145 /* used in ena_admin_aq_entry. Can point directly to control data, or to a 146 * page list chunk. Used also at the end of indirect mode page list chunks, 147 * for chaining. 148 */ 149 struct ena_admin_ctrl_buff_info { 150 u32 length; 151 152 struct ena_common_mem_addr address; 153 }; 154 155 struct ena_admin_sq { 156 u16 sq_idx; 157 158 /* 4:0 : reserved 159 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 160 */ 161 u8 sq_identity; 162 163 u8 reserved1; 164 }; 165 166 struct ena_admin_aq_entry { 167 struct ena_admin_aq_common_desc aq_common_descriptor; 168 169 union { 170 u32 inline_data_w1[3]; 171 172 struct ena_admin_ctrl_buff_info control_buffer; 173 } u; 174 175 u32 inline_data_w4[12]; 176 }; 177 178 struct ena_admin_acq_common_desc { 179 /* command identifier to associate it with the aq descriptor 180 * 11:0 : command_id 181 * 15:12 : reserved12 182 */ 183 u16 command; 184 185 u8 status; 186 187 /* 0 : phase 188 * 7:1 : reserved1 189 */ 190 u8 flags; 191 192 u16 extended_status; 193 194 /* indicates to the driver which AQ entry has been consumed by the 195 * device and could be reused 196 */ 197 u16 sq_head_indx; 198 }; 199 200 struct ena_admin_acq_entry { 201 struct ena_admin_acq_common_desc acq_common_descriptor; 202 203 u32 response_specific_data[14]; 204 }; 205 206 struct ena_admin_aq_create_sq_cmd { 207 struct ena_admin_aq_common_desc aq_common_descriptor; 208 209 /* 4:0 : reserved0_w1 210 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 211 */ 212 u8 sq_identity; 213 214 u8 reserved8_w1; 215 216 /* 3:0 : placement_policy - Describing where the SQ 217 * descriptor ring and the SQ packet headers reside: 218 * 0x1 - descriptors and headers are in OS memory, 219 * 0x3 - descriptors and headers in device memory 220 * (a.k.a Low Latency Queue) 221 * 6:4 : completion_policy - Describing what policy 222 * to use for generation completion entry (cqe) in 223 * the CQ associated with this SQ: 0x0 - cqe for each 224 * sq descriptor, 0x1 - cqe upon request in sq 225 * descriptor, 0x2 - current queue head pointer is 226 * updated in OS memory upon sq descriptor request 227 * 0x3 - current queue head pointer is updated in OS 228 * memory for each sq descriptor 229 * 7 : reserved15_w1 230 */ 231 u8 sq_caps_2; 232 233 /* 0 : is_physically_contiguous - Described if the 234 * queue ring memory is allocated in physical 235 * contiguous pages or split. 236 * 7:1 : reserved17_w1 237 */ 238 u8 sq_caps_3; 239 240 /* associated completion queue id. This CQ must be created prior to 241 * SQ creation 242 */ 243 u16 cq_idx; 244 245 /* submission queue depth in entries */ 246 u16 sq_depth; 247 248 /* SQ physical base address in OS memory. This field should not be 249 * used for Low Latency queues. Has to be page aligned. 250 */ 251 struct ena_common_mem_addr sq_ba; 252 253 /* specifies queue head writeback location in OS memory. Valid if 254 * completion_policy is set to completion_policy_head_on_demand or 255 * completion_policy_head. Has to be cache aligned 256 */ 257 struct ena_common_mem_addr sq_head_writeback; 258 259 u32 reserved0_w7; 260 261 u32 reserved0_w8; 262 }; 263 264 enum ena_admin_sq_direction { 265 ENA_ADMIN_SQ_DIRECTION_TX = 1, 266 ENA_ADMIN_SQ_DIRECTION_RX = 2, 267 }; 268 269 struct ena_admin_acq_create_sq_resp_desc { 270 struct ena_admin_acq_common_desc acq_common_desc; 271 272 u16 sq_idx; 273 274 u16 reserved; 275 276 /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 277 u32 sq_doorbell_offset; 278 279 /* low latency queue ring base address as an offset to PCIe MMIO 280 * LLQ_MEM BAR 281 */ 282 u32 llq_descriptors_offset; 283 284 /* low latency queue headers' memory as an offset to PCIe MMIO 285 * LLQ_MEM BAR 286 */ 287 u32 llq_headers_offset; 288 }; 289 290 struct ena_admin_aq_destroy_sq_cmd { 291 struct ena_admin_aq_common_desc aq_common_descriptor; 292 293 struct ena_admin_sq sq; 294 }; 295 296 struct ena_admin_acq_destroy_sq_resp_desc { 297 struct ena_admin_acq_common_desc acq_common_desc; 298 }; 299 300 struct ena_admin_aq_create_cq_cmd { 301 struct ena_admin_aq_common_desc aq_common_descriptor; 302 303 /* 4:0 : reserved5 304 * 5 : interrupt_mode_enabled - if set, cq operates 305 * in interrupt mode, otherwise - polling 306 * 7:6 : reserved6 307 */ 308 u8 cq_caps_1; 309 310 /* 4:0 : cq_entry_size_words - size of CQ entry in 311 * 32-bit words, valid values: 4, 8. 312 * 7:5 : reserved7 313 */ 314 u8 cq_caps_2; 315 316 /* completion queue depth in # of entries. must be power of 2 */ 317 u16 cq_depth; 318 319 /* msix vector assigned to this cq */ 320 u32 msix_vector; 321 322 /* cq physical base address in OS memory. CQ must be physically 323 * contiguous 324 */ 325 struct ena_common_mem_addr cq_ba; 326 }; 327 328 struct ena_admin_acq_create_cq_resp_desc { 329 struct ena_admin_acq_common_desc acq_common_desc; 330 331 u16 cq_idx; 332 333 /* actual cq depth in number of entries */ 334 u16 cq_actual_depth; 335 336 u32 numa_node_register_offset; 337 338 u32 cq_head_db_register_offset; 339 340 u32 cq_interrupt_unmask_register_offset; 341 }; 342 343 struct ena_admin_aq_destroy_cq_cmd { 344 struct ena_admin_aq_common_desc aq_common_descriptor; 345 346 u16 cq_idx; 347 348 u16 reserved1; 349 }; 350 351 struct ena_admin_acq_destroy_cq_resp_desc { 352 struct ena_admin_acq_common_desc acq_common_desc; 353 }; 354 355 /* ENA AQ Get Statistics command. Extended statistics are placed in control 356 * buffer pointed by AQ entry 357 */ 358 struct ena_admin_aq_get_stats_cmd { 359 struct ena_admin_aq_common_desc aq_common_descriptor; 360 361 union { 362 /* command specific inline data */ 363 u32 inline_data_w1[3]; 364 365 struct ena_admin_ctrl_buff_info control_buffer; 366 } u; 367 368 /* stats type as defined in enum ena_admin_get_stats_type */ 369 u8 type; 370 371 /* stats scope defined in enum ena_admin_get_stats_scope */ 372 u8 scope; 373 374 u16 reserved3; 375 376 /* queue id. used when scope is specific_queue */ 377 u16 queue_idx; 378 379 /* device id, value 0xFFFF means mine. only privileged device can get 380 * stats of other device 381 */ 382 u16 device_id; 383 }; 384 385 /* Basic Statistics Command. */ 386 struct ena_admin_basic_stats { 387 u32 tx_bytes_low; 388 389 u32 tx_bytes_high; 390 391 u32 tx_pkts_low; 392 393 u32 tx_pkts_high; 394 395 u32 rx_bytes_low; 396 397 u32 rx_bytes_high; 398 399 u32 rx_pkts_low; 400 401 u32 rx_pkts_high; 402 403 u32 rx_drops_low; 404 405 u32 rx_drops_high; 406 }; 407 408 struct ena_admin_acq_get_stats_resp { 409 struct ena_admin_acq_common_desc acq_common_desc; 410 411 struct ena_admin_basic_stats basic_stats; 412 }; 413 414 struct ena_admin_get_set_feature_common_desc { 415 /* 1:0 : select - 0x1 - current value; 0x3 - default 416 * value 417 * 7:3 : reserved3 418 */ 419 u8 flags; 420 421 /* as appears in ena_admin_aq_feature_id */ 422 u8 feature_id; 423 424 u16 reserved16; 425 }; 426 427 struct ena_admin_device_attr_feature_desc { 428 u32 impl_id; 429 430 u32 device_version; 431 432 /* bitmap of ena_admin_aq_feature_id */ 433 u32 supported_features; 434 435 u32 reserved3; 436 437 /* Indicates how many bits are used physical address access. */ 438 u32 phys_addr_width; 439 440 /* Indicates how many bits are used virtual address access. */ 441 u32 virt_addr_width; 442 443 /* unicast MAC address (in Network byte order) */ 444 u8 mac_addr[6]; 445 446 u8 reserved7[2]; 447 448 u32 max_mtu; 449 }; 450 451 enum ena_admin_llq_header_location { 452 /* header is in descriptor list */ 453 ENA_ADMIN_INLINE_HEADER = 1, 454 /* header in a separate ring, implies 16B descriptor list entry */ 455 ENA_ADMIN_HEADER_RING = 2, 456 }; 457 458 enum ena_admin_llq_ring_entry_size { 459 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 460 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 461 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 462 }; 463 464 enum ena_admin_llq_num_descs_before_header { 465 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 466 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 467 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 468 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 469 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 470 }; 471 472 /* packet descriptor list entry always starts with one or more descriptors, 473 * followed by a header. The rest of the descriptors are located in the 474 * beginning of the subsequent entry. Stride refers to how the rest of the 475 * descriptors are placed. This field is relevant only for inline header 476 * mode 477 */ 478 enum ena_admin_llq_stride_ctrl { 479 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 480 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 481 }; 482 483 struct ena_admin_feature_llq_desc { 484 u32 max_llq_num; 485 486 u32 max_llq_depth; 487 488 /* specify the header locations the device supports. bitfield of 489 * enum ena_admin_llq_header_location. 490 */ 491 u16 header_location_ctrl_supported; 492 493 /* the header location the driver selected to use. */ 494 u16 header_location_ctrl_enabled; 495 496 /* if inline header is specified - this is the size of descriptor 497 * list entry. If header in a separate ring is specified - this is 498 * the size of header ring entry. bitfield of enum 499 * ena_admin_llq_ring_entry_size. specify the entry sizes the device 500 * supports 501 */ 502 u16 entry_size_ctrl_supported; 503 504 /* the entry size the driver selected to use. */ 505 u16 entry_size_ctrl_enabled; 506 507 /* valid only if inline header is specified. First entry associated 508 * with the packet includes descriptors and header. Rest of the 509 * entries occupied by descriptors. This parameter defines the max 510 * number of descriptors precedding the header in the first entry. 511 * The field is bitfield of enum 512 * ena_admin_llq_num_descs_before_header and specify the values the 513 * device supports 514 */ 515 u16 desc_num_before_header_supported; 516 517 /* the desire field the driver selected to use */ 518 u16 desc_num_before_header_enabled; 519 520 /* valid only if inline was chosen. bitfield of enum 521 * ena_admin_llq_stride_ctrl 522 */ 523 u16 descriptors_stride_ctrl_supported; 524 525 /* the stride control the driver selected to use */ 526 u16 descriptors_stride_ctrl_enabled; 527 }; 528 529 struct ena_admin_queue_feature_desc { 530 u32 max_sq_num; 531 532 u32 max_sq_depth; 533 534 u32 max_cq_num; 535 536 u32 max_cq_depth; 537 538 u32 max_legacy_llq_num; 539 540 u32 max_legacy_llq_depth; 541 542 u32 max_header_size; 543 544 /* Maximum Descriptors number, including meta descriptor, allowed for 545 * a single Tx packet 546 */ 547 u16 max_packet_tx_descs; 548 549 /* Maximum Descriptors number allowed for a single Rx packet */ 550 u16 max_packet_rx_descs; 551 }; 552 553 struct ena_admin_set_feature_mtu_desc { 554 /* exclude L2 */ 555 u32 mtu; 556 }; 557 558 struct ena_admin_set_feature_host_attr_desc { 559 /* host OS info base address in OS memory. host info is 4KB of 560 * physically contiguous 561 */ 562 struct ena_common_mem_addr os_info_ba; 563 564 /* host debug area base address in OS memory. debug area must be 565 * physically contiguous 566 */ 567 struct ena_common_mem_addr debug_ba; 568 569 /* debug area size */ 570 u32 debug_area_size; 571 }; 572 573 struct ena_admin_feature_intr_moder_desc { 574 /* interrupt delay granularity in usec */ 575 u16 intr_delay_resolution; 576 577 u16 reserved; 578 }; 579 580 struct ena_admin_get_feature_link_desc { 581 /* Link speed in Mb */ 582 u32 speed; 583 584 /* bit field of enum ena_admin_link types */ 585 u32 supported; 586 587 /* 0 : autoneg 588 * 1 : duplex - Full Duplex 589 * 31:2 : reserved2 590 */ 591 u32 flags; 592 }; 593 594 struct ena_admin_feature_aenq_desc { 595 /* bitmask for AENQ groups the device can report */ 596 u32 supported_groups; 597 598 /* bitmask for AENQ groups to report */ 599 u32 enabled_groups; 600 }; 601 602 struct ena_admin_feature_offload_desc { 603 /* 0 : TX_L3_csum_ipv4 604 * 1 : TX_L4_ipv4_csum_part - The checksum field 605 * should be initialized with pseudo header checksum 606 * 2 : TX_L4_ipv4_csum_full 607 * 3 : TX_L4_ipv6_csum_part - The checksum field 608 * should be initialized with pseudo header checksum 609 * 4 : TX_L4_ipv6_csum_full 610 * 5 : tso_ipv4 611 * 6 : tso_ipv6 612 * 7 : tso_ecn 613 */ 614 u32 tx; 615 616 /* Receive side supported stateless offload 617 * 0 : RX_L3_csum_ipv4 - IPv4 checksum 618 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 619 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 620 * 3 : RX_hash - Hash calculation 621 */ 622 u32 rx_supported; 623 624 u32 rx_enabled; 625 }; 626 627 enum ena_admin_hash_functions { 628 ENA_ADMIN_TOEPLITZ = 1, 629 ENA_ADMIN_CRC32 = 2, 630 }; 631 632 struct ena_admin_feature_rss_flow_hash_control { 633 u32 keys_num; 634 635 u32 reserved; 636 637 u32 key[10]; 638 }; 639 640 struct ena_admin_feature_rss_flow_hash_function { 641 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 642 u32 supported_func; 643 644 /* 7:0 : selected_func - bitmask of 645 * ena_admin_hash_functions 646 */ 647 u32 selected_func; 648 649 /* initial value */ 650 u32 init_val; 651 }; 652 653 /* RSS flow hash protocols */ 654 enum ena_admin_flow_hash_proto { 655 ENA_ADMIN_RSS_TCP4 = 0, 656 ENA_ADMIN_RSS_UDP4 = 1, 657 ENA_ADMIN_RSS_TCP6 = 2, 658 ENA_ADMIN_RSS_UDP6 = 3, 659 ENA_ADMIN_RSS_IP4 = 4, 660 ENA_ADMIN_RSS_IP6 = 5, 661 ENA_ADMIN_RSS_IP4_FRAG = 6, 662 ENA_ADMIN_RSS_NOT_IP = 7, 663 /* TCPv6 with extension header */ 664 ENA_ADMIN_RSS_TCP6_EX = 8, 665 /* IPv6 with extension header */ 666 ENA_ADMIN_RSS_IP6_EX = 9, 667 ENA_ADMIN_RSS_PROTO_NUM = 16, 668 }; 669 670 /* RSS flow hash fields */ 671 enum ena_admin_flow_hash_fields { 672 /* Ethernet Dest Addr */ 673 ENA_ADMIN_RSS_L2_DA = BIT(0), 674 /* Ethernet Src Addr */ 675 ENA_ADMIN_RSS_L2_SA = BIT(1), 676 /* ipv4/6 Dest Addr */ 677 ENA_ADMIN_RSS_L3_DA = BIT(2), 678 /* ipv4/6 Src Addr */ 679 ENA_ADMIN_RSS_L3_SA = BIT(3), 680 /* tcp/udp Dest Port */ 681 ENA_ADMIN_RSS_L4_DP = BIT(4), 682 /* tcp/udp Src Port */ 683 ENA_ADMIN_RSS_L4_SP = BIT(5), 684 }; 685 686 struct ena_admin_proto_input { 687 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 688 u16 fields; 689 690 u16 reserved2; 691 }; 692 693 struct ena_admin_feature_rss_hash_control { 694 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 695 696 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 697 698 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 699 700 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 701 }; 702 703 struct ena_admin_feature_rss_flow_hash_input { 704 /* supported hash input sorting 705 * 1 : L3_sort - support swap L3 addresses if DA is 706 * smaller than SA 707 * 2 : L4_sort - support swap L4 ports if DP smaller 708 * SP 709 */ 710 u16 supported_input_sort; 711 712 /* enabled hash input sorting 713 * 1 : enable_L3_sort - enable swap L3 addresses if 714 * DA smaller than SA 715 * 2 : enable_L4_sort - enable swap L4 ports if DP 716 * smaller than SP 717 */ 718 u16 enabled_input_sort; 719 }; 720 721 enum ena_admin_os_type { 722 ENA_ADMIN_OS_LINUX = 1, 723 ENA_ADMIN_OS_WIN = 2, 724 ENA_ADMIN_OS_DPDK = 3, 725 ENA_ADMIN_OS_FREEBSD = 4, 726 ENA_ADMIN_OS_IPXE = 5, 727 ENA_ADMIN_OS_ESXI = 6, 728 ENA_ADMIN_OS_GROUPS_NUM = 6, 729 }; 730 731 struct ena_admin_host_info { 732 /* defined in enum ena_admin_os_type */ 733 u32 os_type; 734 735 /* os distribution string format */ 736 u8 os_dist_str[128]; 737 738 /* OS distribution numeric format */ 739 u32 os_dist; 740 741 /* kernel version string format */ 742 u8 kernel_ver_str[32]; 743 744 /* Kernel version numeric format */ 745 u32 kernel_ver; 746 747 /* 7:0 : major 748 * 15:8 : minor 749 * 23:16 : sub_minor 750 * 31:24 : module_type 751 */ 752 u32 driver_version; 753 754 /* features bitmap */ 755 u32 supported_network_features[2]; 756 757 /* ENA spec version of driver */ 758 u16 ena_spec_version; 759 760 /* ENA device's Bus, Device and Function 761 * 2:0 : function 762 * 7:3 : device 763 * 15:8 : bus 764 */ 765 u16 bdf; 766 767 /* Number of CPUs */ 768 u16 num_cpus; 769 770 u16 reserved; 771 }; 772 773 struct ena_admin_rss_ind_table_entry { 774 u16 cq_idx; 775 776 u16 reserved; 777 }; 778 779 struct ena_admin_feature_rss_ind_table { 780 /* min supported table size (2^min_size) */ 781 u16 min_size; 782 783 /* max supported table size (2^max_size) */ 784 u16 max_size; 785 786 /* table size (2^size) */ 787 u16 size; 788 789 u16 reserved; 790 791 /* index of the inline entry. 0xFFFFFFFF means invalid */ 792 u32 inline_index; 793 794 /* used for updating single entry, ignored when setting the entire 795 * table through the control buffer. 796 */ 797 struct ena_admin_rss_ind_table_entry inline_entry; 798 }; 799 800 /* When hint value is 0, driver should use it's own predefined value */ 801 struct ena_admin_ena_hw_hints { 802 /* value in ms */ 803 u16 mmio_read_timeout; 804 805 /* value in ms */ 806 u16 driver_watchdog_timeout; 807 808 /* Per packet tx completion timeout. value in ms */ 809 u16 missing_tx_completion_timeout; 810 811 u16 missed_tx_completion_count_threshold_to_reset; 812 813 /* value in ms */ 814 u16 admin_completion_tx_timeout; 815 816 u16 netdev_wd_timeout; 817 818 u16 max_tx_sgl_size; 819 820 u16 max_rx_sgl_size; 821 822 u16 reserved[8]; 823 }; 824 825 struct ena_admin_get_feat_cmd { 826 struct ena_admin_aq_common_desc aq_common_descriptor; 827 828 struct ena_admin_ctrl_buff_info control_buffer; 829 830 struct ena_admin_get_set_feature_common_desc feat_common; 831 832 u32 raw[11]; 833 }; 834 835 struct ena_admin_get_feat_resp { 836 struct ena_admin_acq_common_desc acq_common_desc; 837 838 union { 839 u32 raw[14]; 840 841 struct ena_admin_device_attr_feature_desc dev_attr; 842 843 struct ena_admin_feature_llq_desc llq; 844 845 struct ena_admin_queue_feature_desc max_queue; 846 847 struct ena_admin_feature_aenq_desc aenq; 848 849 struct ena_admin_get_feature_link_desc link; 850 851 struct ena_admin_feature_offload_desc offload; 852 853 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 854 855 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 856 857 struct ena_admin_feature_rss_ind_table ind_table; 858 859 struct ena_admin_feature_intr_moder_desc intr_moderation; 860 861 struct ena_admin_ena_hw_hints hw_hints; 862 } u; 863 }; 864 865 struct ena_admin_set_feat_cmd { 866 struct ena_admin_aq_common_desc aq_common_descriptor; 867 868 struct ena_admin_ctrl_buff_info control_buffer; 869 870 struct ena_admin_get_set_feature_common_desc feat_common; 871 872 union { 873 u32 raw[11]; 874 875 /* mtu size */ 876 struct ena_admin_set_feature_mtu_desc mtu; 877 878 /* host attributes */ 879 struct ena_admin_set_feature_host_attr_desc host_attr; 880 881 /* AENQ configuration */ 882 struct ena_admin_feature_aenq_desc aenq; 883 884 /* rss flow hash function */ 885 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 886 887 /* rss flow hash input */ 888 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 889 890 /* rss indirection table */ 891 struct ena_admin_feature_rss_ind_table ind_table; 892 893 /* LLQ configuration */ 894 struct ena_admin_feature_llq_desc llq; 895 } u; 896 }; 897 898 struct ena_admin_set_feat_resp { 899 struct ena_admin_acq_common_desc acq_common_desc; 900 901 union { 902 u32 raw[14]; 903 } u; 904 }; 905 906 struct ena_admin_aenq_common_desc { 907 u16 group; 908 909 u16 syndrom; 910 911 /* 0 : phase */ 912 u8 flags; 913 914 u8 reserved1[3]; 915 916 u32 timestamp_low; 917 918 u32 timestamp_high; 919 }; 920 921 /* asynchronous event notification groups */ 922 enum ena_admin_aenq_group { 923 ENA_ADMIN_LINK_CHANGE = 0, 924 ENA_ADMIN_FATAL_ERROR = 1, 925 ENA_ADMIN_WARNING = 2, 926 ENA_ADMIN_NOTIFICATION = 3, 927 ENA_ADMIN_KEEP_ALIVE = 4, 928 ENA_ADMIN_AENQ_GROUPS_NUM = 5, 929 }; 930 931 enum ena_admin_aenq_notification_syndrom { 932 ENA_ADMIN_SUSPEND = 0, 933 ENA_ADMIN_RESUME = 1, 934 ENA_ADMIN_UPDATE_HINTS = 2, 935 }; 936 937 struct ena_admin_aenq_entry { 938 struct ena_admin_aenq_common_desc aenq_common_desc; 939 940 /* command specific inline data */ 941 u32 inline_data_w4[12]; 942 }; 943 944 struct ena_admin_aenq_link_change_desc { 945 struct ena_admin_aenq_common_desc aenq_common_desc; 946 947 /* 0 : link_status */ 948 u32 flags; 949 }; 950 951 struct ena_admin_aenq_keep_alive_desc { 952 struct ena_admin_aenq_common_desc aenq_common_desc; 953 954 u32 rx_drops_low; 955 956 u32 rx_drops_high; 957 }; 958 959 struct ena_admin_ena_mmio_req_read_less_resp { 960 u16 req_id; 961 962 u16 reg_off; 963 964 /* value is valid when poll is cleared */ 965 u32 reg_val; 966 }; 967 968 /* aq_common_desc */ 969 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 970 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 971 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 972 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 973 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 974 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 975 976 /* sq */ 977 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 978 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 979 980 /* acq_common_desc */ 981 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 982 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 983 984 /* aq_create_sq_cmd */ 985 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 986 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 987 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 988 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 989 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 990 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 991 992 /* aq_create_cq_cmd */ 993 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 994 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 995 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 996 997 /* get_set_feature_common_desc */ 998 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 999 1000 /* get_feature_link_desc */ 1001 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1002 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1003 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1004 1005 /* feature_offload_desc */ 1006 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1007 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1008 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1009 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1010 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1011 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1012 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1013 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1014 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1015 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1016 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1017 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1018 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1019 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1020 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1021 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1022 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1023 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1024 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1025 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1026 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1027 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1028 1029 /* feature_rss_flow_hash_function */ 1030 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1031 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1032 1033 /* feature_rss_flow_hash_input */ 1034 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1035 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1036 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1037 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1038 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1039 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1040 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1041 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1042 1043 /* host_info */ 1044 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1045 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1046 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1047 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1048 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1049 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1050 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1051 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1052 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1053 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1054 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1055 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1056 1057 /* aenq_common_desc */ 1058 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1059 1060 /* aenq_link_change_desc */ 1061 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1062 1063 #endif /*_ENA_ADMIN_H_ */ 1064