1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 #ifndef _ENA_REGS_H_ 6 #define _ENA_REGS_H_ 7 8 enum ena_regs_reset_reason_types { 9 ENA_REGS_RESET_NORMAL = 0, 10 ENA_REGS_RESET_KEEP_ALIVE_TO = 1, 11 ENA_REGS_RESET_ADMIN_TO = 2, 12 ENA_REGS_RESET_MISS_TX_CMPL = 3, 13 ENA_REGS_RESET_INV_RX_REQ_ID = 4, 14 ENA_REGS_RESET_INV_TX_REQ_ID = 5, 15 ENA_REGS_RESET_TOO_MANY_RX_DESCS = 6, 16 ENA_REGS_RESET_INIT_ERR = 7, 17 ENA_REGS_RESET_DRIVER_INVALID_STATE = 8, 18 ENA_REGS_RESET_OS_TRIGGER = 9, 19 ENA_REGS_RESET_OS_NETDEV_WD = 10, 20 ENA_REGS_RESET_SHUTDOWN = 11, 21 ENA_REGS_RESET_USER_TRIGGER = 12, 22 ENA_REGS_RESET_GENERIC = 13, 23 ENA_REGS_RESET_MISS_INTERRUPT = 14, 24 ENA_REGS_RESET_SUSPECTED_POLL_STARVATION = 15, 25 }; 26 27 /* ena_registers offsets */ 28 29 /* 0 base */ 30 #define ENA_REGS_VERSION_OFF 0x0 31 #define ENA_REGS_CONTROLLER_VERSION_OFF 0x4 32 #define ENA_REGS_CAPS_OFF 0x8 33 #define ENA_REGS_CAPS_EXT_OFF 0xc 34 #define ENA_REGS_AQ_BASE_LO_OFF 0x10 35 #define ENA_REGS_AQ_BASE_HI_OFF 0x14 36 #define ENA_REGS_AQ_CAPS_OFF 0x18 37 #define ENA_REGS_ACQ_BASE_LO_OFF 0x20 38 #define ENA_REGS_ACQ_BASE_HI_OFF 0x24 39 #define ENA_REGS_ACQ_CAPS_OFF 0x28 40 #define ENA_REGS_AQ_DB_OFF 0x2c 41 #define ENA_REGS_ACQ_TAIL_OFF 0x30 42 #define ENA_REGS_AENQ_CAPS_OFF 0x34 43 #define ENA_REGS_AENQ_BASE_LO_OFF 0x38 44 #define ENA_REGS_AENQ_BASE_HI_OFF 0x3c 45 #define ENA_REGS_AENQ_HEAD_DB_OFF 0x40 46 #define ENA_REGS_AENQ_TAIL_OFF 0x44 47 #define ENA_REGS_INTR_MASK_OFF 0x4c 48 #define ENA_REGS_DEV_CTL_OFF 0x54 49 #define ENA_REGS_DEV_STS_OFF 0x58 50 #define ENA_REGS_MMIO_REG_READ_OFF 0x5c 51 #define ENA_REGS_MMIO_RESP_LO_OFF 0x60 52 #define ENA_REGS_MMIO_RESP_HI_OFF 0x64 53 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x68 54 55 /* version register */ 56 #define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff 57 #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 8 58 #define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00 59 60 /* controller_version register */ 61 #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff 62 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 8 63 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00 64 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 16 65 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000 66 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 24 67 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000 68 69 /* caps register */ 70 #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1 71 #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 1 72 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e 73 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8 74 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00 75 #define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16 76 #define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000 77 78 /* aq_caps register */ 79 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff 80 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 16 81 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000 82 83 /* acq_caps register */ 84 #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff 85 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 16 86 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff0000 87 88 /* aenq_caps register */ 89 #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff 90 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 16 91 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff0000 92 93 /* dev_ctl register */ 94 #define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x1 95 #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 1 96 #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2 97 #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 2 98 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4 99 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3 100 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8 101 #define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT 28 102 #define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000 103 104 /* dev_sts register */ 105 #define ENA_REGS_DEV_STS_READY_MASK 0x1 106 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1 107 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2 108 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2 109 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4 110 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3 111 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8 112 #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4 113 #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10 114 #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5 115 #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20 116 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6 117 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40 118 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7 119 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80 120 121 /* mmio_reg_read register */ 122 #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff 123 #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16 124 #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000 125 126 /* rss_ind_entry_update register */ 127 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff 128 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16 129 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000 130 131 #endif /* _ENA_REGS_H_ */ 132