1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. 4 * 5 * Derived from Intel e1000 driver 6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 7 */ 8 9 #ifndef _ATL1C_HW_H_ 10 #define _ATL1C_HW_H_ 11 12 #include <linux/types.h> 13 #include <linux/mii.h> 14 15 #define FIELD_GETX(_x, _name) ((_x) >> (_name##_SHIFT) & (_name##_MASK)) 16 #define FIELD_SETX(_x, _name, _v) \ 17 (((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\ 18 (((_v) & (_name##_MASK)) << (_name##_SHIFT))) 19 #define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT)) 20 21 struct atl1c_adapter; 22 struct atl1c_hw; 23 24 /* function prototype */ 25 void atl1c_phy_disable(struct atl1c_hw *hw); 26 void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr); 27 int atl1c_phy_reset(struct atl1c_hw *hw); 28 int atl1c_read_mac_addr(struct atl1c_hw *hw); 29 int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex); 30 u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr); 31 void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value); 32 int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); 33 int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data); 34 bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value); 35 int atl1c_phy_init(struct atl1c_hw *hw); 36 int atl1c_check_eeprom_exist(struct atl1c_hw *hw); 37 int atl1c_restart_autoneg(struct atl1c_hw *hw); 38 int atl1c_phy_to_ps_link(struct atl1c_hw *hw); 39 int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc); 40 bool atl1c_wait_mdio_idle(struct atl1c_hw *hw); 41 void atl1c_stop_phy_polling(struct atl1c_hw *hw); 42 void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel); 43 int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, 44 u16 reg, u16 *phy_data); 45 int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, 46 u16 reg, u16 phy_data); 47 int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr, 48 u16 reg_addr, u16 *phy_data); 49 int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr, 50 u16 reg_addr, u16 phy_data); 51 int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data); 52 int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data); 53 void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); 54 55 /* hw-ids */ 56 #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062 57 #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063 58 #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */ 59 #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */ 60 #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */ 61 #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */ 62 #define L2CB_V10 0xc0 63 #define L2CB_V11 0xc1 64 #define L2CB_V20 0xc0 65 #define L2CB_V21 0xc1 66 67 /* register definition */ 68 #define REG_DEVICE_CAP 0x5C 69 #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7 70 #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0 71 72 #define DEVICE_CTRL_MAXRRS_MIN 2 73 74 #define REG_LINK_CTRL 0x68 75 #define LINK_CTRL_L0S_EN 0x01 76 #define LINK_CTRL_L1_EN 0x02 77 #define LINK_CTRL_EXT_SYNC 0x80 78 79 #define REG_PCIE_IND_ACC_ADDR 0x80 80 #define REG_PCIE_IND_ACC_DATA 0x84 81 82 #define REG_DEV_SERIALNUM_CTRL 0x200 83 #define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */ 84 #define REG_DEV_MAC_SEL_SHIFT 0 85 #define REG_DEV_SERIAL_NUM_EN_MASK 0x1 86 #define REG_DEV_SERIAL_NUM_EN_SHIFT 1 87 88 #define REG_TWSI_CTRL 0x218 89 #define TWSI_CTLR_FREQ_MASK 0x3UL 90 #define TWSI_CTRL_FREQ_SHIFT 24 91 #define TWSI_CTRL_FREQ_100K 0 92 #define TWSI_CTRL_FREQ_200K 1 93 #define TWSI_CTRL_FREQ_300K 2 94 #define TWSI_CTRL_FREQ_400K 3 95 #define TWSI_CTRL_LD_EXIST BIT(23) 96 #define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */ 97 #define TWSI_CTRL_SW_LDSTART BIT(11) 98 #define TWSI_CTRL_LD_OFFSET_MASK 0xFF 99 #define TWSI_CTRL_LD_OFFSET_SHIFT 0 100 101 #define REG_PCIE_DEV_MISC_CTRL 0x21C 102 #define PCIE_DEV_MISC_EXT_PIPE 0x2 103 #define PCIE_DEV_MISC_RETRY_BUFDIS 0x1 104 #define PCIE_DEV_MISC_SPIROM_EXIST 0x4 105 #define PCIE_DEV_MISC_SERDES_ENDIAN 0x8 106 #define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10 107 108 #define REG_PCIE_PHYMISC 0x1000 109 #define PCIE_PHYMISC_FORCE_RCV_DET BIT(2) 110 #define PCIE_PHYMISC_NFTS_MASK 0xFFUL 111 #define PCIE_PHYMISC_NFTS_SHIFT 16 112 113 #define REG_PCIE_PHYMISC2 0x1004 114 #define PCIE_PHYMISC2_L0S_TH_MASK 0x3UL 115 #define PCIE_PHYMISC2_L0S_TH_SHIFT 18 116 #define L2CB1_PCIE_PHYMISC2_L0S_TH 3 117 #define PCIE_PHYMISC2_CDR_BW_MASK 0x3UL 118 #define PCIE_PHYMISC2_CDR_BW_SHIFT 16 119 #define L2CB1_PCIE_PHYMISC2_CDR_BW 3 120 121 #define REG_TWSI_DEBUG 0x1108 122 #define TWSI_DEBUG_DEV_EXIST BIT(29) 123 124 #define REG_DMA_DBG 0x1114 125 #define DMA_DBG_VENDOR_MSG BIT(0) 126 127 #define REG_EEPROM_CTRL 0x12C0 128 #define EEPROM_CTRL_DATA_HI_MASK 0xFFFF 129 #define EEPROM_CTRL_DATA_HI_SHIFT 0 130 #define EEPROM_CTRL_ADDR_MASK 0x3FF 131 #define EEPROM_CTRL_ADDR_SHIFT 16 132 #define EEPROM_CTRL_ACK 0x40000000 133 #define EEPROM_CTRL_RW 0x80000000 134 135 #define REG_EEPROM_DATA_LO 0x12C4 136 137 #define REG_OTP_CTRL 0x12F0 138 #define OTP_CTRL_CLK_EN BIT(1) 139 140 #define REG_PM_CTRL 0x12F8 141 #define PM_CTRL_HOTRST BIT(31) 142 #define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on 143 * thrghput(setting in 15A0) */ 144 #define PM_CTRL_SA_DLY_EN BIT(29) 145 #define PM_CTRL_L0S_BUFSRX_EN BIT(28) 146 #define PM_CTRL_LCKDET_TIMER_MASK 0xFUL 147 #define PM_CTRL_LCKDET_TIMER_SHIFT 24 148 #define PM_CTRL_LCKDET_TIMER_DEF 0xC 149 #define PM_CTRL_PM_REQ_TIMER_MASK 0xFUL 150 #define PM_CTRL_PM_REQ_TIMER_SHIFT 20 /* pm_request_l1 time > @ 151 * ->L0s not L1 */ 152 #define PM_CTRL_PM_REQ_TO_DEF 0xF 153 #define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */ 154 #define L1D_PMCTRL_L1_ENTRY_TM_MASK 7UL /* l1dv2.0+, 3bits */ 155 #define L1D_PMCTRL_L1_ENTRY_TM_SHIFT 16 156 #define L1D_PMCTRL_L1_ENTRY_TM_DIS 0 157 #define L1D_PMCTRL_L1_ENTRY_TM_2US 1 158 #define L1D_PMCTRL_L1_ENTRY_TM_4US 2 159 #define L1D_PMCTRL_L1_ENTRY_TM_8US 3 160 #define L1D_PMCTRL_L1_ENTRY_TM_16US 4 161 #define L1D_PMCTRL_L1_ENTRY_TM_24US 5 162 #define L1D_PMCTRL_L1_ENTRY_TM_32US 6 163 #define L1D_PMCTRL_L1_ENTRY_TM_63US 7 164 #define PM_CTRL_L1_ENTRY_TIMER_MASK 0xFUL /* l1C 4bits */ 165 #define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16 166 #define L2CB1_PM_CTRL_L1_ENTRY_TM 7 167 #define L1C_PM_CTRL_L1_ENTRY_TM 0xF 168 #define PM_CTRL_RCVR_WT_TIMER BIT(15) /* 1:1us, 0:2ms */ 169 #define PM_CTRL_CLK_PWM_VER1_1 BIT(14) /* 0:1.0a,1:1.1 */ 170 #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */ 171 #define PM_CTRL_ASPM_L0S_EN BIT(12) 172 #define PM_CTRL_RXL1_AFTER_L0S BIT(11) /* l1dv2.0+ */ 173 #define L1D_PMCTRL_L0S_TIMER_MASK 7UL /* l1d2.0+, 3bits*/ 174 #define L1D_PMCTRL_L0S_TIMER_SHIFT 8 175 #define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xFUL /* l1c, 4bits */ 176 #define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8 177 #define PM_CTRL_SERDES_BUFS_RX_L1_EN BIT(7) 178 #define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */ 179 #define PM_CTRL_SERDES_PLL_L1_EN BIT(5) 180 #define PM_CTRL_SERDES_L1_EN BIT(4) 181 #define PM_CTRL_ASPM_L1_EN BIT(3) 182 #define PM_CTRL_CLK_REQ_EN BIT(2) 183 #define PM_CTRL_RBER_EN BIT(1) 184 #define PM_CTRL_SPRSDWER_EN BIT(0) 185 186 #define REG_LTSSM_ID_CTRL 0x12FC 187 #define LTSSM_ID_EN_WRO 0x1000 188 189 190 /* Selene Master Control Register */ 191 #define REG_MASTER_CTRL 0x1400 192 #define MASTER_CTRL_OTP_SEL BIT(31) 193 #define MASTER_DEV_NUM_MASK 0x7FUL 194 #define MASTER_DEV_NUM_SHIFT 24 195 #define MASTER_REV_NUM_MASK 0xFFUL 196 #define MASTER_REV_NUM_SHIFT 16 197 #define MASTER_CTRL_INT_RDCLR BIT(14) 198 #define MASTER_CTRL_CLK_SEL_DIS BIT(12) /* 1:alwys sel pclk from 199 * serdes, not sw to 25M */ 200 #define MASTER_CTRL_RX_ITIMER_EN BIT(11) /* IRQ MODURATION FOR RX */ 201 #define MASTER_CTRL_TX_ITIMER_EN BIT(10) /* MODURATION FOR TX/RX */ 202 #define MASTER_CTRL_MANU_INT BIT(9) /* SOFT MANUAL INT */ 203 #define MASTER_CTRL_MANUTIMER_EN BIT(8) 204 #define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */ 205 #define MASTER_CTRL_OOB_DIS BIT(6) /* OUT OF BOX DIS */ 206 #define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */ 207 #define MASTER_CTRL_BERT_START BIT(4) 208 #define MASTER_PCIE_TSTMOD_MASK 3UL 209 #define MASTER_PCIE_TSTMOD_SHIFT 2 210 #define MASTER_PCIE_RST BIT(1) 211 #define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */ 212 #define DMA_MAC_RST_TO 50 213 214 /* Timer Initial Value Register */ 215 #define REG_MANUAL_TIMER_INIT 0x1404 216 217 /* IRQ ModeratorTimer Initial Value Register */ 218 #define REG_IRQ_MODRT_TIMER_INIT 0x1408 219 #define IRQ_MODRT_TIMER_MASK 0xffff 220 #define IRQ_MODRT_TX_TIMER_SHIFT 0 221 #define IRQ_MODRT_RX_TIMER_SHIFT 16 222 223 #define REG_GPHY_CTRL 0x140C 224 #define GPHY_CTRL_ADDR_MASK 0x1FUL 225 #define GPHY_CTRL_ADDR_SHIFT 19 226 #define GPHY_CTRL_BP_VLTGSW BIT(18) 227 #define GPHY_CTRL_100AB_EN BIT(17) 228 #define GPHY_CTRL_10AB_EN BIT(16) 229 #define GPHY_CTRL_PHY_PLL_BYPASS BIT(15) 230 #define GPHY_CTRL_PWDOWN_HW BIT(14) /* affect MAC&PHY, to low pw */ 231 #define GPHY_CTRL_PHY_PLL_ON BIT(13) /* 1:pll always on, 0:can sw */ 232 #define GPHY_CTRL_SEL_ANA_RST BIT(12) 233 #define GPHY_CTRL_HIB_PULSE BIT(11) 234 #define GPHY_CTRL_HIB_EN BIT(10) 235 #define GPHY_CTRL_GIGA_DIS BIT(9) 236 #define GPHY_CTRL_PHY_IDDQ_DIS BIT(8) /* pw on RST */ 237 #define GPHY_CTRL_PHY_IDDQ BIT(7) /* bit8 affect bit7 while rb */ 238 #define GPHY_CTRL_LPW_EXIT BIT(6) 239 #define GPHY_CTRL_GATE_25M_EN BIT(5) 240 #define GPHY_CTRL_REV_ANEG BIT(4) 241 #define GPHY_CTRL_ANEG_NOW BIT(3) 242 #define GPHY_CTRL_LED_MODE BIT(2) 243 #define GPHY_CTRL_RTL_MODE BIT(1) 244 #define GPHY_CTRL_EXT_RESET BIT(0) /* 1:out of DSP RST status */ 245 #define GPHY_CTRL_EXT_RST_TO 80 /* 800us atmost */ 246 #define GPHY_CTRL_CLS (\ 247 GPHY_CTRL_LED_MODE |\ 248 GPHY_CTRL_100AB_EN |\ 249 GPHY_CTRL_PHY_PLL_ON) 250 251 /* Block IDLE Status Register */ 252 #define REG_IDLE_STATUS 0x1410 253 #define IDLE_STATUS_SFORCE_MASK 0xFUL 254 #define IDLE_STATUS_SFORCE_SHIFT 14 255 #define IDLE_STATUS_CALIB_DONE BIT(13) 256 #define IDLE_STATUS_CALIB_RES_MASK 0x1FUL 257 #define IDLE_STATUS_CALIB_RES_SHIFT 8 258 #define IDLE_STATUS_CALIBERR_MASK 0xFUL 259 #define IDLE_STATUS_CALIBERR_SHIFT 4 260 #define IDLE_STATUS_TXQ_BUSY BIT(3) 261 #define IDLE_STATUS_RXQ_BUSY BIT(2) 262 #define IDLE_STATUS_TXMAC_BUSY BIT(1) 263 #define IDLE_STATUS_RXMAC_BUSY BIT(0) 264 #define IDLE_STATUS_MASK (\ 265 IDLE_STATUS_TXQ_BUSY |\ 266 IDLE_STATUS_RXQ_BUSY |\ 267 IDLE_STATUS_TXMAC_BUSY |\ 268 IDLE_STATUS_RXMAC_BUSY) 269 270 /* MDIO Control Register */ 271 #define REG_MDIO_CTRL 0x1414 272 #define MDIO_CTRL_MODE_EXT BIT(30) 273 #define MDIO_CTRL_POST_READ BIT(29) 274 #define MDIO_CTRL_AP_EN BIT(28) 275 #define MDIO_CTRL_BUSY BIT(27) 276 #define MDIO_CTRL_CLK_SEL_MASK 0x7UL 277 #define MDIO_CTRL_CLK_SEL_SHIFT 24 278 #define MDIO_CTRL_CLK_25_4 0 /* 25MHz divide 4 */ 279 #define MDIO_CTRL_CLK_25_6 2 280 #define MDIO_CTRL_CLK_25_8 3 281 #define MDIO_CTRL_CLK_25_10 4 282 #define MDIO_CTRL_CLK_25_32 5 283 #define MDIO_CTRL_CLK_25_64 6 284 #define MDIO_CTRL_CLK_25_128 7 285 #define MDIO_CTRL_START BIT(23) 286 #define MDIO_CTRL_SPRES_PRMBL BIT(22) 287 #define MDIO_CTRL_OP_READ BIT(21) /* 1:read, 0:write */ 288 #define MDIO_CTRL_REG_MASK 0x1FUL 289 #define MDIO_CTRL_REG_SHIFT 16 290 #define MDIO_CTRL_DATA_MASK 0xFFFFUL 291 #define MDIO_CTRL_DATA_SHIFT 0 292 #define MDIO_MAX_AC_TO 120 /* 1.2ms timeout for slow clk */ 293 294 /* for extension reg access */ 295 #define REG_MDIO_EXTN 0x1448 296 #define MDIO_EXTN_PORTAD_MASK 0x1FUL 297 #define MDIO_EXTN_PORTAD_SHIFT 21 298 #define MDIO_EXTN_DEVAD_MASK 0x1FUL 299 #define MDIO_EXTN_DEVAD_SHIFT 16 300 #define MDIO_EXTN_REG_MASK 0xFFFFUL 301 #define MDIO_EXTN_REG_SHIFT 0 302 303 /* BIST Control and Status Register0 (for the Packet Memory) */ 304 #define REG_BIST0_CTRL 0x141c 305 #define BIST0_NOW 0x1 306 #define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is 307 * un-repairable because 308 * it has address decoder 309 * failure or more than 1 cell 310 * stuck-to-x failure */ 311 #define BIST0_FUSE_FLAG 0x4 312 313 /* BIST Control and Status Register1(for the retry buffer of PCI Express) */ 314 #define REG_BIST1_CTRL 0x1420 315 #define BIST1_NOW 0x1 316 #define BIST1_SRAM_FAIL 0x2 317 #define BIST1_FUSE_FLAG 0x4 318 319 /* SerDes Lock Detect Control and Status Register */ 320 #define REG_SERDES 0x1424 321 #define SERDES_PHY_CLK_SLOWDOWN BIT(18) 322 #define SERDES_MAC_CLK_SLOWDOWN BIT(17) 323 #define SERDES_SELFB_PLL_MASK 0x3UL 324 #define SERDES_SELFB_PLL_SHIFT 14 325 #define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */ 326 #define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */ 327 #define SERDES_BUFS_RX_EN BIT(11) 328 #define SERDES_PD_RX BIT(10) 329 #define SERDES_PLL_EN BIT(9) 330 #define SERDES_EN BIT(8) 331 #define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */ 332 #define SERDES_SELFB_PLL_CSR_MASK 0x3UL 333 #define SERDES_SELFB_PLL_CSR_SHIFT 4 334 #define SERDES_SELFB_PLL_CSR_4 3 /* 4-12% OV-CLK */ 335 #define SERDES_SELFB_PLL_CSR_0 2 /* 0-4% OV-CLK */ 336 #define SERDES_SELFB_PLL_CSR_12 1 /* 12-18% OV-CLK */ 337 #define SERDES_SELFB_PLL_CSR_18 0 /* 18-25% OV-CLK */ 338 #define SERDES_VCO_SLOW BIT(3) 339 #define SERDES_VCO_FAST BIT(2) 340 #define SERDES_LOCK_DETECT_EN BIT(1) 341 #define SERDES_LOCK_DETECT BIT(0) 342 343 #define REG_LPI_DECISN_TIMER 0x143C 344 #define L2CB_LPI_DESISN_TIMER 0x7D00 345 346 #define REG_LPI_CTRL 0x1440 347 #define LPI_CTRL_CHK_DA BIT(31) 348 #define LPI_CTRL_ENH_TO_MASK 0x1FFFUL 349 #define LPI_CTRL_ENH_TO_SHIFT 12 350 #define LPI_CTRL_ENH_TH_MASK 0x1FUL 351 #define LPI_CTRL_ENH_TH_SHIFT 6 352 #define LPI_CTRL_ENH_EN BIT(5) 353 #define LPI_CTRL_CHK_RX BIT(4) 354 #define LPI_CTRL_CHK_STATE BIT(3) 355 #define LPI_CTRL_GMII BIT(2) 356 #define LPI_CTRL_TO_PHY BIT(1) 357 #define LPI_CTRL_EN BIT(0) 358 359 #define REG_LPI_WAIT 0x1444 360 #define LPI_WAIT_TIMER_MASK 0xFFFFUL 361 #define LPI_WAIT_TIMER_SHIFT 0 362 363 /* MAC Control Register */ 364 #define REG_MAC_CTRL 0x1480 365 #define MAC_CTRL_SPEED_MODE_SW BIT(30) /* 0:phy,1:sw */ 366 #define MAC_CTRL_HASH_ALG_CRC32 BIT(29) /* 1:legacy,0:lw_5b */ 367 #define MAC_CTRL_SINGLE_PAUSE_EN BIT(28) 368 #define MAC_CTRL_DBG BIT(27) 369 #define MAC_CTRL_BC_EN BIT(26) 370 #define MAC_CTRL_MC_ALL_EN BIT(25) 371 #define MAC_CTRL_RX_CHKSUM_EN BIT(24) 372 #define MAC_CTRL_TX_HUGE BIT(23) 373 #define MAC_CTRL_DBG_TX_BKPRESURE BIT(22) 374 #define MAC_CTRL_SPEED_MASK 3UL 375 #define MAC_CTRL_SPEED_SHIFT 20 376 #define MAC_CTRL_SPEED_10_100 1 377 #define MAC_CTRL_SPEED_1000 2 378 #define MAC_CTRL_TX_SIMURST BIT(19) 379 #define MAC_CTRL_SCNT BIT(17) 380 #define MAC_CTRL_TX_PAUSE BIT(16) 381 #define MAC_CTRL_PROMIS_EN BIT(15) 382 #define MAC_CTRL_RMV_VLAN BIT(14) 383 #define MAC_CTRL_PRMLEN_MASK 0xFUL 384 #define MAC_CTRL_PRMLEN_SHIFT 10 385 #define MAC_CTRL_HUGE_EN BIT(9) 386 #define MAC_CTRL_LENCHK BIT(8) 387 #define MAC_CTRL_PAD BIT(7) 388 #define MAC_CTRL_ADD_CRC BIT(6) 389 #define MAC_CTRL_DUPLX BIT(5) 390 #define MAC_CTRL_LOOPBACK BIT(4) 391 #define MAC_CTRL_RX_FLOW BIT(3) 392 #define MAC_CTRL_TX_FLOW BIT(2) 393 #define MAC_CTRL_RX_EN BIT(1) 394 #define MAC_CTRL_TX_EN BIT(0) 395 396 /* MAC IPG/IFG Control Register */ 397 #define REG_MAC_IPG_IFG 0x1484 398 #define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back 399 * inter-packet gap. The 400 * default is 96-bit time */ 401 #define MAC_IPG_IFG_IPGT_MASK 0x7f 402 #define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to 403 * enforce in between RX frames */ 404 #define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */ 405 #define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */ 406 #define MAC_IPG_IFG_IPGR1_MASK 0x7f 407 #define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */ 408 #define MAC_IPG_IFG_IPGR2_MASK 0x7f 409 410 /* MAC STATION ADDRESS */ 411 #define REG_MAC_STA_ADDR 0x1488 412 413 /* Hash table for multicast address */ 414 #define REG_RX_HASH_TABLE 0x1490 415 416 /* MAC Half-Duplex Control Register */ 417 #define REG_MAC_HALF_DUPLX_CTRL 0x1498 418 #define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */ 419 #define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff 420 #define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 421 #define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf 422 #define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 423 #define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 424 #define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure, 425 * immediately start the 426 * transmission after back pressure */ 427 #define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */ 428 #define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */ 429 #define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf 430 #define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */ 431 #define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */ 432 433 /* Maximum Frame Length Control Register */ 434 #define REG_MTU 0x149c 435 436 /* Wake-On-Lan control register */ 437 #define REG_WOL_CTRL 0x14a0 438 #define WOL_PT7_MATCH BIT(31) 439 #define WOL_PT6_MATCH BIT(30) 440 #define WOL_PT5_MATCH BIT(29) 441 #define WOL_PT4_MATCH BIT(28) 442 #define WOL_PT3_MATCH BIT(27) 443 #define WOL_PT2_MATCH BIT(26) 444 #define WOL_PT1_MATCH BIT(25) 445 #define WOL_PT0_MATCH BIT(24) 446 #define WOL_PT7_EN BIT(23) 447 #define WOL_PT6_EN BIT(22) 448 #define WOL_PT5_EN BIT(21) 449 #define WOL_PT4_EN BIT(20) 450 #define WOL_PT3_EN BIT(19) 451 #define WOL_PT2_EN BIT(18) 452 #define WOL_PT1_EN BIT(17) 453 #define WOL_PT0_EN BIT(16) 454 #define WOL_LNKCHG_ST BIT(10) 455 #define WOL_MAGIC_ST BIT(9) 456 #define WOL_PATTERN_ST BIT(8) 457 #define WOL_OOB_EN BIT(6) 458 #define WOL_LINK_CHG_PME_EN BIT(5) 459 #define WOL_LINK_CHG_EN BIT(4) 460 #define WOL_MAGIC_PME_EN BIT(3) 461 #define WOL_MAGIC_EN BIT(2) 462 #define WOL_PATTERN_PME_EN BIT(1) 463 #define WOL_PATTERN_EN BIT(0) 464 465 /* WOL Length ( 2 DWORD ) */ 466 #define REG_WOL_PTLEN1 0x14A4 467 #define WOL_PTLEN1_3_MASK 0xFFUL 468 #define WOL_PTLEN1_3_SHIFT 24 469 #define WOL_PTLEN1_2_MASK 0xFFUL 470 #define WOL_PTLEN1_2_SHIFT 16 471 #define WOL_PTLEN1_1_MASK 0xFFUL 472 #define WOL_PTLEN1_1_SHIFT 8 473 #define WOL_PTLEN1_0_MASK 0xFFUL 474 #define WOL_PTLEN1_0_SHIFT 0 475 476 #define REG_WOL_PTLEN2 0x14A8 477 #define WOL_PTLEN2_7_MASK 0xFFUL 478 #define WOL_PTLEN2_7_SHIFT 24 479 #define WOL_PTLEN2_6_MASK 0xFFUL 480 #define WOL_PTLEN2_6_SHIFT 16 481 #define WOL_PTLEN2_5_MASK 0xFFUL 482 #define WOL_PTLEN2_5_SHIFT 8 483 #define WOL_PTLEN2_4_MASK 0xFFUL 484 #define WOL_PTLEN2_4_SHIFT 0 485 486 /* Internal SRAM Partition Register */ 487 #define RFDX_HEAD_ADDR_MASK 0x03FF 488 #define RFDX_HARD_ADDR_SHIFT 0 489 #define RFDX_TAIL_ADDR_MASK 0x03FF 490 #define RFDX_TAIL_ADDR_SHIFT 16 491 492 #define REG_SRAM_RFD0_INFO 0x1500 493 #define REG_SRAM_RFD1_INFO 0x1504 494 #define REG_SRAM_RFD2_INFO 0x1508 495 #define REG_SRAM_RFD3_INFO 0x150C 496 497 #define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */ 498 #define RFD_NIC_LEN_MASK 0x03FF 499 500 #define REG_SRAM_TRD_ADDR 0x1518 501 #define TPD_HEAD_ADDR_MASK 0x03FF 502 #define TPD_HEAD_ADDR_SHIFT 0 503 #define TPD_TAIL_ADDR_MASK 0x03FF 504 #define TPD_TAIL_ADDR_SHIFT 16 505 506 #define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */ 507 #define TPD_NIC_LEN_MASK 0x03FF 508 509 #define REG_SRAM_RXF_ADDR 0x1520 510 #define REG_SRAM_RXF_LEN 0x1524 511 #define REG_SRAM_TXF_ADDR 0x1528 512 #define REG_SRAM_TXF_LEN 0x152C 513 #define REG_SRAM_TCPH_ADDR 0x1530 514 #define REG_SRAM_PKTH_ADDR 0x1532 515 516 /* 517 * Load Ptr Register 518 * Software sets this bit after the initialization of the head and tail */ 519 #define REG_LOAD_PTR 0x1534 520 521 /* 522 * addresses of all descriptors, as well as the following descriptor 523 * control register, which triggers each function block to load the head 524 * pointer to prepare for the operation. This bit is then self-cleared 525 * after one cycle. 526 */ 527 #define REG_RX_BASE_ADDR_HI 0x1540 528 #define REG_TX_BASE_ADDR_HI 0x1544 529 #define REG_RFD0_HEAD_ADDR_LO 0x1550 530 #define REG_RFD_RING_SIZE 0x1560 531 #define RFD_RING_SIZE_MASK 0x0FFF 532 #define REG_RX_BUF_SIZE 0x1564 533 #define RX_BUF_SIZE_MASK 0xFFFF 534 #define REG_RRD0_HEAD_ADDR_LO 0x1568 535 #define REG_RRD_RING_SIZE 0x1578 536 #define RRD_RING_SIZE_MASK 0x0FFF 537 #define REG_TPD_PRI1_ADDR_LO 0x157C 538 #define REG_TPD_PRI0_ADDR_LO 0x1580 539 #define REG_TPD_RING_SIZE 0x1584 540 #define TPD_RING_SIZE_MASK 0xFFFF 541 542 /* TXQ Control Register */ 543 #define REG_TXQ_CTRL 0x1590 544 #define TXQ_TXF_BURST_NUM_MASK 0xFFFFUL 545 #define TXQ_TXF_BURST_NUM_SHIFT 16 546 #define L1C_TXQ_TXF_BURST_PREF 0x200 547 #define L2CB_TXQ_TXF_BURST_PREF 0x40 548 #define TXQ_CTRL_PEDING_CLR BIT(8) 549 #define TXQ_CTRL_LS_8023_EN BIT(7) 550 #define TXQ_CTRL_ENH_MODE BIT(6) 551 #define TXQ_CTRL_EN BIT(5) 552 #define TXQ_CTRL_IP_OPTION_EN BIT(4) 553 #define TXQ_NUM_TPD_BURST_MASK 0xFUL 554 #define TXQ_NUM_TPD_BURST_SHIFT 0 555 #define TXQ_NUM_TPD_BURST_DEF 5 556 #define TXQ_CFGV (\ 557 FIELDX(TXQ_NUM_TPD_BURST, TXQ_NUM_TPD_BURST_DEF) |\ 558 TXQ_CTRL_ENH_MODE |\ 559 TXQ_CTRL_LS_8023_EN |\ 560 TXQ_CTRL_IP_OPTION_EN) 561 #define L1C_TXQ_CFGV (\ 562 TXQ_CFGV |\ 563 FIELDX(TXQ_TXF_BURST_NUM, L1C_TXQ_TXF_BURST_PREF)) 564 #define L2CB_TXQ_CFGV (\ 565 TXQ_CFGV |\ 566 FIELDX(TXQ_TXF_BURST_NUM, L2CB_TXQ_TXF_BURST_PREF)) 567 568 569 /* Jumbo packet Threshold for task offload */ 570 #define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */ 571 #define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF 572 #define MAX_TSO_FRAME_SIZE (7*1024) 573 574 #define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */ 575 #define TXF_WATER_MARK_MASK 0x0FFF 576 #define TXF_LOW_WATER_MARK_SHIFT 0 577 #define TXF_HIGH_WATER_MARK_SHIFT 16 578 #define TXQ_CTRL_BURST_MODE_EN 0x80000000 579 580 #define REG_THRUPUT_MON_CTRL 0x159C 581 #define THRUPUT_MON_RATE_MASK 0x3 582 #define THRUPUT_MON_RATE_SHIFT 0 583 #define THRUPUT_MON_EN 0x80 584 585 /* RXQ Control Register */ 586 #define REG_RXQ_CTRL 0x15A0 587 #define ASPM_THRUPUT_LIMIT_MASK 0x3 588 #define ASPM_THRUPUT_LIMIT_SHIFT 0 589 #define ASPM_THRUPUT_LIMIT_NO 0x00 590 #define ASPM_THRUPUT_LIMIT_1M 0x01 591 #define ASPM_THRUPUT_LIMIT_10M 0x02 592 #define ASPM_THRUPUT_LIMIT_100M 0x03 593 #define IPV6_CHKSUM_CTRL_EN BIT(7) 594 #define RXQ_RFD_BURST_NUM_MASK 0x003F 595 #define RXQ_RFD_BURST_NUM_SHIFT 20 596 #define RXQ_NUM_RFD_PREF_DEF 8 597 #define RSS_MODE_MASK 3UL 598 #define RSS_MODE_SHIFT 26 599 #define RSS_MODE_DIS 0 600 #define RSS_MODE_SQSI 1 601 #define RSS_MODE_MQSI 2 602 #define RSS_MODE_MQMI 3 603 #define RSS_NIP_QUEUE_SEL BIT(28) /* 0:q0, 1:table */ 604 #define RRS_HASH_CTRL_EN BIT(29) 605 #define RX_CUT_THRU_EN BIT(30) 606 #define RXQ_CTRL_EN BIT(31) 607 608 #define REG_RFD_FREE_THRESH 0x15A4 609 #define RFD_FREE_THRESH_MASK 0x003F 610 #define RFD_FREE_HI_THRESH_SHIFT 0 611 #define RFD_FREE_LO_THRESH_SHIFT 6 612 613 /* RXF flow control register */ 614 #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 615 #define RXQ_RXF_PAUSE_TH_HI_SHIFT 0 616 #define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF 617 #define RXQ_RXF_PAUSE_TH_LO_SHIFT 16 618 #define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF 619 620 #define REG_RXD_DMA_CTRL 0x15AC 621 #define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */ 622 #define RXD_DMA_THRESH_SHIFT 0 623 #define RXD_DMA_DOWN_TIMER_MASK 0xFFFF 624 #define RXD_DMA_DOWN_TIMER_SHIFT 16 625 626 /* DMA Engine Control Register */ 627 #define REG_DMA_CTRL 0x15C0 628 #define DMA_CTRL_SMB_NOW BIT(31) 629 #define DMA_CTRL_WPEND_CLR BIT(30) 630 #define DMA_CTRL_RPEND_CLR BIT(29) 631 #define DMA_CTRL_WDLY_CNT_MASK 0xFUL 632 #define DMA_CTRL_WDLY_CNT_SHIFT 16 633 #define DMA_CTRL_WDLY_CNT_DEF 4 634 #define DMA_CTRL_RDLY_CNT_MASK 0x1FUL 635 #define DMA_CTRL_RDLY_CNT_SHIFT 11 636 #define DMA_CTRL_RDLY_CNT_DEF 15 637 #define DMA_CTRL_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */ 638 #define DMA_CTRL_WREQ_BLEN_MASK 7UL 639 #define DMA_CTRL_WREQ_BLEN_SHIFT 7 640 #define DMA_CTRL_RREQ_BLEN_MASK 7UL 641 #define DMA_CTRL_RREQ_BLEN_SHIFT 4 642 #define L1C_CTRL_DMA_RCB_LEN128 BIT(3) /* 0:64bytes,1:128bytes */ 643 #define DMA_CTRL_RORDER_MODE_MASK 7UL 644 #define DMA_CTRL_RORDER_MODE_SHIFT 0 645 #define DMA_CTRL_RORDER_MODE_OUT 4 646 #define DMA_CTRL_RORDER_MODE_ENHANCE 2 647 #define DMA_CTRL_RORDER_MODE_IN 1 648 649 /* INT-triggle/SMB Control Register */ 650 #define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */ 651 #define SMB_STAT_TIMER_MASK 0xFFFFFF 652 #define REG_TINT_TPD_THRESH 0x15C8 /* tpd th to trig intrrupt */ 653 654 /* Mail box */ 655 #define MB_RFDX_PROD_IDX_MASK 0xFFFF 656 #define REG_MB_RFD0_PROD_IDX 0x15E0 657 658 #define REG_TPD_PRI1_PIDX 0x15F0 /* 16bit,hi-tpd producer idx */ 659 #define REG_TPD_PRI0_PIDX 0x15F2 /* 16bit,lo-tpd producer idx */ 660 #define REG_TPD_PRI1_CIDX 0x15F4 /* 16bit,hi-tpd consumer idx */ 661 #define REG_TPD_PRI0_CIDX 0x15F6 /* 16bit,lo-tpd consumer idx */ 662 663 #define REG_MB_RFD01_CONS_IDX 0x15F8 664 #define MB_RFD0_CONS_IDX_MASK 0x0000FFFF 665 #define MB_RFD1_CONS_IDX_MASK 0xFFFF0000 666 667 /* Interrupt Status Register */ 668 #define REG_ISR 0x1600 669 #define ISR_SMB 0x00000001 670 #define ISR_TIMER 0x00000002 671 /* 672 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set 673 * in Table 51 Selene Master Control Register (Offset 0x1400). 674 */ 675 #define ISR_MANUAL 0x00000004 676 #define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */ 677 #define ISR_RFD0_UR 0x00000010 /* RFD0 under run */ 678 #define ISR_RFD1_UR 0x00000020 679 #define ISR_RFD2_UR 0x00000040 680 #define ISR_RFD3_UR 0x00000080 681 #define ISR_TXF_UR 0x00000100 682 #define ISR_DMAR_TO_RST 0x00000200 683 #define ISR_DMAW_TO_RST 0x00000400 684 #define ISR_TX_CREDIT 0x00000800 685 #define ISR_GPHY 0x00001000 686 /* GPHY low power state interrupt */ 687 #define ISR_GPHY_LPW 0x00002000 688 #define ISR_TXQ_TO_RST 0x00004000 689 #define ISR_TX_PKT 0x00008000 690 #define ISR_RX_PKT_0 0x00010000 691 #define ISR_RX_PKT_1 0x00020000 692 #define ISR_RX_PKT_2 0x00040000 693 #define ISR_RX_PKT_3 0x00080000 694 #define ISR_MAC_RX 0x00100000 695 #define ISR_MAC_TX 0x00200000 696 #define ISR_UR_DETECTED 0x00400000 697 #define ISR_FERR_DETECTED 0x00800000 698 #define ISR_NFERR_DETECTED 0x01000000 699 #define ISR_CERR_DETECTED 0x02000000 700 #define ISR_PHY_LINKDOWN 0x04000000 701 #define ISR_DIS_INT 0x80000000 702 703 /* Interrupt Mask Register */ 704 #define REG_IMR 0x1604 705 706 #define IMR_NORMAL_MASK (\ 707 ISR_MANUAL |\ 708 ISR_HW_RXF_OV |\ 709 ISR_RFD0_UR |\ 710 ISR_TXF_UR |\ 711 ISR_DMAR_TO_RST |\ 712 ISR_TXQ_TO_RST |\ 713 ISR_DMAW_TO_RST |\ 714 ISR_GPHY |\ 715 ISR_TX_PKT |\ 716 ISR_RX_PKT_0 |\ 717 ISR_GPHY_LPW |\ 718 ISR_PHY_LINKDOWN) 719 720 #define ISR_RX_PKT (\ 721 ISR_RX_PKT_0 |\ 722 ISR_RX_PKT_1 |\ 723 ISR_RX_PKT_2 |\ 724 ISR_RX_PKT_3) 725 726 #define ISR_OVER (\ 727 ISR_RFD0_UR |\ 728 ISR_RFD1_UR |\ 729 ISR_RFD2_UR |\ 730 ISR_RFD3_UR |\ 731 ISR_HW_RXF_OV |\ 732 ISR_TXF_UR) 733 734 #define ISR_ERROR (\ 735 ISR_DMAR_TO_RST |\ 736 ISR_TXQ_TO_RST |\ 737 ISR_DMAW_TO_RST |\ 738 ISR_PHY_LINKDOWN) 739 740 #define REG_INT_RETRIG_TIMER 0x1608 741 #define INT_RETRIG_TIMER_MASK 0xFFFF 742 743 #define REG_MAC_RX_STATUS_BIN 0x1700 744 #define REG_MAC_RX_STATUS_END 0x175c 745 #define REG_MAC_TX_STATUS_BIN 0x1760 746 #define REG_MAC_TX_STATUS_END 0x17c0 747 748 #define REG_CLK_GATING_CTRL 0x1814 749 #define CLK_GATING_DMAW_EN 0x0001 750 #define CLK_GATING_DMAR_EN 0x0002 751 #define CLK_GATING_TXQ_EN 0x0004 752 #define CLK_GATING_RXQ_EN 0x0008 753 #define CLK_GATING_TXMAC_EN 0x0010 754 #define CLK_GATING_RXMAC_EN 0x0020 755 756 #define CLK_GATING_EN_ALL (CLK_GATING_DMAW_EN |\ 757 CLK_GATING_DMAR_EN |\ 758 CLK_GATING_TXQ_EN |\ 759 CLK_GATING_RXQ_EN |\ 760 CLK_GATING_TXMAC_EN|\ 761 CLK_GATING_RXMAC_EN) 762 763 /* DEBUG ADDR */ 764 #define REG_DEBUG_DATA0 0x1900 765 #define REG_DEBUG_DATA1 0x1904 766 767 #define L1D_MPW_PHYID1 0xD01C /* V7 */ 768 #define L1D_MPW_PHYID2 0xD01D /* V1-V6 */ 769 #define L1D_MPW_PHYID3 0xD01E /* V8 */ 770 771 772 /* Autoneg Advertisement Register */ 773 #define ADVERTISE_DEFAULT_CAP \ 774 (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM) 775 776 /* 1000BASE-T Control Register */ 777 #define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */ 778 779 #define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 780 #define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 781 #define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 782 #define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 783 #define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 784 #define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 785 #define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 786 #define GIGA_CR_1000T_SPEED_MASK 0x0300 787 #define GIGA_CR_1000T_DEFAULT_CAP 0x0300 788 789 /* PHY Specific Status Register */ 790 #define MII_GIGA_PSSR 0x11 791 #define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 792 #define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 793 #define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 794 #define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */ 795 #define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */ 796 #define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 797 798 /* PHY Interrupt Enable Register */ 799 #define MII_IER 0x12 800 #define IER_LINK_UP 0x0400 801 #define IER_LINK_DOWN 0x0800 802 803 /* PHY Interrupt Status Register */ 804 #define MII_ISR 0x13 805 #define ISR_LINK_UP 0x0400 806 #define ISR_LINK_DOWN 0x0800 807 808 /* Cable-Detect-Test Control Register */ 809 #define MII_CDTC 0x16 810 #define CDTC_EN_OFF 0 /* sc */ 811 #define CDTC_EN_BITS 1 812 #define CDTC_PAIR_OFF 8 813 #define CDTC_PAIR_BIT 2 814 815 /* Cable-Detect-Test Status Register */ 816 #define MII_CDTS 0x1C 817 #define CDTS_STATUS_OFF 8 818 #define CDTS_STATUS_BITS 2 819 #define CDTS_STATUS_NORMAL 0 820 #define CDTS_STATUS_SHORT 1 821 #define CDTS_STATUS_OPEN 2 822 #define CDTS_STATUS_INVALID 3 823 824 #define MII_DBG_ADDR 0x1D 825 #define MII_DBG_DATA 0x1E 826 827 /***************************** debug port *************************************/ 828 829 #define MIIDBG_ANACTRL 0x00 830 #define ANACTRL_CLK125M_DELAY_EN 0x8000 831 #define ANACTRL_VCO_FAST 0x4000 832 #define ANACTRL_VCO_SLOW 0x2000 833 #define ANACTRL_AFE_MODE_EN 0x1000 834 #define ANACTRL_LCKDET_PHY 0x800 835 #define ANACTRL_LCKDET_EN 0x400 836 #define ANACTRL_OEN_125M 0x200 837 #define ANACTRL_HBIAS_EN 0x100 838 #define ANACTRL_HB_EN 0x80 839 #define ANACTRL_SEL_HSP 0x40 840 #define ANACTRL_CLASSA_EN 0x20 841 #define ANACTRL_MANUSWON_SWR_MASK 3U 842 #define ANACTRL_MANUSWON_SWR_SHIFT 2 843 #define ANACTRL_MANUSWON_SWR_2V 0 844 #define ANACTRL_MANUSWON_SWR_1P9V 1 845 #define ANACTRL_MANUSWON_SWR_1P8V 2 846 #define ANACTRL_MANUSWON_SWR_1P7V 3 847 #define ANACTRL_MANUSWON_BW3_4M 0x2 848 #define ANACTRL_RESTART_CAL 0x1 849 #define ANACTRL_DEF 0x02EF 850 851 #define MIIDBG_SYSMODCTRL 0x04 852 #define SYSMODCTRL_IECHOADJ_PFMH_PHY 0x8000 853 #define SYSMODCTRL_IECHOADJ_BIASGEN 0x4000 854 #define SYSMODCTRL_IECHOADJ_PFML_PHY 0x2000 855 #define SYSMODCTRL_IECHOADJ_PS_MASK 3U 856 #define SYSMODCTRL_IECHOADJ_PS_SHIFT 10 857 #define SYSMODCTRL_IECHOADJ_PS_40 3 858 #define SYSMODCTRL_IECHOADJ_PS_20 2 859 #define SYSMODCTRL_IECHOADJ_PS_0 1 860 #define SYSMODCTRL_IECHOADJ_10BT_100MV 0x40 /* 1:100mv, 0:200mv */ 861 #define SYSMODCTRL_IECHOADJ_HLFAP_MASK 3U 862 #define SYSMODCTRL_IECHOADJ_HLFAP_SHIFT 4 863 #define SYSMODCTRL_IECHOADJ_VDFULBW 0x8 864 #define SYSMODCTRL_IECHOADJ_VDBIASHLF 0x4 865 #define SYSMODCTRL_IECHOADJ_VDAMPHLF 0x2 866 #define SYSMODCTRL_IECHOADJ_VDLANSW 0x1 867 #define SYSMODCTRL_IECHOADJ_DEF 0x88BB /* ???? */ 868 869 /* for l1d & l2cb */ 870 #define SYSMODCTRL_IECHOADJ_CUR_ADD 0x8000 871 #define SYSMODCTRL_IECHOADJ_CUR_MASK 7U 872 #define SYSMODCTRL_IECHOADJ_CUR_SHIFT 12 873 #define SYSMODCTRL_IECHOADJ_VOL_MASK 0xFU 874 #define SYSMODCTRL_IECHOADJ_VOL_SHIFT 8 875 #define SYSMODCTRL_IECHOADJ_VOL_17ALL 3 876 #define SYSMODCTRL_IECHOADJ_VOL_100M15 1 877 #define SYSMODCTRL_IECHOADJ_VOL_10M17 0 878 #define SYSMODCTRL_IECHOADJ_BIAS1_MASK 0xFU 879 #define SYSMODCTRL_IECHOADJ_BIAS1_SHIFT 4 880 #define SYSMODCTRL_IECHOADJ_BIAS2_MASK 0xFU 881 #define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT 0 882 #define L1D_SYSMODCTRL_IECHOADJ_DEF 0x4FBB 883 884 #define MIIDBG_SRDSYSMOD 0x05 885 #define SRDSYSMOD_LCKDET_EN 0x2000 886 #define SRDSYSMOD_PLL_EN 0x800 887 #define SRDSYSMOD_SEL_HSP 0x400 888 #define SRDSYSMOD_HLFTXDR 0x200 889 #define SRDSYSMOD_TXCLK_DELAY_EN 0x100 890 #define SRDSYSMOD_TXELECIDLE 0x80 891 #define SRDSYSMOD_DEEMP_EN 0x40 892 #define SRDSYSMOD_MS_PAD 0x4 893 #define SRDSYSMOD_CDR_ADC_VLTG 0x2 894 #define SRDSYSMOD_CDR_DAC_1MA 0x1 895 #define SRDSYSMOD_DEF 0x2C46 896 897 #define MIIDBG_CFGLPSPD 0x0A 898 #define CFGLPSPD_RSTCNT_MASK 3U 899 #define CFGLPSPD_RSTCNT_SHIFT 14 900 #define CFGLPSPD_RSTCNT_CLK125SW 0x2000 901 902 #define MIIDBG_HIBNEG 0x0B 903 #define HIBNEG_PSHIB_EN 0x8000 904 #define HIBNEG_WAKE_BOTH 0x4000 905 #define HIBNEG_ONOFF_ANACHG_SUDEN 0x2000 906 #define HIBNEG_HIB_PULSE 0x1000 907 #define HIBNEG_GATE_25M_EN 0x800 908 #define HIBNEG_RST_80U 0x400 909 #define HIBNEG_RST_TIMER_MASK 3U 910 #define HIBNEG_RST_TIMER_SHIFT 8 911 #define HIBNEG_GTX_CLK_DELAY_MASK 3U 912 #define HIBNEG_GTX_CLK_DELAY_SHIFT 5 913 #define HIBNEG_BYPSS_BRKTIMER 0x10 914 #define HIBNEG_DEF 0xBC40 915 916 #define MIIDBG_TST10BTCFG 0x12 917 #define TST10BTCFG_INTV_TIMER_MASK 3U 918 #define TST10BTCFG_INTV_TIMER_SHIFT 14 919 #define TST10BTCFG_TRIGER_TIMER_MASK 3U 920 #define TST10BTCFG_TRIGER_TIMER_SHIFT 12 921 #define TST10BTCFG_DIV_MAN_MLT3_EN 0x800 922 #define TST10BTCFG_OFF_DAC_IDLE 0x400 923 #define TST10BTCFG_LPBK_DEEP 0x4 /* 1:deep,0:shallow */ 924 #define TST10BTCFG_DEF 0x4C04 925 926 #define MIIDBG_AZ_ANADECT 0x15 927 #define AZ_ANADECT_10BTRX_TH 0x8000 928 #define AZ_ANADECT_BOTH_01CHNL 0x4000 929 #define AZ_ANADECT_INTV_MASK 0x3FU 930 #define AZ_ANADECT_INTV_SHIFT 8 931 #define AZ_ANADECT_THRESH_MASK 0xFU 932 #define AZ_ANADECT_THRESH_SHIFT 4 933 #define AZ_ANADECT_CHNL_MASK 0xFU 934 #define AZ_ANADECT_CHNL_SHIFT 0 935 #define AZ_ANADECT_DEF 0x3220 936 #define AZ_ANADECT_LONG 0xb210 937 938 #define MIIDBG_MSE16DB 0x18 /* l1d */ 939 #define L1D_MSE16DB_UP 0x05EA 940 #define L1D_MSE16DB_DOWN 0x02EA 941 942 #define MIIDBG_LEGCYPS 0x29 943 #define LEGCYPS_EN 0x8000 944 #define LEGCYPS_DAC_AMP1000_MASK 7U 945 #define LEGCYPS_DAC_AMP1000_SHIFT 12 946 #define LEGCYPS_DAC_AMP100_MASK 7U 947 #define LEGCYPS_DAC_AMP100_SHIFT 9 948 #define LEGCYPS_DAC_AMP10_MASK 7U 949 #define LEGCYPS_DAC_AMP10_SHIFT 6 950 #define LEGCYPS_UNPLUG_TIMER_MASK 7U 951 #define LEGCYPS_UNPLUG_TIMER_SHIFT 3 952 #define LEGCYPS_UNPLUG_DECT_EN 0x4 953 #define LEGCYPS_ECNC_PS_EN 0x1 954 #define L1D_LEGCYPS_DEF 0x129D 955 #define L1C_LEGCYPS_DEF 0x36DD 956 957 #define MIIDBG_TST100BTCFG 0x36 958 #define TST100BTCFG_NORMAL_BW_EN 0x8000 959 #define TST100BTCFG_BADLNK_BYPASS 0x4000 960 #define TST100BTCFG_SHORTCABL_TH_MASK 0x3FU 961 #define TST100BTCFG_SHORTCABL_TH_SHIFT 8 962 #define TST100BTCFG_LITCH_EN 0x80 963 #define TST100BTCFG_VLT_SW 0x40 964 #define TST100BTCFG_LONGCABL_TH_MASK 0x3FU 965 #define TST100BTCFG_LONGCABL_TH_SHIFT 0 966 #define TST100BTCFG_DEF 0xE12C 967 968 #define MIIDBG_VOLT_CTRL 0x3B /* only for l2cb 1 & 2 */ 969 #define VOLT_CTRL_CABLE1TH_MASK 0x1FFU 970 #define VOLT_CTRL_CABLE1TH_SHIFT 7 971 #define VOLT_CTRL_AMPCTRL_MASK 3U 972 #define VOLT_CTRL_AMPCTRL_SHIFT 5 973 #define VOLT_CTRL_SW_BYPASS 0x10 974 #define VOLT_CTRL_SWLOWEST 0x8 975 #define VOLT_CTRL_DACAMP10_MASK 7U 976 #define VOLT_CTRL_DACAMP10_SHIFT 0 977 978 #define MIIDBG_CABLE1TH_DET 0x3E 979 #define CABLE1TH_DET_EN 0x8000 980 981 982 /******* dev 3 *********/ 983 #define MIIEXT_PCS 3 984 985 #define MIIEXT_CLDCTRL3 0x8003 986 #define CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000 987 #define CLDCTRL3_AZ_DISAMP 0x1000 988 #define L2CB_CLDCTRL3 0x4D19 989 #define L1D_CLDCTRL3 0xDD19 990 991 #define MIIEXT_CLDCTRL6 0x8006 992 #define CLDCTRL6_CAB_LEN_MASK 0x1FFU 993 #define CLDCTRL6_CAB_LEN_SHIFT 0 994 #define CLDCTRL6_CAB_LEN_SHORT 0x50 995 996 /********* dev 7 **********/ 997 #define MIIEXT_ANEG 7 998 999 #define MIIEXT_LOCAL_EEEADV 0x3C 1000 #define LOCAL_EEEADV_1000BT 0x4 1001 #define LOCAL_EEEADV_100BT 0x2 1002 1003 #define MIIEXT_REMOTE_EEEADV 0x3D 1004 #define REMOTE_EEEADV_1000BT 0x4 1005 #define REMOTE_EEEADV_100BT 0x2 1006 1007 #define MIIEXT_EEE_ANEG 0x8000 1008 #define EEE_ANEG_1000M 0x4 1009 #define EEE_ANEG_100M 0x2 1010 1011 #endif /*_ATL1C_HW_H_*/ 1012