1 /* bnx2x_init.h: Qlogic Everest network driver.
2  *               Structures and macroes needed during the initialization.
3  *
4  * Copyright (c) 2007-2013 Broadcom Corporation
5  * Copyright (c) 2014 QLogic Corporation
6  All rights reserved
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation.
11  *
12  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
13  * Written by: Eliezer Tamir
14  * Modified by: Vladislav Zolotarov
15  */
16 
17 #ifndef BNX2X_INIT_H
18 #define BNX2X_INIT_H
19 
20 /* Init operation types and structures */
21 enum {
22 	OP_RD = 0x1,	/* read a single register */
23 	OP_WR,		/* write a single register */
24 	OP_SW,		/* copy a string to the device */
25 	OP_ZR,		/* clear memory */
26 	OP_ZP,		/* unzip then copy with DMAE */
27 	OP_WR_64,	/* write 64 bit pattern */
28 	OP_WB,		/* copy a string using DMAE */
29 	OP_WB_ZR,	/* Clear a string using DMAE or indirect-wr */
30 	/* Skip the following ops if all of the init modes don't match */
31 	OP_IF_MODE_OR,
32 	/* Skip the following ops if any of the init modes don't match */
33 	OP_IF_MODE_AND,
34 	OP_MAX
35 };
36 
37 enum {
38 	STAGE_START,
39 	STAGE_END,
40 };
41 
42 /* Returns the index of start or end of a specific block stage in ops array*/
43 #define BLOCK_OPS_IDX(block, stage, end) \
44 	(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
45 
46 
47 /* structs for the various opcodes */
48 struct raw_op {
49 	u32 op:8;
50 	u32 offset:24;
51 	u32 raw_data;
52 };
53 
54 struct op_read {
55 	u32 op:8;
56 	u32 offset:24;
57 	u32 val;
58 };
59 
60 struct op_write {
61 	u32 op:8;
62 	u32 offset:24;
63 	u32 val;
64 };
65 
66 struct op_arr_write {
67 	u32 op:8;
68 	u32 offset:24;
69 #ifdef __BIG_ENDIAN
70 	u16 data_len;
71 	u16 data_off;
72 #else /* __LITTLE_ENDIAN */
73 	u16 data_off;
74 	u16 data_len;
75 #endif
76 };
77 
78 struct op_zero {
79 	u32 op:8;
80 	u32 offset:24;
81 	u32 len;
82 };
83 
84 struct op_if_mode {
85 	u32 op:8;
86 	u32 cmd_offset:24;
87 	u32 mode_bit_map;
88 };
89 
90 
91 union init_op {
92 	struct op_read		read;
93 	struct op_write		write;
94 	struct op_arr_write	arr_wr;
95 	struct op_zero		zero;
96 	struct raw_op		raw;
97 	struct op_if_mode	if_mode;
98 };
99 
100 
101 /* Init Phases */
102 enum {
103 	PHASE_COMMON,
104 	PHASE_PORT0,
105 	PHASE_PORT1,
106 	PHASE_PF0,
107 	PHASE_PF1,
108 	PHASE_PF2,
109 	PHASE_PF3,
110 	PHASE_PF4,
111 	PHASE_PF5,
112 	PHASE_PF6,
113 	PHASE_PF7,
114 	NUM_OF_INIT_PHASES
115 };
116 
117 /* Init Modes */
118 enum {
119 	MODE_ASIC                      = 0x00000001,
120 	MODE_FPGA                      = 0x00000002,
121 	MODE_EMUL                      = 0x00000004,
122 	MODE_E2                        = 0x00000008,
123 	MODE_E3                        = 0x00000010,
124 	MODE_PORT2                     = 0x00000020,
125 	MODE_PORT4                     = 0x00000040,
126 	MODE_SF                        = 0x00000080,
127 	MODE_MF                        = 0x00000100,
128 	MODE_MF_SD                     = 0x00000200,
129 	MODE_MF_SI                     = 0x00000400,
130 	MODE_MF_AFEX                   = 0x00000800,
131 	MODE_E3_A0                     = 0x00001000,
132 	MODE_E3_B0                     = 0x00002000,
133 	MODE_COS3                      = 0x00004000,
134 	MODE_COS6                      = 0x00008000,
135 	MODE_LITTLE_ENDIAN             = 0x00010000,
136 	MODE_BIG_ENDIAN                = 0x00020000,
137 };
138 
139 /* Init Blocks */
140 enum {
141 	BLOCK_ATC,
142 	BLOCK_BRB1,
143 	BLOCK_CCM,
144 	BLOCK_CDU,
145 	BLOCK_CFC,
146 	BLOCK_CSDM,
147 	BLOCK_CSEM,
148 	BLOCK_DBG,
149 	BLOCK_DMAE,
150 	BLOCK_DORQ,
151 	BLOCK_HC,
152 	BLOCK_IGU,
153 	BLOCK_MISC,
154 	BLOCK_NIG,
155 	BLOCK_PBF,
156 	BLOCK_PGLUE_B,
157 	BLOCK_PRS,
158 	BLOCK_PXP2,
159 	BLOCK_PXP,
160 	BLOCK_QM,
161 	BLOCK_SRC,
162 	BLOCK_TCM,
163 	BLOCK_TM,
164 	BLOCK_TSDM,
165 	BLOCK_TSEM,
166 	BLOCK_UCM,
167 	BLOCK_UPB,
168 	BLOCK_USDM,
169 	BLOCK_USEM,
170 	BLOCK_XCM,
171 	BLOCK_XPB,
172 	BLOCK_XSDM,
173 	BLOCK_XSEM,
174 	BLOCK_MISC_AEU,
175 	NUM_OF_INIT_BLOCKS
176 };
177 
178 /* QM queue numbers */
179 #define BNX2X_ETH_Q		0
180 #define BNX2X_TOE_Q		3
181 #define BNX2X_TOE_ACK_Q		6
182 #define BNX2X_ISCSI_Q		9
183 #define BNX2X_ISCSI_ACK_Q	11
184 #define BNX2X_FCOE_Q		10
185 
186 /* Vnics per mode */
187 #define BNX2X_PORT2_MODE_NUM_VNICS 4
188 #define BNX2X_PORT4_MODE_NUM_VNICS 2
189 
190 /* COS offset for port1 in E3 B0 4port mode */
191 #define BNX2X_E3B0_PORT1_COS_OFFSET 3
192 
193 /* QM Register addresses */
194 #define BNX2X_Q_VOQ_REG_ADDR(pf_q_num)\
195 	(QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
196 #define BNX2X_VOQ_Q_REG_ADDR(cos, pf_q_num)\
197 	(QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
198 #define BNX2X_Q_CMDQ_REG_ADDR(pf_q_num)\
199 	(QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
200 
201 /* extracts the QM queue number for the specified port and vnic */
202 #define BNX2X_PF_Q_NUM(q_num, port, vnic)\
203 	((((port) << 1) | (vnic)) * 16 + (q_num))
204 
205 
206 /* Maps the specified queue to the specified COS */
207 static inline void bnx2x_map_q_cos(struct bnx2x *bp, u32 q_num, u32 new_cos)
208 {
209 	/* find current COS mapping */
210 	u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4);
211 
212 	/* check if queue->COS mapping has changed */
213 	if (curr_cos != new_cos) {
214 		u32 num_vnics = BNX2X_PORT2_MODE_NUM_VNICS;
215 		u32 reg_addr, reg_bit_map, vnic;
216 
217 		/* update parameters for 4port mode */
218 		if (INIT_MODE_FLAGS(bp) & MODE_PORT4) {
219 			num_vnics = BNX2X_PORT4_MODE_NUM_VNICS;
220 			if (BP_PORT(bp)) {
221 				curr_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
222 				new_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
223 			}
224 		}
225 
226 		/* change queue mapping for each VNIC */
227 		for (vnic = 0; vnic < num_vnics; vnic++) {
228 			u32 pf_q_num =
229 				BNX2X_PF_Q_NUM(q_num, BP_PORT(bp), vnic);
230 			u32 q_bit_map = 1 << (pf_q_num & 0x1f);
231 
232 			/* overwrite queue->VOQ mapping */
233 			REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
234 
235 			/* clear queue bit from current COS bit map */
236 			reg_addr = BNX2X_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
237 			reg_bit_map = REG_RD(bp, reg_addr);
238 			REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map));
239 
240 			/* set queue bit in new COS bit map */
241 			reg_addr = BNX2X_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
242 			reg_bit_map = REG_RD(bp, reg_addr);
243 			REG_WR(bp, reg_addr, reg_bit_map | q_bit_map);
244 
245 			/* set/clear queue bit in command-queue bit map
246 			 * (E2/E3A0 only, valid COS values are 0/1)
247 			 */
248 			if (!(INIT_MODE_FLAGS(bp) & MODE_E3_B0)) {
249 				reg_addr = BNX2X_Q_CMDQ_REG_ADDR(pf_q_num);
250 				reg_bit_map = REG_RD(bp, reg_addr);
251 				q_bit_map = 1 << (2 * (pf_q_num & 0xf));
252 				reg_bit_map = new_cos ?
253 					      (reg_bit_map | q_bit_map) :
254 					      (reg_bit_map & (~q_bit_map));
255 				REG_WR(bp, reg_addr, reg_bit_map);
256 			}
257 		}
258 	}
259 }
260 
261 /* Configures the QM according to the specified per-traffic-type COSes */
262 static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode,
263 				       struct priority_cos *traffic_cos)
264 {
265 	bnx2x_map_q_cos(bp, BNX2X_FCOE_Q,
266 			traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
267 	bnx2x_map_q_cos(bp, BNX2X_ISCSI_Q,
268 			traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
269 	bnx2x_map_q_cos(bp, BNX2X_ISCSI_ACK_Q,
270 		traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
271 	if (mode != STATIC_COS) {
272 		/* required only in backward compatible COS mode */
273 		bnx2x_map_q_cos(bp, BNX2X_ETH_Q,
274 				traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
275 		bnx2x_map_q_cos(bp, BNX2X_TOE_Q,
276 				traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
277 		bnx2x_map_q_cos(bp, BNX2X_TOE_ACK_Q,
278 				traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
279 	}
280 }
281 
282 
283 /* congestion management port init api description
284  * the api works as follows:
285  * the driver should pass the cmng_init_input struct, the port_init function
286  * will prepare the required internal ram structure which will be passed back
287  * to the driver (cmng_init) that will write it into the internal ram.
288  *
289  * IMPORTANT REMARKS:
290  * 1. the cmng_init struct does not represent the contiguous internal ram
291  *    structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET
292  *    offset in order to write the port sub struct and the
293  *    PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other
294  *    words - don't use memcpy!).
295  * 2. although the cmng_init struct is filled for the maximal vnic number
296  *    possible, the driver should only write the valid vnics into the internal
297  *    ram according to the appropriate port mode.
298  */
299 #define BITS_TO_BYTES(x) ((x)/8)
300 
301 /* CMNG constants, as derived from system spec calculations */
302 
303 /* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */
304 #define DEF_MIN_RATE 100
305 
306 /* resolution of the rate shaping timer - 400 usec */
307 #define RS_PERIODIC_TIMEOUT_USEC 400
308 
309 /* number of bytes in single QM arbitration cycle -
310  * coefficient for calculating the fairness timer
311  */
312 #define QM_ARB_BYTES 160000
313 
314 /* resolution of Min algorithm 1:100 */
315 #define MIN_RES 100
316 
317 /* how many bytes above threshold for
318  * the minimal credit of Min algorithm
319  */
320 #define MIN_ABOVE_THRESH 32768
321 
322 /* Fairness algorithm integration time coefficient -
323  * for calculating the actual Tfair
324  */
325 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
326 
327 /* Memory of fairness algorithm - 2 cycles */
328 #define FAIR_MEM 2
329 #define SAFC_TIMEOUT_USEC 52
330 
331 #define SDM_TICKS 4
332 
333 
334 static inline void bnx2x_init_max(const struct cmng_init_input *input_data,
335 				  u32 r_param, struct cmng_init *ram_data)
336 {
337 	u32 vnic;
338 	struct cmng_vnic *vdata = &ram_data->vnic;
339 	struct cmng_struct_per_port *pdata = &ram_data->port;
340 	/* rate shaping per-port variables
341 	 * 100 micro seconds in SDM ticks = 25
342 	 * since each tick is 4 microSeconds
343 	 */
344 
345 	pdata->rs_vars.rs_periodic_timeout =
346 	RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;
347 
348 	/* this is the threshold below which no timer arming will occur.
349 	 * 1.25 coefficient is for the threshold to be a little bigger
350 	 * then the real time to compensate for timer in-accuracy
351 	 */
352 	pdata->rs_vars.rs_threshold =
353 	(5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;
354 
355 	/* rate shaping per-vnic variables */
356 	for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
357 		/* global vnic counter */
358 		vdata->vnic_max_rate[vnic].vn_counter.rate =
359 		input_data->vnic_max_rate[vnic];
360 		/* maximal Mbps for this vnic
361 		 * the quota in each timer period - number of bytes
362 		 * transmitted in this period
363 		 */
364 		vdata->vnic_max_rate[vnic].vn_counter.quota =
365 			RS_PERIODIC_TIMEOUT_USEC *
366 			(u32)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;
367 	}
368 
369 }
370 
371 static inline void bnx2x_init_min(const struct cmng_init_input *input_data,
372 				  u32 r_param, struct cmng_init *ram_data)
373 {
374 	u32 vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;
375 	struct cmng_vnic *vdata = &ram_data->vnic;
376 	struct cmng_struct_per_port *pdata = &ram_data->port;
377 
378 	/* this is the resolution of the fairness timer */
379 	fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
380 
381 	/* fairness per-port variables
382 	 * for 10G it is 1000usec. for 1G it is 10000usec.
383 	 */
384 	tFair = T_FAIR_COEF / input_data->port_rate;
385 
386 	/* this is the threshold below which we won't arm the timer anymore */
387 	pdata->fair_vars.fair_threshold = QM_ARB_BYTES;
388 
389 	/* we multiply by 1e3/8 to get bytes/msec. We don't want the credits
390 	 * to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)
391 	 */
392 	pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;
393 
394 	/* since each tick is 4 microSeconds */
395 	pdata->fair_vars.fairness_timeout =
396 				fair_periodic_timeout_usec / SDM_TICKS;
397 
398 	/* calculate sum of weights */
399 	vnicWeightSum = 0;
400 
401 	for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++)
402 		vnicWeightSum += input_data->vnic_min_rate[vnic];
403 
404 	/* global vnic counter */
405 	if (vnicWeightSum > 0) {
406 		/* fairness per-vnic variables */
407 		for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
408 			/* this is the credit for each period of the fairness
409 			 * algorithm - number of bytes in T_FAIR (this vnic
410 			 * share of the port rate)
411 			 */
412 			vdata->vnic_min_rate[vnic].vn_credit_delta =
413 				(u32)input_data->vnic_min_rate[vnic] * 100 *
414 				(T_FAIR_COEF / (8 * 100 * vnicWeightSum));
415 			if (vdata->vnic_min_rate[vnic].vn_credit_delta <
416 			    pdata->fair_vars.fair_threshold +
417 			    MIN_ABOVE_THRESH) {
418 				vdata->vnic_min_rate[vnic].vn_credit_delta =
419 					pdata->fair_vars.fair_threshold +
420 					MIN_ABOVE_THRESH;
421 			}
422 		}
423 	}
424 }
425 
426 static inline void bnx2x_init_fw_wrr(const struct cmng_init_input *input_data,
427 				     u32 r_param, struct cmng_init *ram_data)
428 {
429 	u32 vnic, cos;
430 	u32 cosWeightSum = 0;
431 	struct cmng_vnic *vdata = &ram_data->vnic;
432 	struct cmng_struct_per_port *pdata = &ram_data->port;
433 
434 	for (cos = 0; cos < MAX_COS_NUMBER; cos++)
435 		cosWeightSum += input_data->cos_min_rate[cos];
436 
437 	if (cosWeightSum > 0) {
438 
439 		for (vnic = 0; vnic < BNX2X_PORT2_MODE_NUM_VNICS; vnic++) {
440 			/* Since cos and vnic shouldn't work together the rate
441 			 * to divide between the coses is the port rate.
442 			 */
443 			u32 *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;
444 			for (cos = 0; cos < MAX_COS_NUMBER; cos++) {
445 				/* this is the credit for each period of
446 				 * the fairness algorithm - number of bytes
447 				 * in T_FAIR (this cos share of the vnic rate)
448 				 */
449 				ccd[cos] =
450 				    (u32)input_data->cos_min_rate[cos] * 100 *
451 				    (T_FAIR_COEF / (8 * 100 * cosWeightSum));
452 				if (ccd[cos] < pdata->fair_vars.fair_threshold
453 						+ MIN_ABOVE_THRESH) {
454 					ccd[cos] =
455 					    pdata->fair_vars.fair_threshold +
456 					    MIN_ABOVE_THRESH;
457 				}
458 			}
459 		}
460 	}
461 }
462 
463 static inline void bnx2x_init_safc(const struct cmng_init_input *input_data,
464 				   struct cmng_init *ram_data)
465 {
466 	/* in microSeconds */
467 	ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;
468 }
469 
470 /* Congestion management port init */
471 static inline void bnx2x_init_cmng(const struct cmng_init_input *input_data,
472 				   struct cmng_init *ram_data)
473 {
474 	u32 r_param;
475 	memset(ram_data, 0, sizeof(struct cmng_init));
476 
477 	ram_data->port.flags = input_data->flags;
478 
479 	/* number of bytes transmitted in a rate of 10Gbps
480 	 * in one usec = 1.25KB.
481 	 */
482 	r_param = BITS_TO_BYTES(input_data->port_rate);
483 	bnx2x_init_max(input_data, r_param, ram_data);
484 	bnx2x_init_min(input_data, r_param, ram_data);
485 	bnx2x_init_fw_wrr(input_data, r_param, ram_data);
486 	bnx2x_init_safc(input_data, ram_data);
487 }
488 
489 
490 
491 /* Returns the index of start or end of a specific block stage in ops array */
492 #define BLOCK_OPS_IDX(block, stage, end) \
493 			(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
494 
495 
496 #define INITOP_SET		0	/* set the HW directly */
497 #define INITOP_CLEAR		1	/* clear the HW directly */
498 #define INITOP_INIT		2	/* set the init-value array */
499 
500 /****************************************************************************
501 * ILT management
502 ****************************************************************************/
503 struct ilt_line {
504 	dma_addr_t page_mapping;
505 	void *page;
506 	u32 size;
507 };
508 
509 struct ilt_client_info {
510 	u32 page_size;
511 	u16 start;
512 	u16 end;
513 	u16 client_num;
514 	u16 flags;
515 #define ILT_CLIENT_SKIP_INIT	0x1
516 #define ILT_CLIENT_SKIP_MEM	0x2
517 };
518 
519 struct bnx2x_ilt {
520 	u32 start_line;
521 	struct ilt_line		*lines;
522 	struct ilt_client_info	clients[4];
523 #define ILT_CLIENT_CDU	0
524 #define ILT_CLIENT_QM	1
525 #define ILT_CLIENT_SRC	2
526 #define ILT_CLIENT_TM	3
527 };
528 
529 /****************************************************************************
530 * SRC configuration
531 ****************************************************************************/
532 struct src_ent {
533 	u8 opaque[56];
534 	u64 next;
535 };
536 
537 /****************************************************************************
538 * Parity configuration
539 ****************************************************************************/
540 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \
541 { \
542 	block##_REG_##block##_PRTY_MASK, \
543 	block##_REG_##block##_PRTY_STS_CLR, \
544 	en_mask, {m1, m1h, m2, m3}, #block \
545 }
546 
547 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \
548 { \
549 	block##_REG_##block##_PRTY_MASK_0, \
550 	block##_REG_##block##_PRTY_STS_CLR_0, \
551 	en_mask, {m1, m1h, m2, m3}, #block"_0" \
552 }
553 
554 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \
555 { \
556 	block##_REG_##block##_PRTY_MASK_1, \
557 	block##_REG_##block##_PRTY_STS_CLR_1, \
558 	en_mask, {m1, m1h, m2, m3}, #block"_1" \
559 }
560 
561 static const struct {
562 	u32 mask_addr;
563 	u32 sts_clr_addr;
564 	u32 en_mask;		/* Mask to enable parity attentions */
565 	struct {
566 		u32 e1;		/* 57710 */
567 		u32 e1h;	/* 57711 */
568 		u32 e2;		/* 57712 */
569 		u32 e3;		/* 578xx */
570 	} reg_mask;		/* Register mask (all valid bits) */
571 	char name[8];		/* Block's longest name is 7 characters long
572 				 * (name + suffix)
573 				 */
574 } bnx2x_blocks_parity_data[] = {
575 	/* bit 19 masked */
576 	/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
577 	/* bit 5,18,20-31 */
578 	/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
579 	/* bit 5 */
580 	/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20);	*/
581 	/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
582 	/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
583 
584 	/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
585 	 * want to handle "system kill" flow at the moment.
586 	 */
587 	BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
588 			0x7ffffff),
589 	BLOCK_PRTY_INFO_0(PXP2,	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
590 			  0xffffffff),
591 	BLOCK_PRTY_INFO_1(PXP2,	0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
592 	BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
593 	BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
594 	BLOCK_PRTY_INFO_0(NIG,	0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
595 	BLOCK_PRTY_INFO_1(NIG,	0xffff, 0, 0, 0xff, 0xffff),
596 	BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
597 	BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
598 	BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
599 	BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
600 	BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
601 	BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
602 	{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
603 		GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
604 		{0xf, 0xf, 0xf, 0xf}, "UPB"},
605 	{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
606 		GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
607 		{0xf, 0xf, 0xf, 0xf}, "XPB"},
608 	BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
609 	BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
610 	BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
611 	BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
612 	BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
613 	BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
614 	BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
615 	BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
616 	BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
617 	BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
618 	BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
619 	BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
620 	BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
621 	BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
622 	BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
623 	BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
624 	BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
625 	BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
626 			  0xffffffff),
627 	BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
628 	BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
629 			  0xffffffff),
630 	BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
631 	BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
632 			  0xffffffff),
633 	BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
634 	BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
635 			  0xffffffff),
636 	BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
637 };
638 
639 
640 /* [28] MCP Latched rom_parity
641  * [29] MCP Latched ump_rx_parity
642  * [30] MCP Latched ump_tx_parity
643  * [31] MCP Latched scpad_parity
644  */
645 #define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS	\
646 	(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
647 	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
648 	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
649 
650 #define MISC_AEU_ENABLE_MCP_PRTY_BITS	\
651 	(MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
652 	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
653 
654 /* Below registers control the MCP parity attention output. When
655  * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
656  * enabled, when cleared - disabled.
657  */
658 static const struct {
659 	u32 addr;
660 	u32 bits;
661 } mcp_attn_ctl_regs[] = {
662 	{ MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
663 		MISC_AEU_ENABLE_MCP_PRTY_BITS },
664 	{ MISC_REG_AEU_ENABLE4_NIG_0,
665 		MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
666 	{ MISC_REG_AEU_ENABLE4_PXP_0,
667 		MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
668 	{ MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
669 		MISC_AEU_ENABLE_MCP_PRTY_BITS },
670 	{ MISC_REG_AEU_ENABLE4_NIG_1,
671 		MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
672 	{ MISC_REG_AEU_ENABLE4_PXP_1,
673 		MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
674 };
675 
676 static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
677 {
678 	int i;
679 	u32 reg_val;
680 
681 	for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
682 		reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);
683 
684 		if (enable)
685 			reg_val |= mcp_attn_ctl_regs[i].bits;
686 		else
687 			reg_val &= ~mcp_attn_ctl_regs[i].bits;
688 
689 		REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);
690 	}
691 }
692 
693 static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
694 {
695 	if (CHIP_IS_E1(bp))
696 		return bnx2x_blocks_parity_data[idx].reg_mask.e1;
697 	else if (CHIP_IS_E1H(bp))
698 		return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
699 	else if (CHIP_IS_E2(bp))
700 		return bnx2x_blocks_parity_data[idx].reg_mask.e2;
701 	else /* CHIP_IS_E3 */
702 		return bnx2x_blocks_parity_data[idx].reg_mask.e3;
703 }
704 
705 static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
706 {
707 	int i;
708 
709 	for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
710 		u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
711 
712 		if (dis_mask) {
713 			REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
714 			       dis_mask);
715 			DP(NETIF_MSG_HW, "Setting parity mask "
716 						 "for %s to\t\t0x%x\n",
717 				    bnx2x_blocks_parity_data[i].name, dis_mask);
718 		}
719 	}
720 
721 	/* Disable MCP parity attentions */
722 	bnx2x_set_mcp_parity(bp, false);
723 }
724 
725 /* Clear the parity error status registers. */
726 static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
727 {
728 	int i;
729 	u32 reg_val, mcp_aeu_bits =
730 		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
731 		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
732 		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
733 		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
734 
735 	/* Clear SEM_FAST parities */
736 	REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
737 	REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
738 	REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
739 	REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
740 
741 	for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
742 		u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
743 
744 		if (reg_mask) {
745 			reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
746 					 sts_clr_addr);
747 			if (reg_val & reg_mask)
748 				DP(NETIF_MSG_HW,
749 					    "Parity errors in %s: 0x%x\n",
750 					    bnx2x_blocks_parity_data[i].name,
751 					    reg_val & reg_mask);
752 		}
753 	}
754 
755 	/* Check if there were parity attentions in MCP */
756 	reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
757 	if (reg_val & mcp_aeu_bits)
758 		DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
759 		   reg_val & mcp_aeu_bits);
760 
761 	/* Clear parity attentions in MCP:
762 	 * [7]  clears Latched rom_parity
763 	 * [8]  clears Latched ump_rx_parity
764 	 * [9]  clears Latched ump_tx_parity
765 	 * [10] clears Latched scpad_parity (both ports)
766 	 */
767 	REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
768 }
769 
770 static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
771 {
772 	int i;
773 
774 	for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
775 		u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
776 
777 		if (reg_mask)
778 			REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
779 				bnx2x_blocks_parity_data[i].en_mask & reg_mask);
780 	}
781 
782 	/* Enable MCP parity attentions */
783 	bnx2x_set_mcp_parity(bp, true);
784 }
785 
786 
787 #endif /* BNX2X_INIT_H */
788 
789