1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #include <linux/bitops.h> 12 #include <linux/ctype.h> 13 #include <linux/stringify.h> 14 #include <linux/ethtool.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/linkmode.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/etherdevice.h> 20 #include <linux/crc32.h> 21 #include <linux/firmware.h> 22 #include <linux/utsname.h> 23 #include <linux/time.h> 24 #include <linux/ptp_clock_kernel.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/timecounter.h> 27 #include <net/netlink.h> 28 #include "bnxt_hsi.h" 29 #include "bnxt.h" 30 #include "bnxt_hwrm.h" 31 #include "bnxt_ulp.h" 32 #include "bnxt_xdp.h" 33 #include "bnxt_ptp.h" 34 #include "bnxt_ethtool.h" 35 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */ 36 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */ 37 #include "bnxt_coredump.h" 38 39 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \ 40 do { \ 41 if (extack) \ 42 NL_SET_ERR_MSG_MOD(extack, msg); \ 43 netdev_err(dev, "%s\n", msg); \ 44 } while (0) 45 46 static u32 bnxt_get_msglevel(struct net_device *dev) 47 { 48 struct bnxt *bp = netdev_priv(dev); 49 50 return bp->msg_enable; 51 } 52 53 static void bnxt_set_msglevel(struct net_device *dev, u32 value) 54 { 55 struct bnxt *bp = netdev_priv(dev); 56 57 bp->msg_enable = value; 58 } 59 60 static int bnxt_get_coalesce(struct net_device *dev, 61 struct ethtool_coalesce *coal, 62 struct kernel_ethtool_coalesce *kernel_coal, 63 struct netlink_ext_ack *extack) 64 { 65 struct bnxt *bp = netdev_priv(dev); 66 struct bnxt_coal *hw_coal; 67 u16 mult; 68 69 memset(coal, 0, sizeof(*coal)); 70 71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM; 72 73 hw_coal = &bp->rx_coal; 74 mult = hw_coal->bufs_per_record; 75 coal->rx_coalesce_usecs = hw_coal->coal_ticks; 76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult; 77 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 78 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 79 if (hw_coal->flags & 80 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 81 kernel_coal->use_cqe_mode_rx = true; 82 83 hw_coal = &bp->tx_coal; 84 mult = hw_coal->bufs_per_record; 85 coal->tx_coalesce_usecs = hw_coal->coal_ticks; 86 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult; 87 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq; 88 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult; 89 if (hw_coal->flags & 90 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET) 91 kernel_coal->use_cqe_mode_tx = true; 92 93 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks; 94 95 return 0; 96 } 97 98 static int bnxt_set_coalesce(struct net_device *dev, 99 struct ethtool_coalesce *coal, 100 struct kernel_ethtool_coalesce *kernel_coal, 101 struct netlink_ext_ack *extack) 102 { 103 struct bnxt *bp = netdev_priv(dev); 104 bool update_stats = false; 105 struct bnxt_coal *hw_coal; 106 int rc = 0; 107 u16 mult; 108 109 if (coal->use_adaptive_rx_coalesce) { 110 bp->flags |= BNXT_FLAG_DIM; 111 } else { 112 if (bp->flags & BNXT_FLAG_DIM) { 113 bp->flags &= ~(BNXT_FLAG_DIM); 114 goto reset_coalesce; 115 } 116 } 117 118 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 119 !(bp->coal_cap.cmpl_params & 120 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)) 121 return -EOPNOTSUPP; 122 123 hw_coal = &bp->rx_coal; 124 mult = hw_coal->bufs_per_record; 125 hw_coal->coal_ticks = coal->rx_coalesce_usecs; 126 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult; 127 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq; 128 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult; 129 hw_coal->flags &= 130 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 131 if (kernel_coal->use_cqe_mode_rx) 132 hw_coal->flags |= 133 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 134 135 hw_coal = &bp->tx_coal; 136 mult = hw_coal->bufs_per_record; 137 hw_coal->coal_ticks = coal->tx_coalesce_usecs; 138 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult; 139 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq; 140 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult; 141 hw_coal->flags &= 142 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 143 if (kernel_coal->use_cqe_mode_tx) 144 hw_coal->flags |= 145 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; 146 147 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) { 148 u32 stats_ticks = coal->stats_block_coalesce_usecs; 149 150 /* Allow 0, which means disable. */ 151 if (stats_ticks) 152 stats_ticks = clamp_t(u32, stats_ticks, 153 BNXT_MIN_STATS_COAL_TICKS, 154 BNXT_MAX_STATS_COAL_TICKS); 155 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS); 156 bp->stats_coal_ticks = stats_ticks; 157 if (bp->stats_coal_ticks) 158 bp->current_interval = 159 bp->stats_coal_ticks * HZ / 1000000; 160 else 161 bp->current_interval = BNXT_TIMER_INTERVAL; 162 update_stats = true; 163 } 164 165 reset_coalesce: 166 if (test_bit(BNXT_STATE_OPEN, &bp->state)) { 167 if (update_stats) { 168 rc = bnxt_close_nic(bp, true, false); 169 if (!rc) 170 rc = bnxt_open_nic(bp, true, false); 171 } else { 172 rc = bnxt_hwrm_set_coal(bp); 173 } 174 } 175 176 return rc; 177 } 178 179 static const char * const bnxt_ring_rx_stats_str[] = { 180 "rx_ucast_packets", 181 "rx_mcast_packets", 182 "rx_bcast_packets", 183 "rx_discards", 184 "rx_errors", 185 "rx_ucast_bytes", 186 "rx_mcast_bytes", 187 "rx_bcast_bytes", 188 }; 189 190 static const char * const bnxt_ring_tx_stats_str[] = { 191 "tx_ucast_packets", 192 "tx_mcast_packets", 193 "tx_bcast_packets", 194 "tx_errors", 195 "tx_discards", 196 "tx_ucast_bytes", 197 "tx_mcast_bytes", 198 "tx_bcast_bytes", 199 }; 200 201 static const char * const bnxt_ring_tpa_stats_str[] = { 202 "tpa_packets", 203 "tpa_bytes", 204 "tpa_events", 205 "tpa_aborts", 206 }; 207 208 static const char * const bnxt_ring_tpa2_stats_str[] = { 209 "rx_tpa_eligible_pkt", 210 "rx_tpa_eligible_bytes", 211 "rx_tpa_pkt", 212 "rx_tpa_bytes", 213 "rx_tpa_errors", 214 "rx_tpa_events", 215 }; 216 217 static const char * const bnxt_rx_sw_stats_str[] = { 218 "rx_l4_csum_errors", 219 "rx_resets", 220 "rx_buf_errors", 221 }; 222 223 static const char * const bnxt_cmn_sw_stats_str[] = { 224 "missed_irqs", 225 }; 226 227 #define BNXT_RX_STATS_ENTRY(counter) \ 228 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) } 229 230 #define BNXT_TX_STATS_ENTRY(counter) \ 231 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) } 232 233 #define BNXT_RX_STATS_EXT_ENTRY(counter) \ 234 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) } 235 236 #define BNXT_TX_STATS_EXT_ENTRY(counter) \ 237 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) } 238 239 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \ 240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \ 241 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions) 242 243 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \ 244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \ 245 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions) 246 247 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \ 248 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \ 249 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \ 250 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \ 251 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \ 252 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \ 253 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \ 254 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \ 255 BNXT_RX_STATS_EXT_PFC_ENTRY(7) 256 257 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \ 258 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \ 259 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \ 260 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \ 261 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \ 262 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \ 263 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \ 264 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \ 265 BNXT_TX_STATS_EXT_PFC_ENTRY(7) 266 267 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \ 268 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \ 269 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n) 270 271 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \ 272 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \ 273 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n) 274 275 #define BNXT_RX_STATS_EXT_COS_ENTRIES \ 276 BNXT_RX_STATS_EXT_COS_ENTRY(0), \ 277 BNXT_RX_STATS_EXT_COS_ENTRY(1), \ 278 BNXT_RX_STATS_EXT_COS_ENTRY(2), \ 279 BNXT_RX_STATS_EXT_COS_ENTRY(3), \ 280 BNXT_RX_STATS_EXT_COS_ENTRY(4), \ 281 BNXT_RX_STATS_EXT_COS_ENTRY(5), \ 282 BNXT_RX_STATS_EXT_COS_ENTRY(6), \ 283 BNXT_RX_STATS_EXT_COS_ENTRY(7) \ 284 285 #define BNXT_TX_STATS_EXT_COS_ENTRIES \ 286 BNXT_TX_STATS_EXT_COS_ENTRY(0), \ 287 BNXT_TX_STATS_EXT_COS_ENTRY(1), \ 288 BNXT_TX_STATS_EXT_COS_ENTRY(2), \ 289 BNXT_TX_STATS_EXT_COS_ENTRY(3), \ 290 BNXT_TX_STATS_EXT_COS_ENTRY(4), \ 291 BNXT_TX_STATS_EXT_COS_ENTRY(5), \ 292 BNXT_TX_STATS_EXT_COS_ENTRY(6), \ 293 BNXT_TX_STATS_EXT_COS_ENTRY(7) \ 294 295 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \ 296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \ 297 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n) 298 299 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \ 300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \ 301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \ 302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \ 303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \ 304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \ 305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \ 306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \ 307 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7) 308 309 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \ 310 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \ 311 __stringify(counter##_pri##n) } 312 313 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \ 314 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \ 315 __stringify(counter##_pri##n) } 316 317 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \ 318 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \ 319 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \ 320 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \ 321 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \ 322 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \ 323 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \ 324 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \ 325 BNXT_RX_STATS_PRI_ENTRY(counter, 7) 326 327 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \ 328 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \ 329 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \ 330 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \ 331 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \ 332 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \ 333 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \ 334 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \ 335 BNXT_TX_STATS_PRI_ENTRY(counter, 7) 336 337 enum { 338 RX_TOTAL_DISCARDS, 339 TX_TOTAL_DISCARDS, 340 RX_NETPOLL_DISCARDS, 341 }; 342 343 static const char *const bnxt_ring_err_stats_arr[] = { 344 "rx_total_l4_csum_errors", 345 "rx_total_resets", 346 "rx_total_buf_errors", 347 "rx_total_oom_discards", 348 "rx_total_netpoll_discards", 349 "rx_total_ring_discards", 350 "tx_total_resets", 351 "tx_total_ring_discards", 352 "total_missed_irqs", 353 }; 354 355 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str) 356 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str) 357 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str) 358 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str) 359 360 static const struct { 361 long offset; 362 char string[ETH_GSTRING_LEN]; 363 } bnxt_port_stats_arr[] = { 364 BNXT_RX_STATS_ENTRY(rx_64b_frames), 365 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames), 366 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames), 367 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames), 368 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames), 369 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames), 370 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames), 371 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames), 372 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames), 373 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames), 374 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames), 375 BNXT_RX_STATS_ENTRY(rx_total_frames), 376 BNXT_RX_STATS_ENTRY(rx_ucast_frames), 377 BNXT_RX_STATS_ENTRY(rx_mcast_frames), 378 BNXT_RX_STATS_ENTRY(rx_bcast_frames), 379 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames), 380 BNXT_RX_STATS_ENTRY(rx_ctrl_frames), 381 BNXT_RX_STATS_ENTRY(rx_pause_frames), 382 BNXT_RX_STATS_ENTRY(rx_pfc_frames), 383 BNXT_RX_STATS_ENTRY(rx_align_err_frames), 384 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames), 385 BNXT_RX_STATS_ENTRY(rx_jbr_frames), 386 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames), 387 BNXT_RX_STATS_ENTRY(rx_tagged_frames), 388 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames), 389 BNXT_RX_STATS_ENTRY(rx_good_frames), 390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0), 391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1), 392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2), 393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3), 394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4), 395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5), 396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6), 397 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7), 398 BNXT_RX_STATS_ENTRY(rx_undrsz_frames), 399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events), 400 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration), 401 BNXT_RX_STATS_ENTRY(rx_bytes), 402 BNXT_RX_STATS_ENTRY(rx_runt_bytes), 403 BNXT_RX_STATS_ENTRY(rx_runt_frames), 404 BNXT_RX_STATS_ENTRY(rx_stat_discard), 405 BNXT_RX_STATS_ENTRY(rx_stat_err), 406 407 BNXT_TX_STATS_ENTRY(tx_64b_frames), 408 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames), 409 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames), 410 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames), 411 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames), 412 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames), 413 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames), 414 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames), 415 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames), 416 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames), 417 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames), 418 BNXT_TX_STATS_ENTRY(tx_good_frames), 419 BNXT_TX_STATS_ENTRY(tx_total_frames), 420 BNXT_TX_STATS_ENTRY(tx_ucast_frames), 421 BNXT_TX_STATS_ENTRY(tx_mcast_frames), 422 BNXT_TX_STATS_ENTRY(tx_bcast_frames), 423 BNXT_TX_STATS_ENTRY(tx_pause_frames), 424 BNXT_TX_STATS_ENTRY(tx_pfc_frames), 425 BNXT_TX_STATS_ENTRY(tx_jabber_frames), 426 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames), 427 BNXT_TX_STATS_ENTRY(tx_err), 428 BNXT_TX_STATS_ENTRY(tx_fifo_underruns), 429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0), 430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1), 431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2), 432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3), 433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4), 434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5), 435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6), 436 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7), 437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events), 438 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration), 439 BNXT_TX_STATS_ENTRY(tx_total_collisions), 440 BNXT_TX_STATS_ENTRY(tx_bytes), 441 BNXT_TX_STATS_ENTRY(tx_xthol_frames), 442 BNXT_TX_STATS_ENTRY(tx_stat_discard), 443 BNXT_TX_STATS_ENTRY(tx_stat_error), 444 }; 445 446 static const struct { 447 long offset; 448 char string[ETH_GSTRING_LEN]; 449 } bnxt_port_stats_ext_arr[] = { 450 BNXT_RX_STATS_EXT_ENTRY(link_down_events), 451 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events), 452 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events), 453 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events), 454 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events), 455 BNXT_RX_STATS_EXT_COS_ENTRIES, 456 BNXT_RX_STATS_EXT_PFC_ENTRIES, 457 BNXT_RX_STATS_EXT_ENTRY(rx_bits), 458 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold), 459 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err), 460 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits), 461 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES, 462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks), 463 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks), 464 }; 465 466 static const struct { 467 long offset; 468 char string[ETH_GSTRING_LEN]; 469 } bnxt_tx_port_stats_ext_arr[] = { 470 BNXT_TX_STATS_EXT_COS_ENTRIES, 471 BNXT_TX_STATS_EXT_PFC_ENTRIES, 472 }; 473 474 static const struct { 475 long base_off; 476 char string[ETH_GSTRING_LEN]; 477 } bnxt_rx_bytes_pri_arr[] = { 478 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes), 479 }; 480 481 static const struct { 482 long base_off; 483 char string[ETH_GSTRING_LEN]; 484 } bnxt_rx_pkts_pri_arr[] = { 485 BNXT_RX_STATS_PRI_ENTRIES(rx_packets), 486 }; 487 488 static const struct { 489 long base_off; 490 char string[ETH_GSTRING_LEN]; 491 } bnxt_tx_bytes_pri_arr[] = { 492 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes), 493 }; 494 495 static const struct { 496 long base_off; 497 char string[ETH_GSTRING_LEN]; 498 } bnxt_tx_pkts_pri_arr[] = { 499 BNXT_TX_STATS_PRI_ENTRIES(tx_packets), 500 }; 501 502 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr) 503 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr) 504 #define BNXT_NUM_STATS_PRI \ 505 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \ 506 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \ 507 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \ 508 ARRAY_SIZE(bnxt_tx_pkts_pri_arr)) 509 510 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp) 511 { 512 if (BNXT_SUPPORTS_TPA(bp)) { 513 if (bp->max_tpa_v2) { 514 if (BNXT_CHIP_P5_THOR(bp)) 515 return BNXT_NUM_TPA_RING_STATS_P5; 516 return BNXT_NUM_TPA_RING_STATS_P5_SR2; 517 } 518 return BNXT_NUM_TPA_RING_STATS; 519 } 520 return 0; 521 } 522 523 static int bnxt_get_num_ring_stats(struct bnxt *bp) 524 { 525 int rx, tx, cmn; 526 527 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS + 528 bnxt_get_num_tpa_ring_stats(bp); 529 tx = NUM_RING_TX_HW_STATS; 530 cmn = NUM_RING_CMN_SW_STATS; 531 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings + 532 cmn * bp->cp_nr_rings; 533 } 534 535 static int bnxt_get_num_stats(struct bnxt *bp) 536 { 537 int num_stats = bnxt_get_num_ring_stats(bp); 538 int len; 539 540 num_stats += BNXT_NUM_RING_ERR_STATS; 541 542 if (bp->flags & BNXT_FLAG_PORT_STATS) 543 num_stats += BNXT_NUM_PORT_STATS; 544 545 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 546 len = min_t(int, bp->fw_rx_stats_ext_size, 547 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 548 num_stats += len; 549 len = min_t(int, bp->fw_tx_stats_ext_size, 550 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 551 num_stats += len; 552 if (bp->pri2cos_valid) 553 num_stats += BNXT_NUM_STATS_PRI; 554 } 555 556 return num_stats; 557 } 558 559 static int bnxt_get_sset_count(struct net_device *dev, int sset) 560 { 561 struct bnxt *bp = netdev_priv(dev); 562 563 switch (sset) { 564 case ETH_SS_STATS: 565 return bnxt_get_num_stats(bp); 566 case ETH_SS_TEST: 567 if (!bp->num_tests) 568 return -EOPNOTSUPP; 569 return bp->num_tests; 570 default: 571 return -EOPNOTSUPP; 572 } 573 } 574 575 static bool is_rx_ring(struct bnxt *bp, int ring_num) 576 { 577 return ring_num < bp->rx_nr_rings; 578 } 579 580 static bool is_tx_ring(struct bnxt *bp, int ring_num) 581 { 582 int tx_base = 0; 583 584 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) 585 tx_base = bp->rx_nr_rings; 586 587 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings)) 588 return true; 589 return false; 590 } 591 592 static void bnxt_get_ethtool_stats(struct net_device *dev, 593 struct ethtool_stats *stats, u64 *buf) 594 { 595 struct bnxt_total_ring_err_stats ring_err_stats = {0}; 596 struct bnxt *bp = netdev_priv(dev); 597 u64 *curr, *prev; 598 u32 tpa_stats; 599 u32 i, j = 0; 600 601 if (!bp->bnapi) { 602 j += bnxt_get_num_ring_stats(bp); 603 goto skip_ring_stats; 604 } 605 606 tpa_stats = bnxt_get_num_tpa_ring_stats(bp); 607 for (i = 0; i < bp->cp_nr_rings; i++) { 608 struct bnxt_napi *bnapi = bp->bnapi[i]; 609 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 610 u64 *sw_stats = cpr->stats.sw_stats; 611 u64 *sw; 612 int k; 613 614 if (is_rx_ring(bp, i)) { 615 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++) 616 buf[j] = sw_stats[k]; 617 } 618 if (is_tx_ring(bp, i)) { 619 k = NUM_RING_RX_HW_STATS; 620 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 621 j++, k++) 622 buf[j] = sw_stats[k]; 623 } 624 if (!tpa_stats || !is_rx_ring(bp, i)) 625 goto skip_tpa_ring_stats; 626 627 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS; 628 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS + 629 tpa_stats; j++, k++) 630 buf[j] = sw_stats[k]; 631 632 skip_tpa_ring_stats: 633 sw = (u64 *)&cpr->sw_stats.rx; 634 if (is_rx_ring(bp, i)) { 635 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++) 636 buf[j] = sw[k]; 637 } 638 639 sw = (u64 *)&cpr->sw_stats.cmn; 640 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++) 641 buf[j] = sw[k]; 642 } 643 644 bnxt_get_ring_err_stats(bp, &ring_err_stats); 645 646 skip_ring_stats: 647 curr = &ring_err_stats.rx_total_l4_csum_errors; 648 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors; 649 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++) 650 buf[j] = *curr + *prev; 651 652 if (bp->flags & BNXT_FLAG_PORT_STATS) { 653 u64 *port_stats = bp->port_stats.sw_stats; 654 655 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) 656 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset); 657 } 658 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 659 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats; 660 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats; 661 u32 len; 662 663 len = min_t(u32, bp->fw_rx_stats_ext_size, 664 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 665 for (i = 0; i < len; i++, j++) { 666 buf[j] = *(rx_port_stats_ext + 667 bnxt_port_stats_ext_arr[i].offset); 668 } 669 len = min_t(u32, bp->fw_tx_stats_ext_size, 670 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 671 for (i = 0; i < len; i++, j++) { 672 buf[j] = *(tx_port_stats_ext + 673 bnxt_tx_port_stats_ext_arr[i].offset); 674 } 675 if (bp->pri2cos_valid) { 676 for (i = 0; i < 8; i++, j++) { 677 long n = bnxt_rx_bytes_pri_arr[i].base_off + 678 bp->pri2cos_idx[i]; 679 680 buf[j] = *(rx_port_stats_ext + n); 681 } 682 for (i = 0; i < 8; i++, j++) { 683 long n = bnxt_rx_pkts_pri_arr[i].base_off + 684 bp->pri2cos_idx[i]; 685 686 buf[j] = *(rx_port_stats_ext + n); 687 } 688 for (i = 0; i < 8; i++, j++) { 689 long n = bnxt_tx_bytes_pri_arr[i].base_off + 690 bp->pri2cos_idx[i]; 691 692 buf[j] = *(tx_port_stats_ext + n); 693 } 694 for (i = 0; i < 8; i++, j++) { 695 long n = bnxt_tx_pkts_pri_arr[i].base_off + 696 bp->pri2cos_idx[i]; 697 698 buf[j] = *(tx_port_stats_ext + n); 699 } 700 } 701 } 702 } 703 704 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 705 { 706 struct bnxt *bp = netdev_priv(dev); 707 static const char * const *str; 708 u32 i, j, num_str; 709 710 switch (stringset) { 711 case ETH_SS_STATS: 712 for (i = 0; i < bp->cp_nr_rings; i++) { 713 if (is_rx_ring(bp, i)) { 714 num_str = NUM_RING_RX_HW_STATS; 715 for (j = 0; j < num_str; j++) { 716 sprintf(buf, "[%d]: %s", i, 717 bnxt_ring_rx_stats_str[j]); 718 buf += ETH_GSTRING_LEN; 719 } 720 } 721 if (is_tx_ring(bp, i)) { 722 num_str = NUM_RING_TX_HW_STATS; 723 for (j = 0; j < num_str; j++) { 724 sprintf(buf, "[%d]: %s", i, 725 bnxt_ring_tx_stats_str[j]); 726 buf += ETH_GSTRING_LEN; 727 } 728 } 729 num_str = bnxt_get_num_tpa_ring_stats(bp); 730 if (!num_str || !is_rx_ring(bp, i)) 731 goto skip_tpa_stats; 732 733 if (bp->max_tpa_v2) 734 str = bnxt_ring_tpa2_stats_str; 735 else 736 str = bnxt_ring_tpa_stats_str; 737 738 for (j = 0; j < num_str; j++) { 739 sprintf(buf, "[%d]: %s", i, str[j]); 740 buf += ETH_GSTRING_LEN; 741 } 742 skip_tpa_stats: 743 if (is_rx_ring(bp, i)) { 744 num_str = NUM_RING_RX_SW_STATS; 745 for (j = 0; j < num_str; j++) { 746 sprintf(buf, "[%d]: %s", i, 747 bnxt_rx_sw_stats_str[j]); 748 buf += ETH_GSTRING_LEN; 749 } 750 } 751 num_str = NUM_RING_CMN_SW_STATS; 752 for (j = 0; j < num_str; j++) { 753 sprintf(buf, "[%d]: %s", i, 754 bnxt_cmn_sw_stats_str[j]); 755 buf += ETH_GSTRING_LEN; 756 } 757 } 758 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) { 759 strscpy(buf, bnxt_ring_err_stats_arr[i], ETH_GSTRING_LEN); 760 buf += ETH_GSTRING_LEN; 761 } 762 763 if (bp->flags & BNXT_FLAG_PORT_STATS) { 764 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) { 765 strcpy(buf, bnxt_port_stats_arr[i].string); 766 buf += ETH_GSTRING_LEN; 767 } 768 } 769 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) { 770 u32 len; 771 772 len = min_t(u32, bp->fw_rx_stats_ext_size, 773 ARRAY_SIZE(bnxt_port_stats_ext_arr)); 774 for (i = 0; i < len; i++) { 775 strcpy(buf, bnxt_port_stats_ext_arr[i].string); 776 buf += ETH_GSTRING_LEN; 777 } 778 len = min_t(u32, bp->fw_tx_stats_ext_size, 779 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr)); 780 for (i = 0; i < len; i++) { 781 strcpy(buf, 782 bnxt_tx_port_stats_ext_arr[i].string); 783 buf += ETH_GSTRING_LEN; 784 } 785 if (bp->pri2cos_valid) { 786 for (i = 0; i < 8; i++) { 787 strcpy(buf, 788 bnxt_rx_bytes_pri_arr[i].string); 789 buf += ETH_GSTRING_LEN; 790 } 791 for (i = 0; i < 8; i++) { 792 strcpy(buf, 793 bnxt_rx_pkts_pri_arr[i].string); 794 buf += ETH_GSTRING_LEN; 795 } 796 for (i = 0; i < 8; i++) { 797 strcpy(buf, 798 bnxt_tx_bytes_pri_arr[i].string); 799 buf += ETH_GSTRING_LEN; 800 } 801 for (i = 0; i < 8; i++) { 802 strcpy(buf, 803 bnxt_tx_pkts_pri_arr[i].string); 804 buf += ETH_GSTRING_LEN; 805 } 806 } 807 } 808 break; 809 case ETH_SS_TEST: 810 if (bp->num_tests) 811 memcpy(buf, bp->test_info->string, 812 bp->num_tests * ETH_GSTRING_LEN); 813 break; 814 default: 815 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n", 816 stringset); 817 break; 818 } 819 } 820 821 static void bnxt_get_ringparam(struct net_device *dev, 822 struct ethtool_ringparam *ering, 823 struct kernel_ethtool_ringparam *kernel_ering, 824 struct netlink_ext_ack *extack) 825 { 826 struct bnxt *bp = netdev_priv(dev); 827 828 if (bp->flags & BNXT_FLAG_AGG_RINGS) { 829 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA; 830 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT; 831 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED; 832 } else { 833 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT; 834 ering->rx_jumbo_max_pending = 0; 835 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED; 836 } 837 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT; 838 839 ering->rx_pending = bp->rx_ring_size; 840 ering->rx_jumbo_pending = bp->rx_agg_ring_size; 841 ering->tx_pending = bp->tx_ring_size; 842 } 843 844 static int bnxt_set_ringparam(struct net_device *dev, 845 struct ethtool_ringparam *ering, 846 struct kernel_ethtool_ringparam *kernel_ering, 847 struct netlink_ext_ack *extack) 848 { 849 struct bnxt *bp = netdev_priv(dev); 850 851 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) || 852 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) || 853 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT)) 854 return -EINVAL; 855 856 if (netif_running(dev)) 857 bnxt_close_nic(bp, false, false); 858 859 bp->rx_ring_size = ering->rx_pending; 860 bp->tx_ring_size = ering->tx_pending; 861 bnxt_set_ring_params(bp); 862 863 if (netif_running(dev)) 864 return bnxt_open_nic(bp, false, false); 865 866 return 0; 867 } 868 869 static void bnxt_get_channels(struct net_device *dev, 870 struct ethtool_channels *channel) 871 { 872 struct bnxt *bp = netdev_priv(dev); 873 struct bnxt_hw_resc *hw_resc = &bp->hw_resc; 874 int max_rx_rings, max_tx_rings, tcs; 875 int max_tx_sch_inputs, tx_grps; 876 877 /* Get the most up-to-date max_tx_sch_inputs. */ 878 if (netif_running(dev) && BNXT_NEW_RM(bp)) 879 bnxt_hwrm_func_resc_qcaps(bp, false); 880 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs; 881 882 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true); 883 if (max_tx_sch_inputs) 884 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 885 886 tcs = netdev_get_num_tc(dev); 887 tx_grps = max(tcs, 1); 888 if (bp->tx_nr_rings_xdp) 889 tx_grps++; 890 max_tx_rings /= tx_grps; 891 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings); 892 893 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) { 894 max_rx_rings = 0; 895 max_tx_rings = 0; 896 } 897 if (max_tx_sch_inputs) 898 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs); 899 900 if (tcs > 1) 901 max_tx_rings /= tcs; 902 903 channel->max_rx = max_rx_rings; 904 channel->max_tx = max_tx_rings; 905 channel->max_other = 0; 906 if (bp->flags & BNXT_FLAG_SHARED_RINGS) { 907 channel->combined_count = bp->rx_nr_rings; 908 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) 909 channel->combined_count--; 910 } else { 911 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) { 912 channel->rx_count = bp->rx_nr_rings; 913 channel->tx_count = bp->tx_nr_rings_per_tc; 914 } 915 } 916 } 917 918 static int bnxt_set_channels(struct net_device *dev, 919 struct ethtool_channels *channel) 920 { 921 struct bnxt *bp = netdev_priv(dev); 922 int req_tx_rings, req_rx_rings, tcs; 923 bool sh = false; 924 int tx_xdp = 0; 925 int rc = 0; 926 927 if (channel->other_count) 928 return -EINVAL; 929 930 if (!channel->combined_count && 931 (!channel->rx_count || !channel->tx_count)) 932 return -EINVAL; 933 934 if (channel->combined_count && 935 (channel->rx_count || channel->tx_count)) 936 return -EINVAL; 937 938 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count || 939 channel->tx_count)) 940 return -EINVAL; 941 942 if (channel->combined_count) 943 sh = true; 944 945 tcs = netdev_get_num_tc(dev); 946 947 req_tx_rings = sh ? channel->combined_count : channel->tx_count; 948 req_rx_rings = sh ? channel->combined_count : channel->rx_count; 949 if (bp->tx_nr_rings_xdp) { 950 if (!sh) { 951 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n"); 952 return -EINVAL; 953 } 954 tx_xdp = req_rx_rings; 955 } 956 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp); 957 if (rc) { 958 netdev_warn(dev, "Unable to allocate the requested rings\n"); 959 return rc; 960 } 961 962 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) != 963 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) && 964 netif_is_rxfh_configured(dev)) { 965 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n"); 966 return -EINVAL; 967 } 968 969 if (netif_running(dev)) { 970 if (BNXT_PF(bp)) { 971 /* TODO CHIMP_FW: Send message to all VF's 972 * before PF unload 973 */ 974 } 975 rc = bnxt_close_nic(bp, true, false); 976 if (rc) { 977 netdev_err(bp->dev, "Set channel failure rc :%x\n", 978 rc); 979 return rc; 980 } 981 } 982 983 if (sh) { 984 bp->flags |= BNXT_FLAG_SHARED_RINGS; 985 bp->rx_nr_rings = channel->combined_count; 986 bp->tx_nr_rings_per_tc = channel->combined_count; 987 } else { 988 bp->flags &= ~BNXT_FLAG_SHARED_RINGS; 989 bp->rx_nr_rings = channel->rx_count; 990 bp->tx_nr_rings_per_tc = channel->tx_count; 991 } 992 bp->tx_nr_rings_xdp = tx_xdp; 993 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp; 994 if (tcs > 1) 995 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp; 996 997 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : 998 bp->tx_nr_rings + bp->rx_nr_rings; 999 1000 /* After changing number of rx channels, update NTUPLE feature. */ 1001 netdev_update_features(dev); 1002 if (netif_running(dev)) { 1003 rc = bnxt_open_nic(bp, true, false); 1004 if ((!rc) && BNXT_PF(bp)) { 1005 /* TODO CHIMP_FW: Send message to all VF's 1006 * to renable 1007 */ 1008 } 1009 } else { 1010 rc = bnxt_reserve_rings(bp, true); 1011 } 1012 1013 return rc; 1014 } 1015 1016 #ifdef CONFIG_RFS_ACCEL 1017 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd, 1018 u32 *rule_locs) 1019 { 1020 int i, j = 0; 1021 1022 cmd->data = bp->ntp_fltr_count; 1023 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1024 struct hlist_head *head; 1025 struct bnxt_ntuple_filter *fltr; 1026 1027 head = &bp->ntp_fltr_hash_tbl[i]; 1028 rcu_read_lock(); 1029 hlist_for_each_entry_rcu(fltr, head, hash) { 1030 if (j == cmd->rule_cnt) 1031 break; 1032 rule_locs[j++] = fltr->sw_id; 1033 } 1034 rcu_read_unlock(); 1035 if (j == cmd->rule_cnt) 1036 break; 1037 } 1038 cmd->rule_cnt = j; 1039 return 0; 1040 } 1041 1042 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1043 { 1044 struct ethtool_rx_flow_spec *fs = 1045 (struct ethtool_rx_flow_spec *)&cmd->fs; 1046 struct bnxt_ntuple_filter *fltr; 1047 struct flow_keys *fkeys; 1048 int i, rc = -EINVAL; 1049 1050 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR) 1051 return rc; 1052 1053 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { 1054 struct hlist_head *head; 1055 1056 head = &bp->ntp_fltr_hash_tbl[i]; 1057 rcu_read_lock(); 1058 hlist_for_each_entry_rcu(fltr, head, hash) { 1059 if (fltr->sw_id == fs->location) 1060 goto fltr_found; 1061 } 1062 rcu_read_unlock(); 1063 } 1064 return rc; 1065 1066 fltr_found: 1067 fkeys = &fltr->fkeys; 1068 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 1069 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1070 fs->flow_type = TCP_V4_FLOW; 1071 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1072 fs->flow_type = UDP_V4_FLOW; 1073 else 1074 goto fltr_err; 1075 1076 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src; 1077 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0); 1078 1079 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst; 1080 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0); 1081 1082 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src; 1083 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0); 1084 1085 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst; 1086 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0); 1087 } else { 1088 int i; 1089 1090 if (fkeys->basic.ip_proto == IPPROTO_TCP) 1091 fs->flow_type = TCP_V6_FLOW; 1092 else if (fkeys->basic.ip_proto == IPPROTO_UDP) 1093 fs->flow_type = UDP_V6_FLOW; 1094 else 1095 goto fltr_err; 1096 1097 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] = 1098 fkeys->addrs.v6addrs.src; 1099 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] = 1100 fkeys->addrs.v6addrs.dst; 1101 for (i = 0; i < 4; i++) { 1102 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0); 1103 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0); 1104 } 1105 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src; 1106 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0); 1107 1108 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst; 1109 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0); 1110 } 1111 1112 fs->ring_cookie = fltr->rxq; 1113 rc = 0; 1114 1115 fltr_err: 1116 rcu_read_unlock(); 1117 1118 return rc; 1119 } 1120 #endif 1121 1122 static u64 get_ethtool_ipv4_rss(struct bnxt *bp) 1123 { 1124 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4) 1125 return RXH_IP_SRC | RXH_IP_DST; 1126 return 0; 1127 } 1128 1129 static u64 get_ethtool_ipv6_rss(struct bnxt *bp) 1130 { 1131 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6) 1132 return RXH_IP_SRC | RXH_IP_DST; 1133 return 0; 1134 } 1135 1136 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1137 { 1138 cmd->data = 0; 1139 switch (cmd->flow_type) { 1140 case TCP_V4_FLOW: 1141 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) 1142 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1143 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1144 cmd->data |= get_ethtool_ipv4_rss(bp); 1145 break; 1146 case UDP_V4_FLOW: 1147 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4) 1148 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1149 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1150 fallthrough; 1151 case SCTP_V4_FLOW: 1152 case AH_ESP_V4_FLOW: 1153 case AH_V4_FLOW: 1154 case ESP_V4_FLOW: 1155 case IPV4_FLOW: 1156 cmd->data |= get_ethtool_ipv4_rss(bp); 1157 break; 1158 1159 case TCP_V6_FLOW: 1160 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) 1161 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1162 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1163 cmd->data |= get_ethtool_ipv6_rss(bp); 1164 break; 1165 case UDP_V6_FLOW: 1166 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6) 1167 cmd->data |= RXH_IP_SRC | RXH_IP_DST | 1168 RXH_L4_B_0_1 | RXH_L4_B_2_3; 1169 fallthrough; 1170 case SCTP_V6_FLOW: 1171 case AH_ESP_V6_FLOW: 1172 case AH_V6_FLOW: 1173 case ESP_V6_FLOW: 1174 case IPV6_FLOW: 1175 cmd->data |= get_ethtool_ipv6_rss(bp); 1176 break; 1177 } 1178 return 0; 1179 } 1180 1181 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3) 1182 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST) 1183 1184 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd) 1185 { 1186 u32 rss_hash_cfg = bp->rss_hash_cfg; 1187 int tuple, rc = 0; 1188 1189 if (cmd->data == RXH_4TUPLE) 1190 tuple = 4; 1191 else if (cmd->data == RXH_2TUPLE) 1192 tuple = 2; 1193 else if (!cmd->data) 1194 tuple = 0; 1195 else 1196 return -EINVAL; 1197 1198 if (cmd->flow_type == TCP_V4_FLOW) { 1199 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1200 if (tuple == 4) 1201 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4; 1202 } else if (cmd->flow_type == UDP_V4_FLOW) { 1203 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1204 return -EINVAL; 1205 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1206 if (tuple == 4) 1207 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4; 1208 } else if (cmd->flow_type == TCP_V6_FLOW) { 1209 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1210 if (tuple == 4) 1211 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6; 1212 } else if (cmd->flow_type == UDP_V6_FLOW) { 1213 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP)) 1214 return -EINVAL; 1215 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1216 if (tuple == 4) 1217 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6; 1218 } else if (tuple == 4) { 1219 return -EINVAL; 1220 } 1221 1222 switch (cmd->flow_type) { 1223 case TCP_V4_FLOW: 1224 case UDP_V4_FLOW: 1225 case SCTP_V4_FLOW: 1226 case AH_ESP_V4_FLOW: 1227 case AH_V4_FLOW: 1228 case ESP_V4_FLOW: 1229 case IPV4_FLOW: 1230 if (tuple == 2) 1231 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1232 else if (!tuple) 1233 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4; 1234 break; 1235 1236 case TCP_V6_FLOW: 1237 case UDP_V6_FLOW: 1238 case SCTP_V6_FLOW: 1239 case AH_ESP_V6_FLOW: 1240 case AH_V6_FLOW: 1241 case ESP_V6_FLOW: 1242 case IPV6_FLOW: 1243 if (tuple == 2) 1244 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1245 else if (!tuple) 1246 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6; 1247 break; 1248 } 1249 1250 if (bp->rss_hash_cfg == rss_hash_cfg) 1251 return 0; 1252 1253 if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA) 1254 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg; 1255 bp->rss_hash_cfg = rss_hash_cfg; 1256 if (netif_running(bp->dev)) { 1257 bnxt_close_nic(bp, false, false); 1258 rc = bnxt_open_nic(bp, false, false); 1259 } 1260 return rc; 1261 } 1262 1263 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1264 u32 *rule_locs) 1265 { 1266 struct bnxt *bp = netdev_priv(dev); 1267 int rc = 0; 1268 1269 switch (cmd->cmd) { 1270 #ifdef CONFIG_RFS_ACCEL 1271 case ETHTOOL_GRXRINGS: 1272 cmd->data = bp->rx_nr_rings; 1273 break; 1274 1275 case ETHTOOL_GRXCLSRLCNT: 1276 cmd->rule_cnt = bp->ntp_fltr_count; 1277 cmd->data = BNXT_NTP_FLTR_MAX_FLTR; 1278 break; 1279 1280 case ETHTOOL_GRXCLSRLALL: 1281 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs); 1282 break; 1283 1284 case ETHTOOL_GRXCLSRULE: 1285 rc = bnxt_grxclsrule(bp, cmd); 1286 break; 1287 #endif 1288 1289 case ETHTOOL_GRXFH: 1290 rc = bnxt_grxfh(bp, cmd); 1291 break; 1292 1293 default: 1294 rc = -EOPNOTSUPP; 1295 break; 1296 } 1297 1298 return rc; 1299 } 1300 1301 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1302 { 1303 struct bnxt *bp = netdev_priv(dev); 1304 int rc; 1305 1306 switch (cmd->cmd) { 1307 case ETHTOOL_SRXFH: 1308 rc = bnxt_srxfh(bp, cmd); 1309 break; 1310 1311 default: 1312 rc = -EOPNOTSUPP; 1313 break; 1314 } 1315 return rc; 1316 } 1317 1318 u32 bnxt_get_rxfh_indir_size(struct net_device *dev) 1319 { 1320 struct bnxt *bp = netdev_priv(dev); 1321 1322 if (bp->flags & BNXT_FLAG_CHIP_P5) 1323 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5); 1324 return HW_HASH_INDEX_SIZE; 1325 } 1326 1327 static u32 bnxt_get_rxfh_key_size(struct net_device *dev) 1328 { 1329 return HW_HASH_KEY_SIZE; 1330 } 1331 1332 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 1333 u8 *hfunc) 1334 { 1335 struct bnxt *bp = netdev_priv(dev); 1336 struct bnxt_vnic_info *vnic; 1337 u32 i, tbl_size; 1338 1339 if (hfunc) 1340 *hfunc = ETH_RSS_HASH_TOP; 1341 1342 if (!bp->vnic_info) 1343 return 0; 1344 1345 vnic = &bp->vnic_info[0]; 1346 if (indir && bp->rss_indir_tbl) { 1347 tbl_size = bnxt_get_rxfh_indir_size(dev); 1348 for (i = 0; i < tbl_size; i++) 1349 indir[i] = bp->rss_indir_tbl[i]; 1350 } 1351 1352 if (key && vnic->rss_hash_key) 1353 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE); 1354 1355 return 0; 1356 } 1357 1358 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir, 1359 const u8 *key, const u8 hfunc) 1360 { 1361 struct bnxt *bp = netdev_priv(dev); 1362 int rc = 0; 1363 1364 if (hfunc && hfunc != ETH_RSS_HASH_TOP) 1365 return -EOPNOTSUPP; 1366 1367 if (key) 1368 return -EOPNOTSUPP; 1369 1370 if (indir) { 1371 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev); 1372 1373 for (i = 0; i < tbl_size; i++) 1374 bp->rss_indir_tbl[i] = indir[i]; 1375 pad = bp->rss_indir_tbl_entries - tbl_size; 1376 if (pad) 1377 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16)); 1378 } 1379 1380 if (netif_running(bp->dev)) { 1381 bnxt_close_nic(bp, false, false); 1382 rc = bnxt_open_nic(bp, false, false); 1383 } 1384 return rc; 1385 } 1386 1387 static void bnxt_get_drvinfo(struct net_device *dev, 1388 struct ethtool_drvinfo *info) 1389 { 1390 struct bnxt *bp = netdev_priv(dev); 1391 1392 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1393 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version)); 1394 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1395 info->n_stats = bnxt_get_num_stats(bp); 1396 info->testinfo_len = bp->num_tests; 1397 /* TODO CHIMP_FW: eeprom dump details */ 1398 info->eedump_len = 0; 1399 /* TODO CHIMP FW: reg dump details */ 1400 info->regdump_len = 0; 1401 } 1402 1403 static int bnxt_get_regs_len(struct net_device *dev) 1404 { 1405 struct bnxt *bp = netdev_priv(dev); 1406 int reg_len; 1407 1408 if (!BNXT_PF(bp)) 1409 return -EOPNOTSUPP; 1410 1411 reg_len = BNXT_PXP_REG_LEN; 1412 1413 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED) 1414 reg_len += sizeof(struct pcie_ctx_hw_stats); 1415 1416 return reg_len; 1417 } 1418 1419 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1420 void *_p) 1421 { 1422 struct pcie_ctx_hw_stats *hw_pcie_stats; 1423 struct hwrm_pcie_qstats_input *req; 1424 struct bnxt *bp = netdev_priv(dev); 1425 dma_addr_t hw_pcie_stats_addr; 1426 int rc; 1427 1428 regs->version = 0; 1429 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p); 1430 1431 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)) 1432 return; 1433 1434 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS)) 1435 return; 1436 1437 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats), 1438 &hw_pcie_stats_addr); 1439 if (!hw_pcie_stats) { 1440 hwrm_req_drop(bp, req); 1441 return; 1442 } 1443 1444 regs->version = 1; 1445 hwrm_req_hold(bp, req); /* hold on to slice */ 1446 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats)); 1447 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr); 1448 rc = hwrm_req_send(bp, req); 1449 if (!rc) { 1450 __le64 *src = (__le64 *)hw_pcie_stats; 1451 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN); 1452 int i; 1453 1454 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++) 1455 dst[i] = le64_to_cpu(src[i]); 1456 } 1457 hwrm_req_drop(bp, req); 1458 } 1459 1460 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1461 { 1462 struct bnxt *bp = netdev_priv(dev); 1463 1464 wol->supported = 0; 1465 wol->wolopts = 0; 1466 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1467 if (bp->flags & BNXT_FLAG_WOL_CAP) { 1468 wol->supported = WAKE_MAGIC; 1469 if (bp->wol) 1470 wol->wolopts = WAKE_MAGIC; 1471 } 1472 } 1473 1474 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1475 { 1476 struct bnxt *bp = netdev_priv(dev); 1477 1478 if (wol->wolopts & ~WAKE_MAGIC) 1479 return -EINVAL; 1480 1481 if (wol->wolopts & WAKE_MAGIC) { 1482 if (!(bp->flags & BNXT_FLAG_WOL_CAP)) 1483 return -EINVAL; 1484 if (!bp->wol) { 1485 if (bnxt_hwrm_alloc_wol_fltr(bp)) 1486 return -EBUSY; 1487 bp->wol = 1; 1488 } 1489 } else { 1490 if (bp->wol) { 1491 if (bnxt_hwrm_free_wol_fltr(bp)) 1492 return -EBUSY; 1493 bp->wol = 0; 1494 } 1495 } 1496 return 0; 1497 } 1498 1499 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause) 1500 { 1501 u32 speed_mask = 0; 1502 1503 /* TODO: support 25GB, 40GB, 50GB with different cable type */ 1504 /* set the advertised speeds */ 1505 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB) 1506 speed_mask |= ADVERTISED_100baseT_Full; 1507 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB) 1508 speed_mask |= ADVERTISED_1000baseT_Full; 1509 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB) 1510 speed_mask |= ADVERTISED_2500baseX_Full; 1511 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB) 1512 speed_mask |= ADVERTISED_10000baseT_Full; 1513 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB) 1514 speed_mask |= ADVERTISED_40000baseCR4_Full; 1515 1516 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH) 1517 speed_mask |= ADVERTISED_Pause; 1518 else if (fw_pause & BNXT_LINK_PAUSE_TX) 1519 speed_mask |= ADVERTISED_Asym_Pause; 1520 else if (fw_pause & BNXT_LINK_PAUSE_RX) 1521 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 1522 1523 return speed_mask; 1524 } 1525 1526 enum bnxt_media_type { 1527 BNXT_MEDIA_UNKNOWN = 0, 1528 BNXT_MEDIA_TP, 1529 BNXT_MEDIA_CR, 1530 BNXT_MEDIA_SR, 1531 BNXT_MEDIA_LR_ER_FR, 1532 BNXT_MEDIA_KR, 1533 BNXT_MEDIA_KX, 1534 BNXT_MEDIA_X, 1535 __BNXT_MEDIA_END, 1536 }; 1537 1538 static const enum bnxt_media_type bnxt_phy_types[] = { 1539 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR, 1540 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR, 1541 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR, 1542 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR, 1543 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR, 1544 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX, 1545 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR, 1546 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP, 1547 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP, 1548 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR, 1549 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR, 1550 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR, 1551 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR, 1552 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR, 1553 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR, 1554 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1555 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1556 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR, 1557 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR, 1558 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR, 1559 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1560 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1561 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR, 1562 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP, 1563 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X, 1564 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X, 1565 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR, 1566 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR, 1567 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR, 1568 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR, 1569 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR, 1570 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR, 1571 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR, 1572 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR, 1573 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR, 1574 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR, 1575 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR, 1576 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR, 1577 }; 1578 1579 static enum bnxt_media_type 1580 bnxt_get_media(struct bnxt_link_info *link_info) 1581 { 1582 switch (link_info->media_type) { 1583 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP: 1584 return BNXT_MEDIA_TP; 1585 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC: 1586 return BNXT_MEDIA_CR; 1587 default: 1588 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types)) 1589 return bnxt_phy_types[link_info->phy_type]; 1590 return BNXT_MEDIA_UNKNOWN; 1591 } 1592 } 1593 1594 enum bnxt_link_speed_indices { 1595 BNXT_LINK_SPEED_UNKNOWN = 0, 1596 BNXT_LINK_SPEED_100MB_IDX, 1597 BNXT_LINK_SPEED_1GB_IDX, 1598 BNXT_LINK_SPEED_10GB_IDX, 1599 BNXT_LINK_SPEED_25GB_IDX, 1600 BNXT_LINK_SPEED_40GB_IDX, 1601 BNXT_LINK_SPEED_50GB_IDX, 1602 BNXT_LINK_SPEED_100GB_IDX, 1603 BNXT_LINK_SPEED_200GB_IDX, 1604 __BNXT_LINK_SPEED_END 1605 }; 1606 1607 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed) 1608 { 1609 switch (speed) { 1610 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX; 1611 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX; 1612 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX; 1613 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX; 1614 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX; 1615 case BNXT_LINK_SPEED_50GB: return BNXT_LINK_SPEED_50GB_IDX; 1616 case BNXT_LINK_SPEED_100GB: return BNXT_LINK_SPEED_100GB_IDX; 1617 case BNXT_LINK_SPEED_200GB: return BNXT_LINK_SPEED_200GB_IDX; 1618 default: return BNXT_LINK_SPEED_UNKNOWN; 1619 } 1620 } 1621 1622 static const enum ethtool_link_mode_bit_indices 1623 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = { 1624 [BNXT_LINK_SPEED_100MB_IDX] = { 1625 { 1626 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1627 }, 1628 }, 1629 [BNXT_LINK_SPEED_1GB_IDX] = { 1630 { 1631 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1632 /* historically baseT, but DAC is more correctly baseX */ 1633 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1634 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1635 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1636 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1637 }, 1638 }, 1639 [BNXT_LINK_SPEED_10GB_IDX] = { 1640 { 1641 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1642 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 1643 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1644 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1645 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1646 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 1647 }, 1648 }, 1649 [BNXT_LINK_SPEED_25GB_IDX] = { 1650 { 1651 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1652 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1653 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1654 }, 1655 }, 1656 [BNXT_LINK_SPEED_40GB_IDX] = { 1657 { 1658 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1659 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1660 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1661 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1662 }, 1663 }, 1664 [BNXT_LINK_SPEED_50GB_IDX] = { 1665 [BNXT_SIG_MODE_NRZ] = { 1666 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1667 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1668 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1669 }, 1670 [BNXT_SIG_MODE_PAM4] = { 1671 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 1672 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 1673 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1674 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 1675 }, 1676 }, 1677 [BNXT_LINK_SPEED_100GB_IDX] = { 1678 [BNXT_SIG_MODE_NRZ] = { 1679 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1680 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1681 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1682 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1683 }, 1684 [BNXT_SIG_MODE_PAM4] = { 1685 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 1686 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 1687 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 1688 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 1689 }, 1690 }, 1691 [BNXT_LINK_SPEED_200GB_IDX] = { 1692 [BNXT_SIG_MODE_PAM4] = { 1693 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1694 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 1695 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 1696 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1697 }, 1698 }, 1699 }; 1700 1701 #define BNXT_LINK_MODE_UNKNOWN -1 1702 1703 static enum ethtool_link_mode_bit_indices 1704 bnxt_get_link_mode(struct bnxt_link_info *link_info) 1705 { 1706 enum ethtool_link_mode_bit_indices link_mode; 1707 enum bnxt_link_speed_indices speed; 1708 enum bnxt_media_type media; 1709 u8 sig_mode; 1710 1711 if (link_info->phy_link_status != BNXT_LINK_LINK) 1712 return BNXT_LINK_MODE_UNKNOWN; 1713 1714 media = bnxt_get_media(link_info); 1715 if (BNXT_AUTO_MODE(link_info->auto_mode)) { 1716 speed = bnxt_fw_speed_idx(link_info->link_speed); 1717 sig_mode = link_info->active_fec_sig_mode & 1718 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK; 1719 } else { 1720 speed = bnxt_fw_speed_idx(link_info->req_link_speed); 1721 sig_mode = link_info->req_signal_mode; 1722 } 1723 if (sig_mode >= BNXT_SIG_MODE_MAX) 1724 return BNXT_LINK_MODE_UNKNOWN; 1725 1726 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux 1727 * link mode, but since no such devices exist, the zeroes in the 1728 * map can be conveniently used to represent unknown link modes. 1729 */ 1730 link_mode = bnxt_link_modes[speed][sig_mode][media]; 1731 if (!link_mode) 1732 return BNXT_LINK_MODE_UNKNOWN; 1733 1734 switch (link_mode) { 1735 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 1736 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1737 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT; 1738 break; 1739 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 1740 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1741 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT; 1742 break; 1743 default: 1744 break; 1745 } 1746 1747 return link_mode; 1748 } 1749 1750 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info, 1751 struct ethtool_link_ksettings *lk_ksettings) 1752 { 1753 struct bnxt *bp = container_of(link_info, struct bnxt, link_info); 1754 1755 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) { 1756 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1757 lk_ksettings->link_modes.supported); 1758 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1759 lk_ksettings->link_modes.supported); 1760 } 1761 1762 if (link_info->support_auto_speeds || link_info->support_pam4_auto_speeds) 1763 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1764 lk_ksettings->link_modes.supported); 1765 1766 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 1767 return; 1768 1769 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX) 1770 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1771 lk_ksettings->link_modes.advertising); 1772 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1) 1773 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1774 lk_ksettings->link_modes.advertising); 1775 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX) 1776 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1777 lk_ksettings->link_modes.lp_advertising); 1778 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1) 1779 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1780 lk_ksettings->link_modes.lp_advertising); 1781 } 1782 1783 static const u16 bnxt_nrz_speed_masks[] = { 1784 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB, 1785 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB, 1786 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB, 1787 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB, 1788 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB, 1789 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB, 1790 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB, 1791 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */ 1792 }; 1793 1794 static const u16 bnxt_pam4_speed_masks[] = { 1795 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB, 1796 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB, 1797 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB, 1798 }; 1799 1800 static enum bnxt_link_speed_indices 1801 bnxt_encoding_speed_idx(u8 sig_mode, u16 speed_msk) 1802 { 1803 const u16 *speeds; 1804 int idx, len; 1805 1806 switch (sig_mode) { 1807 case BNXT_SIG_MODE_NRZ: 1808 speeds = bnxt_nrz_speed_masks; 1809 len = ARRAY_SIZE(bnxt_nrz_speed_masks); 1810 break; 1811 case BNXT_SIG_MODE_PAM4: 1812 speeds = bnxt_pam4_speed_masks; 1813 len = ARRAY_SIZE(bnxt_pam4_speed_masks); 1814 break; 1815 default: 1816 return BNXT_LINK_SPEED_UNKNOWN; 1817 } 1818 1819 for (idx = 0; idx < len; idx++) { 1820 if (speeds[idx] == speed_msk) 1821 return idx; 1822 } 1823 1824 return BNXT_LINK_SPEED_UNKNOWN; 1825 } 1826 1827 #define BNXT_FW_SPEED_MSK_BITS 16 1828 1829 static void 1830 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 1831 u8 sig_mode, unsigned long *et_mask) 1832 { 1833 enum ethtool_link_mode_bit_indices link_mode; 1834 enum bnxt_link_speed_indices speed; 1835 u8 bit; 1836 1837 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) { 1838 speed = bnxt_encoding_speed_idx(sig_mode, 1 << bit); 1839 if (!speed) 1840 continue; 1841 1842 link_mode = bnxt_link_modes[speed][sig_mode][media]; 1843 if (!link_mode) 1844 continue; 1845 1846 linkmode_set_bit(link_mode, et_mask); 1847 } 1848 } 1849 1850 static void 1851 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media, 1852 u8 sig_mode, unsigned long *et_mask) 1853 { 1854 if (media) { 1855 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, et_mask); 1856 return; 1857 } 1858 1859 /* list speeds for all media if unknown */ 1860 for (media = 1; media < __BNXT_MEDIA_END; media++) 1861 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, et_mask); 1862 } 1863 1864 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds, 1865 u16 speed_msk, const unsigned long *et_mask, 1866 enum ethtool_link_mode_bit_indices mode) 1867 { 1868 bool mode_desired = linkmode_test_bit(mode, et_mask); 1869 1870 if (!mode) 1871 return; 1872 1873 /* enabled speeds for installed media should override */ 1874 if (installed_media && mode_desired) { 1875 *speeds |= speed_msk; 1876 *delta |= speed_msk; 1877 return; 1878 } 1879 1880 /* many to one mapping, only allow one change per fw_speed bit */ 1881 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) { 1882 *speeds ^= speed_msk; 1883 *delta |= speed_msk; 1884 } 1885 } 1886 1887 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info, 1888 const unsigned long *et_mask) 1889 { 1890 enum bnxt_media_type media = bnxt_get_media(link_info); 1891 u32 delta_pam4 = 0; 1892 u32 delta_nrz = 0; 1893 int i, m; 1894 1895 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) { 1896 /* accept any legal media from user */ 1897 for (m = 1; m < __BNXT_MEDIA_END; m++) { 1898 bnxt_update_speed(&delta_nrz, m == media, 1899 &link_info->advertising, 1900 bnxt_nrz_speed_masks[i], et_mask, 1901 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]); 1902 bnxt_update_speed(&delta_pam4, m == media, 1903 &link_info->advertising_pam4, 1904 bnxt_pam4_speed_masks[i], et_mask, 1905 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]); 1906 } 1907 } 1908 } 1909 1910 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info, 1911 struct ethtool_link_ksettings *lk_ksettings) 1912 { 1913 u16 fec_cfg = link_info->fec_cfg; 1914 1915 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) { 1916 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1917 lk_ksettings->link_modes.advertising); 1918 return; 1919 } 1920 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 1921 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1922 lk_ksettings->link_modes.advertising); 1923 if (fec_cfg & BNXT_FEC_ENC_RS) 1924 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1925 lk_ksettings->link_modes.advertising); 1926 if (fec_cfg & BNXT_FEC_ENC_LLRS) 1927 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1928 lk_ksettings->link_modes.advertising); 1929 } 1930 1931 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info, 1932 struct ethtool_link_ksettings *lk_ksettings) 1933 { 1934 u16 fec_cfg = link_info->fec_cfg; 1935 1936 if (fec_cfg & BNXT_FEC_NONE) { 1937 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1938 lk_ksettings->link_modes.supported); 1939 return; 1940 } 1941 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP) 1942 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1943 lk_ksettings->link_modes.supported); 1944 if (fec_cfg & BNXT_FEC_ENC_RS_CAP) 1945 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1946 lk_ksettings->link_modes.supported); 1947 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP) 1948 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1949 lk_ksettings->link_modes.supported); 1950 } 1951 1952 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 1953 { 1954 switch (fw_link_speed) { 1955 case BNXT_LINK_SPEED_100MB: 1956 return SPEED_100; 1957 case BNXT_LINK_SPEED_1GB: 1958 return SPEED_1000; 1959 case BNXT_LINK_SPEED_2_5GB: 1960 return SPEED_2500; 1961 case BNXT_LINK_SPEED_10GB: 1962 return SPEED_10000; 1963 case BNXT_LINK_SPEED_20GB: 1964 return SPEED_20000; 1965 case BNXT_LINK_SPEED_25GB: 1966 return SPEED_25000; 1967 case BNXT_LINK_SPEED_40GB: 1968 return SPEED_40000; 1969 case BNXT_LINK_SPEED_50GB: 1970 return SPEED_50000; 1971 case BNXT_LINK_SPEED_100GB: 1972 return SPEED_100000; 1973 case BNXT_LINK_SPEED_200GB: 1974 return SPEED_200000; 1975 default: 1976 return SPEED_UNKNOWN; 1977 } 1978 } 1979 1980 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings, 1981 struct bnxt_link_info *link_info) 1982 { 1983 struct ethtool_link_settings *base = &lk_ksettings->base; 1984 1985 if (link_info->link_state == BNXT_LINK_STATE_UP) { 1986 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed); 1987 base->duplex = DUPLEX_HALF; 1988 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL) 1989 base->duplex = DUPLEX_FULL; 1990 } else if (!link_info->autoneg) { 1991 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed); 1992 base->duplex = DUPLEX_HALF; 1993 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL) 1994 base->duplex = DUPLEX_FULL; 1995 } 1996 } 1997 1998 static int bnxt_get_link_ksettings(struct net_device *dev, 1999 struct ethtool_link_ksettings *lk_ksettings) 2000 { 2001 struct ethtool_link_settings *base = &lk_ksettings->base; 2002 enum ethtool_link_mode_bit_indices link_mode; 2003 struct bnxt *bp = netdev_priv(dev); 2004 struct bnxt_link_info *link_info; 2005 enum bnxt_media_type media; 2006 2007 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising); 2008 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising); 2009 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported); 2010 base->duplex = DUPLEX_UNKNOWN; 2011 base->speed = SPEED_UNKNOWN; 2012 link_info = &bp->link_info; 2013 2014 mutex_lock(&bp->link_lock); 2015 bnxt_get_ethtool_modes(link_info, lk_ksettings); 2016 media = bnxt_get_media(link_info); 2017 bnxt_get_ethtool_speeds(link_info->support_speeds, 2018 media, BNXT_SIG_MODE_NRZ, 2019 lk_ksettings->link_modes.supported); 2020 bnxt_get_ethtool_speeds(link_info->support_pam4_speeds, 2021 media, BNXT_SIG_MODE_PAM4, 2022 lk_ksettings->link_modes.supported); 2023 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings); 2024 link_mode = bnxt_get_link_mode(link_info); 2025 if (link_mode != BNXT_LINK_MODE_UNKNOWN) 2026 ethtool_params_from_link_mode(lk_ksettings, link_mode); 2027 else 2028 bnxt_get_default_speeds(lk_ksettings, link_info); 2029 2030 if (link_info->autoneg) { 2031 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings); 2032 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2033 lk_ksettings->link_modes.advertising); 2034 base->autoneg = AUTONEG_ENABLE; 2035 bnxt_get_ethtool_speeds(link_info->advertising, 2036 media, BNXT_SIG_MODE_NRZ, 2037 lk_ksettings->link_modes.advertising); 2038 bnxt_get_ethtool_speeds(link_info->advertising_pam4, 2039 media, BNXT_SIG_MODE_PAM4, 2040 lk_ksettings->link_modes.advertising); 2041 if (link_info->phy_link_status == BNXT_LINK_LINK) { 2042 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, 2043 media, BNXT_SIG_MODE_NRZ, 2044 lk_ksettings->link_modes.lp_advertising); 2045 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, 2046 media, BNXT_SIG_MODE_PAM4, 2047 lk_ksettings->link_modes.lp_advertising); 2048 } 2049 } else { 2050 base->autoneg = AUTONEG_DISABLE; 2051 } 2052 2053 base->port = PORT_NONE; 2054 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 2055 base->port = PORT_TP; 2056 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2057 lk_ksettings->link_modes.supported); 2058 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, 2059 lk_ksettings->link_modes.advertising); 2060 } else { 2061 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2062 lk_ksettings->link_modes.supported); 2063 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 2064 lk_ksettings->link_modes.advertising); 2065 2066 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC) 2067 base->port = PORT_DA; 2068 else 2069 base->port = PORT_FIBRE; 2070 } 2071 base->phy_address = link_info->phy_addr; 2072 mutex_unlock(&bp->link_lock); 2073 2074 return 0; 2075 } 2076 2077 static int 2078 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes) 2079 { 2080 struct bnxt *bp = netdev_priv(dev); 2081 struct bnxt_link_info *link_info = &bp->link_info; 2082 u16 support_pam4_spds = link_info->support_pam4_speeds; 2083 u16 support_spds = link_info->support_speeds; 2084 u8 sig_mode = BNXT_SIG_MODE_NRZ; 2085 u32 lanes_needed = 1; 2086 u16 fw_speed = 0; 2087 2088 switch (ethtool_speed) { 2089 case SPEED_100: 2090 if (support_spds & BNXT_LINK_SPEED_MSK_100MB) 2091 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB; 2092 break; 2093 case SPEED_1000: 2094 if (support_spds & BNXT_LINK_SPEED_MSK_1GB) 2095 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 2096 break; 2097 case SPEED_2500: 2098 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB) 2099 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB; 2100 break; 2101 case SPEED_10000: 2102 if (support_spds & BNXT_LINK_SPEED_MSK_10GB) 2103 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 2104 break; 2105 case SPEED_20000: 2106 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) { 2107 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB; 2108 lanes_needed = 2; 2109 } 2110 break; 2111 case SPEED_25000: 2112 if (support_spds & BNXT_LINK_SPEED_MSK_25GB) 2113 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 2114 break; 2115 case SPEED_40000: 2116 if (support_spds & BNXT_LINK_SPEED_MSK_40GB) { 2117 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 2118 lanes_needed = 4; 2119 } 2120 break; 2121 case SPEED_50000: 2122 if ((support_spds & BNXT_LINK_SPEED_MSK_50GB) && lanes != 1) { 2123 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 2124 lanes_needed = 2; 2125 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) { 2126 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB; 2127 sig_mode = BNXT_SIG_MODE_PAM4; 2128 } 2129 break; 2130 case SPEED_100000: 2131 if ((support_spds & BNXT_LINK_SPEED_MSK_100GB) && 2132 lanes != 2 && lanes != 1) { 2133 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB; 2134 lanes_needed = 4; 2135 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) { 2136 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB; 2137 sig_mode = BNXT_SIG_MODE_PAM4; 2138 lanes_needed = 2; 2139 } 2140 break; 2141 case SPEED_200000: 2142 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) { 2143 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB; 2144 sig_mode = BNXT_SIG_MODE_PAM4; 2145 lanes_needed = 4; 2146 } 2147 break; 2148 } 2149 2150 if (!fw_speed) { 2151 netdev_err(dev, "unsupported speed!\n"); 2152 return -EINVAL; 2153 } 2154 2155 if (lanes && lanes != lanes_needed) { 2156 netdev_err(dev, "unsupported number of lanes for speed\n"); 2157 return -EINVAL; 2158 } 2159 2160 if (link_info->req_link_speed == fw_speed && 2161 link_info->req_signal_mode == sig_mode && 2162 link_info->autoneg == 0) 2163 return -EALREADY; 2164 2165 link_info->req_link_speed = fw_speed; 2166 link_info->req_signal_mode = sig_mode; 2167 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL; 2168 link_info->autoneg = 0; 2169 link_info->advertising = 0; 2170 link_info->advertising_pam4 = 0; 2171 2172 return 0; 2173 } 2174 2175 u16 bnxt_get_fw_auto_link_speeds(u32 advertising) 2176 { 2177 u16 fw_speed_mask = 0; 2178 2179 /* only support autoneg at speed 100, 1000, and 10000 */ 2180 if (advertising & (ADVERTISED_100baseT_Full | 2181 ADVERTISED_100baseT_Half)) { 2182 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB; 2183 } 2184 if (advertising & (ADVERTISED_1000baseT_Full | 2185 ADVERTISED_1000baseT_Half)) { 2186 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB; 2187 } 2188 if (advertising & ADVERTISED_10000baseT_Full) 2189 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB; 2190 2191 if (advertising & ADVERTISED_40000baseCR4_Full) 2192 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB; 2193 2194 return fw_speed_mask; 2195 } 2196 2197 static int bnxt_set_link_ksettings(struct net_device *dev, 2198 const struct ethtool_link_ksettings *lk_ksettings) 2199 { 2200 struct bnxt *bp = netdev_priv(dev); 2201 struct bnxt_link_info *link_info = &bp->link_info; 2202 const struct ethtool_link_settings *base = &lk_ksettings->base; 2203 bool set_pause = false; 2204 u32 speed, lanes = 0; 2205 int rc = 0; 2206 2207 if (!BNXT_PHY_CFG_ABLE(bp)) 2208 return -EOPNOTSUPP; 2209 2210 mutex_lock(&bp->link_lock); 2211 if (base->autoneg == AUTONEG_ENABLE) { 2212 bnxt_set_ethtool_speeds(link_info, 2213 lk_ksettings->link_modes.advertising); 2214 link_info->autoneg |= BNXT_AUTONEG_SPEED; 2215 if (!link_info->advertising && !link_info->advertising_pam4) { 2216 link_info->advertising = link_info->support_auto_speeds; 2217 link_info->advertising_pam4 = 2218 link_info->support_pam4_auto_speeds; 2219 } 2220 /* any change to autoneg will cause link change, therefore the 2221 * driver should put back the original pause setting in autoneg 2222 */ 2223 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 2224 set_pause = true; 2225 } else { 2226 u8 phy_type = link_info->phy_type; 2227 2228 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET || 2229 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE || 2230 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) { 2231 netdev_err(dev, "10GBase-T devices must autoneg\n"); 2232 rc = -EINVAL; 2233 goto set_setting_exit; 2234 } 2235 if (base->duplex == DUPLEX_HALF) { 2236 netdev_err(dev, "HALF DUPLEX is not supported!\n"); 2237 rc = -EINVAL; 2238 goto set_setting_exit; 2239 } 2240 speed = base->speed; 2241 lanes = lk_ksettings->lanes; 2242 rc = bnxt_force_link_speed(dev, speed, lanes); 2243 if (rc) { 2244 if (rc == -EALREADY) 2245 rc = 0; 2246 goto set_setting_exit; 2247 } 2248 } 2249 2250 if (netif_running(dev)) 2251 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false); 2252 2253 set_setting_exit: 2254 mutex_unlock(&bp->link_lock); 2255 return rc; 2256 } 2257 2258 static int bnxt_get_fecparam(struct net_device *dev, 2259 struct ethtool_fecparam *fec) 2260 { 2261 struct bnxt *bp = netdev_priv(dev); 2262 struct bnxt_link_info *link_info; 2263 u8 active_fec; 2264 u16 fec_cfg; 2265 2266 link_info = &bp->link_info; 2267 fec_cfg = link_info->fec_cfg; 2268 active_fec = link_info->active_fec_sig_mode & 2269 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK; 2270 if (fec_cfg & BNXT_FEC_NONE) { 2271 fec->fec = ETHTOOL_FEC_NONE; 2272 fec->active_fec = ETHTOOL_FEC_NONE; 2273 return 0; 2274 } 2275 if (fec_cfg & BNXT_FEC_AUTONEG) 2276 fec->fec |= ETHTOOL_FEC_AUTO; 2277 if (fec_cfg & BNXT_FEC_ENC_BASE_R) 2278 fec->fec |= ETHTOOL_FEC_BASER; 2279 if (fec_cfg & BNXT_FEC_ENC_RS) 2280 fec->fec |= ETHTOOL_FEC_RS; 2281 if (fec_cfg & BNXT_FEC_ENC_LLRS) 2282 fec->fec |= ETHTOOL_FEC_LLRS; 2283 2284 switch (active_fec) { 2285 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE: 2286 fec->active_fec |= ETHTOOL_FEC_BASER; 2287 break; 2288 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE: 2289 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE: 2290 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE: 2291 fec->active_fec |= ETHTOOL_FEC_RS; 2292 break; 2293 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE: 2294 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE: 2295 fec->active_fec |= ETHTOOL_FEC_LLRS; 2296 break; 2297 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE: 2298 fec->active_fec |= ETHTOOL_FEC_OFF; 2299 break; 2300 } 2301 return 0; 2302 } 2303 2304 static void bnxt_get_fec_stats(struct net_device *dev, 2305 struct ethtool_fec_stats *fec_stats) 2306 { 2307 struct bnxt *bp = netdev_priv(dev); 2308 u64 *rx; 2309 2310 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 2311 return; 2312 2313 rx = bp->rx_port_stats_ext.sw_stats; 2314 fec_stats->corrected_bits.total = 2315 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits)); 2316 2317 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY) 2318 return; 2319 2320 fec_stats->corrected_blocks.total = 2321 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 2322 fec_stats->uncorrectable_blocks.total = 2323 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 2324 } 2325 2326 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, 2327 u32 fec) 2328 { 2329 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE; 2330 2331 if (fec & ETHTOOL_FEC_BASER) 2332 fw_fec |= BNXT_FEC_BASE_R_ON(link_info); 2333 else if (fec & ETHTOOL_FEC_RS) 2334 fw_fec |= BNXT_FEC_RS_ON(link_info); 2335 else if (fec & ETHTOOL_FEC_LLRS) 2336 fw_fec |= BNXT_FEC_LLRS_ON; 2337 return fw_fec; 2338 } 2339 2340 static int bnxt_set_fecparam(struct net_device *dev, 2341 struct ethtool_fecparam *fecparam) 2342 { 2343 struct hwrm_port_phy_cfg_input *req; 2344 struct bnxt *bp = netdev_priv(dev); 2345 struct bnxt_link_info *link_info; 2346 u32 new_cfg, fec = fecparam->fec; 2347 u16 fec_cfg; 2348 int rc; 2349 2350 link_info = &bp->link_info; 2351 fec_cfg = link_info->fec_cfg; 2352 if (fec_cfg & BNXT_FEC_NONE) 2353 return -EOPNOTSUPP; 2354 2355 if (fec & ETHTOOL_FEC_OFF) { 2356 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE | 2357 BNXT_FEC_ALL_OFF(link_info); 2358 goto apply_fec; 2359 } 2360 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) || 2361 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) || 2362 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) || 2363 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP))) 2364 return -EINVAL; 2365 2366 if (fec & ETHTOOL_FEC_AUTO) { 2367 if (!link_info->autoneg) 2368 return -EINVAL; 2369 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE; 2370 } else { 2371 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec); 2372 } 2373 2374 apply_fec: 2375 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 2376 if (rc) 2377 return rc; 2378 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 2379 rc = hwrm_req_send(bp, req); 2380 /* update current settings */ 2381 if (!rc) { 2382 mutex_lock(&bp->link_lock); 2383 bnxt_update_link(bp, false); 2384 mutex_unlock(&bp->link_lock); 2385 } 2386 return rc; 2387 } 2388 2389 static void bnxt_get_pauseparam(struct net_device *dev, 2390 struct ethtool_pauseparam *epause) 2391 { 2392 struct bnxt *bp = netdev_priv(dev); 2393 struct bnxt_link_info *link_info = &bp->link_info; 2394 2395 if (BNXT_VF(bp)) 2396 return; 2397 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL); 2398 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX); 2399 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX); 2400 } 2401 2402 static void bnxt_get_pause_stats(struct net_device *dev, 2403 struct ethtool_pause_stats *epstat) 2404 { 2405 struct bnxt *bp = netdev_priv(dev); 2406 u64 *rx, *tx; 2407 2408 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 2409 return; 2410 2411 rx = bp->port_stats.sw_stats; 2412 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 2413 2414 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames); 2415 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames); 2416 } 2417 2418 static int bnxt_set_pauseparam(struct net_device *dev, 2419 struct ethtool_pauseparam *epause) 2420 { 2421 int rc = 0; 2422 struct bnxt *bp = netdev_priv(dev); 2423 struct bnxt_link_info *link_info = &bp->link_info; 2424 2425 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) 2426 return -EOPNOTSUPP; 2427 2428 mutex_lock(&bp->link_lock); 2429 if (epause->autoneg) { 2430 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 2431 rc = -EINVAL; 2432 goto pause_exit; 2433 } 2434 2435 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; 2436 link_info->req_flow_ctrl = 0; 2437 } else { 2438 /* when transition from auto pause to force pause, 2439 * force a link change 2440 */ 2441 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) 2442 link_info->force_link_chng = true; 2443 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL; 2444 link_info->req_flow_ctrl = 0; 2445 } 2446 if (epause->rx_pause) 2447 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX; 2448 2449 if (epause->tx_pause) 2450 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX; 2451 2452 if (netif_running(dev)) 2453 rc = bnxt_hwrm_set_pause(bp); 2454 2455 pause_exit: 2456 mutex_unlock(&bp->link_lock); 2457 return rc; 2458 } 2459 2460 static u32 bnxt_get_link(struct net_device *dev) 2461 { 2462 struct bnxt *bp = netdev_priv(dev); 2463 2464 /* TODO: handle MF, VF, driver close case */ 2465 return BNXT_LINK_IS_UP(bp); 2466 } 2467 2468 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, 2469 struct hwrm_nvm_get_dev_info_output *nvm_dev_info) 2470 { 2471 struct hwrm_nvm_get_dev_info_output *resp; 2472 struct hwrm_nvm_get_dev_info_input *req; 2473 int rc; 2474 2475 if (BNXT_VF(bp)) 2476 return -EOPNOTSUPP; 2477 2478 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO); 2479 if (rc) 2480 return rc; 2481 2482 resp = hwrm_req_hold(bp, req); 2483 rc = hwrm_req_send(bp, req); 2484 if (!rc) 2485 memcpy(nvm_dev_info, resp, sizeof(*resp)); 2486 hwrm_req_drop(bp, req); 2487 return rc; 2488 } 2489 2490 static void bnxt_print_admin_err(struct bnxt *bp) 2491 { 2492 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n"); 2493 } 2494 2495 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 2496 u16 ext, u16 *index, u32 *item_length, 2497 u32 *data_length); 2498 2499 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type, 2500 u16 dir_ordinal, u16 dir_ext, u16 dir_attr, 2501 u32 dir_item_len, const u8 *data, 2502 size_t data_len) 2503 { 2504 struct bnxt *bp = netdev_priv(dev); 2505 struct hwrm_nvm_write_input *req; 2506 int rc; 2507 2508 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE); 2509 if (rc) 2510 return rc; 2511 2512 if (data_len && data) { 2513 dma_addr_t dma_handle; 2514 u8 *kmem; 2515 2516 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle); 2517 if (!kmem) { 2518 hwrm_req_drop(bp, req); 2519 return -ENOMEM; 2520 } 2521 2522 req->dir_data_length = cpu_to_le32(data_len); 2523 2524 memcpy(kmem, data, data_len); 2525 req->host_src_addr = cpu_to_le64(dma_handle); 2526 } 2527 2528 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 2529 req->dir_type = cpu_to_le16(dir_type); 2530 req->dir_ordinal = cpu_to_le16(dir_ordinal); 2531 req->dir_ext = cpu_to_le16(dir_ext); 2532 req->dir_attr = cpu_to_le16(dir_attr); 2533 req->dir_item_length = cpu_to_le32(dir_item_len); 2534 rc = hwrm_req_send(bp, req); 2535 2536 if (rc == -EACCES) 2537 bnxt_print_admin_err(bp); 2538 return rc; 2539 } 2540 2541 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type, 2542 u8 self_reset, u8 flags) 2543 { 2544 struct bnxt *bp = netdev_priv(dev); 2545 struct hwrm_fw_reset_input *req; 2546 int rc; 2547 2548 if (!bnxt_hwrm_reset_permitted(bp)) { 2549 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver"); 2550 return -EPERM; 2551 } 2552 2553 rc = hwrm_req_init(bp, req, HWRM_FW_RESET); 2554 if (rc) 2555 return rc; 2556 2557 req->embedded_proc_type = proc_type; 2558 req->selfrst_status = self_reset; 2559 req->flags = flags; 2560 2561 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) { 2562 rc = hwrm_req_send_silent(bp, req); 2563 } else { 2564 rc = hwrm_req_send(bp, req); 2565 if (rc == -EACCES) 2566 bnxt_print_admin_err(bp); 2567 } 2568 return rc; 2569 } 2570 2571 static int bnxt_firmware_reset(struct net_device *dev, 2572 enum bnxt_nvm_directory_type dir_type) 2573 { 2574 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE; 2575 u8 proc_type, flags = 0; 2576 2577 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */ 2578 /* (e.g. when firmware isn't already running) */ 2579 switch (dir_type) { 2580 case BNX_DIR_TYPE_CHIMP_PATCH: 2581 case BNX_DIR_TYPE_BOOTCODE: 2582 case BNX_DIR_TYPE_BOOTCODE_2: 2583 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT; 2584 /* Self-reset ChiMP upon next PCIe reset: */ 2585 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2586 break; 2587 case BNX_DIR_TYPE_APE_FW: 2588 case BNX_DIR_TYPE_APE_PATCH: 2589 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT; 2590 /* Self-reset APE upon next PCIe reset: */ 2591 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST; 2592 break; 2593 case BNX_DIR_TYPE_KONG_FW: 2594 case BNX_DIR_TYPE_KONG_PATCH: 2595 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL; 2596 break; 2597 case BNX_DIR_TYPE_BONO_FW: 2598 case BNX_DIR_TYPE_BONO_PATCH: 2599 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE; 2600 break; 2601 default: 2602 return -EINVAL; 2603 } 2604 2605 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags); 2606 } 2607 2608 static int bnxt_firmware_reset_chip(struct net_device *dev) 2609 { 2610 struct bnxt *bp = netdev_priv(dev); 2611 u8 flags = 0; 2612 2613 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET) 2614 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL; 2615 2616 return bnxt_hwrm_firmware_reset(dev, 2617 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP, 2618 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP, 2619 flags); 2620 } 2621 2622 static int bnxt_firmware_reset_ap(struct net_device *dev) 2623 { 2624 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP, 2625 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE, 2626 0); 2627 } 2628 2629 static int bnxt_flash_firmware(struct net_device *dev, 2630 u16 dir_type, 2631 const u8 *fw_data, 2632 size_t fw_size) 2633 { 2634 int rc = 0; 2635 u16 code_type; 2636 u32 stored_crc; 2637 u32 calculated_crc; 2638 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data; 2639 2640 switch (dir_type) { 2641 case BNX_DIR_TYPE_BOOTCODE: 2642 case BNX_DIR_TYPE_BOOTCODE_2: 2643 code_type = CODE_BOOT; 2644 break; 2645 case BNX_DIR_TYPE_CHIMP_PATCH: 2646 code_type = CODE_CHIMP_PATCH; 2647 break; 2648 case BNX_DIR_TYPE_APE_FW: 2649 code_type = CODE_MCTP_PASSTHRU; 2650 break; 2651 case BNX_DIR_TYPE_APE_PATCH: 2652 code_type = CODE_APE_PATCH; 2653 break; 2654 case BNX_DIR_TYPE_KONG_FW: 2655 code_type = CODE_KONG_FW; 2656 break; 2657 case BNX_DIR_TYPE_KONG_PATCH: 2658 code_type = CODE_KONG_PATCH; 2659 break; 2660 case BNX_DIR_TYPE_BONO_FW: 2661 code_type = CODE_BONO_FW; 2662 break; 2663 case BNX_DIR_TYPE_BONO_PATCH: 2664 code_type = CODE_BONO_PATCH; 2665 break; 2666 default: 2667 netdev_err(dev, "Unsupported directory entry type: %u\n", 2668 dir_type); 2669 return -EINVAL; 2670 } 2671 if (fw_size < sizeof(struct bnxt_fw_header)) { 2672 netdev_err(dev, "Invalid firmware file size: %u\n", 2673 (unsigned int)fw_size); 2674 return -EINVAL; 2675 } 2676 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) { 2677 netdev_err(dev, "Invalid firmware signature: %08X\n", 2678 le32_to_cpu(header->signature)); 2679 return -EINVAL; 2680 } 2681 if (header->code_type != code_type) { 2682 netdev_err(dev, "Expected firmware type: %d, read: %d\n", 2683 code_type, header->code_type); 2684 return -EINVAL; 2685 } 2686 if (header->device != DEVICE_CUMULUS_FAMILY) { 2687 netdev_err(dev, "Expected firmware device family %d, read: %d\n", 2688 DEVICE_CUMULUS_FAMILY, header->device); 2689 return -EINVAL; 2690 } 2691 /* Confirm the CRC32 checksum of the file: */ 2692 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2693 sizeof(stored_crc))); 2694 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2695 if (calculated_crc != stored_crc) { 2696 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n", 2697 (unsigned long)stored_crc, 2698 (unsigned long)calculated_crc); 2699 return -EINVAL; 2700 } 2701 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2702 0, 0, 0, fw_data, fw_size); 2703 if (rc == 0) /* Firmware update successful */ 2704 rc = bnxt_firmware_reset(dev, dir_type); 2705 2706 return rc; 2707 } 2708 2709 static int bnxt_flash_microcode(struct net_device *dev, 2710 u16 dir_type, 2711 const u8 *fw_data, 2712 size_t fw_size) 2713 { 2714 struct bnxt_ucode_trailer *trailer; 2715 u32 calculated_crc; 2716 u32 stored_crc; 2717 int rc = 0; 2718 2719 if (fw_size < sizeof(struct bnxt_ucode_trailer)) { 2720 netdev_err(dev, "Invalid microcode file size: %u\n", 2721 (unsigned int)fw_size); 2722 return -EINVAL; 2723 } 2724 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size - 2725 sizeof(*trailer))); 2726 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) { 2727 netdev_err(dev, "Invalid microcode trailer signature: %08X\n", 2728 le32_to_cpu(trailer->sig)); 2729 return -EINVAL; 2730 } 2731 if (le16_to_cpu(trailer->dir_type) != dir_type) { 2732 netdev_err(dev, "Expected microcode type: %d, read: %d\n", 2733 dir_type, le16_to_cpu(trailer->dir_type)); 2734 return -EINVAL; 2735 } 2736 if (le16_to_cpu(trailer->trailer_length) < 2737 sizeof(struct bnxt_ucode_trailer)) { 2738 netdev_err(dev, "Invalid microcode trailer length: %d\n", 2739 le16_to_cpu(trailer->trailer_length)); 2740 return -EINVAL; 2741 } 2742 2743 /* Confirm the CRC32 checksum of the file: */ 2744 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size - 2745 sizeof(stored_crc))); 2746 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc)); 2747 if (calculated_crc != stored_crc) { 2748 netdev_err(dev, 2749 "CRC32 (%08lX) does not match calculated: %08lX\n", 2750 (unsigned long)stored_crc, 2751 (unsigned long)calculated_crc); 2752 return -EINVAL; 2753 } 2754 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2755 0, 0, 0, fw_data, fw_size); 2756 2757 return rc; 2758 } 2759 2760 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type) 2761 { 2762 switch (dir_type) { 2763 case BNX_DIR_TYPE_CHIMP_PATCH: 2764 case BNX_DIR_TYPE_BOOTCODE: 2765 case BNX_DIR_TYPE_BOOTCODE_2: 2766 case BNX_DIR_TYPE_APE_FW: 2767 case BNX_DIR_TYPE_APE_PATCH: 2768 case BNX_DIR_TYPE_KONG_FW: 2769 case BNX_DIR_TYPE_KONG_PATCH: 2770 case BNX_DIR_TYPE_BONO_FW: 2771 case BNX_DIR_TYPE_BONO_PATCH: 2772 return true; 2773 } 2774 2775 return false; 2776 } 2777 2778 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type) 2779 { 2780 switch (dir_type) { 2781 case BNX_DIR_TYPE_AVS: 2782 case BNX_DIR_TYPE_EXP_ROM_MBA: 2783 case BNX_DIR_TYPE_PCIE: 2784 case BNX_DIR_TYPE_TSCF_UCODE: 2785 case BNX_DIR_TYPE_EXT_PHY: 2786 case BNX_DIR_TYPE_CCM: 2787 case BNX_DIR_TYPE_ISCSI_BOOT: 2788 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2789 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2790 return true; 2791 } 2792 2793 return false; 2794 } 2795 2796 static bool bnxt_dir_type_is_executable(u16 dir_type) 2797 { 2798 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2799 bnxt_dir_type_is_other_exec_format(dir_type); 2800 } 2801 2802 static int bnxt_flash_firmware_from_file(struct net_device *dev, 2803 u16 dir_type, 2804 const char *filename) 2805 { 2806 const struct firmware *fw; 2807 int rc; 2808 2809 rc = request_firmware(&fw, filename, &dev->dev); 2810 if (rc != 0) { 2811 netdev_err(dev, "Error %d requesting firmware file: %s\n", 2812 rc, filename); 2813 return rc; 2814 } 2815 if (bnxt_dir_type_is_ape_bin_format(dir_type)) 2816 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size); 2817 else if (bnxt_dir_type_is_other_exec_format(dir_type)) 2818 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size); 2819 else 2820 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST, 2821 0, 0, 0, fw->data, fw->size); 2822 release_firmware(fw); 2823 return rc; 2824 } 2825 2826 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM" 2827 #define MSG_INVALID_PKG "PKG install error : Invalid package" 2828 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error" 2829 #define MSG_INVALID_DEV "PKG install error : Invalid device" 2830 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 2831 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 2832 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 2833 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 2834 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 2835 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 2836 2837 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result, 2838 struct netlink_ext_ack *extack) 2839 { 2840 switch (result) { 2841 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER: 2842 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER: 2843 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR: 2844 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR: 2845 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND: 2846 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED: 2847 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR); 2848 return -EINVAL; 2849 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE: 2850 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER: 2851 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE: 2852 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM: 2853 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH: 2854 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST: 2855 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER: 2856 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM: 2857 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM: 2858 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH: 2859 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE: 2860 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM: 2861 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM: 2862 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG); 2863 return -ENOPKG; 2864 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR: 2865 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR); 2866 return -EPERM; 2867 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV: 2868 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID: 2869 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR: 2870 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID: 2871 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM: 2872 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV); 2873 return -EOPNOTSUPP; 2874 default: 2875 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR); 2876 return -EIO; 2877 } 2878 } 2879 2880 #define BNXT_PKG_DMA_SIZE 0x40000 2881 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 2882 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 2883 2884 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 2885 struct netlink_ext_ack *extack) 2886 { 2887 u32 item_len; 2888 int rc; 2889 2890 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2891 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 2892 &item_len, NULL); 2893 if (rc) { 2894 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 2895 return rc; 2896 } 2897 2898 if (fw_size > item_len) { 2899 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 2900 BNX_DIR_ORDINAL_FIRST, 0, 1, 2901 round_up(fw_size, 4096), NULL, 0); 2902 if (rc) { 2903 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 2904 return rc; 2905 } 2906 } 2907 return 0; 2908 } 2909 2910 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 2911 u32 install_type, struct netlink_ext_ack *extack) 2912 { 2913 struct hwrm_nvm_install_update_input *install; 2914 struct hwrm_nvm_install_update_output *resp; 2915 struct hwrm_nvm_modify_input *modify; 2916 struct bnxt *bp = netdev_priv(dev); 2917 bool defrag_attempted = false; 2918 dma_addr_t dma_handle; 2919 u8 *kmem = NULL; 2920 u32 modify_len; 2921 u32 item_len; 2922 u8 cmd_err; 2923 u16 index; 2924 int rc; 2925 2926 /* resize before flashing larger image than available space */ 2927 rc = bnxt_resize_update_entry(dev, fw->size, extack); 2928 if (rc) 2929 return rc; 2930 2931 bnxt_hwrm_fw_set_time(bp); 2932 2933 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY); 2934 if (rc) 2935 return rc; 2936 2937 /* Try allocating a large DMA buffer first. Older fw will 2938 * cause excessive NVRAM erases when using small blocks. 2939 */ 2940 modify_len = roundup_pow_of_two(fw->size); 2941 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE); 2942 while (1) { 2943 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle); 2944 if (!kmem && modify_len > PAGE_SIZE) 2945 modify_len /= 2; 2946 else 2947 break; 2948 } 2949 if (!kmem) { 2950 hwrm_req_drop(bp, modify); 2951 return -ENOMEM; 2952 } 2953 2954 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE); 2955 if (rc) { 2956 hwrm_req_drop(bp, modify); 2957 return rc; 2958 } 2959 2960 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout); 2961 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout); 2962 2963 hwrm_req_hold(bp, modify); 2964 modify->host_src_addr = cpu_to_le64(dma_handle); 2965 2966 resp = hwrm_req_hold(bp, install); 2967 if ((install_type & 0xffff) == 0) 2968 install_type >>= 16; 2969 install->install_type = cpu_to_le32(install_type); 2970 2971 do { 2972 u32 copied = 0, len = modify_len; 2973 2974 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2975 BNX_DIR_ORDINAL_FIRST, 2976 BNX_DIR_EXT_NONE, 2977 &index, &item_len, NULL); 2978 if (rc) { 2979 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 2980 break; 2981 } 2982 if (fw->size > item_len) { 2983 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR); 2984 rc = -EFBIG; 2985 break; 2986 } 2987 2988 modify->dir_idx = cpu_to_le16(index); 2989 2990 if (fw->size > modify_len) 2991 modify->flags = BNXT_NVM_MORE_FLAG; 2992 while (copied < fw->size) { 2993 u32 balance = fw->size - copied; 2994 2995 if (balance <= modify_len) { 2996 len = balance; 2997 if (copied) 2998 modify->flags |= BNXT_NVM_LAST_FLAG; 2999 } 3000 memcpy(kmem, fw->data + copied, len); 3001 modify->len = cpu_to_le32(len); 3002 modify->offset = cpu_to_le32(copied); 3003 rc = hwrm_req_send(bp, modify); 3004 if (rc) 3005 goto pkg_abort; 3006 copied += len; 3007 } 3008 3009 rc = hwrm_req_send_silent(bp, install); 3010 if (!rc) 3011 break; 3012 3013 if (defrag_attempted) { 3014 /* We have tried to defragment already in the previous 3015 * iteration. Return with the result for INSTALL_UPDATE 3016 */ 3017 break; 3018 } 3019 3020 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3021 3022 switch (cmd_err) { 3023 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK: 3024 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR); 3025 rc = -EALREADY; 3026 break; 3027 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR: 3028 install->flags = 3029 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG); 3030 3031 rc = hwrm_req_send_silent(bp, install); 3032 if (!rc) 3033 break; 3034 3035 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err; 3036 3037 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) { 3038 /* FW has cleared NVM area, driver will create 3039 * UPDATE directory and try the flash again 3040 */ 3041 defrag_attempted = true; 3042 install->flags = 0; 3043 rc = bnxt_flash_nvram(bp->dev, 3044 BNX_DIR_TYPE_UPDATE, 3045 BNX_DIR_ORDINAL_FIRST, 3046 0, 0, item_len, NULL, 0); 3047 if (!rc) 3048 break; 3049 } 3050 fallthrough; 3051 default: 3052 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR); 3053 } 3054 } while (defrag_attempted && !rc); 3055 3056 pkg_abort: 3057 hwrm_req_drop(bp, modify); 3058 hwrm_req_drop(bp, install); 3059 3060 if (resp->result) { 3061 netdev_err(dev, "PKG install error = %d, problem_item = %d\n", 3062 (s8)resp->result, (int)resp->problem_item); 3063 rc = nvm_update_err_to_stderr(dev, resp->result, extack); 3064 } 3065 if (rc == -EACCES) 3066 bnxt_print_admin_err(bp); 3067 return rc; 3068 } 3069 3070 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename, 3071 u32 install_type, struct netlink_ext_ack *extack) 3072 { 3073 const struct firmware *fw; 3074 int rc; 3075 3076 rc = request_firmware(&fw, filename, &dev->dev); 3077 if (rc != 0) { 3078 netdev_err(dev, "PKG error %d requesting file: %s\n", 3079 rc, filename); 3080 return rc; 3081 } 3082 3083 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack); 3084 3085 release_firmware(fw); 3086 3087 return rc; 3088 } 3089 3090 static int bnxt_flash_device(struct net_device *dev, 3091 struct ethtool_flash *flash) 3092 { 3093 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) { 3094 netdev_err(dev, "flashdev not supported from a virtual function\n"); 3095 return -EINVAL; 3096 } 3097 3098 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS || 3099 flash->region > 0xffff) 3100 return bnxt_flash_package_from_file(dev, flash->data, 3101 flash->region, NULL); 3102 3103 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data); 3104 } 3105 3106 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length) 3107 { 3108 struct hwrm_nvm_get_dir_info_output *output; 3109 struct hwrm_nvm_get_dir_info_input *req; 3110 struct bnxt *bp = netdev_priv(dev); 3111 int rc; 3112 3113 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO); 3114 if (rc) 3115 return rc; 3116 3117 output = hwrm_req_hold(bp, req); 3118 rc = hwrm_req_send(bp, req); 3119 if (!rc) { 3120 *entries = le32_to_cpu(output->entries); 3121 *length = le32_to_cpu(output->entry_length); 3122 } 3123 hwrm_req_drop(bp, req); 3124 return rc; 3125 } 3126 3127 static int bnxt_get_eeprom_len(struct net_device *dev) 3128 { 3129 struct bnxt *bp = netdev_priv(dev); 3130 3131 if (BNXT_VF(bp)) 3132 return 0; 3133 3134 /* The -1 return value allows the entire 32-bit range of offsets to be 3135 * passed via the ethtool command-line utility. 3136 */ 3137 return -1; 3138 } 3139 3140 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data) 3141 { 3142 struct bnxt *bp = netdev_priv(dev); 3143 int rc; 3144 u32 dir_entries; 3145 u32 entry_length; 3146 u8 *buf; 3147 size_t buflen; 3148 dma_addr_t dma_handle; 3149 struct hwrm_nvm_get_dir_entries_input *req; 3150 3151 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length); 3152 if (rc != 0) 3153 return rc; 3154 3155 if (!dir_entries || !entry_length) 3156 return -EIO; 3157 3158 /* Insert 2 bytes of directory info (count and size of entries) */ 3159 if (len < 2) 3160 return -EINVAL; 3161 3162 *data++ = dir_entries; 3163 *data++ = entry_length; 3164 len -= 2; 3165 memset(data, 0xff, len); 3166 3167 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES); 3168 if (rc) 3169 return rc; 3170 3171 buflen = mul_u32_u32(dir_entries, entry_length); 3172 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle); 3173 if (!buf) { 3174 hwrm_req_drop(bp, req); 3175 return -ENOMEM; 3176 } 3177 req->host_dest_addr = cpu_to_le64(dma_handle); 3178 3179 hwrm_req_hold(bp, req); /* hold the slice */ 3180 rc = hwrm_req_send(bp, req); 3181 if (rc == 0) 3182 memcpy(data, buf, len > buflen ? buflen : len); 3183 hwrm_req_drop(bp, req); 3184 return rc; 3185 } 3186 3187 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset, 3188 u32 length, u8 *data) 3189 { 3190 struct bnxt *bp = netdev_priv(dev); 3191 int rc; 3192 u8 *buf; 3193 dma_addr_t dma_handle; 3194 struct hwrm_nvm_read_input *req; 3195 3196 if (!length) 3197 return -EINVAL; 3198 3199 rc = hwrm_req_init(bp, req, HWRM_NVM_READ); 3200 if (rc) 3201 return rc; 3202 3203 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle); 3204 if (!buf) { 3205 hwrm_req_drop(bp, req); 3206 return -ENOMEM; 3207 } 3208 3209 req->host_dest_addr = cpu_to_le64(dma_handle); 3210 req->dir_idx = cpu_to_le16(index); 3211 req->offset = cpu_to_le32(offset); 3212 req->len = cpu_to_le32(length); 3213 3214 hwrm_req_hold(bp, req); /* hold the slice */ 3215 rc = hwrm_req_send(bp, req); 3216 if (rc == 0) 3217 memcpy(data, buf, length); 3218 hwrm_req_drop(bp, req); 3219 return rc; 3220 } 3221 3222 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal, 3223 u16 ext, u16 *index, u32 *item_length, 3224 u32 *data_length) 3225 { 3226 struct hwrm_nvm_find_dir_entry_output *output; 3227 struct hwrm_nvm_find_dir_entry_input *req; 3228 struct bnxt *bp = netdev_priv(dev); 3229 int rc; 3230 3231 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY); 3232 if (rc) 3233 return rc; 3234 3235 req->enables = 0; 3236 req->dir_idx = 0; 3237 req->dir_type = cpu_to_le16(type); 3238 req->dir_ordinal = cpu_to_le16(ordinal); 3239 req->dir_ext = cpu_to_le16(ext); 3240 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ; 3241 output = hwrm_req_hold(bp, req); 3242 rc = hwrm_req_send_silent(bp, req); 3243 if (rc == 0) { 3244 if (index) 3245 *index = le16_to_cpu(output->dir_idx); 3246 if (item_length) 3247 *item_length = le32_to_cpu(output->dir_item_length); 3248 if (data_length) 3249 *data_length = le32_to_cpu(output->dir_data_length); 3250 } 3251 hwrm_req_drop(bp, req); 3252 return rc; 3253 } 3254 3255 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen) 3256 { 3257 char *retval = NULL; 3258 char *p; 3259 char *value; 3260 int field = 0; 3261 3262 if (datalen < 1) 3263 return NULL; 3264 /* null-terminate the log data (removing last '\n'): */ 3265 data[datalen - 1] = 0; 3266 for (p = data; *p != 0; p++) { 3267 field = 0; 3268 retval = NULL; 3269 while (*p != 0 && *p != '\n') { 3270 value = p; 3271 while (*p != 0 && *p != '\t' && *p != '\n') 3272 p++; 3273 if (field == desired_field) 3274 retval = value; 3275 if (*p != '\t') 3276 break; 3277 *p = 0; 3278 field++; 3279 p++; 3280 } 3281 if (*p == 0) 3282 break; 3283 *p = 0; 3284 } 3285 return retval; 3286 } 3287 3288 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size) 3289 { 3290 struct bnxt *bp = netdev_priv(dev); 3291 u16 index = 0; 3292 char *pkgver; 3293 u32 pkglen; 3294 u8 *pkgbuf; 3295 int rc; 3296 3297 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG, 3298 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, 3299 &index, NULL, &pkglen); 3300 if (rc) 3301 return rc; 3302 3303 pkgbuf = kzalloc(pkglen, GFP_KERNEL); 3304 if (!pkgbuf) { 3305 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n", 3306 pkglen); 3307 return -ENOMEM; 3308 } 3309 3310 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf); 3311 if (rc) 3312 goto err; 3313 3314 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf, 3315 pkglen); 3316 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) 3317 strscpy(ver, pkgver, size); 3318 else 3319 rc = -ENOENT; 3320 3321 err: 3322 kfree(pkgbuf); 3323 3324 return rc; 3325 } 3326 3327 static void bnxt_get_pkgver(struct net_device *dev) 3328 { 3329 struct bnxt *bp = netdev_priv(dev); 3330 char buf[FW_VER_STR_LEN]; 3331 int len; 3332 3333 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) { 3334 len = strlen(bp->fw_ver_str); 3335 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1, 3336 "/pkg %s", buf); 3337 } 3338 } 3339 3340 static int bnxt_get_eeprom(struct net_device *dev, 3341 struct ethtool_eeprom *eeprom, 3342 u8 *data) 3343 { 3344 u32 index; 3345 u32 offset; 3346 3347 if (eeprom->offset == 0) /* special offset value to get directory */ 3348 return bnxt_get_nvram_directory(dev, eeprom->len, data); 3349 3350 index = eeprom->offset >> 24; 3351 offset = eeprom->offset & 0xffffff; 3352 3353 if (index == 0) { 3354 netdev_err(dev, "unsupported index value: %d\n", index); 3355 return -EINVAL; 3356 } 3357 3358 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data); 3359 } 3360 3361 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index) 3362 { 3363 struct hwrm_nvm_erase_dir_entry_input *req; 3364 struct bnxt *bp = netdev_priv(dev); 3365 int rc; 3366 3367 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY); 3368 if (rc) 3369 return rc; 3370 3371 req->dir_idx = cpu_to_le16(index); 3372 return hwrm_req_send(bp, req); 3373 } 3374 3375 static int bnxt_set_eeprom(struct net_device *dev, 3376 struct ethtool_eeprom *eeprom, 3377 u8 *data) 3378 { 3379 struct bnxt *bp = netdev_priv(dev); 3380 u8 index, dir_op; 3381 u16 type, ext, ordinal, attr; 3382 3383 if (!BNXT_PF(bp)) { 3384 netdev_err(dev, "NVM write not supported from a virtual function\n"); 3385 return -EINVAL; 3386 } 3387 3388 type = eeprom->magic >> 16; 3389 3390 if (type == 0xffff) { /* special value for directory operations */ 3391 index = eeprom->magic & 0xff; 3392 dir_op = eeprom->magic >> 8; 3393 if (index == 0) 3394 return -EINVAL; 3395 switch (dir_op) { 3396 case 0x0e: /* erase */ 3397 if (eeprom->offset != ~eeprom->magic) 3398 return -EINVAL; 3399 return bnxt_erase_nvram_directory(dev, index - 1); 3400 default: 3401 return -EINVAL; 3402 } 3403 } 3404 3405 /* Create or re-write an NVM item: */ 3406 if (bnxt_dir_type_is_executable(type)) 3407 return -EOPNOTSUPP; 3408 ext = eeprom->magic & 0xffff; 3409 ordinal = eeprom->offset >> 16; 3410 attr = eeprom->offset & 0xffff; 3411 3412 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data, 3413 eeprom->len); 3414 } 3415 3416 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata) 3417 { 3418 struct bnxt *bp = netdev_priv(dev); 3419 struct ethtool_eee *eee = &bp->eee; 3420 struct bnxt_link_info *link_info = &bp->link_info; 3421 u32 advertising; 3422 int rc = 0; 3423 3424 if (!BNXT_PHY_CFG_ABLE(bp)) 3425 return -EOPNOTSUPP; 3426 3427 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3428 return -EOPNOTSUPP; 3429 3430 mutex_lock(&bp->link_lock); 3431 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0); 3432 if (!edata->eee_enabled) 3433 goto eee_ok; 3434 3435 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { 3436 netdev_warn(dev, "EEE requires autoneg\n"); 3437 rc = -EINVAL; 3438 goto eee_exit; 3439 } 3440 if (edata->tx_lpi_enabled) { 3441 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi || 3442 edata->tx_lpi_timer < bp->lpi_tmr_lo)) { 3443 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n", 3444 bp->lpi_tmr_lo, bp->lpi_tmr_hi); 3445 rc = -EINVAL; 3446 goto eee_exit; 3447 } else if (!bp->lpi_tmr_hi) { 3448 edata->tx_lpi_timer = eee->tx_lpi_timer; 3449 } 3450 } 3451 if (!edata->advertised) { 3452 edata->advertised = advertising & eee->supported; 3453 } else if (edata->advertised & ~advertising) { 3454 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", 3455 edata->advertised, advertising); 3456 rc = -EINVAL; 3457 goto eee_exit; 3458 } 3459 3460 eee->advertised = edata->advertised; 3461 eee->tx_lpi_enabled = edata->tx_lpi_enabled; 3462 eee->tx_lpi_timer = edata->tx_lpi_timer; 3463 eee_ok: 3464 eee->eee_enabled = edata->eee_enabled; 3465 3466 if (netif_running(dev)) 3467 rc = bnxt_hwrm_set_link_setting(bp, false, true); 3468 3469 eee_exit: 3470 mutex_unlock(&bp->link_lock); 3471 return rc; 3472 } 3473 3474 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata) 3475 { 3476 struct bnxt *bp = netdev_priv(dev); 3477 3478 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP)) 3479 return -EOPNOTSUPP; 3480 3481 *edata = bp->eee; 3482 if (!bp->eee.eee_enabled) { 3483 /* Preserve tx_lpi_timer so that the last value will be used 3484 * by default when it is re-enabled. 3485 */ 3486 edata->advertised = 0; 3487 edata->tx_lpi_enabled = 0; 3488 } 3489 3490 if (!bp->eee.eee_active) 3491 edata->lp_advertised = 0; 3492 3493 return 0; 3494 } 3495 3496 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 3497 u16 page_number, u8 bank, 3498 u16 start_addr, u16 data_length, 3499 u8 *buf) 3500 { 3501 struct hwrm_port_phy_i2c_read_output *output; 3502 struct hwrm_port_phy_i2c_read_input *req; 3503 int rc, byte_offset = 0; 3504 3505 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ); 3506 if (rc) 3507 return rc; 3508 3509 output = hwrm_req_hold(bp, req); 3510 req->i2c_slave_addr = i2c_addr; 3511 req->page_number = cpu_to_le16(page_number); 3512 req->port_id = cpu_to_le16(bp->pf.port_id); 3513 do { 3514 u16 xfer_size; 3515 3516 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE); 3517 data_length -= xfer_size; 3518 req->page_offset = cpu_to_le16(start_addr + byte_offset); 3519 req->data_length = xfer_size; 3520 req->enables = 3521 cpu_to_le32((start_addr + byte_offset ? 3522 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 3523 0) | 3524 (bank ? 3525 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 3526 0)); 3527 rc = hwrm_req_send(bp, req); 3528 if (!rc) 3529 memcpy(buf + byte_offset, output->data, xfer_size); 3530 byte_offset += xfer_size; 3531 } while (!rc && data_length > 0); 3532 hwrm_req_drop(bp, req); 3533 3534 return rc; 3535 } 3536 3537 static int bnxt_get_module_info(struct net_device *dev, 3538 struct ethtool_modinfo *modinfo) 3539 { 3540 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1]; 3541 struct bnxt *bp = netdev_priv(dev); 3542 int rc; 3543 3544 /* No point in going further if phy status indicates 3545 * module is not inserted or if it is powered down or 3546 * if it is of type 10GBase-T 3547 */ 3548 if (bp->link_info.module_status > 3549 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3550 return -EOPNOTSUPP; 3551 3552 /* This feature is not supported in older firmware versions */ 3553 if (bp->hwrm_spec_code < 0x10202) 3554 return -EOPNOTSUPP; 3555 3556 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 3557 SFF_DIAG_SUPPORT_OFFSET + 1, 3558 data); 3559 if (!rc) { 3560 u8 module_id = data[0]; 3561 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET]; 3562 3563 switch (module_id) { 3564 case SFF_MODULE_ID_SFP: 3565 modinfo->type = ETH_MODULE_SFF_8472; 3566 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3567 if (!diag_supported) 3568 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3569 break; 3570 case SFF_MODULE_ID_QSFP: 3571 case SFF_MODULE_ID_QSFP_PLUS: 3572 modinfo->type = ETH_MODULE_SFF_8436; 3573 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 3574 break; 3575 case SFF_MODULE_ID_QSFP28: 3576 modinfo->type = ETH_MODULE_SFF_8636; 3577 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 3578 break; 3579 default: 3580 rc = -EOPNOTSUPP; 3581 break; 3582 } 3583 } 3584 return rc; 3585 } 3586 3587 static int bnxt_get_module_eeprom(struct net_device *dev, 3588 struct ethtool_eeprom *eeprom, 3589 u8 *data) 3590 { 3591 struct bnxt *bp = netdev_priv(dev); 3592 u16 start = eeprom->offset, length = eeprom->len; 3593 int rc = 0; 3594 3595 memset(data, 0, eeprom->len); 3596 3597 /* Read A0 portion of the EEPROM */ 3598 if (start < ETH_MODULE_SFF_8436_LEN) { 3599 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 3600 length = ETH_MODULE_SFF_8436_LEN - start; 3601 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3602 start, length, data); 3603 if (rc) 3604 return rc; 3605 start += length; 3606 data += length; 3607 length = eeprom->len - length; 3608 } 3609 3610 /* Read A2 portion of the EEPROM */ 3611 if (length) { 3612 start -= ETH_MODULE_SFF_8436_LEN; 3613 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 3614 start, length, data); 3615 } 3616 return rc; 3617 } 3618 3619 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 3620 { 3621 if (bp->link_info.module_status <= 3622 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3623 return 0; 3624 3625 switch (bp->link_info.module_status) { 3626 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 3627 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 3628 break; 3629 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 3630 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 3631 break; 3632 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 3633 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 3634 break; 3635 default: 3636 NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 3637 break; 3638 } 3639 return -EINVAL; 3640 } 3641 3642 static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 3643 const struct ethtool_module_eeprom *page_data, 3644 struct netlink_ext_ack *extack) 3645 { 3646 struct bnxt *bp = netdev_priv(dev); 3647 int rc; 3648 3649 rc = bnxt_get_module_status(bp, extack); 3650 if (rc) 3651 return rc; 3652 3653 if (bp->hwrm_spec_code < 0x10202) { 3654 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 3655 return -EINVAL; 3656 } 3657 3658 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 3659 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 3660 return -EINVAL; 3661 } 3662 3663 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 3664 page_data->page, page_data->bank, 3665 page_data->offset, 3666 page_data->length, 3667 page_data->data); 3668 if (rc) { 3669 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 3670 return rc; 3671 } 3672 return page_data->length; 3673 } 3674 3675 static int bnxt_nway_reset(struct net_device *dev) 3676 { 3677 int rc = 0; 3678 3679 struct bnxt *bp = netdev_priv(dev); 3680 struct bnxt_link_info *link_info = &bp->link_info; 3681 3682 if (!BNXT_PHY_CFG_ABLE(bp)) 3683 return -EOPNOTSUPP; 3684 3685 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) 3686 return -EINVAL; 3687 3688 if (netif_running(dev)) 3689 rc = bnxt_hwrm_set_link_setting(bp, true, false); 3690 3691 return rc; 3692 } 3693 3694 static int bnxt_set_phys_id(struct net_device *dev, 3695 enum ethtool_phys_id_state state) 3696 { 3697 struct hwrm_port_led_cfg_input *req; 3698 struct bnxt *bp = netdev_priv(dev); 3699 struct bnxt_pf_info *pf = &bp->pf; 3700 struct bnxt_led_cfg *led_cfg; 3701 u8 led_state; 3702 __le16 duration; 3703 int rc, i; 3704 3705 if (!bp->num_leds || BNXT_VF(bp)) 3706 return -EOPNOTSUPP; 3707 3708 if (state == ETHTOOL_ID_ACTIVE) { 3709 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT; 3710 duration = cpu_to_le16(500); 3711 } else if (state == ETHTOOL_ID_INACTIVE) { 3712 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT; 3713 duration = cpu_to_le16(0); 3714 } else { 3715 return -EINVAL; 3716 } 3717 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG); 3718 if (rc) 3719 return rc; 3720 3721 req->port_id = cpu_to_le16(pf->port_id); 3722 req->num_leds = bp->num_leds; 3723 led_cfg = (struct bnxt_led_cfg *)&req->led0_id; 3724 for (i = 0; i < bp->num_leds; i++, led_cfg++) { 3725 req->enables |= BNXT_LED_DFLT_ENABLES(i); 3726 led_cfg->led_id = bp->leds[i].led_id; 3727 led_cfg->led_state = led_state; 3728 led_cfg->led_blink_on = duration; 3729 led_cfg->led_blink_off = duration; 3730 led_cfg->led_group_id = bp->leds[i].led_group_id; 3731 } 3732 return hwrm_req_send(bp, req); 3733 } 3734 3735 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring) 3736 { 3737 struct hwrm_selftest_irq_input *req; 3738 int rc; 3739 3740 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ); 3741 if (rc) 3742 return rc; 3743 3744 req->cmpl_ring = cpu_to_le16(cmpl_ring); 3745 return hwrm_req_send(bp, req); 3746 } 3747 3748 static int bnxt_test_irq(struct bnxt *bp) 3749 { 3750 int i; 3751 3752 for (i = 0; i < bp->cp_nr_rings; i++) { 3753 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id; 3754 int rc; 3755 3756 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring); 3757 if (rc) 3758 return rc; 3759 } 3760 return 0; 3761 } 3762 3763 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable) 3764 { 3765 struct hwrm_port_mac_cfg_input *req; 3766 int rc; 3767 3768 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG); 3769 if (rc) 3770 return rc; 3771 3772 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK); 3773 if (enable) 3774 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL; 3775 else 3776 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE; 3777 return hwrm_req_send(bp, req); 3778 } 3779 3780 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds) 3781 { 3782 struct hwrm_port_phy_qcaps_output *resp; 3783 struct hwrm_port_phy_qcaps_input *req; 3784 int rc; 3785 3786 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS); 3787 if (rc) 3788 return rc; 3789 3790 resp = hwrm_req_hold(bp, req); 3791 rc = hwrm_req_send(bp, req); 3792 if (!rc) 3793 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode); 3794 3795 hwrm_req_drop(bp, req); 3796 return rc; 3797 } 3798 3799 static int bnxt_disable_an_for_lpbk(struct bnxt *bp, 3800 struct hwrm_port_phy_cfg_input *req) 3801 { 3802 struct bnxt_link_info *link_info = &bp->link_info; 3803 u16 fw_advertising; 3804 u16 fw_speed; 3805 int rc; 3806 3807 if (!link_info->autoneg || 3808 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK)) 3809 return 0; 3810 3811 rc = bnxt_query_force_speeds(bp, &fw_advertising); 3812 if (rc) 3813 return rc; 3814 3815 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB; 3816 if (BNXT_LINK_IS_UP(bp)) 3817 fw_speed = bp->link_info.link_speed; 3818 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB) 3819 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB; 3820 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB) 3821 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB; 3822 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB) 3823 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB; 3824 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB) 3825 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB; 3826 3827 req->force_link_speed = cpu_to_le16(fw_speed); 3828 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE | 3829 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); 3830 rc = hwrm_req_send(bp, req); 3831 req->flags = 0; 3832 req->force_link_speed = cpu_to_le16(0); 3833 return rc; 3834 } 3835 3836 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext) 3837 { 3838 struct hwrm_port_phy_cfg_input *req; 3839 int rc; 3840 3841 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG); 3842 if (rc) 3843 return rc; 3844 3845 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */ 3846 hwrm_req_hold(bp, req); 3847 3848 if (enable) { 3849 bnxt_disable_an_for_lpbk(bp, req); 3850 if (ext) 3851 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL; 3852 else 3853 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL; 3854 } else { 3855 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE; 3856 } 3857 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK); 3858 rc = hwrm_req_send(bp, req); 3859 hwrm_req_drop(bp, req); 3860 return rc; 3861 } 3862 3863 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3864 u32 raw_cons, int pkt_size) 3865 { 3866 struct bnxt_napi *bnapi = cpr->bnapi; 3867 struct bnxt_rx_ring_info *rxr; 3868 struct bnxt_sw_rx_bd *rx_buf; 3869 struct rx_cmp *rxcmp; 3870 u16 cp_cons, cons; 3871 u8 *data; 3872 u32 len; 3873 int i; 3874 3875 rxr = bnapi->rx_ring; 3876 cp_cons = RING_CMP(raw_cons); 3877 rxcmp = (struct rx_cmp *) 3878 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; 3879 cons = rxcmp->rx_cmp_opaque; 3880 rx_buf = &rxr->rx_buf_ring[cons]; 3881 data = rx_buf->data_ptr; 3882 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; 3883 if (len != pkt_size) 3884 return -EIO; 3885 i = ETH_ALEN; 3886 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr)) 3887 return -EIO; 3888 i += ETH_ALEN; 3889 for ( ; i < pkt_size; i++) { 3890 if (data[i] != (u8)(i & 0xff)) 3891 return -EIO; 3892 } 3893 return 0; 3894 } 3895 3896 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, 3897 int pkt_size) 3898 { 3899 struct tx_cmp *txcmp; 3900 int rc = -EIO; 3901 u32 raw_cons; 3902 u32 cons; 3903 int i; 3904 3905 raw_cons = cpr->cp_raw_cons; 3906 for (i = 0; i < 200; i++) { 3907 cons = RING_CMP(raw_cons); 3908 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; 3909 3910 if (!TX_CMP_VALID(txcmp, raw_cons)) { 3911 udelay(5); 3912 continue; 3913 } 3914 3915 /* The valid test of the entry must be done first before 3916 * reading any further. 3917 */ 3918 dma_rmb(); 3919 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) { 3920 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size); 3921 raw_cons = NEXT_RAW_CMP(raw_cons); 3922 raw_cons = NEXT_RAW_CMP(raw_cons); 3923 break; 3924 } 3925 raw_cons = NEXT_RAW_CMP(raw_cons); 3926 } 3927 cpr->cp_raw_cons = raw_cons; 3928 return rc; 3929 } 3930 3931 static int bnxt_run_loopback(struct bnxt *bp) 3932 { 3933 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0]; 3934 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0]; 3935 struct bnxt_cp_ring_info *cpr; 3936 int pkt_size, i = 0; 3937 struct sk_buff *skb; 3938 dma_addr_t map; 3939 u8 *data; 3940 int rc; 3941 3942 cpr = &rxr->bnapi->cp_ring; 3943 if (bp->flags & BNXT_FLAG_CHIP_P5) 3944 cpr = cpr->cp_ring_arr[BNXT_RX_HDL]; 3945 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh); 3946 skb = netdev_alloc_skb(bp->dev, pkt_size); 3947 if (!skb) 3948 return -ENOMEM; 3949 data = skb_put(skb, pkt_size); 3950 ether_addr_copy(&data[i], bp->dev->dev_addr); 3951 i += ETH_ALEN; 3952 ether_addr_copy(&data[i], bp->dev->dev_addr); 3953 i += ETH_ALEN; 3954 for ( ; i < pkt_size; i++) 3955 data[i] = (u8)(i & 0xff); 3956 3957 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 3958 DMA_TO_DEVICE); 3959 if (dma_mapping_error(&bp->pdev->dev, map)) { 3960 dev_kfree_skb(skb); 3961 return -EIO; 3962 } 3963 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL); 3964 3965 /* Sync BD data before updating doorbell */ 3966 wmb(); 3967 3968 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod); 3969 rc = bnxt_poll_loopback(bp, cpr, pkt_size); 3970 3971 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 3972 dev_kfree_skb(skb); 3973 return rc; 3974 } 3975 3976 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results) 3977 { 3978 struct hwrm_selftest_exec_output *resp; 3979 struct hwrm_selftest_exec_input *req; 3980 int rc; 3981 3982 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC); 3983 if (rc) 3984 return rc; 3985 3986 hwrm_req_timeout(bp, req, bp->test_info->timeout); 3987 req->flags = test_mask; 3988 3989 resp = hwrm_req_hold(bp, req); 3990 rc = hwrm_req_send(bp, req); 3991 *test_results = resp->test_success; 3992 hwrm_req_drop(bp, req); 3993 return rc; 3994 } 3995 3996 #define BNXT_DRV_TESTS 4 3997 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS) 3998 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1) 3999 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2) 4000 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3) 4001 4002 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest, 4003 u64 *buf) 4004 { 4005 struct bnxt *bp = netdev_priv(dev); 4006 bool do_ext_lpbk = false; 4007 bool offline = false; 4008 u8 test_results = 0; 4009 u8 test_mask = 0; 4010 int rc = 0, i; 4011 4012 if (!bp->num_tests || !BNXT_PF(bp)) 4013 return; 4014 memset(buf, 0, sizeof(u64) * bp->num_tests); 4015 if (!netif_running(dev)) { 4016 etest->flags |= ETH_TEST_FL_FAILED; 4017 return; 4018 } 4019 4020 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) && 4021 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK)) 4022 do_ext_lpbk = true; 4023 4024 if (etest->flags & ETH_TEST_FL_OFFLINE) { 4025 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) { 4026 etest->flags |= ETH_TEST_FL_FAILED; 4027 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n"); 4028 return; 4029 } 4030 offline = true; 4031 } 4032 4033 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4034 u8 bit_val = 1 << i; 4035 4036 if (!(bp->test_info->offline_mask & bit_val)) 4037 test_mask |= bit_val; 4038 else if (offline) 4039 test_mask |= bit_val; 4040 } 4041 if (!offline) { 4042 bnxt_run_fw_tests(bp, test_mask, &test_results); 4043 } else { 4044 bnxt_ulp_stop(bp); 4045 rc = bnxt_close_nic(bp, true, false); 4046 if (rc) { 4047 etest->flags |= ETH_TEST_FL_FAILED; 4048 bnxt_ulp_start(bp, rc); 4049 return; 4050 } 4051 bnxt_run_fw_tests(bp, test_mask, &test_results); 4052 4053 buf[BNXT_MACLPBK_TEST_IDX] = 1; 4054 bnxt_hwrm_mac_loopback(bp, true); 4055 msleep(250); 4056 rc = bnxt_half_open_nic(bp); 4057 if (rc) { 4058 bnxt_hwrm_mac_loopback(bp, false); 4059 etest->flags |= ETH_TEST_FL_FAILED; 4060 bnxt_ulp_start(bp, rc); 4061 return; 4062 } 4063 if (bnxt_run_loopback(bp)) 4064 etest->flags |= ETH_TEST_FL_FAILED; 4065 else 4066 buf[BNXT_MACLPBK_TEST_IDX] = 0; 4067 4068 bnxt_hwrm_mac_loopback(bp, false); 4069 bnxt_hwrm_phy_loopback(bp, true, false); 4070 msleep(1000); 4071 if (bnxt_run_loopback(bp)) { 4072 buf[BNXT_PHYLPBK_TEST_IDX] = 1; 4073 etest->flags |= ETH_TEST_FL_FAILED; 4074 } 4075 if (do_ext_lpbk) { 4076 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 4077 bnxt_hwrm_phy_loopback(bp, true, true); 4078 msleep(1000); 4079 if (bnxt_run_loopback(bp)) { 4080 buf[BNXT_EXTLPBK_TEST_IDX] = 1; 4081 etest->flags |= ETH_TEST_FL_FAILED; 4082 } 4083 } 4084 bnxt_hwrm_phy_loopback(bp, false, false); 4085 bnxt_half_close_nic(bp); 4086 rc = bnxt_open_nic(bp, true, true); 4087 bnxt_ulp_start(bp, rc); 4088 } 4089 if (rc || bnxt_test_irq(bp)) { 4090 buf[BNXT_IRQ_TEST_IDX] = 1; 4091 etest->flags |= ETH_TEST_FL_FAILED; 4092 } 4093 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) { 4094 u8 bit_val = 1 << i; 4095 4096 if ((test_mask & bit_val) && !(test_results & bit_val)) { 4097 buf[i] = 1; 4098 etest->flags |= ETH_TEST_FL_FAILED; 4099 } 4100 } 4101 } 4102 4103 static int bnxt_reset(struct net_device *dev, u32 *flags) 4104 { 4105 struct bnxt *bp = netdev_priv(dev); 4106 bool reload = false; 4107 u32 req = *flags; 4108 4109 if (!req) 4110 return -EINVAL; 4111 4112 if (!BNXT_PF(bp)) { 4113 netdev_err(dev, "Reset is not supported from a VF\n"); 4114 return -EOPNOTSUPP; 4115 } 4116 4117 if (pci_vfs_assigned(bp->pdev) && 4118 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) { 4119 netdev_err(dev, 4120 "Reset not allowed when VFs are assigned to VMs\n"); 4121 return -EBUSY; 4122 } 4123 4124 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) { 4125 /* This feature is not supported in older firmware versions */ 4126 if (bp->hwrm_spec_code >= 0x10803) { 4127 if (!bnxt_firmware_reset_chip(dev)) { 4128 netdev_info(dev, "Firmware reset request successful.\n"); 4129 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) 4130 reload = true; 4131 *flags &= ~BNXT_FW_RESET_CHIP; 4132 } 4133 } else if (req == BNXT_FW_RESET_CHIP) { 4134 return -EOPNOTSUPP; /* only request, fail hard */ 4135 } 4136 } 4137 4138 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) { 4139 /* This feature is not supported in older firmware versions */ 4140 if (bp->hwrm_spec_code >= 0x10803) { 4141 if (!bnxt_firmware_reset_ap(dev)) { 4142 netdev_info(dev, "Reset application processor successful.\n"); 4143 reload = true; 4144 *flags &= ~BNXT_FW_RESET_AP; 4145 } 4146 } else if (req == BNXT_FW_RESET_AP) { 4147 return -EOPNOTSUPP; /* only request, fail hard */ 4148 } 4149 } 4150 4151 if (reload) 4152 netdev_info(dev, "Reload driver to complete reset\n"); 4153 4154 return 0; 4155 } 4156 4157 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump) 4158 { 4159 struct bnxt *bp = netdev_priv(dev); 4160 4161 if (dump->flag > BNXT_DUMP_CRASH) { 4162 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n"); 4163 return -EINVAL; 4164 } 4165 4166 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) { 4167 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n"); 4168 return -EOPNOTSUPP; 4169 } 4170 4171 bp->dump_flag = dump->flag; 4172 return 0; 4173 } 4174 4175 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump) 4176 { 4177 struct bnxt *bp = netdev_priv(dev); 4178 4179 if (bp->hwrm_spec_code < 0x10801) 4180 return -EOPNOTSUPP; 4181 4182 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 | 4183 bp->ver_resp.hwrm_fw_min_8b << 16 | 4184 bp->ver_resp.hwrm_fw_bld_8b << 8 | 4185 bp->ver_resp.hwrm_fw_rsvd_8b; 4186 4187 dump->flag = bp->dump_flag; 4188 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag); 4189 return 0; 4190 } 4191 4192 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump, 4193 void *buf) 4194 { 4195 struct bnxt *bp = netdev_priv(dev); 4196 4197 if (bp->hwrm_spec_code < 0x10801) 4198 return -EOPNOTSUPP; 4199 4200 memset(buf, 0, dump->len); 4201 4202 dump->flag = bp->dump_flag; 4203 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len); 4204 } 4205 4206 static int bnxt_get_ts_info(struct net_device *dev, 4207 struct ethtool_ts_info *info) 4208 { 4209 struct bnxt *bp = netdev_priv(dev); 4210 struct bnxt_ptp_cfg *ptp; 4211 4212 ptp = bp->ptp_cfg; 4213 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 4214 SOF_TIMESTAMPING_RX_SOFTWARE | 4215 SOF_TIMESTAMPING_SOFTWARE; 4216 4217 info->phc_index = -1; 4218 if (!ptp) 4219 return 0; 4220 4221 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | 4222 SOF_TIMESTAMPING_RX_HARDWARE | 4223 SOF_TIMESTAMPING_RAW_HARDWARE; 4224 if (ptp->ptp_clock) 4225 info->phc_index = ptp_clock_index(ptp->ptp_clock); 4226 4227 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 4228 4229 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 4230 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 4231 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 4232 4233 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) 4234 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL); 4235 return 0; 4236 } 4237 4238 void bnxt_ethtool_init(struct bnxt *bp) 4239 { 4240 struct hwrm_selftest_qlist_output *resp; 4241 struct hwrm_selftest_qlist_input *req; 4242 struct bnxt_test_info *test_info; 4243 struct net_device *dev = bp->dev; 4244 int i, rc; 4245 4246 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER)) 4247 bnxt_get_pkgver(dev); 4248 4249 bp->num_tests = 0; 4250 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp)) 4251 return; 4252 4253 test_info = bp->test_info; 4254 if (!test_info) { 4255 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL); 4256 if (!test_info) 4257 return; 4258 bp->test_info = test_info; 4259 } 4260 4261 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST)) 4262 return; 4263 4264 resp = hwrm_req_hold(bp, req); 4265 rc = hwrm_req_send_silent(bp, req); 4266 if (rc) 4267 goto ethtool_init_exit; 4268 4269 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS; 4270 if (bp->num_tests > BNXT_MAX_TEST) 4271 bp->num_tests = BNXT_MAX_TEST; 4272 4273 test_info->offline_mask = resp->offline_tests; 4274 test_info->timeout = le16_to_cpu(resp->test_timeout); 4275 if (!test_info->timeout) 4276 test_info->timeout = HWRM_CMD_TIMEOUT; 4277 for (i = 0; i < bp->num_tests; i++) { 4278 char *str = test_info->string[i]; 4279 char *fw_str = resp->test_name[i]; 4280 4281 if (i == BNXT_MACLPBK_TEST_IDX) { 4282 strcpy(str, "Mac loopback test (offline)"); 4283 } else if (i == BNXT_PHYLPBK_TEST_IDX) { 4284 strcpy(str, "Phy loopback test (offline)"); 4285 } else if (i == BNXT_EXTLPBK_TEST_IDX) { 4286 strcpy(str, "Ext loopback test (offline)"); 4287 } else if (i == BNXT_IRQ_TEST_IDX) { 4288 strcpy(str, "Interrupt_test (offline)"); 4289 } else { 4290 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)", 4291 fw_str, test_info->offline_mask & (1 << i) ? 4292 "offline" : "online"); 4293 } 4294 } 4295 4296 ethtool_init_exit: 4297 hwrm_req_drop(bp, req); 4298 } 4299 4300 static void bnxt_get_eth_phy_stats(struct net_device *dev, 4301 struct ethtool_eth_phy_stats *phy_stats) 4302 { 4303 struct bnxt *bp = netdev_priv(dev); 4304 u64 *rx; 4305 4306 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 4307 return; 4308 4309 rx = bp->rx_port_stats_ext.sw_stats; 4310 phy_stats->SymbolErrorDuringCarrier = 4311 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err)); 4312 } 4313 4314 static void bnxt_get_eth_mac_stats(struct net_device *dev, 4315 struct ethtool_eth_mac_stats *mac_stats) 4316 { 4317 struct bnxt *bp = netdev_priv(dev); 4318 u64 *rx, *tx; 4319 4320 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4321 return; 4322 4323 rx = bp->port_stats.sw_stats; 4324 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4325 4326 mac_stats->FramesReceivedOK = 4327 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames); 4328 mac_stats->FramesTransmittedOK = 4329 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames); 4330 mac_stats->FrameCheckSequenceErrors = 4331 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames); 4332 mac_stats->AlignmentErrors = 4333 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames); 4334 mac_stats->OutOfRangeLengthField = 4335 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames); 4336 } 4337 4338 static void bnxt_get_eth_ctrl_stats(struct net_device *dev, 4339 struct ethtool_eth_ctrl_stats *ctrl_stats) 4340 { 4341 struct bnxt *bp = netdev_priv(dev); 4342 u64 *rx; 4343 4344 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4345 return; 4346 4347 rx = bp->port_stats.sw_stats; 4348 ctrl_stats->MACControlFramesReceived = 4349 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames); 4350 } 4351 4352 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = { 4353 { 0, 64 }, 4354 { 65, 127 }, 4355 { 128, 255 }, 4356 { 256, 511 }, 4357 { 512, 1023 }, 4358 { 1024, 1518 }, 4359 { 1519, 2047 }, 4360 { 2048, 4095 }, 4361 { 4096, 9216 }, 4362 { 9217, 16383 }, 4363 {} 4364 }; 4365 4366 static void bnxt_get_rmon_stats(struct net_device *dev, 4367 struct ethtool_rmon_stats *rmon_stats, 4368 const struct ethtool_rmon_hist_range **ranges) 4369 { 4370 struct bnxt *bp = netdev_priv(dev); 4371 u64 *rx, *tx; 4372 4373 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS)) 4374 return; 4375 4376 rx = bp->port_stats.sw_stats; 4377 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8; 4378 4379 rmon_stats->jabbers = 4380 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames); 4381 rmon_stats->oversize_pkts = 4382 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames); 4383 rmon_stats->undersize_pkts = 4384 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames); 4385 4386 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames); 4387 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames); 4388 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames); 4389 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames); 4390 rmon_stats->hist[4] = 4391 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames); 4392 rmon_stats->hist[5] = 4393 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames); 4394 rmon_stats->hist[6] = 4395 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames); 4396 rmon_stats->hist[7] = 4397 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames); 4398 rmon_stats->hist[8] = 4399 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames); 4400 rmon_stats->hist[9] = 4401 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames); 4402 4403 rmon_stats->hist_tx[0] = 4404 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames); 4405 rmon_stats->hist_tx[1] = 4406 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames); 4407 rmon_stats->hist_tx[2] = 4408 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames); 4409 rmon_stats->hist_tx[3] = 4410 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames); 4411 rmon_stats->hist_tx[4] = 4412 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames); 4413 rmon_stats->hist_tx[5] = 4414 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames); 4415 rmon_stats->hist_tx[6] = 4416 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames); 4417 rmon_stats->hist_tx[7] = 4418 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames); 4419 rmon_stats->hist_tx[8] = 4420 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames); 4421 rmon_stats->hist_tx[9] = 4422 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames); 4423 4424 *ranges = bnxt_rmon_ranges; 4425 } 4426 4427 static void bnxt_get_link_ext_stats(struct net_device *dev, 4428 struct ethtool_link_ext_stats *stats) 4429 { 4430 struct bnxt *bp = netdev_priv(dev); 4431 u64 *rx; 4432 4433 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT)) 4434 return; 4435 4436 rx = bp->rx_port_stats_ext.sw_stats; 4437 stats->link_down_events = 4438 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events)); 4439 } 4440 4441 void bnxt_ethtool_free(struct bnxt *bp) 4442 { 4443 kfree(bp->test_info); 4444 bp->test_info = NULL; 4445 } 4446 4447 const struct ethtool_ops bnxt_ethtool_ops = { 4448 .cap_link_lanes_supported = 1, 4449 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 4450 ETHTOOL_COALESCE_MAX_FRAMES | 4451 ETHTOOL_COALESCE_USECS_IRQ | 4452 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 4453 ETHTOOL_COALESCE_STATS_BLOCK_USECS | 4454 ETHTOOL_COALESCE_USE_ADAPTIVE_RX | 4455 ETHTOOL_COALESCE_USE_CQE, 4456 .get_link_ksettings = bnxt_get_link_ksettings, 4457 .set_link_ksettings = bnxt_set_link_ksettings, 4458 .get_fec_stats = bnxt_get_fec_stats, 4459 .get_fecparam = bnxt_get_fecparam, 4460 .set_fecparam = bnxt_set_fecparam, 4461 .get_pause_stats = bnxt_get_pause_stats, 4462 .get_pauseparam = bnxt_get_pauseparam, 4463 .set_pauseparam = bnxt_set_pauseparam, 4464 .get_drvinfo = bnxt_get_drvinfo, 4465 .get_regs_len = bnxt_get_regs_len, 4466 .get_regs = bnxt_get_regs, 4467 .get_wol = bnxt_get_wol, 4468 .set_wol = bnxt_set_wol, 4469 .get_coalesce = bnxt_get_coalesce, 4470 .set_coalesce = bnxt_set_coalesce, 4471 .get_msglevel = bnxt_get_msglevel, 4472 .set_msglevel = bnxt_set_msglevel, 4473 .get_sset_count = bnxt_get_sset_count, 4474 .get_strings = bnxt_get_strings, 4475 .get_ethtool_stats = bnxt_get_ethtool_stats, 4476 .set_ringparam = bnxt_set_ringparam, 4477 .get_ringparam = bnxt_get_ringparam, 4478 .get_channels = bnxt_get_channels, 4479 .set_channels = bnxt_set_channels, 4480 .get_rxnfc = bnxt_get_rxnfc, 4481 .set_rxnfc = bnxt_set_rxnfc, 4482 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size, 4483 .get_rxfh_key_size = bnxt_get_rxfh_key_size, 4484 .get_rxfh = bnxt_get_rxfh, 4485 .set_rxfh = bnxt_set_rxfh, 4486 .flash_device = bnxt_flash_device, 4487 .get_eeprom_len = bnxt_get_eeprom_len, 4488 .get_eeprom = bnxt_get_eeprom, 4489 .set_eeprom = bnxt_set_eeprom, 4490 .get_link = bnxt_get_link, 4491 .get_link_ext_stats = bnxt_get_link_ext_stats, 4492 .get_eee = bnxt_get_eee, 4493 .set_eee = bnxt_set_eee, 4494 .get_module_info = bnxt_get_module_info, 4495 .get_module_eeprom = bnxt_get_module_eeprom, 4496 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 4497 .nway_reset = bnxt_nway_reset, 4498 .set_phys_id = bnxt_set_phys_id, 4499 .self_test = bnxt_self_test, 4500 .get_ts_info = bnxt_get_ts_info, 4501 .reset = bnxt_reset, 4502 .set_dump = bnxt_set_dump, 4503 .get_dump_flag = bnxt_get_dump_flag, 4504 .get_dump_data = bnxt_get_dump_data, 4505 .get_eth_phy_stats = bnxt_get_eth_phy_stats, 4506 .get_eth_mac_stats = bnxt_get_eth_mac_stats, 4507 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats, 4508 .get_rmon_stats = bnxt_get_rmon_stats, 4509 }; 4510