1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2017 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/sched.h> 13 #include <linux/types.h> 14 #include <linux/fcntl.h> 15 #include <linux/interrupt.h> 16 #include <linux/string.h> 17 #include <linux/if_ether.h> 18 #include <linux/init.h> 19 #include <linux/errno.h> 20 #include <linux/delay.h> 21 #include <linux/platform_device.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/pm.h> 24 #include <linux/clk.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_net.h> 29 #include <linux/of_platform.h> 30 #include <net/arp.h> 31 32 #include <linux/mii.h> 33 #include <linux/ethtool.h> 34 #include <linux/netdevice.h> 35 #include <linux/inetdevice.h> 36 #include <linux/etherdevice.h> 37 #include <linux/skbuff.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <linux/ipv6.h> 41 #include <linux/phy.h> 42 #include <linux/platform_data/bcmgenet.h> 43 44 #include <asm/unaligned.h> 45 46 #include "bcmgenet.h" 47 48 /* Maximum number of hardware queues, downsized if needed */ 49 #define GENET_MAX_MQ_CNT 4 50 51 /* Default highest priority queue for multi queue support */ 52 #define GENET_Q0_PRIORITY 0 53 54 #define GENET_Q16_RX_BD_CNT \ 55 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 56 #define GENET_Q16_TX_BD_CNT \ 57 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 58 59 #define RX_BUF_LENGTH 2048 60 #define SKB_ALIGNMENT 32 61 62 /* Tx/Rx DMA register offset, skip 256 descriptors */ 63 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 64 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 65 66 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 67 TOTAL_DESC * DMA_DESC_SIZE) 68 69 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 70 TOTAL_DESC * DMA_DESC_SIZE) 71 72 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 73 { 74 /* MIPS chips strapped for BE will automagically configure the 75 * peripheral registers for CPU-native byte order. 76 */ 77 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 78 __raw_writel(value, offset); 79 else 80 writel_relaxed(value, offset); 81 } 82 83 static inline u32 bcmgenet_readl(void __iomem *offset) 84 { 85 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 86 return __raw_readl(offset); 87 else 88 return readl_relaxed(offset); 89 } 90 91 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 92 void __iomem *d, u32 value) 93 { 94 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 95 } 96 97 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, 98 void __iomem *d) 99 { 100 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS); 101 } 102 103 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 104 void __iomem *d, 105 dma_addr_t addr) 106 { 107 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 108 109 /* Register writes to GISB bus can take couple hundred nanoseconds 110 * and are done for each packet, save these expensive writes unless 111 * the platform is explicitly configured for 64-bits/LPAE. 112 */ 113 #ifdef CONFIG_PHYS_ADDR_T_64BIT 114 if (priv->hw_params->flags & GENET_HAS_40BITS) 115 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 116 #endif 117 } 118 119 /* Combined address + length/status setter */ 120 static inline void dmadesc_set(struct bcmgenet_priv *priv, 121 void __iomem *d, dma_addr_t addr, u32 val) 122 { 123 dmadesc_set_addr(priv, d, addr); 124 dmadesc_set_length_status(priv, d, val); 125 } 126 127 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 128 void __iomem *d) 129 { 130 dma_addr_t addr; 131 132 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 133 134 /* Register writes to GISB bus can take couple hundred nanoseconds 135 * and are done for each packet, save these expensive writes unless 136 * the platform is explicitly configured for 64-bits/LPAE. 137 */ 138 #ifdef CONFIG_PHYS_ADDR_T_64BIT 139 if (priv->hw_params->flags & GENET_HAS_40BITS) 140 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 141 #endif 142 return addr; 143 } 144 145 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 146 147 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 148 NETIF_MSG_LINK) 149 150 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 151 { 152 if (GENET_IS_V1(priv)) 153 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 154 else 155 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 156 } 157 158 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 159 { 160 if (GENET_IS_V1(priv)) 161 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 162 else 163 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 164 } 165 166 /* These macros are defined to deal with register map change 167 * between GENET1.1 and GENET2. Only those currently being used 168 * by driver are defined. 169 */ 170 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 171 { 172 if (GENET_IS_V1(priv)) 173 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 174 else 175 return bcmgenet_readl(priv->base + 176 priv->hw_params->tbuf_offset + TBUF_CTRL); 177 } 178 179 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 180 { 181 if (GENET_IS_V1(priv)) 182 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 183 else 184 bcmgenet_writel(val, priv->base + 185 priv->hw_params->tbuf_offset + TBUF_CTRL); 186 } 187 188 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 189 { 190 if (GENET_IS_V1(priv)) 191 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 192 else 193 return bcmgenet_readl(priv->base + 194 priv->hw_params->tbuf_offset + TBUF_BP_MC); 195 } 196 197 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 198 { 199 if (GENET_IS_V1(priv)) 200 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 201 else 202 bcmgenet_writel(val, priv->base + 203 priv->hw_params->tbuf_offset + TBUF_BP_MC); 204 } 205 206 /* RX/TX DMA register accessors */ 207 enum dma_reg { 208 DMA_RING_CFG = 0, 209 DMA_CTRL, 210 DMA_STATUS, 211 DMA_SCB_BURST_SIZE, 212 DMA_ARB_CTRL, 213 DMA_PRIORITY_0, 214 DMA_PRIORITY_1, 215 DMA_PRIORITY_2, 216 DMA_INDEX2RING_0, 217 DMA_INDEX2RING_1, 218 DMA_INDEX2RING_2, 219 DMA_INDEX2RING_3, 220 DMA_INDEX2RING_4, 221 DMA_INDEX2RING_5, 222 DMA_INDEX2RING_6, 223 DMA_INDEX2RING_7, 224 DMA_RING0_TIMEOUT, 225 DMA_RING1_TIMEOUT, 226 DMA_RING2_TIMEOUT, 227 DMA_RING3_TIMEOUT, 228 DMA_RING4_TIMEOUT, 229 DMA_RING5_TIMEOUT, 230 DMA_RING6_TIMEOUT, 231 DMA_RING7_TIMEOUT, 232 DMA_RING8_TIMEOUT, 233 DMA_RING9_TIMEOUT, 234 DMA_RING10_TIMEOUT, 235 DMA_RING11_TIMEOUT, 236 DMA_RING12_TIMEOUT, 237 DMA_RING13_TIMEOUT, 238 DMA_RING14_TIMEOUT, 239 DMA_RING15_TIMEOUT, 240 DMA_RING16_TIMEOUT, 241 }; 242 243 static const u8 bcmgenet_dma_regs_v3plus[] = { 244 [DMA_RING_CFG] = 0x00, 245 [DMA_CTRL] = 0x04, 246 [DMA_STATUS] = 0x08, 247 [DMA_SCB_BURST_SIZE] = 0x0C, 248 [DMA_ARB_CTRL] = 0x2C, 249 [DMA_PRIORITY_0] = 0x30, 250 [DMA_PRIORITY_1] = 0x34, 251 [DMA_PRIORITY_2] = 0x38, 252 [DMA_RING0_TIMEOUT] = 0x2C, 253 [DMA_RING1_TIMEOUT] = 0x30, 254 [DMA_RING2_TIMEOUT] = 0x34, 255 [DMA_RING3_TIMEOUT] = 0x38, 256 [DMA_RING4_TIMEOUT] = 0x3c, 257 [DMA_RING5_TIMEOUT] = 0x40, 258 [DMA_RING6_TIMEOUT] = 0x44, 259 [DMA_RING7_TIMEOUT] = 0x48, 260 [DMA_RING8_TIMEOUT] = 0x4c, 261 [DMA_RING9_TIMEOUT] = 0x50, 262 [DMA_RING10_TIMEOUT] = 0x54, 263 [DMA_RING11_TIMEOUT] = 0x58, 264 [DMA_RING12_TIMEOUT] = 0x5c, 265 [DMA_RING13_TIMEOUT] = 0x60, 266 [DMA_RING14_TIMEOUT] = 0x64, 267 [DMA_RING15_TIMEOUT] = 0x68, 268 [DMA_RING16_TIMEOUT] = 0x6C, 269 [DMA_INDEX2RING_0] = 0x70, 270 [DMA_INDEX2RING_1] = 0x74, 271 [DMA_INDEX2RING_2] = 0x78, 272 [DMA_INDEX2RING_3] = 0x7C, 273 [DMA_INDEX2RING_4] = 0x80, 274 [DMA_INDEX2RING_5] = 0x84, 275 [DMA_INDEX2RING_6] = 0x88, 276 [DMA_INDEX2RING_7] = 0x8C, 277 }; 278 279 static const u8 bcmgenet_dma_regs_v2[] = { 280 [DMA_RING_CFG] = 0x00, 281 [DMA_CTRL] = 0x04, 282 [DMA_STATUS] = 0x08, 283 [DMA_SCB_BURST_SIZE] = 0x0C, 284 [DMA_ARB_CTRL] = 0x30, 285 [DMA_PRIORITY_0] = 0x34, 286 [DMA_PRIORITY_1] = 0x38, 287 [DMA_PRIORITY_2] = 0x3C, 288 [DMA_RING0_TIMEOUT] = 0x2C, 289 [DMA_RING1_TIMEOUT] = 0x30, 290 [DMA_RING2_TIMEOUT] = 0x34, 291 [DMA_RING3_TIMEOUT] = 0x38, 292 [DMA_RING4_TIMEOUT] = 0x3c, 293 [DMA_RING5_TIMEOUT] = 0x40, 294 [DMA_RING6_TIMEOUT] = 0x44, 295 [DMA_RING7_TIMEOUT] = 0x48, 296 [DMA_RING8_TIMEOUT] = 0x4c, 297 [DMA_RING9_TIMEOUT] = 0x50, 298 [DMA_RING10_TIMEOUT] = 0x54, 299 [DMA_RING11_TIMEOUT] = 0x58, 300 [DMA_RING12_TIMEOUT] = 0x5c, 301 [DMA_RING13_TIMEOUT] = 0x60, 302 [DMA_RING14_TIMEOUT] = 0x64, 303 [DMA_RING15_TIMEOUT] = 0x68, 304 [DMA_RING16_TIMEOUT] = 0x6C, 305 }; 306 307 static const u8 bcmgenet_dma_regs_v1[] = { 308 [DMA_CTRL] = 0x00, 309 [DMA_STATUS] = 0x04, 310 [DMA_SCB_BURST_SIZE] = 0x0C, 311 [DMA_ARB_CTRL] = 0x30, 312 [DMA_PRIORITY_0] = 0x34, 313 [DMA_PRIORITY_1] = 0x38, 314 [DMA_PRIORITY_2] = 0x3C, 315 [DMA_RING0_TIMEOUT] = 0x2C, 316 [DMA_RING1_TIMEOUT] = 0x30, 317 [DMA_RING2_TIMEOUT] = 0x34, 318 [DMA_RING3_TIMEOUT] = 0x38, 319 [DMA_RING4_TIMEOUT] = 0x3c, 320 [DMA_RING5_TIMEOUT] = 0x40, 321 [DMA_RING6_TIMEOUT] = 0x44, 322 [DMA_RING7_TIMEOUT] = 0x48, 323 [DMA_RING8_TIMEOUT] = 0x4c, 324 [DMA_RING9_TIMEOUT] = 0x50, 325 [DMA_RING10_TIMEOUT] = 0x54, 326 [DMA_RING11_TIMEOUT] = 0x58, 327 [DMA_RING12_TIMEOUT] = 0x5c, 328 [DMA_RING13_TIMEOUT] = 0x60, 329 [DMA_RING14_TIMEOUT] = 0x64, 330 [DMA_RING15_TIMEOUT] = 0x68, 331 [DMA_RING16_TIMEOUT] = 0x6C, 332 }; 333 334 /* Set at runtime once bcmgenet version is known */ 335 static const u8 *bcmgenet_dma_regs; 336 337 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 338 { 339 return netdev_priv(dev_get_drvdata(dev)); 340 } 341 342 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 343 enum dma_reg r) 344 { 345 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 347 } 348 349 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 350 u32 val, enum dma_reg r) 351 { 352 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 354 } 355 356 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 357 enum dma_reg r) 358 { 359 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 361 } 362 363 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 364 u32 val, enum dma_reg r) 365 { 366 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 367 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 368 } 369 370 /* RDMA/TDMA ring registers and accessors 371 * we merge the common fields and just prefix with T/D the registers 372 * having different meaning depending on the direction 373 */ 374 enum dma_ring_reg { 375 TDMA_READ_PTR = 0, 376 RDMA_WRITE_PTR = TDMA_READ_PTR, 377 TDMA_READ_PTR_HI, 378 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 379 TDMA_CONS_INDEX, 380 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 381 TDMA_PROD_INDEX, 382 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 383 DMA_RING_BUF_SIZE, 384 DMA_START_ADDR, 385 DMA_START_ADDR_HI, 386 DMA_END_ADDR, 387 DMA_END_ADDR_HI, 388 DMA_MBUF_DONE_THRESH, 389 TDMA_FLOW_PERIOD, 390 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 391 TDMA_WRITE_PTR, 392 RDMA_READ_PTR = TDMA_WRITE_PTR, 393 TDMA_WRITE_PTR_HI, 394 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 395 }; 396 397 /* GENET v4 supports 40-bits pointer addressing 398 * for obvious reasons the LO and HI word parts 399 * are contiguous, but this offsets the other 400 * registers. 401 */ 402 static const u8 genet_dma_ring_regs_v4[] = { 403 [TDMA_READ_PTR] = 0x00, 404 [TDMA_READ_PTR_HI] = 0x04, 405 [TDMA_CONS_INDEX] = 0x08, 406 [TDMA_PROD_INDEX] = 0x0C, 407 [DMA_RING_BUF_SIZE] = 0x10, 408 [DMA_START_ADDR] = 0x14, 409 [DMA_START_ADDR_HI] = 0x18, 410 [DMA_END_ADDR] = 0x1C, 411 [DMA_END_ADDR_HI] = 0x20, 412 [DMA_MBUF_DONE_THRESH] = 0x24, 413 [TDMA_FLOW_PERIOD] = 0x28, 414 [TDMA_WRITE_PTR] = 0x2C, 415 [TDMA_WRITE_PTR_HI] = 0x30, 416 }; 417 418 static const u8 genet_dma_ring_regs_v123[] = { 419 [TDMA_READ_PTR] = 0x00, 420 [TDMA_CONS_INDEX] = 0x04, 421 [TDMA_PROD_INDEX] = 0x08, 422 [DMA_RING_BUF_SIZE] = 0x0C, 423 [DMA_START_ADDR] = 0x10, 424 [DMA_END_ADDR] = 0x14, 425 [DMA_MBUF_DONE_THRESH] = 0x18, 426 [TDMA_FLOW_PERIOD] = 0x1C, 427 [TDMA_WRITE_PTR] = 0x20, 428 }; 429 430 /* Set at runtime once GENET version is known */ 431 static const u8 *genet_dma_ring_regs; 432 433 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 434 unsigned int ring, 435 enum dma_ring_reg r) 436 { 437 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 438 (DMA_RING_SIZE * ring) + 439 genet_dma_ring_regs[r]); 440 } 441 442 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 443 unsigned int ring, u32 val, 444 enum dma_ring_reg r) 445 { 446 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 447 (DMA_RING_SIZE * ring) + 448 genet_dma_ring_regs[r]); 449 } 450 451 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 452 unsigned int ring, 453 enum dma_ring_reg r) 454 { 455 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 456 (DMA_RING_SIZE * ring) + 457 genet_dma_ring_regs[r]); 458 } 459 460 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 461 unsigned int ring, u32 val, 462 enum dma_ring_reg r) 463 { 464 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 465 (DMA_RING_SIZE * ring) + 466 genet_dma_ring_regs[r]); 467 } 468 469 static int bcmgenet_begin(struct net_device *dev) 470 { 471 struct bcmgenet_priv *priv = netdev_priv(dev); 472 473 /* Turn on the clock */ 474 return clk_prepare_enable(priv->clk); 475 } 476 477 static void bcmgenet_complete(struct net_device *dev) 478 { 479 struct bcmgenet_priv *priv = netdev_priv(dev); 480 481 /* Turn off the clock */ 482 clk_disable_unprepare(priv->clk); 483 } 484 485 static int bcmgenet_get_link_ksettings(struct net_device *dev, 486 struct ethtool_link_ksettings *cmd) 487 { 488 if (!netif_running(dev)) 489 return -EINVAL; 490 491 if (!dev->phydev) 492 return -ENODEV; 493 494 phy_ethtool_ksettings_get(dev->phydev, cmd); 495 496 return 0; 497 } 498 499 static int bcmgenet_set_link_ksettings(struct net_device *dev, 500 const struct ethtool_link_ksettings *cmd) 501 { 502 if (!netif_running(dev)) 503 return -EINVAL; 504 505 if (!dev->phydev) 506 return -ENODEV; 507 508 return phy_ethtool_ksettings_set(dev->phydev, cmd); 509 } 510 511 static int bcmgenet_set_rx_csum(struct net_device *dev, 512 netdev_features_t wanted) 513 { 514 struct bcmgenet_priv *priv = netdev_priv(dev); 515 u32 rbuf_chk_ctrl; 516 bool rx_csum_en; 517 518 rx_csum_en = !!(wanted & NETIF_F_RXCSUM); 519 520 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 521 522 /* enable rx checksumming */ 523 if (rx_csum_en) 524 rbuf_chk_ctrl |= RBUF_RXCHK_EN; 525 else 526 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; 527 priv->desc_rxchk_en = rx_csum_en; 528 529 /* If UniMAC forwards CRC, we need to skip over it to get 530 * a valid CHK bit to be set in the per-packet status word 531 */ 532 if (rx_csum_en && priv->crc_fwd_en) 533 rbuf_chk_ctrl |= RBUF_SKIP_FCS; 534 else 535 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; 536 537 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); 538 539 return 0; 540 } 541 542 static int bcmgenet_set_tx_csum(struct net_device *dev, 543 netdev_features_t wanted) 544 { 545 struct bcmgenet_priv *priv = netdev_priv(dev); 546 bool desc_64b_en; 547 u32 tbuf_ctrl, rbuf_ctrl; 548 549 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); 550 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 551 552 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 553 554 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ 555 if (desc_64b_en) { 556 tbuf_ctrl |= RBUF_64B_EN; 557 rbuf_ctrl |= RBUF_64B_EN; 558 } else { 559 tbuf_ctrl &= ~RBUF_64B_EN; 560 rbuf_ctrl &= ~RBUF_64B_EN; 561 } 562 priv->desc_64b_en = desc_64b_en; 563 564 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); 565 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); 566 567 return 0; 568 } 569 570 static int bcmgenet_set_features(struct net_device *dev, 571 netdev_features_t features) 572 { 573 netdev_features_t changed = features ^ dev->features; 574 netdev_features_t wanted = dev->wanted_features; 575 int ret = 0; 576 577 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 578 ret = bcmgenet_set_tx_csum(dev, wanted); 579 if (changed & (NETIF_F_RXCSUM)) 580 ret = bcmgenet_set_rx_csum(dev, wanted); 581 582 return ret; 583 } 584 585 static u32 bcmgenet_get_msglevel(struct net_device *dev) 586 { 587 struct bcmgenet_priv *priv = netdev_priv(dev); 588 589 return priv->msg_enable; 590 } 591 592 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 593 { 594 struct bcmgenet_priv *priv = netdev_priv(dev); 595 596 priv->msg_enable = level; 597 } 598 599 static int bcmgenet_get_coalesce(struct net_device *dev, 600 struct ethtool_coalesce *ec) 601 { 602 struct bcmgenet_priv *priv = netdev_priv(dev); 603 struct bcmgenet_rx_ring *ring; 604 unsigned int i; 605 606 ec->tx_max_coalesced_frames = 607 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 608 DMA_MBUF_DONE_THRESH); 609 ec->rx_max_coalesced_frames = 610 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 611 DMA_MBUF_DONE_THRESH); 612 ec->rx_coalesce_usecs = 613 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 614 615 for (i = 0; i < priv->hw_params->rx_queues; i++) { 616 ring = &priv->rx_rings[i]; 617 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 618 } 619 ring = &priv->rx_rings[DESC_INDEX]; 620 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 621 622 return 0; 623 } 624 625 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 626 u32 usecs, u32 pkts) 627 { 628 struct bcmgenet_priv *priv = ring->priv; 629 unsigned int i = ring->index; 630 u32 reg; 631 632 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 633 634 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 635 reg &= ~DMA_TIMEOUT_MASK; 636 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 637 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 638 } 639 640 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 641 struct ethtool_coalesce *ec) 642 { 643 struct dim_cq_moder moder; 644 u32 usecs, pkts; 645 646 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 647 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 648 usecs = ring->rx_coalesce_usecs; 649 pkts = ring->rx_max_coalesced_frames; 650 651 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 652 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 653 usecs = moder.usec; 654 pkts = moder.pkts; 655 } 656 657 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 658 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 659 } 660 661 static int bcmgenet_set_coalesce(struct net_device *dev, 662 struct ethtool_coalesce *ec) 663 { 664 struct bcmgenet_priv *priv = netdev_priv(dev); 665 unsigned int i; 666 667 /* Base system clock is 125Mhz, DMA timeout is this reference clock 668 * divided by 1024, which yields roughly 8.192us, our maximum value 669 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 670 */ 671 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 672 ec->tx_max_coalesced_frames == 0 || 673 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 674 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 675 return -EINVAL; 676 677 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 678 return -EINVAL; 679 680 /* GENET TDMA hardware does not support a configurable timeout, but will 681 * always generate an interrupt either after MBDONE packets have been 682 * transmitted, or when the ring is empty. 683 */ 684 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high || 685 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low || 686 ec->use_adaptive_tx_coalesce) 687 return -EOPNOTSUPP; 688 689 /* Program all TX queues with the same values, as there is no 690 * ethtool knob to do coalescing on a per-queue basis 691 */ 692 for (i = 0; i < priv->hw_params->tx_queues; i++) 693 bcmgenet_tdma_ring_writel(priv, i, 694 ec->tx_max_coalesced_frames, 695 DMA_MBUF_DONE_THRESH); 696 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 697 ec->tx_max_coalesced_frames, 698 DMA_MBUF_DONE_THRESH); 699 700 for (i = 0; i < priv->hw_params->rx_queues; i++) 701 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 702 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec); 703 704 return 0; 705 } 706 707 /* standard ethtool support functions. */ 708 enum bcmgenet_stat_type { 709 BCMGENET_STAT_NETDEV = -1, 710 BCMGENET_STAT_MIB_RX, 711 BCMGENET_STAT_MIB_TX, 712 BCMGENET_STAT_RUNT, 713 BCMGENET_STAT_MISC, 714 BCMGENET_STAT_SOFT, 715 }; 716 717 struct bcmgenet_stats { 718 char stat_string[ETH_GSTRING_LEN]; 719 int stat_sizeof; 720 int stat_offset; 721 enum bcmgenet_stat_type type; 722 /* reg offset from UMAC base for misc counters */ 723 u16 reg_offset; 724 }; 725 726 #define STAT_NETDEV(m) { \ 727 .stat_string = __stringify(m), \ 728 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 729 .stat_offset = offsetof(struct net_device_stats, m), \ 730 .type = BCMGENET_STAT_NETDEV, \ 731 } 732 733 #define STAT_GENET_MIB(str, m, _type) { \ 734 .stat_string = str, \ 735 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 736 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 737 .type = _type, \ 738 } 739 740 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 741 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 742 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 743 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 744 745 #define STAT_GENET_MISC(str, m, offset) { \ 746 .stat_string = str, \ 747 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 748 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 749 .type = BCMGENET_STAT_MISC, \ 750 .reg_offset = offset, \ 751 } 752 753 #define STAT_GENET_Q(num) \ 754 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 755 tx_rings[num].packets), \ 756 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 757 tx_rings[num].bytes), \ 758 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 759 rx_rings[num].bytes), \ 760 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 761 rx_rings[num].packets), \ 762 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 763 rx_rings[num].errors), \ 764 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 765 rx_rings[num].dropped) 766 767 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 768 * between the end of TX stats and the beginning of the RX RUNT 769 */ 770 #define BCMGENET_STAT_OFFSET 0xc 771 772 /* Hardware counters must be kept in sync because the order/offset 773 * is important here (order in structure declaration = order in hardware) 774 */ 775 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 776 /* general stats */ 777 STAT_NETDEV(rx_packets), 778 STAT_NETDEV(tx_packets), 779 STAT_NETDEV(rx_bytes), 780 STAT_NETDEV(tx_bytes), 781 STAT_NETDEV(rx_errors), 782 STAT_NETDEV(tx_errors), 783 STAT_NETDEV(rx_dropped), 784 STAT_NETDEV(tx_dropped), 785 STAT_NETDEV(multicast), 786 /* UniMAC RSV counters */ 787 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 788 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 789 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 790 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 791 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 792 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 793 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 794 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 795 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 796 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 797 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 798 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 799 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 800 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 801 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 802 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 803 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 804 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 805 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 806 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 807 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 808 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 809 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 810 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 811 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 812 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 813 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 814 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 815 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 816 /* UniMAC TSV counters */ 817 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 818 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 819 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 820 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 821 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 822 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 823 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 824 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 825 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 826 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 827 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 828 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 829 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 830 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 831 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 832 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 833 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 834 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 835 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 836 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 837 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 838 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 839 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 840 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 841 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 842 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 843 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 844 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 845 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 846 /* UniMAC RUNT counters */ 847 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 848 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 849 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 850 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 851 /* Misc UniMAC counters */ 852 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 853 UMAC_RBUF_OVFL_CNT_V1), 854 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 855 UMAC_RBUF_ERR_CNT_V1), 856 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 857 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 858 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 859 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 860 /* Per TX queues */ 861 STAT_GENET_Q(0), 862 STAT_GENET_Q(1), 863 STAT_GENET_Q(2), 864 STAT_GENET_Q(3), 865 STAT_GENET_Q(16), 866 }; 867 868 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 869 870 static void bcmgenet_get_drvinfo(struct net_device *dev, 871 struct ethtool_drvinfo *info) 872 { 873 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 874 strlcpy(info->version, "v2.0", sizeof(info->version)); 875 } 876 877 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 878 { 879 switch (string_set) { 880 case ETH_SS_STATS: 881 return BCMGENET_STATS_LEN; 882 default: 883 return -EOPNOTSUPP; 884 } 885 } 886 887 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 888 u8 *data) 889 { 890 int i; 891 892 switch (stringset) { 893 case ETH_SS_STATS: 894 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 895 memcpy(data + i * ETH_GSTRING_LEN, 896 bcmgenet_gstrings_stats[i].stat_string, 897 ETH_GSTRING_LEN); 898 } 899 break; 900 } 901 } 902 903 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 904 { 905 u16 new_offset; 906 u32 val; 907 908 switch (offset) { 909 case UMAC_RBUF_OVFL_CNT_V1: 910 if (GENET_IS_V2(priv)) 911 new_offset = RBUF_OVFL_CNT_V2; 912 else 913 new_offset = RBUF_OVFL_CNT_V3PLUS; 914 915 val = bcmgenet_rbuf_readl(priv, new_offset); 916 /* clear if overflowed */ 917 if (val == ~0) 918 bcmgenet_rbuf_writel(priv, 0, new_offset); 919 break; 920 case UMAC_RBUF_ERR_CNT_V1: 921 if (GENET_IS_V2(priv)) 922 new_offset = RBUF_ERR_CNT_V2; 923 else 924 new_offset = RBUF_ERR_CNT_V3PLUS; 925 926 val = bcmgenet_rbuf_readl(priv, new_offset); 927 /* clear if overflowed */ 928 if (val == ~0) 929 bcmgenet_rbuf_writel(priv, 0, new_offset); 930 break; 931 default: 932 val = bcmgenet_umac_readl(priv, offset); 933 /* clear if overflowed */ 934 if (val == ~0) 935 bcmgenet_umac_writel(priv, 0, offset); 936 break; 937 } 938 939 return val; 940 } 941 942 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 943 { 944 int i, j = 0; 945 946 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 947 const struct bcmgenet_stats *s; 948 u8 offset = 0; 949 u32 val = 0; 950 char *p; 951 952 s = &bcmgenet_gstrings_stats[i]; 953 switch (s->type) { 954 case BCMGENET_STAT_NETDEV: 955 case BCMGENET_STAT_SOFT: 956 continue; 957 case BCMGENET_STAT_RUNT: 958 offset += BCMGENET_STAT_OFFSET; 959 /* fall through */ 960 case BCMGENET_STAT_MIB_TX: 961 offset += BCMGENET_STAT_OFFSET; 962 /* fall through */ 963 case BCMGENET_STAT_MIB_RX: 964 val = bcmgenet_umac_readl(priv, 965 UMAC_MIB_START + j + offset); 966 offset = 0; /* Reset Offset */ 967 break; 968 case BCMGENET_STAT_MISC: 969 if (GENET_IS_V1(priv)) { 970 val = bcmgenet_umac_readl(priv, s->reg_offset); 971 /* clear if overflowed */ 972 if (val == ~0) 973 bcmgenet_umac_writel(priv, 0, 974 s->reg_offset); 975 } else { 976 val = bcmgenet_update_stat_misc(priv, 977 s->reg_offset); 978 } 979 break; 980 } 981 982 j += s->stat_sizeof; 983 p = (char *)priv + s->stat_offset; 984 *(u32 *)p = val; 985 } 986 } 987 988 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 989 struct ethtool_stats *stats, 990 u64 *data) 991 { 992 struct bcmgenet_priv *priv = netdev_priv(dev); 993 int i; 994 995 if (netif_running(dev)) 996 bcmgenet_update_mib_counters(priv); 997 998 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 999 const struct bcmgenet_stats *s; 1000 char *p; 1001 1002 s = &bcmgenet_gstrings_stats[i]; 1003 if (s->type == BCMGENET_STAT_NETDEV) 1004 p = (char *)&dev->stats; 1005 else 1006 p = (char *)priv; 1007 p += s->stat_offset; 1008 if (sizeof(unsigned long) != sizeof(u32) && 1009 s->stat_sizeof == sizeof(unsigned long)) 1010 data[i] = *(unsigned long *)p; 1011 else 1012 data[i] = *(u32 *)p; 1013 } 1014 } 1015 1016 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1017 { 1018 struct bcmgenet_priv *priv = netdev_priv(dev); 1019 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1020 u32 reg; 1021 1022 if (enable && !priv->clk_eee_enabled) { 1023 clk_prepare_enable(priv->clk_eee); 1024 priv->clk_eee_enabled = true; 1025 } 1026 1027 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1028 if (enable) 1029 reg |= EEE_EN; 1030 else 1031 reg &= ~EEE_EN; 1032 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1033 1034 /* Enable EEE and switch to a 27Mhz clock automatically */ 1035 reg = bcmgenet_readl(priv->base + off); 1036 if (enable) 1037 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1038 else 1039 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1040 bcmgenet_writel(reg, priv->base + off); 1041 1042 /* Do the same for thing for RBUF */ 1043 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1044 if (enable) 1045 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1046 else 1047 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1048 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1049 1050 if (!enable && priv->clk_eee_enabled) { 1051 clk_disable_unprepare(priv->clk_eee); 1052 priv->clk_eee_enabled = false; 1053 } 1054 1055 priv->eee.eee_enabled = enable; 1056 priv->eee.eee_active = enable; 1057 } 1058 1059 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1060 { 1061 struct bcmgenet_priv *priv = netdev_priv(dev); 1062 struct ethtool_eee *p = &priv->eee; 1063 1064 if (GENET_IS_V1(priv)) 1065 return -EOPNOTSUPP; 1066 1067 if (!dev->phydev) 1068 return -ENODEV; 1069 1070 e->eee_enabled = p->eee_enabled; 1071 e->eee_active = p->eee_active; 1072 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1073 1074 return phy_ethtool_get_eee(dev->phydev, e); 1075 } 1076 1077 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1078 { 1079 struct bcmgenet_priv *priv = netdev_priv(dev); 1080 struct ethtool_eee *p = &priv->eee; 1081 int ret = 0; 1082 1083 if (GENET_IS_V1(priv)) 1084 return -EOPNOTSUPP; 1085 1086 if (!dev->phydev) 1087 return -ENODEV; 1088 1089 p->eee_enabled = e->eee_enabled; 1090 1091 if (!p->eee_enabled) { 1092 bcmgenet_eee_enable_set(dev, false); 1093 } else { 1094 ret = phy_init_eee(dev->phydev, 0); 1095 if (ret) { 1096 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1097 return ret; 1098 } 1099 1100 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1101 bcmgenet_eee_enable_set(dev, true); 1102 } 1103 1104 return phy_ethtool_set_eee(dev->phydev, e); 1105 } 1106 1107 /* standard ethtool support functions. */ 1108 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1109 .begin = bcmgenet_begin, 1110 .complete = bcmgenet_complete, 1111 .get_strings = bcmgenet_get_strings, 1112 .get_sset_count = bcmgenet_get_sset_count, 1113 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1114 .get_drvinfo = bcmgenet_get_drvinfo, 1115 .get_link = ethtool_op_get_link, 1116 .get_msglevel = bcmgenet_get_msglevel, 1117 .set_msglevel = bcmgenet_set_msglevel, 1118 .get_wol = bcmgenet_get_wol, 1119 .set_wol = bcmgenet_set_wol, 1120 .get_eee = bcmgenet_get_eee, 1121 .set_eee = bcmgenet_set_eee, 1122 .nway_reset = phy_ethtool_nway_reset, 1123 .get_coalesce = bcmgenet_get_coalesce, 1124 .set_coalesce = bcmgenet_set_coalesce, 1125 .get_link_ksettings = bcmgenet_get_link_ksettings, 1126 .set_link_ksettings = bcmgenet_set_link_ksettings, 1127 .get_ts_info = ethtool_op_get_ts_info, 1128 }; 1129 1130 /* Power down the unimac, based on mode. */ 1131 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1132 enum bcmgenet_power_mode mode) 1133 { 1134 int ret = 0; 1135 u32 reg; 1136 1137 switch (mode) { 1138 case GENET_POWER_CABLE_SENSE: 1139 phy_detach(priv->dev->phydev); 1140 break; 1141 1142 case GENET_POWER_WOL_MAGIC: 1143 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1144 break; 1145 1146 case GENET_POWER_PASSIVE: 1147 /* Power down LED */ 1148 if (priv->hw_params->flags & GENET_HAS_EXT) { 1149 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1150 if (GENET_IS_V5(priv)) 1151 reg |= EXT_PWR_DOWN_PHY_EN | 1152 EXT_PWR_DOWN_PHY_RD | 1153 EXT_PWR_DOWN_PHY_SD | 1154 EXT_PWR_DOWN_PHY_RX | 1155 EXT_PWR_DOWN_PHY_TX | 1156 EXT_IDDQ_GLBL_PWR; 1157 else 1158 reg |= EXT_PWR_DOWN_PHY; 1159 1160 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1161 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1162 1163 bcmgenet_phy_power_set(priv->dev, false); 1164 } 1165 break; 1166 default: 1167 break; 1168 } 1169 1170 return ret; 1171 } 1172 1173 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1174 enum bcmgenet_power_mode mode) 1175 { 1176 u32 reg; 1177 1178 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1179 return; 1180 1181 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1182 1183 switch (mode) { 1184 case GENET_POWER_PASSIVE: 1185 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1186 if (GENET_IS_V5(priv)) { 1187 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1188 EXT_PWR_DOWN_PHY_RD | 1189 EXT_PWR_DOWN_PHY_SD | 1190 EXT_PWR_DOWN_PHY_RX | 1191 EXT_PWR_DOWN_PHY_TX | 1192 EXT_IDDQ_GLBL_PWR); 1193 reg |= EXT_PHY_RESET; 1194 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1195 mdelay(1); 1196 1197 reg &= ~EXT_PHY_RESET; 1198 } else { 1199 reg &= ~EXT_PWR_DOWN_PHY; 1200 reg |= EXT_PWR_DN_EN_LD; 1201 } 1202 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1203 bcmgenet_phy_power_set(priv->dev, true); 1204 break; 1205 1206 case GENET_POWER_CABLE_SENSE: 1207 /* enable APD */ 1208 if (!GENET_IS_V5(priv)) { 1209 reg |= EXT_PWR_DN_EN_LD; 1210 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1211 } 1212 break; 1213 case GENET_POWER_WOL_MAGIC: 1214 bcmgenet_wol_power_up_cfg(priv, mode); 1215 return; 1216 default: 1217 break; 1218 } 1219 } 1220 1221 /* ioctl handle special commands that are not present in ethtool. */ 1222 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1223 { 1224 if (!netif_running(dev)) 1225 return -EINVAL; 1226 1227 if (!dev->phydev) 1228 return -ENODEV; 1229 1230 return phy_mii_ioctl(dev->phydev, rq, cmd); 1231 } 1232 1233 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1234 struct bcmgenet_tx_ring *ring) 1235 { 1236 struct enet_cb *tx_cb_ptr; 1237 1238 tx_cb_ptr = ring->cbs; 1239 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1240 1241 /* Advancing local write pointer */ 1242 if (ring->write_ptr == ring->end_ptr) 1243 ring->write_ptr = ring->cb_ptr; 1244 else 1245 ring->write_ptr++; 1246 1247 return tx_cb_ptr; 1248 } 1249 1250 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1251 struct bcmgenet_tx_ring *ring) 1252 { 1253 struct enet_cb *tx_cb_ptr; 1254 1255 tx_cb_ptr = ring->cbs; 1256 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1257 1258 /* Rewinding local write pointer */ 1259 if (ring->write_ptr == ring->cb_ptr) 1260 ring->write_ptr = ring->end_ptr; 1261 else 1262 ring->write_ptr--; 1263 1264 return tx_cb_ptr; 1265 } 1266 1267 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1268 { 1269 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1270 INTRL2_CPU_MASK_SET); 1271 } 1272 1273 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1274 { 1275 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1276 INTRL2_CPU_MASK_CLEAR); 1277 } 1278 1279 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1280 { 1281 bcmgenet_intrl2_1_writel(ring->priv, 1282 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1283 INTRL2_CPU_MASK_SET); 1284 } 1285 1286 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1287 { 1288 bcmgenet_intrl2_1_writel(ring->priv, 1289 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1290 INTRL2_CPU_MASK_CLEAR); 1291 } 1292 1293 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1294 { 1295 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1296 INTRL2_CPU_MASK_SET); 1297 } 1298 1299 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1300 { 1301 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1302 INTRL2_CPU_MASK_CLEAR); 1303 } 1304 1305 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1306 { 1307 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1308 INTRL2_CPU_MASK_CLEAR); 1309 } 1310 1311 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1312 { 1313 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1314 INTRL2_CPU_MASK_SET); 1315 } 1316 1317 /* Simple helper to free a transmit control block's resources 1318 * Returns an skb when the last transmit control block associated with the 1319 * skb is freed. The skb should be freed by the caller if necessary. 1320 */ 1321 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1322 struct enet_cb *cb) 1323 { 1324 struct sk_buff *skb; 1325 1326 skb = cb->skb; 1327 1328 if (skb) { 1329 cb->skb = NULL; 1330 if (cb == GENET_CB(skb)->first_cb) 1331 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1332 dma_unmap_len(cb, dma_len), 1333 DMA_TO_DEVICE); 1334 else 1335 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1336 dma_unmap_len(cb, dma_len), 1337 DMA_TO_DEVICE); 1338 dma_unmap_addr_set(cb, dma_addr, 0); 1339 1340 if (cb == GENET_CB(skb)->last_cb) 1341 return skb; 1342 1343 } else if (dma_unmap_addr(cb, dma_addr)) { 1344 dma_unmap_page(dev, 1345 dma_unmap_addr(cb, dma_addr), 1346 dma_unmap_len(cb, dma_len), 1347 DMA_TO_DEVICE); 1348 dma_unmap_addr_set(cb, dma_addr, 0); 1349 } 1350 1351 return NULL; 1352 } 1353 1354 /* Simple helper to free a receive control block's resources */ 1355 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1356 struct enet_cb *cb) 1357 { 1358 struct sk_buff *skb; 1359 1360 skb = cb->skb; 1361 cb->skb = NULL; 1362 1363 if (dma_unmap_addr(cb, dma_addr)) { 1364 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1365 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1366 dma_unmap_addr_set(cb, dma_addr, 0); 1367 } 1368 1369 return skb; 1370 } 1371 1372 /* Unlocked version of the reclaim routine */ 1373 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1374 struct bcmgenet_tx_ring *ring) 1375 { 1376 struct bcmgenet_priv *priv = netdev_priv(dev); 1377 unsigned int txbds_processed = 0; 1378 unsigned int bytes_compl = 0; 1379 unsigned int pkts_compl = 0; 1380 unsigned int txbds_ready; 1381 unsigned int c_index; 1382 struct sk_buff *skb; 1383 1384 /* Clear status before servicing to reduce spurious interrupts */ 1385 if (ring->index == DESC_INDEX) 1386 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1387 INTRL2_CPU_CLEAR); 1388 else 1389 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1390 INTRL2_CPU_CLEAR); 1391 1392 /* Compute how many buffers are transmitted since last xmit call */ 1393 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1394 & DMA_C_INDEX_MASK; 1395 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1396 1397 netif_dbg(priv, tx_done, dev, 1398 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1399 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1400 1401 /* Reclaim transmitted buffers */ 1402 while (txbds_processed < txbds_ready) { 1403 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1404 &priv->tx_cbs[ring->clean_ptr]); 1405 if (skb) { 1406 pkts_compl++; 1407 bytes_compl += GENET_CB(skb)->bytes_sent; 1408 dev_consume_skb_any(skb); 1409 } 1410 1411 txbds_processed++; 1412 if (likely(ring->clean_ptr < ring->end_ptr)) 1413 ring->clean_ptr++; 1414 else 1415 ring->clean_ptr = ring->cb_ptr; 1416 } 1417 1418 ring->free_bds += txbds_processed; 1419 ring->c_index = c_index; 1420 1421 ring->packets += pkts_compl; 1422 ring->bytes += bytes_compl; 1423 1424 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1425 pkts_compl, bytes_compl); 1426 1427 return txbds_processed; 1428 } 1429 1430 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1431 struct bcmgenet_tx_ring *ring) 1432 { 1433 unsigned int released; 1434 1435 spin_lock_bh(&ring->lock); 1436 released = __bcmgenet_tx_reclaim(dev, ring); 1437 spin_unlock_bh(&ring->lock); 1438 1439 return released; 1440 } 1441 1442 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1443 { 1444 struct bcmgenet_tx_ring *ring = 1445 container_of(napi, struct bcmgenet_tx_ring, napi); 1446 unsigned int work_done = 0; 1447 struct netdev_queue *txq; 1448 1449 spin_lock(&ring->lock); 1450 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1451 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1452 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1453 netif_tx_wake_queue(txq); 1454 } 1455 spin_unlock(&ring->lock); 1456 1457 if (work_done == 0) { 1458 napi_complete(napi); 1459 ring->int_enable(ring); 1460 1461 return 0; 1462 } 1463 1464 return budget; 1465 } 1466 1467 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1468 { 1469 struct bcmgenet_priv *priv = netdev_priv(dev); 1470 int i; 1471 1472 if (netif_is_multiqueue(dev)) { 1473 for (i = 0; i < priv->hw_params->tx_queues; i++) 1474 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1475 } 1476 1477 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1478 } 1479 1480 /* Reallocate the SKB to put enough headroom in front of it and insert 1481 * the transmit checksum offsets in the descriptors 1482 */ 1483 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev, 1484 struct sk_buff *skb) 1485 { 1486 struct status_64 *status = NULL; 1487 struct sk_buff *new_skb; 1488 u16 offset; 1489 u8 ip_proto; 1490 __be16 ip_ver; 1491 u32 tx_csum_info; 1492 1493 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1494 /* If 64 byte status block enabled, must make sure skb has 1495 * enough headroom for us to insert 64B status block. 1496 */ 1497 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1498 dev_kfree_skb(skb); 1499 if (!new_skb) { 1500 dev->stats.tx_dropped++; 1501 return NULL; 1502 } 1503 skb = new_skb; 1504 } 1505 1506 skb_push(skb, sizeof(*status)); 1507 status = (struct status_64 *)skb->data; 1508 1509 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1510 ip_ver = skb->protocol; 1511 switch (ip_ver) { 1512 case htons(ETH_P_IP): 1513 ip_proto = ip_hdr(skb)->protocol; 1514 break; 1515 case htons(ETH_P_IPV6): 1516 ip_proto = ipv6_hdr(skb)->nexthdr; 1517 break; 1518 default: 1519 return skb; 1520 } 1521 1522 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1523 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1524 (offset + skb->csum_offset); 1525 1526 /* Set the length valid bit for TCP and UDP and just set 1527 * the special UDP flag for IPv4, else just set to 0. 1528 */ 1529 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 1530 tx_csum_info |= STATUS_TX_CSUM_LV; 1531 if (ip_proto == IPPROTO_UDP && 1532 ip_ver == htons(ETH_P_IP)) 1533 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1534 } else { 1535 tx_csum_info = 0; 1536 } 1537 1538 status->tx_csum_info = tx_csum_info; 1539 } 1540 1541 return skb; 1542 } 1543 1544 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1545 { 1546 struct bcmgenet_priv *priv = netdev_priv(dev); 1547 struct device *kdev = &priv->pdev->dev; 1548 struct bcmgenet_tx_ring *ring = NULL; 1549 struct enet_cb *tx_cb_ptr; 1550 struct netdev_queue *txq; 1551 int nr_frags, index; 1552 dma_addr_t mapping; 1553 unsigned int size; 1554 skb_frag_t *frag; 1555 u32 len_stat; 1556 int ret; 1557 int i; 1558 1559 index = skb_get_queue_mapping(skb); 1560 /* Mapping strategy: 1561 * queue_mapping = 0, unclassified, packet xmited through ring16 1562 * queue_mapping = 1, goes to ring 0. (highest priority queue 1563 * queue_mapping = 2, goes to ring 1. 1564 * queue_mapping = 3, goes to ring 2. 1565 * queue_mapping = 4, goes to ring 3. 1566 */ 1567 if (index == 0) 1568 index = DESC_INDEX; 1569 else 1570 index -= 1; 1571 1572 ring = &priv->tx_rings[index]; 1573 txq = netdev_get_tx_queue(dev, ring->queue); 1574 1575 nr_frags = skb_shinfo(skb)->nr_frags; 1576 1577 spin_lock(&ring->lock); 1578 if (ring->free_bds <= (nr_frags + 1)) { 1579 if (!netif_tx_queue_stopped(txq)) { 1580 netif_tx_stop_queue(txq); 1581 netdev_err(dev, 1582 "%s: tx ring %d full when queue %d awake\n", 1583 __func__, index, ring->queue); 1584 } 1585 ret = NETDEV_TX_BUSY; 1586 goto out; 1587 } 1588 1589 if (skb_padto(skb, ETH_ZLEN)) { 1590 ret = NETDEV_TX_OK; 1591 goto out; 1592 } 1593 1594 /* Retain how many bytes will be sent on the wire, without TSB inserted 1595 * by transmit checksum offload 1596 */ 1597 GENET_CB(skb)->bytes_sent = skb->len; 1598 1599 /* set the SKB transmit checksum */ 1600 if (priv->desc_64b_en) { 1601 skb = bcmgenet_put_tx_csum(dev, skb); 1602 if (!skb) { 1603 ret = NETDEV_TX_OK; 1604 goto out; 1605 } 1606 } 1607 1608 for (i = 0; i <= nr_frags; i++) { 1609 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1610 1611 BUG_ON(!tx_cb_ptr); 1612 1613 if (!i) { 1614 /* Transmit single SKB or head of fragment list */ 1615 GENET_CB(skb)->first_cb = tx_cb_ptr; 1616 size = skb_headlen(skb); 1617 mapping = dma_map_single(kdev, skb->data, size, 1618 DMA_TO_DEVICE); 1619 } else { 1620 /* xmit fragment */ 1621 frag = &skb_shinfo(skb)->frags[i - 1]; 1622 size = skb_frag_size(frag); 1623 mapping = skb_frag_dma_map(kdev, frag, 0, size, 1624 DMA_TO_DEVICE); 1625 } 1626 1627 ret = dma_mapping_error(kdev, mapping); 1628 if (ret) { 1629 priv->mib.tx_dma_failed++; 1630 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 1631 ret = NETDEV_TX_OK; 1632 goto out_unmap_frags; 1633 } 1634 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1635 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 1636 1637 tx_cb_ptr->skb = skb; 1638 1639 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 1640 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 1641 1642 if (!i) { 1643 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 1644 if (skb->ip_summed == CHECKSUM_PARTIAL) 1645 len_stat |= DMA_TX_DO_CSUM; 1646 } 1647 if (i == nr_frags) 1648 len_stat |= DMA_EOP; 1649 1650 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 1651 } 1652 1653 GENET_CB(skb)->last_cb = tx_cb_ptr; 1654 skb_tx_timestamp(skb); 1655 1656 /* Decrement total BD count and advance our write pointer */ 1657 ring->free_bds -= nr_frags + 1; 1658 ring->prod_index += nr_frags + 1; 1659 ring->prod_index &= DMA_P_INDEX_MASK; 1660 1661 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 1662 1663 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 1664 netif_tx_stop_queue(txq); 1665 1666 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 1667 /* Packets are ready, update producer index */ 1668 bcmgenet_tdma_ring_writel(priv, ring->index, 1669 ring->prod_index, TDMA_PROD_INDEX); 1670 out: 1671 spin_unlock(&ring->lock); 1672 1673 return ret; 1674 1675 out_unmap_frags: 1676 /* Back up for failed control block mapping */ 1677 bcmgenet_put_txcb(priv, ring); 1678 1679 /* Unmap successfully mapped control blocks */ 1680 while (i-- > 0) { 1681 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 1682 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 1683 } 1684 1685 dev_kfree_skb(skb); 1686 goto out; 1687 } 1688 1689 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 1690 struct enet_cb *cb) 1691 { 1692 struct device *kdev = &priv->pdev->dev; 1693 struct sk_buff *skb; 1694 struct sk_buff *rx_skb; 1695 dma_addr_t mapping; 1696 1697 /* Allocate a new Rx skb */ 1698 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); 1699 if (!skb) { 1700 priv->mib.alloc_rx_buff_failed++; 1701 netif_err(priv, rx_err, priv->dev, 1702 "%s: Rx skb allocation failed\n", __func__); 1703 return NULL; 1704 } 1705 1706 /* DMA-map the new Rx skb */ 1707 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 1708 DMA_FROM_DEVICE); 1709 if (dma_mapping_error(kdev, mapping)) { 1710 priv->mib.rx_dma_failed++; 1711 dev_kfree_skb_any(skb); 1712 netif_err(priv, rx_err, priv->dev, 1713 "%s: Rx skb DMA mapping failed\n", __func__); 1714 return NULL; 1715 } 1716 1717 /* Grab the current Rx skb from the ring and DMA-unmap it */ 1718 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 1719 1720 /* Put the new Rx skb on the ring */ 1721 cb->skb = skb; 1722 dma_unmap_addr_set(cb, dma_addr, mapping); 1723 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 1724 dmadesc_set_addr(priv, cb->bd_addr, mapping); 1725 1726 /* Return the current Rx skb to caller */ 1727 return rx_skb; 1728 } 1729 1730 /* bcmgenet_desc_rx - descriptor based rx process. 1731 * this could be called from bottom half, or from NAPI polling method. 1732 */ 1733 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 1734 unsigned int budget) 1735 { 1736 struct bcmgenet_priv *priv = ring->priv; 1737 struct net_device *dev = priv->dev; 1738 struct enet_cb *cb; 1739 struct sk_buff *skb; 1740 u32 dma_length_status; 1741 unsigned long dma_flag; 1742 int len; 1743 unsigned int rxpktprocessed = 0, rxpkttoprocess; 1744 unsigned int bytes_processed = 0; 1745 unsigned int p_index, mask; 1746 unsigned int discards; 1747 unsigned int chksum_ok = 0; 1748 1749 /* Clear status before servicing to reduce spurious interrupts */ 1750 if (ring->index == DESC_INDEX) { 1751 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 1752 INTRL2_CPU_CLEAR); 1753 } else { 1754 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 1755 bcmgenet_intrl2_1_writel(priv, 1756 mask, 1757 INTRL2_CPU_CLEAR); 1758 } 1759 1760 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 1761 1762 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 1763 DMA_P_INDEX_DISCARD_CNT_MASK; 1764 if (discards > ring->old_discards) { 1765 discards = discards - ring->old_discards; 1766 ring->errors += discards; 1767 ring->old_discards += discards; 1768 1769 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 1770 if (ring->old_discards >= 0xC000) { 1771 ring->old_discards = 0; 1772 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 1773 RDMA_PROD_INDEX); 1774 } 1775 } 1776 1777 p_index &= DMA_P_INDEX_MASK; 1778 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 1779 1780 netif_dbg(priv, rx_status, dev, 1781 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 1782 1783 while ((rxpktprocessed < rxpkttoprocess) && 1784 (rxpktprocessed < budget)) { 1785 cb = &priv->rx_cbs[ring->read_ptr]; 1786 skb = bcmgenet_rx_refill(priv, cb); 1787 1788 if (unlikely(!skb)) { 1789 ring->dropped++; 1790 goto next; 1791 } 1792 1793 if (!priv->desc_64b_en) { 1794 dma_length_status = 1795 dmadesc_get_length_status(priv, cb->bd_addr); 1796 } else { 1797 struct status_64 *status; 1798 1799 status = (struct status_64 *)skb->data; 1800 dma_length_status = status->length_status; 1801 } 1802 1803 /* DMA flags and length are still valid no matter how 1804 * we got the Receive Status Vector (64B RSB or register) 1805 */ 1806 dma_flag = dma_length_status & 0xffff; 1807 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 1808 1809 netif_dbg(priv, rx_status, dev, 1810 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 1811 __func__, p_index, ring->c_index, 1812 ring->read_ptr, dma_length_status); 1813 1814 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 1815 netif_err(priv, rx_status, dev, 1816 "dropping fragmented packet!\n"); 1817 ring->errors++; 1818 dev_kfree_skb_any(skb); 1819 goto next; 1820 } 1821 1822 /* report errors */ 1823 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 1824 DMA_RX_OV | 1825 DMA_RX_NO | 1826 DMA_RX_LG | 1827 DMA_RX_RXER))) { 1828 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 1829 (unsigned int)dma_flag); 1830 if (dma_flag & DMA_RX_CRC_ERROR) 1831 dev->stats.rx_crc_errors++; 1832 if (dma_flag & DMA_RX_OV) 1833 dev->stats.rx_over_errors++; 1834 if (dma_flag & DMA_RX_NO) 1835 dev->stats.rx_frame_errors++; 1836 if (dma_flag & DMA_RX_LG) 1837 dev->stats.rx_length_errors++; 1838 dev->stats.rx_errors++; 1839 dev_kfree_skb_any(skb); 1840 goto next; 1841 } /* error packet */ 1842 1843 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) && 1844 priv->desc_rxchk_en; 1845 1846 skb_put(skb, len); 1847 if (priv->desc_64b_en) { 1848 skb_pull(skb, 64); 1849 len -= 64; 1850 } 1851 1852 if (likely(chksum_ok)) 1853 skb->ip_summed = CHECKSUM_UNNECESSARY; 1854 1855 /* remove hardware 2bytes added for IP alignment */ 1856 skb_pull(skb, 2); 1857 len -= 2; 1858 1859 if (priv->crc_fwd_en) { 1860 skb_trim(skb, len - ETH_FCS_LEN); 1861 len -= ETH_FCS_LEN; 1862 } 1863 1864 bytes_processed += len; 1865 1866 /*Finish setting up the received SKB and send it to the kernel*/ 1867 skb->protocol = eth_type_trans(skb, priv->dev); 1868 ring->packets++; 1869 ring->bytes += len; 1870 if (dma_flag & DMA_RX_MULT) 1871 dev->stats.multicast++; 1872 1873 /* Notify kernel */ 1874 napi_gro_receive(&ring->napi, skb); 1875 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 1876 1877 next: 1878 rxpktprocessed++; 1879 if (likely(ring->read_ptr < ring->end_ptr)) 1880 ring->read_ptr++; 1881 else 1882 ring->read_ptr = ring->cb_ptr; 1883 1884 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 1885 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 1886 } 1887 1888 ring->dim.bytes = bytes_processed; 1889 ring->dim.packets = rxpktprocessed; 1890 1891 return rxpktprocessed; 1892 } 1893 1894 /* Rx NAPI polling method */ 1895 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 1896 { 1897 struct bcmgenet_rx_ring *ring = container_of(napi, 1898 struct bcmgenet_rx_ring, napi); 1899 struct dim_sample dim_sample = {}; 1900 unsigned int work_done; 1901 1902 work_done = bcmgenet_desc_rx(ring, budget); 1903 1904 if (work_done < budget) { 1905 napi_complete_done(napi, work_done); 1906 ring->int_enable(ring); 1907 } 1908 1909 if (ring->dim.use_dim) { 1910 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 1911 ring->dim.bytes, &dim_sample); 1912 net_dim(&ring->dim.dim, dim_sample); 1913 } 1914 1915 return work_done; 1916 } 1917 1918 static void bcmgenet_dim_work(struct work_struct *work) 1919 { 1920 struct dim *dim = container_of(work, struct dim, work); 1921 struct bcmgenet_net_dim *ndim = 1922 container_of(dim, struct bcmgenet_net_dim, dim); 1923 struct bcmgenet_rx_ring *ring = 1924 container_of(ndim, struct bcmgenet_rx_ring, dim); 1925 struct dim_cq_moder cur_profile = 1926 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1927 1928 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 1929 dim->state = DIM_START_MEASURE; 1930 } 1931 1932 /* Assign skb to RX DMA descriptor. */ 1933 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 1934 struct bcmgenet_rx_ring *ring) 1935 { 1936 struct enet_cb *cb; 1937 struct sk_buff *skb; 1938 int i; 1939 1940 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 1941 1942 /* loop here for each buffer needing assign */ 1943 for (i = 0; i < ring->size; i++) { 1944 cb = ring->cbs + i; 1945 skb = bcmgenet_rx_refill(priv, cb); 1946 if (skb) 1947 dev_consume_skb_any(skb); 1948 if (!cb->skb) 1949 return -ENOMEM; 1950 } 1951 1952 return 0; 1953 } 1954 1955 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 1956 { 1957 struct sk_buff *skb; 1958 struct enet_cb *cb; 1959 int i; 1960 1961 for (i = 0; i < priv->num_rx_bds; i++) { 1962 cb = &priv->rx_cbs[i]; 1963 1964 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 1965 if (skb) 1966 dev_consume_skb_any(skb); 1967 } 1968 } 1969 1970 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 1971 { 1972 u32 reg; 1973 1974 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1975 if (enable) 1976 reg |= mask; 1977 else 1978 reg &= ~mask; 1979 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 1980 1981 /* UniMAC stops on a packet boundary, wait for a full-size packet 1982 * to be processed 1983 */ 1984 if (enable == 0) 1985 usleep_range(1000, 2000); 1986 } 1987 1988 static void reset_umac(struct bcmgenet_priv *priv) 1989 { 1990 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 1991 bcmgenet_rbuf_ctrl_set(priv, 0); 1992 udelay(10); 1993 1994 /* disable MAC while updating its registers */ 1995 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1996 1997 /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ 1998 bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD); 1999 } 2000 2001 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2002 { 2003 /* Mask all interrupts.*/ 2004 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2005 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2006 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2007 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2008 } 2009 2010 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2011 { 2012 u32 int0_enable = 0; 2013 2014 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2015 * and MoCA PHY 2016 */ 2017 if (priv->internal_phy) { 2018 int0_enable |= UMAC_IRQ_LINK_EVENT; 2019 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2020 int0_enable |= UMAC_IRQ_PHY_DET_R; 2021 } else if (priv->ext_phy) { 2022 int0_enable |= UMAC_IRQ_LINK_EVENT; 2023 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2024 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 2025 int0_enable |= UMAC_IRQ_LINK_EVENT; 2026 } 2027 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2028 } 2029 2030 static void init_umac(struct bcmgenet_priv *priv) 2031 { 2032 struct device *kdev = &priv->pdev->dev; 2033 u32 reg; 2034 u32 int0_enable = 0; 2035 2036 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2037 2038 reset_umac(priv); 2039 2040 /* clear tx/rx counter */ 2041 bcmgenet_umac_writel(priv, 2042 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2043 UMAC_MIB_CTRL); 2044 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2045 2046 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2047 2048 /* init rx registers, enable ip header optimization */ 2049 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2050 reg |= RBUF_ALIGN_2B; 2051 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2052 2053 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2054 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2055 2056 bcmgenet_intr_disable(priv); 2057 2058 /* Configure backpressure vectors for MoCA */ 2059 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2060 reg = bcmgenet_bp_mc_get(priv); 2061 reg |= BIT(priv->hw_params->bp_in_en_shift); 2062 2063 /* bp_mask: back pressure mask */ 2064 if (netif_is_multiqueue(priv->dev)) 2065 reg |= priv->hw_params->bp_in_mask; 2066 else 2067 reg &= ~priv->hw_params->bp_in_mask; 2068 bcmgenet_bp_mc_set(priv, reg); 2069 } 2070 2071 /* Enable MDIO interrupts on GENET v3+ */ 2072 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2073 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2074 2075 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2076 2077 dev_dbg(kdev, "done init umac\n"); 2078 } 2079 2080 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2081 void (*cb)(struct work_struct *work)) 2082 { 2083 struct bcmgenet_net_dim *dim = &ring->dim; 2084 2085 INIT_WORK(&dim->dim.work, cb); 2086 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2087 dim->event_ctr = 0; 2088 dim->packets = 0; 2089 dim->bytes = 0; 2090 } 2091 2092 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2093 { 2094 struct bcmgenet_net_dim *dim = &ring->dim; 2095 struct dim_cq_moder moder; 2096 u32 usecs, pkts; 2097 2098 usecs = ring->rx_coalesce_usecs; 2099 pkts = ring->rx_max_coalesced_frames; 2100 2101 /* If DIM was enabled, re-apply default parameters */ 2102 if (dim->use_dim) { 2103 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2104 usecs = moder.usec; 2105 pkts = moder.pkts; 2106 } 2107 2108 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2109 } 2110 2111 /* Initialize a Tx ring along with corresponding hardware registers */ 2112 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2113 unsigned int index, unsigned int size, 2114 unsigned int start_ptr, unsigned int end_ptr) 2115 { 2116 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2117 u32 words_per_bd = WORDS_PER_BD(priv); 2118 u32 flow_period_val = 0; 2119 2120 spin_lock_init(&ring->lock); 2121 ring->priv = priv; 2122 ring->index = index; 2123 if (index == DESC_INDEX) { 2124 ring->queue = 0; 2125 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2126 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2127 } else { 2128 ring->queue = index + 1; 2129 ring->int_enable = bcmgenet_tx_ring_int_enable; 2130 ring->int_disable = bcmgenet_tx_ring_int_disable; 2131 } 2132 ring->cbs = priv->tx_cbs + start_ptr; 2133 ring->size = size; 2134 ring->clean_ptr = start_ptr; 2135 ring->c_index = 0; 2136 ring->free_bds = size; 2137 ring->write_ptr = start_ptr; 2138 ring->cb_ptr = start_ptr; 2139 ring->end_ptr = end_ptr - 1; 2140 ring->prod_index = 0; 2141 2142 /* Set flow period for ring != 16 */ 2143 if (index != DESC_INDEX) 2144 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2145 2146 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2147 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2148 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2149 /* Disable rate control for now */ 2150 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2151 TDMA_FLOW_PERIOD); 2152 bcmgenet_tdma_ring_writel(priv, index, 2153 ((size << DMA_RING_SIZE_SHIFT) | 2154 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2155 2156 /* Set start and end address, read and write pointers */ 2157 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2158 DMA_START_ADDR); 2159 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2160 TDMA_READ_PTR); 2161 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2162 TDMA_WRITE_PTR); 2163 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2164 DMA_END_ADDR); 2165 2166 /* Initialize Tx NAPI */ 2167 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 2168 NAPI_POLL_WEIGHT); 2169 } 2170 2171 /* Initialize a RDMA ring */ 2172 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2173 unsigned int index, unsigned int size, 2174 unsigned int start_ptr, unsigned int end_ptr) 2175 { 2176 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2177 u32 words_per_bd = WORDS_PER_BD(priv); 2178 int ret; 2179 2180 ring->priv = priv; 2181 ring->index = index; 2182 if (index == DESC_INDEX) { 2183 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2184 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2185 } else { 2186 ring->int_enable = bcmgenet_rx_ring_int_enable; 2187 ring->int_disable = bcmgenet_rx_ring_int_disable; 2188 } 2189 ring->cbs = priv->rx_cbs + start_ptr; 2190 ring->size = size; 2191 ring->c_index = 0; 2192 ring->read_ptr = start_ptr; 2193 ring->cb_ptr = start_ptr; 2194 ring->end_ptr = end_ptr - 1; 2195 2196 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2197 if (ret) 2198 return ret; 2199 2200 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2201 bcmgenet_init_rx_coalesce(ring); 2202 2203 /* Initialize Rx NAPI */ 2204 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 2205 NAPI_POLL_WEIGHT); 2206 2207 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2208 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2209 bcmgenet_rdma_ring_writel(priv, index, 2210 ((size << DMA_RING_SIZE_SHIFT) | 2211 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2212 bcmgenet_rdma_ring_writel(priv, index, 2213 (DMA_FC_THRESH_LO << 2214 DMA_XOFF_THRESHOLD_SHIFT) | 2215 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2216 2217 /* Set start and end address, read and write pointers */ 2218 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2219 DMA_START_ADDR); 2220 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2221 RDMA_READ_PTR); 2222 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2223 RDMA_WRITE_PTR); 2224 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2225 DMA_END_ADDR); 2226 2227 return ret; 2228 } 2229 2230 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2231 { 2232 unsigned int i; 2233 struct bcmgenet_tx_ring *ring; 2234 2235 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2236 ring = &priv->tx_rings[i]; 2237 napi_enable(&ring->napi); 2238 ring->int_enable(ring); 2239 } 2240 2241 ring = &priv->tx_rings[DESC_INDEX]; 2242 napi_enable(&ring->napi); 2243 ring->int_enable(ring); 2244 } 2245 2246 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2247 { 2248 unsigned int i; 2249 struct bcmgenet_tx_ring *ring; 2250 2251 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2252 ring = &priv->tx_rings[i]; 2253 napi_disable(&ring->napi); 2254 } 2255 2256 ring = &priv->tx_rings[DESC_INDEX]; 2257 napi_disable(&ring->napi); 2258 } 2259 2260 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2261 { 2262 unsigned int i; 2263 struct bcmgenet_tx_ring *ring; 2264 2265 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2266 ring = &priv->tx_rings[i]; 2267 netif_napi_del(&ring->napi); 2268 } 2269 2270 ring = &priv->tx_rings[DESC_INDEX]; 2271 netif_napi_del(&ring->napi); 2272 } 2273 2274 /* Initialize Tx queues 2275 * 2276 * Queues 0-3 are priority-based, each one has 32 descriptors, 2277 * with queue 0 being the highest priority queue. 2278 * 2279 * Queue 16 is the default Tx queue with 2280 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2281 * 2282 * The transmit control block pool is then partitioned as follows: 2283 * - Tx queue 0 uses tx_cbs[0..31] 2284 * - Tx queue 1 uses tx_cbs[32..63] 2285 * - Tx queue 2 uses tx_cbs[64..95] 2286 * - Tx queue 3 uses tx_cbs[96..127] 2287 * - Tx queue 16 uses tx_cbs[128..255] 2288 */ 2289 static void bcmgenet_init_tx_queues(struct net_device *dev) 2290 { 2291 struct bcmgenet_priv *priv = netdev_priv(dev); 2292 u32 i, dma_enable; 2293 u32 dma_ctrl, ring_cfg; 2294 u32 dma_priority[3] = {0, 0, 0}; 2295 2296 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2297 dma_enable = dma_ctrl & DMA_EN; 2298 dma_ctrl &= ~DMA_EN; 2299 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2300 2301 dma_ctrl = 0; 2302 ring_cfg = 0; 2303 2304 /* Enable strict priority arbiter mode */ 2305 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2306 2307 /* Initialize Tx priority queues */ 2308 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2309 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2310 i * priv->hw_params->tx_bds_per_q, 2311 (i + 1) * priv->hw_params->tx_bds_per_q); 2312 ring_cfg |= (1 << i); 2313 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2314 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2315 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2316 } 2317 2318 /* Initialize Tx default queue 16 */ 2319 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2320 priv->hw_params->tx_queues * 2321 priv->hw_params->tx_bds_per_q, 2322 TOTAL_DESC); 2323 ring_cfg |= (1 << DESC_INDEX); 2324 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2325 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2326 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2327 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2328 2329 /* Set Tx queue priorities */ 2330 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2331 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2332 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2333 2334 /* Enable Tx queues */ 2335 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2336 2337 /* Enable Tx DMA */ 2338 if (dma_enable) 2339 dma_ctrl |= DMA_EN; 2340 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2341 } 2342 2343 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2344 { 2345 unsigned int i; 2346 struct bcmgenet_rx_ring *ring; 2347 2348 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2349 ring = &priv->rx_rings[i]; 2350 napi_enable(&ring->napi); 2351 ring->int_enable(ring); 2352 } 2353 2354 ring = &priv->rx_rings[DESC_INDEX]; 2355 napi_enable(&ring->napi); 2356 ring->int_enable(ring); 2357 } 2358 2359 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2360 { 2361 unsigned int i; 2362 struct bcmgenet_rx_ring *ring; 2363 2364 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2365 ring = &priv->rx_rings[i]; 2366 napi_disable(&ring->napi); 2367 cancel_work_sync(&ring->dim.dim.work); 2368 } 2369 2370 ring = &priv->rx_rings[DESC_INDEX]; 2371 napi_disable(&ring->napi); 2372 cancel_work_sync(&ring->dim.dim.work); 2373 } 2374 2375 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2376 { 2377 unsigned int i; 2378 struct bcmgenet_rx_ring *ring; 2379 2380 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2381 ring = &priv->rx_rings[i]; 2382 netif_napi_del(&ring->napi); 2383 } 2384 2385 ring = &priv->rx_rings[DESC_INDEX]; 2386 netif_napi_del(&ring->napi); 2387 } 2388 2389 /* Initialize Rx queues 2390 * 2391 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2392 * used to direct traffic to these queues. 2393 * 2394 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2395 */ 2396 static int bcmgenet_init_rx_queues(struct net_device *dev) 2397 { 2398 struct bcmgenet_priv *priv = netdev_priv(dev); 2399 u32 i; 2400 u32 dma_enable; 2401 u32 dma_ctrl; 2402 u32 ring_cfg; 2403 int ret; 2404 2405 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2406 dma_enable = dma_ctrl & DMA_EN; 2407 dma_ctrl &= ~DMA_EN; 2408 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2409 2410 dma_ctrl = 0; 2411 ring_cfg = 0; 2412 2413 /* Initialize Rx priority queues */ 2414 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2415 ret = bcmgenet_init_rx_ring(priv, i, 2416 priv->hw_params->rx_bds_per_q, 2417 i * priv->hw_params->rx_bds_per_q, 2418 (i + 1) * 2419 priv->hw_params->rx_bds_per_q); 2420 if (ret) 2421 return ret; 2422 2423 ring_cfg |= (1 << i); 2424 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2425 } 2426 2427 /* Initialize Rx default queue 16 */ 2428 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2429 priv->hw_params->rx_queues * 2430 priv->hw_params->rx_bds_per_q, 2431 TOTAL_DESC); 2432 if (ret) 2433 return ret; 2434 2435 ring_cfg |= (1 << DESC_INDEX); 2436 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2437 2438 /* Enable rings */ 2439 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2440 2441 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2442 if (dma_enable) 2443 dma_ctrl |= DMA_EN; 2444 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2445 2446 return 0; 2447 } 2448 2449 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2450 { 2451 int ret = 0; 2452 int timeout = 0; 2453 u32 reg; 2454 u32 dma_ctrl; 2455 int i; 2456 2457 /* Disable TDMA to stop add more frames in TX DMA */ 2458 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2459 reg &= ~DMA_EN; 2460 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2461 2462 /* Check TDMA status register to confirm TDMA is disabled */ 2463 while (timeout++ < DMA_TIMEOUT_VAL) { 2464 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2465 if (reg & DMA_DISABLED) 2466 break; 2467 2468 udelay(1); 2469 } 2470 2471 if (timeout == DMA_TIMEOUT_VAL) { 2472 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2473 ret = -ETIMEDOUT; 2474 } 2475 2476 /* Wait 10ms for packet drain in both tx and rx dma */ 2477 usleep_range(10000, 20000); 2478 2479 /* Disable RDMA */ 2480 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2481 reg &= ~DMA_EN; 2482 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2483 2484 timeout = 0; 2485 /* Check RDMA status register to confirm RDMA is disabled */ 2486 while (timeout++ < DMA_TIMEOUT_VAL) { 2487 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2488 if (reg & DMA_DISABLED) 2489 break; 2490 2491 udelay(1); 2492 } 2493 2494 if (timeout == DMA_TIMEOUT_VAL) { 2495 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2496 ret = -ETIMEDOUT; 2497 } 2498 2499 dma_ctrl = 0; 2500 for (i = 0; i < priv->hw_params->rx_queues; i++) 2501 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2502 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2503 reg &= ~dma_ctrl; 2504 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2505 2506 dma_ctrl = 0; 2507 for (i = 0; i < priv->hw_params->tx_queues; i++) 2508 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2509 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2510 reg &= ~dma_ctrl; 2511 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2512 2513 return ret; 2514 } 2515 2516 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2517 { 2518 struct netdev_queue *txq; 2519 int i; 2520 2521 bcmgenet_fini_rx_napi(priv); 2522 bcmgenet_fini_tx_napi(priv); 2523 2524 for (i = 0; i < priv->num_tx_bds; i++) 2525 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev, 2526 priv->tx_cbs + i)); 2527 2528 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2529 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2530 netdev_tx_reset_queue(txq); 2531 } 2532 2533 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 2534 netdev_tx_reset_queue(txq); 2535 2536 bcmgenet_free_rx_buffers(priv); 2537 kfree(priv->rx_cbs); 2538 kfree(priv->tx_cbs); 2539 } 2540 2541 /* init_edma: Initialize DMA control register */ 2542 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 2543 { 2544 int ret; 2545 unsigned int i; 2546 struct enet_cb *cb; 2547 2548 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2549 2550 /* Initialize common Rx ring structures */ 2551 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 2552 priv->num_rx_bds = TOTAL_DESC; 2553 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 2554 GFP_KERNEL); 2555 if (!priv->rx_cbs) 2556 return -ENOMEM; 2557 2558 for (i = 0; i < priv->num_rx_bds; i++) { 2559 cb = priv->rx_cbs + i; 2560 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 2561 } 2562 2563 /* Initialize common TX ring structures */ 2564 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 2565 priv->num_tx_bds = TOTAL_DESC; 2566 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 2567 GFP_KERNEL); 2568 if (!priv->tx_cbs) { 2569 kfree(priv->rx_cbs); 2570 return -ENOMEM; 2571 } 2572 2573 for (i = 0; i < priv->num_tx_bds; i++) { 2574 cb = priv->tx_cbs + i; 2575 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 2576 } 2577 2578 /* Init rDma */ 2579 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 2580 DMA_SCB_BURST_SIZE); 2581 2582 /* Initialize Rx queues */ 2583 ret = bcmgenet_init_rx_queues(priv->dev); 2584 if (ret) { 2585 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 2586 bcmgenet_free_rx_buffers(priv); 2587 kfree(priv->rx_cbs); 2588 kfree(priv->tx_cbs); 2589 return ret; 2590 } 2591 2592 /* Init tDma */ 2593 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 2594 DMA_SCB_BURST_SIZE); 2595 2596 /* Initialize Tx queues */ 2597 bcmgenet_init_tx_queues(priv->dev); 2598 2599 return 0; 2600 } 2601 2602 /* Interrupt bottom half */ 2603 static void bcmgenet_irq_task(struct work_struct *work) 2604 { 2605 unsigned int status; 2606 struct bcmgenet_priv *priv = container_of( 2607 work, struct bcmgenet_priv, bcmgenet_irq_work); 2608 2609 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 2610 2611 spin_lock_irq(&priv->lock); 2612 status = priv->irq0_stat; 2613 priv->irq0_stat = 0; 2614 spin_unlock_irq(&priv->lock); 2615 2616 if (status & UMAC_IRQ_PHY_DET_R && 2617 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 2618 phy_init_hw(priv->dev->phydev); 2619 genphy_config_aneg(priv->dev->phydev); 2620 } 2621 2622 /* Link UP/DOWN event */ 2623 if (status & UMAC_IRQ_LINK_EVENT) 2624 phy_mac_interrupt(priv->dev->phydev); 2625 2626 } 2627 2628 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 2629 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 2630 { 2631 struct bcmgenet_priv *priv = dev_id; 2632 struct bcmgenet_rx_ring *rx_ring; 2633 struct bcmgenet_tx_ring *tx_ring; 2634 unsigned int index, status; 2635 2636 /* Read irq status */ 2637 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 2638 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2639 2640 /* clear interrupts */ 2641 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 2642 2643 netif_dbg(priv, intr, priv->dev, 2644 "%s: IRQ=0x%x\n", __func__, status); 2645 2646 /* Check Rx priority queue interrupts */ 2647 for (index = 0; index < priv->hw_params->rx_queues; index++) { 2648 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 2649 continue; 2650 2651 rx_ring = &priv->rx_rings[index]; 2652 rx_ring->dim.event_ctr++; 2653 2654 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2655 rx_ring->int_disable(rx_ring); 2656 __napi_schedule_irqoff(&rx_ring->napi); 2657 } 2658 } 2659 2660 /* Check Tx priority queue interrupts */ 2661 for (index = 0; index < priv->hw_params->tx_queues; index++) { 2662 if (!(status & BIT(index))) 2663 continue; 2664 2665 tx_ring = &priv->tx_rings[index]; 2666 2667 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2668 tx_ring->int_disable(tx_ring); 2669 __napi_schedule_irqoff(&tx_ring->napi); 2670 } 2671 } 2672 2673 return IRQ_HANDLED; 2674 } 2675 2676 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 2677 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 2678 { 2679 struct bcmgenet_priv *priv = dev_id; 2680 struct bcmgenet_rx_ring *rx_ring; 2681 struct bcmgenet_tx_ring *tx_ring; 2682 unsigned int status; 2683 unsigned long flags; 2684 2685 /* Read irq status */ 2686 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 2687 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2688 2689 /* clear interrupts */ 2690 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 2691 2692 netif_dbg(priv, intr, priv->dev, 2693 "IRQ=0x%x\n", status); 2694 2695 if (status & UMAC_IRQ_RXDMA_DONE) { 2696 rx_ring = &priv->rx_rings[DESC_INDEX]; 2697 rx_ring->dim.event_ctr++; 2698 2699 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2700 rx_ring->int_disable(rx_ring); 2701 __napi_schedule_irqoff(&rx_ring->napi); 2702 } 2703 } 2704 2705 if (status & UMAC_IRQ_TXDMA_DONE) { 2706 tx_ring = &priv->tx_rings[DESC_INDEX]; 2707 2708 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2709 tx_ring->int_disable(tx_ring); 2710 __napi_schedule_irqoff(&tx_ring->napi); 2711 } 2712 } 2713 2714 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 2715 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 2716 wake_up(&priv->wq); 2717 } 2718 2719 /* all other interested interrupts handled in bottom half */ 2720 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 2721 if (status) { 2722 /* Save irq status for bottom-half processing. */ 2723 spin_lock_irqsave(&priv->lock, flags); 2724 priv->irq0_stat |= status; 2725 spin_unlock_irqrestore(&priv->lock, flags); 2726 2727 schedule_work(&priv->bcmgenet_irq_work); 2728 } 2729 2730 return IRQ_HANDLED; 2731 } 2732 2733 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 2734 { 2735 struct bcmgenet_priv *priv = dev_id; 2736 2737 pm_wakeup_event(&priv->pdev->dev, 0); 2738 2739 return IRQ_HANDLED; 2740 } 2741 2742 #ifdef CONFIG_NET_POLL_CONTROLLER 2743 static void bcmgenet_poll_controller(struct net_device *dev) 2744 { 2745 struct bcmgenet_priv *priv = netdev_priv(dev); 2746 2747 /* Invoke the main RX/TX interrupt handler */ 2748 disable_irq(priv->irq0); 2749 bcmgenet_isr0(priv->irq0, priv); 2750 enable_irq(priv->irq0); 2751 2752 /* And the interrupt handler for RX/TX priority queues */ 2753 disable_irq(priv->irq1); 2754 bcmgenet_isr1(priv->irq1, priv); 2755 enable_irq(priv->irq1); 2756 } 2757 #endif 2758 2759 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 2760 { 2761 u32 reg; 2762 2763 reg = bcmgenet_rbuf_ctrl_get(priv); 2764 reg |= BIT(1); 2765 bcmgenet_rbuf_ctrl_set(priv, reg); 2766 udelay(10); 2767 2768 reg &= ~BIT(1); 2769 bcmgenet_rbuf_ctrl_set(priv, reg); 2770 udelay(10); 2771 } 2772 2773 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 2774 unsigned char *addr) 2775 { 2776 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 2777 (addr[2] << 8) | addr[3], UMAC_MAC0); 2778 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 2779 } 2780 2781 /* Returns a reusable dma control register value */ 2782 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 2783 { 2784 u32 reg; 2785 u32 dma_ctrl; 2786 2787 /* disable DMA */ 2788 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2789 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2790 reg &= ~dma_ctrl; 2791 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2792 2793 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2794 reg &= ~dma_ctrl; 2795 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2796 2797 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 2798 udelay(10); 2799 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 2800 2801 return dma_ctrl; 2802 } 2803 2804 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 2805 { 2806 u32 reg; 2807 2808 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2809 reg |= dma_ctrl; 2810 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2811 2812 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2813 reg |= dma_ctrl; 2814 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2815 } 2816 2817 /* bcmgenet_hfb_clear 2818 * 2819 * Clear Hardware Filter Block and disable all filtering. 2820 */ 2821 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 2822 { 2823 u32 i; 2824 2825 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 2826 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 2827 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 2828 2829 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 2830 bcmgenet_rdma_writel(priv, 0x0, i); 2831 2832 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 2833 bcmgenet_hfb_reg_writel(priv, 0x0, 2834 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 2835 2836 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 2837 priv->hw_params->hfb_filter_size; i++) 2838 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 2839 } 2840 2841 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 2842 { 2843 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 2844 return; 2845 2846 bcmgenet_hfb_clear(priv); 2847 } 2848 2849 static void bcmgenet_netif_start(struct net_device *dev) 2850 { 2851 struct bcmgenet_priv *priv = netdev_priv(dev); 2852 2853 /* Start the network engine */ 2854 bcmgenet_enable_rx_napi(priv); 2855 2856 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 2857 2858 bcmgenet_enable_tx_napi(priv); 2859 2860 /* Monitor link interrupts now */ 2861 bcmgenet_link_intr_enable(priv); 2862 2863 phy_start(dev->phydev); 2864 } 2865 2866 static int bcmgenet_open(struct net_device *dev) 2867 { 2868 struct bcmgenet_priv *priv = netdev_priv(dev); 2869 unsigned long dma_ctrl; 2870 u32 reg; 2871 int ret; 2872 2873 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 2874 2875 /* Turn on the clock */ 2876 clk_prepare_enable(priv->clk); 2877 2878 /* If this is an internal GPHY, power it back on now, before UniMAC is 2879 * brought out of reset as absolutely no UniMAC activity is allowed 2880 */ 2881 if (priv->internal_phy) 2882 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 2883 2884 /* take MAC out of reset */ 2885 bcmgenet_umac_reset(priv); 2886 2887 init_umac(priv); 2888 2889 /* Make sure we reflect the value of CRC_CMD_FWD */ 2890 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2891 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 2892 2893 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2894 2895 if (priv->internal_phy) { 2896 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2897 reg |= EXT_ENERGY_DET_MASK; 2898 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2899 } 2900 2901 /* Disable RX/TX DMA and flush TX queues */ 2902 dma_ctrl = bcmgenet_dma_disable(priv); 2903 2904 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2905 ret = bcmgenet_init_dma(priv); 2906 if (ret) { 2907 netdev_err(dev, "failed to initialize DMA\n"); 2908 goto err_clk_disable; 2909 } 2910 2911 /* Always enable ring 16 - descriptor ring */ 2912 bcmgenet_enable_dma(priv, dma_ctrl); 2913 2914 /* HFB init */ 2915 bcmgenet_hfb_init(priv); 2916 2917 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 2918 dev->name, priv); 2919 if (ret < 0) { 2920 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 2921 goto err_fini_dma; 2922 } 2923 2924 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 2925 dev->name, priv); 2926 if (ret < 0) { 2927 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 2928 goto err_irq0; 2929 } 2930 2931 ret = bcmgenet_mii_probe(dev); 2932 if (ret) { 2933 netdev_err(dev, "failed to connect to PHY\n"); 2934 goto err_irq1; 2935 } 2936 2937 bcmgenet_netif_start(dev); 2938 2939 netif_tx_start_all_queues(dev); 2940 2941 return 0; 2942 2943 err_irq1: 2944 free_irq(priv->irq1, priv); 2945 err_irq0: 2946 free_irq(priv->irq0, priv); 2947 err_fini_dma: 2948 bcmgenet_dma_teardown(priv); 2949 bcmgenet_fini_dma(priv); 2950 err_clk_disable: 2951 if (priv->internal_phy) 2952 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2953 clk_disable_unprepare(priv->clk); 2954 return ret; 2955 } 2956 2957 static void bcmgenet_netif_stop(struct net_device *dev) 2958 { 2959 struct bcmgenet_priv *priv = netdev_priv(dev); 2960 2961 bcmgenet_disable_tx_napi(priv); 2962 netif_tx_disable(dev); 2963 2964 /* Disable MAC receive */ 2965 umac_enable_set(priv, CMD_RX_EN, false); 2966 2967 bcmgenet_dma_teardown(priv); 2968 2969 /* Disable MAC transmit. TX DMA disabled must be done before this */ 2970 umac_enable_set(priv, CMD_TX_EN, false); 2971 2972 phy_stop(dev->phydev); 2973 bcmgenet_disable_rx_napi(priv); 2974 bcmgenet_intr_disable(priv); 2975 2976 /* Wait for pending work items to complete. Since interrupts are 2977 * disabled no new work will be scheduled. 2978 */ 2979 cancel_work_sync(&priv->bcmgenet_irq_work); 2980 2981 priv->old_link = -1; 2982 priv->old_speed = -1; 2983 priv->old_duplex = -1; 2984 priv->old_pause = -1; 2985 2986 /* tx reclaim */ 2987 bcmgenet_tx_reclaim_all(dev); 2988 bcmgenet_fini_dma(priv); 2989 } 2990 2991 static int bcmgenet_close(struct net_device *dev) 2992 { 2993 struct bcmgenet_priv *priv = netdev_priv(dev); 2994 int ret = 0; 2995 2996 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 2997 2998 bcmgenet_netif_stop(dev); 2999 3000 /* Really kill the PHY state machine and disconnect from it */ 3001 phy_disconnect(dev->phydev); 3002 3003 free_irq(priv->irq0, priv); 3004 free_irq(priv->irq1, priv); 3005 3006 if (priv->internal_phy) 3007 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3008 3009 clk_disable_unprepare(priv->clk); 3010 3011 return ret; 3012 } 3013 3014 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3015 { 3016 struct bcmgenet_priv *priv = ring->priv; 3017 u32 p_index, c_index, intsts, intmsk; 3018 struct netdev_queue *txq; 3019 unsigned int free_bds; 3020 bool txq_stopped; 3021 3022 if (!netif_msg_tx_err(priv)) 3023 return; 3024 3025 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3026 3027 spin_lock(&ring->lock); 3028 if (ring->index == DESC_INDEX) { 3029 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3030 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3031 } else { 3032 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3033 intmsk = 1 << ring->index; 3034 } 3035 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3036 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3037 txq_stopped = netif_tx_queue_stopped(txq); 3038 free_bds = ring->free_bds; 3039 spin_unlock(&ring->lock); 3040 3041 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3042 "TX queue status: %s, interrupts: %s\n" 3043 "(sw)free_bds: %d (sw)size: %d\n" 3044 "(sw)p_index: %d (hw)p_index: %d\n" 3045 "(sw)c_index: %d (hw)c_index: %d\n" 3046 "(sw)clean_p: %d (sw)write_p: %d\n" 3047 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3048 ring->index, ring->queue, 3049 txq_stopped ? "stopped" : "active", 3050 intsts & intmsk ? "enabled" : "disabled", 3051 free_bds, ring->size, 3052 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3053 ring->c_index, c_index & DMA_C_INDEX_MASK, 3054 ring->clean_ptr, ring->write_ptr, 3055 ring->cb_ptr, ring->end_ptr); 3056 } 3057 3058 static void bcmgenet_timeout(struct net_device *dev) 3059 { 3060 struct bcmgenet_priv *priv = netdev_priv(dev); 3061 u32 int0_enable = 0; 3062 u32 int1_enable = 0; 3063 unsigned int q; 3064 3065 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3066 3067 for (q = 0; q < priv->hw_params->tx_queues; q++) 3068 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3069 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3070 3071 bcmgenet_tx_reclaim_all(dev); 3072 3073 for (q = 0; q < priv->hw_params->tx_queues; q++) 3074 int1_enable |= (1 << q); 3075 3076 int0_enable = UMAC_IRQ_TXDMA_DONE; 3077 3078 /* Re-enable TX interrupts if disabled */ 3079 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3080 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3081 3082 netif_trans_update(dev); 3083 3084 dev->stats.tx_errors++; 3085 3086 netif_tx_wake_all_queues(dev); 3087 } 3088 3089 #define MAX_MDF_FILTER 17 3090 3091 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3092 unsigned char *addr, 3093 int *i) 3094 { 3095 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3096 UMAC_MDF_ADDR + (*i * 4)); 3097 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3098 addr[4] << 8 | addr[5], 3099 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3100 *i += 2; 3101 } 3102 3103 static void bcmgenet_set_rx_mode(struct net_device *dev) 3104 { 3105 struct bcmgenet_priv *priv = netdev_priv(dev); 3106 struct netdev_hw_addr *ha; 3107 int i, nfilter; 3108 u32 reg; 3109 3110 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3111 3112 /* Number of filters needed */ 3113 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3114 3115 /* 3116 * Turn on promicuous mode for three scenarios 3117 * 1. IFF_PROMISC flag is set 3118 * 2. IFF_ALLMULTI flag is set 3119 * 3. The number of filters needed exceeds the number filters 3120 * supported by the hardware. 3121 */ 3122 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3123 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3124 (nfilter > MAX_MDF_FILTER)) { 3125 reg |= CMD_PROMISC; 3126 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3127 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3128 return; 3129 } else { 3130 reg &= ~CMD_PROMISC; 3131 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3132 } 3133 3134 /* update MDF filter */ 3135 i = 0; 3136 /* Broadcast */ 3137 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3138 /* my own address.*/ 3139 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3140 3141 /* Unicast */ 3142 netdev_for_each_uc_addr(ha, dev) 3143 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3144 3145 /* Multicast */ 3146 netdev_for_each_mc_addr(ha, dev) 3147 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3148 3149 /* Enable filters */ 3150 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3151 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3152 } 3153 3154 /* Set the hardware MAC address. */ 3155 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3156 { 3157 struct sockaddr *addr = p; 3158 3159 /* Setting the MAC address at the hardware level is not possible 3160 * without disabling the UniMAC RX/TX enable bits. 3161 */ 3162 if (netif_running(dev)) 3163 return -EBUSY; 3164 3165 ether_addr_copy(dev->dev_addr, addr->sa_data); 3166 3167 return 0; 3168 } 3169 3170 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3171 { 3172 struct bcmgenet_priv *priv = netdev_priv(dev); 3173 unsigned long tx_bytes = 0, tx_packets = 0; 3174 unsigned long rx_bytes = 0, rx_packets = 0; 3175 unsigned long rx_errors = 0, rx_dropped = 0; 3176 struct bcmgenet_tx_ring *tx_ring; 3177 struct bcmgenet_rx_ring *rx_ring; 3178 unsigned int q; 3179 3180 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3181 tx_ring = &priv->tx_rings[q]; 3182 tx_bytes += tx_ring->bytes; 3183 tx_packets += tx_ring->packets; 3184 } 3185 tx_ring = &priv->tx_rings[DESC_INDEX]; 3186 tx_bytes += tx_ring->bytes; 3187 tx_packets += tx_ring->packets; 3188 3189 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3190 rx_ring = &priv->rx_rings[q]; 3191 3192 rx_bytes += rx_ring->bytes; 3193 rx_packets += rx_ring->packets; 3194 rx_errors += rx_ring->errors; 3195 rx_dropped += rx_ring->dropped; 3196 } 3197 rx_ring = &priv->rx_rings[DESC_INDEX]; 3198 rx_bytes += rx_ring->bytes; 3199 rx_packets += rx_ring->packets; 3200 rx_errors += rx_ring->errors; 3201 rx_dropped += rx_ring->dropped; 3202 3203 dev->stats.tx_bytes = tx_bytes; 3204 dev->stats.tx_packets = tx_packets; 3205 dev->stats.rx_bytes = rx_bytes; 3206 dev->stats.rx_packets = rx_packets; 3207 dev->stats.rx_errors = rx_errors; 3208 dev->stats.rx_missed_errors = rx_errors; 3209 return &dev->stats; 3210 } 3211 3212 static const struct net_device_ops bcmgenet_netdev_ops = { 3213 .ndo_open = bcmgenet_open, 3214 .ndo_stop = bcmgenet_close, 3215 .ndo_start_xmit = bcmgenet_xmit, 3216 .ndo_tx_timeout = bcmgenet_timeout, 3217 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3218 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3219 .ndo_do_ioctl = bcmgenet_ioctl, 3220 .ndo_set_features = bcmgenet_set_features, 3221 #ifdef CONFIG_NET_POLL_CONTROLLER 3222 .ndo_poll_controller = bcmgenet_poll_controller, 3223 #endif 3224 .ndo_get_stats = bcmgenet_get_stats, 3225 }; 3226 3227 /* Array of GENET hardware parameters/characteristics */ 3228 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3229 [GENET_V1] = { 3230 .tx_queues = 0, 3231 .tx_bds_per_q = 0, 3232 .rx_queues = 0, 3233 .rx_bds_per_q = 0, 3234 .bp_in_en_shift = 16, 3235 .bp_in_mask = 0xffff, 3236 .hfb_filter_cnt = 16, 3237 .qtag_mask = 0x1F, 3238 .hfb_offset = 0x1000, 3239 .rdma_offset = 0x2000, 3240 .tdma_offset = 0x3000, 3241 .words_per_bd = 2, 3242 }, 3243 [GENET_V2] = { 3244 .tx_queues = 4, 3245 .tx_bds_per_q = 32, 3246 .rx_queues = 0, 3247 .rx_bds_per_q = 0, 3248 .bp_in_en_shift = 16, 3249 .bp_in_mask = 0xffff, 3250 .hfb_filter_cnt = 16, 3251 .qtag_mask = 0x1F, 3252 .tbuf_offset = 0x0600, 3253 .hfb_offset = 0x1000, 3254 .hfb_reg_offset = 0x2000, 3255 .rdma_offset = 0x3000, 3256 .tdma_offset = 0x4000, 3257 .words_per_bd = 2, 3258 .flags = GENET_HAS_EXT, 3259 }, 3260 [GENET_V3] = { 3261 .tx_queues = 4, 3262 .tx_bds_per_q = 32, 3263 .rx_queues = 0, 3264 .rx_bds_per_q = 0, 3265 .bp_in_en_shift = 17, 3266 .bp_in_mask = 0x1ffff, 3267 .hfb_filter_cnt = 48, 3268 .hfb_filter_size = 128, 3269 .qtag_mask = 0x3F, 3270 .tbuf_offset = 0x0600, 3271 .hfb_offset = 0x8000, 3272 .hfb_reg_offset = 0xfc00, 3273 .rdma_offset = 0x10000, 3274 .tdma_offset = 0x11000, 3275 .words_per_bd = 2, 3276 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3277 GENET_HAS_MOCA_LINK_DET, 3278 }, 3279 [GENET_V4] = { 3280 .tx_queues = 4, 3281 .tx_bds_per_q = 32, 3282 .rx_queues = 0, 3283 .rx_bds_per_q = 0, 3284 .bp_in_en_shift = 17, 3285 .bp_in_mask = 0x1ffff, 3286 .hfb_filter_cnt = 48, 3287 .hfb_filter_size = 128, 3288 .qtag_mask = 0x3F, 3289 .tbuf_offset = 0x0600, 3290 .hfb_offset = 0x8000, 3291 .hfb_reg_offset = 0xfc00, 3292 .rdma_offset = 0x2000, 3293 .tdma_offset = 0x4000, 3294 .words_per_bd = 3, 3295 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3296 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3297 }, 3298 [GENET_V5] = { 3299 .tx_queues = 4, 3300 .tx_bds_per_q = 32, 3301 .rx_queues = 0, 3302 .rx_bds_per_q = 0, 3303 .bp_in_en_shift = 17, 3304 .bp_in_mask = 0x1ffff, 3305 .hfb_filter_cnt = 48, 3306 .hfb_filter_size = 128, 3307 .qtag_mask = 0x3F, 3308 .tbuf_offset = 0x0600, 3309 .hfb_offset = 0x8000, 3310 .hfb_reg_offset = 0xfc00, 3311 .rdma_offset = 0x2000, 3312 .tdma_offset = 0x4000, 3313 .words_per_bd = 3, 3314 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3315 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3316 }, 3317 }; 3318 3319 /* Infer hardware parameters from the detected GENET version */ 3320 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3321 { 3322 struct bcmgenet_hw_params *params; 3323 u32 reg; 3324 u8 major; 3325 u16 gphy_rev; 3326 3327 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3328 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3329 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3330 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3331 } else if (GENET_IS_V3(priv)) { 3332 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3333 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3334 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3335 } else if (GENET_IS_V2(priv)) { 3336 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3337 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3338 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3339 } else if (GENET_IS_V1(priv)) { 3340 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3341 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3342 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3343 } 3344 3345 /* enum genet_version starts at 1 */ 3346 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3347 params = priv->hw_params; 3348 3349 /* Read GENET HW version */ 3350 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3351 major = (reg >> 24 & 0x0f); 3352 if (major == 6) 3353 major = 5; 3354 else if (major == 5) 3355 major = 4; 3356 else if (major == 0) 3357 major = 1; 3358 if (major != priv->version) { 3359 dev_err(&priv->pdev->dev, 3360 "GENET version mismatch, got: %d, configured for: %d\n", 3361 major, priv->version); 3362 } 3363 3364 /* Print the GENET core version */ 3365 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3366 major, (reg >> 16) & 0x0f, reg & 0xffff); 3367 3368 /* Store the integrated PHY revision for the MDIO probing function 3369 * to pass this information to the PHY driver. The PHY driver expects 3370 * to find the PHY major revision in bits 15:8 while the GENET register 3371 * stores that information in bits 7:0, account for that. 3372 * 3373 * On newer chips, starting with PHY revision G0, a new scheme is 3374 * deployed similar to the Starfighter 2 switch with GPHY major 3375 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3376 * is reserved as well as special value 0x01ff, we have a small 3377 * heuristic to check for the new GPHY revision and re-arrange things 3378 * so the GPHY driver is happy. 3379 */ 3380 gphy_rev = reg & 0xffff; 3381 3382 if (GENET_IS_V5(priv)) { 3383 /* The EPHY revision should come from the MDIO registers of 3384 * the PHY not from GENET. 3385 */ 3386 if (gphy_rev != 0) { 3387 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3388 gphy_rev); 3389 } 3390 /* This is reserved so should require special treatment */ 3391 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3392 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3393 return; 3394 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3395 } else if ((gphy_rev & 0xf0) != 0) { 3396 priv->gphy_rev = gphy_rev << 8; 3397 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3398 } else if ((gphy_rev & 0xff00) != 0) { 3399 priv->gphy_rev = gphy_rev; 3400 } 3401 3402 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3403 if (!(params->flags & GENET_HAS_40BITS)) 3404 pr_warn("GENET does not support 40-bits PA\n"); 3405 #endif 3406 3407 pr_debug("Configuration for version: %d\n" 3408 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3409 "BP << en: %2d, BP msk: 0x%05x\n" 3410 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3411 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3412 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3413 "Words/BD: %d\n", 3414 priv->version, 3415 params->tx_queues, params->tx_bds_per_q, 3416 params->rx_queues, params->rx_bds_per_q, 3417 params->bp_in_en_shift, params->bp_in_mask, 3418 params->hfb_filter_cnt, params->qtag_mask, 3419 params->tbuf_offset, params->hfb_offset, 3420 params->hfb_reg_offset, 3421 params->rdma_offset, params->tdma_offset, 3422 params->words_per_bd); 3423 } 3424 3425 struct bcmgenet_plat_data { 3426 enum bcmgenet_version version; 3427 u32 dma_max_burst_length; 3428 }; 3429 3430 static const struct bcmgenet_plat_data v1_plat_data = { 3431 .version = GENET_V1, 3432 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3433 }; 3434 3435 static const struct bcmgenet_plat_data v2_plat_data = { 3436 .version = GENET_V2, 3437 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3438 }; 3439 3440 static const struct bcmgenet_plat_data v3_plat_data = { 3441 .version = GENET_V3, 3442 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3443 }; 3444 3445 static const struct bcmgenet_plat_data v4_plat_data = { 3446 .version = GENET_V4, 3447 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3448 }; 3449 3450 static const struct bcmgenet_plat_data v5_plat_data = { 3451 .version = GENET_V5, 3452 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3453 }; 3454 3455 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3456 .version = GENET_V5, 3457 .dma_max_burst_length = 0x08, 3458 }; 3459 3460 static const struct of_device_id bcmgenet_match[] = { 3461 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3462 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3463 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3464 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3465 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3466 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3467 { }, 3468 }; 3469 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3470 3471 static int bcmgenet_probe(struct platform_device *pdev) 3472 { 3473 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3474 struct device_node *dn = pdev->dev.of_node; 3475 const struct of_device_id *of_id = NULL; 3476 const struct bcmgenet_plat_data *pdata; 3477 struct bcmgenet_priv *priv; 3478 struct net_device *dev; 3479 const void *macaddr; 3480 unsigned int i; 3481 int err = -EIO; 3482 const char *phy_mode_str; 3483 3484 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3485 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3486 GENET_MAX_MQ_CNT + 1); 3487 if (!dev) { 3488 dev_err(&pdev->dev, "can't allocate net device\n"); 3489 return -ENOMEM; 3490 } 3491 3492 if (dn) { 3493 of_id = of_match_node(bcmgenet_match, dn); 3494 if (!of_id) 3495 return -EINVAL; 3496 } 3497 3498 priv = netdev_priv(dev); 3499 priv->irq0 = platform_get_irq(pdev, 0); 3500 if (priv->irq0 < 0) { 3501 err = priv->irq0; 3502 goto err; 3503 } 3504 priv->irq1 = platform_get_irq(pdev, 1); 3505 if (priv->irq1 < 0) { 3506 err = priv->irq1; 3507 goto err; 3508 } 3509 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3510 3511 if (dn) 3512 macaddr = of_get_mac_address(dn); 3513 else 3514 macaddr = pd->mac_address; 3515 3516 priv->base = devm_platform_ioremap_resource(pdev, 0); 3517 if (IS_ERR(priv->base)) { 3518 err = PTR_ERR(priv->base); 3519 goto err; 3520 } 3521 3522 spin_lock_init(&priv->lock); 3523 3524 SET_NETDEV_DEV(dev, &pdev->dev); 3525 dev_set_drvdata(&pdev->dev, dev); 3526 if (IS_ERR_OR_NULL(macaddr) || !is_valid_ether_addr(macaddr)) { 3527 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 3528 eth_hw_addr_random(dev); 3529 } else { 3530 ether_addr_copy(dev->dev_addr, macaddr); 3531 } 3532 dev->watchdog_timeo = 2 * HZ; 3533 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3534 dev->netdev_ops = &bcmgenet_netdev_ops; 3535 3536 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3537 3538 /* Set hardware features */ 3539 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | 3540 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; 3541 3542 /* Request the WOL interrupt and advertise suspend if available */ 3543 priv->wol_irq_disabled = true; 3544 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3545 dev->name, priv); 3546 if (!err) 3547 device_set_wakeup_capable(&pdev->dev, 1); 3548 3549 /* Set the needed headroom to account for any possible 3550 * features enabling/disabling at runtime 3551 */ 3552 dev->needed_headroom += 64; 3553 3554 netdev_boot_setup_check(dev); 3555 3556 priv->dev = dev; 3557 priv->pdev = pdev; 3558 if (of_id) { 3559 pdata = of_id->data; 3560 priv->version = pdata->version; 3561 priv->dma_max_burst_length = pdata->dma_max_burst_length; 3562 } else { 3563 priv->version = pd->genet_version; 3564 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH; 3565 } 3566 3567 priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); 3568 if (IS_ERR(priv->clk)) { 3569 dev_warn(&priv->pdev->dev, "failed to get enet clock\n"); 3570 priv->clk = NULL; 3571 } 3572 3573 clk_prepare_enable(priv->clk); 3574 3575 bcmgenet_set_hw_params(priv); 3576 3577 /* Mii wait queue */ 3578 init_waitqueue_head(&priv->wq); 3579 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 3580 priv->rx_buf_len = RX_BUF_LENGTH; 3581 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 3582 3583 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); 3584 if (IS_ERR(priv->clk_wol)) { 3585 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n"); 3586 priv->clk_wol = NULL; 3587 } 3588 3589 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee"); 3590 if (IS_ERR(priv->clk_eee)) { 3591 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n"); 3592 priv->clk_eee = NULL; 3593 } 3594 3595 /* If this is an internal GPHY, power it on now, before UniMAC is 3596 * brought out of reset as absolutely no UniMAC activity is allowed 3597 */ 3598 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) && 3599 !strcasecmp(phy_mode_str, "internal")) 3600 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3601 3602 reset_umac(priv); 3603 3604 err = bcmgenet_mii_init(dev); 3605 if (err) 3606 goto err_clk_disable; 3607 3608 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 3609 * just the ring 16 descriptor based TX 3610 */ 3611 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 3612 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 3613 3614 /* Set default coalescing parameters */ 3615 for (i = 0; i < priv->hw_params->rx_queues; i++) 3616 priv->rx_rings[i].rx_max_coalesced_frames = 1; 3617 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; 3618 3619 /* libphy will determine the link state */ 3620 netif_carrier_off(dev); 3621 3622 /* Turn off the main clock, WOL clock is handled separately */ 3623 clk_disable_unprepare(priv->clk); 3624 3625 err = register_netdev(dev); 3626 if (err) 3627 goto err; 3628 3629 return err; 3630 3631 err_clk_disable: 3632 clk_disable_unprepare(priv->clk); 3633 err: 3634 free_netdev(dev); 3635 return err; 3636 } 3637 3638 static int bcmgenet_remove(struct platform_device *pdev) 3639 { 3640 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 3641 3642 dev_set_drvdata(&pdev->dev, NULL); 3643 unregister_netdev(priv->dev); 3644 bcmgenet_mii_exit(priv->dev); 3645 free_netdev(priv->dev); 3646 3647 return 0; 3648 } 3649 3650 static void bcmgenet_shutdown(struct platform_device *pdev) 3651 { 3652 bcmgenet_remove(pdev); 3653 } 3654 3655 #ifdef CONFIG_PM_SLEEP 3656 static int bcmgenet_resume(struct device *d) 3657 { 3658 struct net_device *dev = dev_get_drvdata(d); 3659 struct bcmgenet_priv *priv = netdev_priv(dev); 3660 unsigned long dma_ctrl; 3661 int ret; 3662 u32 reg; 3663 3664 if (!netif_running(dev)) 3665 return 0; 3666 3667 /* Turn on the clock */ 3668 ret = clk_prepare_enable(priv->clk); 3669 if (ret) 3670 return ret; 3671 3672 /* If this is an internal GPHY, power it back on now, before UniMAC is 3673 * brought out of reset as absolutely no UniMAC activity is allowed 3674 */ 3675 if (priv->internal_phy) 3676 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3677 3678 bcmgenet_umac_reset(priv); 3679 3680 init_umac(priv); 3681 3682 /* From WOL-enabled suspend, switch to regular clock */ 3683 if (priv->wolopts) 3684 clk_disable_unprepare(priv->clk_wol); 3685 3686 phy_init_hw(dev->phydev); 3687 3688 /* Speed settings must be restored */ 3689 genphy_config_aneg(dev->phydev); 3690 bcmgenet_mii_config(priv->dev, false); 3691 3692 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3693 3694 if (priv->internal_phy) { 3695 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3696 reg |= EXT_ENERGY_DET_MASK; 3697 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3698 } 3699 3700 if (priv->wolopts) 3701 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 3702 3703 /* Disable RX/TX DMA and flush TX queues */ 3704 dma_ctrl = bcmgenet_dma_disable(priv); 3705 3706 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3707 ret = bcmgenet_init_dma(priv); 3708 if (ret) { 3709 netdev_err(dev, "failed to initialize DMA\n"); 3710 goto out_clk_disable; 3711 } 3712 3713 /* Always enable ring 16 - descriptor ring */ 3714 bcmgenet_enable_dma(priv, dma_ctrl); 3715 3716 if (!device_may_wakeup(d)) 3717 phy_resume(dev->phydev); 3718 3719 if (priv->eee.eee_enabled) 3720 bcmgenet_eee_enable_set(dev, true); 3721 3722 bcmgenet_netif_start(dev); 3723 3724 netif_device_attach(dev); 3725 3726 return 0; 3727 3728 out_clk_disable: 3729 if (priv->internal_phy) 3730 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3731 clk_disable_unprepare(priv->clk); 3732 return ret; 3733 } 3734 3735 static int bcmgenet_suspend(struct device *d) 3736 { 3737 struct net_device *dev = dev_get_drvdata(d); 3738 struct bcmgenet_priv *priv = netdev_priv(dev); 3739 int ret = 0; 3740 3741 if (!netif_running(dev)) 3742 return 0; 3743 3744 netif_device_detach(dev); 3745 3746 bcmgenet_netif_stop(dev); 3747 3748 if (!device_may_wakeup(d)) 3749 phy_suspend(dev->phydev); 3750 3751 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 3752 if (device_may_wakeup(d) && priv->wolopts) { 3753 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 3754 clk_prepare_enable(priv->clk_wol); 3755 } else if (priv->internal_phy) { 3756 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3757 } 3758 3759 /* Turn off the clocks */ 3760 clk_disable_unprepare(priv->clk); 3761 3762 if (ret) 3763 bcmgenet_resume(d); 3764 3765 return ret; 3766 } 3767 #endif /* CONFIG_PM_SLEEP */ 3768 3769 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); 3770 3771 static struct platform_driver bcmgenet_driver = { 3772 .probe = bcmgenet_probe, 3773 .remove = bcmgenet_remove, 3774 .shutdown = bcmgenet_shutdown, 3775 .driver = { 3776 .name = "bcmgenet", 3777 .of_match_table = bcmgenet_match, 3778 .pm = &bcmgenet_pm_ops, 3779 }, 3780 }; 3781 module_platform_driver(bcmgenet_driver); 3782 3783 MODULE_AUTHOR("Broadcom Corporation"); 3784 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 3785 MODULE_ALIAS("platform:bcmgenet"); 3786 MODULE_LICENSE("GPL"); 3787