1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET MDIO routines 4 * 5 * Copyright (c) 2014-2017 Broadcom 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/types.h> 10 #include <linux/delay.h> 11 #include <linux/wait.h> 12 #include <linux/mii.h> 13 #include <linux/ethtool.h> 14 #include <linux/bitops.h> 15 #include <linux/netdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/brcmphy.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/platform_data/bcmgenet.h> 24 #include <linux/platform_data/mdio-bcm-unimac.h> 25 26 #include "bcmgenet.h" 27 28 static void bcmgenet_mac_config(struct net_device *dev) 29 { 30 struct bcmgenet_priv *priv = netdev_priv(dev); 31 struct phy_device *phydev = dev->phydev; 32 u32 reg, cmd_bits = 0; 33 34 /* speed */ 35 if (phydev->speed == SPEED_1000) 36 cmd_bits = CMD_SPEED_1000; 37 else if (phydev->speed == SPEED_100) 38 cmd_bits = CMD_SPEED_100; 39 else 40 cmd_bits = CMD_SPEED_10; 41 cmd_bits <<= CMD_SPEED_SHIFT; 42 43 /* duplex */ 44 if (phydev->duplex != DUPLEX_FULL) { 45 cmd_bits |= CMD_HD_EN | 46 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 47 } else { 48 /* pause capability defaults to Symmetric */ 49 if (priv->autoneg_pause) { 50 bool tx_pause = 0, rx_pause = 0; 51 52 if (phydev->autoneg) 53 phy_get_pause(phydev, &tx_pause, &rx_pause); 54 55 if (!tx_pause) 56 cmd_bits |= CMD_TX_PAUSE_IGNORE; 57 if (!rx_pause) 58 cmd_bits |= CMD_RX_PAUSE_IGNORE; 59 } 60 61 /* Manual override */ 62 if (!priv->rx_pause) 63 cmd_bits |= CMD_RX_PAUSE_IGNORE; 64 if (!priv->tx_pause) 65 cmd_bits |= CMD_TX_PAUSE_IGNORE; 66 } 67 68 /* Program UMAC and RGMII block based on established 69 * link speed, duplex, and pause. The speed set in 70 * umac->cmd tell RGMII block which clock to use for 71 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 72 * Receive clock is provided by the PHY. 73 */ 74 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 75 reg |= RGMII_LINK; 76 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 77 78 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 79 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 80 CMD_HD_EN | 81 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 82 reg |= cmd_bits; 83 if (reg & CMD_SW_RESET) { 84 reg &= ~CMD_SW_RESET; 85 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 86 udelay(2); 87 reg |= CMD_TX_EN | CMD_RX_EN; 88 } 89 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 90 91 priv->eee.eee_active = phy_init_eee(phydev, 0) >= 0; 92 bcmgenet_eee_enable_set(dev, 93 priv->eee.eee_enabled && priv->eee.eee_active, 94 priv->eee.tx_lpi_enabled); 95 } 96 97 /* setup netdev link state when PHY link status change and 98 * update UMAC and RGMII block when link up 99 */ 100 void bcmgenet_mii_setup(struct net_device *dev) 101 { 102 struct bcmgenet_priv *priv = netdev_priv(dev); 103 struct phy_device *phydev = dev->phydev; 104 u32 reg; 105 106 if (phydev->link) { 107 bcmgenet_mac_config(dev); 108 } else { 109 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 110 reg &= ~RGMII_LINK; 111 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 112 } 113 114 phy_print_status(phydev); 115 } 116 117 118 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 119 struct fixed_phy_status *status) 120 { 121 struct bcmgenet_priv *priv; 122 u32 reg; 123 124 if (dev && dev->phydev && status) { 125 priv = netdev_priv(dev); 126 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 127 status->link = !!(reg & MODE_LINK_STATUS); 128 } 129 130 return 0; 131 } 132 133 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx) 134 { 135 struct phy_device *phydev = dev->phydev; 136 137 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx); 138 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising, 139 rx | tx); 140 phy_start_aneg(phydev); 141 142 mutex_lock(&phydev->lock); 143 if (phydev->link) 144 bcmgenet_mac_config(dev); 145 mutex_unlock(&phydev->lock); 146 } 147 148 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 149 { 150 struct bcmgenet_priv *priv = netdev_priv(dev); 151 u32 reg = 0; 152 153 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 154 if (GENET_IS_V4(priv) || priv->ephy_16nm) { 155 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 156 if (enable) { 157 reg &= ~EXT_CK25_DIS; 158 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 159 mdelay(1); 160 161 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 162 EXT_CFG_IDDQ_GLOBAL_PWR); 163 reg |= EXT_GPHY_RESET; 164 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 165 mdelay(1); 166 167 reg &= ~EXT_GPHY_RESET; 168 } else { 169 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 170 EXT_GPHY_RESET | EXT_CFG_IDDQ_GLOBAL_PWR; 171 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 172 mdelay(1); 173 reg |= EXT_CK25_DIS; 174 } 175 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 176 udelay(60); 177 } else { 178 mdelay(1); 179 } 180 } 181 182 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 183 { 184 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 185 fixed_phy_set_link_update(priv->dev->phydev, 186 bcmgenet_fixed_phy_link_update); 187 } 188 189 int bcmgenet_mii_config(struct net_device *dev, bool init) 190 { 191 struct bcmgenet_priv *priv = netdev_priv(dev); 192 struct phy_device *phydev = dev->phydev; 193 struct device *kdev = &priv->pdev->dev; 194 const char *phy_name = NULL; 195 u32 id_mode_dis = 0; 196 u32 port_ctrl; 197 u32 reg; 198 199 switch (priv->phy_interface) { 200 case PHY_INTERFACE_MODE_INTERNAL: 201 phy_name = "internal PHY"; 202 fallthrough; 203 case PHY_INTERFACE_MODE_MOCA: 204 /* Irrespective of the actually configured PHY speed (100 or 205 * 1000) GENETv4 only has an internal GPHY so we will just end 206 * up masking the Gigabit features from what we support, not 207 * switching to the EPHY 208 */ 209 if (GENET_IS_V4(priv)) 210 port_ctrl = PORT_MODE_INT_GPHY; 211 else 212 port_ctrl = PORT_MODE_INT_EPHY; 213 214 if (!phy_name) { 215 phy_name = "MoCA"; 216 if (!GENET_IS_V5(priv)) 217 port_ctrl |= LED_ACT_SOURCE_MAC; 218 bcmgenet_moca_phy_setup(priv); 219 } 220 break; 221 222 case PHY_INTERFACE_MODE_MII: 223 phy_name = "external MII"; 224 phy_set_max_speed(phydev, SPEED_100); 225 port_ctrl = PORT_MODE_EXT_EPHY; 226 break; 227 228 case PHY_INTERFACE_MODE_REVMII: 229 phy_name = "external RvMII"; 230 /* of_mdiobus_register took care of reading the 'max-speed' 231 * PHY property for us, effectively limiting the PHY supported 232 * capabilities, use that knowledge to also configure the 233 * Reverse MII interface correctly. 234 */ 235 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 236 dev->phydev->supported)) 237 port_ctrl = PORT_MODE_EXT_RVMII_50; 238 else 239 port_ctrl = PORT_MODE_EXT_RVMII_25; 240 break; 241 242 case PHY_INTERFACE_MODE_RGMII: 243 /* RGMII_NO_ID: TXC transitions at the same time as TXD 244 * (requires PCB or receiver-side delay) 245 * 246 * ID is implicitly disabled for 100Mbps (RG)MII operation. 247 */ 248 phy_name = "external RGMII (no delay)"; 249 id_mode_dis = BIT(16); 250 port_ctrl = PORT_MODE_EXT_GPHY; 251 break; 252 253 case PHY_INTERFACE_MODE_RGMII_TXID: 254 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */ 255 phy_name = "external RGMII (TX delay)"; 256 port_ctrl = PORT_MODE_EXT_GPHY; 257 break; 258 259 case PHY_INTERFACE_MODE_RGMII_RXID: 260 phy_name = "external RGMII (RX delay)"; 261 port_ctrl = PORT_MODE_EXT_GPHY; 262 break; 263 default: 264 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 265 return -EINVAL; 266 } 267 268 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 269 270 priv->ext_phy = !priv->internal_phy && 271 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 272 273 /* This is an external PHY (xMII), so we need to enable the RGMII 274 * block for the interface to work, unconditionally clear the 275 * Out-of-band disable since we do not need it. 276 */ 277 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 278 reg &= ~OOB_DISABLE; 279 if (priv->ext_phy) { 280 reg &= ~ID_MODE_DIS; 281 reg |= id_mode_dis; 282 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 283 reg |= RGMII_MODE_EN_V123; 284 else 285 reg |= RGMII_MODE_EN; 286 } 287 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 288 289 if (init) 290 dev_info(kdev, "configuring instance for %s\n", phy_name); 291 292 return 0; 293 } 294 295 int bcmgenet_mii_probe(struct net_device *dev) 296 { 297 struct bcmgenet_priv *priv = netdev_priv(dev); 298 struct device *kdev = &priv->pdev->dev; 299 struct device_node *dn = kdev->of_node; 300 phy_interface_t phy_iface = priv->phy_interface; 301 struct phy_device *phydev; 302 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 303 PHY_BRCM_DIS_TXCRXC_NOENRGY | 304 PHY_BRCM_IDDQ_SUSPEND; 305 int ret; 306 307 /* Communicate the integrated PHY revision */ 308 if (priv->internal_phy) 309 phy_flags = priv->gphy_rev; 310 311 /* This is an ugly quirk but we have not been correctly interpreting 312 * the phy_interface values and we have done that across different 313 * drivers, so at least we are consistent in our mistakes. 314 * 315 * When the Generic PHY driver is in use either the PHY has been 316 * strapped or programmed correctly by the boot loader so we should 317 * stick to our incorrect interpretation since we have validated it. 318 * 319 * Now when a dedicated PHY driver is in use, we need to reverse the 320 * meaning of the phy_interface_mode values to something that the PHY 321 * driver will interpret and act on such that we have two mistakes 322 * canceling themselves so to speak. We only do this for the two 323 * modes that GENET driver officially supports on Broadcom STB chips: 324 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other 325 * modes are not *officially* supported with the boot loader and the 326 * scripted environment generating Device Tree blobs for those 327 * platforms. 328 * 329 * Note that internal PHY, MoCA and fixed-link configurations are not 330 * affected because they use different phy_interface_t values or the 331 * Generic PHY driver. 332 */ 333 switch (priv->phy_interface) { 334 case PHY_INTERFACE_MODE_RGMII: 335 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 336 break; 337 case PHY_INTERFACE_MODE_RGMII_TXID: 338 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 339 break; 340 default: 341 break; 342 } 343 344 if (dn) { 345 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 346 phy_flags, phy_iface); 347 if (!phydev) { 348 pr_err("could not attach to PHY\n"); 349 return -ENODEV; 350 } 351 } else { 352 if (has_acpi_companion(kdev)) { 353 char mdio_bus_id[MII_BUS_ID_SIZE]; 354 struct mii_bus *unimacbus; 355 356 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 357 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 358 359 unimacbus = mdio_find_bus(mdio_bus_id); 360 if (!unimacbus) { 361 pr_err("Unable to find mii\n"); 362 return -ENODEV; 363 } 364 phydev = phy_find_first(unimacbus); 365 put_device(&unimacbus->dev); 366 if (!phydev) { 367 pr_err("Unable to find PHY\n"); 368 return -ENODEV; 369 } 370 } else { 371 phydev = dev->phydev; 372 } 373 phydev->dev_flags = phy_flags; 374 375 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 376 phy_iface); 377 if (ret) { 378 pr_err("could not attach to PHY\n"); 379 return -ENODEV; 380 } 381 } 382 383 /* Configure port multiplexer based on what the probed PHY device since 384 * reading the 'max-speed' property determines the maximum supported 385 * PHY speed which is needed for bcmgenet_mii_config() to configure 386 * things appropriately. 387 */ 388 ret = bcmgenet_mii_config(dev, true); 389 if (ret) { 390 phy_disconnect(dev->phydev); 391 return ret; 392 } 393 394 /* The internal PHY has its link interrupts routed to the 395 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 396 * that prevents the signaling of link UP interrupts when 397 * the link operates at 10Mbps, so fallback to polling for 398 * those versions of GENET. 399 */ 400 if (priv->internal_phy && !GENET_IS_V5(priv)) 401 dev->phydev->irq = PHY_MAC_INTERRUPT; 402 403 /* Indicate that the MAC is responsible for PHY PM */ 404 dev->phydev->mac_managed_pm = true; 405 406 return 0; 407 } 408 409 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 410 { 411 struct device_node *dn = priv->pdev->dev.of_node; 412 struct device *kdev = &priv->pdev->dev; 413 char *compat; 414 415 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 416 if (!compat) 417 return NULL; 418 419 priv->mdio_dn = of_get_compatible_child(dn, compat); 420 kfree(compat); 421 if (!priv->mdio_dn) { 422 dev_err(kdev, "unable to find MDIO bus node\n"); 423 return NULL; 424 } 425 426 return priv->mdio_dn; 427 } 428 429 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 430 struct unimac_mdio_pdata *ppd) 431 { 432 struct device *kdev = &priv->pdev->dev; 433 struct bcmgenet_platform_data *pd = kdev->platform_data; 434 435 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 436 /* 437 * Internal or external PHY with MDIO access 438 */ 439 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 440 ppd->phy_mask = 1 << pd->phy_address; 441 else 442 ppd->phy_mask = 0; 443 } 444 } 445 446 static int bcmgenet_mii_wait(void *wait_func_data) 447 { 448 struct bcmgenet_priv *priv = wait_func_data; 449 450 wait_event_timeout(priv->wq, 451 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 452 & MDIO_START_BUSY), 453 HZ / 100); 454 return 0; 455 } 456 457 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 458 { 459 struct platform_device *pdev = priv->pdev; 460 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 461 struct device_node *dn = pdev->dev.of_node; 462 struct unimac_mdio_pdata ppd; 463 struct platform_device *ppdev; 464 struct resource *pres, res; 465 int id, ret; 466 467 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 468 if (!pres) { 469 dev_err(&pdev->dev, "Invalid resource\n"); 470 return -EINVAL; 471 } 472 memset(&res, 0, sizeof(res)); 473 memset(&ppd, 0, sizeof(ppd)); 474 475 ppd.wait_func = bcmgenet_mii_wait; 476 ppd.wait_func_data = priv; 477 ppd.bus_name = "bcmgenet MII bus"; 478 479 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 480 * and is 2 * 32-bits word long, 8 bytes total. 481 */ 482 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 483 res.end = res.start + 8; 484 res.flags = IORESOURCE_MEM; 485 486 if (dn) 487 id = of_alias_get_id(dn, "eth"); 488 else 489 id = pdev->id; 490 491 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 492 if (!ppdev) 493 return -ENOMEM; 494 495 /* Retain this platform_device pointer for later cleanup */ 496 priv->mii_pdev = ppdev; 497 ppdev->dev.parent = &pdev->dev; 498 if (dn) 499 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 500 else if (pdata) 501 bcmgenet_mii_pdata_init(priv, &ppd); 502 else 503 ppd.phy_mask = ~0; 504 505 ret = platform_device_add_resources(ppdev, &res, 1); 506 if (ret) 507 goto out; 508 509 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 510 if (ret) 511 goto out; 512 513 ret = platform_device_add(ppdev); 514 if (ret) 515 goto out; 516 517 return 0; 518 out: 519 platform_device_put(ppdev); 520 return ret; 521 } 522 523 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv) 524 { 525 struct device *kdev = &priv->pdev->dev; 526 int phy_mode = device_get_phy_mode(kdev); 527 528 if (phy_mode < 0) { 529 dev_err(kdev, "invalid PHY mode property\n"); 530 return phy_mode; 531 } 532 533 priv->phy_interface = phy_mode; 534 535 /* We need to specifically look up whether this PHY interface is 536 * internal or not *before* we even try to probe the PHY driver 537 * over MDIO as we may have shut down the internal PHY for power 538 * saving purposes. 539 */ 540 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 541 priv->internal_phy = true; 542 543 return 0; 544 } 545 546 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 547 { 548 struct device_node *dn = priv->pdev->dev.of_node; 549 struct phy_device *phydev; 550 int ret; 551 552 /* Fetch the PHY phandle */ 553 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 554 555 /* In the case of a fixed PHY, the DT node associated 556 * to the PHY is the Ethernet MAC DT node. 557 */ 558 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 559 ret = of_phy_register_fixed_link(dn); 560 if (ret) 561 return ret; 562 563 priv->phy_dn = of_node_get(dn); 564 } 565 566 /* Get the link mode */ 567 ret = bcmgenet_phy_interface_init(priv); 568 if (ret) 569 return ret; 570 571 /* Make sure we initialize MoCA PHYs with a link down */ 572 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 573 phydev = of_phy_find_device(dn); 574 if (phydev) { 575 phydev->link = 0; 576 put_device(&phydev->mdio.dev); 577 } 578 } 579 580 return 0; 581 } 582 583 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 584 { 585 struct device *kdev = &priv->pdev->dev; 586 struct bcmgenet_platform_data *pd = kdev->platform_data; 587 char phy_name[MII_BUS_ID_SIZE + 3]; 588 char mdio_bus_id[MII_BUS_ID_SIZE]; 589 struct phy_device *phydev; 590 591 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 592 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 593 594 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 595 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 596 mdio_bus_id, pd->phy_address); 597 598 /* 599 * Internal or external PHY with MDIO access 600 */ 601 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 602 if (IS_ERR(phydev)) { 603 dev_err(kdev, "failed to register PHY device\n"); 604 return PTR_ERR(phydev); 605 } 606 } else { 607 /* 608 * MoCA port or no MDIO access. 609 * Use fixed PHY to represent the link layer. 610 */ 611 struct fixed_phy_status fphy_status = { 612 .link = 1, 613 .speed = pd->phy_speed, 614 .duplex = pd->phy_duplex, 615 .pause = 0, 616 .asym_pause = 0, 617 }; 618 619 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 620 if (IS_ERR(phydev)) { 621 dev_err(kdev, "failed to register fixed PHY device\n"); 622 return PTR_ERR(phydev); 623 } 624 625 /* Make sure we initialize MoCA PHYs with a link down */ 626 phydev->link = 0; 627 628 } 629 630 priv->phy_interface = pd->phy_interface; 631 632 return 0; 633 } 634 635 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 636 { 637 struct device *kdev = &priv->pdev->dev; 638 struct device_node *dn = kdev->of_node; 639 640 if (dn) 641 return bcmgenet_mii_of_init(priv); 642 else if (has_acpi_companion(kdev)) 643 return bcmgenet_phy_interface_init(priv); 644 else 645 return bcmgenet_mii_pd_init(priv); 646 } 647 648 int bcmgenet_mii_init(struct net_device *dev) 649 { 650 struct bcmgenet_priv *priv = netdev_priv(dev); 651 int ret; 652 653 ret = bcmgenet_mii_register(priv); 654 if (ret) 655 return ret; 656 657 ret = bcmgenet_mii_bus_init(priv); 658 if (ret) 659 goto out; 660 661 return 0; 662 663 out: 664 bcmgenet_mii_exit(dev); 665 return ret; 666 } 667 668 void bcmgenet_mii_exit(struct net_device *dev) 669 { 670 struct bcmgenet_priv *priv = netdev_priv(dev); 671 struct device_node *dn = priv->pdev->dev.of_node; 672 673 if (of_phy_is_fixed_link(dn)) 674 of_phy_deregister_fixed_link(dn); 675 of_node_put(priv->phy_dn); 676 clk_prepare_enable(priv->clk); 677 platform_device_unregister(priv->mii_pdev); 678 clk_disable_unprepare(priv->clk); 679 } 680