1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2b83f1527SRafal Ozieblo /*
3b83f1527SRafal Ozieblo * Cadence MACB/GEM Ethernet Controller driver
4b83f1527SRafal Ozieblo *
5b83f1527SRafal Ozieblo * Copyright (C) 2004-2006 Atmel Corporation
6b83f1527SRafal Ozieblo */
7b83f1527SRafal Ozieblo
8b83f1527SRafal Ozieblo #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9b83f1527SRafal Ozieblo #include <linux/clk.h>
10c218ad55SYash Shah #include <linux/clk-provider.h>
11653e92a9SClaudiu Beznea #include <linux/crc32.h>
12b83f1527SRafal Ozieblo #include <linux/module.h>
13b83f1527SRafal Ozieblo #include <linux/moduleparam.h>
14b83f1527SRafal Ozieblo #include <linux/kernel.h>
15b83f1527SRafal Ozieblo #include <linux/types.h>
16b83f1527SRafal Ozieblo #include <linux/circ_buf.h>
17b83f1527SRafal Ozieblo #include <linux/slab.h>
18b83f1527SRafal Ozieblo #include <linux/init.h>
19b83f1527SRafal Ozieblo #include <linux/io.h>
20b83f1527SRafal Ozieblo #include <linux/gpio.h>
21b83f1527SRafal Ozieblo #include <linux/gpio/consumer.h>
22b83f1527SRafal Ozieblo #include <linux/interrupt.h>
23b83f1527SRafal Ozieblo #include <linux/netdevice.h>
24b83f1527SRafal Ozieblo #include <linux/etherdevice.h>
25b83f1527SRafal Ozieblo #include <linux/dma-mapping.h>
26b83f1527SRafal Ozieblo #include <linux/platform_device.h>
277897b071SAntoine Tenart #include <linux/phylink.h>
28b83f1527SRafal Ozieblo #include <linux/of.h>
29b83f1527SRafal Ozieblo #include <linux/of_gpio.h>
30b83f1527SRafal Ozieblo #include <linux/of_mdio.h>
31b83f1527SRafal Ozieblo #include <linux/of_net.h>
32b83f1527SRafal Ozieblo #include <linux/ip.h>
33b83f1527SRafal Ozieblo #include <linux/udp.h>
34b83f1527SRafal Ozieblo #include <linux/tcp.h>
358beb79b7SHarini Katakam #include <linux/iopoll.h>
368b73fa3aSRobert Hancock #include <linux/phy/phy.h>
37d54f89afSHarini Katakam #include <linux/pm_runtime.h>
385cebb40bSHarini Katakam #include <linux/ptp_classify.h>
398b73fa3aSRobert Hancock #include <linux/reset.h>
4032cee781SRadhey Shyam Pandey #include <linux/firmware/xlnx-zynqmp.h>
41b83f1527SRafal Ozieblo #include "macb.h"
42b83f1527SRafal Ozieblo
43c218ad55SYash Shah /* This structure is only used for MACB on SiFive FU540 devices */
44c218ad55SYash Shah struct sifive_fu540_macb_mgmt {
45c218ad55SYash Shah void __iomem *reg;
46c218ad55SYash Shah unsigned long rate;
47c218ad55SYash Shah struct clk_hw hw;
48c218ad55SYash Shah };
49c218ad55SYash Shah
50b83f1527SRafal Ozieblo #define MACB_RX_BUFFER_SIZE 128
51b83f1527SRafal Ozieblo #define RX_BUFFER_MULTIPLE 64 /* bytes */
52b83f1527SRafal Ozieblo
53b83f1527SRafal Ozieblo #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
54b83f1527SRafal Ozieblo #define MIN_RX_RING_SIZE 64
55b83f1527SRafal Ozieblo #define MAX_RX_RING_SIZE 8192
56b83f1527SRafal Ozieblo #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
57b83f1527SRafal Ozieblo * (bp)->rx_ring_size)
58b83f1527SRafal Ozieblo
59b83f1527SRafal Ozieblo #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
60b83f1527SRafal Ozieblo #define MIN_TX_RING_SIZE 64
61b83f1527SRafal Ozieblo #define MAX_TX_RING_SIZE 4096
62b83f1527SRafal Ozieblo #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
63b83f1527SRafal Ozieblo * (bp)->tx_ring_size)
64b83f1527SRafal Ozieblo
65b83f1527SRafal Ozieblo /* level of occupied TX descriptors under which we wake up TX process */
66b83f1527SRafal Ozieblo #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
67b83f1527SRafal Ozieblo
68e501070eSHarini Katakam #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
69b83f1527SRafal Ozieblo #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
70b83f1527SRafal Ozieblo | MACB_BIT(ISR_RLE) \
71b83f1527SRafal Ozieblo | MACB_BIT(TXERR))
7242983885SClaudiu Beznea #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
7342983885SClaudiu Beznea | MACB_BIT(TXUBR))
74b83f1527SRafal Ozieblo
75b83f1527SRafal Ozieblo /* Max length of transmit frame must be a multiple of 8 bytes */
76b83f1527SRafal Ozieblo #define MACB_TX_LEN_ALIGN 8
77b83f1527SRafal Ozieblo #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
78f822e9c4SHarini Katakam /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
79f822e9c4SHarini Katakam * false amba_error in TX path from the DMA assuming there is not enough
80f822e9c4SHarini Katakam * space in the SRAM (16KB) even when there is.
81f822e9c4SHarini Katakam */
82f822e9c4SHarini Katakam #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
83b83f1527SRafal Ozieblo
84b83f1527SRafal Ozieblo #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
85f9c45ae0SDavid S. Miller #define MACB_NETIF_LSO NETIF_F_TSO
86b83f1527SRafal Ozieblo
87b83f1527SRafal Ozieblo #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
88b83f1527SRafal Ozieblo #define MACB_WOL_ENABLED (0x1 << 1)
89b83f1527SRafal Ozieblo
90e4e143e2SParshuram Thombare #define HS_SPEED_10000M 4
91e4e143e2SParshuram Thombare #define MACB_SERDES_RATE_10G 1
92e4e143e2SParshuram Thombare
93b83f1527SRafal Ozieblo /* Graceful stop timeouts in us. We should allow up to
94b83f1527SRafal Ozieblo * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
95b83f1527SRafal Ozieblo */
96ed0578a4SHarini Katakam #define MACB_HALT_TIMEOUT 14000
97d54f89afSHarini Katakam #define MACB_PM_TIMEOUT 100 /* ms */
98d54f89afSHarini Katakam
998beb79b7SHarini Katakam #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
1008beb79b7SHarini Katakam
101b83f1527SRafal Ozieblo /* DMA buffer descriptor might be different size
102b83f1527SRafal Ozieblo * depends on hardware configuration:
103b83f1527SRafal Ozieblo *
104b83f1527SRafal Ozieblo * 1. dma address width 32 bits:
105b83f1527SRafal Ozieblo * word 1: 32 bit address of Data Buffer
106b83f1527SRafal Ozieblo * word 2: control
107b83f1527SRafal Ozieblo *
108b83f1527SRafal Ozieblo * 2. dma address width 64 bits:
109b83f1527SRafal Ozieblo * word 1: 32 bit address of Data Buffer
110b83f1527SRafal Ozieblo * word 2: control
111b83f1527SRafal Ozieblo * word 3: upper 32 bit address of Data Buffer
112b83f1527SRafal Ozieblo * word 4: unused
113b83f1527SRafal Ozieblo *
114b83f1527SRafal Ozieblo * 3. dma address width 32 bits with hardware timestamping:
115b83f1527SRafal Ozieblo * word 1: 32 bit address of Data Buffer
116b83f1527SRafal Ozieblo * word 2: control
117b83f1527SRafal Ozieblo * word 3: timestamp word 1
118b83f1527SRafal Ozieblo * word 4: timestamp word 2
119b83f1527SRafal Ozieblo *
120b83f1527SRafal Ozieblo * 4. dma address width 64 bits with hardware timestamping:
121b83f1527SRafal Ozieblo * word 1: 32 bit address of Data Buffer
122b83f1527SRafal Ozieblo * word 2: control
123b83f1527SRafal Ozieblo * word 3: upper 32 bit address of Data Buffer
124b83f1527SRafal Ozieblo * word 4: unused
125b83f1527SRafal Ozieblo * word 5: timestamp word 1
126b83f1527SRafal Ozieblo * word 6: timestamp word 2
127b83f1527SRafal Ozieblo */
macb_dma_desc_get_size(struct macb * bp)128b83f1527SRafal Ozieblo static unsigned int macb_dma_desc_get_size(struct macb *bp)
129b83f1527SRafal Ozieblo {
130b83f1527SRafal Ozieblo #ifdef MACB_EXT_DESC
131b83f1527SRafal Ozieblo unsigned int desc_size;
132b83f1527SRafal Ozieblo
133b83f1527SRafal Ozieblo switch (bp->hw_dma_cap) {
134b83f1527SRafal Ozieblo case HW_DMA_CAP_64B:
135b83f1527SRafal Ozieblo desc_size = sizeof(struct macb_dma_desc)
136b83f1527SRafal Ozieblo + sizeof(struct macb_dma_desc_64);
137b83f1527SRafal Ozieblo break;
138b83f1527SRafal Ozieblo case HW_DMA_CAP_PTP:
139b83f1527SRafal Ozieblo desc_size = sizeof(struct macb_dma_desc)
140b83f1527SRafal Ozieblo + sizeof(struct macb_dma_desc_ptp);
141b83f1527SRafal Ozieblo break;
142b83f1527SRafal Ozieblo case HW_DMA_CAP_64B_PTP:
143b83f1527SRafal Ozieblo desc_size = sizeof(struct macb_dma_desc)
144b83f1527SRafal Ozieblo + sizeof(struct macb_dma_desc_64)
145b83f1527SRafal Ozieblo + sizeof(struct macb_dma_desc_ptp);
146b83f1527SRafal Ozieblo break;
147b83f1527SRafal Ozieblo default:
148b83f1527SRafal Ozieblo desc_size = sizeof(struct macb_dma_desc);
149b83f1527SRafal Ozieblo }
150b83f1527SRafal Ozieblo return desc_size;
151b83f1527SRafal Ozieblo #endif
152b83f1527SRafal Ozieblo return sizeof(struct macb_dma_desc);
153b83f1527SRafal Ozieblo }
154b83f1527SRafal Ozieblo
macb_adj_dma_desc_idx(struct macb * bp,unsigned int desc_idx)155b83f1527SRafal Ozieblo static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
156b83f1527SRafal Ozieblo {
157b83f1527SRafal Ozieblo #ifdef MACB_EXT_DESC
158b83f1527SRafal Ozieblo switch (bp->hw_dma_cap) {
159b83f1527SRafal Ozieblo case HW_DMA_CAP_64B:
160b83f1527SRafal Ozieblo case HW_DMA_CAP_PTP:
161b83f1527SRafal Ozieblo desc_idx <<= 1;
162b83f1527SRafal Ozieblo break;
163b83f1527SRafal Ozieblo case HW_DMA_CAP_64B_PTP:
164b83f1527SRafal Ozieblo desc_idx *= 3;
165b83f1527SRafal Ozieblo break;
166b83f1527SRafal Ozieblo default:
167b83f1527SRafal Ozieblo break;
168b83f1527SRafal Ozieblo }
169b83f1527SRafal Ozieblo #endif
170b83f1527SRafal Ozieblo return desc_idx;
171b83f1527SRafal Ozieblo }
172b83f1527SRafal Ozieblo
173b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
macb_64b_desc(struct macb * bp,struct macb_dma_desc * desc)174b83f1527SRafal Ozieblo static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
175b83f1527SRafal Ozieblo {
17699dcb843SShubhrajyoti Datta return (struct macb_dma_desc_64 *)((void *)desc
17799dcb843SShubhrajyoti Datta + sizeof(struct macb_dma_desc));
178b83f1527SRafal Ozieblo }
179b83f1527SRafal Ozieblo #endif
180b83f1527SRafal Ozieblo
181b83f1527SRafal Ozieblo /* Ring buffer accessors */
macb_tx_ring_wrap(struct macb * bp,unsigned int index)182b83f1527SRafal Ozieblo static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
183b83f1527SRafal Ozieblo {
184b83f1527SRafal Ozieblo return index & (bp->tx_ring_size - 1);
185b83f1527SRafal Ozieblo }
186b83f1527SRafal Ozieblo
macb_tx_desc(struct macb_queue * queue,unsigned int index)187b83f1527SRafal Ozieblo static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
188b83f1527SRafal Ozieblo unsigned int index)
189b83f1527SRafal Ozieblo {
190b83f1527SRafal Ozieblo index = macb_tx_ring_wrap(queue->bp, index);
191b83f1527SRafal Ozieblo index = macb_adj_dma_desc_idx(queue->bp, index);
192b83f1527SRafal Ozieblo return &queue->tx_ring[index];
193b83f1527SRafal Ozieblo }
194b83f1527SRafal Ozieblo
macb_tx_skb(struct macb_queue * queue,unsigned int index)195b83f1527SRafal Ozieblo static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
196b83f1527SRafal Ozieblo unsigned int index)
197b83f1527SRafal Ozieblo {
198b83f1527SRafal Ozieblo return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
199b83f1527SRafal Ozieblo }
200b83f1527SRafal Ozieblo
macb_tx_dma(struct macb_queue * queue,unsigned int index)201b83f1527SRafal Ozieblo static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
202b83f1527SRafal Ozieblo {
203b83f1527SRafal Ozieblo dma_addr_t offset;
204b83f1527SRafal Ozieblo
205b83f1527SRafal Ozieblo offset = macb_tx_ring_wrap(queue->bp, index) *
206b83f1527SRafal Ozieblo macb_dma_desc_get_size(queue->bp);
207b83f1527SRafal Ozieblo
208b83f1527SRafal Ozieblo return queue->tx_ring_dma + offset;
209b83f1527SRafal Ozieblo }
210b83f1527SRafal Ozieblo
macb_rx_ring_wrap(struct macb * bp,unsigned int index)211b83f1527SRafal Ozieblo static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
212b83f1527SRafal Ozieblo {
213b83f1527SRafal Ozieblo return index & (bp->rx_ring_size - 1);
214b83f1527SRafal Ozieblo }
215b83f1527SRafal Ozieblo
macb_rx_desc(struct macb_queue * queue,unsigned int index)216ae1f2a56SRafal Ozieblo static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
217b83f1527SRafal Ozieblo {
218ae1f2a56SRafal Ozieblo index = macb_rx_ring_wrap(queue->bp, index);
219ae1f2a56SRafal Ozieblo index = macb_adj_dma_desc_idx(queue->bp, index);
220ae1f2a56SRafal Ozieblo return &queue->rx_ring[index];
221b83f1527SRafal Ozieblo }
222b83f1527SRafal Ozieblo
macb_rx_buffer(struct macb_queue * queue,unsigned int index)223ae1f2a56SRafal Ozieblo static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
224b83f1527SRafal Ozieblo {
225ae1f2a56SRafal Ozieblo return queue->rx_buffers + queue->bp->rx_buffer_size *
226ae1f2a56SRafal Ozieblo macb_rx_ring_wrap(queue->bp, index);
227b83f1527SRafal Ozieblo }
228b83f1527SRafal Ozieblo
229b83f1527SRafal Ozieblo /* I/O accessors */
hw_readl_native(struct macb * bp,int offset)230b83f1527SRafal Ozieblo static u32 hw_readl_native(struct macb *bp, int offset)
231b83f1527SRafal Ozieblo {
232b83f1527SRafal Ozieblo return __raw_readl(bp->regs + offset);
233b83f1527SRafal Ozieblo }
234b83f1527SRafal Ozieblo
hw_writel_native(struct macb * bp,int offset,u32 value)235b83f1527SRafal Ozieblo static void hw_writel_native(struct macb *bp, int offset, u32 value)
236b83f1527SRafal Ozieblo {
237b83f1527SRafal Ozieblo __raw_writel(value, bp->regs + offset);
238b83f1527SRafal Ozieblo }
239b83f1527SRafal Ozieblo
hw_readl(struct macb * bp,int offset)240b83f1527SRafal Ozieblo static u32 hw_readl(struct macb *bp, int offset)
241b83f1527SRafal Ozieblo {
242b83f1527SRafal Ozieblo return readl_relaxed(bp->regs + offset);
243b83f1527SRafal Ozieblo }
244b83f1527SRafal Ozieblo
hw_writel(struct macb * bp,int offset,u32 value)245b83f1527SRafal Ozieblo static void hw_writel(struct macb *bp, int offset, u32 value)
246b83f1527SRafal Ozieblo {
247b83f1527SRafal Ozieblo writel_relaxed(value, bp->regs + offset);
248b83f1527SRafal Ozieblo }
249b83f1527SRafal Ozieblo
250b83f1527SRafal Ozieblo /* Find the CPU endianness by using the loopback bit of NCR register. When the
251b83f1527SRafal Ozieblo * CPU is in big endian we need to program swapped mode for management
252b83f1527SRafal Ozieblo * descriptor access.
253b83f1527SRafal Ozieblo */
hw_is_native_io(void __iomem * addr)254b83f1527SRafal Ozieblo static bool hw_is_native_io(void __iomem *addr)
255b83f1527SRafal Ozieblo {
256b83f1527SRafal Ozieblo u32 value = MACB_BIT(LLB);
257b83f1527SRafal Ozieblo
258b83f1527SRafal Ozieblo __raw_writel(value, addr + MACB_NCR);
259b83f1527SRafal Ozieblo value = __raw_readl(addr + MACB_NCR);
260b83f1527SRafal Ozieblo
261b83f1527SRafal Ozieblo /* Write 0 back to disable everything */
262b83f1527SRafal Ozieblo __raw_writel(0, addr + MACB_NCR);
263b83f1527SRafal Ozieblo
264b83f1527SRafal Ozieblo return value == MACB_BIT(LLB);
265b83f1527SRafal Ozieblo }
266b83f1527SRafal Ozieblo
hw_is_gem(void __iomem * addr,bool native_io)267b83f1527SRafal Ozieblo static bool hw_is_gem(void __iomem *addr, bool native_io)
268b83f1527SRafal Ozieblo {
269b83f1527SRafal Ozieblo u32 id;
270b83f1527SRafal Ozieblo
271b83f1527SRafal Ozieblo if (native_io)
272b83f1527SRafal Ozieblo id = __raw_readl(addr + MACB_MID);
273b83f1527SRafal Ozieblo else
274b83f1527SRafal Ozieblo id = readl_relaxed(addr + MACB_MID);
275b83f1527SRafal Ozieblo
276b83f1527SRafal Ozieblo return MACB_BFEXT(IDNUM, id) >= 0x2;
277b83f1527SRafal Ozieblo }
278b83f1527SRafal Ozieblo
macb_set_hwaddr(struct macb * bp)279b83f1527SRafal Ozieblo static void macb_set_hwaddr(struct macb *bp)
280b83f1527SRafal Ozieblo {
281b83f1527SRafal Ozieblo u32 bottom;
282b83f1527SRafal Ozieblo u16 top;
283b83f1527SRafal Ozieblo
284b83f1527SRafal Ozieblo bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
285b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA1B, bottom);
286b83f1527SRafal Ozieblo top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
287b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA1T, top);
288b83f1527SRafal Ozieblo
289ee4e92c2SHarini Katakam if (gem_has_ptp(bp)) {
290ee4e92c2SHarini Katakam gem_writel(bp, RXPTPUNI, bottom);
291ee4e92c2SHarini Katakam gem_writel(bp, TXPTPUNI, bottom);
292ee4e92c2SHarini Katakam }
293ee4e92c2SHarini Katakam
294b83f1527SRafal Ozieblo /* Clear unused address register sets */
295b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA2B, 0);
296b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA2T, 0);
297b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA3B, 0);
298b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA3T, 0);
299b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA4B, 0);
300b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA4T, 0);
301b83f1527SRafal Ozieblo }
302b83f1527SRafal Ozieblo
macb_get_hwaddr(struct macb * bp)303b83f1527SRafal Ozieblo static void macb_get_hwaddr(struct macb *bp)
304b83f1527SRafal Ozieblo {
305b83f1527SRafal Ozieblo u32 bottom;
306b83f1527SRafal Ozieblo u16 top;
307b83f1527SRafal Ozieblo u8 addr[6];
308b83f1527SRafal Ozieblo int i;
309b83f1527SRafal Ozieblo
310b83f1527SRafal Ozieblo /* Check all 4 address register for valid address */
311b83f1527SRafal Ozieblo for (i = 0; i < 4; i++) {
312b83f1527SRafal Ozieblo bottom = macb_or_gem_readl(bp, SA1B + i * 8);
313b83f1527SRafal Ozieblo top = macb_or_gem_readl(bp, SA1T + i * 8);
314b83f1527SRafal Ozieblo
315b83f1527SRafal Ozieblo addr[0] = bottom & 0xff;
316b83f1527SRafal Ozieblo addr[1] = (bottom >> 8) & 0xff;
317b83f1527SRafal Ozieblo addr[2] = (bottom >> 16) & 0xff;
318b83f1527SRafal Ozieblo addr[3] = (bottom >> 24) & 0xff;
319b83f1527SRafal Ozieblo addr[4] = top & 0xff;
320b83f1527SRafal Ozieblo addr[5] = (top >> 8) & 0xff;
321b83f1527SRafal Ozieblo
322b83f1527SRafal Ozieblo if (is_valid_ether_addr(addr)) {
323c51e5062SJakub Kicinski eth_hw_addr_set(bp->dev, addr);
324b83f1527SRafal Ozieblo return;
325b83f1527SRafal Ozieblo }
326b83f1527SRafal Ozieblo }
327b83f1527SRafal Ozieblo
328b83f1527SRafal Ozieblo dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
329b83f1527SRafal Ozieblo eth_hw_addr_random(bp->dev);
330b83f1527SRafal Ozieblo }
331b83f1527SRafal Ozieblo
macb_mdio_wait_for_idle(struct macb * bp)3328beb79b7SHarini Katakam static int macb_mdio_wait_for_idle(struct macb *bp)
3338beb79b7SHarini Katakam {
3348beb79b7SHarini Katakam u32 val;
3358beb79b7SHarini Katakam
3368beb79b7SHarini Katakam return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
3378beb79b7SHarini Katakam 1, MACB_MDIO_TIMEOUT);
3388beb79b7SHarini Katakam }
3398beb79b7SHarini Katakam
macb_mdio_read_c22(struct mii_bus * bus,int mii_id,int regnum)340a4d65b1dSAndrew Lunn static int macb_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
341b83f1527SRafal Ozieblo {
342b83f1527SRafal Ozieblo struct macb *bp = bus->priv;
343d54f89afSHarini Katakam int status;
3448beb79b7SHarini Katakam
345b66bfc13SMinghao Chi status = pm_runtime_resume_and_get(&bp->pdev->dev);
346b66bfc13SMinghao Chi if (status < 0)
347d54f89afSHarini Katakam goto mdio_pm_exit;
348d54f89afSHarini Katakam
349d54f89afSHarini Katakam status = macb_mdio_wait_for_idle(bp);
350d54f89afSHarini Katakam if (status < 0)
351d54f89afSHarini Katakam goto mdio_read_exit;
352b83f1527SRafal Ozieblo
35343ad352dSMilind Parab macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
35443ad352dSMilind Parab | MACB_BF(RW, MACB_MAN_C22_READ)
355b83f1527SRafal Ozieblo | MACB_BF(PHYA, mii_id)
356b83f1527SRafal Ozieblo | MACB_BF(REGA, regnum)
35743ad352dSMilind Parab | MACB_BF(CODE, MACB_MAN_C22_CODE)));
358b83f1527SRafal Ozieblo
359d54f89afSHarini Katakam status = macb_mdio_wait_for_idle(bp);
360d54f89afSHarini Katakam if (status < 0)
361d54f89afSHarini Katakam goto mdio_read_exit;
362b83f1527SRafal Ozieblo
363d54f89afSHarini Katakam status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
364b83f1527SRafal Ozieblo
365d54f89afSHarini Katakam mdio_read_exit:
366d54f89afSHarini Katakam pm_runtime_mark_last_busy(&bp->pdev->dev);
367d54f89afSHarini Katakam pm_runtime_put_autosuspend(&bp->pdev->dev);
368d54f89afSHarini Katakam mdio_pm_exit:
369d54f89afSHarini Katakam return status;
370b83f1527SRafal Ozieblo }
371b83f1527SRafal Ozieblo
macb_mdio_read_c45(struct mii_bus * bus,int mii_id,int devad,int regnum)372a4d65b1dSAndrew Lunn static int macb_mdio_read_c45(struct mii_bus *bus, int mii_id, int devad,
373a4d65b1dSAndrew Lunn int regnum)
374a4d65b1dSAndrew Lunn {
375a4d65b1dSAndrew Lunn struct macb *bp = bus->priv;
376a4d65b1dSAndrew Lunn int status;
377a4d65b1dSAndrew Lunn
378a4d65b1dSAndrew Lunn status = pm_runtime_get_sync(&bp->pdev->dev);
379a4d65b1dSAndrew Lunn if (status < 0) {
380a4d65b1dSAndrew Lunn pm_runtime_put_noidle(&bp->pdev->dev);
381a4d65b1dSAndrew Lunn goto mdio_pm_exit;
382a4d65b1dSAndrew Lunn }
383a4d65b1dSAndrew Lunn
384a4d65b1dSAndrew Lunn status = macb_mdio_wait_for_idle(bp);
385a4d65b1dSAndrew Lunn if (status < 0)
386a4d65b1dSAndrew Lunn goto mdio_read_exit;
387a4d65b1dSAndrew Lunn
388a4d65b1dSAndrew Lunn macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
389a4d65b1dSAndrew Lunn | MACB_BF(RW, MACB_MAN_C45_ADDR)
390a4d65b1dSAndrew Lunn | MACB_BF(PHYA, mii_id)
391a4d65b1dSAndrew Lunn | MACB_BF(REGA, devad & 0x1F)
392a4d65b1dSAndrew Lunn | MACB_BF(DATA, regnum & 0xFFFF)
393a4d65b1dSAndrew Lunn | MACB_BF(CODE, MACB_MAN_C45_CODE)));
394a4d65b1dSAndrew Lunn
395a4d65b1dSAndrew Lunn status = macb_mdio_wait_for_idle(bp);
396a4d65b1dSAndrew Lunn if (status < 0)
397a4d65b1dSAndrew Lunn goto mdio_read_exit;
398a4d65b1dSAndrew Lunn
399a4d65b1dSAndrew Lunn macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
400a4d65b1dSAndrew Lunn | MACB_BF(RW, MACB_MAN_C45_READ)
401a4d65b1dSAndrew Lunn | MACB_BF(PHYA, mii_id)
402a4d65b1dSAndrew Lunn | MACB_BF(REGA, devad & 0x1F)
403a4d65b1dSAndrew Lunn | MACB_BF(CODE, MACB_MAN_C45_CODE)));
404a4d65b1dSAndrew Lunn
405a4d65b1dSAndrew Lunn status = macb_mdio_wait_for_idle(bp);
406a4d65b1dSAndrew Lunn if (status < 0)
407a4d65b1dSAndrew Lunn goto mdio_read_exit;
408a4d65b1dSAndrew Lunn
409a4d65b1dSAndrew Lunn status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
410a4d65b1dSAndrew Lunn
411a4d65b1dSAndrew Lunn mdio_read_exit:
412a4d65b1dSAndrew Lunn pm_runtime_mark_last_busy(&bp->pdev->dev);
413a4d65b1dSAndrew Lunn pm_runtime_put_autosuspend(&bp->pdev->dev);
414a4d65b1dSAndrew Lunn mdio_pm_exit:
415a4d65b1dSAndrew Lunn return status;
416a4d65b1dSAndrew Lunn }
417a4d65b1dSAndrew Lunn
macb_mdio_write_c22(struct mii_bus * bus,int mii_id,int regnum,u16 value)418a4d65b1dSAndrew Lunn static int macb_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
419b83f1527SRafal Ozieblo u16 value)
420b83f1527SRafal Ozieblo {
421b83f1527SRafal Ozieblo struct macb *bp = bus->priv;
422d54f89afSHarini Katakam int status;
4238beb79b7SHarini Katakam
424b66bfc13SMinghao Chi status = pm_runtime_resume_and_get(&bp->pdev->dev);
425b66bfc13SMinghao Chi if (status < 0)
426d54f89afSHarini Katakam goto mdio_pm_exit;
427d54f89afSHarini Katakam
428d54f89afSHarini Katakam status = macb_mdio_wait_for_idle(bp);
429d54f89afSHarini Katakam if (status < 0)
430d54f89afSHarini Katakam goto mdio_write_exit;
431b83f1527SRafal Ozieblo
432a4d65b1dSAndrew Lunn macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
433a4d65b1dSAndrew Lunn | MACB_BF(RW, MACB_MAN_C22_WRITE)
434a4d65b1dSAndrew Lunn | MACB_BF(PHYA, mii_id)
435a4d65b1dSAndrew Lunn | MACB_BF(REGA, regnum)
436a4d65b1dSAndrew Lunn | MACB_BF(CODE, MACB_MAN_C22_CODE)
437a4d65b1dSAndrew Lunn | MACB_BF(DATA, value)));
438a4d65b1dSAndrew Lunn
439a4d65b1dSAndrew Lunn status = macb_mdio_wait_for_idle(bp);
440a4d65b1dSAndrew Lunn if (status < 0)
441a4d65b1dSAndrew Lunn goto mdio_write_exit;
442a4d65b1dSAndrew Lunn
443a4d65b1dSAndrew Lunn mdio_write_exit:
444a4d65b1dSAndrew Lunn pm_runtime_mark_last_busy(&bp->pdev->dev);
445a4d65b1dSAndrew Lunn pm_runtime_put_autosuspend(&bp->pdev->dev);
446a4d65b1dSAndrew Lunn mdio_pm_exit:
447a4d65b1dSAndrew Lunn return status;
448a4d65b1dSAndrew Lunn }
449a4d65b1dSAndrew Lunn
macb_mdio_write_c45(struct mii_bus * bus,int mii_id,int devad,int regnum,u16 value)450a4d65b1dSAndrew Lunn static int macb_mdio_write_c45(struct mii_bus *bus, int mii_id,
451a4d65b1dSAndrew Lunn int devad, int regnum,
452a4d65b1dSAndrew Lunn u16 value)
453a4d65b1dSAndrew Lunn {
454a4d65b1dSAndrew Lunn struct macb *bp = bus->priv;
455a4d65b1dSAndrew Lunn int status;
456a4d65b1dSAndrew Lunn
457a4d65b1dSAndrew Lunn status = pm_runtime_get_sync(&bp->pdev->dev);
458a4d65b1dSAndrew Lunn if (status < 0) {
459a4d65b1dSAndrew Lunn pm_runtime_put_noidle(&bp->pdev->dev);
460a4d65b1dSAndrew Lunn goto mdio_pm_exit;
461a4d65b1dSAndrew Lunn }
462a4d65b1dSAndrew Lunn
463a4d65b1dSAndrew Lunn status = macb_mdio_wait_for_idle(bp);
464a4d65b1dSAndrew Lunn if (status < 0)
465a4d65b1dSAndrew Lunn goto mdio_write_exit;
466a4d65b1dSAndrew Lunn
46743ad352dSMilind Parab macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
46843ad352dSMilind Parab | MACB_BF(RW, MACB_MAN_C45_ADDR)
46943ad352dSMilind Parab | MACB_BF(PHYA, mii_id)
470a4d65b1dSAndrew Lunn | MACB_BF(REGA, devad & 0x1F)
47143ad352dSMilind Parab | MACB_BF(DATA, regnum & 0xFFFF)
47243ad352dSMilind Parab | MACB_BF(CODE, MACB_MAN_C45_CODE)));
47343ad352dSMilind Parab
47443ad352dSMilind Parab status = macb_mdio_wait_for_idle(bp);
47543ad352dSMilind Parab if (status < 0)
47643ad352dSMilind Parab goto mdio_write_exit;
47743ad352dSMilind Parab
47843ad352dSMilind Parab macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
47943ad352dSMilind Parab | MACB_BF(RW, MACB_MAN_C45_WRITE)
48043ad352dSMilind Parab | MACB_BF(PHYA, mii_id)
481a4d65b1dSAndrew Lunn | MACB_BF(REGA, devad & 0x1F)
48243ad352dSMilind Parab | MACB_BF(CODE, MACB_MAN_C45_CODE)
48343ad352dSMilind Parab | MACB_BF(DATA, value)));
484b83f1527SRafal Ozieblo
485d54f89afSHarini Katakam status = macb_mdio_wait_for_idle(bp);
486d54f89afSHarini Katakam if (status < 0)
487d54f89afSHarini Katakam goto mdio_write_exit;
488b83f1527SRafal Ozieblo
489d54f89afSHarini Katakam mdio_write_exit:
490d54f89afSHarini Katakam pm_runtime_mark_last_busy(&bp->pdev->dev);
491d54f89afSHarini Katakam pm_runtime_put_autosuspend(&bp->pdev->dev);
492d54f89afSHarini Katakam mdio_pm_exit:
493d54f89afSHarini Katakam return status;
494b83f1527SRafal Ozieblo }
495b83f1527SRafal Ozieblo
macb_init_buffers(struct macb * bp)4966e952d95SAntoine Tenart static void macb_init_buffers(struct macb *bp)
4976e952d95SAntoine Tenart {
4986e952d95SAntoine Tenart struct macb_queue *queue;
4996e952d95SAntoine Tenart unsigned int q;
5006e952d95SAntoine Tenart
5016e952d95SAntoine Tenart for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
5026e952d95SAntoine Tenart queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
5036e952d95SAntoine Tenart #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5046e952d95SAntoine Tenart if (bp->hw_dma_cap & HW_DMA_CAP_64B)
5056e952d95SAntoine Tenart queue_writel(queue, RBQPH,
5066e952d95SAntoine Tenart upper_32_bits(queue->rx_ring_dma));
5076e952d95SAntoine Tenart #endif
5086e952d95SAntoine Tenart queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
5096e952d95SAntoine Tenart #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5106e952d95SAntoine Tenart if (bp->hw_dma_cap & HW_DMA_CAP_64B)
5116e952d95SAntoine Tenart queue_writel(queue, TBQPH,
5126e952d95SAntoine Tenart upper_32_bits(queue->tx_ring_dma));
5136e952d95SAntoine Tenart #endif
5146e952d95SAntoine Tenart }
5156e952d95SAntoine Tenart }
5166e952d95SAntoine Tenart
517b83f1527SRafal Ozieblo /**
518b83f1527SRafal Ozieblo * macb_set_tx_clk() - Set a clock to a new frequency
519daafa1d3SClaudiu Beznea * @bp: pointer to struct macb
520d0ea5cbdSJesse Brandeburg * @speed: New frequency in Hz
521b83f1527SRafal Ozieblo */
macb_set_tx_clk(struct macb * bp,int speed)522daafa1d3SClaudiu Beznea static void macb_set_tx_clk(struct macb *bp, int speed)
523b83f1527SRafal Ozieblo {
524b83f1527SRafal Ozieblo long ferr, rate, rate_rounded;
525b83f1527SRafal Ozieblo
5261d0d561aSCharles Keepax if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
527b83f1527SRafal Ozieblo return;
528b83f1527SRafal Ozieblo
52943e57631SMichael Walle /* In case of MII the PHY is the clock master */
53043e57631SMichael Walle if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
53143e57631SMichael Walle return;
53243e57631SMichael Walle
533b83f1527SRafal Ozieblo switch (speed) {
534b83f1527SRafal Ozieblo case SPEED_10:
535b83f1527SRafal Ozieblo rate = 2500000;
536b83f1527SRafal Ozieblo break;
537b83f1527SRafal Ozieblo case SPEED_100:
538b83f1527SRafal Ozieblo rate = 25000000;
539b83f1527SRafal Ozieblo break;
540b83f1527SRafal Ozieblo case SPEED_1000:
541b83f1527SRafal Ozieblo rate = 125000000;
542b83f1527SRafal Ozieblo break;
543b83f1527SRafal Ozieblo default:
544b83f1527SRafal Ozieblo return;
545b83f1527SRafal Ozieblo }
546b83f1527SRafal Ozieblo
547daafa1d3SClaudiu Beznea rate_rounded = clk_round_rate(bp->tx_clk, rate);
548b83f1527SRafal Ozieblo if (rate_rounded < 0)
549b83f1527SRafal Ozieblo return;
550b83f1527SRafal Ozieblo
551b83f1527SRafal Ozieblo /* RGMII allows 50 ppm frequency error. Test and warn if this limit
552b83f1527SRafal Ozieblo * is not satisfied.
553b83f1527SRafal Ozieblo */
554b83f1527SRafal Ozieblo ferr = abs(rate_rounded - rate);
555b83f1527SRafal Ozieblo ferr = DIV_ROUND_UP(ferr, rate / 100000);
556b83f1527SRafal Ozieblo if (ferr > 5)
557daafa1d3SClaudiu Beznea netdev_warn(bp->dev,
558daafa1d3SClaudiu Beznea "unable to generate target frequency: %ld Hz\n",
559b83f1527SRafal Ozieblo rate);
560b83f1527SRafal Ozieblo
561daafa1d3SClaudiu Beznea if (clk_set_rate(bp->tx_clk, rate_rounded))
562daafa1d3SClaudiu Beznea netdev_err(bp->dev, "adjusting tx_clk failed.\n");
563b83f1527SRafal Ozieblo }
564b83f1527SRafal Ozieblo
macb_usx_pcs_link_up(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex)565f40df95dSRussell King (Oracle) static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
566e4e143e2SParshuram Thombare phy_interface_t interface, int speed,
567e4e143e2SParshuram Thombare int duplex)
568e4e143e2SParshuram Thombare {
5698876769bSRussell King (Oracle) struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
570e4e143e2SParshuram Thombare u32 config;
571e4e143e2SParshuram Thombare
572e4e143e2SParshuram Thombare config = gem_readl(bp, USX_CONTROL);
573e4e143e2SParshuram Thombare config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
574e4e143e2SParshuram Thombare config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
575e4e143e2SParshuram Thombare config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
576e4e143e2SParshuram Thombare config |= GEM_BIT(TX_EN);
577e4e143e2SParshuram Thombare gem_writel(bp, USX_CONTROL, config);
578e4e143e2SParshuram Thombare }
579e4e143e2SParshuram Thombare
macb_usx_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)580e4e143e2SParshuram Thombare static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
581e4e143e2SParshuram Thombare struct phylink_link_state *state)
582e4e143e2SParshuram Thombare {
5838876769bSRussell King (Oracle) struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
584e4e143e2SParshuram Thombare u32 val;
585e4e143e2SParshuram Thombare
586e4e143e2SParshuram Thombare state->speed = SPEED_10000;
587e4e143e2SParshuram Thombare state->duplex = 1;
588e4e143e2SParshuram Thombare state->an_complete = 1;
589e4e143e2SParshuram Thombare
590e4e143e2SParshuram Thombare val = gem_readl(bp, USX_STATUS);
591e4e143e2SParshuram Thombare state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
592e4e143e2SParshuram Thombare val = gem_readl(bp, NCFGR);
593e4e143e2SParshuram Thombare if (val & GEM_BIT(PAE))
594e4e143e2SParshuram Thombare state->pause = MLO_PAUSE_RX;
595e4e143e2SParshuram Thombare }
596e4e143e2SParshuram Thombare
macb_usx_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)597e4e143e2SParshuram Thombare static int macb_usx_pcs_config(struct phylink_pcs *pcs,
598f40df95dSRussell King (Oracle) unsigned int neg_mode,
599e4e143e2SParshuram Thombare phy_interface_t interface,
600e4e143e2SParshuram Thombare const unsigned long *advertising,
601e4e143e2SParshuram Thombare bool permit_pause_to_mac)
602e4e143e2SParshuram Thombare {
6038876769bSRussell King (Oracle) struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
604e4e143e2SParshuram Thombare
605e4e143e2SParshuram Thombare gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
606e4e143e2SParshuram Thombare GEM_BIT(SIGNAL_OK));
607e4e143e2SParshuram Thombare
608e4e143e2SParshuram Thombare return 0;
609e4e143e2SParshuram Thombare }
610e4e143e2SParshuram Thombare
macb_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)611e4e143e2SParshuram Thombare static void macb_pcs_get_state(struct phylink_pcs *pcs,
6127897b071SAntoine Tenart struct phylink_link_state *state)
6137897b071SAntoine Tenart {
614d46b7e4fSRussell King state->link = 0;
6157897b071SAntoine Tenart }
6167897b071SAntoine Tenart
macb_pcs_an_restart(struct phylink_pcs * pcs)617e4e143e2SParshuram Thombare static void macb_pcs_an_restart(struct phylink_pcs *pcs)
6187897b071SAntoine Tenart {
6197897b071SAntoine Tenart /* Not supported */
6207897b071SAntoine Tenart }
6217897b071SAntoine Tenart
macb_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)6220012eeb3SParshuram Thombare static int macb_pcs_config(struct phylink_pcs *pcs,
623f40df95dSRussell King (Oracle) unsigned int neg_mode,
6240012eeb3SParshuram Thombare phy_interface_t interface,
6250012eeb3SParshuram Thombare const unsigned long *advertising,
6260012eeb3SParshuram Thombare bool permit_pause_to_mac)
6270012eeb3SParshuram Thombare {
6280012eeb3SParshuram Thombare return 0;
6290012eeb3SParshuram Thombare }
6300012eeb3SParshuram Thombare
631e4e143e2SParshuram Thombare static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
632e4e143e2SParshuram Thombare .pcs_get_state = macb_usx_pcs_get_state,
633e4e143e2SParshuram Thombare .pcs_config = macb_usx_pcs_config,
634e4e143e2SParshuram Thombare .pcs_link_up = macb_usx_pcs_link_up,
635e4e143e2SParshuram Thombare };
636e4e143e2SParshuram Thombare
637e4e143e2SParshuram Thombare static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
638e4e143e2SParshuram Thombare .pcs_get_state = macb_pcs_get_state,
639e4e143e2SParshuram Thombare .pcs_an_restart = macb_pcs_an_restart,
6400012eeb3SParshuram Thombare .pcs_config = macb_pcs_config,
641e4e143e2SParshuram Thombare };
642e4e143e2SParshuram Thombare
macb_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)6437897b071SAntoine Tenart static void macb_mac_config(struct phylink_config *config, unsigned int mode,
6447897b071SAntoine Tenart const struct phylink_link_state *state)
6457897b071SAntoine Tenart {
6467897b071SAntoine Tenart struct net_device *ndev = to_net_dev(config->dev);
6477897b071SAntoine Tenart struct macb *bp = netdev_priv(ndev);
648b83f1527SRafal Ozieblo unsigned long flags;
6497897b071SAntoine Tenart u32 old_ctrl, ctrl;
650e4e143e2SParshuram Thombare u32 old_ncr, ncr;
651b83f1527SRafal Ozieblo
652b83f1527SRafal Ozieblo spin_lock_irqsave(&bp->lock, flags);
653b83f1527SRafal Ozieblo
6547897b071SAntoine Tenart old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
655e4e143e2SParshuram Thombare old_ncr = ncr = macb_or_gem_readl(bp, NCR);
656b83f1527SRafal Ozieblo
657ac2fcfa9SAlexandre Belloni if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
658ac2fcfa9SAlexandre Belloni if (state->interface == PHY_INTERFACE_MODE_RMII)
659ac2fcfa9SAlexandre Belloni ctrl |= MACB_BIT(RM9200_RMII);
660f7ba7dbfSStefan Roese } else if (macb_is_gem(bp)) {
661633e98a7SRussell King ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
662e4e143e2SParshuram Thombare ncr &= ~GEM_BIT(ENABLE_HS_MAC);
663ac2fcfa9SAlexandre Belloni
664e4e143e2SParshuram Thombare if (state->interface == PHY_INTERFACE_MODE_SGMII) {
665ac2fcfa9SAlexandre Belloni ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
666e4e143e2SParshuram Thombare } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
667e4e143e2SParshuram Thombare ctrl |= GEM_BIT(PCSSEL);
668e4e143e2SParshuram Thombare ncr |= GEM_BIT(ENABLE_HS_MAC);
6691a9b5a26SClaudiu Beznea } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
6701a9b5a26SClaudiu Beznea bp->phy_interface == PHY_INTERFACE_MODE_MII) {
6711a9b5a26SClaudiu Beznea ncr |= MACB_BIT(MIIONRGMII);
672e4e143e2SParshuram Thombare }
673ac2fcfa9SAlexandre Belloni }
674b83f1527SRafal Ozieblo
6757897b071SAntoine Tenart /* Apply the new configuration, if any */
6767897b071SAntoine Tenart if (old_ctrl ^ ctrl)
6777897b071SAntoine Tenart macb_or_gem_writel(bp, NCFGR, ctrl);
6787897b071SAntoine Tenart
679e4e143e2SParshuram Thombare if (old_ncr ^ ncr)
680e4e143e2SParshuram Thombare macb_or_gem_writel(bp, NCR, ncr);
681e4e143e2SParshuram Thombare
682e276e5e4SRobert Hancock /* Disable AN for SGMII fixed link configuration, enable otherwise.
683e276e5e4SRobert Hancock * Must be written after PCSSEL is set in NCFGR,
684e276e5e4SRobert Hancock * otherwise writes will not take effect.
685e276e5e4SRobert Hancock */
686e276e5e4SRobert Hancock if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
687e276e5e4SRobert Hancock u32 pcsctrl, old_pcsctrl;
688e276e5e4SRobert Hancock
689e276e5e4SRobert Hancock old_pcsctrl = gem_readl(bp, PCSCNTRL);
690e276e5e4SRobert Hancock if (mode == MLO_AN_FIXED)
691e276e5e4SRobert Hancock pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
692e276e5e4SRobert Hancock else
693e276e5e4SRobert Hancock pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
694e276e5e4SRobert Hancock if (old_pcsctrl != pcsctrl)
695e276e5e4SRobert Hancock gem_writel(bp, PCSCNTRL, pcsctrl);
696e276e5e4SRobert Hancock }
697e276e5e4SRobert Hancock
698b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags);
699b83f1527SRafal Ozieblo }
700b83f1527SRafal Ozieblo
macb_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)7017897b071SAntoine Tenart static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
7027897b071SAntoine Tenart phy_interface_t interface)
703b83f1527SRafal Ozieblo {
7047897b071SAntoine Tenart struct net_device *ndev = to_net_dev(config->dev);
7057897b071SAntoine Tenart struct macb *bp = netdev_priv(ndev);
7067897b071SAntoine Tenart struct macb_queue *queue;
7077897b071SAntoine Tenart unsigned int q;
7087897b071SAntoine Tenart u32 ctrl;
709739de9a1SBrad Mouring
710ac2fcfa9SAlexandre Belloni if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
7117897b071SAntoine Tenart for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
7127897b071SAntoine Tenart queue_writel(queue, IDR,
7137897b071SAntoine Tenart bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
714739de9a1SBrad Mouring
7157897b071SAntoine Tenart /* Disable Rx and Tx */
7167897b071SAntoine Tenart ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
7177897b071SAntoine Tenart macb_writel(bp, NCR, ctrl);
7187897b071SAntoine Tenart
7197897b071SAntoine Tenart netif_tx_stop_all_queues(ndev);
7207897b071SAntoine Tenart }
7217897b071SAntoine Tenart
macb_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)72291a208f2SRussell King static void macb_mac_link_up(struct phylink_config *config,
72391a208f2SRussell King struct phy_device *phy,
72491a208f2SRussell King unsigned int mode, phy_interface_t interface,
72591a208f2SRussell King int speed, int duplex,
72691a208f2SRussell King bool tx_pause, bool rx_pause)
7277897b071SAntoine Tenart {
7287897b071SAntoine Tenart struct net_device *ndev = to_net_dev(config->dev);
7297897b071SAntoine Tenart struct macb *bp = netdev_priv(ndev);
7307897b071SAntoine Tenart struct macb_queue *queue;
731633e98a7SRussell King unsigned long flags;
7327897b071SAntoine Tenart unsigned int q;
733633e98a7SRussell King u32 ctrl;
734633e98a7SRussell King
735633e98a7SRussell King spin_lock_irqsave(&bp->lock, flags);
736633e98a7SRussell King
737633e98a7SRussell King ctrl = macb_or_gem_readl(bp, NCFGR);
738633e98a7SRussell King
739633e98a7SRussell King ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
740633e98a7SRussell King
741633e98a7SRussell King if (speed == SPEED_100)
742633e98a7SRussell King ctrl |= MACB_BIT(SPD);
743633e98a7SRussell King
744633e98a7SRussell King if (duplex)
745633e98a7SRussell King ctrl |= MACB_BIT(FD);
7467897b071SAntoine Tenart
747ac2fcfa9SAlexandre Belloni if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
748f7ba7dbfSStefan Roese ctrl &= ~MACB_BIT(PAE);
749f7ba7dbfSStefan Roese if (macb_is_gem(bp)) {
750f7ba7dbfSStefan Roese ctrl &= ~GEM_BIT(GBE);
751633e98a7SRussell King
752633e98a7SRussell King if (speed == SPEED_1000)
753633e98a7SRussell King ctrl |= GEM_BIT(GBE);
754f7ba7dbfSStefan Roese }
755633e98a7SRussell King
756d7739b0bSParshuram Thombare if (rx_pause)
757633e98a7SRussell King ctrl |= MACB_BIT(PAE);
758633e98a7SRussell King
7597897b071SAntoine Tenart /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
7607897b071SAntoine Tenart * cleared the pipeline and control registers.
761739de9a1SBrad Mouring */
7627897b071SAntoine Tenart bp->macbgem_ops.mog_init_rings(bp);
7637897b071SAntoine Tenart macb_init_buffers(bp);
7647897b071SAntoine Tenart
7657897b071SAntoine Tenart for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
7667897b071SAntoine Tenart queue_writel(queue, IER,
7677897b071SAntoine Tenart bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
768ac2fcfa9SAlexandre Belloni }
7697897b071SAntoine Tenart
770633e98a7SRussell King macb_or_gem_writel(bp, NCFGR, ctrl);
771633e98a7SRussell King
772e4e143e2SParshuram Thombare if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
773e4e143e2SParshuram Thombare gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
774e4e143e2SParshuram Thombare gem_readl(bp, HS_MAC_CONFIG)));
775e4e143e2SParshuram Thombare
776633e98a7SRussell King spin_unlock_irqrestore(&bp->lock, flags);
777633e98a7SRussell King
778403f0e77SSascha Hauer if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
779403f0e77SSascha Hauer macb_set_tx_clk(bp, speed);
780403f0e77SSascha Hauer
781ee4e92c2SHarini Katakam /* Enable Rx and Tx; Enable PTP unicast */
782ee4e92c2SHarini Katakam ctrl = macb_readl(bp, NCR);
783ee4e92c2SHarini Katakam if (gem_has_ptp(bp))
784ee4e92c2SHarini Katakam ctrl |= MACB_BIT(PTPUNI);
785ee4e92c2SHarini Katakam
786ee4e92c2SHarini Katakam macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE));
7877897b071SAntoine Tenart
7887897b071SAntoine Tenart netif_tx_wake_all_queues(ndev);
789739de9a1SBrad Mouring }
790739de9a1SBrad Mouring
macb_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)7918876769bSRussell King (Oracle) static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
792e4e143e2SParshuram Thombare phy_interface_t interface)
793e4e143e2SParshuram Thombare {
794e4e143e2SParshuram Thombare struct net_device *ndev = to_net_dev(config->dev);
795e4e143e2SParshuram Thombare struct macb *bp = netdev_priv(ndev);
796e4e143e2SParshuram Thombare
797e4e143e2SParshuram Thombare if (interface == PHY_INTERFACE_MODE_10GBASER)
7988876769bSRussell King (Oracle) return &bp->phylink_usx_pcs;
7990012eeb3SParshuram Thombare else if (interface == PHY_INTERFACE_MODE_SGMII)
8008876769bSRussell King (Oracle) return &bp->phylink_sgmii_pcs;
8010012eeb3SParshuram Thombare else
8028876769bSRussell King (Oracle) return NULL;
803e4e143e2SParshuram Thombare }
804e4e143e2SParshuram Thombare
8057897b071SAntoine Tenart static const struct phylink_mac_ops macb_phylink_ops = {
8068876769bSRussell King (Oracle) .mac_select_pcs = macb_mac_select_pcs,
8077897b071SAntoine Tenart .mac_config = macb_mac_config,
8087897b071SAntoine Tenart .mac_link_down = macb_mac_link_down,
8097897b071SAntoine Tenart .mac_link_up = macb_mac_link_up,
8107897b071SAntoine Tenart };
811b83f1527SRafal Ozieblo
macb_phy_handle_exists(struct device_node * dn)812fd2a8914SMilind Parab static bool macb_phy_handle_exists(struct device_node *dn)
813fd2a8914SMilind Parab {
814fd2a8914SMilind Parab dn = of_parse_phandle(dn, "phy-handle", 0);
815fd2a8914SMilind Parab of_node_put(dn);
816fd2a8914SMilind Parab return dn != NULL;
817fd2a8914SMilind Parab }
818fd2a8914SMilind Parab
macb_phylink_connect(struct macb * bp)8197897b071SAntoine Tenart static int macb_phylink_connect(struct macb *bp)
8207897b071SAntoine Tenart {
821fd2a8914SMilind Parab struct device_node *dn = bp->pdev->dev.of_node;
8227897b071SAntoine Tenart struct net_device *dev = bp->dev;
8237897b071SAntoine Tenart struct phy_device *phydev;
8247897b071SAntoine Tenart int ret;
8257897b071SAntoine Tenart
826fd2a8914SMilind Parab if (dn)
827fd2a8914SMilind Parab ret = phylink_of_phy_connect(bp->phylink, dn, 0);
828fd2a8914SMilind Parab
829fd2a8914SMilind Parab if (!dn || (ret && !macb_phy_handle_exists(dn))) {
830b83f1527SRafal Ozieblo phydev = phy_find_first(bp->mii_bus);
831b83f1527SRafal Ozieblo if (!phydev) {
832b83f1527SRafal Ozieblo netdev_err(dev, "no PHY found\n");
833b83f1527SRafal Ozieblo return -ENXIO;
834b83f1527SRafal Ozieblo }
835b83f1527SRafal Ozieblo
836b83f1527SRafal Ozieblo /* attach the mac to the phy */
8377897b071SAntoine Tenart ret = phylink_connect_phy(bp->phylink, phydev);
838b83f1527SRafal Ozieblo }
839fd2a8914SMilind Parab
840fd2a8914SMilind Parab if (ret) {
841fd2a8914SMilind Parab netdev_err(dev, "Could not attach PHY (%d)\n", ret);
842fd2a8914SMilind Parab return ret;
843b83f1527SRafal Ozieblo }
844b83f1527SRafal Ozieblo
8457897b071SAntoine Tenart phylink_start(bp->phylink);
846b83f1527SRafal Ozieblo
8477897b071SAntoine Tenart return 0;
8487897b071SAntoine Tenart }
849b83f1527SRafal Ozieblo
macb_get_pcs_fixed_state(struct phylink_config * config,struct phylink_link_state * state)8508fab174bSRobert Hancock static void macb_get_pcs_fixed_state(struct phylink_config *config,
8518fab174bSRobert Hancock struct phylink_link_state *state)
8528fab174bSRobert Hancock {
8538fab174bSRobert Hancock struct net_device *ndev = to_net_dev(config->dev);
8548fab174bSRobert Hancock struct macb *bp = netdev_priv(ndev);
8558fab174bSRobert Hancock
8568fab174bSRobert Hancock state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
8578fab174bSRobert Hancock }
8588fab174bSRobert Hancock
8597897b071SAntoine Tenart /* based on au1000_eth. c*/
macb_mii_probe(struct net_device * dev)8607897b071SAntoine Tenart static int macb_mii_probe(struct net_device *dev)
8617897b071SAntoine Tenart {
8627897b071SAntoine Tenart struct macb *bp = netdev_priv(dev);
8637897b071SAntoine Tenart
8648876769bSRussell King (Oracle) bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
865f40df95dSRussell King (Oracle) bp->phylink_sgmii_pcs.neg_mode = true;
8668876769bSRussell King (Oracle) bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
867f40df95dSRussell King (Oracle) bp->phylink_usx_pcs.neg_mode = true;
8688876769bSRussell King (Oracle)
8697897b071SAntoine Tenart bp->phylink_config.dev = &dev->dev;
8707897b071SAntoine Tenart bp->phylink_config.type = PHYLINK_NETDEV;
87115a9dbecSSergiu Moga bp->phylink_config.mac_managed_pm = true;
8727897b071SAntoine Tenart
8738fab174bSRobert Hancock if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
8748fab174bSRobert Hancock bp->phylink_config.poll_fixed_state = true;
8758fab174bSRobert Hancock bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
8768fab174bSRobert Hancock }
8778fab174bSRobert Hancock
878cc0a75ebSRussell King (Oracle) bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
879cc0a75ebSRussell King (Oracle) MAC_10 | MAC_100;
880cc0a75ebSRussell King (Oracle)
881cc0a75ebSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_MII,
882cc0a75ebSRussell King (Oracle) bp->phylink_config.supported_interfaces);
883cc0a75ebSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_RMII,
884cc0a75ebSRussell King (Oracle) bp->phylink_config.supported_interfaces);
885cc0a75ebSRussell King (Oracle)
886cc0a75ebSRussell King (Oracle) /* Determine what modes are supported */
887cc0a75ebSRussell King (Oracle) if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
888cc0a75ebSRussell King (Oracle) bp->phylink_config.mac_capabilities |= MAC_1000FD;
889cc0a75ebSRussell King (Oracle) if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
890cc0a75ebSRussell King (Oracle) bp->phylink_config.mac_capabilities |= MAC_1000HD;
891cc0a75ebSRussell King (Oracle)
892cc0a75ebSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_GMII,
893cc0a75ebSRussell King (Oracle) bp->phylink_config.supported_interfaces);
894cc0a75ebSRussell King (Oracle) phy_interface_set_rgmii(bp->phylink_config.supported_interfaces);
895cc0a75ebSRussell King (Oracle)
896cc0a75ebSRussell King (Oracle) if (bp->caps & MACB_CAPS_PCS)
897cc0a75ebSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_SGMII,
898cc0a75ebSRussell King (Oracle) bp->phylink_config.supported_interfaces);
899cc0a75ebSRussell King (Oracle)
900cc0a75ebSRussell King (Oracle) if (bp->caps & MACB_CAPS_HIGH_SPEED) {
901cc0a75ebSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_10GBASER,
902cc0a75ebSRussell King (Oracle) bp->phylink_config.supported_interfaces);
903cc0a75ebSRussell King (Oracle) bp->phylink_config.mac_capabilities |= MAC_10000FD;
904cc0a75ebSRussell King (Oracle) }
905cc0a75ebSRussell King (Oracle) }
906cc0a75ebSRussell King (Oracle)
9077897b071SAntoine Tenart bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
9087897b071SAntoine Tenart bp->phy_interface, &macb_phylink_ops);
9097897b071SAntoine Tenart if (IS_ERR(bp->phylink)) {
9107897b071SAntoine Tenart netdev_err(dev, "Could not create a phylink instance (%ld)\n",
9117897b071SAntoine Tenart PTR_ERR(bp->phylink));
9127897b071SAntoine Tenart return PTR_ERR(bp->phylink);
9137897b071SAntoine Tenart }
914b83f1527SRafal Ozieblo
915b83f1527SRafal Ozieblo return 0;
916b83f1527SRafal Ozieblo }
917b83f1527SRafal Ozieblo
macb_mdiobus_register(struct macb * bp)918ef8a2e27SAntoine Tenart static int macb_mdiobus_register(struct macb *bp)
919ef8a2e27SAntoine Tenart {
920ef8a2e27SAntoine Tenart struct device_node *child, *np = bp->pdev->dev.of_node;
921ef8a2e27SAntoine Tenart
9224d98bb0dSSean Anderson /* If we have a child named mdio, probe it instead of looking for PHYs
9234d98bb0dSSean Anderson * directly under the MAC node
9244d98bb0dSSean Anderson */
9254d98bb0dSSean Anderson child = of_get_child_by_name(np, "mdio");
9268db3cbc5SGuenter Roeck if (child) {
9274d98bb0dSSean Anderson int ret = of_mdiobus_register(bp->mii_bus, child);
9284d98bb0dSSean Anderson
9294d98bb0dSSean Anderson of_node_put(child);
9304d98bb0dSSean Anderson return ret;
9314d98bb0dSSean Anderson }
9324d98bb0dSSean Anderson
93379540d13SCodrin Ciubotariu if (of_phy_is_fixed_link(np))
93479540d13SCodrin Ciubotariu return mdiobus_register(bp->mii_bus);
93579540d13SCodrin Ciubotariu
936ef8a2e27SAntoine Tenart /* Only create the PHY from the device tree if at least one PHY is
937ef8a2e27SAntoine Tenart * described. Otherwise scan the entire MDIO bus. We do this to support
938ef8a2e27SAntoine Tenart * old device tree that did not follow the best practices and did not
939ef8a2e27SAntoine Tenart * describe their network PHYs.
940ef8a2e27SAntoine Tenart */
941ef8a2e27SAntoine Tenart for_each_available_child_of_node(np, child)
942ef8a2e27SAntoine Tenart if (of_mdiobus_child_is_phy(child)) {
943ef8a2e27SAntoine Tenart /* The loop increments the child refcount,
944ef8a2e27SAntoine Tenart * decrement it before returning.
945ef8a2e27SAntoine Tenart */
946ef8a2e27SAntoine Tenart of_node_put(child);
947ef8a2e27SAntoine Tenart
948ef8a2e27SAntoine Tenart return of_mdiobus_register(bp->mii_bus, np);
949ef8a2e27SAntoine Tenart }
950ef8a2e27SAntoine Tenart
951ef8a2e27SAntoine Tenart return mdiobus_register(bp->mii_bus);
952ef8a2e27SAntoine Tenart }
953ef8a2e27SAntoine Tenart
macb_mii_init(struct macb * bp)954b83f1527SRafal Ozieblo static int macb_mii_init(struct macb *bp)
955b83f1527SRafal Ozieblo {
956ab5f1105SAhmad Fatoum int err = -ENXIO;
957b83f1527SRafal Ozieblo
958b83f1527SRafal Ozieblo /* Enable management port */
959b83f1527SRafal Ozieblo macb_writel(bp, NCR, MACB_BIT(MPE));
960b83f1527SRafal Ozieblo
961b83f1527SRafal Ozieblo bp->mii_bus = mdiobus_alloc();
962b83f1527SRafal Ozieblo if (!bp->mii_bus) {
963b83f1527SRafal Ozieblo err = -ENOMEM;
964b83f1527SRafal Ozieblo goto err_out;
965b83f1527SRafal Ozieblo }
966b83f1527SRafal Ozieblo
967b83f1527SRafal Ozieblo bp->mii_bus->name = "MACB_mii_bus";
968a4d65b1dSAndrew Lunn bp->mii_bus->read = &macb_mdio_read_c22;
969a4d65b1dSAndrew Lunn bp->mii_bus->write = &macb_mdio_write_c22;
970a4d65b1dSAndrew Lunn bp->mii_bus->read_c45 = &macb_mdio_read_c45;
971a4d65b1dSAndrew Lunn bp->mii_bus->write_c45 = &macb_mdio_write_c45;
972b83f1527SRafal Ozieblo snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
973b83f1527SRafal Ozieblo bp->pdev->name, bp->pdev->id);
974b83f1527SRafal Ozieblo bp->mii_bus->priv = bp;
975b83f1527SRafal Ozieblo bp->mii_bus->parent = &bp->pdev->dev;
976b83f1527SRafal Ozieblo
977b83f1527SRafal Ozieblo dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
978b83f1527SRafal Ozieblo
979ef8a2e27SAntoine Tenart err = macb_mdiobus_register(bp);
980b83f1527SRafal Ozieblo if (err)
9817897b071SAntoine Tenart goto err_out_free_mdiobus;
982b83f1527SRafal Ozieblo
983b83f1527SRafal Ozieblo err = macb_mii_probe(bp->dev);
984b83f1527SRafal Ozieblo if (err)
985b83f1527SRafal Ozieblo goto err_out_unregister_bus;
986b83f1527SRafal Ozieblo
987b83f1527SRafal Ozieblo return 0;
988b83f1527SRafal Ozieblo
989b83f1527SRafal Ozieblo err_out_unregister_bus:
990b83f1527SRafal Ozieblo mdiobus_unregister(bp->mii_bus);
991739de9a1SBrad Mouring err_out_free_mdiobus:
992b83f1527SRafal Ozieblo mdiobus_free(bp->mii_bus);
993b83f1527SRafal Ozieblo err_out:
994b83f1527SRafal Ozieblo return err;
995b83f1527SRafal Ozieblo }
996b83f1527SRafal Ozieblo
macb_update_stats(struct macb * bp)997b83f1527SRafal Ozieblo static void macb_update_stats(struct macb *bp)
998b83f1527SRafal Ozieblo {
999b83f1527SRafal Ozieblo u32 *p = &bp->hw_stats.macb.rx_pause_frames;
1000b83f1527SRafal Ozieblo u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
1001b83f1527SRafal Ozieblo int offset = MACB_PFR;
1002b83f1527SRafal Ozieblo
1003b83f1527SRafal Ozieblo WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
1004b83f1527SRafal Ozieblo
1005b83f1527SRafal Ozieblo for (; p < end; p++, offset += 4)
1006b83f1527SRafal Ozieblo *p += bp->macb_reg_readl(bp, offset);
1007b83f1527SRafal Ozieblo }
1008b83f1527SRafal Ozieblo
macb_halt_tx(struct macb * bp)1009b83f1527SRafal Ozieblo static int macb_halt_tx(struct macb *bp)
1010b83f1527SRafal Ozieblo {
1011b83f1527SRafal Ozieblo unsigned long halt_time, timeout;
1012b83f1527SRafal Ozieblo u32 status;
1013b83f1527SRafal Ozieblo
1014b83f1527SRafal Ozieblo macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
1015b83f1527SRafal Ozieblo
1016b83f1527SRafal Ozieblo timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
1017b83f1527SRafal Ozieblo do {
1018b83f1527SRafal Ozieblo halt_time = jiffies;
1019b83f1527SRafal Ozieblo status = macb_readl(bp, TSR);
1020b83f1527SRafal Ozieblo if (!(status & MACB_BIT(TGO)))
1021b83f1527SRafal Ozieblo return 0;
1022b83f1527SRafal Ozieblo
102316fe10cfSJia-Ju Bai udelay(250);
1024b83f1527SRafal Ozieblo } while (time_before(halt_time, timeout));
1025b83f1527SRafal Ozieblo
1026b83f1527SRafal Ozieblo return -ETIMEDOUT;
1027b83f1527SRafal Ozieblo }
1028b83f1527SRafal Ozieblo
macb_tx_unmap(struct macb * bp,struct macb_tx_skb * tx_skb,int budget)1029138badbcSRobert Hancock static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget)
1030b83f1527SRafal Ozieblo {
1031b83f1527SRafal Ozieblo if (tx_skb->mapping) {
1032b83f1527SRafal Ozieblo if (tx_skb->mapped_as_page)
1033b83f1527SRafal Ozieblo dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
1034b83f1527SRafal Ozieblo tx_skb->size, DMA_TO_DEVICE);
1035b83f1527SRafal Ozieblo else
1036b83f1527SRafal Ozieblo dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
1037b83f1527SRafal Ozieblo tx_skb->size, DMA_TO_DEVICE);
1038b83f1527SRafal Ozieblo tx_skb->mapping = 0;
1039b83f1527SRafal Ozieblo }
1040b83f1527SRafal Ozieblo
1041b83f1527SRafal Ozieblo if (tx_skb->skb) {
1042138badbcSRobert Hancock napi_consume_skb(tx_skb->skb, budget);
1043b83f1527SRafal Ozieblo tx_skb->skb = NULL;
1044b83f1527SRafal Ozieblo }
1045b83f1527SRafal Ozieblo }
1046b83f1527SRafal Ozieblo
macb_set_addr(struct macb * bp,struct macb_dma_desc * desc,dma_addr_t addr)1047b83f1527SRafal Ozieblo static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
1048b83f1527SRafal Ozieblo {
1049b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1050b83f1527SRafal Ozieblo struct macb_dma_desc_64 *desc_64;
1051b83f1527SRafal Ozieblo
1052b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1053b83f1527SRafal Ozieblo desc_64 = macb_64b_desc(bp, desc);
1054b83f1527SRafal Ozieblo desc_64->addrh = upper_32_bits(addr);
1055e100a897SAnssi Hannula /* The low bits of RX address contain the RX_USED bit, clearing
1056e100a897SAnssi Hannula * of which allows packet RX. Make sure the high bits are also
1057e100a897SAnssi Hannula * visible to HW at that point.
1058e100a897SAnssi Hannula */
1059e100a897SAnssi Hannula dma_wmb();
1060b83f1527SRafal Ozieblo }
1061b83f1527SRafal Ozieblo #endif
1062b83f1527SRafal Ozieblo desc->addr = lower_32_bits(addr);
1063b83f1527SRafal Ozieblo }
1064b83f1527SRafal Ozieblo
macb_get_addr(struct macb * bp,struct macb_dma_desc * desc)1065b83f1527SRafal Ozieblo static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1066b83f1527SRafal Ozieblo {
1067b83f1527SRafal Ozieblo dma_addr_t addr = 0;
1068b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1069b83f1527SRafal Ozieblo struct macb_dma_desc_64 *desc_64;
1070b83f1527SRafal Ozieblo
1071b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1072b83f1527SRafal Ozieblo desc_64 = macb_64b_desc(bp, desc);
1073b83f1527SRafal Ozieblo addr = ((u64)(desc_64->addrh) << 32);
1074b83f1527SRafal Ozieblo }
1075b83f1527SRafal Ozieblo #endif
1076b83f1527SRafal Ozieblo addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1077e8b74453SRoman Gushchin #ifdef CONFIG_MACB_USE_HWSTAMP
1078e8b74453SRoman Gushchin if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
1079e8b74453SRoman Gushchin addr &= ~GEM_BIT(DMA_RXVALID);
1080e8b74453SRoman Gushchin #endif
1081b83f1527SRafal Ozieblo return addr;
1082b83f1527SRafal Ozieblo }
1083b83f1527SRafal Ozieblo
macb_tx_error_task(struct work_struct * work)1084b83f1527SRafal Ozieblo static void macb_tx_error_task(struct work_struct *work)
1085b83f1527SRafal Ozieblo {
1086b83f1527SRafal Ozieblo struct macb_queue *queue = container_of(work, struct macb_queue,
1087b83f1527SRafal Ozieblo tx_error_task);
108872abf217SHarini Katakam bool halt_timeout = false;
1089b83f1527SRafal Ozieblo struct macb *bp = queue->bp;
1090b83f1527SRafal Ozieblo struct macb_tx_skb *tx_skb;
1091b83f1527SRafal Ozieblo struct macb_dma_desc *desc;
1092b83f1527SRafal Ozieblo struct sk_buff *skb;
1093b83f1527SRafal Ozieblo unsigned int tail;
1094b83f1527SRafal Ozieblo unsigned long flags;
1095b83f1527SRafal Ozieblo
1096b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1097b83f1527SRafal Ozieblo (unsigned int)(queue - bp->queues),
1098b83f1527SRafal Ozieblo queue->tx_tail, queue->tx_head);
1099b83f1527SRafal Ozieblo
1100138badbcSRobert Hancock /* Prevent the queue NAPI TX poll from running, as it calls
1101138badbcSRobert Hancock * macb_tx_complete(), which in turn may call netif_wake_subqueue().
1102b83f1527SRafal Ozieblo * As explained below, we have to halt the transmission before updating
1103b83f1527SRafal Ozieblo * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1104b83f1527SRafal Ozieblo * network engine about the macb/gem being halted.
1105b83f1527SRafal Ozieblo */
1106138badbcSRobert Hancock napi_disable(&queue->napi_tx);
1107b83f1527SRafal Ozieblo spin_lock_irqsave(&bp->lock, flags);
1108b83f1527SRafal Ozieblo
1109b83f1527SRafal Ozieblo /* Make sure nobody is trying to queue up new packets */
1110b83f1527SRafal Ozieblo netif_tx_stop_all_queues(bp->dev);
1111b83f1527SRafal Ozieblo
1112b83f1527SRafal Ozieblo /* Stop transmission now
1113b83f1527SRafal Ozieblo * (in case we have just queued new packets)
1114b83f1527SRafal Ozieblo * macb/gem must be halted to write TBQP register
1115b83f1527SRafal Ozieblo */
111672abf217SHarini Katakam if (macb_halt_tx(bp)) {
1117b83f1527SRafal Ozieblo netdev_err(bp->dev, "BUG: halt tx timed out\n");
111872abf217SHarini Katakam macb_writel(bp, NCR, macb_readl(bp, NCR) & (~MACB_BIT(TE)));
111972abf217SHarini Katakam halt_timeout = true;
112072abf217SHarini Katakam }
1121b83f1527SRafal Ozieblo
1122b83f1527SRafal Ozieblo /* Treat frames in TX queue including the ones that caused the error.
1123b83f1527SRafal Ozieblo * Free transmit buffers in upper layer.
1124b83f1527SRafal Ozieblo */
1125b83f1527SRafal Ozieblo for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1126b83f1527SRafal Ozieblo u32 ctrl;
1127b83f1527SRafal Ozieblo
1128b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, tail);
1129b83f1527SRafal Ozieblo ctrl = desc->ctrl;
1130b83f1527SRafal Ozieblo tx_skb = macb_tx_skb(queue, tail);
1131b83f1527SRafal Ozieblo skb = tx_skb->skb;
1132b83f1527SRafal Ozieblo
1133b83f1527SRafal Ozieblo if (ctrl & MACB_BIT(TX_USED)) {
1134b83f1527SRafal Ozieblo /* skb is set for the last buffer of the frame */
1135b83f1527SRafal Ozieblo while (!skb) {
1136138badbcSRobert Hancock macb_tx_unmap(bp, tx_skb, 0);
1137b83f1527SRafal Ozieblo tail++;
1138b83f1527SRafal Ozieblo tx_skb = macb_tx_skb(queue, tail);
1139b83f1527SRafal Ozieblo skb = tx_skb->skb;
1140b83f1527SRafal Ozieblo }
1141b83f1527SRafal Ozieblo
1142b83f1527SRafal Ozieblo /* ctrl still refers to the first buffer descriptor
1143b83f1527SRafal Ozieblo * since it's the only one written back by the hardware
1144b83f1527SRafal Ozieblo */
1145b83f1527SRafal Ozieblo if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1146b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1147b83f1527SRafal Ozieblo macb_tx_ring_wrap(bp, tail),
1148b83f1527SRafal Ozieblo skb->data);
1149b83f1527SRafal Ozieblo bp->dev->stats.tx_packets++;
1150512286bbSRafal Ozieblo queue->stats.tx_packets++;
1151b83f1527SRafal Ozieblo bp->dev->stats.tx_bytes += skb->len;
1152512286bbSRafal Ozieblo queue->stats.tx_bytes += skb->len;
1153b83f1527SRafal Ozieblo }
1154b83f1527SRafal Ozieblo } else {
1155b83f1527SRafal Ozieblo /* "Buffers exhausted mid-frame" errors may only happen
1156b83f1527SRafal Ozieblo * if the driver is buggy, so complain loudly about
1157b83f1527SRafal Ozieblo * those. Statistics are updated by hardware.
1158b83f1527SRafal Ozieblo */
1159b83f1527SRafal Ozieblo if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1160b83f1527SRafal Ozieblo netdev_err(bp->dev,
1161b83f1527SRafal Ozieblo "BUG: TX buffers exhausted mid-frame\n");
1162b83f1527SRafal Ozieblo
1163b83f1527SRafal Ozieblo desc->ctrl = ctrl | MACB_BIT(TX_USED);
1164b83f1527SRafal Ozieblo }
1165b83f1527SRafal Ozieblo
1166138badbcSRobert Hancock macb_tx_unmap(bp, tx_skb, 0);
1167b83f1527SRafal Ozieblo }
1168b83f1527SRafal Ozieblo
1169b83f1527SRafal Ozieblo /* Set end of TX queue */
1170b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, 0);
1171b83f1527SRafal Ozieblo macb_set_addr(bp, desc, 0);
1172b83f1527SRafal Ozieblo desc->ctrl = MACB_BIT(TX_USED);
1173b83f1527SRafal Ozieblo
1174b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */
1175b83f1527SRafal Ozieblo wmb();
1176b83f1527SRafal Ozieblo
1177b83f1527SRafal Ozieblo /* Reinitialize the TX desc queue */
1178b83f1527SRafal Ozieblo queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1179b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1180b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1181b83f1527SRafal Ozieblo queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1182b83f1527SRafal Ozieblo #endif
1183b83f1527SRafal Ozieblo /* Make TX ring reflect state of hardware */
1184b83f1527SRafal Ozieblo queue->tx_head = 0;
1185b83f1527SRafal Ozieblo queue->tx_tail = 0;
1186b83f1527SRafal Ozieblo
1187b83f1527SRafal Ozieblo /* Housework before enabling TX IRQ */
1188b83f1527SRafal Ozieblo macb_writel(bp, TSR, macb_readl(bp, TSR));
1189b83f1527SRafal Ozieblo queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1190b83f1527SRafal Ozieblo
119172abf217SHarini Katakam if (halt_timeout)
119272abf217SHarini Katakam macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
119372abf217SHarini Katakam
1194b83f1527SRafal Ozieblo /* Now we are ready to start transmission again */
1195b83f1527SRafal Ozieblo netif_tx_start_all_queues(bp->dev);
1196b83f1527SRafal Ozieblo macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1197b83f1527SRafal Ozieblo
1198b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags);
1199138badbcSRobert Hancock napi_enable(&queue->napi_tx);
1200b83f1527SRafal Ozieblo }
1201b83f1527SRafal Ozieblo
ptp_one_step_sync(struct sk_buff * skb)12025cebb40bSHarini Katakam static bool ptp_one_step_sync(struct sk_buff *skb)
12035cebb40bSHarini Katakam {
12045cebb40bSHarini Katakam struct ptp_header *hdr;
12055cebb40bSHarini Katakam unsigned int ptp_class;
12065cebb40bSHarini Katakam u8 msgtype;
12075cebb40bSHarini Katakam
12085cebb40bSHarini Katakam /* No need to parse packet if PTP TS is not involved */
12095cebb40bSHarini Katakam if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
12105cebb40bSHarini Katakam goto not_oss;
12115cebb40bSHarini Katakam
12125cebb40bSHarini Katakam /* Identify and return whether PTP one step sync is being processed */
12135cebb40bSHarini Katakam ptp_class = ptp_classify_raw(skb);
12145cebb40bSHarini Katakam if (ptp_class == PTP_CLASS_NONE)
12155cebb40bSHarini Katakam goto not_oss;
12165cebb40bSHarini Katakam
12175cebb40bSHarini Katakam hdr = ptp_parse_header(skb, ptp_class);
12185cebb40bSHarini Katakam if (!hdr)
12195cebb40bSHarini Katakam goto not_oss;
12205cebb40bSHarini Katakam
12215cebb40bSHarini Katakam if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP)
12225cebb40bSHarini Katakam goto not_oss;
12235cebb40bSHarini Katakam
12245cebb40bSHarini Katakam msgtype = ptp_get_msgtype(hdr, ptp_class);
12255cebb40bSHarini Katakam if (msgtype == PTP_MSGTYPE_SYNC)
12265cebb40bSHarini Katakam return true;
12275cebb40bSHarini Katakam
12285cebb40bSHarini Katakam not_oss:
12295cebb40bSHarini Katakam return false;
12305cebb40bSHarini Katakam }
12315cebb40bSHarini Katakam
macb_tx_complete(struct macb_queue * queue,int budget)1232138badbcSRobert Hancock static int macb_tx_complete(struct macb_queue *queue, int budget)
1233b83f1527SRafal Ozieblo {
1234b83f1527SRafal Ozieblo struct macb *bp = queue->bp;
1235b83f1527SRafal Ozieblo u16 queue_index = queue - bp->queues;
1236138badbcSRobert Hancock unsigned int tail;
1237138badbcSRobert Hancock unsigned int head;
1238138badbcSRobert Hancock int packets = 0;
1239b83f1527SRafal Ozieblo
1240138badbcSRobert Hancock spin_lock(&queue->tx_ptr_lock);
1241b83f1527SRafal Ozieblo head = queue->tx_head;
1242138badbcSRobert Hancock for (tail = queue->tx_tail; tail != head && packets < budget; tail++) {
1243b83f1527SRafal Ozieblo struct macb_tx_skb *tx_skb;
1244b83f1527SRafal Ozieblo struct sk_buff *skb;
1245b83f1527SRafal Ozieblo struct macb_dma_desc *desc;
1246b83f1527SRafal Ozieblo u32 ctrl;
1247b83f1527SRafal Ozieblo
1248b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, tail);
1249b83f1527SRafal Ozieblo
1250b83f1527SRafal Ozieblo /* Make hw descriptor updates visible to CPU */
1251b83f1527SRafal Ozieblo rmb();
1252b83f1527SRafal Ozieblo
1253b83f1527SRafal Ozieblo ctrl = desc->ctrl;
1254b83f1527SRafal Ozieblo
1255b83f1527SRafal Ozieblo /* TX_USED bit is only set by hardware on the very first buffer
1256b83f1527SRafal Ozieblo * descriptor of the transmitted frame.
1257b83f1527SRafal Ozieblo */
1258b83f1527SRafal Ozieblo if (!(ctrl & MACB_BIT(TX_USED)))
1259b83f1527SRafal Ozieblo break;
1260b83f1527SRafal Ozieblo
1261b83f1527SRafal Ozieblo /* Process all buffers of the current transmitted frame */
1262b83f1527SRafal Ozieblo for (;; tail++) {
1263b83f1527SRafal Ozieblo tx_skb = macb_tx_skb(queue, tail);
1264b83f1527SRafal Ozieblo skb = tx_skb->skb;
1265b83f1527SRafal Ozieblo
1266b83f1527SRafal Ozieblo /* First, update TX stats if needed */
1267b83f1527SRafal Ozieblo if (skb) {
12685cebb40bSHarini Katakam if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
12698e7610e6SRobert Hancock !ptp_one_step_sync(skb))
12708e7610e6SRobert Hancock gem_ptp_do_txstamp(bp, skb, desc);
12718e7610e6SRobert Hancock
1272b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1273b83f1527SRafal Ozieblo macb_tx_ring_wrap(bp, tail),
1274b83f1527SRafal Ozieblo skb->data);
1275b83f1527SRafal Ozieblo bp->dev->stats.tx_packets++;
1276512286bbSRafal Ozieblo queue->stats.tx_packets++;
1277b83f1527SRafal Ozieblo bp->dev->stats.tx_bytes += skb->len;
1278512286bbSRafal Ozieblo queue->stats.tx_bytes += skb->len;
1279138badbcSRobert Hancock packets++;
1280b83f1527SRafal Ozieblo }
1281b83f1527SRafal Ozieblo
1282b83f1527SRafal Ozieblo /* Now we can safely release resources */
1283138badbcSRobert Hancock macb_tx_unmap(bp, tx_skb, budget);
1284b83f1527SRafal Ozieblo
1285b83f1527SRafal Ozieblo /* skb is set only for the last buffer of the frame.
1286b83f1527SRafal Ozieblo * WARNING: at this point skb has been freed by
1287b83f1527SRafal Ozieblo * macb_tx_unmap().
1288b83f1527SRafal Ozieblo */
1289b83f1527SRafal Ozieblo if (skb)
1290b83f1527SRafal Ozieblo break;
1291b83f1527SRafal Ozieblo }
1292b83f1527SRafal Ozieblo }
1293b83f1527SRafal Ozieblo
1294b83f1527SRafal Ozieblo queue->tx_tail = tail;
1295b83f1527SRafal Ozieblo if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1296b83f1527SRafal Ozieblo CIRC_CNT(queue->tx_head, queue->tx_tail,
1297b83f1527SRafal Ozieblo bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1298b83f1527SRafal Ozieblo netif_wake_subqueue(bp->dev, queue_index);
1299138badbcSRobert Hancock spin_unlock(&queue->tx_ptr_lock);
1300138badbcSRobert Hancock
1301138badbcSRobert Hancock return packets;
1302b83f1527SRafal Ozieblo }
1303b83f1527SRafal Ozieblo
gem_rx_refill(struct macb_queue * queue)1304ae1f2a56SRafal Ozieblo static void gem_rx_refill(struct macb_queue *queue)
1305b83f1527SRafal Ozieblo {
1306b83f1527SRafal Ozieblo unsigned int entry;
1307b83f1527SRafal Ozieblo struct sk_buff *skb;
1308b83f1527SRafal Ozieblo dma_addr_t paddr;
1309ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp;
1310b83f1527SRafal Ozieblo struct macb_dma_desc *desc;
1311b83f1527SRafal Ozieblo
1312ae1f2a56SRafal Ozieblo while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1313b83f1527SRafal Ozieblo bp->rx_ring_size) > 0) {
1314ae1f2a56SRafal Ozieblo entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1315b83f1527SRafal Ozieblo
1316b83f1527SRafal Ozieblo /* Make hw descriptor updates visible to CPU */
1317b83f1527SRafal Ozieblo rmb();
1318b83f1527SRafal Ozieblo
1319ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, entry);
1320b83f1527SRafal Ozieblo
1321ae1f2a56SRafal Ozieblo if (!queue->rx_skbuff[entry]) {
1322b83f1527SRafal Ozieblo /* allocate sk_buff for this free entry in ring */
1323b83f1527SRafal Ozieblo skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1324b83f1527SRafal Ozieblo if (unlikely(!skb)) {
1325b83f1527SRafal Ozieblo netdev_err(bp->dev,
1326b83f1527SRafal Ozieblo "Unable to allocate sk_buff\n");
1327b83f1527SRafal Ozieblo break;
1328b83f1527SRafal Ozieblo }
1329b83f1527SRafal Ozieblo
1330b83f1527SRafal Ozieblo /* now fill corresponding descriptor entry */
1331b83f1527SRafal Ozieblo paddr = dma_map_single(&bp->pdev->dev, skb->data,
1332b83f1527SRafal Ozieblo bp->rx_buffer_size,
1333b83f1527SRafal Ozieblo DMA_FROM_DEVICE);
1334b83f1527SRafal Ozieblo if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1335b83f1527SRafal Ozieblo dev_kfree_skb(skb);
1336b83f1527SRafal Ozieblo break;
1337b83f1527SRafal Ozieblo }
1338b83f1527SRafal Ozieblo
1339ae1f2a56SRafal Ozieblo queue->rx_skbuff[entry] = skb;
1340b83f1527SRafal Ozieblo
1341b83f1527SRafal Ozieblo if (entry == bp->rx_ring_size - 1)
1342b83f1527SRafal Ozieblo paddr |= MACB_BIT(RX_WRAP);
1343b83f1527SRafal Ozieblo desc->ctrl = 0;
13448159ecabSAnssi Hannula /* Setting addr clears RX_USED and allows reception,
13458159ecabSAnssi Hannula * make sure ctrl is cleared first to avoid a race.
13468159ecabSAnssi Hannula */
13478159ecabSAnssi Hannula dma_wmb();
13488159ecabSAnssi Hannula macb_set_addr(bp, desc, paddr);
1349b83f1527SRafal Ozieblo
1350b83f1527SRafal Ozieblo /* properly align Ethernet header */
1351b83f1527SRafal Ozieblo skb_reserve(skb, NET_IP_ALIGN);
1352b83f1527SRafal Ozieblo } else {
1353b83f1527SRafal Ozieblo desc->ctrl = 0;
13548159ecabSAnssi Hannula dma_wmb();
13558159ecabSAnssi Hannula desc->addr &= ~MACB_BIT(RX_USED);
1356b83f1527SRafal Ozieblo }
13579500acc6SHarini Katakam queue->rx_prepared_head++;
1358b83f1527SRafal Ozieblo }
1359b83f1527SRafal Ozieblo
1360b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */
1361b83f1527SRafal Ozieblo wmb();
1362b83f1527SRafal Ozieblo
1363ae1f2a56SRafal Ozieblo netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1364ae1f2a56SRafal Ozieblo queue, queue->rx_prepared_head, queue->rx_tail);
1365b83f1527SRafal Ozieblo }
1366b83f1527SRafal Ozieblo
1367b83f1527SRafal Ozieblo /* Mark DMA descriptors from begin up to and not including end as unused */
discard_partial_frame(struct macb_queue * queue,unsigned int begin,unsigned int end)1368ae1f2a56SRafal Ozieblo static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1369b83f1527SRafal Ozieblo unsigned int end)
1370b83f1527SRafal Ozieblo {
1371b83f1527SRafal Ozieblo unsigned int frag;
1372b83f1527SRafal Ozieblo
1373b83f1527SRafal Ozieblo for (frag = begin; frag != end; frag++) {
1374ae1f2a56SRafal Ozieblo struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1375b83f1527SRafal Ozieblo
1376b83f1527SRafal Ozieblo desc->addr &= ~MACB_BIT(RX_USED);
1377b83f1527SRafal Ozieblo }
1378b83f1527SRafal Ozieblo
1379b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */
1380b83f1527SRafal Ozieblo wmb();
1381b83f1527SRafal Ozieblo
1382b83f1527SRafal Ozieblo /* When this happens, the hardware stats registers for
1383b83f1527SRafal Ozieblo * whatever caused this is updated, so we don't have to record
1384b83f1527SRafal Ozieblo * anything.
1385b83f1527SRafal Ozieblo */
1386b83f1527SRafal Ozieblo }
1387b83f1527SRafal Ozieblo
gem_rx(struct macb_queue * queue,struct napi_struct * napi,int budget)138897236cdaSAntoine Tenart static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
138997236cdaSAntoine Tenart int budget)
1390b83f1527SRafal Ozieblo {
1391ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp;
1392b83f1527SRafal Ozieblo unsigned int len;
1393b83f1527SRafal Ozieblo unsigned int entry;
1394b83f1527SRafal Ozieblo struct sk_buff *skb;
1395b83f1527SRafal Ozieblo struct macb_dma_desc *desc;
1396b83f1527SRafal Ozieblo int count = 0;
1397b83f1527SRafal Ozieblo
1398b83f1527SRafal Ozieblo while (count < budget) {
1399b83f1527SRafal Ozieblo u32 ctrl;
1400b83f1527SRafal Ozieblo dma_addr_t addr;
1401b83f1527SRafal Ozieblo bool rxused;
1402b83f1527SRafal Ozieblo
1403ae1f2a56SRafal Ozieblo entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1404ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, entry);
1405b83f1527SRafal Ozieblo
1406b83f1527SRafal Ozieblo /* Make hw descriptor updates visible to CPU */
1407b83f1527SRafal Ozieblo rmb();
1408b83f1527SRafal Ozieblo
1409b83f1527SRafal Ozieblo rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1410b83f1527SRafal Ozieblo addr = macb_get_addr(bp, desc);
1411b83f1527SRafal Ozieblo
1412b83f1527SRafal Ozieblo if (!rxused)
1413b83f1527SRafal Ozieblo break;
1414b83f1527SRafal Ozieblo
14156e0af298SAnssi Hannula /* Ensure ctrl is at least as up-to-date as rxused */
14166e0af298SAnssi Hannula dma_rmb();
14176e0af298SAnssi Hannula
14186e0af298SAnssi Hannula ctrl = desc->ctrl;
14196e0af298SAnssi Hannula
1420ae1f2a56SRafal Ozieblo queue->rx_tail++;
1421b83f1527SRafal Ozieblo count++;
1422b83f1527SRafal Ozieblo
1423b83f1527SRafal Ozieblo if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1424b83f1527SRafal Ozieblo netdev_err(bp->dev,
1425b83f1527SRafal Ozieblo "not whole frame pointed by descriptor\n");
1426b83f1527SRafal Ozieblo bp->dev->stats.rx_dropped++;
1427512286bbSRafal Ozieblo queue->stats.rx_dropped++;
1428b83f1527SRafal Ozieblo break;
1429b83f1527SRafal Ozieblo }
1430ae1f2a56SRafal Ozieblo skb = queue->rx_skbuff[entry];
1431b83f1527SRafal Ozieblo if (unlikely(!skb)) {
1432b83f1527SRafal Ozieblo netdev_err(bp->dev,
1433b83f1527SRafal Ozieblo "inconsistent Rx descriptor chain\n");
1434b83f1527SRafal Ozieblo bp->dev->stats.rx_dropped++;
1435512286bbSRafal Ozieblo queue->stats.rx_dropped++;
1436b83f1527SRafal Ozieblo break;
1437b83f1527SRafal Ozieblo }
1438b83f1527SRafal Ozieblo /* now everything is ready for receiving packet */
1439ae1f2a56SRafal Ozieblo queue->rx_skbuff[entry] = NULL;
1440b83f1527SRafal Ozieblo len = ctrl & bp->rx_frm_len_mask;
1441b83f1527SRafal Ozieblo
1442b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1443b83f1527SRafal Ozieblo
1444b83f1527SRafal Ozieblo skb_put(skb, len);
1445b83f1527SRafal Ozieblo dma_unmap_single(&bp->pdev->dev, addr,
1446b83f1527SRafal Ozieblo bp->rx_buffer_size, DMA_FROM_DEVICE);
1447b83f1527SRafal Ozieblo
1448b83f1527SRafal Ozieblo skb->protocol = eth_type_trans(skb, bp->dev);
1449b83f1527SRafal Ozieblo skb_checksum_none_assert(skb);
1450b83f1527SRafal Ozieblo if (bp->dev->features & NETIF_F_RXCSUM &&
1451b83f1527SRafal Ozieblo !(bp->dev->flags & IFF_PROMISC) &&
1452b83f1527SRafal Ozieblo GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1453b83f1527SRafal Ozieblo skb->ip_summed = CHECKSUM_UNNECESSARY;
1454b83f1527SRafal Ozieblo
1455b83f1527SRafal Ozieblo bp->dev->stats.rx_packets++;
1456512286bbSRafal Ozieblo queue->stats.rx_packets++;
1457b83f1527SRafal Ozieblo bp->dev->stats.rx_bytes += skb->len;
1458512286bbSRafal Ozieblo queue->stats.rx_bytes += skb->len;
1459b83f1527SRafal Ozieblo
1460ab91f0a9SRafal Ozieblo gem_ptp_do_rxstamp(bp, skb, desc);
1461ab91f0a9SRafal Ozieblo
1462b83f1527SRafal Ozieblo #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1463b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1464b83f1527SRafal Ozieblo skb->len, skb->csum);
1465b83f1527SRafal Ozieblo print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1466b83f1527SRafal Ozieblo skb_mac_header(skb), 16, true);
1467b83f1527SRafal Ozieblo print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1468b83f1527SRafal Ozieblo skb->data, 32, true);
1469b83f1527SRafal Ozieblo #endif
1470b83f1527SRafal Ozieblo
147197236cdaSAntoine Tenart napi_gro_receive(napi, skb);
1472b83f1527SRafal Ozieblo }
1473b83f1527SRafal Ozieblo
1474ae1f2a56SRafal Ozieblo gem_rx_refill(queue);
1475b83f1527SRafal Ozieblo
1476b83f1527SRafal Ozieblo return count;
1477b83f1527SRafal Ozieblo }
1478b83f1527SRafal Ozieblo
macb_rx_frame(struct macb_queue * queue,struct napi_struct * napi,unsigned int first_frag,unsigned int last_frag)147997236cdaSAntoine Tenart static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
148097236cdaSAntoine Tenart unsigned int first_frag, unsigned int last_frag)
1481b83f1527SRafal Ozieblo {
1482b83f1527SRafal Ozieblo unsigned int len;
1483b83f1527SRafal Ozieblo unsigned int frag;
1484b83f1527SRafal Ozieblo unsigned int offset;
1485b83f1527SRafal Ozieblo struct sk_buff *skb;
1486b83f1527SRafal Ozieblo struct macb_dma_desc *desc;
1487ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp;
1488b83f1527SRafal Ozieblo
1489ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, last_frag);
1490b83f1527SRafal Ozieblo len = desc->ctrl & bp->rx_frm_len_mask;
1491b83f1527SRafal Ozieblo
1492b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1493b83f1527SRafal Ozieblo macb_rx_ring_wrap(bp, first_frag),
1494b83f1527SRafal Ozieblo macb_rx_ring_wrap(bp, last_frag), len);
1495b83f1527SRafal Ozieblo
1496b83f1527SRafal Ozieblo /* The ethernet header starts NET_IP_ALIGN bytes into the
1497b83f1527SRafal Ozieblo * first buffer. Since the header is 14 bytes, this makes the
1498b83f1527SRafal Ozieblo * payload word-aligned.
1499b83f1527SRafal Ozieblo *
1500b83f1527SRafal Ozieblo * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1501b83f1527SRafal Ozieblo * the two padding bytes into the skb so that we avoid hitting
1502b83f1527SRafal Ozieblo * the slowpath in memcpy(), and pull them off afterwards.
1503b83f1527SRafal Ozieblo */
1504b83f1527SRafal Ozieblo skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1505b83f1527SRafal Ozieblo if (!skb) {
1506b83f1527SRafal Ozieblo bp->dev->stats.rx_dropped++;
1507b83f1527SRafal Ozieblo for (frag = first_frag; ; frag++) {
1508ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, frag);
1509b83f1527SRafal Ozieblo desc->addr &= ~MACB_BIT(RX_USED);
1510b83f1527SRafal Ozieblo if (frag == last_frag)
1511b83f1527SRafal Ozieblo break;
1512b83f1527SRafal Ozieblo }
1513b83f1527SRafal Ozieblo
1514b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */
1515b83f1527SRafal Ozieblo wmb();
1516b83f1527SRafal Ozieblo
1517b83f1527SRafal Ozieblo return 1;
1518b83f1527SRafal Ozieblo }
1519b83f1527SRafal Ozieblo
1520b83f1527SRafal Ozieblo offset = 0;
1521b83f1527SRafal Ozieblo len += NET_IP_ALIGN;
1522b83f1527SRafal Ozieblo skb_checksum_none_assert(skb);
1523b83f1527SRafal Ozieblo skb_put(skb, len);
1524b83f1527SRafal Ozieblo
1525b83f1527SRafal Ozieblo for (frag = first_frag; ; frag++) {
1526b83f1527SRafal Ozieblo unsigned int frag_len = bp->rx_buffer_size;
1527b83f1527SRafal Ozieblo
1528b83f1527SRafal Ozieblo if (offset + frag_len > len) {
1529b83f1527SRafal Ozieblo if (unlikely(frag != last_frag)) {
1530b83f1527SRafal Ozieblo dev_kfree_skb_any(skb);
1531b83f1527SRafal Ozieblo return -1;
1532b83f1527SRafal Ozieblo }
1533b83f1527SRafal Ozieblo frag_len = len - offset;
1534b83f1527SRafal Ozieblo }
1535b83f1527SRafal Ozieblo skb_copy_to_linear_data_offset(skb, offset,
1536ae1f2a56SRafal Ozieblo macb_rx_buffer(queue, frag),
1537b83f1527SRafal Ozieblo frag_len);
1538b83f1527SRafal Ozieblo offset += bp->rx_buffer_size;
1539ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, frag);
1540b83f1527SRafal Ozieblo desc->addr &= ~MACB_BIT(RX_USED);
1541b83f1527SRafal Ozieblo
1542b83f1527SRafal Ozieblo if (frag == last_frag)
1543b83f1527SRafal Ozieblo break;
1544b83f1527SRafal Ozieblo }
1545b83f1527SRafal Ozieblo
1546b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */
1547b83f1527SRafal Ozieblo wmb();
1548b83f1527SRafal Ozieblo
1549b83f1527SRafal Ozieblo __skb_pull(skb, NET_IP_ALIGN);
1550b83f1527SRafal Ozieblo skb->protocol = eth_type_trans(skb, bp->dev);
1551b83f1527SRafal Ozieblo
1552b83f1527SRafal Ozieblo bp->dev->stats.rx_packets++;
1553b83f1527SRafal Ozieblo bp->dev->stats.rx_bytes += skb->len;
1554b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1555b83f1527SRafal Ozieblo skb->len, skb->csum);
155697236cdaSAntoine Tenart napi_gro_receive(napi, skb);
1557b83f1527SRafal Ozieblo
1558b83f1527SRafal Ozieblo return 0;
1559b83f1527SRafal Ozieblo }
1560b83f1527SRafal Ozieblo
macb_init_rx_ring(struct macb_queue * queue)1561ae1f2a56SRafal Ozieblo static inline void macb_init_rx_ring(struct macb_queue *queue)
1562b83f1527SRafal Ozieblo {
1563ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp;
1564b83f1527SRafal Ozieblo dma_addr_t addr;
1565b83f1527SRafal Ozieblo struct macb_dma_desc *desc = NULL;
1566b83f1527SRafal Ozieblo int i;
1567b83f1527SRafal Ozieblo
1568ae1f2a56SRafal Ozieblo addr = queue->rx_buffers_dma;
1569b83f1527SRafal Ozieblo for (i = 0; i < bp->rx_ring_size; i++) {
1570ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, i);
1571b83f1527SRafal Ozieblo macb_set_addr(bp, desc, addr);
1572b83f1527SRafal Ozieblo desc->ctrl = 0;
1573b83f1527SRafal Ozieblo addr += bp->rx_buffer_size;
1574b83f1527SRafal Ozieblo }
1575b83f1527SRafal Ozieblo desc->addr |= MACB_BIT(RX_WRAP);
1576ae1f2a56SRafal Ozieblo queue->rx_tail = 0;
1577b83f1527SRafal Ozieblo }
1578b83f1527SRafal Ozieblo
macb_rx(struct macb_queue * queue,struct napi_struct * napi,int budget)157997236cdaSAntoine Tenart static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
158097236cdaSAntoine Tenart int budget)
1581b83f1527SRafal Ozieblo {
1582ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp;
1583b83f1527SRafal Ozieblo bool reset_rx_queue = false;
1584b83f1527SRafal Ozieblo int received = 0;
1585b83f1527SRafal Ozieblo unsigned int tail;
1586b83f1527SRafal Ozieblo int first_frag = -1;
1587b83f1527SRafal Ozieblo
1588ae1f2a56SRafal Ozieblo for (tail = queue->rx_tail; budget > 0; tail++) {
1589ae1f2a56SRafal Ozieblo struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1590b83f1527SRafal Ozieblo u32 ctrl;
1591b83f1527SRafal Ozieblo
1592b83f1527SRafal Ozieblo /* Make hw descriptor updates visible to CPU */
1593b83f1527SRafal Ozieblo rmb();
1594b83f1527SRafal Ozieblo
1595b83f1527SRafal Ozieblo if (!(desc->addr & MACB_BIT(RX_USED)))
1596b83f1527SRafal Ozieblo break;
1597b83f1527SRafal Ozieblo
15986e0af298SAnssi Hannula /* Ensure ctrl is at least as up-to-date as addr */
15996e0af298SAnssi Hannula dma_rmb();
16006e0af298SAnssi Hannula
16016e0af298SAnssi Hannula ctrl = desc->ctrl;
16026e0af298SAnssi Hannula
1603b83f1527SRafal Ozieblo if (ctrl & MACB_BIT(RX_SOF)) {
1604b83f1527SRafal Ozieblo if (first_frag != -1)
1605ae1f2a56SRafal Ozieblo discard_partial_frame(queue, first_frag, tail);
1606b83f1527SRafal Ozieblo first_frag = tail;
1607b83f1527SRafal Ozieblo }
1608b83f1527SRafal Ozieblo
1609b83f1527SRafal Ozieblo if (ctrl & MACB_BIT(RX_EOF)) {
1610b83f1527SRafal Ozieblo int dropped;
1611b83f1527SRafal Ozieblo
1612b83f1527SRafal Ozieblo if (unlikely(first_frag == -1)) {
1613b83f1527SRafal Ozieblo reset_rx_queue = true;
1614b83f1527SRafal Ozieblo continue;
1615b83f1527SRafal Ozieblo }
1616b83f1527SRafal Ozieblo
161797236cdaSAntoine Tenart dropped = macb_rx_frame(queue, napi, first_frag, tail);
1618b83f1527SRafal Ozieblo first_frag = -1;
1619b83f1527SRafal Ozieblo if (unlikely(dropped < 0)) {
1620b83f1527SRafal Ozieblo reset_rx_queue = true;
1621b83f1527SRafal Ozieblo continue;
1622b83f1527SRafal Ozieblo }
1623b83f1527SRafal Ozieblo if (!dropped) {
1624b83f1527SRafal Ozieblo received++;
1625b83f1527SRafal Ozieblo budget--;
1626b83f1527SRafal Ozieblo }
1627b83f1527SRafal Ozieblo }
1628b83f1527SRafal Ozieblo }
1629b83f1527SRafal Ozieblo
1630b83f1527SRafal Ozieblo if (unlikely(reset_rx_queue)) {
1631b83f1527SRafal Ozieblo unsigned long flags;
1632b83f1527SRafal Ozieblo u32 ctrl;
1633b83f1527SRafal Ozieblo
1634b83f1527SRafal Ozieblo netdev_err(bp->dev, "RX queue corruption: reset it\n");
1635b83f1527SRafal Ozieblo
1636b83f1527SRafal Ozieblo spin_lock_irqsave(&bp->lock, flags);
1637b83f1527SRafal Ozieblo
1638b83f1527SRafal Ozieblo ctrl = macb_readl(bp, NCR);
1639b83f1527SRafal Ozieblo macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1640b83f1527SRafal Ozieblo
1641ae1f2a56SRafal Ozieblo macb_init_rx_ring(queue);
1642ae1f2a56SRafal Ozieblo queue_writel(queue, RBQP, queue->rx_ring_dma);
1643b83f1527SRafal Ozieblo
1644b83f1527SRafal Ozieblo macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1645b83f1527SRafal Ozieblo
1646b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags);
1647b83f1527SRafal Ozieblo return received;
1648b83f1527SRafal Ozieblo }
1649b83f1527SRafal Ozieblo
1650b83f1527SRafal Ozieblo if (first_frag != -1)
1651ae1f2a56SRafal Ozieblo queue->rx_tail = first_frag;
1652b83f1527SRafal Ozieblo else
1653ae1f2a56SRafal Ozieblo queue->rx_tail = tail;
1654b83f1527SRafal Ozieblo
1655b83f1527SRafal Ozieblo return received;
1656b83f1527SRafal Ozieblo }
1657b83f1527SRafal Ozieblo
macb_rx_pending(struct macb_queue * queue)16581900e30dSRobert Hancock static bool macb_rx_pending(struct macb_queue *queue)
16591900e30dSRobert Hancock {
16601900e30dSRobert Hancock struct macb *bp = queue->bp;
16611900e30dSRobert Hancock unsigned int entry;
16621900e30dSRobert Hancock struct macb_dma_desc *desc;
16631900e30dSRobert Hancock
16641900e30dSRobert Hancock entry = macb_rx_ring_wrap(bp, queue->rx_tail);
16651900e30dSRobert Hancock desc = macb_rx_desc(queue, entry);
16661900e30dSRobert Hancock
16671900e30dSRobert Hancock /* Make hw descriptor updates visible to CPU */
16681900e30dSRobert Hancock rmb();
16691900e30dSRobert Hancock
16701900e30dSRobert Hancock return (desc->addr & MACB_BIT(RX_USED)) != 0;
16711900e30dSRobert Hancock }
16721900e30dSRobert Hancock
macb_rx_poll(struct napi_struct * napi,int budget)1673138badbcSRobert Hancock static int macb_rx_poll(struct napi_struct *napi, int budget)
1674b83f1527SRafal Ozieblo {
1675138badbcSRobert Hancock struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx);
1676ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp;
1677b83f1527SRafal Ozieblo int work_done;
1678b83f1527SRafal Ozieblo
167997236cdaSAntoine Tenart work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1680b83f1527SRafal Ozieblo
1681138badbcSRobert Hancock netdev_vdbg(bp->dev, "RX poll: queue = %u, work_done = %d, budget = %d\n",
16821900e30dSRobert Hancock (unsigned int)(queue - bp->queues), work_done, budget);
16831900e30dSRobert Hancock
16841900e30dSRobert Hancock if (work_done < budget && napi_complete_done(napi, work_done)) {
1685e501070eSHarini Katakam queue_writel(queue, IER, bp->rx_intr_mask);
16860bf476fcSRobert Hancock
16871900e30dSRobert Hancock /* Packet completions only seem to propagate to raise
16881900e30dSRobert Hancock * interrupts when interrupts are enabled at the time, so if
16891900e30dSRobert Hancock * packets were received while interrupts were disabled,
16901900e30dSRobert Hancock * they will not cause another interrupt to be generated when
16911900e30dSRobert Hancock * interrupts are re-enabled.
16921900e30dSRobert Hancock * Check for this case here to avoid losing a wakeup. This can
16931900e30dSRobert Hancock * potentially race with the interrupt handler doing the same
16941900e30dSRobert Hancock * actions if an interrupt is raised just after enabling them,
16950bf476fcSRobert Hancock * but this should be harmless.
16960bf476fcSRobert Hancock */
16971900e30dSRobert Hancock if (macb_rx_pending(queue)) {
16980bf476fcSRobert Hancock queue_writel(queue, IDR, bp->rx_intr_mask);
16990bf476fcSRobert Hancock if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
17000bf476fcSRobert Hancock queue_writel(queue, ISR, MACB_BIT(RCOMP));
17011900e30dSRobert Hancock netdev_vdbg(bp->dev, "poll: packets pending, reschedule\n");
17020bf476fcSRobert Hancock napi_schedule(napi);
17030bf476fcSRobert Hancock }
1704b83f1527SRafal Ozieblo }
1705b83f1527SRafal Ozieblo
1706b83f1527SRafal Ozieblo /* TODO: Handle errors */
1707b83f1527SRafal Ozieblo
1708b83f1527SRafal Ozieblo return work_done;
1709b83f1527SRafal Ozieblo }
1710b83f1527SRafal Ozieblo
macb_tx_restart(struct macb_queue * queue)1711138badbcSRobert Hancock static void macb_tx_restart(struct macb_queue *queue)
1712138badbcSRobert Hancock {
1713138badbcSRobert Hancock struct macb *bp = queue->bp;
1714138badbcSRobert Hancock unsigned int head_idx, tbqp;
1715138badbcSRobert Hancock
1716138badbcSRobert Hancock spin_lock(&queue->tx_ptr_lock);
1717138badbcSRobert Hancock
1718138badbcSRobert Hancock if (queue->tx_head == queue->tx_tail)
1719138badbcSRobert Hancock goto out_tx_ptr_unlock;
1720138badbcSRobert Hancock
1721138badbcSRobert Hancock tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1722138badbcSRobert Hancock tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1723138badbcSRobert Hancock head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head));
1724138badbcSRobert Hancock
1725138badbcSRobert Hancock if (tbqp == head_idx)
1726138badbcSRobert Hancock goto out_tx_ptr_unlock;
1727138badbcSRobert Hancock
1728138badbcSRobert Hancock spin_lock_irq(&bp->lock);
1729138badbcSRobert Hancock macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1730138badbcSRobert Hancock spin_unlock_irq(&bp->lock);
1731138badbcSRobert Hancock
1732138badbcSRobert Hancock out_tx_ptr_unlock:
1733138badbcSRobert Hancock spin_unlock(&queue->tx_ptr_lock);
1734138badbcSRobert Hancock }
1735138badbcSRobert Hancock
macb_tx_complete_pending(struct macb_queue * queue)1736138badbcSRobert Hancock static bool macb_tx_complete_pending(struct macb_queue *queue)
1737138badbcSRobert Hancock {
1738138badbcSRobert Hancock bool retval = false;
1739138badbcSRobert Hancock
1740138badbcSRobert Hancock spin_lock(&queue->tx_ptr_lock);
1741138badbcSRobert Hancock if (queue->tx_head != queue->tx_tail) {
1742138badbcSRobert Hancock /* Make hw descriptor updates visible to CPU */
1743138badbcSRobert Hancock rmb();
1744138badbcSRobert Hancock
1745138badbcSRobert Hancock if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED))
1746138badbcSRobert Hancock retval = true;
1747138badbcSRobert Hancock }
1748138badbcSRobert Hancock spin_unlock(&queue->tx_ptr_lock);
1749138badbcSRobert Hancock return retval;
1750138badbcSRobert Hancock }
1751138badbcSRobert Hancock
macb_tx_poll(struct napi_struct * napi,int budget)1752138badbcSRobert Hancock static int macb_tx_poll(struct napi_struct *napi, int budget)
1753138badbcSRobert Hancock {
1754138badbcSRobert Hancock struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx);
1755138badbcSRobert Hancock struct macb *bp = queue->bp;
1756138badbcSRobert Hancock int work_done;
1757138badbcSRobert Hancock
1758138badbcSRobert Hancock work_done = macb_tx_complete(queue, budget);
1759138badbcSRobert Hancock
1760138badbcSRobert Hancock rmb(); // ensure txubr_pending is up to date
1761138badbcSRobert Hancock if (queue->txubr_pending) {
1762138badbcSRobert Hancock queue->txubr_pending = false;
1763138badbcSRobert Hancock netdev_vdbg(bp->dev, "poll: tx restart\n");
1764138badbcSRobert Hancock macb_tx_restart(queue);
1765138badbcSRobert Hancock }
1766138badbcSRobert Hancock
1767138badbcSRobert Hancock netdev_vdbg(bp->dev, "TX poll: queue = %u, work_done = %d, budget = %d\n",
1768138badbcSRobert Hancock (unsigned int)(queue - bp->queues), work_done, budget);
1769138badbcSRobert Hancock
1770138badbcSRobert Hancock if (work_done < budget && napi_complete_done(napi, work_done)) {
1771138badbcSRobert Hancock queue_writel(queue, IER, MACB_BIT(TCOMP));
1772138badbcSRobert Hancock
1773138badbcSRobert Hancock /* Packet completions only seem to propagate to raise
1774138badbcSRobert Hancock * interrupts when interrupts are enabled at the time, so if
1775138badbcSRobert Hancock * packets were sent while interrupts were disabled,
1776138badbcSRobert Hancock * they will not cause another interrupt to be generated when
1777138badbcSRobert Hancock * interrupts are re-enabled.
1778138badbcSRobert Hancock * Check for this case here to avoid losing a wakeup. This can
1779138badbcSRobert Hancock * potentially race with the interrupt handler doing the same
1780138badbcSRobert Hancock * actions if an interrupt is raised just after enabling them,
1781138badbcSRobert Hancock * but this should be harmless.
1782138badbcSRobert Hancock */
1783138badbcSRobert Hancock if (macb_tx_complete_pending(queue)) {
1784138badbcSRobert Hancock queue_writel(queue, IDR, MACB_BIT(TCOMP));
1785138badbcSRobert Hancock if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1786138badbcSRobert Hancock queue_writel(queue, ISR, MACB_BIT(TCOMP));
1787138badbcSRobert Hancock netdev_vdbg(bp->dev, "TX poll: packets pending, reschedule\n");
1788138badbcSRobert Hancock napi_schedule(napi);
1789138badbcSRobert Hancock }
1790138badbcSRobert Hancock }
1791138badbcSRobert Hancock
1792138badbcSRobert Hancock return work_done;
1793138badbcSRobert Hancock }
1794138badbcSRobert Hancock
macb_hresp_error_task(struct tasklet_struct * t)1795e7412b83SAllen Pais static void macb_hresp_error_task(struct tasklet_struct *t)
1796032dc41bSHarini Katakam {
1797e7412b83SAllen Pais struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1798032dc41bSHarini Katakam struct net_device *dev = bp->dev;
1799580d395cSClaudiu Beznea struct macb_queue *queue;
1800032dc41bSHarini Katakam unsigned int q;
1801032dc41bSHarini Katakam u32 ctrl;
1802032dc41bSHarini Katakam
1803032dc41bSHarini Katakam for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1804e501070eSHarini Katakam queue_writel(queue, IDR, bp->rx_intr_mask |
1805032dc41bSHarini Katakam MACB_TX_INT_FLAGS |
1806032dc41bSHarini Katakam MACB_BIT(HRESP));
1807032dc41bSHarini Katakam }
1808032dc41bSHarini Katakam ctrl = macb_readl(bp, NCR);
1809032dc41bSHarini Katakam ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1810032dc41bSHarini Katakam macb_writel(bp, NCR, ctrl);
1811032dc41bSHarini Katakam
1812032dc41bSHarini Katakam netif_tx_stop_all_queues(dev);
1813032dc41bSHarini Katakam netif_carrier_off(dev);
1814032dc41bSHarini Katakam
1815032dc41bSHarini Katakam bp->macbgem_ops.mog_init_rings(bp);
1816032dc41bSHarini Katakam
1817032dc41bSHarini Katakam /* Initialize TX and RX buffers */
18186e952d95SAntoine Tenart macb_init_buffers(bp);
1819032dc41bSHarini Katakam
1820032dc41bSHarini Katakam /* Enable interrupts */
18216e952d95SAntoine Tenart for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1822032dc41bSHarini Katakam queue_writel(queue, IER,
1823e501070eSHarini Katakam bp->rx_intr_mask |
1824032dc41bSHarini Katakam MACB_TX_INT_FLAGS |
1825032dc41bSHarini Katakam MACB_BIT(HRESP));
1826032dc41bSHarini Katakam
1827032dc41bSHarini Katakam ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1828032dc41bSHarini Katakam macb_writel(bp, NCR, ctrl);
1829032dc41bSHarini Katakam
1830032dc41bSHarini Katakam netif_carrier_on(dev);
1831032dc41bSHarini Katakam netif_tx_start_all_queues(dev);
1832032dc41bSHarini Katakam }
1833032dc41bSHarini Katakam
macb_wol_interrupt(int irq,void * dev_id)18349d45c8e8SNicolas Ferre static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
18359d45c8e8SNicolas Ferre {
18369d45c8e8SNicolas Ferre struct macb_queue *queue = dev_id;
18379d45c8e8SNicolas Ferre struct macb *bp = queue->bp;
18389d45c8e8SNicolas Ferre u32 status;
18399d45c8e8SNicolas Ferre
18409d45c8e8SNicolas Ferre status = queue_readl(queue, ISR);
18419d45c8e8SNicolas Ferre
18429d45c8e8SNicolas Ferre if (unlikely(!status))
18439d45c8e8SNicolas Ferre return IRQ_NONE;
18449d45c8e8SNicolas Ferre
18459d45c8e8SNicolas Ferre spin_lock(&bp->lock);
18469d45c8e8SNicolas Ferre
18479d45c8e8SNicolas Ferre if (status & MACB_BIT(WOL)) {
18489d45c8e8SNicolas Ferre queue_writel(queue, IDR, MACB_BIT(WOL));
18499d45c8e8SNicolas Ferre macb_writel(bp, WOL, 0);
18509d45c8e8SNicolas Ferre netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
18519d45c8e8SNicolas Ferre (unsigned int)(queue - bp->queues),
18529d45c8e8SNicolas Ferre (unsigned long)status);
18539d45c8e8SNicolas Ferre if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
18549d45c8e8SNicolas Ferre queue_writel(queue, ISR, MACB_BIT(WOL));
18559d45c8e8SNicolas Ferre pm_wakeup_event(&bp->pdev->dev, 0);
18569d45c8e8SNicolas Ferre }
18579d45c8e8SNicolas Ferre
18589d45c8e8SNicolas Ferre spin_unlock(&bp->lock);
18599d45c8e8SNicolas Ferre
18609d45c8e8SNicolas Ferre return IRQ_HANDLED;
18619d45c8e8SNicolas Ferre }
18629d45c8e8SNicolas Ferre
gem_wol_interrupt(int irq,void * dev_id)1863558e35ccSNicolas Ferre static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1864558e35ccSNicolas Ferre {
1865558e35ccSNicolas Ferre struct macb_queue *queue = dev_id;
1866558e35ccSNicolas Ferre struct macb *bp = queue->bp;
1867558e35ccSNicolas Ferre u32 status;
1868558e35ccSNicolas Ferre
1869558e35ccSNicolas Ferre status = queue_readl(queue, ISR);
1870558e35ccSNicolas Ferre
1871558e35ccSNicolas Ferre if (unlikely(!status))
1872558e35ccSNicolas Ferre return IRQ_NONE;
1873558e35ccSNicolas Ferre
1874558e35ccSNicolas Ferre spin_lock(&bp->lock);
1875558e35ccSNicolas Ferre
1876558e35ccSNicolas Ferre if (status & GEM_BIT(WOL)) {
1877558e35ccSNicolas Ferre queue_writel(queue, IDR, GEM_BIT(WOL));
1878558e35ccSNicolas Ferre gem_writel(bp, WOL, 0);
1879558e35ccSNicolas Ferre netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1880558e35ccSNicolas Ferre (unsigned int)(queue - bp->queues),
1881558e35ccSNicolas Ferre (unsigned long)status);
1882558e35ccSNicolas Ferre if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1883558e35ccSNicolas Ferre queue_writel(queue, ISR, GEM_BIT(WOL));
1884558e35ccSNicolas Ferre pm_wakeup_event(&bp->pdev->dev, 0);
1885558e35ccSNicolas Ferre }
1886558e35ccSNicolas Ferre
1887558e35ccSNicolas Ferre spin_unlock(&bp->lock);
1888558e35ccSNicolas Ferre
1889558e35ccSNicolas Ferre return IRQ_HANDLED;
1890558e35ccSNicolas Ferre }
1891558e35ccSNicolas Ferre
macb_interrupt(int irq,void * dev_id)1892b83f1527SRafal Ozieblo static irqreturn_t macb_interrupt(int irq, void *dev_id)
1893b83f1527SRafal Ozieblo {
1894b83f1527SRafal Ozieblo struct macb_queue *queue = dev_id;
1895b83f1527SRafal Ozieblo struct macb *bp = queue->bp;
1896b83f1527SRafal Ozieblo struct net_device *dev = bp->dev;
1897b83f1527SRafal Ozieblo u32 status, ctrl;
1898b83f1527SRafal Ozieblo
1899b83f1527SRafal Ozieblo status = queue_readl(queue, ISR);
1900b83f1527SRafal Ozieblo
1901b83f1527SRafal Ozieblo if (unlikely(!status))
1902b83f1527SRafal Ozieblo return IRQ_NONE;
1903b83f1527SRafal Ozieblo
1904b83f1527SRafal Ozieblo spin_lock(&bp->lock);
1905b83f1527SRafal Ozieblo
1906b83f1527SRafal Ozieblo while (status) {
1907b83f1527SRafal Ozieblo /* close possible race with dev_close */
1908b83f1527SRafal Ozieblo if (unlikely(!netif_running(dev))) {
1909b83f1527SRafal Ozieblo queue_writel(queue, IDR, -1);
1910b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1911b83f1527SRafal Ozieblo queue_writel(queue, ISR, -1);
1912b83f1527SRafal Ozieblo break;
1913b83f1527SRafal Ozieblo }
1914b83f1527SRafal Ozieblo
1915b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1916b83f1527SRafal Ozieblo (unsigned int)(queue - bp->queues),
1917b83f1527SRafal Ozieblo (unsigned long)status);
1918b83f1527SRafal Ozieblo
1919e501070eSHarini Katakam if (status & bp->rx_intr_mask) {
1920b83f1527SRafal Ozieblo /* There's no point taking any more interrupts
1921b83f1527SRafal Ozieblo * until we have processed the buffers. The
1922b83f1527SRafal Ozieblo * scheduling call may fail if the poll routine
1923b83f1527SRafal Ozieblo * is already scheduled, so disable interrupts
1924b83f1527SRafal Ozieblo * now.
1925b83f1527SRafal Ozieblo */
1926e501070eSHarini Katakam queue_writel(queue, IDR, bp->rx_intr_mask);
1927b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1928b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(RCOMP));
1929b83f1527SRafal Ozieblo
1930138badbcSRobert Hancock if (napi_schedule_prep(&queue->napi_rx)) {
1931b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1932138badbcSRobert Hancock __napi_schedule(&queue->napi_rx);
1933138badbcSRobert Hancock }
1934138badbcSRobert Hancock }
1935138badbcSRobert Hancock
1936138badbcSRobert Hancock if (status & (MACB_BIT(TCOMP) |
1937138badbcSRobert Hancock MACB_BIT(TXUBR))) {
1938138badbcSRobert Hancock queue_writel(queue, IDR, MACB_BIT(TCOMP));
1939138badbcSRobert Hancock if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1940138badbcSRobert Hancock queue_writel(queue, ISR, MACB_BIT(TCOMP) |
1941138badbcSRobert Hancock MACB_BIT(TXUBR));
1942138badbcSRobert Hancock
1943138badbcSRobert Hancock if (status & MACB_BIT(TXUBR)) {
1944138badbcSRobert Hancock queue->txubr_pending = true;
1945138badbcSRobert Hancock wmb(); // ensure softirq can see update
1946138badbcSRobert Hancock }
1947138badbcSRobert Hancock
1948138badbcSRobert Hancock if (napi_schedule_prep(&queue->napi_tx)) {
1949138badbcSRobert Hancock netdev_vdbg(bp->dev, "scheduling TX softirq\n");
1950138badbcSRobert Hancock __napi_schedule(&queue->napi_tx);
1951b83f1527SRafal Ozieblo }
1952b83f1527SRafal Ozieblo }
1953b83f1527SRafal Ozieblo
1954b83f1527SRafal Ozieblo if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1955b83f1527SRafal Ozieblo queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1956b83f1527SRafal Ozieblo schedule_work(&queue->tx_error_task);
1957b83f1527SRafal Ozieblo
1958b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1959b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1960b83f1527SRafal Ozieblo
1961b83f1527SRafal Ozieblo break;
1962b83f1527SRafal Ozieblo }
1963b83f1527SRafal Ozieblo
1964b83f1527SRafal Ozieblo /* Link change detection isn't possible with RMII, so we'll
1965b83f1527SRafal Ozieblo * add that if/when we get our hands on a full-blown MII PHY.
1966b83f1527SRafal Ozieblo */
1967b83f1527SRafal Ozieblo
1968b83f1527SRafal Ozieblo /* There is a hardware issue under heavy load where DMA can
1969b83f1527SRafal Ozieblo * stop, this causes endless "used buffer descriptor read"
1970b83f1527SRafal Ozieblo * interrupts but it can be cleared by re-enabling RX. See
1971e501070eSHarini Katakam * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1972e501070eSHarini Katakam * section 16.7.4 for details. RXUBR is only enabled for
1973e501070eSHarini Katakam * these two versions.
1974b83f1527SRafal Ozieblo */
1975b83f1527SRafal Ozieblo if (status & MACB_BIT(RXUBR)) {
1976b83f1527SRafal Ozieblo ctrl = macb_readl(bp, NCR);
1977b83f1527SRafal Ozieblo macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1978b83f1527SRafal Ozieblo wmb();
1979b83f1527SRafal Ozieblo macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1980b83f1527SRafal Ozieblo
1981b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1982b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(RXUBR));
1983b83f1527SRafal Ozieblo }
1984b83f1527SRafal Ozieblo
1985b83f1527SRafal Ozieblo if (status & MACB_BIT(ISR_ROVR)) {
1986b83f1527SRafal Ozieblo /* We missed at least one packet */
1987b83f1527SRafal Ozieblo if (macb_is_gem(bp))
1988b83f1527SRafal Ozieblo bp->hw_stats.gem.rx_overruns++;
1989b83f1527SRafal Ozieblo else
1990b83f1527SRafal Ozieblo bp->hw_stats.macb.rx_overruns++;
1991b83f1527SRafal Ozieblo
1992b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1993b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1994b83f1527SRafal Ozieblo }
1995b83f1527SRafal Ozieblo
1996b83f1527SRafal Ozieblo if (status & MACB_BIT(HRESP)) {
1997032dc41bSHarini Katakam tasklet_schedule(&bp->hresp_err_tasklet);
1998b83f1527SRafal Ozieblo netdev_err(dev, "DMA bus error: HRESP not OK\n");
1999b83f1527SRafal Ozieblo
2000b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2001b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(HRESP));
2002b83f1527SRafal Ozieblo }
2003b83f1527SRafal Ozieblo status = queue_readl(queue, ISR);
2004b83f1527SRafal Ozieblo }
2005b83f1527SRafal Ozieblo
2006b83f1527SRafal Ozieblo spin_unlock(&bp->lock);
2007b83f1527SRafal Ozieblo
2008b83f1527SRafal Ozieblo return IRQ_HANDLED;
2009b83f1527SRafal Ozieblo }
2010b83f1527SRafal Ozieblo
2011b83f1527SRafal Ozieblo #ifdef CONFIG_NET_POLL_CONTROLLER
2012b83f1527SRafal Ozieblo /* Polling receive - used by netconsole and other diagnostic tools
2013b83f1527SRafal Ozieblo * to allow network i/o with interrupts disabled.
2014b83f1527SRafal Ozieblo */
macb_poll_controller(struct net_device * dev)2015b83f1527SRafal Ozieblo static void macb_poll_controller(struct net_device *dev)
2016b83f1527SRafal Ozieblo {
2017b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
2018b83f1527SRafal Ozieblo struct macb_queue *queue;
2019b83f1527SRafal Ozieblo unsigned long flags;
2020b83f1527SRafal Ozieblo unsigned int q;
2021b83f1527SRafal Ozieblo
2022b83f1527SRafal Ozieblo local_irq_save(flags);
2023b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2024b83f1527SRafal Ozieblo macb_interrupt(dev->irq, queue);
2025b83f1527SRafal Ozieblo local_irq_restore(flags);
2026b83f1527SRafal Ozieblo }
2027b83f1527SRafal Ozieblo #endif
2028b83f1527SRafal Ozieblo
macb_tx_map(struct macb * bp,struct macb_queue * queue,struct sk_buff * skb,unsigned int hdrlen)2029b83f1527SRafal Ozieblo static unsigned int macb_tx_map(struct macb *bp,
2030b83f1527SRafal Ozieblo struct macb_queue *queue,
2031b83f1527SRafal Ozieblo struct sk_buff *skb,
2032b83f1527SRafal Ozieblo unsigned int hdrlen)
2033b83f1527SRafal Ozieblo {
2034b83f1527SRafal Ozieblo dma_addr_t mapping;
2035b83f1527SRafal Ozieblo unsigned int len, entry, i, tx_head = queue->tx_head;
2036b83f1527SRafal Ozieblo struct macb_tx_skb *tx_skb = NULL;
2037b83f1527SRafal Ozieblo struct macb_dma_desc *desc;
2038b83f1527SRafal Ozieblo unsigned int offset, size, count = 0;
2039b83f1527SRafal Ozieblo unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
2040b83f1527SRafal Ozieblo unsigned int eof = 1, mss_mfs = 0;
2041b83f1527SRafal Ozieblo u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
2042b83f1527SRafal Ozieblo
2043b83f1527SRafal Ozieblo /* LSO */
2044b83f1527SRafal Ozieblo if (skb_shinfo(skb)->gso_size != 0) {
2045b83f1527SRafal Ozieblo if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2046b83f1527SRafal Ozieblo /* UDP - UFO */
2047b83f1527SRafal Ozieblo lso_ctrl = MACB_LSO_UFO_ENABLE;
2048b83f1527SRafal Ozieblo else
2049b83f1527SRafal Ozieblo /* TCP - TSO */
2050b83f1527SRafal Ozieblo lso_ctrl = MACB_LSO_TSO_ENABLE;
2051b83f1527SRafal Ozieblo }
2052b83f1527SRafal Ozieblo
2053b83f1527SRafal Ozieblo /* First, map non-paged data */
2054b83f1527SRafal Ozieblo len = skb_headlen(skb);
2055b83f1527SRafal Ozieblo
2056b83f1527SRafal Ozieblo /* first buffer length */
2057b83f1527SRafal Ozieblo size = hdrlen;
2058b83f1527SRafal Ozieblo
2059b83f1527SRafal Ozieblo offset = 0;
2060b83f1527SRafal Ozieblo while (len) {
2061b83f1527SRafal Ozieblo entry = macb_tx_ring_wrap(bp, tx_head);
2062b83f1527SRafal Ozieblo tx_skb = &queue->tx_skb[entry];
2063b83f1527SRafal Ozieblo
2064b83f1527SRafal Ozieblo mapping = dma_map_single(&bp->pdev->dev,
2065b83f1527SRafal Ozieblo skb->data + offset,
2066b83f1527SRafal Ozieblo size, DMA_TO_DEVICE);
2067b83f1527SRafal Ozieblo if (dma_mapping_error(&bp->pdev->dev, mapping))
2068b83f1527SRafal Ozieblo goto dma_error;
2069b83f1527SRafal Ozieblo
2070b83f1527SRafal Ozieblo /* Save info to properly release resources */
2071b83f1527SRafal Ozieblo tx_skb->skb = NULL;
2072b83f1527SRafal Ozieblo tx_skb->mapping = mapping;
2073b83f1527SRafal Ozieblo tx_skb->size = size;
2074b83f1527SRafal Ozieblo tx_skb->mapped_as_page = false;
2075b83f1527SRafal Ozieblo
2076b83f1527SRafal Ozieblo len -= size;
2077b83f1527SRafal Ozieblo offset += size;
2078b83f1527SRafal Ozieblo count++;
2079b83f1527SRafal Ozieblo tx_head++;
2080b83f1527SRafal Ozieblo
2081b83f1527SRafal Ozieblo size = min(len, bp->max_tx_length);
2082b83f1527SRafal Ozieblo }
2083b83f1527SRafal Ozieblo
2084b83f1527SRafal Ozieblo /* Then, map paged data from fragments */
2085b83f1527SRafal Ozieblo for (f = 0; f < nr_frags; f++) {
2086b83f1527SRafal Ozieblo const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2087b83f1527SRafal Ozieblo
2088b83f1527SRafal Ozieblo len = skb_frag_size(frag);
2089b83f1527SRafal Ozieblo offset = 0;
2090b83f1527SRafal Ozieblo while (len) {
2091b83f1527SRafal Ozieblo size = min(len, bp->max_tx_length);
2092b83f1527SRafal Ozieblo entry = macb_tx_ring_wrap(bp, tx_head);
2093b83f1527SRafal Ozieblo tx_skb = &queue->tx_skb[entry];
2094b83f1527SRafal Ozieblo
2095b83f1527SRafal Ozieblo mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
2096b83f1527SRafal Ozieblo offset, size, DMA_TO_DEVICE);
2097b83f1527SRafal Ozieblo if (dma_mapping_error(&bp->pdev->dev, mapping))
2098b83f1527SRafal Ozieblo goto dma_error;
2099b83f1527SRafal Ozieblo
2100b83f1527SRafal Ozieblo /* Save info to properly release resources */
2101b83f1527SRafal Ozieblo tx_skb->skb = NULL;
2102b83f1527SRafal Ozieblo tx_skb->mapping = mapping;
2103b83f1527SRafal Ozieblo tx_skb->size = size;
2104b83f1527SRafal Ozieblo tx_skb->mapped_as_page = true;
2105b83f1527SRafal Ozieblo
2106b83f1527SRafal Ozieblo len -= size;
2107b83f1527SRafal Ozieblo offset += size;
2108b83f1527SRafal Ozieblo count++;
2109b83f1527SRafal Ozieblo tx_head++;
2110b83f1527SRafal Ozieblo }
2111b83f1527SRafal Ozieblo }
2112b83f1527SRafal Ozieblo
2113b83f1527SRafal Ozieblo /* Should never happen */
2114b83f1527SRafal Ozieblo if (unlikely(!tx_skb)) {
2115b83f1527SRafal Ozieblo netdev_err(bp->dev, "BUG! empty skb!\n");
2116b83f1527SRafal Ozieblo return 0;
2117b83f1527SRafal Ozieblo }
2118b83f1527SRafal Ozieblo
2119b83f1527SRafal Ozieblo /* This is the last buffer of the frame: save socket buffer */
2120b83f1527SRafal Ozieblo tx_skb->skb = skb;
2121b83f1527SRafal Ozieblo
2122b83f1527SRafal Ozieblo /* Update TX ring: update buffer descriptors in reverse order
2123b83f1527SRafal Ozieblo * to avoid race condition
2124b83f1527SRafal Ozieblo */
2125b83f1527SRafal Ozieblo
2126b83f1527SRafal Ozieblo /* Set 'TX_USED' bit in buffer descriptor at tx_head position
2127b83f1527SRafal Ozieblo * to set the end of TX queue
2128b83f1527SRafal Ozieblo */
2129b83f1527SRafal Ozieblo i = tx_head;
2130b83f1527SRafal Ozieblo entry = macb_tx_ring_wrap(bp, i);
2131b83f1527SRafal Ozieblo ctrl = MACB_BIT(TX_USED);
2132b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, entry);
2133b83f1527SRafal Ozieblo desc->ctrl = ctrl;
2134b83f1527SRafal Ozieblo
2135b83f1527SRafal Ozieblo if (lso_ctrl) {
2136b83f1527SRafal Ozieblo if (lso_ctrl == MACB_LSO_UFO_ENABLE)
2137b83f1527SRafal Ozieblo /* include header and FCS in value given to h/w */
2138b83f1527SRafal Ozieblo mss_mfs = skb_shinfo(skb)->gso_size +
2139b83f1527SRafal Ozieblo skb_transport_offset(skb) +
2140b83f1527SRafal Ozieblo ETH_FCS_LEN;
2141b83f1527SRafal Ozieblo else /* TSO */ {
2142b83f1527SRafal Ozieblo mss_mfs = skb_shinfo(skb)->gso_size;
2143b83f1527SRafal Ozieblo /* TCP Sequence Number Source Select
2144b83f1527SRafal Ozieblo * can be set only for TSO
2145b83f1527SRafal Ozieblo */
2146b83f1527SRafal Ozieblo seq_ctrl = 0;
2147b83f1527SRafal Ozieblo }
2148b83f1527SRafal Ozieblo }
2149b83f1527SRafal Ozieblo
2150b83f1527SRafal Ozieblo do {
2151b83f1527SRafal Ozieblo i--;
2152b83f1527SRafal Ozieblo entry = macb_tx_ring_wrap(bp, i);
2153b83f1527SRafal Ozieblo tx_skb = &queue->tx_skb[entry];
2154b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, entry);
2155b83f1527SRafal Ozieblo
2156b83f1527SRafal Ozieblo ctrl = (u32)tx_skb->size;
2157b83f1527SRafal Ozieblo if (eof) {
2158b83f1527SRafal Ozieblo ctrl |= MACB_BIT(TX_LAST);
2159b83f1527SRafal Ozieblo eof = 0;
2160b83f1527SRafal Ozieblo }
2161b83f1527SRafal Ozieblo if (unlikely(entry == (bp->tx_ring_size - 1)))
2162b83f1527SRafal Ozieblo ctrl |= MACB_BIT(TX_WRAP);
2163b83f1527SRafal Ozieblo
2164b83f1527SRafal Ozieblo /* First descriptor is header descriptor */
2165b83f1527SRafal Ozieblo if (i == queue->tx_head) {
2166b83f1527SRafal Ozieblo ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2167b83f1527SRafal Ozieblo ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2168653e92a9SClaudiu Beznea if ((bp->dev->features & NETIF_F_HW_CSUM) &&
21695cebb40bSHarini Katakam skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl &&
21705cebb40bSHarini Katakam !ptp_one_step_sync(skb))
2171653e92a9SClaudiu Beznea ctrl |= MACB_BIT(TX_NOCRC);
2172b83f1527SRafal Ozieblo } else
2173b83f1527SRafal Ozieblo /* Only set MSS/MFS on payload descriptors
2174b83f1527SRafal Ozieblo * (second or later descriptor)
2175b83f1527SRafal Ozieblo */
2176b83f1527SRafal Ozieblo ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2177b83f1527SRafal Ozieblo
2178b83f1527SRafal Ozieblo /* Set TX buffer descriptor */
2179b83f1527SRafal Ozieblo macb_set_addr(bp, desc, tx_skb->mapping);
2180b83f1527SRafal Ozieblo /* desc->addr must be visible to hardware before clearing
2181b83f1527SRafal Ozieblo * 'TX_USED' bit in desc->ctrl.
2182b83f1527SRafal Ozieblo */
2183b83f1527SRafal Ozieblo wmb();
2184b83f1527SRafal Ozieblo desc->ctrl = ctrl;
2185b83f1527SRafal Ozieblo } while (i != queue->tx_head);
2186b83f1527SRafal Ozieblo
2187b83f1527SRafal Ozieblo queue->tx_head = tx_head;
2188b83f1527SRafal Ozieblo
2189b83f1527SRafal Ozieblo return count;
2190b83f1527SRafal Ozieblo
2191b83f1527SRafal Ozieblo dma_error:
2192b83f1527SRafal Ozieblo netdev_err(bp->dev, "TX DMA map failed\n");
2193b83f1527SRafal Ozieblo
2194b83f1527SRafal Ozieblo for (i = queue->tx_head; i != tx_head; i++) {
2195b83f1527SRafal Ozieblo tx_skb = macb_tx_skb(queue, i);
2196b83f1527SRafal Ozieblo
2197138badbcSRobert Hancock macb_tx_unmap(bp, tx_skb, 0);
2198b83f1527SRafal Ozieblo }
2199b83f1527SRafal Ozieblo
2200b83f1527SRafal Ozieblo return 0;
2201b83f1527SRafal Ozieblo }
2202b83f1527SRafal Ozieblo
macb_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2203b83f1527SRafal Ozieblo static netdev_features_t macb_features_check(struct sk_buff *skb,
2204b83f1527SRafal Ozieblo struct net_device *dev,
2205b83f1527SRafal Ozieblo netdev_features_t features)
2206b83f1527SRafal Ozieblo {
2207b83f1527SRafal Ozieblo unsigned int nr_frags, f;
2208b83f1527SRafal Ozieblo unsigned int hdrlen;
2209b83f1527SRafal Ozieblo
2210b83f1527SRafal Ozieblo /* Validate LSO compatibility */
2211b83f1527SRafal Ozieblo
221241c1ef97SHarini Katakam /* there is only one buffer or protocol is not UDP */
221341c1ef97SHarini Katakam if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2214b83f1527SRafal Ozieblo return features;
2215b83f1527SRafal Ozieblo
2216b83f1527SRafal Ozieblo /* length of header */
2217b83f1527SRafal Ozieblo hdrlen = skb_transport_offset(skb);
2218b83f1527SRafal Ozieblo
221941c1ef97SHarini Katakam /* For UFO only:
2220b83f1527SRafal Ozieblo * When software supplies two or more payload buffers all payload buffers
2221b83f1527SRafal Ozieblo * apart from the last must be a multiple of 8 bytes in size.
2222b83f1527SRafal Ozieblo */
2223b83f1527SRafal Ozieblo if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2224b83f1527SRafal Ozieblo return features & ~MACB_NETIF_LSO;
2225b83f1527SRafal Ozieblo
2226b83f1527SRafal Ozieblo nr_frags = skb_shinfo(skb)->nr_frags;
2227b83f1527SRafal Ozieblo /* No need to check last fragment */
2228b83f1527SRafal Ozieblo nr_frags--;
2229b83f1527SRafal Ozieblo for (f = 0; f < nr_frags; f++) {
2230b83f1527SRafal Ozieblo const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2231b83f1527SRafal Ozieblo
2232b83f1527SRafal Ozieblo if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2233b83f1527SRafal Ozieblo return features & ~MACB_NETIF_LSO;
2234b83f1527SRafal Ozieblo }
2235b83f1527SRafal Ozieblo return features;
2236b83f1527SRafal Ozieblo }
2237b83f1527SRafal Ozieblo
macb_clear_csum(struct sk_buff * skb)2238b83f1527SRafal Ozieblo static inline int macb_clear_csum(struct sk_buff *skb)
2239b83f1527SRafal Ozieblo {
2240b83f1527SRafal Ozieblo /* no change for packets without checksum offloading */
2241b83f1527SRafal Ozieblo if (skb->ip_summed != CHECKSUM_PARTIAL)
2242b83f1527SRafal Ozieblo return 0;
2243b83f1527SRafal Ozieblo
2244b83f1527SRafal Ozieblo /* make sure we can modify the header */
2245b83f1527SRafal Ozieblo if (unlikely(skb_cow_head(skb, 0)))
2246b83f1527SRafal Ozieblo return -1;
2247b83f1527SRafal Ozieblo
2248b83f1527SRafal Ozieblo /* initialize checksum field
2249b83f1527SRafal Ozieblo * This is required - at least for Zynq, which otherwise calculates
2250b83f1527SRafal Ozieblo * wrong UDP header checksums for UDP packets with UDP data len <=2
2251b83f1527SRafal Ozieblo */
2252b83f1527SRafal Ozieblo *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2253b83f1527SRafal Ozieblo return 0;
2254b83f1527SRafal Ozieblo }
2255b83f1527SRafal Ozieblo
macb_pad_and_fcs(struct sk_buff ** skb,struct net_device * ndev)2256653e92a9SClaudiu Beznea static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2257653e92a9SClaudiu Beznea {
2258403dc167SMark Deneen bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2259403dc167SMark Deneen skb_is_nonlinear(*skb);
2260653e92a9SClaudiu Beznea int padlen = ETH_ZLEN - (*skb)->len;
2261653e92a9SClaudiu Beznea int tailroom = skb_tailroom(*skb);
2262653e92a9SClaudiu Beznea struct sk_buff *nskb;
2263653e92a9SClaudiu Beznea u32 fcs;
2264653e92a9SClaudiu Beznea
2265653e92a9SClaudiu Beznea if (!(ndev->features & NETIF_F_HW_CSUM) ||
2266653e92a9SClaudiu Beznea !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
22675cebb40bSHarini Katakam skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb))
2268653e92a9SClaudiu Beznea return 0;
2269653e92a9SClaudiu Beznea
2270653e92a9SClaudiu Beznea if (padlen <= 0) {
2271653e92a9SClaudiu Beznea /* FCS could be appeded to tailroom. */
2272653e92a9SClaudiu Beznea if (tailroom >= ETH_FCS_LEN)
2273653e92a9SClaudiu Beznea goto add_fcs;
2274653e92a9SClaudiu Beznea /* No room for FCS, need to reallocate skb. */
2275653e92a9SClaudiu Beznea else
2276899ecaedSTristram Ha padlen = ETH_FCS_LEN;
2277653e92a9SClaudiu Beznea } else {
2278653e92a9SClaudiu Beznea /* Add room for FCS. */
2279653e92a9SClaudiu Beznea padlen += ETH_FCS_LEN;
2280653e92a9SClaudiu Beznea }
2281653e92a9SClaudiu Beznea
22827b90f5a6SRobert Hancock if (cloned || tailroom < padlen) {
2283653e92a9SClaudiu Beznea nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2284653e92a9SClaudiu Beznea if (!nskb)
2285653e92a9SClaudiu Beznea return -ENOMEM;
2286653e92a9SClaudiu Beznea
2287f3e5c070SHuang Zijiang dev_consume_skb_any(*skb);
2288653e92a9SClaudiu Beznea *skb = nskb;
2289653e92a9SClaudiu Beznea }
2290653e92a9SClaudiu Beznea
2291ba3e1847SClaudiu Beznea if (padlen > ETH_FCS_LEN)
2292653e92a9SClaudiu Beznea skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2293653e92a9SClaudiu Beznea
2294653e92a9SClaudiu Beznea add_fcs:
2295653e92a9SClaudiu Beznea /* set FCS to packet */
2296653e92a9SClaudiu Beznea fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2297653e92a9SClaudiu Beznea fcs = ~fcs;
2298653e92a9SClaudiu Beznea
2299653e92a9SClaudiu Beznea skb_put_u8(*skb, fcs & 0xff);
2300653e92a9SClaudiu Beznea skb_put_u8(*skb, (fcs >> 8) & 0xff);
2301653e92a9SClaudiu Beznea skb_put_u8(*skb, (fcs >> 16) & 0xff);
2302653e92a9SClaudiu Beznea skb_put_u8(*skb, (fcs >> 24) & 0xff);
2303653e92a9SClaudiu Beznea
2304653e92a9SClaudiu Beznea return 0;
2305653e92a9SClaudiu Beznea }
2306653e92a9SClaudiu Beznea
macb_start_xmit(struct sk_buff * skb,struct net_device * dev)2307d1c38957SClaudiu Beznea static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2308b83f1527SRafal Ozieblo {
2309b83f1527SRafal Ozieblo u16 queue_index = skb_get_queue_mapping(skb);
2310b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
2311b83f1527SRafal Ozieblo struct macb_queue *queue = &bp->queues[queue_index];
2312b83f1527SRafal Ozieblo unsigned int desc_cnt, nr_frags, frag_size, f;
2313b83f1527SRafal Ozieblo unsigned int hdrlen;
23148932b5a5SClaudiu Beznea bool is_lso;
2315d1c38957SClaudiu Beznea netdev_tx_t ret = NETDEV_TX_OK;
2316b83f1527SRafal Ozieblo
231733729f25SClaudiu Beznea if (macb_clear_csum(skb)) {
231833729f25SClaudiu Beznea dev_kfree_skb_any(skb);
231933729f25SClaudiu Beznea return ret;
232033729f25SClaudiu Beznea }
232133729f25SClaudiu Beznea
2322653e92a9SClaudiu Beznea if (macb_pad_and_fcs(&skb, dev)) {
2323653e92a9SClaudiu Beznea dev_kfree_skb_any(skb);
2324653e92a9SClaudiu Beznea return ret;
2325653e92a9SClaudiu Beznea }
2326653e92a9SClaudiu Beznea
23278e7610e6SRobert Hancock #ifdef CONFIG_MACB_USE_HWSTAMP
23288e7610e6SRobert Hancock if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
23298e7610e6SRobert Hancock (bp->hw_dma_cap & HW_DMA_CAP_PTP))
23308e7610e6SRobert Hancock skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
23318e7610e6SRobert Hancock #endif
23328e7610e6SRobert Hancock
2333b83f1527SRafal Ozieblo is_lso = (skb_shinfo(skb)->gso_size != 0);
2334b83f1527SRafal Ozieblo
2335b83f1527SRafal Ozieblo if (is_lso) {
2336b83f1527SRafal Ozieblo /* length of headers */
23378932b5a5SClaudiu Beznea if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2338b83f1527SRafal Ozieblo /* only queue eth + ip headers separately for UDP */
2339b83f1527SRafal Ozieblo hdrlen = skb_transport_offset(skb);
2340b83f1527SRafal Ozieblo else
2341504148feSEric Dumazet hdrlen = skb_tcp_all_headers(skb);
2342b83f1527SRafal Ozieblo if (skb_headlen(skb) < hdrlen) {
2343b83f1527SRafal Ozieblo netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2344b83f1527SRafal Ozieblo /* if this is required, would need to copy to single buffer */
2345b83f1527SRafal Ozieblo return NETDEV_TX_BUSY;
2346b83f1527SRafal Ozieblo }
2347b83f1527SRafal Ozieblo } else
2348b83f1527SRafal Ozieblo hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2349b83f1527SRafal Ozieblo
2350b83f1527SRafal Ozieblo #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2351b83f1527SRafal Ozieblo netdev_vdbg(bp->dev,
2352b83f1527SRafal Ozieblo "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2353b83f1527SRafal Ozieblo queue_index, skb->len, skb->head, skb->data,
2354b83f1527SRafal Ozieblo skb_tail_pointer(skb), skb_end_pointer(skb));
2355b83f1527SRafal Ozieblo print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2356b83f1527SRafal Ozieblo skb->data, 16, true);
2357b83f1527SRafal Ozieblo #endif
2358b83f1527SRafal Ozieblo
2359b83f1527SRafal Ozieblo /* Count how many TX buffer descriptors are needed to send this
2360b83f1527SRafal Ozieblo * socket buffer: skb fragments of jumbo frames may need to be
2361b83f1527SRafal Ozieblo * split into many buffer descriptors.
2362b83f1527SRafal Ozieblo */
2363b83f1527SRafal Ozieblo if (is_lso && (skb_headlen(skb) > hdrlen))
2364b83f1527SRafal Ozieblo /* extra header descriptor if also payload in first buffer */
2365b83f1527SRafal Ozieblo desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2366b83f1527SRafal Ozieblo else
2367b83f1527SRafal Ozieblo desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2368b83f1527SRafal Ozieblo nr_frags = skb_shinfo(skb)->nr_frags;
2369b83f1527SRafal Ozieblo for (f = 0; f < nr_frags; f++) {
2370b83f1527SRafal Ozieblo frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2371b83f1527SRafal Ozieblo desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2372b83f1527SRafal Ozieblo }
2373b83f1527SRafal Ozieblo
2374138badbcSRobert Hancock spin_lock_bh(&queue->tx_ptr_lock);
2375b83f1527SRafal Ozieblo
2376b83f1527SRafal Ozieblo /* This is a hard error, log it. */
2377b83f1527SRafal Ozieblo if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2378b83f1527SRafal Ozieblo bp->tx_ring_size) < desc_cnt) {
2379b83f1527SRafal Ozieblo netif_stop_subqueue(dev, queue_index);
2380b83f1527SRafal Ozieblo netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2381b83f1527SRafal Ozieblo queue->tx_head, queue->tx_tail);
2382138badbcSRobert Hancock ret = NETDEV_TX_BUSY;
2383138badbcSRobert Hancock goto unlock;
2384b83f1527SRafal Ozieblo }
2385b83f1527SRafal Ozieblo
2386b83f1527SRafal Ozieblo /* Map socket buffer for DMA transfer */
2387b83f1527SRafal Ozieblo if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2388b83f1527SRafal Ozieblo dev_kfree_skb_any(skb);
2389b83f1527SRafal Ozieblo goto unlock;
2390b83f1527SRafal Ozieblo }
2391b83f1527SRafal Ozieblo
2392b83f1527SRafal Ozieblo /* Make newly initialized descriptor visible to hardware */
2393b83f1527SRafal Ozieblo wmb();
2394b83f1527SRafal Ozieblo skb_tx_timestamp(skb);
2395b83f1527SRafal Ozieblo
2396138badbcSRobert Hancock spin_lock_irq(&bp->lock);
2397b83f1527SRafal Ozieblo macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2398138badbcSRobert Hancock spin_unlock_irq(&bp->lock);
2399b83f1527SRafal Ozieblo
2400b83f1527SRafal Ozieblo if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2401b83f1527SRafal Ozieblo netif_stop_subqueue(dev, queue_index);
2402b83f1527SRafal Ozieblo
2403b83f1527SRafal Ozieblo unlock:
2404138badbcSRobert Hancock spin_unlock_bh(&queue->tx_ptr_lock);
2405b83f1527SRafal Ozieblo
2406d1c38957SClaudiu Beznea return ret;
2407b83f1527SRafal Ozieblo }
2408b83f1527SRafal Ozieblo
macb_init_rx_buffer_size(struct macb * bp,size_t size)2409b83f1527SRafal Ozieblo static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2410b83f1527SRafal Ozieblo {
2411b83f1527SRafal Ozieblo if (!macb_is_gem(bp)) {
2412b83f1527SRafal Ozieblo bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2413b83f1527SRafal Ozieblo } else {
2414b83f1527SRafal Ozieblo bp->rx_buffer_size = size;
2415b83f1527SRafal Ozieblo
2416b83f1527SRafal Ozieblo if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2417b83f1527SRafal Ozieblo netdev_dbg(bp->dev,
2418b83f1527SRafal Ozieblo "RX buffer must be multiple of %d bytes, expanding\n",
2419b83f1527SRafal Ozieblo RX_BUFFER_MULTIPLE);
2420b83f1527SRafal Ozieblo bp->rx_buffer_size =
2421b83f1527SRafal Ozieblo roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2422b83f1527SRafal Ozieblo }
2423b83f1527SRafal Ozieblo }
2424b83f1527SRafal Ozieblo
2425b83f1527SRafal Ozieblo netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2426b83f1527SRafal Ozieblo bp->dev->mtu, bp->rx_buffer_size);
2427b83f1527SRafal Ozieblo }
2428b83f1527SRafal Ozieblo
gem_free_rx_buffers(struct macb * bp)2429b83f1527SRafal Ozieblo static void gem_free_rx_buffers(struct macb *bp)
2430b83f1527SRafal Ozieblo {
2431b83f1527SRafal Ozieblo struct sk_buff *skb;
2432b83f1527SRafal Ozieblo struct macb_dma_desc *desc;
2433ae1f2a56SRafal Ozieblo struct macb_queue *queue;
2434b83f1527SRafal Ozieblo dma_addr_t addr;
2435ae1f2a56SRafal Ozieblo unsigned int q;
2436b83f1527SRafal Ozieblo int i;
2437b83f1527SRafal Ozieblo
2438ae1f2a56SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2439ae1f2a56SRafal Ozieblo if (!queue->rx_skbuff)
2440ae1f2a56SRafal Ozieblo continue;
2441b83f1527SRafal Ozieblo
2442b83f1527SRafal Ozieblo for (i = 0; i < bp->rx_ring_size; i++) {
2443ae1f2a56SRafal Ozieblo skb = queue->rx_skbuff[i];
2444b83f1527SRafal Ozieblo
2445b83f1527SRafal Ozieblo if (!skb)
2446b83f1527SRafal Ozieblo continue;
2447b83f1527SRafal Ozieblo
2448ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, i);
2449b83f1527SRafal Ozieblo addr = macb_get_addr(bp, desc);
2450b83f1527SRafal Ozieblo
2451b83f1527SRafal Ozieblo dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2452b83f1527SRafal Ozieblo DMA_FROM_DEVICE);
2453b83f1527SRafal Ozieblo dev_kfree_skb_any(skb);
2454b83f1527SRafal Ozieblo skb = NULL;
2455b83f1527SRafal Ozieblo }
2456b83f1527SRafal Ozieblo
2457ae1f2a56SRafal Ozieblo kfree(queue->rx_skbuff);
2458ae1f2a56SRafal Ozieblo queue->rx_skbuff = NULL;
2459ae1f2a56SRafal Ozieblo }
2460b83f1527SRafal Ozieblo }
2461b83f1527SRafal Ozieblo
macb_free_rx_buffers(struct macb * bp)2462b83f1527SRafal Ozieblo static void macb_free_rx_buffers(struct macb *bp)
2463b83f1527SRafal Ozieblo {
2464ae1f2a56SRafal Ozieblo struct macb_queue *queue = &bp->queues[0];
2465ae1f2a56SRafal Ozieblo
2466ae1f2a56SRafal Ozieblo if (queue->rx_buffers) {
2467b83f1527SRafal Ozieblo dma_free_coherent(&bp->pdev->dev,
2468b83f1527SRafal Ozieblo bp->rx_ring_size * bp->rx_buffer_size,
2469ae1f2a56SRafal Ozieblo queue->rx_buffers, queue->rx_buffers_dma);
2470ae1f2a56SRafal Ozieblo queue->rx_buffers = NULL;
2471b83f1527SRafal Ozieblo }
2472b83f1527SRafal Ozieblo }
2473b83f1527SRafal Ozieblo
macb_free_consistent(struct macb * bp)2474b83f1527SRafal Ozieblo static void macb_free_consistent(struct macb *bp)
2475b83f1527SRafal Ozieblo {
2476b83f1527SRafal Ozieblo struct macb_queue *queue;
2477b83f1527SRafal Ozieblo unsigned int q;
2478404cd086SHarini Katakam int size;
2479b83f1527SRafal Ozieblo
2480b83f1527SRafal Ozieblo bp->macbgem_ops.mog_free_rx_buffers(bp);
2481b83f1527SRafal Ozieblo
2482b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2483b83f1527SRafal Ozieblo kfree(queue->tx_skb);
2484b83f1527SRafal Ozieblo queue->tx_skb = NULL;
2485b83f1527SRafal Ozieblo if (queue->tx_ring) {
2486404cd086SHarini Katakam size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2487404cd086SHarini Katakam dma_free_coherent(&bp->pdev->dev, size,
2488b83f1527SRafal Ozieblo queue->tx_ring, queue->tx_ring_dma);
2489b83f1527SRafal Ozieblo queue->tx_ring = NULL;
2490b83f1527SRafal Ozieblo }
2491e50b770eSHarini Katakam if (queue->rx_ring) {
2492404cd086SHarini Katakam size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2493404cd086SHarini Katakam dma_free_coherent(&bp->pdev->dev, size,
2494e50b770eSHarini Katakam queue->rx_ring, queue->rx_ring_dma);
2495e50b770eSHarini Katakam queue->rx_ring = NULL;
2496e50b770eSHarini Katakam }
2497b83f1527SRafal Ozieblo }
2498b83f1527SRafal Ozieblo }
2499b83f1527SRafal Ozieblo
gem_alloc_rx_buffers(struct macb * bp)2500b83f1527SRafal Ozieblo static int gem_alloc_rx_buffers(struct macb *bp)
2501b83f1527SRafal Ozieblo {
2502ae1f2a56SRafal Ozieblo struct macb_queue *queue;
2503ae1f2a56SRafal Ozieblo unsigned int q;
2504b83f1527SRafal Ozieblo int size;
2505b83f1527SRafal Ozieblo
2506ae1f2a56SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2507b83f1527SRafal Ozieblo size = bp->rx_ring_size * sizeof(struct sk_buff *);
2508ae1f2a56SRafal Ozieblo queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2509ae1f2a56SRafal Ozieblo if (!queue->rx_skbuff)
2510b83f1527SRafal Ozieblo return -ENOMEM;
2511b83f1527SRafal Ozieblo else
2512b83f1527SRafal Ozieblo netdev_dbg(bp->dev,
2513b83f1527SRafal Ozieblo "Allocated %d RX struct sk_buff entries at %p\n",
2514ae1f2a56SRafal Ozieblo bp->rx_ring_size, queue->rx_skbuff);
2515ae1f2a56SRafal Ozieblo }
2516b83f1527SRafal Ozieblo return 0;
2517b83f1527SRafal Ozieblo }
2518b83f1527SRafal Ozieblo
macb_alloc_rx_buffers(struct macb * bp)2519b83f1527SRafal Ozieblo static int macb_alloc_rx_buffers(struct macb *bp)
2520b83f1527SRafal Ozieblo {
2521ae1f2a56SRafal Ozieblo struct macb_queue *queue = &bp->queues[0];
2522b83f1527SRafal Ozieblo int size;
2523b83f1527SRafal Ozieblo
2524b83f1527SRafal Ozieblo size = bp->rx_ring_size * bp->rx_buffer_size;
2525ae1f2a56SRafal Ozieblo queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2526ae1f2a56SRafal Ozieblo &queue->rx_buffers_dma, GFP_KERNEL);
2527ae1f2a56SRafal Ozieblo if (!queue->rx_buffers)
2528b83f1527SRafal Ozieblo return -ENOMEM;
2529b83f1527SRafal Ozieblo
2530b83f1527SRafal Ozieblo netdev_dbg(bp->dev,
2531b83f1527SRafal Ozieblo "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2532ae1f2a56SRafal Ozieblo size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2533b83f1527SRafal Ozieblo return 0;
2534b83f1527SRafal Ozieblo }
2535b83f1527SRafal Ozieblo
macb_alloc_consistent(struct macb * bp)2536b83f1527SRafal Ozieblo static int macb_alloc_consistent(struct macb *bp)
2537b83f1527SRafal Ozieblo {
2538b83f1527SRafal Ozieblo struct macb_queue *queue;
2539b83f1527SRafal Ozieblo unsigned int q;
2540b83f1527SRafal Ozieblo int size;
2541b83f1527SRafal Ozieblo
2542b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2543404cd086SHarini Katakam size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2544b83f1527SRafal Ozieblo queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2545b83f1527SRafal Ozieblo &queue->tx_ring_dma,
2546b83f1527SRafal Ozieblo GFP_KERNEL);
2547b83f1527SRafal Ozieblo if (!queue->tx_ring)
2548b83f1527SRafal Ozieblo goto out_err;
2549b83f1527SRafal Ozieblo netdev_dbg(bp->dev,
2550b83f1527SRafal Ozieblo "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2551b83f1527SRafal Ozieblo q, size, (unsigned long)queue->tx_ring_dma,
2552b83f1527SRafal Ozieblo queue->tx_ring);
2553b83f1527SRafal Ozieblo
2554b83f1527SRafal Ozieblo size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2555b83f1527SRafal Ozieblo queue->tx_skb = kmalloc(size, GFP_KERNEL);
2556b83f1527SRafal Ozieblo if (!queue->tx_skb)
2557b83f1527SRafal Ozieblo goto out_err;
2558b83f1527SRafal Ozieblo
2559404cd086SHarini Katakam size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2560ae1f2a56SRafal Ozieblo queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2561ae1f2a56SRafal Ozieblo &queue->rx_ring_dma, GFP_KERNEL);
2562ae1f2a56SRafal Ozieblo if (!queue->rx_ring)
2563b83f1527SRafal Ozieblo goto out_err;
2564b83f1527SRafal Ozieblo netdev_dbg(bp->dev,
2565b83f1527SRafal Ozieblo "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2566ae1f2a56SRafal Ozieblo size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2567ae1f2a56SRafal Ozieblo }
2568b83f1527SRafal Ozieblo if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2569b83f1527SRafal Ozieblo goto out_err;
2570b83f1527SRafal Ozieblo
2571b83f1527SRafal Ozieblo return 0;
2572b83f1527SRafal Ozieblo
2573b83f1527SRafal Ozieblo out_err:
2574b83f1527SRafal Ozieblo macb_free_consistent(bp);
2575b83f1527SRafal Ozieblo return -ENOMEM;
2576b83f1527SRafal Ozieblo }
2577b83f1527SRafal Ozieblo
gem_init_rings(struct macb * bp)2578b83f1527SRafal Ozieblo static void gem_init_rings(struct macb *bp)
2579b83f1527SRafal Ozieblo {
2580b83f1527SRafal Ozieblo struct macb_queue *queue;
2581b83f1527SRafal Ozieblo struct macb_dma_desc *desc = NULL;
2582b83f1527SRafal Ozieblo unsigned int q;
2583b83f1527SRafal Ozieblo int i;
2584b83f1527SRafal Ozieblo
2585b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2586b83f1527SRafal Ozieblo for (i = 0; i < bp->tx_ring_size; i++) {
2587b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, i);
2588b83f1527SRafal Ozieblo macb_set_addr(bp, desc, 0);
2589b83f1527SRafal Ozieblo desc->ctrl = MACB_BIT(TX_USED);
2590b83f1527SRafal Ozieblo }
2591b83f1527SRafal Ozieblo desc->ctrl |= MACB_BIT(TX_WRAP);
2592b83f1527SRafal Ozieblo queue->tx_head = 0;
2593b83f1527SRafal Ozieblo queue->tx_tail = 0;
2594ae1f2a56SRafal Ozieblo
2595ae1f2a56SRafal Ozieblo queue->rx_tail = 0;
2596ae1f2a56SRafal Ozieblo queue->rx_prepared_head = 0;
2597ae1f2a56SRafal Ozieblo
2598ae1f2a56SRafal Ozieblo gem_rx_refill(queue);
2599b83f1527SRafal Ozieblo }
2600b83f1527SRafal Ozieblo
2601b83f1527SRafal Ozieblo }
2602b83f1527SRafal Ozieblo
macb_init_rings(struct macb * bp)2603b83f1527SRafal Ozieblo static void macb_init_rings(struct macb *bp)
2604b83f1527SRafal Ozieblo {
2605b83f1527SRafal Ozieblo int i;
2606b83f1527SRafal Ozieblo struct macb_dma_desc *desc = NULL;
2607b83f1527SRafal Ozieblo
2608ae1f2a56SRafal Ozieblo macb_init_rx_ring(&bp->queues[0]);
2609b83f1527SRafal Ozieblo
2610b83f1527SRafal Ozieblo for (i = 0; i < bp->tx_ring_size; i++) {
2611b83f1527SRafal Ozieblo desc = macb_tx_desc(&bp->queues[0], i);
2612b83f1527SRafal Ozieblo macb_set_addr(bp, desc, 0);
2613b83f1527SRafal Ozieblo desc->ctrl = MACB_BIT(TX_USED);
2614b83f1527SRafal Ozieblo }
2615b83f1527SRafal Ozieblo bp->queues[0].tx_head = 0;
2616b83f1527SRafal Ozieblo bp->queues[0].tx_tail = 0;
2617b83f1527SRafal Ozieblo desc->ctrl |= MACB_BIT(TX_WRAP);
2618b83f1527SRafal Ozieblo }
2619b83f1527SRafal Ozieblo
macb_reset_hw(struct macb * bp)2620b83f1527SRafal Ozieblo static void macb_reset_hw(struct macb *bp)
2621b83f1527SRafal Ozieblo {
2622b83f1527SRafal Ozieblo struct macb_queue *queue;
2623b83f1527SRafal Ozieblo unsigned int q;
26240da70f80SAnssi Hannula u32 ctrl = macb_readl(bp, NCR);
2625b83f1527SRafal Ozieblo
2626b83f1527SRafal Ozieblo /* Disable RX and TX (XXX: Should we halt the transmission
2627b83f1527SRafal Ozieblo * more gracefully?)
2628b83f1527SRafal Ozieblo */
26290da70f80SAnssi Hannula ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2630b83f1527SRafal Ozieblo
2631b83f1527SRafal Ozieblo /* Clear the stats registers (XXX: Update stats first?) */
26320da70f80SAnssi Hannula ctrl |= MACB_BIT(CLRSTAT);
26330da70f80SAnssi Hannula
26340da70f80SAnssi Hannula macb_writel(bp, NCR, ctrl);
2635b83f1527SRafal Ozieblo
2636b83f1527SRafal Ozieblo /* Clear all status flags */
2637b83f1527SRafal Ozieblo macb_writel(bp, TSR, -1);
2638b83f1527SRafal Ozieblo macb_writel(bp, RSR, -1);
2639b83f1527SRafal Ozieblo
2640cae4bc06SMaulik Jodhani /* Disable RX partial store and forward and reset watermark value */
2641cae4bc06SMaulik Jodhani gem_writel(bp, PBUFRXCUT, 0);
2642cae4bc06SMaulik Jodhani
2643b83f1527SRafal Ozieblo /* Disable all interrupts */
2644b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2645b83f1527SRafal Ozieblo queue_writel(queue, IDR, -1);
2646b83f1527SRafal Ozieblo queue_readl(queue, ISR);
2647b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2648b83f1527SRafal Ozieblo queue_writel(queue, ISR, -1);
2649b83f1527SRafal Ozieblo }
2650b83f1527SRafal Ozieblo }
2651b83f1527SRafal Ozieblo
gem_mdc_clk_div(struct macb * bp)2652b83f1527SRafal Ozieblo static u32 gem_mdc_clk_div(struct macb *bp)
2653b83f1527SRafal Ozieblo {
2654b83f1527SRafal Ozieblo u32 config;
2655b83f1527SRafal Ozieblo unsigned long pclk_hz = clk_get_rate(bp->pclk);
2656b83f1527SRafal Ozieblo
2657b83f1527SRafal Ozieblo if (pclk_hz <= 20000000)
2658b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV8);
2659b83f1527SRafal Ozieblo else if (pclk_hz <= 40000000)
2660b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV16);
2661b83f1527SRafal Ozieblo else if (pclk_hz <= 80000000)
2662b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV32);
2663b83f1527SRafal Ozieblo else if (pclk_hz <= 120000000)
2664b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV48);
2665b83f1527SRafal Ozieblo else if (pclk_hz <= 160000000)
2666b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV64);
2667b31587feSBartosz Wawrzyniak else if (pclk_hz <= 240000000)
2668b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV96);
2669b31587feSBartosz Wawrzyniak else if (pclk_hz <= 320000000)
2670b31587feSBartosz Wawrzyniak config = GEM_BF(CLK, GEM_CLK_DIV128);
2671b31587feSBartosz Wawrzyniak else
2672b31587feSBartosz Wawrzyniak config = GEM_BF(CLK, GEM_CLK_DIV224);
2673b83f1527SRafal Ozieblo
2674b83f1527SRafal Ozieblo return config;
2675b83f1527SRafal Ozieblo }
2676b83f1527SRafal Ozieblo
macb_mdc_clk_div(struct macb * bp)2677b83f1527SRafal Ozieblo static u32 macb_mdc_clk_div(struct macb *bp)
2678b83f1527SRafal Ozieblo {
2679b83f1527SRafal Ozieblo u32 config;
2680b83f1527SRafal Ozieblo unsigned long pclk_hz;
2681b83f1527SRafal Ozieblo
2682b83f1527SRafal Ozieblo if (macb_is_gem(bp))
2683b83f1527SRafal Ozieblo return gem_mdc_clk_div(bp);
2684b83f1527SRafal Ozieblo
2685b83f1527SRafal Ozieblo pclk_hz = clk_get_rate(bp->pclk);
2686b83f1527SRafal Ozieblo if (pclk_hz <= 20000000)
2687b83f1527SRafal Ozieblo config = MACB_BF(CLK, MACB_CLK_DIV8);
2688b83f1527SRafal Ozieblo else if (pclk_hz <= 40000000)
2689b83f1527SRafal Ozieblo config = MACB_BF(CLK, MACB_CLK_DIV16);
2690b83f1527SRafal Ozieblo else if (pclk_hz <= 80000000)
2691b83f1527SRafal Ozieblo config = MACB_BF(CLK, MACB_CLK_DIV32);
2692b83f1527SRafal Ozieblo else
2693b83f1527SRafal Ozieblo config = MACB_BF(CLK, MACB_CLK_DIV64);
2694b83f1527SRafal Ozieblo
2695b83f1527SRafal Ozieblo return config;
2696b83f1527SRafal Ozieblo }
2697b83f1527SRafal Ozieblo
2698b83f1527SRafal Ozieblo /* Get the DMA bus width field of the network configuration register that we
2699b83f1527SRafal Ozieblo * should program. We find the width from decoding the design configuration
2700b83f1527SRafal Ozieblo * register to find the maximum supported data bus width.
2701b83f1527SRafal Ozieblo */
macb_dbw(struct macb * bp)2702b83f1527SRafal Ozieblo static u32 macb_dbw(struct macb *bp)
2703b83f1527SRafal Ozieblo {
2704b83f1527SRafal Ozieblo if (!macb_is_gem(bp))
2705b83f1527SRafal Ozieblo return 0;
2706b83f1527SRafal Ozieblo
2707b83f1527SRafal Ozieblo switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2708b83f1527SRafal Ozieblo case 4:
2709b83f1527SRafal Ozieblo return GEM_BF(DBW, GEM_DBW128);
2710b83f1527SRafal Ozieblo case 2:
2711b83f1527SRafal Ozieblo return GEM_BF(DBW, GEM_DBW64);
2712b83f1527SRafal Ozieblo case 1:
2713b83f1527SRafal Ozieblo default:
2714b83f1527SRafal Ozieblo return GEM_BF(DBW, GEM_DBW32);
2715b83f1527SRafal Ozieblo }
2716b83f1527SRafal Ozieblo }
2717b83f1527SRafal Ozieblo
2718b83f1527SRafal Ozieblo /* Configure the receive DMA engine
2719b83f1527SRafal Ozieblo * - use the correct receive buffer size
2720b83f1527SRafal Ozieblo * - set best burst length for DMA operations
2721b83f1527SRafal Ozieblo * (if not supported by FIFO, it will fallback to default)
2722b83f1527SRafal Ozieblo * - set both rx/tx packet buffers to full memory size
2723b83f1527SRafal Ozieblo * These are configurable parameters for GEM.
2724b83f1527SRafal Ozieblo */
macb_configure_dma(struct macb * bp)2725b83f1527SRafal Ozieblo static void macb_configure_dma(struct macb *bp)
2726b83f1527SRafal Ozieblo {
2727ae1f2a56SRafal Ozieblo struct macb_queue *queue;
2728ae1f2a56SRafal Ozieblo u32 buffer_size;
2729ae1f2a56SRafal Ozieblo unsigned int q;
2730b83f1527SRafal Ozieblo u32 dmacfg;
2731b83f1527SRafal Ozieblo
2732ae1f2a56SRafal Ozieblo buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2733b83f1527SRafal Ozieblo if (macb_is_gem(bp)) {
2734b83f1527SRafal Ozieblo dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2735ae1f2a56SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2736ae1f2a56SRafal Ozieblo if (q)
2737ae1f2a56SRafal Ozieblo queue_writel(queue, RBQS, buffer_size);
2738ae1f2a56SRafal Ozieblo else
2739ae1f2a56SRafal Ozieblo dmacfg |= GEM_BF(RXBS, buffer_size);
2740ae1f2a56SRafal Ozieblo }
2741b83f1527SRafal Ozieblo if (bp->dma_burst_length)
2742b83f1527SRafal Ozieblo dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2743b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2744b83f1527SRafal Ozieblo dmacfg &= ~GEM_BIT(ENDIA_PKT);
2745b83f1527SRafal Ozieblo
2746b83f1527SRafal Ozieblo if (bp->native_io)
2747b83f1527SRafal Ozieblo dmacfg &= ~GEM_BIT(ENDIA_DESC);
2748b83f1527SRafal Ozieblo else
2749b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2750b83f1527SRafal Ozieblo
2751b83f1527SRafal Ozieblo if (bp->dev->features & NETIF_F_HW_CSUM)
2752b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(TXCOEN);
2753b83f1527SRafal Ozieblo else
2754b83f1527SRafal Ozieblo dmacfg &= ~GEM_BIT(TXCOEN);
2755b83f1527SRafal Ozieblo
2756bd620720SMichal Simek dmacfg &= ~GEM_BIT(ADDR64);
2757b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2758b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2759b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(ADDR64);
2760b83f1527SRafal Ozieblo #endif
2761b83f1527SRafal Ozieblo #ifdef CONFIG_MACB_USE_HWSTAMP
2762b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2763b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2764b83f1527SRafal Ozieblo #endif
2765b83f1527SRafal Ozieblo netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2766b83f1527SRafal Ozieblo dmacfg);
2767b83f1527SRafal Ozieblo gem_writel(bp, DMACFG, dmacfg);
2768b83f1527SRafal Ozieblo }
2769b83f1527SRafal Ozieblo }
2770b83f1527SRafal Ozieblo
macb_init_hw(struct macb * bp)2771b83f1527SRafal Ozieblo static void macb_init_hw(struct macb *bp)
2772b83f1527SRafal Ozieblo {
2773b83f1527SRafal Ozieblo u32 config;
2774b83f1527SRafal Ozieblo
2775b83f1527SRafal Ozieblo macb_reset_hw(bp);
2776b83f1527SRafal Ozieblo macb_set_hwaddr(bp);
2777b83f1527SRafal Ozieblo
2778b83f1527SRafal Ozieblo config = macb_mdc_clk_div(bp);
2779b83f1527SRafal Ozieblo config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2780b83f1527SRafal Ozieblo config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2781b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_JUMBO)
2782b83f1527SRafal Ozieblo config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2783b83f1527SRafal Ozieblo else
2784b83f1527SRafal Ozieblo config |= MACB_BIT(BIG); /* Receive oversized frames */
2785b83f1527SRafal Ozieblo if (bp->dev->flags & IFF_PROMISC)
2786b83f1527SRafal Ozieblo config |= MACB_BIT(CAF); /* Copy All Frames */
2787b83f1527SRafal Ozieblo else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2788b83f1527SRafal Ozieblo config |= GEM_BIT(RXCOEN);
2789b83f1527SRafal Ozieblo if (!(bp->dev->flags & IFF_BROADCAST))
2790b83f1527SRafal Ozieblo config |= MACB_BIT(NBC); /* No BroadCast */
2791b83f1527SRafal Ozieblo config |= macb_dbw(bp);
2792b83f1527SRafal Ozieblo macb_writel(bp, NCFGR, config);
2793b83f1527SRafal Ozieblo if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2794b83f1527SRafal Ozieblo gem_writel(bp, JML, bp->jumbo_max_len);
2795b83f1527SRafal Ozieblo bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2796b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_JUMBO)
2797b83f1527SRafal Ozieblo bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2798b83f1527SRafal Ozieblo
2799b83f1527SRafal Ozieblo macb_configure_dma(bp);
2800cae4bc06SMaulik Jodhani
2801cae4bc06SMaulik Jodhani /* Enable RX partial store and forward and set watermark */
2802cae4bc06SMaulik Jodhani if (bp->rx_watermark)
2803cae4bc06SMaulik Jodhani gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU)));
2804b83f1527SRafal Ozieblo }
2805b83f1527SRafal Ozieblo
2806b83f1527SRafal Ozieblo /* The hash address register is 64 bits long and takes up two
2807b83f1527SRafal Ozieblo * locations in the memory map. The least significant bits are stored
2808b83f1527SRafal Ozieblo * in EMAC_HSL and the most significant bits in EMAC_HSH.
2809b83f1527SRafal Ozieblo *
2810b83f1527SRafal Ozieblo * The unicast hash enable and the multicast hash enable bits in the
2811b83f1527SRafal Ozieblo * network configuration register enable the reception of hash matched
2812b83f1527SRafal Ozieblo * frames. The destination address is reduced to a 6 bit index into
2813b83f1527SRafal Ozieblo * the 64 bit hash register using the following hash function. The
2814b83f1527SRafal Ozieblo * hash function is an exclusive or of every sixth bit of the
2815b83f1527SRafal Ozieblo * destination address.
2816b83f1527SRafal Ozieblo *
2817b83f1527SRafal Ozieblo * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2818b83f1527SRafal Ozieblo * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2819b83f1527SRafal Ozieblo * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2820b83f1527SRafal Ozieblo * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2821b83f1527SRafal Ozieblo * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2822b83f1527SRafal Ozieblo * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2823b83f1527SRafal Ozieblo *
2824b83f1527SRafal Ozieblo * da[0] represents the least significant bit of the first byte
2825b83f1527SRafal Ozieblo * received, that is, the multicast/unicast indicator, and da[47]
2826b83f1527SRafal Ozieblo * represents the most significant bit of the last byte received. If
2827b83f1527SRafal Ozieblo * the hash index, hi[n], points to a bit that is set in the hash
2828b83f1527SRafal Ozieblo * register then the frame will be matched according to whether the
2829b83f1527SRafal Ozieblo * frame is multicast or unicast. A multicast match will be signalled
2830b83f1527SRafal Ozieblo * if the multicast hash enable bit is set, da[0] is 1 and the hash
2831b83f1527SRafal Ozieblo * index points to a bit set in the hash register. A unicast match
2832b83f1527SRafal Ozieblo * will be signalled if the unicast hash enable bit is set, da[0] is 0
2833b83f1527SRafal Ozieblo * and the hash index points to a bit set in the hash register. To
2834b83f1527SRafal Ozieblo * receive all multicast frames, the hash register should be set with
2835b83f1527SRafal Ozieblo * all ones and the multicast hash enable bit should be set in the
2836b83f1527SRafal Ozieblo * network configuration register.
2837b83f1527SRafal Ozieblo */
2838b83f1527SRafal Ozieblo
hash_bit_value(int bitnr,__u8 * addr)2839b83f1527SRafal Ozieblo static inline int hash_bit_value(int bitnr, __u8 *addr)
2840b83f1527SRafal Ozieblo {
2841b83f1527SRafal Ozieblo if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2842b83f1527SRafal Ozieblo return 1;
2843b83f1527SRafal Ozieblo return 0;
2844b83f1527SRafal Ozieblo }
2845b83f1527SRafal Ozieblo
2846b83f1527SRafal Ozieblo /* Return the hash index value for the specified address. */
hash_get_index(__u8 * addr)2847b83f1527SRafal Ozieblo static int hash_get_index(__u8 *addr)
2848b83f1527SRafal Ozieblo {
2849b83f1527SRafal Ozieblo int i, j, bitval;
2850b83f1527SRafal Ozieblo int hash_index = 0;
2851b83f1527SRafal Ozieblo
2852b83f1527SRafal Ozieblo for (j = 0; j < 6; j++) {
2853b83f1527SRafal Ozieblo for (i = 0, bitval = 0; i < 8; i++)
2854b83f1527SRafal Ozieblo bitval ^= hash_bit_value(i * 6 + j, addr);
2855b83f1527SRafal Ozieblo
2856b83f1527SRafal Ozieblo hash_index |= (bitval << j);
2857b83f1527SRafal Ozieblo }
2858b83f1527SRafal Ozieblo
2859b83f1527SRafal Ozieblo return hash_index;
2860b83f1527SRafal Ozieblo }
2861b83f1527SRafal Ozieblo
2862b83f1527SRafal Ozieblo /* Add multicast addresses to the internal multicast-hash table. */
macb_sethashtable(struct net_device * dev)2863b83f1527SRafal Ozieblo static void macb_sethashtable(struct net_device *dev)
2864b83f1527SRafal Ozieblo {
2865b83f1527SRafal Ozieblo struct netdev_hw_addr *ha;
2866b83f1527SRafal Ozieblo unsigned long mc_filter[2];
2867b83f1527SRafal Ozieblo unsigned int bitnr;
2868b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
2869b83f1527SRafal Ozieblo
2870b83f1527SRafal Ozieblo mc_filter[0] = 0;
2871b83f1527SRafal Ozieblo mc_filter[1] = 0;
2872b83f1527SRafal Ozieblo
2873b83f1527SRafal Ozieblo netdev_for_each_mc_addr(ha, dev) {
2874b83f1527SRafal Ozieblo bitnr = hash_get_index(ha->addr);
2875b83f1527SRafal Ozieblo mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2876b83f1527SRafal Ozieblo }
2877b83f1527SRafal Ozieblo
2878b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRB, mc_filter[0]);
2879b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRT, mc_filter[1]);
2880b83f1527SRafal Ozieblo }
2881b83f1527SRafal Ozieblo
2882b83f1527SRafal Ozieblo /* Enable/Disable promiscuous and multicast modes. */
macb_set_rx_mode(struct net_device * dev)2883b83f1527SRafal Ozieblo static void macb_set_rx_mode(struct net_device *dev)
2884b83f1527SRafal Ozieblo {
2885b83f1527SRafal Ozieblo unsigned long cfg;
2886b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
2887b83f1527SRafal Ozieblo
2888b83f1527SRafal Ozieblo cfg = macb_readl(bp, NCFGR);
2889b83f1527SRafal Ozieblo
2890b83f1527SRafal Ozieblo if (dev->flags & IFF_PROMISC) {
2891b83f1527SRafal Ozieblo /* Enable promiscuous mode */
2892b83f1527SRafal Ozieblo cfg |= MACB_BIT(CAF);
2893b83f1527SRafal Ozieblo
2894b83f1527SRafal Ozieblo /* Disable RX checksum offload */
2895b83f1527SRafal Ozieblo if (macb_is_gem(bp))
2896b83f1527SRafal Ozieblo cfg &= ~GEM_BIT(RXCOEN);
2897b83f1527SRafal Ozieblo } else {
2898b83f1527SRafal Ozieblo /* Disable promiscuous mode */
2899b83f1527SRafal Ozieblo cfg &= ~MACB_BIT(CAF);
2900b83f1527SRafal Ozieblo
2901b83f1527SRafal Ozieblo /* Enable RX checksum offload only if requested */
2902b83f1527SRafal Ozieblo if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2903b83f1527SRafal Ozieblo cfg |= GEM_BIT(RXCOEN);
2904b83f1527SRafal Ozieblo }
2905b83f1527SRafal Ozieblo
2906b83f1527SRafal Ozieblo if (dev->flags & IFF_ALLMULTI) {
2907b83f1527SRafal Ozieblo /* Enable all multicast mode */
2908b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRB, -1);
2909b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRT, -1);
2910b83f1527SRafal Ozieblo cfg |= MACB_BIT(NCFGR_MTI);
2911b83f1527SRafal Ozieblo } else if (!netdev_mc_empty(dev)) {
2912b83f1527SRafal Ozieblo /* Enable specific multicasts */
2913b83f1527SRafal Ozieblo macb_sethashtable(dev);
2914b83f1527SRafal Ozieblo cfg |= MACB_BIT(NCFGR_MTI);
2915b83f1527SRafal Ozieblo } else if (dev->flags & (~IFF_ALLMULTI)) {
2916b83f1527SRafal Ozieblo /* Disable all multicast mode */
2917b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRB, 0);
2918b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRT, 0);
2919b83f1527SRafal Ozieblo cfg &= ~MACB_BIT(NCFGR_MTI);
2920b83f1527SRafal Ozieblo }
2921b83f1527SRafal Ozieblo
2922b83f1527SRafal Ozieblo macb_writel(bp, NCFGR, cfg);
2923b83f1527SRafal Ozieblo }
2924b83f1527SRafal Ozieblo
macb_open(struct net_device * dev)2925b83f1527SRafal Ozieblo static int macb_open(struct net_device *dev)
2926b83f1527SRafal Ozieblo {
2927b83f1527SRafal Ozieblo size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
29287897b071SAntoine Tenart struct macb *bp = netdev_priv(dev);
2929ae1f2a56SRafal Ozieblo struct macb_queue *queue;
2930ae1f2a56SRafal Ozieblo unsigned int q;
2931b83f1527SRafal Ozieblo int err;
2932b83f1527SRafal Ozieblo
2933b83f1527SRafal Ozieblo netdev_dbg(bp->dev, "open\n");
2934b83f1527SRafal Ozieblo
2935b66bfc13SMinghao Chi err = pm_runtime_resume_and_get(&bp->pdev->dev);
2936d54f89afSHarini Katakam if (err < 0)
2937b66bfc13SMinghao Chi return err;
2938d54f89afSHarini Katakam
2939b83f1527SRafal Ozieblo /* RX buffers initialization */
2940b83f1527SRafal Ozieblo macb_init_rx_buffer_size(bp, bufsz);
2941b83f1527SRafal Ozieblo
2942b83f1527SRafal Ozieblo err = macb_alloc_consistent(bp);
2943b83f1527SRafal Ozieblo if (err) {
2944b83f1527SRafal Ozieblo netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2945b83f1527SRafal Ozieblo err);
2946d54f89afSHarini Katakam goto pm_exit;
2947b83f1527SRafal Ozieblo }
2948b83f1527SRafal Ozieblo
2949138badbcSRobert Hancock for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2950138badbcSRobert Hancock napi_enable(&queue->napi_rx);
2951138badbcSRobert Hancock napi_enable(&queue->napi_tx);
2952138badbcSRobert Hancock }
2953ae1f2a56SRafal Ozieblo
295405044531SHarini Katakam macb_init_hw(bp);
295505044531SHarini Katakam
29568b73fa3aSRobert Hancock err = phy_power_on(bp->sgmii_phy);
29577897b071SAntoine Tenart if (err)
2958faa62087SClaudiu Beznea goto reset_hw;
2959b83f1527SRafal Ozieblo
29608b73fa3aSRobert Hancock err = macb_phylink_connect(bp);
29618b73fa3aSRobert Hancock if (err)
29628b73fa3aSRobert Hancock goto phy_off;
29638b73fa3aSRobert Hancock
2964b83f1527SRafal Ozieblo netif_tx_start_all_queues(dev);
2965b83f1527SRafal Ozieblo
2966b83f1527SRafal Ozieblo if (bp->ptp_info)
2967b83f1527SRafal Ozieblo bp->ptp_info->ptp_init(dev);
2968b83f1527SRafal Ozieblo
2969939a5bf7SCharles Keepax return 0;
2970939a5bf7SCharles Keepax
29718b73fa3aSRobert Hancock phy_off:
29728b73fa3aSRobert Hancock phy_power_off(bp->sgmii_phy);
29738b73fa3aSRobert Hancock
2974faa62087SClaudiu Beznea reset_hw:
2975faa62087SClaudiu Beznea macb_reset_hw(bp);
2976138badbcSRobert Hancock for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2977138badbcSRobert Hancock napi_disable(&queue->napi_rx);
2978138badbcSRobert Hancock napi_disable(&queue->napi_tx);
2979138badbcSRobert Hancock }
2980faa62087SClaudiu Beznea macb_free_consistent(bp);
2981d54f89afSHarini Katakam pm_exit:
2982d54f89afSHarini Katakam pm_runtime_put_sync(&bp->pdev->dev);
2983d54f89afSHarini Katakam return err;
2984d54f89afSHarini Katakam }
2985b83f1527SRafal Ozieblo
macb_close(struct net_device * dev)2986b83f1527SRafal Ozieblo static int macb_close(struct net_device *dev)
2987b83f1527SRafal Ozieblo {
2988b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
2989ae1f2a56SRafal Ozieblo struct macb_queue *queue;
2990b83f1527SRafal Ozieblo unsigned long flags;
2991ae1f2a56SRafal Ozieblo unsigned int q;
2992b83f1527SRafal Ozieblo
2993b83f1527SRafal Ozieblo netif_tx_stop_all_queues(dev);
2994ae1f2a56SRafal Ozieblo
2995138badbcSRobert Hancock for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2996138badbcSRobert Hancock napi_disable(&queue->napi_rx);
2997138badbcSRobert Hancock napi_disable(&queue->napi_tx);
2998138badbcSRobert Hancock }
2999b83f1527SRafal Ozieblo
30007897b071SAntoine Tenart phylink_stop(bp->phylink);
30017897b071SAntoine Tenart phylink_disconnect_phy(bp->phylink);
3002b83f1527SRafal Ozieblo
30038b73fa3aSRobert Hancock phy_power_off(bp->sgmii_phy);
30048b73fa3aSRobert Hancock
3005b83f1527SRafal Ozieblo spin_lock_irqsave(&bp->lock, flags);
3006b83f1527SRafal Ozieblo macb_reset_hw(bp);
3007b83f1527SRafal Ozieblo netif_carrier_off(dev);
3008b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags);
3009b83f1527SRafal Ozieblo
3010b83f1527SRafal Ozieblo macb_free_consistent(bp);
3011b83f1527SRafal Ozieblo
3012b83f1527SRafal Ozieblo if (bp->ptp_info)
3013b83f1527SRafal Ozieblo bp->ptp_info->ptp_remove(dev);
3014b83f1527SRafal Ozieblo
3015d54f89afSHarini Katakam pm_runtime_put(&bp->pdev->dev);
3016d54f89afSHarini Katakam
3017b83f1527SRafal Ozieblo return 0;
3018b83f1527SRafal Ozieblo }
3019b83f1527SRafal Ozieblo
macb_change_mtu(struct net_device * dev,int new_mtu)3020b83f1527SRafal Ozieblo static int macb_change_mtu(struct net_device *dev, int new_mtu)
3021b83f1527SRafal Ozieblo {
3022b83f1527SRafal Ozieblo if (netif_running(dev))
3023b83f1527SRafal Ozieblo return -EBUSY;
3024b83f1527SRafal Ozieblo
3025*1eb2cdedSEric Dumazet WRITE_ONCE(dev->mtu, new_mtu);
3026b83f1527SRafal Ozieblo
3027b83f1527SRafal Ozieblo return 0;
3028b83f1527SRafal Ozieblo }
3029b83f1527SRafal Ozieblo
macb_set_mac_addr(struct net_device * dev,void * addr)303014ef5c39SRoman Gushchin static int macb_set_mac_addr(struct net_device *dev, void *addr)
303114ef5c39SRoman Gushchin {
303214ef5c39SRoman Gushchin int err;
303314ef5c39SRoman Gushchin
303414ef5c39SRoman Gushchin err = eth_mac_addr(dev, addr);
303514ef5c39SRoman Gushchin if (err < 0)
303614ef5c39SRoman Gushchin return err;
303714ef5c39SRoman Gushchin
303814ef5c39SRoman Gushchin macb_set_hwaddr(netdev_priv(dev));
303914ef5c39SRoman Gushchin return 0;
304014ef5c39SRoman Gushchin }
304114ef5c39SRoman Gushchin
gem_update_stats(struct macb * bp)3042b83f1527SRafal Ozieblo static void gem_update_stats(struct macb *bp)
3043b83f1527SRafal Ozieblo {
3044512286bbSRafal Ozieblo struct macb_queue *queue;
3045512286bbSRafal Ozieblo unsigned int i, q, idx;
3046512286bbSRafal Ozieblo unsigned long *stat;
3047512286bbSRafal Ozieblo
3048b83f1527SRafal Ozieblo u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
3049b83f1527SRafal Ozieblo
3050b83f1527SRafal Ozieblo for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
3051b83f1527SRafal Ozieblo u32 offset = gem_statistics[i].offset;
3052b83f1527SRafal Ozieblo u64 val = bp->macb_reg_readl(bp, offset);
3053b83f1527SRafal Ozieblo
3054b83f1527SRafal Ozieblo bp->ethtool_stats[i] += val;
3055b83f1527SRafal Ozieblo *p += val;
3056b83f1527SRafal Ozieblo
3057b83f1527SRafal Ozieblo if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
3058b83f1527SRafal Ozieblo /* Add GEM_OCTTXH, GEM_OCTRXH */
3059b83f1527SRafal Ozieblo val = bp->macb_reg_readl(bp, offset + 4);
3060b83f1527SRafal Ozieblo bp->ethtool_stats[i] += ((u64)val) << 32;
3061b83f1527SRafal Ozieblo *(++p) += val;
3062b83f1527SRafal Ozieblo }
3063b83f1527SRafal Ozieblo }
3064512286bbSRafal Ozieblo
3065512286bbSRafal Ozieblo idx = GEM_STATS_LEN;
3066512286bbSRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
3067512286bbSRafal Ozieblo for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
3068512286bbSRafal Ozieblo bp->ethtool_stats[idx++] = *stat;
3069b83f1527SRafal Ozieblo }
3070b83f1527SRafal Ozieblo
gem_get_stats(struct macb * bp)3071b83f1527SRafal Ozieblo static struct net_device_stats *gem_get_stats(struct macb *bp)
3072b83f1527SRafal Ozieblo {
3073b83f1527SRafal Ozieblo struct gem_stats *hwstat = &bp->hw_stats.gem;
3074b83f1527SRafal Ozieblo struct net_device_stats *nstat = &bp->dev->stats;
3075b83f1527SRafal Ozieblo
30765eff1461SZong Li if (!netif_running(bp->dev))
30775eff1461SZong Li return nstat;
30785eff1461SZong Li
3079b83f1527SRafal Ozieblo gem_update_stats(bp);
3080b83f1527SRafal Ozieblo
3081b83f1527SRafal Ozieblo nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
3082b83f1527SRafal Ozieblo hwstat->rx_alignment_errors +
3083b83f1527SRafal Ozieblo hwstat->rx_resource_errors +
3084b83f1527SRafal Ozieblo hwstat->rx_overruns +
3085b83f1527SRafal Ozieblo hwstat->rx_oversize_frames +
3086b83f1527SRafal Ozieblo hwstat->rx_jabbers +
3087b83f1527SRafal Ozieblo hwstat->rx_undersized_frames +
3088b83f1527SRafal Ozieblo hwstat->rx_length_field_frame_errors);
3089b83f1527SRafal Ozieblo nstat->tx_errors = (hwstat->tx_late_collisions +
3090b83f1527SRafal Ozieblo hwstat->tx_excessive_collisions +
3091b83f1527SRafal Ozieblo hwstat->tx_underrun +
3092b83f1527SRafal Ozieblo hwstat->tx_carrier_sense_errors);
3093b83f1527SRafal Ozieblo nstat->multicast = hwstat->rx_multicast_frames;
3094b83f1527SRafal Ozieblo nstat->collisions = (hwstat->tx_single_collision_frames +
3095b83f1527SRafal Ozieblo hwstat->tx_multiple_collision_frames +
3096b83f1527SRafal Ozieblo hwstat->tx_excessive_collisions);
3097b83f1527SRafal Ozieblo nstat->rx_length_errors = (hwstat->rx_oversize_frames +
3098b83f1527SRafal Ozieblo hwstat->rx_jabbers +
3099b83f1527SRafal Ozieblo hwstat->rx_undersized_frames +
3100b83f1527SRafal Ozieblo hwstat->rx_length_field_frame_errors);
3101b83f1527SRafal Ozieblo nstat->rx_over_errors = hwstat->rx_resource_errors;
3102b83f1527SRafal Ozieblo nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
3103b83f1527SRafal Ozieblo nstat->rx_frame_errors = hwstat->rx_alignment_errors;
3104b83f1527SRafal Ozieblo nstat->rx_fifo_errors = hwstat->rx_overruns;
3105b83f1527SRafal Ozieblo nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
3106b83f1527SRafal Ozieblo nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
3107b83f1527SRafal Ozieblo nstat->tx_fifo_errors = hwstat->tx_underrun;
3108b83f1527SRafal Ozieblo
3109b83f1527SRafal Ozieblo return nstat;
3110b83f1527SRafal Ozieblo }
3111b83f1527SRafal Ozieblo
gem_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)3112b83f1527SRafal Ozieblo static void gem_get_ethtool_stats(struct net_device *dev,
3113b83f1527SRafal Ozieblo struct ethtool_stats *stats, u64 *data)
3114b83f1527SRafal Ozieblo {
3115b83f1527SRafal Ozieblo struct macb *bp;
3116b83f1527SRafal Ozieblo
3117b83f1527SRafal Ozieblo bp = netdev_priv(dev);
3118b83f1527SRafal Ozieblo gem_update_stats(bp);
3119512286bbSRafal Ozieblo memcpy(data, &bp->ethtool_stats, sizeof(u64)
3120512286bbSRafal Ozieblo * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
3121b83f1527SRafal Ozieblo }
3122b83f1527SRafal Ozieblo
gem_get_sset_count(struct net_device * dev,int sset)3123b83f1527SRafal Ozieblo static int gem_get_sset_count(struct net_device *dev, int sset)
3124b83f1527SRafal Ozieblo {
3125512286bbSRafal Ozieblo struct macb *bp = netdev_priv(dev);
3126512286bbSRafal Ozieblo
3127b83f1527SRafal Ozieblo switch (sset) {
3128b83f1527SRafal Ozieblo case ETH_SS_STATS:
3129512286bbSRafal Ozieblo return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
3130b83f1527SRafal Ozieblo default:
3131b83f1527SRafal Ozieblo return -EOPNOTSUPP;
3132b83f1527SRafal Ozieblo }
3133b83f1527SRafal Ozieblo }
3134b83f1527SRafal Ozieblo
gem_get_ethtool_strings(struct net_device * dev,u32 sset,u8 * p)3135b83f1527SRafal Ozieblo static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
3136b83f1527SRafal Ozieblo {
3137512286bbSRafal Ozieblo char stat_string[ETH_GSTRING_LEN];
3138512286bbSRafal Ozieblo struct macb *bp = netdev_priv(dev);
3139512286bbSRafal Ozieblo struct macb_queue *queue;
3140b83f1527SRafal Ozieblo unsigned int i;
3141512286bbSRafal Ozieblo unsigned int q;
3142b83f1527SRafal Ozieblo
3143b83f1527SRafal Ozieblo switch (sset) {
3144b83f1527SRafal Ozieblo case ETH_SS_STATS:
3145b83f1527SRafal Ozieblo for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
3146b83f1527SRafal Ozieblo memcpy(p, gem_statistics[i].stat_string,
3147b83f1527SRafal Ozieblo ETH_GSTRING_LEN);
3148512286bbSRafal Ozieblo
3149512286bbSRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3150512286bbSRafal Ozieblo for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
3151512286bbSRafal Ozieblo snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
3152512286bbSRafal Ozieblo q, queue_statistics[i].stat_string);
3153512286bbSRafal Ozieblo memcpy(p, stat_string, ETH_GSTRING_LEN);
3154512286bbSRafal Ozieblo }
3155512286bbSRafal Ozieblo }
3156b83f1527SRafal Ozieblo break;
3157b83f1527SRafal Ozieblo }
3158b83f1527SRafal Ozieblo }
3159b83f1527SRafal Ozieblo
macb_get_stats(struct net_device * dev)3160b83f1527SRafal Ozieblo static struct net_device_stats *macb_get_stats(struct net_device *dev)
3161b83f1527SRafal Ozieblo {
3162b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
3163b83f1527SRafal Ozieblo struct net_device_stats *nstat = &bp->dev->stats;
3164b83f1527SRafal Ozieblo struct macb_stats *hwstat = &bp->hw_stats.macb;
3165b83f1527SRafal Ozieblo
3166b83f1527SRafal Ozieblo if (macb_is_gem(bp))
3167b83f1527SRafal Ozieblo return gem_get_stats(bp);
3168b83f1527SRafal Ozieblo
3169b83f1527SRafal Ozieblo /* read stats from hardware */
3170b83f1527SRafal Ozieblo macb_update_stats(bp);
3171b83f1527SRafal Ozieblo
3172b83f1527SRafal Ozieblo /* Convert HW stats into netdevice stats */
3173b83f1527SRafal Ozieblo nstat->rx_errors = (hwstat->rx_fcs_errors +
3174b83f1527SRafal Ozieblo hwstat->rx_align_errors +
3175b83f1527SRafal Ozieblo hwstat->rx_resource_errors +
3176b83f1527SRafal Ozieblo hwstat->rx_overruns +
3177b83f1527SRafal Ozieblo hwstat->rx_oversize_pkts +
3178b83f1527SRafal Ozieblo hwstat->rx_jabbers +
3179b83f1527SRafal Ozieblo hwstat->rx_undersize_pkts +
3180b83f1527SRafal Ozieblo hwstat->rx_length_mismatch);
3181b83f1527SRafal Ozieblo nstat->tx_errors = (hwstat->tx_late_cols +
3182b83f1527SRafal Ozieblo hwstat->tx_excessive_cols +
3183b83f1527SRafal Ozieblo hwstat->tx_underruns +
3184b83f1527SRafal Ozieblo hwstat->tx_carrier_errors +
3185b83f1527SRafal Ozieblo hwstat->sqe_test_errors);
3186b83f1527SRafal Ozieblo nstat->collisions = (hwstat->tx_single_cols +
3187b83f1527SRafal Ozieblo hwstat->tx_multiple_cols +
3188b83f1527SRafal Ozieblo hwstat->tx_excessive_cols);
3189b83f1527SRafal Ozieblo nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
3190b83f1527SRafal Ozieblo hwstat->rx_jabbers +
3191b83f1527SRafal Ozieblo hwstat->rx_undersize_pkts +
3192b83f1527SRafal Ozieblo hwstat->rx_length_mismatch);
3193b83f1527SRafal Ozieblo nstat->rx_over_errors = hwstat->rx_resource_errors +
3194b83f1527SRafal Ozieblo hwstat->rx_overruns;
3195b83f1527SRafal Ozieblo nstat->rx_crc_errors = hwstat->rx_fcs_errors;
3196b83f1527SRafal Ozieblo nstat->rx_frame_errors = hwstat->rx_align_errors;
3197b83f1527SRafal Ozieblo nstat->rx_fifo_errors = hwstat->rx_overruns;
3198b83f1527SRafal Ozieblo /* XXX: What does "missed" mean? */
3199b83f1527SRafal Ozieblo nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
3200b83f1527SRafal Ozieblo nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
3201b83f1527SRafal Ozieblo nstat->tx_fifo_errors = hwstat->tx_underruns;
3202b83f1527SRafal Ozieblo /* Don't know about heartbeat or window errors... */
3203b83f1527SRafal Ozieblo
3204b83f1527SRafal Ozieblo return nstat;
3205b83f1527SRafal Ozieblo }
3206b83f1527SRafal Ozieblo
macb_get_regs_len(struct net_device * netdev)3207b83f1527SRafal Ozieblo static int macb_get_regs_len(struct net_device *netdev)
3208b83f1527SRafal Ozieblo {
3209b83f1527SRafal Ozieblo return MACB_GREGS_NBR * sizeof(u32);
3210b83f1527SRafal Ozieblo }
3211b83f1527SRafal Ozieblo
macb_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)3212b83f1527SRafal Ozieblo static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3213b83f1527SRafal Ozieblo void *p)
3214b83f1527SRafal Ozieblo {
3215b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
3216b83f1527SRafal Ozieblo unsigned int tail, head;
3217b83f1527SRafal Ozieblo u32 *regs_buff = p;
3218b83f1527SRafal Ozieblo
3219b83f1527SRafal Ozieblo regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3220b83f1527SRafal Ozieblo | MACB_GREGS_VERSION;
3221b83f1527SRafal Ozieblo
3222b83f1527SRafal Ozieblo tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
3223b83f1527SRafal Ozieblo head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
3224b83f1527SRafal Ozieblo
3225b83f1527SRafal Ozieblo regs_buff[0] = macb_readl(bp, NCR);
3226b83f1527SRafal Ozieblo regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3227b83f1527SRafal Ozieblo regs_buff[2] = macb_readl(bp, NSR);
3228b83f1527SRafal Ozieblo regs_buff[3] = macb_readl(bp, TSR);
3229b83f1527SRafal Ozieblo regs_buff[4] = macb_readl(bp, RBQP);
3230b83f1527SRafal Ozieblo regs_buff[5] = macb_readl(bp, TBQP);
3231b83f1527SRafal Ozieblo regs_buff[6] = macb_readl(bp, RSR);
3232b83f1527SRafal Ozieblo regs_buff[7] = macb_readl(bp, IMR);
3233b83f1527SRafal Ozieblo
3234b83f1527SRafal Ozieblo regs_buff[8] = tail;
3235b83f1527SRafal Ozieblo regs_buff[9] = head;
3236b83f1527SRafal Ozieblo regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
3237b83f1527SRafal Ozieblo regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3238b83f1527SRafal Ozieblo
3239b83f1527SRafal Ozieblo if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3240b83f1527SRafal Ozieblo regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3241b83f1527SRafal Ozieblo if (macb_is_gem(bp))
3242b83f1527SRafal Ozieblo regs_buff[13] = gem_readl(bp, DMACFG);
3243b83f1527SRafal Ozieblo }
3244b83f1527SRafal Ozieblo
macb_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)3245b83f1527SRafal Ozieblo static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3246b83f1527SRafal Ozieblo {
3247b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3248b83f1527SRafal Ozieblo
3249253fe094SNicolas Ferre if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
32507897b071SAntoine Tenart phylink_ethtool_get_wol(bp->phylink, wol);
3251253fe094SNicolas Ferre wol->supported |= WAKE_MAGIC;
3252253fe094SNicolas Ferre
3253253fe094SNicolas Ferre if (bp->wol & MACB_WOL_ENABLED)
3254253fe094SNicolas Ferre wol->wolopts |= WAKE_MAGIC;
3255253fe094SNicolas Ferre }
3256b83f1527SRafal Ozieblo }
3257b83f1527SRafal Ozieblo
macb_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)3258b83f1527SRafal Ozieblo static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3259b83f1527SRafal Ozieblo {
3260b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev);
32617897b071SAntoine Tenart int ret;
32627897b071SAntoine Tenart
3263253fe094SNicolas Ferre /* Pass the order to phylink layer */
32647897b071SAntoine Tenart ret = phylink_ethtool_set_wol(bp->phylink, wol);
3265253fe094SNicolas Ferre /* Don't manage WoL on MAC if handled by the PHY
3266253fe094SNicolas Ferre * or if there's a failure in talking to the PHY
3267253fe094SNicolas Ferre */
3268253fe094SNicolas Ferre if (!ret || ret != -EOPNOTSUPP)
3269253fe094SNicolas Ferre return ret;
3270b83f1527SRafal Ozieblo
3271b83f1527SRafal Ozieblo if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
3272b83f1527SRafal Ozieblo (wol->wolopts & ~WAKE_MAGIC))
3273b83f1527SRafal Ozieblo return -EOPNOTSUPP;
3274b83f1527SRafal Ozieblo
3275b83f1527SRafal Ozieblo if (wol->wolopts & WAKE_MAGIC)
3276b83f1527SRafal Ozieblo bp->wol |= MACB_WOL_ENABLED;
3277b83f1527SRafal Ozieblo else
3278b83f1527SRafal Ozieblo bp->wol &= ~MACB_WOL_ENABLED;
3279b83f1527SRafal Ozieblo
3280b83f1527SRafal Ozieblo device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
3281b83f1527SRafal Ozieblo
3282b83f1527SRafal Ozieblo return 0;
3283b83f1527SRafal Ozieblo }
3284b83f1527SRafal Ozieblo
macb_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * kset)32857897b071SAntoine Tenart static int macb_get_link_ksettings(struct net_device *netdev,
32867897b071SAntoine Tenart struct ethtool_link_ksettings *kset)
32877897b071SAntoine Tenart {
32887897b071SAntoine Tenart struct macb *bp = netdev_priv(netdev);
32897897b071SAntoine Tenart
32907897b071SAntoine Tenart return phylink_ethtool_ksettings_get(bp->phylink, kset);
32917897b071SAntoine Tenart }
32927897b071SAntoine Tenart
macb_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * kset)32937897b071SAntoine Tenart static int macb_set_link_ksettings(struct net_device *netdev,
32947897b071SAntoine Tenart const struct ethtool_link_ksettings *kset)
32957897b071SAntoine Tenart {
32967897b071SAntoine Tenart struct macb *bp = netdev_priv(netdev);
32977897b071SAntoine Tenart
32987897b071SAntoine Tenart return phylink_ethtool_ksettings_set(bp->phylink, kset);
32997897b071SAntoine Tenart }
33007897b071SAntoine Tenart
macb_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)3301b83f1527SRafal Ozieblo static void macb_get_ringparam(struct net_device *netdev,
330274624944SHao Chen struct ethtool_ringparam *ring,
330374624944SHao Chen struct kernel_ethtool_ringparam *kernel_ring,
330474624944SHao Chen struct netlink_ext_ack *extack)
3305b83f1527SRafal Ozieblo {
3306b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3307b83f1527SRafal Ozieblo
3308b83f1527SRafal Ozieblo ring->rx_max_pending = MAX_RX_RING_SIZE;
3309b83f1527SRafal Ozieblo ring->tx_max_pending = MAX_TX_RING_SIZE;
3310b83f1527SRafal Ozieblo
3311b83f1527SRafal Ozieblo ring->rx_pending = bp->rx_ring_size;
3312b83f1527SRafal Ozieblo ring->tx_pending = bp->tx_ring_size;
3313b83f1527SRafal Ozieblo }
3314b83f1527SRafal Ozieblo
macb_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)3315b83f1527SRafal Ozieblo static int macb_set_ringparam(struct net_device *netdev,
331674624944SHao Chen struct ethtool_ringparam *ring,
331774624944SHao Chen struct kernel_ethtool_ringparam *kernel_ring,
331874624944SHao Chen struct netlink_ext_ack *extack)
3319b83f1527SRafal Ozieblo {
3320b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3321b83f1527SRafal Ozieblo u32 new_rx_size, new_tx_size;
3322b83f1527SRafal Ozieblo unsigned int reset = 0;
3323b83f1527SRafal Ozieblo
3324b83f1527SRafal Ozieblo if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3325b83f1527SRafal Ozieblo return -EINVAL;
3326b83f1527SRafal Ozieblo
3327b83f1527SRafal Ozieblo new_rx_size = clamp_t(u32, ring->rx_pending,
3328b83f1527SRafal Ozieblo MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3329b83f1527SRafal Ozieblo new_rx_size = roundup_pow_of_two(new_rx_size);
3330b83f1527SRafal Ozieblo
3331b83f1527SRafal Ozieblo new_tx_size = clamp_t(u32, ring->tx_pending,
3332b83f1527SRafal Ozieblo MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3333b83f1527SRafal Ozieblo new_tx_size = roundup_pow_of_two(new_tx_size);
3334b83f1527SRafal Ozieblo
3335b83f1527SRafal Ozieblo if ((new_tx_size == bp->tx_ring_size) &&
3336b83f1527SRafal Ozieblo (new_rx_size == bp->rx_ring_size)) {
3337b83f1527SRafal Ozieblo /* nothing to do */
3338b83f1527SRafal Ozieblo return 0;
3339b83f1527SRafal Ozieblo }
3340b83f1527SRafal Ozieblo
3341b83f1527SRafal Ozieblo if (netif_running(bp->dev)) {
3342b83f1527SRafal Ozieblo reset = 1;
3343b83f1527SRafal Ozieblo macb_close(bp->dev);
3344b83f1527SRafal Ozieblo }
3345b83f1527SRafal Ozieblo
3346b83f1527SRafal Ozieblo bp->rx_ring_size = new_rx_size;
3347b83f1527SRafal Ozieblo bp->tx_ring_size = new_tx_size;
3348b83f1527SRafal Ozieblo
3349b83f1527SRafal Ozieblo if (reset)
3350b83f1527SRafal Ozieblo macb_open(bp->dev);
3351b83f1527SRafal Ozieblo
3352b83f1527SRafal Ozieblo return 0;
3353b83f1527SRafal Ozieblo }
3354b83f1527SRafal Ozieblo
3355ab91f0a9SRafal Ozieblo #ifdef CONFIG_MACB_USE_HWSTAMP
gem_get_tsu_rate(struct macb * bp)3356ab91f0a9SRafal Ozieblo static unsigned int gem_get_tsu_rate(struct macb *bp)
3357ab91f0a9SRafal Ozieblo {
3358ab91f0a9SRafal Ozieblo struct clk *tsu_clk;
3359ab91f0a9SRafal Ozieblo unsigned int tsu_rate;
3360ab91f0a9SRafal Ozieblo
3361ab91f0a9SRafal Ozieblo tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3362ab91f0a9SRafal Ozieblo if (!IS_ERR(tsu_clk))
3363ab91f0a9SRafal Ozieblo tsu_rate = clk_get_rate(tsu_clk);
3364ab91f0a9SRafal Ozieblo /* try pclk instead */
3365ab91f0a9SRafal Ozieblo else if (!IS_ERR(bp->pclk)) {
3366ab91f0a9SRafal Ozieblo tsu_clk = bp->pclk;
3367ab91f0a9SRafal Ozieblo tsu_rate = clk_get_rate(tsu_clk);
3368ab91f0a9SRafal Ozieblo } else
3369ab91f0a9SRafal Ozieblo return -ENOTSUPP;
3370ab91f0a9SRafal Ozieblo return tsu_rate;
3371ab91f0a9SRafal Ozieblo }
3372ab91f0a9SRafal Ozieblo
gem_get_ptp_max_adj(void)3373ab91f0a9SRafal Ozieblo static s32 gem_get_ptp_max_adj(void)
3374ab91f0a9SRafal Ozieblo {
3375ab91f0a9SRafal Ozieblo return 64000000;
3376ab91f0a9SRafal Ozieblo }
3377ab91f0a9SRafal Ozieblo
gem_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)3378ab91f0a9SRafal Ozieblo static int gem_get_ts_info(struct net_device *dev,
3379ab91f0a9SRafal Ozieblo struct ethtool_ts_info *info)
3380ab91f0a9SRafal Ozieblo {
3381ab91f0a9SRafal Ozieblo struct macb *bp = netdev_priv(dev);
3382ab91f0a9SRafal Ozieblo
3383ab91f0a9SRafal Ozieblo if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3384ab91f0a9SRafal Ozieblo ethtool_op_get_ts_info(dev, info);
3385ab91f0a9SRafal Ozieblo return 0;
3386ab91f0a9SRafal Ozieblo }
3387ab91f0a9SRafal Ozieblo
3388ab91f0a9SRafal Ozieblo info->so_timestamping =
3389ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_TX_SOFTWARE |
3390ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_RX_SOFTWARE |
3391ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_SOFTWARE |
3392ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_TX_HARDWARE |
3393ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_RX_HARDWARE |
3394ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_RAW_HARDWARE;
3395ab91f0a9SRafal Ozieblo info->tx_types =
3396ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3397ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_TX_OFF) |
3398ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_TX_ON);
3399ab91f0a9SRafal Ozieblo info->rx_filters =
3400ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_FILTER_NONE) |
3401ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_FILTER_ALL);
3402ab91f0a9SRafal Ozieblo
3403ab91f0a9SRafal Ozieblo info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3404ab91f0a9SRafal Ozieblo
3405ab91f0a9SRafal Ozieblo return 0;
3406ab91f0a9SRafal Ozieblo }
3407ab91f0a9SRafal Ozieblo
3408ab91f0a9SRafal Ozieblo static struct macb_ptp_info gem_ptp_info = {
3409ab91f0a9SRafal Ozieblo .ptp_init = gem_ptp_init,
3410ab91f0a9SRafal Ozieblo .ptp_remove = gem_ptp_remove,
3411ab91f0a9SRafal Ozieblo .get_ptp_max_adj = gem_get_ptp_max_adj,
3412ab91f0a9SRafal Ozieblo .get_tsu_rate = gem_get_tsu_rate,
3413ab91f0a9SRafal Ozieblo .get_ts_info = gem_get_ts_info,
3414ab91f0a9SRafal Ozieblo .get_hwtst = gem_get_hwtst,
3415ab91f0a9SRafal Ozieblo .set_hwtst = gem_set_hwtst,
3416ab91f0a9SRafal Ozieblo };
3417ab91f0a9SRafal Ozieblo #endif
3418ab91f0a9SRafal Ozieblo
macb_get_ts_info(struct net_device * netdev,struct ethtool_ts_info * info)3419b83f1527SRafal Ozieblo static int macb_get_ts_info(struct net_device *netdev,
3420b83f1527SRafal Ozieblo struct ethtool_ts_info *info)
3421b83f1527SRafal Ozieblo {
3422b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3423b83f1527SRafal Ozieblo
3424b83f1527SRafal Ozieblo if (bp->ptp_info)
3425b83f1527SRafal Ozieblo return bp->ptp_info->get_ts_info(netdev, info);
3426b83f1527SRafal Ozieblo
3427b83f1527SRafal Ozieblo return ethtool_op_get_ts_info(netdev, info);
3428b83f1527SRafal Ozieblo }
3429b83f1527SRafal Ozieblo
gem_enable_flow_filters(struct macb * bp,bool enable)3430ae8223deSRafal Ozieblo static void gem_enable_flow_filters(struct macb *bp, bool enable)
3431ae8223deSRafal Ozieblo {
3432c1e85c6cSClaudiu Beznea struct net_device *netdev = bp->dev;
3433ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item;
3434ae8223deSRafal Ozieblo u32 t2_scr;
3435ae8223deSRafal Ozieblo int num_t2_scr;
3436ae8223deSRafal Ozieblo
3437c1e85c6cSClaudiu Beznea if (!(netdev->features & NETIF_F_NTUPLE))
3438c1e85c6cSClaudiu Beznea return;
3439c1e85c6cSClaudiu Beznea
3440ae8223deSRafal Ozieblo num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3441ae8223deSRafal Ozieblo
3442ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3443ae8223deSRafal Ozieblo struct ethtool_rx_flow_spec *fs = &item->fs;
3444ae8223deSRafal Ozieblo struct ethtool_tcpip4_spec *tp4sp_m;
3445ae8223deSRafal Ozieblo
3446ae8223deSRafal Ozieblo if (fs->location >= num_t2_scr)
3447ae8223deSRafal Ozieblo continue;
3448ae8223deSRafal Ozieblo
3449ae8223deSRafal Ozieblo t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3450ae8223deSRafal Ozieblo
3451ae8223deSRafal Ozieblo /* enable/disable screener regs for the flow entry */
3452ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3453ae8223deSRafal Ozieblo
3454ae8223deSRafal Ozieblo /* only enable fields with no masking */
3455ae8223deSRafal Ozieblo tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3456ae8223deSRafal Ozieblo
3457ae8223deSRafal Ozieblo if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3458ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3459ae8223deSRafal Ozieblo else
3460ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3461ae8223deSRafal Ozieblo
3462ae8223deSRafal Ozieblo if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3463ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3464ae8223deSRafal Ozieblo else
3465ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3466ae8223deSRafal Ozieblo
3467ae8223deSRafal Ozieblo if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3468ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3469ae8223deSRafal Ozieblo else
3470ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3471ae8223deSRafal Ozieblo
3472ae8223deSRafal Ozieblo gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3473ae8223deSRafal Ozieblo }
3474ae8223deSRafal Ozieblo }
3475ae8223deSRafal Ozieblo
gem_prog_cmp_regs(struct macb * bp,struct ethtool_rx_flow_spec * fs)3476ae8223deSRafal Ozieblo static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3477ae8223deSRafal Ozieblo {
3478ae8223deSRafal Ozieblo struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3479ae8223deSRafal Ozieblo uint16_t index = fs->location;
3480ae8223deSRafal Ozieblo u32 w0, w1, t2_scr;
3481ae8223deSRafal Ozieblo bool cmp_a = false;
3482ae8223deSRafal Ozieblo bool cmp_b = false;
3483ae8223deSRafal Ozieblo bool cmp_c = false;
3484ae8223deSRafal Ozieblo
3485a14d273bSClaudiu Beznea if (!macb_is_gem(bp))
3486a14d273bSClaudiu Beznea return;
3487a14d273bSClaudiu Beznea
3488ae8223deSRafal Ozieblo tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3489ae8223deSRafal Ozieblo tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3490ae8223deSRafal Ozieblo
3491ae8223deSRafal Ozieblo /* ignore field if any masking set */
3492ae8223deSRafal Ozieblo if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3493ae8223deSRafal Ozieblo /* 1st compare reg - IP source address */
3494ae8223deSRafal Ozieblo w0 = 0;
3495ae8223deSRafal Ozieblo w1 = 0;
3496ae8223deSRafal Ozieblo w0 = tp4sp_v->ip4src;
3497ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3498ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3499ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3500ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3501ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3502ae8223deSRafal Ozieblo cmp_a = true;
3503ae8223deSRafal Ozieblo }
3504ae8223deSRafal Ozieblo
3505ae8223deSRafal Ozieblo /* ignore field if any masking set */
3506ae8223deSRafal Ozieblo if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3507ae8223deSRafal Ozieblo /* 2nd compare reg - IP destination address */
3508ae8223deSRafal Ozieblo w0 = 0;
3509ae8223deSRafal Ozieblo w1 = 0;
3510ae8223deSRafal Ozieblo w0 = tp4sp_v->ip4dst;
3511ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3512ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3513ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3514ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3515ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3516ae8223deSRafal Ozieblo cmp_b = true;
3517ae8223deSRafal Ozieblo }
3518ae8223deSRafal Ozieblo
3519ae8223deSRafal Ozieblo /* ignore both port fields if masking set in both */
3520ae8223deSRafal Ozieblo if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3521ae8223deSRafal Ozieblo /* 3rd compare reg - source port, destination port */
3522ae8223deSRafal Ozieblo w0 = 0;
3523ae8223deSRafal Ozieblo w1 = 0;
3524ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3525ae8223deSRafal Ozieblo if (tp4sp_m->psrc == tp4sp_m->pdst) {
3526ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3527ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3528ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3529ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3530ae8223deSRafal Ozieblo } else {
3531ae8223deSRafal Ozieblo /* only one port definition */
3532ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3533ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3534ae8223deSRafal Ozieblo if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3535ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3536ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3537ae8223deSRafal Ozieblo } else { /* dst port */
3538ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3539ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3540ae8223deSRafal Ozieblo }
3541ae8223deSRafal Ozieblo }
3542ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3543ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3544ae8223deSRafal Ozieblo cmp_c = true;
3545ae8223deSRafal Ozieblo }
3546ae8223deSRafal Ozieblo
3547ae8223deSRafal Ozieblo t2_scr = 0;
3548ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3549ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3550ae8223deSRafal Ozieblo if (cmp_a)
3551ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3552ae8223deSRafal Ozieblo if (cmp_b)
3553ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3554ae8223deSRafal Ozieblo if (cmp_c)
3555ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3556ae8223deSRafal Ozieblo gem_writel_n(bp, SCRT2, index, t2_scr);
3557ae8223deSRafal Ozieblo }
3558ae8223deSRafal Ozieblo
gem_add_flow_filter(struct net_device * netdev,struct ethtool_rxnfc * cmd)3559ae8223deSRafal Ozieblo static int gem_add_flow_filter(struct net_device *netdev,
3560ae8223deSRafal Ozieblo struct ethtool_rxnfc *cmd)
3561ae8223deSRafal Ozieblo {
3562ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3563ae8223deSRafal Ozieblo struct ethtool_rx_flow_spec *fs = &cmd->fs;
3564ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item, *newfs;
35657038cdb7SJulia Cartwright unsigned long flags;
3566ae8223deSRafal Ozieblo int ret = -EINVAL;
3567ae8223deSRafal Ozieblo bool added = false;
3568ae8223deSRafal Ozieblo
3569cc1674eeSJulia Cartwright newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3570ae8223deSRafal Ozieblo if (newfs == NULL)
3571ae8223deSRafal Ozieblo return -ENOMEM;
3572ae8223deSRafal Ozieblo memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3573ae8223deSRafal Ozieblo
3574ae8223deSRafal Ozieblo netdev_dbg(netdev,
3575ae8223deSRafal Ozieblo "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3576ae8223deSRafal Ozieblo fs->flow_type, (int)fs->ring_cookie, fs->location,
3577ae8223deSRafal Ozieblo htonl(fs->h_u.tcp_ip4_spec.ip4src),
3578ae8223deSRafal Ozieblo htonl(fs->h_u.tcp_ip4_spec.ip4dst),
35796ee49d62SBen Dooks be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
35806ee49d62SBen Dooks be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3581ae8223deSRafal Ozieblo
35827038cdb7SJulia Cartwright spin_lock_irqsave(&bp->rx_fs_lock, flags);
35837038cdb7SJulia Cartwright
3584ae8223deSRafal Ozieblo /* find correct place to add in list */
3585ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3586ae8223deSRafal Ozieblo if (item->fs.location > newfs->fs.location) {
3587ae8223deSRafal Ozieblo list_add_tail(&newfs->list, &item->list);
3588ae8223deSRafal Ozieblo added = true;
3589ae8223deSRafal Ozieblo break;
3590ae8223deSRafal Ozieblo } else if (item->fs.location == fs->location) {
3591ae8223deSRafal Ozieblo netdev_err(netdev, "Rule not added: location %d not free!\n",
3592ae8223deSRafal Ozieblo fs->location);
3593ae8223deSRafal Ozieblo ret = -EBUSY;
3594ae8223deSRafal Ozieblo goto err;
3595ae8223deSRafal Ozieblo }
3596ae8223deSRafal Ozieblo }
3597ae8223deSRafal Ozieblo if (!added)
3598ae8223deSRafal Ozieblo list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3599ae8223deSRafal Ozieblo
3600ae8223deSRafal Ozieblo gem_prog_cmp_regs(bp, fs);
3601ae8223deSRafal Ozieblo bp->rx_fs_list.count++;
3602ae8223deSRafal Ozieblo /* enable filtering if NTUPLE on */
3603ae8223deSRafal Ozieblo gem_enable_flow_filters(bp, 1);
3604ae8223deSRafal Ozieblo
36057038cdb7SJulia Cartwright spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3606ae8223deSRafal Ozieblo return 0;
3607ae8223deSRafal Ozieblo
3608ae8223deSRafal Ozieblo err:
36097038cdb7SJulia Cartwright spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3610ae8223deSRafal Ozieblo kfree(newfs);
3611ae8223deSRafal Ozieblo return ret;
3612ae8223deSRafal Ozieblo }
3613ae8223deSRafal Ozieblo
gem_del_flow_filter(struct net_device * netdev,struct ethtool_rxnfc * cmd)3614ae8223deSRafal Ozieblo static int gem_del_flow_filter(struct net_device *netdev,
3615ae8223deSRafal Ozieblo struct ethtool_rxnfc *cmd)
3616ae8223deSRafal Ozieblo {
3617ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3618ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item;
3619ae8223deSRafal Ozieblo struct ethtool_rx_flow_spec *fs;
36207038cdb7SJulia Cartwright unsigned long flags;
36217038cdb7SJulia Cartwright
36227038cdb7SJulia Cartwright spin_lock_irqsave(&bp->rx_fs_lock, flags);
3623ae8223deSRafal Ozieblo
3624ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3625ae8223deSRafal Ozieblo if (item->fs.location == cmd->fs.location) {
3626ae8223deSRafal Ozieblo /* disable screener regs for the flow entry */
3627ae8223deSRafal Ozieblo fs = &(item->fs);
3628ae8223deSRafal Ozieblo netdev_dbg(netdev,
3629ae8223deSRafal Ozieblo "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3630ae8223deSRafal Ozieblo fs->flow_type, (int)fs->ring_cookie, fs->location,
3631ae8223deSRafal Ozieblo htonl(fs->h_u.tcp_ip4_spec.ip4src),
3632ae8223deSRafal Ozieblo htonl(fs->h_u.tcp_ip4_spec.ip4dst),
36336ee49d62SBen Dooks be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
36346ee49d62SBen Dooks be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3635ae8223deSRafal Ozieblo
3636ae8223deSRafal Ozieblo gem_writel_n(bp, SCRT2, fs->location, 0);
3637ae8223deSRafal Ozieblo
3638ae8223deSRafal Ozieblo list_del(&item->list);
3639ae8223deSRafal Ozieblo bp->rx_fs_list.count--;
36407038cdb7SJulia Cartwright spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
36417038cdb7SJulia Cartwright kfree(item);
3642ae8223deSRafal Ozieblo return 0;
3643ae8223deSRafal Ozieblo }
3644ae8223deSRafal Ozieblo }
3645ae8223deSRafal Ozieblo
36467038cdb7SJulia Cartwright spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3647ae8223deSRafal Ozieblo return -EINVAL;
3648ae8223deSRafal Ozieblo }
3649ae8223deSRafal Ozieblo
gem_get_flow_entry(struct net_device * netdev,struct ethtool_rxnfc * cmd)3650ae8223deSRafal Ozieblo static int gem_get_flow_entry(struct net_device *netdev,
3651ae8223deSRafal Ozieblo struct ethtool_rxnfc *cmd)
3652ae8223deSRafal Ozieblo {
3653ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3654ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item;
3655ae8223deSRafal Ozieblo
3656ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3657ae8223deSRafal Ozieblo if (item->fs.location == cmd->fs.location) {
3658ae8223deSRafal Ozieblo memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3659ae8223deSRafal Ozieblo return 0;
3660ae8223deSRafal Ozieblo }
3661ae8223deSRafal Ozieblo }
3662ae8223deSRafal Ozieblo return -EINVAL;
3663ae8223deSRafal Ozieblo }
3664ae8223deSRafal Ozieblo
gem_get_all_flow_entries(struct net_device * netdev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3665ae8223deSRafal Ozieblo static int gem_get_all_flow_entries(struct net_device *netdev,
3666ae8223deSRafal Ozieblo struct ethtool_rxnfc *cmd, u32 *rule_locs)
3667ae8223deSRafal Ozieblo {
3668ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3669ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item;
3670ae8223deSRafal Ozieblo uint32_t cnt = 0;
3671ae8223deSRafal Ozieblo
3672ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3673ae8223deSRafal Ozieblo if (cnt == cmd->rule_cnt)
3674ae8223deSRafal Ozieblo return -EMSGSIZE;
3675ae8223deSRafal Ozieblo rule_locs[cnt] = item->fs.location;
3676ae8223deSRafal Ozieblo cnt++;
3677ae8223deSRafal Ozieblo }
3678ae8223deSRafal Ozieblo cmd->data = bp->max_tuples;
3679ae8223deSRafal Ozieblo cmd->rule_cnt = cnt;
3680ae8223deSRafal Ozieblo
3681ae8223deSRafal Ozieblo return 0;
3682ae8223deSRafal Ozieblo }
3683ae8223deSRafal Ozieblo
gem_get_rxnfc(struct net_device * netdev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3684ae8223deSRafal Ozieblo static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3685ae8223deSRafal Ozieblo u32 *rule_locs)
3686ae8223deSRafal Ozieblo {
3687ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3688ae8223deSRafal Ozieblo int ret = 0;
3689ae8223deSRafal Ozieblo
3690ae8223deSRafal Ozieblo switch (cmd->cmd) {
3691ae8223deSRafal Ozieblo case ETHTOOL_GRXRINGS:
3692ae8223deSRafal Ozieblo cmd->data = bp->num_queues;
3693ae8223deSRafal Ozieblo break;
3694ae8223deSRafal Ozieblo case ETHTOOL_GRXCLSRLCNT:
3695ae8223deSRafal Ozieblo cmd->rule_cnt = bp->rx_fs_list.count;
3696ae8223deSRafal Ozieblo break;
3697ae8223deSRafal Ozieblo case ETHTOOL_GRXCLSRULE:
3698ae8223deSRafal Ozieblo ret = gem_get_flow_entry(netdev, cmd);
3699ae8223deSRafal Ozieblo break;
3700ae8223deSRafal Ozieblo case ETHTOOL_GRXCLSRLALL:
3701ae8223deSRafal Ozieblo ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3702ae8223deSRafal Ozieblo break;
3703ae8223deSRafal Ozieblo default:
3704ae8223deSRafal Ozieblo netdev_err(netdev,
3705ae8223deSRafal Ozieblo "Command parameter %d is not supported\n", cmd->cmd);
3706ae8223deSRafal Ozieblo ret = -EOPNOTSUPP;
3707ae8223deSRafal Ozieblo }
3708ae8223deSRafal Ozieblo
3709ae8223deSRafal Ozieblo return ret;
3710ae8223deSRafal Ozieblo }
3711ae8223deSRafal Ozieblo
gem_set_rxnfc(struct net_device * netdev,struct ethtool_rxnfc * cmd)3712ae8223deSRafal Ozieblo static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3713ae8223deSRafal Ozieblo {
3714ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3715ae8223deSRafal Ozieblo int ret;
3716ae8223deSRafal Ozieblo
3717ae8223deSRafal Ozieblo switch (cmd->cmd) {
3718ae8223deSRafal Ozieblo case ETHTOOL_SRXCLSRLINS:
3719ae8223deSRafal Ozieblo if ((cmd->fs.location >= bp->max_tuples)
3720ae8223deSRafal Ozieblo || (cmd->fs.ring_cookie >= bp->num_queues)) {
3721ae8223deSRafal Ozieblo ret = -EINVAL;
3722ae8223deSRafal Ozieblo break;
3723ae8223deSRafal Ozieblo }
3724ae8223deSRafal Ozieblo ret = gem_add_flow_filter(netdev, cmd);
3725ae8223deSRafal Ozieblo break;
3726ae8223deSRafal Ozieblo case ETHTOOL_SRXCLSRLDEL:
3727ae8223deSRafal Ozieblo ret = gem_del_flow_filter(netdev, cmd);
3728ae8223deSRafal Ozieblo break;
3729ae8223deSRafal Ozieblo default:
3730ae8223deSRafal Ozieblo netdev_err(netdev,
3731ae8223deSRafal Ozieblo "Command parameter %d is not supported\n", cmd->cmd);
3732ae8223deSRafal Ozieblo ret = -EOPNOTSUPP;
3733ae8223deSRafal Ozieblo }
3734ae8223deSRafal Ozieblo
3735ae8223deSRafal Ozieblo return ret;
3736ae8223deSRafal Ozieblo }
3737ae8223deSRafal Ozieblo
3738b83f1527SRafal Ozieblo static const struct ethtool_ops macb_ethtool_ops = {
3739b83f1527SRafal Ozieblo .get_regs_len = macb_get_regs_len,
3740b83f1527SRafal Ozieblo .get_regs = macb_get_regs,
3741b83f1527SRafal Ozieblo .get_link = ethtool_op_get_link,
3742b83f1527SRafal Ozieblo .get_ts_info = ethtool_op_get_ts_info,
3743b83f1527SRafal Ozieblo .get_wol = macb_get_wol,
3744b83f1527SRafal Ozieblo .set_wol = macb_set_wol,
37457897b071SAntoine Tenart .get_link_ksettings = macb_get_link_ksettings,
37467897b071SAntoine Tenart .set_link_ksettings = macb_set_link_ksettings,
3747b83f1527SRafal Ozieblo .get_ringparam = macb_get_ringparam,
3748b83f1527SRafal Ozieblo .set_ringparam = macb_set_ringparam,
3749b83f1527SRafal Ozieblo };
3750b83f1527SRafal Ozieblo
3751b83f1527SRafal Ozieblo static const struct ethtool_ops gem_ethtool_ops = {
3752b83f1527SRafal Ozieblo .get_regs_len = macb_get_regs_len,
3753b83f1527SRafal Ozieblo .get_regs = macb_get_regs,
3754558e35ccSNicolas Ferre .get_wol = macb_get_wol,
3755558e35ccSNicolas Ferre .set_wol = macb_set_wol,
3756b83f1527SRafal Ozieblo .get_link = ethtool_op_get_link,
3757b83f1527SRafal Ozieblo .get_ts_info = macb_get_ts_info,
3758b83f1527SRafal Ozieblo .get_ethtool_stats = gem_get_ethtool_stats,
3759b83f1527SRafal Ozieblo .get_strings = gem_get_ethtool_strings,
3760b83f1527SRafal Ozieblo .get_sset_count = gem_get_sset_count,
37617897b071SAntoine Tenart .get_link_ksettings = macb_get_link_ksettings,
37627897b071SAntoine Tenart .set_link_ksettings = macb_set_link_ksettings,
3763b83f1527SRafal Ozieblo .get_ringparam = macb_get_ringparam,
3764b83f1527SRafal Ozieblo .set_ringparam = macb_set_ringparam,
3765ae8223deSRafal Ozieblo .get_rxnfc = gem_get_rxnfc,
3766ae8223deSRafal Ozieblo .set_rxnfc = gem_set_rxnfc,
3767b83f1527SRafal Ozieblo };
3768b83f1527SRafal Ozieblo
macb_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)3769b83f1527SRafal Ozieblo static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3770b83f1527SRafal Ozieblo {
3771b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
3772b83f1527SRafal Ozieblo
3773b83f1527SRafal Ozieblo if (!netif_running(dev))
3774b83f1527SRafal Ozieblo return -EINVAL;
3775b83f1527SRafal Ozieblo
3776202cb220SKory Maincent return phylink_mii_ioctl(bp->phylink, rq, cmd);
3777b83f1527SRafal Ozieblo }
3778b83f1527SRafal Ozieblo
macb_hwtstamp_get(struct net_device * dev,struct kernel_hwtstamp_config * cfg)3779202cb220SKory Maincent static int macb_hwtstamp_get(struct net_device *dev,
3780202cb220SKory Maincent struct kernel_hwtstamp_config *cfg)
3781202cb220SKory Maincent {
3782202cb220SKory Maincent struct macb *bp = netdev_priv(dev);
3783202cb220SKory Maincent
3784202cb220SKory Maincent if (!netif_running(dev))
3785202cb220SKory Maincent return -EINVAL;
3786202cb220SKory Maincent
3787202cb220SKory Maincent if (!bp->ptp_info)
3788202cb220SKory Maincent return -EOPNOTSUPP;
3789202cb220SKory Maincent
3790202cb220SKory Maincent return bp->ptp_info->get_hwtst(dev, cfg);
3791202cb220SKory Maincent }
3792202cb220SKory Maincent
macb_hwtstamp_set(struct net_device * dev,struct kernel_hwtstamp_config * cfg,struct netlink_ext_ack * extack)3793202cb220SKory Maincent static int macb_hwtstamp_set(struct net_device *dev,
3794202cb220SKory Maincent struct kernel_hwtstamp_config *cfg,
3795202cb220SKory Maincent struct netlink_ext_ack *extack)
3796202cb220SKory Maincent {
3797202cb220SKory Maincent struct macb *bp = netdev_priv(dev);
3798202cb220SKory Maincent
3799202cb220SKory Maincent if (!netif_running(dev))
3800202cb220SKory Maincent return -EINVAL;
3801202cb220SKory Maincent
3802202cb220SKory Maincent if (!bp->ptp_info)
3803202cb220SKory Maincent return -EOPNOTSUPP;
3804202cb220SKory Maincent
3805202cb220SKory Maincent return bp->ptp_info->set_hwtst(dev, cfg, extack);
38067897b071SAntoine Tenart }
38077897b071SAntoine Tenart
macb_set_txcsum_feature(struct macb * bp,netdev_features_t features)3808c1e85c6cSClaudiu Beznea static inline void macb_set_txcsum_feature(struct macb *bp,
3809c1e85c6cSClaudiu Beznea netdev_features_t features)
3810c1e85c6cSClaudiu Beznea {
3811c1e85c6cSClaudiu Beznea u32 val;
3812c1e85c6cSClaudiu Beznea
3813c1e85c6cSClaudiu Beznea if (!macb_is_gem(bp))
3814c1e85c6cSClaudiu Beznea return;
3815c1e85c6cSClaudiu Beznea
3816c1e85c6cSClaudiu Beznea val = gem_readl(bp, DMACFG);
3817c1e85c6cSClaudiu Beznea if (features & NETIF_F_HW_CSUM)
3818c1e85c6cSClaudiu Beznea val |= GEM_BIT(TXCOEN);
3819c1e85c6cSClaudiu Beznea else
3820c1e85c6cSClaudiu Beznea val &= ~GEM_BIT(TXCOEN);
3821c1e85c6cSClaudiu Beznea
3822c1e85c6cSClaudiu Beznea gem_writel(bp, DMACFG, val);
3823c1e85c6cSClaudiu Beznea }
3824c1e85c6cSClaudiu Beznea
macb_set_rxcsum_feature(struct macb * bp,netdev_features_t features)3825c1e85c6cSClaudiu Beznea static inline void macb_set_rxcsum_feature(struct macb *bp,
3826c1e85c6cSClaudiu Beznea netdev_features_t features)
3827c1e85c6cSClaudiu Beznea {
3828c1e85c6cSClaudiu Beznea struct net_device *netdev = bp->dev;
3829c1e85c6cSClaudiu Beznea u32 val;
3830c1e85c6cSClaudiu Beznea
3831c1e85c6cSClaudiu Beznea if (!macb_is_gem(bp))
3832c1e85c6cSClaudiu Beznea return;
3833c1e85c6cSClaudiu Beznea
3834c1e85c6cSClaudiu Beznea val = gem_readl(bp, NCFGR);
3835c1e85c6cSClaudiu Beznea if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3836c1e85c6cSClaudiu Beznea val |= GEM_BIT(RXCOEN);
3837c1e85c6cSClaudiu Beznea else
3838c1e85c6cSClaudiu Beznea val &= ~GEM_BIT(RXCOEN);
3839c1e85c6cSClaudiu Beznea
3840c1e85c6cSClaudiu Beznea gem_writel(bp, NCFGR, val);
3841c1e85c6cSClaudiu Beznea }
3842c1e85c6cSClaudiu Beznea
macb_set_rxflow_feature(struct macb * bp,netdev_features_t features)3843c1e85c6cSClaudiu Beznea static inline void macb_set_rxflow_feature(struct macb *bp,
3844c1e85c6cSClaudiu Beznea netdev_features_t features)
3845c1e85c6cSClaudiu Beznea {
3846c1e85c6cSClaudiu Beznea if (!macb_is_gem(bp))
3847c1e85c6cSClaudiu Beznea return;
3848c1e85c6cSClaudiu Beznea
3849c1e85c6cSClaudiu Beznea gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3850c1e85c6cSClaudiu Beznea }
3851c1e85c6cSClaudiu Beznea
macb_set_features(struct net_device * netdev,netdev_features_t features)3852b83f1527SRafal Ozieblo static int macb_set_features(struct net_device *netdev,
3853b83f1527SRafal Ozieblo netdev_features_t features)
3854b83f1527SRafal Ozieblo {
3855b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev);
3856b83f1527SRafal Ozieblo netdev_features_t changed = features ^ netdev->features;
3857b83f1527SRafal Ozieblo
3858b83f1527SRafal Ozieblo /* TX checksum offload */
3859c1e85c6cSClaudiu Beznea if (changed & NETIF_F_HW_CSUM)
3860c1e85c6cSClaudiu Beznea macb_set_txcsum_feature(bp, features);
3861b83f1527SRafal Ozieblo
3862b83f1527SRafal Ozieblo /* RX checksum offload */
3863c1e85c6cSClaudiu Beznea if (changed & NETIF_F_RXCSUM)
3864c1e85c6cSClaudiu Beznea macb_set_rxcsum_feature(bp, features);
3865b83f1527SRafal Ozieblo
3866ae8223deSRafal Ozieblo /* RX Flow Filters */
3867c1e85c6cSClaudiu Beznea if (changed & NETIF_F_NTUPLE)
3868c1e85c6cSClaudiu Beznea macb_set_rxflow_feature(bp, features);
3869ae8223deSRafal Ozieblo
3870b83f1527SRafal Ozieblo return 0;
3871b83f1527SRafal Ozieblo }
3872b83f1527SRafal Ozieblo
macb_restore_features(struct macb * bp)3873c1e85c6cSClaudiu Beznea static void macb_restore_features(struct macb *bp)
3874c1e85c6cSClaudiu Beznea {
3875c1e85c6cSClaudiu Beznea struct net_device *netdev = bp->dev;
3876c1e85c6cSClaudiu Beznea netdev_features_t features = netdev->features;
3877a14d273bSClaudiu Beznea struct ethtool_rx_fs_item *item;
3878c1e85c6cSClaudiu Beznea
3879c1e85c6cSClaudiu Beznea /* TX checksum offload */
3880c1e85c6cSClaudiu Beznea macb_set_txcsum_feature(bp, features);
3881c1e85c6cSClaudiu Beznea
3882c1e85c6cSClaudiu Beznea /* RX checksum offload */
3883c1e85c6cSClaudiu Beznea macb_set_rxcsum_feature(bp, features);
3884c1e85c6cSClaudiu Beznea
3885c1e85c6cSClaudiu Beznea /* RX Flow Filters */
3886a14d273bSClaudiu Beznea list_for_each_entry(item, &bp->rx_fs_list.list, list)
3887a14d273bSClaudiu Beznea gem_prog_cmp_regs(bp, &item->fs);
3888a14d273bSClaudiu Beznea
3889c1e85c6cSClaudiu Beznea macb_set_rxflow_feature(bp, features);
3890c1e85c6cSClaudiu Beznea }
3891c1e85c6cSClaudiu Beznea
3892b83f1527SRafal Ozieblo static const struct net_device_ops macb_netdev_ops = {
3893b83f1527SRafal Ozieblo .ndo_open = macb_open,
3894b83f1527SRafal Ozieblo .ndo_stop = macb_close,
3895b83f1527SRafal Ozieblo .ndo_start_xmit = macb_start_xmit,
3896b83f1527SRafal Ozieblo .ndo_set_rx_mode = macb_set_rx_mode,
3897b83f1527SRafal Ozieblo .ndo_get_stats = macb_get_stats,
3898a7605370SArnd Bergmann .ndo_eth_ioctl = macb_ioctl,
3899b83f1527SRafal Ozieblo .ndo_validate_addr = eth_validate_addr,
3900b83f1527SRafal Ozieblo .ndo_change_mtu = macb_change_mtu,
390114ef5c39SRoman Gushchin .ndo_set_mac_address = macb_set_mac_addr,
3902b83f1527SRafal Ozieblo #ifdef CONFIG_NET_POLL_CONTROLLER
3903b83f1527SRafal Ozieblo .ndo_poll_controller = macb_poll_controller,
3904b83f1527SRafal Ozieblo #endif
3905b83f1527SRafal Ozieblo .ndo_set_features = macb_set_features,
3906b83f1527SRafal Ozieblo .ndo_features_check = macb_features_check,
3907202cb220SKory Maincent .ndo_hwtstamp_set = macb_hwtstamp_set,
3908202cb220SKory Maincent .ndo_hwtstamp_get = macb_hwtstamp_get,
3909b83f1527SRafal Ozieblo };
3910b83f1527SRafal Ozieblo
3911b83f1527SRafal Ozieblo /* Configure peripheral capabilities according to device tree
3912b83f1527SRafal Ozieblo * and integration options used
3913b83f1527SRafal Ozieblo */
macb_configure_caps(struct macb * bp,const struct macb_config * dt_conf)3914b83f1527SRafal Ozieblo static void macb_configure_caps(struct macb *bp,
3915b83f1527SRafal Ozieblo const struct macb_config *dt_conf)
3916b83f1527SRafal Ozieblo {
3917b83f1527SRafal Ozieblo u32 dcfg;
3918b83f1527SRafal Ozieblo
3919b83f1527SRafal Ozieblo if (dt_conf)
3920b83f1527SRafal Ozieblo bp->caps = dt_conf->caps;
3921b83f1527SRafal Ozieblo
3922b83f1527SRafal Ozieblo if (hw_is_gem(bp->regs, bp->native_io)) {
3923b83f1527SRafal Ozieblo bp->caps |= MACB_CAPS_MACB_IS_GEM;
3924b83f1527SRafal Ozieblo
3925b83f1527SRafal Ozieblo dcfg = gem_readl(bp, DCFG1);
3926b83f1527SRafal Ozieblo if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3927b83f1527SRafal Ozieblo bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3928e4e143e2SParshuram Thombare if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3929e4e143e2SParshuram Thombare bp->caps |= MACB_CAPS_PCS;
3930e4e143e2SParshuram Thombare dcfg = gem_readl(bp, DCFG12);
3931e4e143e2SParshuram Thombare if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3932e4e143e2SParshuram Thombare bp->caps |= MACB_CAPS_HIGH_SPEED;
3933b83f1527SRafal Ozieblo dcfg = gem_readl(bp, DCFG2);
3934b83f1527SRafal Ozieblo if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3935b83f1527SRafal Ozieblo bp->caps |= MACB_CAPS_FIFO_MODE;
3936ab91f0a9SRafal Ozieblo if (gem_has_ptp(bp)) {
3937b83f1527SRafal Ozieblo if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
39387897b071SAntoine Tenart dev_err(&bp->pdev->dev,
39397897b071SAntoine Tenart "GEM doesn't support hardware ptp.\n");
3940ab91f0a9SRafal Ozieblo else {
3941adee474aSHarini Katakam #ifdef CONFIG_MACB_USE_HWSTAMP
3942b83f1527SRafal Ozieblo bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3943ab91f0a9SRafal Ozieblo bp->ptp_info = &gem_ptp_info;
3944ab91f0a9SRafal Ozieblo #endif
3945ab91f0a9SRafal Ozieblo }
3946adee474aSHarini Katakam }
3947adee474aSHarini Katakam }
3948b83f1527SRafal Ozieblo
3949b83f1527SRafal Ozieblo dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3950b83f1527SRafal Ozieblo }
3951b83f1527SRafal Ozieblo
macb_probe_queues(void __iomem * mem,bool native_io,unsigned int * queue_mask,unsigned int * num_queues)3952b83f1527SRafal Ozieblo static void macb_probe_queues(void __iomem *mem,
3953b83f1527SRafal Ozieblo bool native_io,
3954b83f1527SRafal Ozieblo unsigned int *queue_mask,
3955b83f1527SRafal Ozieblo unsigned int *num_queues)
3956b83f1527SRafal Ozieblo {
3957b83f1527SRafal Ozieblo *queue_mask = 0x1;
3958b83f1527SRafal Ozieblo *num_queues = 1;
3959b83f1527SRafal Ozieblo
3960b83f1527SRafal Ozieblo /* is it macb or gem ?
3961b83f1527SRafal Ozieblo *
3962b83f1527SRafal Ozieblo * We need to read directly from the hardware here because
3963b83f1527SRafal Ozieblo * we are early in the probe process and don't have the
3964b83f1527SRafal Ozieblo * MACB_CAPS_MACB_IS_GEM flag positioned
3965b83f1527SRafal Ozieblo */
3966b83f1527SRafal Ozieblo if (!hw_is_gem(mem, native_io))
3967b83f1527SRafal Ozieblo return;
3968b83f1527SRafal Ozieblo
3969b83f1527SRafal Ozieblo /* bit 0 is never set but queue 0 always exists */
3970fec371f6SClaudiu Beznea *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3971b7ab39b3SClaudiu Beznea *num_queues = hweight32(*queue_mask);
3972b83f1527SRafal Ozieblo }
3973b83f1527SRafal Ozieblo
macb_clks_disable(struct clk * pclk,struct clk * hclk,struct clk * tx_clk,struct clk * rx_clk,struct clk * tsu_clk)397438493da4SClaudiu Beznea static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
397538493da4SClaudiu Beznea struct clk *rx_clk, struct clk *tsu_clk)
397638493da4SClaudiu Beznea {
397738493da4SClaudiu Beznea struct clk_bulk_data clks[] = {
397838493da4SClaudiu Beznea { .clk = tsu_clk, },
397938493da4SClaudiu Beznea { .clk = rx_clk, },
398038493da4SClaudiu Beznea { .clk = pclk, },
398138493da4SClaudiu Beznea { .clk = hclk, },
398238493da4SClaudiu Beznea { .clk = tx_clk },
398338493da4SClaudiu Beznea };
398438493da4SClaudiu Beznea
398538493da4SClaudiu Beznea clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
398638493da4SClaudiu Beznea }
398738493da4SClaudiu Beznea
macb_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)3988b83f1527SRafal Ozieblo static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3989b83f1527SRafal Ozieblo struct clk **hclk, struct clk **tx_clk,
3990f5473d1dSHarini Katakam struct clk **rx_clk, struct clk **tsu_clk)
3991b83f1527SRafal Ozieblo {
3992b83f1527SRafal Ozieblo struct macb_platform_data *pdata;
3993b83f1527SRafal Ozieblo int err;
3994b83f1527SRafal Ozieblo
3995b83f1527SRafal Ozieblo pdata = dev_get_platdata(&pdev->dev);
3996b83f1527SRafal Ozieblo if (pdata) {
3997b83f1527SRafal Ozieblo *pclk = pdata->pclk;
3998b83f1527SRafal Ozieblo *hclk = pdata->hclk;
3999b83f1527SRafal Ozieblo } else {
4000b83f1527SRafal Ozieblo *pclk = devm_clk_get(&pdev->dev, "pclk");
4001b83f1527SRafal Ozieblo *hclk = devm_clk_get(&pdev->dev, "hclk");
4002b83f1527SRafal Ozieblo }
4003b83f1527SRafal Ozieblo
4004a04be4b6SMichael Tretter if (IS_ERR_OR_NULL(*pclk))
4005a04be4b6SMichael Tretter return dev_err_probe(&pdev->dev,
4006a04be4b6SMichael Tretter IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
4007a04be4b6SMichael Tretter "failed to get pclk\n");
4008b83f1527SRafal Ozieblo
4009a04be4b6SMichael Tretter if (IS_ERR_OR_NULL(*hclk))
4010a04be4b6SMichael Tretter return dev_err_probe(&pdev->dev,
4011a04be4b6SMichael Tretter IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
4012a04be4b6SMichael Tretter "failed to get hclk\n");
4013b83f1527SRafal Ozieblo
4014bd310acaSMichael Tretter *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
4015b83f1527SRafal Ozieblo if (IS_ERR(*tx_clk))
4016bd310acaSMichael Tretter return PTR_ERR(*tx_clk);
4017b83f1527SRafal Ozieblo
4018bd310acaSMichael Tretter *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
4019b83f1527SRafal Ozieblo if (IS_ERR(*rx_clk))
4020bd310acaSMichael Tretter return PTR_ERR(*rx_clk);
4021b83f1527SRafal Ozieblo
4022bd310acaSMichael Tretter *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
4023f5473d1dSHarini Katakam if (IS_ERR(*tsu_clk))
4024bd310acaSMichael Tretter return PTR_ERR(*tsu_clk);
4025f5473d1dSHarini Katakam
4026b83f1527SRafal Ozieblo err = clk_prepare_enable(*pclk);
4027b83f1527SRafal Ozieblo if (err) {
4028f413cbb3SLuca Ceresoli dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4029b83f1527SRafal Ozieblo return err;
4030b83f1527SRafal Ozieblo }
4031b83f1527SRafal Ozieblo
4032b83f1527SRafal Ozieblo err = clk_prepare_enable(*hclk);
4033b83f1527SRafal Ozieblo if (err) {
4034f413cbb3SLuca Ceresoli dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
4035b83f1527SRafal Ozieblo goto err_disable_pclk;
4036b83f1527SRafal Ozieblo }
4037b83f1527SRafal Ozieblo
4038b83f1527SRafal Ozieblo err = clk_prepare_enable(*tx_clk);
4039b83f1527SRafal Ozieblo if (err) {
4040f413cbb3SLuca Ceresoli dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
4041b83f1527SRafal Ozieblo goto err_disable_hclk;
4042b83f1527SRafal Ozieblo }
4043b83f1527SRafal Ozieblo
4044b83f1527SRafal Ozieblo err = clk_prepare_enable(*rx_clk);
4045b83f1527SRafal Ozieblo if (err) {
4046f413cbb3SLuca Ceresoli dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
4047b83f1527SRafal Ozieblo goto err_disable_txclk;
4048b83f1527SRafal Ozieblo }
4049b83f1527SRafal Ozieblo
4050f5473d1dSHarini Katakam err = clk_prepare_enable(*tsu_clk);
4051f5473d1dSHarini Katakam if (err) {
4052f413cbb3SLuca Ceresoli dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
4053f5473d1dSHarini Katakam goto err_disable_rxclk;
4054f5473d1dSHarini Katakam }
4055f5473d1dSHarini Katakam
4056b83f1527SRafal Ozieblo return 0;
4057b83f1527SRafal Ozieblo
4058f5473d1dSHarini Katakam err_disable_rxclk:
4059f5473d1dSHarini Katakam clk_disable_unprepare(*rx_clk);
4060f5473d1dSHarini Katakam
4061b83f1527SRafal Ozieblo err_disable_txclk:
4062b83f1527SRafal Ozieblo clk_disable_unprepare(*tx_clk);
4063b83f1527SRafal Ozieblo
4064b83f1527SRafal Ozieblo err_disable_hclk:
4065b83f1527SRafal Ozieblo clk_disable_unprepare(*hclk);
4066b83f1527SRafal Ozieblo
4067b83f1527SRafal Ozieblo err_disable_pclk:
4068b83f1527SRafal Ozieblo clk_disable_unprepare(*pclk);
4069b83f1527SRafal Ozieblo
4070b83f1527SRafal Ozieblo return err;
4071b83f1527SRafal Ozieblo }
4072b83f1527SRafal Ozieblo
macb_init(struct platform_device * pdev)4073b83f1527SRafal Ozieblo static int macb_init(struct platform_device *pdev)
4074b83f1527SRafal Ozieblo {
4075b83f1527SRafal Ozieblo struct net_device *dev = platform_get_drvdata(pdev);
4076b83f1527SRafal Ozieblo unsigned int hw_q, q;
4077b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
4078b83f1527SRafal Ozieblo struct macb_queue *queue;
4079b83f1527SRafal Ozieblo int err;
4080ae8223deSRafal Ozieblo u32 val, reg;
4081b83f1527SRafal Ozieblo
4082b83f1527SRafal Ozieblo bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
4083b83f1527SRafal Ozieblo bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
4084b83f1527SRafal Ozieblo
4085b83f1527SRafal Ozieblo /* set the queue register mapping once for all: queue0 has a special
4086b83f1527SRafal Ozieblo * register mapping but we don't want to test the queue index then
4087b83f1527SRafal Ozieblo * compute the corresponding register offset at run time.
4088b83f1527SRafal Ozieblo */
4089b83f1527SRafal Ozieblo for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
4090b83f1527SRafal Ozieblo if (!(bp->queue_mask & (1 << hw_q)))
4091b83f1527SRafal Ozieblo continue;
4092b83f1527SRafal Ozieblo
4093b83f1527SRafal Ozieblo queue = &bp->queues[q];
4094b83f1527SRafal Ozieblo queue->bp = bp;
4095138badbcSRobert Hancock spin_lock_init(&queue->tx_ptr_lock);
4096b48b89f9SJakub Kicinski netif_napi_add(dev, &queue->napi_rx, macb_rx_poll);
4097b48b89f9SJakub Kicinski netif_napi_add(dev, &queue->napi_tx, macb_tx_poll);
4098b83f1527SRafal Ozieblo if (hw_q) {
4099b83f1527SRafal Ozieblo queue->ISR = GEM_ISR(hw_q - 1);
4100b83f1527SRafal Ozieblo queue->IER = GEM_IER(hw_q - 1);
4101b83f1527SRafal Ozieblo queue->IDR = GEM_IDR(hw_q - 1);
4102b83f1527SRafal Ozieblo queue->IMR = GEM_IMR(hw_q - 1);
4103b83f1527SRafal Ozieblo queue->TBQP = GEM_TBQP(hw_q - 1);
4104ae1f2a56SRafal Ozieblo queue->RBQP = GEM_RBQP(hw_q - 1);
4105ae1f2a56SRafal Ozieblo queue->RBQS = GEM_RBQS(hw_q - 1);
4106b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4107ae1f2a56SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4108b83f1527SRafal Ozieblo queue->TBQPH = GEM_TBQPH(hw_q - 1);
4109ae1f2a56SRafal Ozieblo queue->RBQPH = GEM_RBQPH(hw_q - 1);
4110ae1f2a56SRafal Ozieblo }
4111b83f1527SRafal Ozieblo #endif
4112b83f1527SRafal Ozieblo } else {
4113b83f1527SRafal Ozieblo /* queue0 uses legacy registers */
4114b83f1527SRafal Ozieblo queue->ISR = MACB_ISR;
4115b83f1527SRafal Ozieblo queue->IER = MACB_IER;
4116b83f1527SRafal Ozieblo queue->IDR = MACB_IDR;
4117b83f1527SRafal Ozieblo queue->IMR = MACB_IMR;
4118b83f1527SRafal Ozieblo queue->TBQP = MACB_TBQP;
4119ae1f2a56SRafal Ozieblo queue->RBQP = MACB_RBQP;
4120b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4121ae1f2a56SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4122b83f1527SRafal Ozieblo queue->TBQPH = MACB_TBQPH;
4123ae1f2a56SRafal Ozieblo queue->RBQPH = MACB_RBQPH;
4124ae1f2a56SRafal Ozieblo }
4125b83f1527SRafal Ozieblo #endif
4126b83f1527SRafal Ozieblo }
4127b83f1527SRafal Ozieblo
4128b83f1527SRafal Ozieblo /* get irq: here we use the linux queue index, not the hardware
4129b83f1527SRafal Ozieblo * queue index. the queue irq definitions in the device tree
4130b83f1527SRafal Ozieblo * must remove the optional gaps that could exist in the
4131b83f1527SRafal Ozieblo * hardware queue mask.
4132b83f1527SRafal Ozieblo */
4133b83f1527SRafal Ozieblo queue->irq = platform_get_irq(pdev, q);
4134b83f1527SRafal Ozieblo err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
4135b83f1527SRafal Ozieblo IRQF_SHARED, dev->name, queue);
4136b83f1527SRafal Ozieblo if (err) {
4137b83f1527SRafal Ozieblo dev_err(&pdev->dev,
4138b83f1527SRafal Ozieblo "Unable to request IRQ %d (error %d)\n",
4139b83f1527SRafal Ozieblo queue->irq, err);
4140b83f1527SRafal Ozieblo return err;
4141b83f1527SRafal Ozieblo }
4142b83f1527SRafal Ozieblo
4143b83f1527SRafal Ozieblo INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
4144b83f1527SRafal Ozieblo q++;
4145b83f1527SRafal Ozieblo }
4146b83f1527SRafal Ozieblo
4147b83f1527SRafal Ozieblo dev->netdev_ops = &macb_netdev_ops;
4148b83f1527SRafal Ozieblo
4149b83f1527SRafal Ozieblo /* setup appropriated routines according to adapter type */
4150b83f1527SRafal Ozieblo if (macb_is_gem(bp)) {
4151b83f1527SRafal Ozieblo bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
4152b83f1527SRafal Ozieblo bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
4153b83f1527SRafal Ozieblo bp->macbgem_ops.mog_init_rings = gem_init_rings;
4154b83f1527SRafal Ozieblo bp->macbgem_ops.mog_rx = gem_rx;
4155b83f1527SRafal Ozieblo dev->ethtool_ops = &gem_ethtool_ops;
4156b83f1527SRafal Ozieblo } else {
4157b83f1527SRafal Ozieblo bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
4158b83f1527SRafal Ozieblo bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
4159b83f1527SRafal Ozieblo bp->macbgem_ops.mog_init_rings = macb_init_rings;
4160b83f1527SRafal Ozieblo bp->macbgem_ops.mog_rx = macb_rx;
4161b83f1527SRafal Ozieblo dev->ethtool_ops = &macb_ethtool_ops;
4162b83f1527SRafal Ozieblo }
4163b83f1527SRafal Ozieblo
416414ef5c39SRoman Gushchin dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
416514ef5c39SRoman Gushchin
4166b83f1527SRafal Ozieblo /* Set features */
4167b83f1527SRafal Ozieblo dev->hw_features = NETIF_F_SG;
4168b83f1527SRafal Ozieblo
4169b83f1527SRafal Ozieblo /* Check LSO capability */
4170b83f1527SRafal Ozieblo if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
4171b83f1527SRafal Ozieblo dev->hw_features |= MACB_NETIF_LSO;
4172b83f1527SRafal Ozieblo
4173b83f1527SRafal Ozieblo /* Checksum offload is only available on gem with packet buffer */
4174b83f1527SRafal Ozieblo if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
4175b83f1527SRafal Ozieblo dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
4176b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_SG_DISABLED)
4177b83f1527SRafal Ozieblo dev->hw_features &= ~NETIF_F_SG;
4178b83f1527SRafal Ozieblo dev->features = dev->hw_features;
4179b83f1527SRafal Ozieblo
4180ae8223deSRafal Ozieblo /* Check RX Flow Filters support.
4181ae8223deSRafal Ozieblo * Max Rx flows set by availability of screeners & compare regs:
4182ae8223deSRafal Ozieblo * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
4183ae8223deSRafal Ozieblo */
4184ae8223deSRafal Ozieblo reg = gem_readl(bp, DCFG8);
4185ae8223deSRafal Ozieblo bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
4186ae8223deSRafal Ozieblo GEM_BFEXT(T2SCR, reg));
4187a714e27eSClaudiu Beznea INIT_LIST_HEAD(&bp->rx_fs_list.list);
4188ae8223deSRafal Ozieblo if (bp->max_tuples > 0) {
4189ae8223deSRafal Ozieblo /* also needs one ethtype match to check IPv4 */
4190ae8223deSRafal Ozieblo if (GEM_BFEXT(SCR2ETH, reg) > 0) {
4191ae8223deSRafal Ozieblo /* program this reg now */
4192ae8223deSRafal Ozieblo reg = 0;
4193ae8223deSRafal Ozieblo reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
4194ae8223deSRafal Ozieblo gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
4195ae8223deSRafal Ozieblo /* Filtering is supported in hw but don't enable it in kernel now */
4196ae8223deSRafal Ozieblo dev->hw_features |= NETIF_F_NTUPLE;
4197ae8223deSRafal Ozieblo /* init Rx flow definitions */
4198ae8223deSRafal Ozieblo bp->rx_fs_list.count = 0;
4199ae8223deSRafal Ozieblo spin_lock_init(&bp->rx_fs_lock);
4200ae8223deSRafal Ozieblo } else
4201ae8223deSRafal Ozieblo bp->max_tuples = 0;
4202ae8223deSRafal Ozieblo }
4203ae8223deSRafal Ozieblo
4204b83f1527SRafal Ozieblo if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
4205b83f1527SRafal Ozieblo val = 0;
42062ccb0161SAlexandre Belloni if (phy_interface_mode_is_rgmii(bp->phy_interface))
4207edac6386SClaudiu Beznea val = bp->usrio->rgmii;
4208b83f1527SRafal Ozieblo else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
4209b83f1527SRafal Ozieblo (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4210edac6386SClaudiu Beznea val = bp->usrio->rmii;
4211b83f1527SRafal Ozieblo else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4212edac6386SClaudiu Beznea val = bp->usrio->mii;
4213b83f1527SRafal Ozieblo
4214b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
4215edac6386SClaudiu Beznea val |= bp->usrio->refclk;
4216b83f1527SRafal Ozieblo
4217b83f1527SRafal Ozieblo macb_or_gem_writel(bp, USRIO, val);
4218b83f1527SRafal Ozieblo }
4219b83f1527SRafal Ozieblo
4220b83f1527SRafal Ozieblo /* Set MII management clock divider */
4221b83f1527SRafal Ozieblo val = macb_mdc_clk_div(bp);
4222b83f1527SRafal Ozieblo val |= macb_dbw(bp);
4223b83f1527SRafal Ozieblo if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
4224b83f1527SRafal Ozieblo val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
4225b83f1527SRafal Ozieblo macb_writel(bp, NCFGR, val);
4226b83f1527SRafal Ozieblo
4227b83f1527SRafal Ozieblo return 0;
4228b83f1527SRafal Ozieblo }
4229b83f1527SRafal Ozieblo
4230b1242236SAtish Patra static const struct macb_usrio_config macb_default_usrio = {
4231b1242236SAtish Patra .mii = MACB_BIT(MII),
4232b1242236SAtish Patra .rmii = MACB_BIT(RMII),
4233b1242236SAtish Patra .rgmii = GEM_BIT(RGMII),
4234b1242236SAtish Patra .refclk = MACB_BIT(CLKEN),
4235b1242236SAtish Patra };
4236b1242236SAtish Patra
4237b83f1527SRafal Ozieblo #if defined(CONFIG_OF)
4238b83f1527SRafal Ozieblo /* 1518 rounded up */
4239b83f1527SRafal Ozieblo #define AT91ETHER_MAX_RBUFF_SZ 0x600
4240b83f1527SRafal Ozieblo /* max number of receive buffers */
4241b83f1527SRafal Ozieblo #define AT91ETHER_MAX_RX_DESCR 9
4242b83f1527SRafal Ozieblo
424349db9228SArnd Bergmann static struct sifive_fu540_macb_mgmt *mgmt;
424449db9228SArnd Bergmann
at91ether_alloc_coherent(struct macb * lp)424533fdef24SClaudiu Beznea static int at91ether_alloc_coherent(struct macb *lp)
4246b83f1527SRafal Ozieblo {
4247ae1f2a56SRafal Ozieblo struct macb_queue *q = &lp->queues[0];
4248b83f1527SRafal Ozieblo
4249ae1f2a56SRafal Ozieblo q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
4250b83f1527SRafal Ozieblo (AT91ETHER_MAX_RX_DESCR *
4251b83f1527SRafal Ozieblo macb_dma_desc_get_size(lp)),
4252ae1f2a56SRafal Ozieblo &q->rx_ring_dma, GFP_KERNEL);
4253ae1f2a56SRafal Ozieblo if (!q->rx_ring)
4254b83f1527SRafal Ozieblo return -ENOMEM;
4255b83f1527SRafal Ozieblo
4256ae1f2a56SRafal Ozieblo q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
4257b83f1527SRafal Ozieblo AT91ETHER_MAX_RX_DESCR *
4258b83f1527SRafal Ozieblo AT91ETHER_MAX_RBUFF_SZ,
4259ae1f2a56SRafal Ozieblo &q->rx_buffers_dma, GFP_KERNEL);
4260ae1f2a56SRafal Ozieblo if (!q->rx_buffers) {
4261b83f1527SRafal Ozieblo dma_free_coherent(&lp->pdev->dev,
4262b83f1527SRafal Ozieblo AT91ETHER_MAX_RX_DESCR *
4263b83f1527SRafal Ozieblo macb_dma_desc_get_size(lp),
4264ae1f2a56SRafal Ozieblo q->rx_ring, q->rx_ring_dma);
4265ae1f2a56SRafal Ozieblo q->rx_ring = NULL;
4266b83f1527SRafal Ozieblo return -ENOMEM;
4267b83f1527SRafal Ozieblo }
4268b83f1527SRafal Ozieblo
426933fdef24SClaudiu Beznea return 0;
427033fdef24SClaudiu Beznea }
427133fdef24SClaudiu Beznea
at91ether_free_coherent(struct macb * lp)427233fdef24SClaudiu Beznea static void at91ether_free_coherent(struct macb *lp)
427333fdef24SClaudiu Beznea {
427433fdef24SClaudiu Beznea struct macb_queue *q = &lp->queues[0];
427533fdef24SClaudiu Beznea
427633fdef24SClaudiu Beznea if (q->rx_ring) {
427733fdef24SClaudiu Beznea dma_free_coherent(&lp->pdev->dev,
427833fdef24SClaudiu Beznea AT91ETHER_MAX_RX_DESCR *
427933fdef24SClaudiu Beznea macb_dma_desc_get_size(lp),
428033fdef24SClaudiu Beznea q->rx_ring, q->rx_ring_dma);
428133fdef24SClaudiu Beznea q->rx_ring = NULL;
428233fdef24SClaudiu Beznea }
428333fdef24SClaudiu Beznea
428433fdef24SClaudiu Beznea if (q->rx_buffers) {
428533fdef24SClaudiu Beznea dma_free_coherent(&lp->pdev->dev,
428633fdef24SClaudiu Beznea AT91ETHER_MAX_RX_DESCR *
428733fdef24SClaudiu Beznea AT91ETHER_MAX_RBUFF_SZ,
428833fdef24SClaudiu Beznea q->rx_buffers, q->rx_buffers_dma);
428933fdef24SClaudiu Beznea q->rx_buffers = NULL;
429033fdef24SClaudiu Beznea }
429133fdef24SClaudiu Beznea }
429233fdef24SClaudiu Beznea
429333fdef24SClaudiu Beznea /* Initialize and start the Receiver and Transmit subsystems */
at91ether_start(struct macb * lp)429433fdef24SClaudiu Beznea static int at91ether_start(struct macb *lp)
429533fdef24SClaudiu Beznea {
429633fdef24SClaudiu Beznea struct macb_queue *q = &lp->queues[0];
429733fdef24SClaudiu Beznea struct macb_dma_desc *desc;
429833fdef24SClaudiu Beznea dma_addr_t addr;
429933fdef24SClaudiu Beznea u32 ctl;
430033fdef24SClaudiu Beznea int i, ret;
430133fdef24SClaudiu Beznea
430233fdef24SClaudiu Beznea ret = at91ether_alloc_coherent(lp);
430333fdef24SClaudiu Beznea if (ret)
430433fdef24SClaudiu Beznea return ret;
430533fdef24SClaudiu Beznea
4306ae1f2a56SRafal Ozieblo addr = q->rx_buffers_dma;
4307b83f1527SRafal Ozieblo for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4308ae1f2a56SRafal Ozieblo desc = macb_rx_desc(q, i);
4309b83f1527SRafal Ozieblo macb_set_addr(lp, desc, addr);
4310b83f1527SRafal Ozieblo desc->ctrl = 0;
4311b83f1527SRafal Ozieblo addr += AT91ETHER_MAX_RBUFF_SZ;
4312b83f1527SRafal Ozieblo }
4313b83f1527SRafal Ozieblo
4314b83f1527SRafal Ozieblo /* Set the Wrap bit on the last descriptor */
4315b83f1527SRafal Ozieblo desc->addr |= MACB_BIT(RX_WRAP);
4316b83f1527SRafal Ozieblo
4317b83f1527SRafal Ozieblo /* Reset buffer index */
4318ae1f2a56SRafal Ozieblo q->rx_tail = 0;
4319b83f1527SRafal Ozieblo
4320b83f1527SRafal Ozieblo /* Program address of descriptor list in Rx Buffer Queue register */
4321ae1f2a56SRafal Ozieblo macb_writel(lp, RBQP, q->rx_ring_dma);
4322b83f1527SRafal Ozieblo
4323b83f1527SRafal Ozieblo /* Enable Receive and Transmit */
4324b83f1527SRafal Ozieblo ctl = macb_readl(lp, NCR);
4325b83f1527SRafal Ozieblo macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4326b83f1527SRafal Ozieblo
432733fdef24SClaudiu Beznea /* Enable MAC interrupts */
432833fdef24SClaudiu Beznea macb_writel(lp, IER, MACB_BIT(RCOMP) |
432933fdef24SClaudiu Beznea MACB_BIT(RXUBR) |
433033fdef24SClaudiu Beznea MACB_BIT(ISR_TUND) |
433133fdef24SClaudiu Beznea MACB_BIT(ISR_RLE) |
433233fdef24SClaudiu Beznea MACB_BIT(TCOMP) |
433333fdef24SClaudiu Beznea MACB_BIT(ISR_ROVR) |
433433fdef24SClaudiu Beznea MACB_BIT(HRESP));
433533fdef24SClaudiu Beznea
4336b83f1527SRafal Ozieblo return 0;
4337b83f1527SRafal Ozieblo }
4338b83f1527SRafal Ozieblo
at91ether_stop(struct macb * lp)433933fdef24SClaudiu Beznea static void at91ether_stop(struct macb *lp)
434033fdef24SClaudiu Beznea {
434133fdef24SClaudiu Beznea u32 ctl;
434233fdef24SClaudiu Beznea
434333fdef24SClaudiu Beznea /* Disable MAC interrupts */
434433fdef24SClaudiu Beznea macb_writel(lp, IDR, MACB_BIT(RCOMP) |
434533fdef24SClaudiu Beznea MACB_BIT(RXUBR) |
434633fdef24SClaudiu Beznea MACB_BIT(ISR_TUND) |
434733fdef24SClaudiu Beznea MACB_BIT(ISR_RLE) |
434833fdef24SClaudiu Beznea MACB_BIT(TCOMP) |
434933fdef24SClaudiu Beznea MACB_BIT(ISR_ROVR) |
435033fdef24SClaudiu Beznea MACB_BIT(HRESP));
435133fdef24SClaudiu Beznea
435233fdef24SClaudiu Beznea /* Disable Receiver and Transmitter */
435333fdef24SClaudiu Beznea ctl = macb_readl(lp, NCR);
435433fdef24SClaudiu Beznea macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
435533fdef24SClaudiu Beznea
435633fdef24SClaudiu Beznea /* Free resources. */
435733fdef24SClaudiu Beznea at91ether_free_coherent(lp);
435833fdef24SClaudiu Beznea }
435933fdef24SClaudiu Beznea
4360b83f1527SRafal Ozieblo /* Open the ethernet interface */
at91ether_open(struct net_device * dev)4361b83f1527SRafal Ozieblo static int at91ether_open(struct net_device *dev)
4362b83f1527SRafal Ozieblo {
4363b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev);
4364b83f1527SRafal Ozieblo u32 ctl;
4365b83f1527SRafal Ozieblo int ret;
4366b83f1527SRafal Ozieblo
4367b66bfc13SMinghao Chi ret = pm_runtime_resume_and_get(&lp->pdev->dev);
4368b66bfc13SMinghao Chi if (ret < 0)
4369e6a41c23SAlexandre Belloni return ret;
4370e6a41c23SAlexandre Belloni
4371b83f1527SRafal Ozieblo /* Clear internal statistics */
4372b83f1527SRafal Ozieblo ctl = macb_readl(lp, NCR);
4373b83f1527SRafal Ozieblo macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4374b83f1527SRafal Ozieblo
4375b83f1527SRafal Ozieblo macb_set_hwaddr(lp);
4376b83f1527SRafal Ozieblo
437733fdef24SClaudiu Beznea ret = at91ether_start(lp);
4378b83f1527SRafal Ozieblo if (ret)
43790eaf228dSClaudiu Beznea goto pm_exit;
4380b83f1527SRafal Ozieblo
43817897b071SAntoine Tenart ret = macb_phylink_connect(lp);
43827897b071SAntoine Tenart if (ret)
438333fdef24SClaudiu Beznea goto stop;
4384b83f1527SRafal Ozieblo
4385b83f1527SRafal Ozieblo netif_start_queue(dev);
4386b83f1527SRafal Ozieblo
4387b83f1527SRafal Ozieblo return 0;
43880eaf228dSClaudiu Beznea
438933fdef24SClaudiu Beznea stop:
439033fdef24SClaudiu Beznea at91ether_stop(lp);
43910eaf228dSClaudiu Beznea pm_exit:
43920eaf228dSClaudiu Beznea pm_runtime_put_sync(&lp->pdev->dev);
43930eaf228dSClaudiu Beznea return ret;
4394b83f1527SRafal Ozieblo }
4395b83f1527SRafal Ozieblo
4396b83f1527SRafal Ozieblo /* Close the interface */
at91ether_close(struct net_device * dev)4397b83f1527SRafal Ozieblo static int at91ether_close(struct net_device *dev)
4398b83f1527SRafal Ozieblo {
4399b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev);
4400b83f1527SRafal Ozieblo
4401b83f1527SRafal Ozieblo netif_stop_queue(dev);
4402b83f1527SRafal Ozieblo
44037897b071SAntoine Tenart phylink_stop(lp->phylink);
44047897b071SAntoine Tenart phylink_disconnect_phy(lp->phylink);
44057897b071SAntoine Tenart
440633fdef24SClaudiu Beznea at91ether_stop(lp);
4407b83f1527SRafal Ozieblo
4408e6a41c23SAlexandre Belloni return pm_runtime_put(&lp->pdev->dev);
4409b83f1527SRafal Ozieblo }
4410b83f1527SRafal Ozieblo
4411b83f1527SRafal Ozieblo /* Transmit packet */
at91ether_start_xmit(struct sk_buff * skb,struct net_device * dev)4412d1c38957SClaudiu Beznea static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4413d1c38957SClaudiu Beznea struct net_device *dev)
4414b83f1527SRafal Ozieblo {
4415b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev);
4416b83f1527SRafal Ozieblo
44171d608d2eSWilly Tarreau if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
44181d608d2eSWilly Tarreau int desc = 0;
44191d608d2eSWilly Tarreau
44201d608d2eSWilly Tarreau netif_stop_queue(dev);
4421b83f1527SRafal Ozieblo
4422b83f1527SRafal Ozieblo /* Store packet information (to free when Tx completed) */
442373d74228SWilly Tarreau lp->rm9200_txq[desc].skb = skb;
442473d74228SWilly Tarreau lp->rm9200_txq[desc].size = skb->len;
442573d74228SWilly Tarreau lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4426564923e4SChristoph Hellwig skb->len, DMA_TO_DEVICE);
442773d74228SWilly Tarreau if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4428b83f1527SRafal Ozieblo dev_kfree_skb_any(skb);
4429b83f1527SRafal Ozieblo dev->stats.tx_dropped++;
4430b83f1527SRafal Ozieblo netdev_err(dev, "%s: DMA mapping error\n", __func__);
4431b83f1527SRafal Ozieblo return NETDEV_TX_OK;
4432b83f1527SRafal Ozieblo }
4433b83f1527SRafal Ozieblo
4434b83f1527SRafal Ozieblo /* Set address of the data in the Transmit Address register */
443573d74228SWilly Tarreau macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4436b83f1527SRafal Ozieblo /* Set length of the packet in the Transmit Control register */
4437b83f1527SRafal Ozieblo macb_writel(lp, TCR, skb->len);
4438b83f1527SRafal Ozieblo
4439b83f1527SRafal Ozieblo } else {
4440b83f1527SRafal Ozieblo netdev_err(dev, "%s called, but device is busy!\n", __func__);
4441b83f1527SRafal Ozieblo return NETDEV_TX_BUSY;
4442b83f1527SRafal Ozieblo }
4443b83f1527SRafal Ozieblo
4444b83f1527SRafal Ozieblo return NETDEV_TX_OK;
4445b83f1527SRafal Ozieblo }
4446b83f1527SRafal Ozieblo
4447b83f1527SRafal Ozieblo /* Extract received frame from buffer descriptors and sent to upper layers.
4448b83f1527SRafal Ozieblo * (Called from interrupt context)
4449b83f1527SRafal Ozieblo */
at91ether_rx(struct net_device * dev)4450b83f1527SRafal Ozieblo static void at91ether_rx(struct net_device *dev)
4451b83f1527SRafal Ozieblo {
4452b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev);
4453ae1f2a56SRafal Ozieblo struct macb_queue *q = &lp->queues[0];
4454b83f1527SRafal Ozieblo struct macb_dma_desc *desc;
4455b83f1527SRafal Ozieblo unsigned char *p_recv;
4456b83f1527SRafal Ozieblo struct sk_buff *skb;
4457b83f1527SRafal Ozieblo unsigned int pktlen;
4458b83f1527SRafal Ozieblo
4459ae1f2a56SRafal Ozieblo desc = macb_rx_desc(q, q->rx_tail);
4460b83f1527SRafal Ozieblo while (desc->addr & MACB_BIT(RX_USED)) {
4461ae1f2a56SRafal Ozieblo p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4462b83f1527SRafal Ozieblo pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4463b83f1527SRafal Ozieblo skb = netdev_alloc_skb(dev, pktlen + 2);
4464b83f1527SRafal Ozieblo if (skb) {
4465b83f1527SRafal Ozieblo skb_reserve(skb, 2);
4466b83f1527SRafal Ozieblo skb_put_data(skb, p_recv, pktlen);
4467b83f1527SRafal Ozieblo
4468b83f1527SRafal Ozieblo skb->protocol = eth_type_trans(skb, dev);
4469b83f1527SRafal Ozieblo dev->stats.rx_packets++;
4470b83f1527SRafal Ozieblo dev->stats.rx_bytes += pktlen;
4471b83f1527SRafal Ozieblo netif_rx(skb);
4472b83f1527SRafal Ozieblo } else {
4473b83f1527SRafal Ozieblo dev->stats.rx_dropped++;
4474b83f1527SRafal Ozieblo }
4475b83f1527SRafal Ozieblo
4476b83f1527SRafal Ozieblo if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4477b83f1527SRafal Ozieblo dev->stats.multicast++;
4478b83f1527SRafal Ozieblo
4479b83f1527SRafal Ozieblo /* reset ownership bit */
4480b83f1527SRafal Ozieblo desc->addr &= ~MACB_BIT(RX_USED);
4481b83f1527SRafal Ozieblo
4482b83f1527SRafal Ozieblo /* wrap after last buffer */
4483ae1f2a56SRafal Ozieblo if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4484ae1f2a56SRafal Ozieblo q->rx_tail = 0;
4485b83f1527SRafal Ozieblo else
4486ae1f2a56SRafal Ozieblo q->rx_tail++;
4487b83f1527SRafal Ozieblo
4488ae1f2a56SRafal Ozieblo desc = macb_rx_desc(q, q->rx_tail);
4489b83f1527SRafal Ozieblo }
4490b83f1527SRafal Ozieblo }
4491b83f1527SRafal Ozieblo
4492b83f1527SRafal Ozieblo /* MAC interrupt handler */
at91ether_interrupt(int irq,void * dev_id)4493b83f1527SRafal Ozieblo static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4494b83f1527SRafal Ozieblo {
4495b83f1527SRafal Ozieblo struct net_device *dev = dev_id;
4496b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev);
4497b83f1527SRafal Ozieblo u32 intstatus, ctl;
449873d74228SWilly Tarreau unsigned int desc;
4499b83f1527SRafal Ozieblo
4500b83f1527SRafal Ozieblo /* MAC Interrupt Status register indicates what interrupts are pending.
4501b83f1527SRafal Ozieblo * It is automatically cleared once read.
4502b83f1527SRafal Ozieblo */
4503b83f1527SRafal Ozieblo intstatus = macb_readl(lp, ISR);
4504b83f1527SRafal Ozieblo
4505b83f1527SRafal Ozieblo /* Receive complete */
4506b83f1527SRafal Ozieblo if (intstatus & MACB_BIT(RCOMP))
4507b83f1527SRafal Ozieblo at91ether_rx(dev);
4508b83f1527SRafal Ozieblo
4509b83f1527SRafal Ozieblo /* Transmit complete */
45101d608d2eSWilly Tarreau if (intstatus & MACB_BIT(TCOMP)) {
4511b83f1527SRafal Ozieblo /* The TCOM bit is set even if the transmission failed */
4512b83f1527SRafal Ozieblo if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4513b83f1527SRafal Ozieblo dev->stats.tx_errors++;
4514b83f1527SRafal Ozieblo
45151d608d2eSWilly Tarreau desc = 0;
45161d608d2eSWilly Tarreau if (lp->rm9200_txq[desc].skb) {
451773d74228SWilly Tarreau dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
451873d74228SWilly Tarreau lp->rm9200_txq[desc].skb = NULL;
451973d74228SWilly Tarreau dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
452073d74228SWilly Tarreau lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4521b83f1527SRafal Ozieblo dev->stats.tx_packets++;
452273d74228SWilly Tarreau dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4523b83f1527SRafal Ozieblo }
4524b83f1527SRafal Ozieblo netif_wake_queue(dev);
4525b83f1527SRafal Ozieblo }
4526b83f1527SRafal Ozieblo
4527b83f1527SRafal Ozieblo /* Work-around for EMAC Errata section 41.3.1 */
4528b83f1527SRafal Ozieblo if (intstatus & MACB_BIT(RXUBR)) {
4529b83f1527SRafal Ozieblo ctl = macb_readl(lp, NCR);
4530b83f1527SRafal Ozieblo macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4531b83f1527SRafal Ozieblo wmb();
4532b83f1527SRafal Ozieblo macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4533b83f1527SRafal Ozieblo }
4534b83f1527SRafal Ozieblo
4535b83f1527SRafal Ozieblo if (intstatus & MACB_BIT(ISR_ROVR))
4536b83f1527SRafal Ozieblo netdev_err(dev, "ROVR error\n");
4537b83f1527SRafal Ozieblo
4538b83f1527SRafal Ozieblo return IRQ_HANDLED;
4539b83f1527SRafal Ozieblo }
4540b83f1527SRafal Ozieblo
4541b83f1527SRafal Ozieblo #ifdef CONFIG_NET_POLL_CONTROLLER
at91ether_poll_controller(struct net_device * dev)4542b83f1527SRafal Ozieblo static void at91ether_poll_controller(struct net_device *dev)
4543b83f1527SRafal Ozieblo {
4544b83f1527SRafal Ozieblo unsigned long flags;
4545b83f1527SRafal Ozieblo
4546b83f1527SRafal Ozieblo local_irq_save(flags);
4547b83f1527SRafal Ozieblo at91ether_interrupt(dev->irq, dev);
4548b83f1527SRafal Ozieblo local_irq_restore(flags);
4549b83f1527SRafal Ozieblo }
4550b83f1527SRafal Ozieblo #endif
4551b83f1527SRafal Ozieblo
4552b83f1527SRafal Ozieblo static const struct net_device_ops at91ether_netdev_ops = {
4553b83f1527SRafal Ozieblo .ndo_open = at91ether_open,
4554b83f1527SRafal Ozieblo .ndo_stop = at91ether_close,
4555b83f1527SRafal Ozieblo .ndo_start_xmit = at91ether_start_xmit,
4556b83f1527SRafal Ozieblo .ndo_get_stats = macb_get_stats,
4557b83f1527SRafal Ozieblo .ndo_set_rx_mode = macb_set_rx_mode,
4558b83f1527SRafal Ozieblo .ndo_set_mac_address = eth_mac_addr,
4559a7605370SArnd Bergmann .ndo_eth_ioctl = macb_ioctl,
4560b83f1527SRafal Ozieblo .ndo_validate_addr = eth_validate_addr,
4561b83f1527SRafal Ozieblo #ifdef CONFIG_NET_POLL_CONTROLLER
4562b83f1527SRafal Ozieblo .ndo_poll_controller = at91ether_poll_controller,
4563b83f1527SRafal Ozieblo #endif
4564202cb220SKory Maincent .ndo_hwtstamp_set = macb_hwtstamp_set,
4565202cb220SKory Maincent .ndo_hwtstamp_get = macb_hwtstamp_get,
4566b83f1527SRafal Ozieblo };
4567b83f1527SRafal Ozieblo
at91ether_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4568b83f1527SRafal Ozieblo static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4569b83f1527SRafal Ozieblo struct clk **hclk, struct clk **tx_clk,
4570f5473d1dSHarini Katakam struct clk **rx_clk, struct clk **tsu_clk)
4571b83f1527SRafal Ozieblo {
4572b83f1527SRafal Ozieblo int err;
4573b83f1527SRafal Ozieblo
4574b83f1527SRafal Ozieblo *hclk = NULL;
4575b83f1527SRafal Ozieblo *tx_clk = NULL;
4576b83f1527SRafal Ozieblo *rx_clk = NULL;
4577f5473d1dSHarini Katakam *tsu_clk = NULL;
4578b83f1527SRafal Ozieblo
4579b83f1527SRafal Ozieblo *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4580b83f1527SRafal Ozieblo if (IS_ERR(*pclk))
4581b83f1527SRafal Ozieblo return PTR_ERR(*pclk);
4582b83f1527SRafal Ozieblo
4583b83f1527SRafal Ozieblo err = clk_prepare_enable(*pclk);
4584b83f1527SRafal Ozieblo if (err) {
4585f413cbb3SLuca Ceresoli dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4586b83f1527SRafal Ozieblo return err;
4587b83f1527SRafal Ozieblo }
4588b83f1527SRafal Ozieblo
4589b83f1527SRafal Ozieblo return 0;
4590b83f1527SRafal Ozieblo }
4591b83f1527SRafal Ozieblo
at91ether_init(struct platform_device * pdev)4592b83f1527SRafal Ozieblo static int at91ether_init(struct platform_device *pdev)
4593b83f1527SRafal Ozieblo {
4594b83f1527SRafal Ozieblo struct net_device *dev = platform_get_drvdata(pdev);
4595b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev);
4596b83f1527SRafal Ozieblo int err;
4597b83f1527SRafal Ozieblo
4598fec9d3b1SAlexandre Belloni bp->queues[0].bp = bp;
4599fec9d3b1SAlexandre Belloni
4600b83f1527SRafal Ozieblo dev->netdev_ops = &at91ether_netdev_ops;
4601b83f1527SRafal Ozieblo dev->ethtool_ops = &macb_ethtool_ops;
4602b83f1527SRafal Ozieblo
4603b83f1527SRafal Ozieblo err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4604b83f1527SRafal Ozieblo 0, dev->name, dev);
4605b83f1527SRafal Ozieblo if (err)
4606b83f1527SRafal Ozieblo return err;
4607b83f1527SRafal Ozieblo
4608b83f1527SRafal Ozieblo macb_writel(bp, NCR, 0);
4609b83f1527SRafal Ozieblo
4610ac2fcfa9SAlexandre Belloni macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4611b83f1527SRafal Ozieblo
4612b83f1527SRafal Ozieblo return 0;
4613b83f1527SRafal Ozieblo }
4614b83f1527SRafal Ozieblo
fu540_macb_tx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)4615c218ad55SYash Shah static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4616c218ad55SYash Shah unsigned long parent_rate)
4617c218ad55SYash Shah {
4618c218ad55SYash Shah return mgmt->rate;
4619c218ad55SYash Shah }
4620c218ad55SYash Shah
fu540_macb_tx_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)4621c218ad55SYash Shah static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4622c218ad55SYash Shah unsigned long *parent_rate)
4623c218ad55SYash Shah {
4624c218ad55SYash Shah if (WARN_ON(rate < 2500000))
4625c218ad55SYash Shah return 2500000;
4626c218ad55SYash Shah else if (rate == 2500000)
4627c218ad55SYash Shah return 2500000;
4628c218ad55SYash Shah else if (WARN_ON(rate < 13750000))
4629c218ad55SYash Shah return 2500000;
4630c218ad55SYash Shah else if (WARN_ON(rate < 25000000))
4631c218ad55SYash Shah return 25000000;
4632c218ad55SYash Shah else if (rate == 25000000)
4633c218ad55SYash Shah return 25000000;
4634c218ad55SYash Shah else if (WARN_ON(rate < 75000000))
4635c218ad55SYash Shah return 25000000;
4636c218ad55SYash Shah else if (WARN_ON(rate < 125000000))
4637c218ad55SYash Shah return 125000000;
4638c218ad55SYash Shah else if (rate == 125000000)
4639c218ad55SYash Shah return 125000000;
4640c218ad55SYash Shah
4641c218ad55SYash Shah WARN_ON(rate > 125000000);
4642c218ad55SYash Shah
4643c218ad55SYash Shah return 125000000;
4644c218ad55SYash Shah }
4645c218ad55SYash Shah
fu540_macb_tx_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)4646c218ad55SYash Shah static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4647c218ad55SYash Shah unsigned long parent_rate)
4648c218ad55SYash Shah {
4649c218ad55SYash Shah rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4650c218ad55SYash Shah if (rate != 125000000)
4651c218ad55SYash Shah iowrite32(1, mgmt->reg);
4652c218ad55SYash Shah else
4653c218ad55SYash Shah iowrite32(0, mgmt->reg);
4654c218ad55SYash Shah mgmt->rate = rate;
4655c218ad55SYash Shah
4656c218ad55SYash Shah return 0;
4657c218ad55SYash Shah }
4658c218ad55SYash Shah
4659c218ad55SYash Shah static const struct clk_ops fu540_c000_ops = {
4660c218ad55SYash Shah .recalc_rate = fu540_macb_tx_recalc_rate,
4661c218ad55SYash Shah .round_rate = fu540_macb_tx_round_rate,
4662c218ad55SYash Shah .set_rate = fu540_macb_tx_set_rate,
4663c218ad55SYash Shah };
4664c218ad55SYash Shah
fu540_c000_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4665c218ad55SYash Shah static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4666c218ad55SYash Shah struct clk **hclk, struct clk **tx_clk,
4667c218ad55SYash Shah struct clk **rx_clk, struct clk **tsu_clk)
4668c218ad55SYash Shah {
4669c218ad55SYash Shah struct clk_init_data init;
4670c218ad55SYash Shah int err = 0;
4671c218ad55SYash Shah
4672c218ad55SYash Shah err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4673c218ad55SYash Shah if (err)
4674c218ad55SYash Shah return err;
4675c218ad55SYash Shah
4676c218ad55SYash Shah mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4677f4de93f0SClaudiu Beznea if (!mgmt) {
4678f4de93f0SClaudiu Beznea err = -ENOMEM;
4679f4de93f0SClaudiu Beznea goto err_disable_clks;
4680f4de93f0SClaudiu Beznea }
4681c218ad55SYash Shah
4682c218ad55SYash Shah init.name = "sifive-gemgxl-mgmt";
4683c218ad55SYash Shah init.ops = &fu540_c000_ops;
4684c218ad55SYash Shah init.flags = 0;
4685c218ad55SYash Shah init.num_parents = 0;
4686c218ad55SYash Shah
4687c218ad55SYash Shah mgmt->rate = 0;
4688c218ad55SYash Shah mgmt->hw.init = &init;
4689c218ad55SYash Shah
4690d89091a4SStephen Boyd *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4691f4de93f0SClaudiu Beznea if (IS_ERR(*tx_clk)) {
4692f4de93f0SClaudiu Beznea err = PTR_ERR(*tx_clk);
4693f4de93f0SClaudiu Beznea goto err_disable_clks;
4694f4de93f0SClaudiu Beznea }
4695c218ad55SYash Shah
4696c218ad55SYash Shah err = clk_prepare_enable(*tx_clk);
4697f4de93f0SClaudiu Beznea if (err) {
4698c218ad55SYash Shah dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4699f4de93f0SClaudiu Beznea *tx_clk = NULL;
4700f4de93f0SClaudiu Beznea goto err_disable_clks;
4701f4de93f0SClaudiu Beznea } else {
4702c218ad55SYash Shah dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4703f4de93f0SClaudiu Beznea }
4704c218ad55SYash Shah
4705c218ad55SYash Shah return 0;
4706f4de93f0SClaudiu Beznea
4707f4de93f0SClaudiu Beznea err_disable_clks:
4708f4de93f0SClaudiu Beznea macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4709f4de93f0SClaudiu Beznea
4710f4de93f0SClaudiu Beznea return err;
4711c218ad55SYash Shah }
4712c218ad55SYash Shah
fu540_c000_init(struct platform_device * pdev)4713c218ad55SYash Shah static int fu540_c000_init(struct platform_device *pdev)
4714c218ad55SYash Shah {
4715b959c77dSDejin Zheng mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4716b959c77dSDejin Zheng if (IS_ERR(mgmt->reg))
4717b959c77dSDejin Zheng return PTR_ERR(mgmt->reg);
4718c218ad55SYash Shah
4719c218ad55SYash Shah return macb_init(pdev);
4720c218ad55SYash Shah }
4721c218ad55SYash Shah
init_reset_optional(struct platform_device * pdev)47228a78ac73SConor Dooley static int init_reset_optional(struct platform_device *pdev)
47238a78ac73SConor Dooley {
47248a78ac73SConor Dooley struct net_device *dev = platform_get_drvdata(pdev);
47258a78ac73SConor Dooley struct macb *bp = netdev_priv(dev);
47268a78ac73SConor Dooley int ret;
47278a78ac73SConor Dooley
47288a78ac73SConor Dooley if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
47298a78ac73SConor Dooley /* Ensure PHY device used in SGMII mode is ready */
47308a78ac73SConor Dooley bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);
47318a78ac73SConor Dooley
47328a78ac73SConor Dooley if (IS_ERR(bp->sgmii_phy))
47338a78ac73SConor Dooley return dev_err_probe(&pdev->dev, PTR_ERR(bp->sgmii_phy),
47348a78ac73SConor Dooley "failed to get SGMII PHY\n");
47358a78ac73SConor Dooley
47368a78ac73SConor Dooley ret = phy_init(bp->sgmii_phy);
47378a78ac73SConor Dooley if (ret)
47388a78ac73SConor Dooley return dev_err_probe(&pdev->dev, ret,
47398a78ac73SConor Dooley "failed to init SGMII PHY\n");
47408a78ac73SConor Dooley
474132cee781SRadhey Shyam Pandey ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG);
474232cee781SRadhey Shyam Pandey if (!ret) {
474332cee781SRadhey Shyam Pandey u32 pm_info[2];
474432cee781SRadhey Shyam Pandey
474532cee781SRadhey Shyam Pandey ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
474632cee781SRadhey Shyam Pandey pm_info, ARRAY_SIZE(pm_info));
474732cee781SRadhey Shyam Pandey if (ret) {
474832cee781SRadhey Shyam Pandey dev_err(&pdev->dev, "Failed to read power management information\n");
474932cee781SRadhey Shyam Pandey goto err_out_phy_exit;
475032cee781SRadhey Shyam Pandey }
475132cee781SRadhey Shyam Pandey ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0);
475232cee781SRadhey Shyam Pandey if (ret)
475332cee781SRadhey Shyam Pandey goto err_out_phy_exit;
475432cee781SRadhey Shyam Pandey
475532cee781SRadhey Shyam Pandey ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1);
475632cee781SRadhey Shyam Pandey if (ret)
475732cee781SRadhey Shyam Pandey goto err_out_phy_exit;
475832cee781SRadhey Shyam Pandey }
475932cee781SRadhey Shyam Pandey
4760c9011b02SRadhey Shyam Pandey }
4761c9011b02SRadhey Shyam Pandey
47628a78ac73SConor Dooley /* Fully reset controller at hardware level if mapped in device tree */
47638a78ac73SConor Dooley ret = device_reset_optional(&pdev->dev);
47648a78ac73SConor Dooley if (ret) {
47658a78ac73SConor Dooley phy_exit(bp->sgmii_phy);
47668a78ac73SConor Dooley return dev_err_probe(&pdev->dev, ret, "failed to reset controller");
47678a78ac73SConor Dooley }
47688a78ac73SConor Dooley
47698a78ac73SConor Dooley ret = macb_init(pdev);
477032cee781SRadhey Shyam Pandey
477132cee781SRadhey Shyam Pandey err_out_phy_exit:
47728a78ac73SConor Dooley if (ret)
47738a78ac73SConor Dooley phy_exit(bp->sgmii_phy);
47748a78ac73SConor Dooley
47758a78ac73SConor Dooley return ret;
47768a78ac73SConor Dooley }
47778a78ac73SConor Dooley
4778ec771de6SClaudiu Beznea static const struct macb_usrio_config sama7g5_usrio = {
4779ec771de6SClaudiu Beznea .mii = 0,
4780ec771de6SClaudiu Beznea .rmii = 1,
4781ec771de6SClaudiu Beznea .rgmii = 2,
4782ec771de6SClaudiu Beznea .refclk = BIT(2),
4783ec771de6SClaudiu Beznea .hdfctlen = BIT(6),
4784ec771de6SClaudiu Beznea };
4785ec771de6SClaudiu Beznea
4786c218ad55SYash Shah static const struct macb_config fu540_c000_config = {
4787c218ad55SYash Shah .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4788c218ad55SYash Shah MACB_CAPS_GEM_HAS_PTP,
4789c218ad55SYash Shah .dma_burst_length = 16,
4790c218ad55SYash Shah .clk_init = fu540_c000_clk_init,
4791c218ad55SYash Shah .init = fu540_c000_init,
4792c218ad55SYash Shah .jumbo_max_len = 10240,
4793edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4794c218ad55SYash Shah };
4795c218ad55SYash Shah
4796b83f1527SRafal Ozieblo static const struct macb_config at91sam9260_config = {
4797b83f1527SRafal Ozieblo .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4798b83f1527SRafal Ozieblo .clk_init = macb_clk_init,
4799b83f1527SRafal Ozieblo .init = macb_init,
4800edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4801b83f1527SRafal Ozieblo };
4802b83f1527SRafal Ozieblo
4803eb4ed8e2SNicolas Ferre static const struct macb_config sama5d3macb_config = {
4804649bef9cSConor Dooley .caps = MACB_CAPS_SG_DISABLED |
4805649bef9cSConor Dooley MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4806eb4ed8e2SNicolas Ferre .clk_init = macb_clk_init,
4807eb4ed8e2SNicolas Ferre .init = macb_init,
4808edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4809eb4ed8e2SNicolas Ferre };
4810eb4ed8e2SNicolas Ferre
4811b83f1527SRafal Ozieblo static const struct macb_config pc302gem_config = {
4812b83f1527SRafal Ozieblo .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4813b83f1527SRafal Ozieblo .dma_burst_length = 16,
4814b83f1527SRafal Ozieblo .clk_init = macb_clk_init,
4815b83f1527SRafal Ozieblo .init = macb_init,
4816edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4817b83f1527SRafal Ozieblo };
4818b83f1527SRafal Ozieblo
4819b83f1527SRafal Ozieblo static const struct macb_config sama5d2_config = {
4820b83f1527SRafal Ozieblo .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4821b83f1527SRafal Ozieblo .dma_burst_length = 16,
4822b83f1527SRafal Ozieblo .clk_init = macb_clk_init,
4823b83f1527SRafal Ozieblo .init = macb_init,
4824edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4825b83f1527SRafal Ozieblo };
4826b83f1527SRafal Ozieblo
48277d13ad50SHari Prasath static const struct macb_config sama5d29_config = {
48287d13ad50SHari Prasath .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
48297d13ad50SHari Prasath .dma_burst_length = 16,
48307d13ad50SHari Prasath .clk_init = macb_clk_init,
48317d13ad50SHari Prasath .init = macb_init,
48327d13ad50SHari Prasath .usrio = &macb_default_usrio,
48337d13ad50SHari Prasath };
48347d13ad50SHari Prasath
4835b83f1527SRafal Ozieblo static const struct macb_config sama5d3_config = {
4836649bef9cSConor Dooley .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4837649bef9cSConor Dooley MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4838b83f1527SRafal Ozieblo .dma_burst_length = 16,
4839b83f1527SRafal Ozieblo .clk_init = macb_clk_init,
4840b83f1527SRafal Ozieblo .init = macb_init,
4841233a1587Svishnuvardhan .jumbo_max_len = 10240,
4842edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4843b83f1527SRafal Ozieblo };
4844b83f1527SRafal Ozieblo
4845b83f1527SRafal Ozieblo static const struct macb_config sama5d4_config = {
4846b83f1527SRafal Ozieblo .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4847b83f1527SRafal Ozieblo .dma_burst_length = 4,
4848b83f1527SRafal Ozieblo .clk_init = macb_clk_init,
4849b83f1527SRafal Ozieblo .init = macb_init,
4850edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4851b83f1527SRafal Ozieblo };
4852b83f1527SRafal Ozieblo
4853b83f1527SRafal Ozieblo static const struct macb_config emac_config = {
4854ac2fcfa9SAlexandre Belloni .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4855b83f1527SRafal Ozieblo .clk_init = at91ether_clk_init,
4856b83f1527SRafal Ozieblo .init = at91ether_init,
4857edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4858b83f1527SRafal Ozieblo };
4859b83f1527SRafal Ozieblo
4860b83f1527SRafal Ozieblo static const struct macb_config np4_config = {
4861b83f1527SRafal Ozieblo .caps = MACB_CAPS_USRIO_DISABLED,
4862b83f1527SRafal Ozieblo .clk_init = macb_clk_init,
4863b83f1527SRafal Ozieblo .init = macb_init,
4864edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4865b83f1527SRafal Ozieblo };
4866b83f1527SRafal Ozieblo
4867b83f1527SRafal Ozieblo static const struct macb_config zynqmp_config = {
4868ab91f0a9SRafal Ozieblo .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4869ab91f0a9SRafal Ozieblo MACB_CAPS_JUMBO |
4870404cd086SHarini Katakam MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4871b83f1527SRafal Ozieblo .dma_burst_length = 16,
4872b83f1527SRafal Ozieblo .clk_init = macb_clk_init,
48738aad66aaSConor Dooley .init = init_reset_optional,
4874b83f1527SRafal Ozieblo .jumbo_max_len = 10240,
4875edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4876b83f1527SRafal Ozieblo };
4877b83f1527SRafal Ozieblo
4878b83f1527SRafal Ozieblo static const struct macb_config zynq_config = {
4879e501070eSHarini Katakam .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4880e501070eSHarini Katakam MACB_CAPS_NEEDS_RSTONUBR,
4881b83f1527SRafal Ozieblo .dma_burst_length = 16,
4882b83f1527SRafal Ozieblo .clk_init = macb_clk_init,
4883b83f1527SRafal Ozieblo .init = macb_init,
4884edac6386SClaudiu Beznea .usrio = &macb_default_usrio,
4885b83f1527SRafal Ozieblo };
4886b83f1527SRafal Ozieblo
48878aad66aaSConor Dooley static const struct macb_config mpfs_config = {
48888aad66aaSConor Dooley .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
48898aad66aaSConor Dooley MACB_CAPS_JUMBO |
48908aad66aaSConor Dooley MACB_CAPS_GEM_HAS_PTP,
48918aad66aaSConor Dooley .dma_burst_length = 16,
48928aad66aaSConor Dooley .clk_init = macb_clk_init,
48938aad66aaSConor Dooley .init = init_reset_optional,
48948aad66aaSConor Dooley .usrio = &macb_default_usrio,
4895314cf958SDaire McNamara .max_tx_length = 4040, /* Cadence Erratum 1686 */
4896314cf958SDaire McNamara .jumbo_max_len = 4040,
48978aad66aaSConor Dooley };
48988aad66aaSConor Dooley
4899ec771de6SClaudiu Beznea static const struct macb_config sama7g5_gem_config = {
49000f4f6d73SClaudiu Beznea .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
4901abc783a7SDurai Manickam KR MACB_CAPS_MIIONRGMII | MACB_CAPS_GEM_HAS_PTP,
4902ec771de6SClaudiu Beznea .dma_burst_length = 16,
4903ec771de6SClaudiu Beznea .clk_init = macb_clk_init,
4904ec771de6SClaudiu Beznea .init = macb_init,
4905ec771de6SClaudiu Beznea .usrio = &sama7g5_usrio,
4906ec771de6SClaudiu Beznea };
4907ec771de6SClaudiu Beznea
4908700d566eSClaudiu Beznea static const struct macb_config sama7g5_emac_config = {
49090f4f6d73SClaudiu Beznea .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
49109bae0dd0SDurai Manickam KR MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII |
49119bae0dd0SDurai Manickam KR MACB_CAPS_GEM_HAS_PTP,
4912700d566eSClaudiu Beznea .dma_burst_length = 16,
4913700d566eSClaudiu Beznea .clk_init = macb_clk_init,
4914700d566eSClaudiu Beznea .init = macb_init,
4915700d566eSClaudiu Beznea .usrio = &sama7g5_usrio,
4916700d566eSClaudiu Beznea };
4917700d566eSClaudiu Beznea
49188a1c9753SHarini Katakam static const struct macb_config versal_config = {
49198a1c9753SHarini Katakam .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
49208a1c9753SHarini Katakam MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK,
49218a1c9753SHarini Katakam .dma_burst_length = 16,
49228a1c9753SHarini Katakam .clk_init = macb_clk_init,
49238a1c9753SHarini Katakam .init = init_reset_optional,
49248a1c9753SHarini Katakam .jumbo_max_len = 10240,
49258a1c9753SHarini Katakam .usrio = &macb_default_usrio,
49268a1c9753SHarini Katakam };
49278a1c9753SHarini Katakam
4928b83f1527SRafal Ozieblo static const struct of_device_id macb_dt_ids[] = {
4929b83f1527SRafal Ozieblo { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4930b83f1527SRafal Ozieblo { .compatible = "cdns,macb" },
4931b83f1527SRafal Ozieblo { .compatible = "cdns,np4-macb", .data = &np4_config },
4932b83f1527SRafal Ozieblo { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4933b83f1527SRafal Ozieblo { .compatible = "cdns,gem", .data = &pc302gem_config },
49343e3e0cdfSNicolas Ferre { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4935b83f1527SRafal Ozieblo { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
49367d13ad50SHari Prasath { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
4937b83f1527SRafal Ozieblo { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4938eb4ed8e2SNicolas Ferre { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4939b83f1527SRafal Ozieblo { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4940b83f1527SRafal Ozieblo { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4941b83f1527SRafal Ozieblo { .compatible = "cdns,emac", .data = &emac_config },
4942623cd870SKrzysztof Kozlowski { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
4943623cd870SKrzysztof Kozlowski { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
49446342ea88SYash Shah { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
49458aad66aaSConor Dooley { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
4946ec771de6SClaudiu Beznea { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4947700d566eSClaudiu Beznea { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4948623cd870SKrzysztof Kozlowski { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
4949623cd870SKrzysztof Kozlowski { .compatible = "xlnx,zynq-gem", .data = &zynq_config },
4950623cd870SKrzysztof Kozlowski { .compatible = "xlnx,versal-gem", .data = &versal_config},
4951b83f1527SRafal Ozieblo { /* sentinel */ }
4952b83f1527SRafal Ozieblo };
4953b83f1527SRafal Ozieblo MODULE_DEVICE_TABLE(of, macb_dt_ids);
4954b83f1527SRafal Ozieblo #endif /* CONFIG_OF */
4955b83f1527SRafal Ozieblo
4956b83f1527SRafal Ozieblo static const struct macb_config default_gem_config = {
4957ab91f0a9SRafal Ozieblo .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4958ab91f0a9SRafal Ozieblo MACB_CAPS_JUMBO |
4959ab91f0a9SRafal Ozieblo MACB_CAPS_GEM_HAS_PTP,
4960b83f1527SRafal Ozieblo .dma_burst_length = 16,
4961b83f1527SRafal Ozieblo .clk_init = macb_clk_init,
4962b83f1527SRafal Ozieblo .init = macb_init,
4963b1242236SAtish Patra .usrio = &macb_default_usrio,
4964b83f1527SRafal Ozieblo .jumbo_max_len = 10240,
4965b83f1527SRafal Ozieblo };
4966b83f1527SRafal Ozieblo
macb_probe(struct platform_device * pdev)4967b83f1527SRafal Ozieblo static int macb_probe(struct platform_device *pdev)
4968b83f1527SRafal Ozieblo {
4969b83f1527SRafal Ozieblo const struct macb_config *macb_config = &default_gem_config;
4970b83f1527SRafal Ozieblo int (*clk_init)(struct platform_device *, struct clk **,
4971f5473d1dSHarini Katakam struct clk **, struct clk **, struct clk **,
4972f5473d1dSHarini Katakam struct clk **) = macb_config->clk_init;
4973b83f1527SRafal Ozieblo int (*init)(struct platform_device *) = macb_config->init;
4974b83f1527SRafal Ozieblo struct device_node *np = pdev->dev.of_node;
4975b83f1527SRafal Ozieblo struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4976f5473d1dSHarini Katakam struct clk *tsu_clk = NULL;
4977b83f1527SRafal Ozieblo unsigned int queue_mask, num_queues;
4978b83f1527SRafal Ozieblo bool native_io;
49790c65b2b9SAndrew Lunn phy_interface_t interface;
4980b83f1527SRafal Ozieblo struct net_device *dev;
4981b83f1527SRafal Ozieblo struct resource *regs;
4982cae4bc06SMaulik Jodhani u32 wtrmrk_rst_val;
4983b83f1527SRafal Ozieblo void __iomem *mem;
4984b83f1527SRafal Ozieblo struct macb *bp;
4985404cd086SHarini Katakam int err, val;
4986b83f1527SRafal Ozieblo
4987809660cbSYang Yingliang mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
4988b83f1527SRafal Ozieblo if (IS_ERR(mem))
4989b83f1527SRafal Ozieblo return PTR_ERR(mem);
4990b83f1527SRafal Ozieblo
4991b83f1527SRafal Ozieblo if (np) {
4992b83f1527SRafal Ozieblo const struct of_device_id *match;
4993b83f1527SRafal Ozieblo
4994b83f1527SRafal Ozieblo match = of_match_node(macb_dt_ids, np);
4995b83f1527SRafal Ozieblo if (match && match->data) {
4996b83f1527SRafal Ozieblo macb_config = match->data;
4997b83f1527SRafal Ozieblo clk_init = macb_config->clk_init;
4998b83f1527SRafal Ozieblo init = macb_config->init;
4999b83f1527SRafal Ozieblo }
5000b83f1527SRafal Ozieblo }
5001b83f1527SRafal Ozieblo
5002f5473d1dSHarini Katakam err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
5003b83f1527SRafal Ozieblo if (err)
5004b83f1527SRafal Ozieblo return err;
5005b83f1527SRafal Ozieblo
5006d54f89afSHarini Katakam pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
5007d54f89afSHarini Katakam pm_runtime_use_autosuspend(&pdev->dev);
5008d54f89afSHarini Katakam pm_runtime_get_noresume(&pdev->dev);
5009d54f89afSHarini Katakam pm_runtime_set_active(&pdev->dev);
5010d54f89afSHarini Katakam pm_runtime_enable(&pdev->dev);
5011b83f1527SRafal Ozieblo native_io = hw_is_native_io(mem);
5012b83f1527SRafal Ozieblo
5013b83f1527SRafal Ozieblo macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
5014b83f1527SRafal Ozieblo dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
5015b83f1527SRafal Ozieblo if (!dev) {
5016b83f1527SRafal Ozieblo err = -ENOMEM;
5017b83f1527SRafal Ozieblo goto err_disable_clocks;
5018b83f1527SRafal Ozieblo }
5019b83f1527SRafal Ozieblo
5020b83f1527SRafal Ozieblo dev->base_addr = regs->start;
5021b83f1527SRafal Ozieblo
5022b83f1527SRafal Ozieblo SET_NETDEV_DEV(dev, &pdev->dev);
5023b83f1527SRafal Ozieblo
5024b83f1527SRafal Ozieblo bp = netdev_priv(dev);
5025b83f1527SRafal Ozieblo bp->pdev = pdev;
5026b83f1527SRafal Ozieblo bp->dev = dev;
5027b83f1527SRafal Ozieblo bp->regs = mem;
5028b83f1527SRafal Ozieblo bp->native_io = native_io;
5029b83f1527SRafal Ozieblo if (native_io) {
5030b83f1527SRafal Ozieblo bp->macb_reg_readl = hw_readl_native;
5031b83f1527SRafal Ozieblo bp->macb_reg_writel = hw_writel_native;
5032b83f1527SRafal Ozieblo } else {
5033b83f1527SRafal Ozieblo bp->macb_reg_readl = hw_readl;
5034b83f1527SRafal Ozieblo bp->macb_reg_writel = hw_writel;
5035b83f1527SRafal Ozieblo }
5036b83f1527SRafal Ozieblo bp->num_queues = num_queues;
5037b83f1527SRafal Ozieblo bp->queue_mask = queue_mask;
5038b83f1527SRafal Ozieblo if (macb_config)
5039b83f1527SRafal Ozieblo bp->dma_burst_length = macb_config->dma_burst_length;
5040b83f1527SRafal Ozieblo bp->pclk = pclk;
5041b83f1527SRafal Ozieblo bp->hclk = hclk;
5042b83f1527SRafal Ozieblo bp->tx_clk = tx_clk;
5043b83f1527SRafal Ozieblo bp->rx_clk = rx_clk;
5044f5473d1dSHarini Katakam bp->tsu_clk = tsu_clk;
5045b83f1527SRafal Ozieblo if (macb_config)
5046b83f1527SRafal Ozieblo bp->jumbo_max_len = macb_config->jumbo_max_len;
5047b83f1527SRafal Ozieblo
5048314cf958SDaire McNamara if (!hw_is_gem(bp->regs, bp->native_io))
5049314cf958SDaire McNamara bp->max_tx_length = MACB_MAX_TX_LEN;
5050314cf958SDaire McNamara else if (macb_config->max_tx_length)
5051314cf958SDaire McNamara bp->max_tx_length = macb_config->max_tx_length;
5052314cf958SDaire McNamara else
5053314cf958SDaire McNamara bp->max_tx_length = GEM_MAX_TX_LEN;
5054314cf958SDaire McNamara
5055b83f1527SRafal Ozieblo bp->wol = 0;
50561a87e641SRob Herring if (of_property_read_bool(np, "magic-packet"))
5057b83f1527SRafal Ozieblo bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
5058ced4799dSNicolas Ferre device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
5059b83f1527SRafal Ozieblo
5060edac6386SClaudiu Beznea bp->usrio = macb_config->usrio;
5061edac6386SClaudiu Beznea
5062cae4bc06SMaulik Jodhani /* By default we set to partial store and forward mode for zynqmp.
5063cae4bc06SMaulik Jodhani * Disable if not set in devicetree.
5064cae4bc06SMaulik Jodhani */
5065cae4bc06SMaulik Jodhani if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) {
5066cae4bc06SMaulik Jodhani err = of_property_read_u32(bp->pdev->dev.of_node,
5067cae4bc06SMaulik Jodhani "cdns,rx-watermark",
5068cae4bc06SMaulik Jodhani &bp->rx_watermark);
5069cae4bc06SMaulik Jodhani
5070cae4bc06SMaulik Jodhani if (!err) {
5071cae4bc06SMaulik Jodhani /* Disable partial store and forward in case of error or
5072cae4bc06SMaulik Jodhani * invalid watermark value
5073cae4bc06SMaulik Jodhani */
5074cae4bc06SMaulik Jodhani wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1;
5075cae4bc06SMaulik Jodhani if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) {
5076cae4bc06SMaulik Jodhani dev_info(&bp->pdev->dev, "Invalid watermark value\n");
5077cae4bc06SMaulik Jodhani bp->rx_watermark = 0;
5078cae4bc06SMaulik Jodhani }
5079cae4bc06SMaulik Jodhani }
5080cae4bc06SMaulik Jodhani }
5081b83f1527SRafal Ozieblo spin_lock_init(&bp->lock);
5082b83f1527SRafal Ozieblo
5083b83f1527SRafal Ozieblo /* setup capabilities */
5084b83f1527SRafal Ozieblo macb_configure_caps(bp, macb_config);
5085b83f1527SRafal Ozieblo
5086b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5087b83f1527SRafal Ozieblo if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
508837f78606SMarc St-Amand dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
5089b83f1527SRafal Ozieblo bp->hw_dma_cap |= HW_DMA_CAP_64B;
5090b83f1527SRafal Ozieblo }
5091b83f1527SRafal Ozieblo #endif
5092b83f1527SRafal Ozieblo platform_set_drvdata(pdev, dev);
5093b83f1527SRafal Ozieblo
5094b83f1527SRafal Ozieblo dev->irq = platform_get_irq(pdev, 0);
5095b83f1527SRafal Ozieblo if (dev->irq < 0) {
5096b83f1527SRafal Ozieblo err = dev->irq;
5097b83f1527SRafal Ozieblo goto err_out_free_netdev;
5098b83f1527SRafal Ozieblo }
5099b83f1527SRafal Ozieblo
5100b83f1527SRafal Ozieblo /* MTU range: 68 - 1500 or 10240 */
5101b83f1527SRafal Ozieblo dev->min_mtu = GEM_MTU_MIN_SIZE;
510246e31db5SOleksij Rempel if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
510346e31db5SOleksij Rempel dev->max_mtu = bp->jumbo_max_len - ETH_HLEN - ETH_FCS_LEN;
5104b83f1527SRafal Ozieblo else
5105b83f1527SRafal Ozieblo dev->max_mtu = ETH_DATA_LEN;
5106b83f1527SRafal Ozieblo
5107404cd086SHarini Katakam if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
5108404cd086SHarini Katakam val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
5109404cd086SHarini Katakam if (val)
5110404cd086SHarini Katakam bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
5111404cd086SHarini Katakam macb_dma_desc_get_size(bp);
5112404cd086SHarini Katakam
5113404cd086SHarini Katakam val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
5114404cd086SHarini Katakam if (val)
5115404cd086SHarini Katakam bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
5116404cd086SHarini Katakam macb_dma_desc_get_size(bp);
5117404cd086SHarini Katakam }
5118404cd086SHarini Katakam
5119e501070eSHarini Katakam bp->rx_intr_mask = MACB_RX_INT_FLAGS;
5120e501070eSHarini Katakam if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
5121e501070eSHarini Katakam bp->rx_intr_mask |= MACB_BIT(RXUBR);
5122e501070eSHarini Katakam
51239ca01b25SJakub Kicinski err = of_get_ethdev_address(np, bp->dev);
512483216e39SMichael Walle if (err == -EPROBE_DEFER)
5125541ddc66SPetr Štetiar goto err_out_free_netdev;
512683216e39SMichael Walle else if (err)
5127b83f1527SRafal Ozieblo macb_get_hwaddr(bp);
5128b83f1527SRafal Ozieblo
51290c65b2b9SAndrew Lunn err = of_get_phy_mode(np, &interface);
51300c65b2b9SAndrew Lunn if (err)
51318b952747SNicolas Ferre /* not found in DT, MII by default */
5132b83f1527SRafal Ozieblo bp->phy_interface = PHY_INTERFACE_MODE_MII;
51338b952747SNicolas Ferre else
51340c65b2b9SAndrew Lunn bp->phy_interface = interface;
5135b83f1527SRafal Ozieblo
5136b83f1527SRafal Ozieblo /* IP specific init */
5137b83f1527SRafal Ozieblo err = init(pdev);
5138b83f1527SRafal Ozieblo if (err)
5139b83f1527SRafal Ozieblo goto err_out_free_netdev;
5140b83f1527SRafal Ozieblo
5141b83f1527SRafal Ozieblo err = macb_mii_init(bp);
5142b83f1527SRafal Ozieblo if (err)
51438b73fa3aSRobert Hancock goto err_out_phy_exit;
5144b83f1527SRafal Ozieblo
5145b83f1527SRafal Ozieblo netif_carrier_off(dev);
5146b83f1527SRafal Ozieblo
5147b83f1527SRafal Ozieblo err = register_netdev(dev);
5148b83f1527SRafal Ozieblo if (err) {
5149b83f1527SRafal Ozieblo dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5150b83f1527SRafal Ozieblo goto err_out_unregister_mdio;
5151b83f1527SRafal Ozieblo }
5152b83f1527SRafal Ozieblo
5153e7412b83SAllen Pais tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
5154032dc41bSHarini Katakam
5155b83f1527SRafal Ozieblo netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
5156b83f1527SRafal Ozieblo macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
5157b83f1527SRafal Ozieblo dev->base_addr, dev->irq, dev->dev_addr);
5158b83f1527SRafal Ozieblo
5159d54f89afSHarini Katakam pm_runtime_mark_last_busy(&bp->pdev->dev);
5160d54f89afSHarini Katakam pm_runtime_put_autosuspend(&bp->pdev->dev);
5161d54f89afSHarini Katakam
5162b83f1527SRafal Ozieblo return 0;
5163b83f1527SRafal Ozieblo
5164b83f1527SRafal Ozieblo err_out_unregister_mdio:
5165b83f1527SRafal Ozieblo mdiobus_unregister(bp->mii_bus);
5166b83f1527SRafal Ozieblo mdiobus_free(bp->mii_bus);
5167b83f1527SRafal Ozieblo
51688b73fa3aSRobert Hancock err_out_phy_exit:
51698b73fa3aSRobert Hancock phy_exit(bp->sgmii_phy);
51708b73fa3aSRobert Hancock
5171b83f1527SRafal Ozieblo err_out_free_netdev:
5172b83f1527SRafal Ozieblo free_netdev(dev);
5173b83f1527SRafal Ozieblo
5174b83f1527SRafal Ozieblo err_disable_clocks:
517538493da4SClaudiu Beznea macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
5176d54f89afSHarini Katakam pm_runtime_disable(&pdev->dev);
5177d54f89afSHarini Katakam pm_runtime_set_suspended(&pdev->dev);
5178d54f89afSHarini Katakam pm_runtime_dont_use_autosuspend(&pdev->dev);
5179b83f1527SRafal Ozieblo
5180b83f1527SRafal Ozieblo return err;
5181b83f1527SRafal Ozieblo }
5182b83f1527SRafal Ozieblo
macb_remove(struct platform_device * pdev)51836b594040SUwe Kleine-König static void macb_remove(struct platform_device *pdev)
5184b83f1527SRafal Ozieblo {
5185b83f1527SRafal Ozieblo struct net_device *dev;
5186b83f1527SRafal Ozieblo struct macb *bp;
5187b83f1527SRafal Ozieblo
5188b83f1527SRafal Ozieblo dev = platform_get_drvdata(pdev);
5189b83f1527SRafal Ozieblo
5190b83f1527SRafal Ozieblo if (dev) {
5191b83f1527SRafal Ozieblo bp = netdev_priv(dev);
51928b73fa3aSRobert Hancock phy_exit(bp->sgmii_phy);
5193b83f1527SRafal Ozieblo mdiobus_unregister(bp->mii_bus);
5194b83f1527SRafal Ozieblo mdiobus_free(bp->mii_bus);
5195b83f1527SRafal Ozieblo
5196b83f1527SRafal Ozieblo unregister_netdev(dev);
519761183b05SChuhong Yuan tasklet_kill(&bp->hresp_err_tasklet);
5198d54f89afSHarini Katakam pm_runtime_disable(&pdev->dev);
5199d54f89afSHarini Katakam pm_runtime_dont_use_autosuspend(&pdev->dev);
5200d54f89afSHarini Katakam if (!pm_runtime_suspended(&pdev->dev)) {
520138493da4SClaudiu Beznea macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
520238493da4SClaudiu Beznea bp->rx_clk, bp->tsu_clk);
5203d54f89afSHarini Katakam pm_runtime_set_suspended(&pdev->dev);
5204d54f89afSHarini Katakam }
52057897b071SAntoine Tenart phylink_destroy(bp->phylink);
5206b83f1527SRafal Ozieblo free_netdev(dev);
5207b83f1527SRafal Ozieblo }
5208b83f1527SRafal Ozieblo }
5209b83f1527SRafal Ozieblo
macb_suspend(struct device * dev)5210b83f1527SRafal Ozieblo static int __maybe_unused macb_suspend(struct device *dev)
5211b83f1527SRafal Ozieblo {
5212ce886a47SWolfram Sang struct net_device *netdev = dev_get_drvdata(dev);
5213b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev);
5214bbf6aceaSJiapeng Chong struct macb_queue *queue;
5215de991c58SHarini Katakam unsigned long flags;
5216de991c58SHarini Katakam unsigned int q;
5217558e35ccSNicolas Ferre int err;
5218b83f1527SRafal Ozieblo
52196c461e39SRadhey Shyam Pandey if (!device_may_wakeup(&bp->dev->dev))
52206c461e39SRadhey Shyam Pandey phy_exit(bp->sgmii_phy);
52216c461e39SRadhey Shyam Pandey
5222de991c58SHarini Katakam if (!netif_running(netdev))
5223de991c58SHarini Katakam return 0;
5224de991c58SHarini Katakam
5225b83f1527SRafal Ozieblo if (bp->wol & MACB_WOL_ENABLED) {
5226558e35ccSNicolas Ferre spin_lock_irqsave(&bp->lock, flags);
5227558e35ccSNicolas Ferre /* Flush all status bits */
5228558e35ccSNicolas Ferre macb_writel(bp, TSR, -1);
5229558e35ccSNicolas Ferre macb_writel(bp, RSR, -1);
5230558e35ccSNicolas Ferre for (q = 0, queue = bp->queues; q < bp->num_queues;
5231558e35ccSNicolas Ferre ++q, ++queue) {
5232558e35ccSNicolas Ferre /* Disable all interrupts */
5233558e35ccSNicolas Ferre queue_writel(queue, IDR, -1);
5234558e35ccSNicolas Ferre queue_readl(queue, ISR);
5235558e35ccSNicolas Ferre if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5236558e35ccSNicolas Ferre queue_writel(queue, ISR, -1);
5237558e35ccSNicolas Ferre }
5238558e35ccSNicolas Ferre /* Change interrupt handler and
5239558e35ccSNicolas Ferre * Enable WoL IRQ on queue 0
5240558e35ccSNicolas Ferre */
5241558e35ccSNicolas Ferre devm_free_irq(dev, bp->queues[0].irq, bp->queues);
52429d45c8e8SNicolas Ferre if (macb_is_gem(bp)) {
5243558e35ccSNicolas Ferre err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
5244558e35ccSNicolas Ferre IRQF_SHARED, netdev->name, bp->queues);
5245558e35ccSNicolas Ferre if (err) {
5246558e35ccSNicolas Ferre dev_err(dev,
5247558e35ccSNicolas Ferre "Unable to request IRQ %d (error %d)\n",
5248558e35ccSNicolas Ferre bp->queues[0].irq, err);
5249558e35ccSNicolas Ferre spin_unlock_irqrestore(&bp->lock, flags);
5250558e35ccSNicolas Ferre return err;
5251558e35ccSNicolas Ferre }
5252558e35ccSNicolas Ferre queue_writel(bp->queues, IER, GEM_BIT(WOL));
5253558e35ccSNicolas Ferre gem_writel(bp, WOL, MACB_BIT(MAG));
5254de991c58SHarini Katakam } else {
52559d45c8e8SNicolas Ferre err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
52569d45c8e8SNicolas Ferre IRQF_SHARED, netdev->name, bp->queues);
52579d45c8e8SNicolas Ferre if (err) {
52589d45c8e8SNicolas Ferre dev_err(dev,
52599d45c8e8SNicolas Ferre "Unable to request IRQ %d (error %d)\n",
52609d45c8e8SNicolas Ferre bp->queues[0].irq, err);
52619d45c8e8SNicolas Ferre spin_unlock_irqrestore(&bp->lock, flags);
52629d45c8e8SNicolas Ferre return err;
52639d45c8e8SNicolas Ferre }
5264558e35ccSNicolas Ferre queue_writel(bp->queues, IER, MACB_BIT(WOL));
5265558e35ccSNicolas Ferre macb_writel(bp, WOL, MACB_BIT(MAG));
5266558e35ccSNicolas Ferre }
5267558e35ccSNicolas Ferre spin_unlock_irqrestore(&bp->lock, flags);
5268558e35ccSNicolas Ferre
5269558e35ccSNicolas Ferre enable_irq_wake(bp->queues[0].irq);
5270558e35ccSNicolas Ferre }
5271558e35ccSNicolas Ferre
5272de991c58SHarini Katakam netif_device_detach(netdev);
5273de991c58SHarini Katakam for (q = 0, queue = bp->queues; q < bp->num_queues;
5274138badbcSRobert Hancock ++q, ++queue) {
5275138badbcSRobert Hancock napi_disable(&queue->napi_rx);
5276138badbcSRobert Hancock napi_disable(&queue->napi_tx);
5277138badbcSRobert Hancock }
5278558e35ccSNicolas Ferre
5279558e35ccSNicolas Ferre if (!(bp->wol & MACB_WOL_ENABLED)) {
52807897b071SAntoine Tenart rtnl_lock();
52817897b071SAntoine Tenart phylink_stop(bp->phylink);
52827897b071SAntoine Tenart rtnl_unlock();
5283de991c58SHarini Katakam spin_lock_irqsave(&bp->lock, flags);
5284de991c58SHarini Katakam macb_reset_hw(bp);
5285de991c58SHarini Katakam spin_unlock_irqrestore(&bp->lock, flags);
5286558e35ccSNicolas Ferre }
5287c1e85c6cSClaudiu Beznea
5288c1e85c6cSClaudiu Beznea if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5289c1e85c6cSClaudiu Beznea bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
5290c1e85c6cSClaudiu Beznea
5291c1e85c6cSClaudiu Beznea if (netdev->hw_features & NETIF_F_NTUPLE)
5292c1e85c6cSClaudiu Beznea bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
5293d54f89afSHarini Katakam
5294de991c58SHarini Katakam if (bp->ptp_info)
5295de991c58SHarini Katakam bp->ptp_info->ptp_remove(netdev);
52966c8f85caSNicolas Ferre if (!device_may_wakeup(dev))
5297d54f89afSHarini Katakam pm_runtime_force_suspend(dev);
5298d54f89afSHarini Katakam
5299d54f89afSHarini Katakam return 0;
5300d54f89afSHarini Katakam }
5301d54f89afSHarini Katakam
macb_resume(struct device * dev)5302d54f89afSHarini Katakam static int __maybe_unused macb_resume(struct device *dev)
5303d54f89afSHarini Katakam {
5304d54f89afSHarini Katakam struct net_device *netdev = dev_get_drvdata(dev);
5305d54f89afSHarini Katakam struct macb *bp = netdev_priv(netdev);
5306bbf6aceaSJiapeng Chong struct macb_queue *queue;
5307558e35ccSNicolas Ferre unsigned long flags;
5308de991c58SHarini Katakam unsigned int q;
5309558e35ccSNicolas Ferre int err;
5310de991c58SHarini Katakam
53116c461e39SRadhey Shyam Pandey if (!device_may_wakeup(&bp->dev->dev))
53126c461e39SRadhey Shyam Pandey phy_init(bp->sgmii_phy);
53136c461e39SRadhey Shyam Pandey
5314de991c58SHarini Katakam if (!netif_running(netdev))
5315de991c58SHarini Katakam return 0;
5316d54f89afSHarini Katakam
53176c8f85caSNicolas Ferre if (!device_may_wakeup(dev))
5318d54f89afSHarini Katakam pm_runtime_force_resume(dev);
5319d54f89afSHarini Katakam
5320d54f89afSHarini Katakam if (bp->wol & MACB_WOL_ENABLED) {
5321558e35ccSNicolas Ferre spin_lock_irqsave(&bp->lock, flags);
5322558e35ccSNicolas Ferre /* Disable WoL */
5323558e35ccSNicolas Ferre if (macb_is_gem(bp)) {
5324558e35ccSNicolas Ferre queue_writel(bp->queues, IDR, GEM_BIT(WOL));
5325558e35ccSNicolas Ferre gem_writel(bp, WOL, 0);
5326de991c58SHarini Katakam } else {
5327558e35ccSNicolas Ferre queue_writel(bp->queues, IDR, MACB_BIT(WOL));
5328558e35ccSNicolas Ferre macb_writel(bp, WOL, 0);
5329558e35ccSNicolas Ferre }
5330558e35ccSNicolas Ferre /* Clear ISR on queue 0 */
5331558e35ccSNicolas Ferre queue_readl(bp->queues, ISR);
5332558e35ccSNicolas Ferre if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5333558e35ccSNicolas Ferre queue_writel(bp->queues, ISR, -1);
5334558e35ccSNicolas Ferre /* Replace interrupt handler on queue 0 */
5335558e35ccSNicolas Ferre devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5336558e35ccSNicolas Ferre err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
5337558e35ccSNicolas Ferre IRQF_SHARED, netdev->name, bp->queues);
5338558e35ccSNicolas Ferre if (err) {
5339558e35ccSNicolas Ferre dev_err(dev,
5340558e35ccSNicolas Ferre "Unable to request IRQ %d (error %d)\n",
5341558e35ccSNicolas Ferre bp->queues[0].irq, err);
5342558e35ccSNicolas Ferre spin_unlock_irqrestore(&bp->lock, flags);
5343558e35ccSNicolas Ferre return err;
5344558e35ccSNicolas Ferre }
5345558e35ccSNicolas Ferre spin_unlock_irqrestore(&bp->lock, flags);
5346558e35ccSNicolas Ferre
5347558e35ccSNicolas Ferre disable_irq_wake(bp->queues[0].irq);
5348558e35ccSNicolas Ferre
5349558e35ccSNicolas Ferre /* Now make sure we disable phy before moving
5350558e35ccSNicolas Ferre * to common restore path
5351558e35ccSNicolas Ferre */
5352558e35ccSNicolas Ferre rtnl_lock();
5353558e35ccSNicolas Ferre phylink_stop(bp->phylink);
5354558e35ccSNicolas Ferre rtnl_unlock();
5355558e35ccSNicolas Ferre }
5356558e35ccSNicolas Ferre
5357558e35ccSNicolas Ferre for (q = 0, queue = bp->queues; q < bp->num_queues;
5358138badbcSRobert Hancock ++q, ++queue) {
5359138badbcSRobert Hancock napi_enable(&queue->napi_rx);
5360138badbcSRobert Hancock napi_enable(&queue->napi_tx);
5361138badbcSRobert Hancock }
5362c1e85c6cSClaudiu Beznea
5363c1e85c6cSClaudiu Beznea if (netdev->hw_features & NETIF_F_NTUPLE)
5364c1e85c6cSClaudiu Beznea gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
5365c1e85c6cSClaudiu Beznea
5366c1e85c6cSClaudiu Beznea if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5367c1e85c6cSClaudiu Beznea macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5368c1e85c6cSClaudiu Beznea
5369558e35ccSNicolas Ferre macb_writel(bp, NCR, MACB_BIT(MPE));
5370de991c58SHarini Katakam macb_init_hw(bp);
5371de991c58SHarini Katakam macb_set_rx_mode(netdev);
5372c1e85c6cSClaudiu Beznea macb_restore_features(bp);
5373558e35ccSNicolas Ferre rtnl_lock();
5374f22bd29bSRadhey Shyam Pandey
5375558e35ccSNicolas Ferre phylink_start(bp->phylink);
5376558e35ccSNicolas Ferre rtnl_unlock();
5377558e35ccSNicolas Ferre
5378d54f89afSHarini Katakam netif_device_attach(netdev);
5379de991c58SHarini Katakam if (bp->ptp_info)
5380de991c58SHarini Katakam bp->ptp_info->ptp_init(netdev);
5381d54f89afSHarini Katakam
5382d54f89afSHarini Katakam return 0;
5383d54f89afSHarini Katakam }
5384d54f89afSHarini Katakam
macb_runtime_suspend(struct device * dev)5385d54f89afSHarini Katakam static int __maybe_unused macb_runtime_suspend(struct device *dev)
5386d54f89afSHarini Katakam {
5387f9cb7597SWolfram Sang struct net_device *netdev = dev_get_drvdata(dev);
5388d54f89afSHarini Katakam struct macb *bp = netdev_priv(netdev);
5389d54f89afSHarini Katakam
539038493da4SClaudiu Beznea if (!(device_may_wakeup(dev)))
539138493da4SClaudiu Beznea macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
53928a1c9753SHarini Katakam else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK))
539338493da4SClaudiu Beznea macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5394b83f1527SRafal Ozieblo
5395b83f1527SRafal Ozieblo return 0;
5396b83f1527SRafal Ozieblo }
5397b83f1527SRafal Ozieblo
macb_runtime_resume(struct device * dev)5398d54f89afSHarini Katakam static int __maybe_unused macb_runtime_resume(struct device *dev)
5399b83f1527SRafal Ozieblo {
5400f9cb7597SWolfram Sang struct net_device *netdev = dev_get_drvdata(dev);
5401b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev);
5402b83f1527SRafal Ozieblo
5403515a10a7SNicolas Ferre if (!(device_may_wakeup(dev))) {
5404b83f1527SRafal Ozieblo clk_prepare_enable(bp->pclk);
5405b83f1527SRafal Ozieblo clk_prepare_enable(bp->hclk);
5406b83f1527SRafal Ozieblo clk_prepare_enable(bp->tx_clk);
5407b83f1527SRafal Ozieblo clk_prepare_enable(bp->rx_clk);
5408f5473d1dSHarini Katakam clk_prepare_enable(bp->tsu_clk);
54098a1c9753SHarini Katakam } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) {
54108a1c9753SHarini Katakam clk_prepare_enable(bp->tsu_clk);
54118a1c9753SHarini Katakam }
5412b83f1527SRafal Ozieblo
5413b83f1527SRafal Ozieblo return 0;
5414b83f1527SRafal Ozieblo }
5415b83f1527SRafal Ozieblo
5416d54f89afSHarini Katakam static const struct dev_pm_ops macb_pm_ops = {
5417d54f89afSHarini Katakam SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5418d54f89afSHarini Katakam SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5419d54f89afSHarini Katakam };
5420b83f1527SRafal Ozieblo
5421b83f1527SRafal Ozieblo static struct platform_driver macb_driver = {
5422b83f1527SRafal Ozieblo .probe = macb_probe,
54236b594040SUwe Kleine-König .remove_new = macb_remove,
5424b83f1527SRafal Ozieblo .driver = {
5425b83f1527SRafal Ozieblo .name = "macb",
5426b83f1527SRafal Ozieblo .of_match_table = of_match_ptr(macb_dt_ids),
5427b83f1527SRafal Ozieblo .pm = &macb_pm_ops,
5428b83f1527SRafal Ozieblo },
5429b83f1527SRafal Ozieblo };
5430b83f1527SRafal Ozieblo
5431b83f1527SRafal Ozieblo module_platform_driver(macb_driver);
5432b83f1527SRafal Ozieblo
5433b83f1527SRafal Ozieblo MODULE_LICENSE("GPL");
5434b83f1527SRafal Ozieblo MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5435b83f1527SRafal Ozieblo MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5436b83f1527SRafal Ozieblo MODULE_ALIAS("platform:macb");
5437