1b83f1527SRafal Ozieblo /* 2b83f1527SRafal Ozieblo * Cadence MACB/GEM Ethernet Controller driver 3b83f1527SRafal Ozieblo * 4b83f1527SRafal Ozieblo * Copyright (C) 2004-2006 Atmel Corporation 5b83f1527SRafal Ozieblo * 6b83f1527SRafal Ozieblo * This program is free software; you can redistribute it and/or modify 7b83f1527SRafal Ozieblo * it under the terms of the GNU General Public License version 2 as 8b83f1527SRafal Ozieblo * published by the Free Software Foundation. 9b83f1527SRafal Ozieblo */ 10b83f1527SRafal Ozieblo 11b83f1527SRafal Ozieblo #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12b83f1527SRafal Ozieblo #include <linux/clk.h> 13653e92a9SClaudiu Beznea #include <linux/crc32.h> 14b83f1527SRafal Ozieblo #include <linux/module.h> 15b83f1527SRafal Ozieblo #include <linux/moduleparam.h> 16b83f1527SRafal Ozieblo #include <linux/kernel.h> 17b83f1527SRafal Ozieblo #include <linux/types.h> 18b83f1527SRafal Ozieblo #include <linux/circ_buf.h> 19b83f1527SRafal Ozieblo #include <linux/slab.h> 20b83f1527SRafal Ozieblo #include <linux/init.h> 21b83f1527SRafal Ozieblo #include <linux/io.h> 22b83f1527SRafal Ozieblo #include <linux/gpio.h> 23b83f1527SRafal Ozieblo #include <linux/gpio/consumer.h> 24b83f1527SRafal Ozieblo #include <linux/interrupt.h> 25b83f1527SRafal Ozieblo #include <linux/netdevice.h> 26b83f1527SRafal Ozieblo #include <linux/etherdevice.h> 27b83f1527SRafal Ozieblo #include <linux/dma-mapping.h> 28b83f1527SRafal Ozieblo #include <linux/platform_data/macb.h> 29b83f1527SRafal Ozieblo #include <linux/platform_device.h> 30b83f1527SRafal Ozieblo #include <linux/phy.h> 31b83f1527SRafal Ozieblo #include <linux/of.h> 32b83f1527SRafal Ozieblo #include <linux/of_device.h> 33b83f1527SRafal Ozieblo #include <linux/of_gpio.h> 34b83f1527SRafal Ozieblo #include <linux/of_mdio.h> 35b83f1527SRafal Ozieblo #include <linux/of_net.h> 36b83f1527SRafal Ozieblo #include <linux/ip.h> 37b83f1527SRafal Ozieblo #include <linux/udp.h> 38b83f1527SRafal Ozieblo #include <linux/tcp.h> 39b83f1527SRafal Ozieblo #include "macb.h" 40b83f1527SRafal Ozieblo 41b83f1527SRafal Ozieblo #define MACB_RX_BUFFER_SIZE 128 42b83f1527SRafal Ozieblo #define RX_BUFFER_MULTIPLE 64 /* bytes */ 43b83f1527SRafal Ozieblo 44b83f1527SRafal Ozieblo #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */ 45b83f1527SRafal Ozieblo #define MIN_RX_RING_SIZE 64 46b83f1527SRafal Ozieblo #define MAX_RX_RING_SIZE 8192 47b83f1527SRafal Ozieblo #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \ 48b83f1527SRafal Ozieblo * (bp)->rx_ring_size) 49b83f1527SRafal Ozieblo 50b83f1527SRafal Ozieblo #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */ 51b83f1527SRafal Ozieblo #define MIN_TX_RING_SIZE 64 52b83f1527SRafal Ozieblo #define MAX_TX_RING_SIZE 4096 53b83f1527SRafal Ozieblo #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \ 54b83f1527SRafal Ozieblo * (bp)->tx_ring_size) 55b83f1527SRafal Ozieblo 56b83f1527SRafal Ozieblo /* level of occupied TX descriptors under which we wake up TX process */ 57b83f1527SRafal Ozieblo #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4) 58b83f1527SRafal Ozieblo 59b83f1527SRafal Ozieblo #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ 60b83f1527SRafal Ozieblo | MACB_BIT(ISR_ROVR)) 61b83f1527SRafal Ozieblo #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ 62b83f1527SRafal Ozieblo | MACB_BIT(ISR_RLE) \ 63b83f1527SRafal Ozieblo | MACB_BIT(TXERR)) 6442983885SClaudiu Beznea #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \ 6542983885SClaudiu Beznea | MACB_BIT(TXUBR)) 66b83f1527SRafal Ozieblo 67b83f1527SRafal Ozieblo /* Max length of transmit frame must be a multiple of 8 bytes */ 68b83f1527SRafal Ozieblo #define MACB_TX_LEN_ALIGN 8 69b83f1527SRafal Ozieblo #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1))) 70b83f1527SRafal Ozieblo #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1))) 71b83f1527SRafal Ozieblo 72b83f1527SRafal Ozieblo #define GEM_MTU_MIN_SIZE ETH_MIN_MTU 73f9c45ae0SDavid S. Miller #define MACB_NETIF_LSO NETIF_F_TSO 74b83f1527SRafal Ozieblo 75b83f1527SRafal Ozieblo #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0) 76b83f1527SRafal Ozieblo #define MACB_WOL_ENABLED (0x1 << 1) 77b83f1527SRafal Ozieblo 78b83f1527SRafal Ozieblo /* Graceful stop timeouts in us. We should allow up to 79b83f1527SRafal Ozieblo * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) 80b83f1527SRafal Ozieblo */ 81b83f1527SRafal Ozieblo #define MACB_HALT_TIMEOUT 1230 82b83f1527SRafal Ozieblo 83b83f1527SRafal Ozieblo /* DMA buffer descriptor might be different size 84b83f1527SRafal Ozieblo * depends on hardware configuration: 85b83f1527SRafal Ozieblo * 86b83f1527SRafal Ozieblo * 1. dma address width 32 bits: 87b83f1527SRafal Ozieblo * word 1: 32 bit address of Data Buffer 88b83f1527SRafal Ozieblo * word 2: control 89b83f1527SRafal Ozieblo * 90b83f1527SRafal Ozieblo * 2. dma address width 64 bits: 91b83f1527SRafal Ozieblo * word 1: 32 bit address of Data Buffer 92b83f1527SRafal Ozieblo * word 2: control 93b83f1527SRafal Ozieblo * word 3: upper 32 bit address of Data Buffer 94b83f1527SRafal Ozieblo * word 4: unused 95b83f1527SRafal Ozieblo * 96b83f1527SRafal Ozieblo * 3. dma address width 32 bits with hardware timestamping: 97b83f1527SRafal Ozieblo * word 1: 32 bit address of Data Buffer 98b83f1527SRafal Ozieblo * word 2: control 99b83f1527SRafal Ozieblo * word 3: timestamp word 1 100b83f1527SRafal Ozieblo * word 4: timestamp word 2 101b83f1527SRafal Ozieblo * 102b83f1527SRafal Ozieblo * 4. dma address width 64 bits with hardware timestamping: 103b83f1527SRafal Ozieblo * word 1: 32 bit address of Data Buffer 104b83f1527SRafal Ozieblo * word 2: control 105b83f1527SRafal Ozieblo * word 3: upper 32 bit address of Data Buffer 106b83f1527SRafal Ozieblo * word 4: unused 107b83f1527SRafal Ozieblo * word 5: timestamp word 1 108b83f1527SRafal Ozieblo * word 6: timestamp word 2 109b83f1527SRafal Ozieblo */ 110b83f1527SRafal Ozieblo static unsigned int macb_dma_desc_get_size(struct macb *bp) 111b83f1527SRafal Ozieblo { 112b83f1527SRafal Ozieblo #ifdef MACB_EXT_DESC 113b83f1527SRafal Ozieblo unsigned int desc_size; 114b83f1527SRafal Ozieblo 115b83f1527SRafal Ozieblo switch (bp->hw_dma_cap) { 116b83f1527SRafal Ozieblo case HW_DMA_CAP_64B: 117b83f1527SRafal Ozieblo desc_size = sizeof(struct macb_dma_desc) 118b83f1527SRafal Ozieblo + sizeof(struct macb_dma_desc_64); 119b83f1527SRafal Ozieblo break; 120b83f1527SRafal Ozieblo case HW_DMA_CAP_PTP: 121b83f1527SRafal Ozieblo desc_size = sizeof(struct macb_dma_desc) 122b83f1527SRafal Ozieblo + sizeof(struct macb_dma_desc_ptp); 123b83f1527SRafal Ozieblo break; 124b83f1527SRafal Ozieblo case HW_DMA_CAP_64B_PTP: 125b83f1527SRafal Ozieblo desc_size = sizeof(struct macb_dma_desc) 126b83f1527SRafal Ozieblo + sizeof(struct macb_dma_desc_64) 127b83f1527SRafal Ozieblo + sizeof(struct macb_dma_desc_ptp); 128b83f1527SRafal Ozieblo break; 129b83f1527SRafal Ozieblo default: 130b83f1527SRafal Ozieblo desc_size = sizeof(struct macb_dma_desc); 131b83f1527SRafal Ozieblo } 132b83f1527SRafal Ozieblo return desc_size; 133b83f1527SRafal Ozieblo #endif 134b83f1527SRafal Ozieblo return sizeof(struct macb_dma_desc); 135b83f1527SRafal Ozieblo } 136b83f1527SRafal Ozieblo 137b83f1527SRafal Ozieblo static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx) 138b83f1527SRafal Ozieblo { 139b83f1527SRafal Ozieblo #ifdef MACB_EXT_DESC 140b83f1527SRafal Ozieblo switch (bp->hw_dma_cap) { 141b83f1527SRafal Ozieblo case HW_DMA_CAP_64B: 142b83f1527SRafal Ozieblo case HW_DMA_CAP_PTP: 143b83f1527SRafal Ozieblo desc_idx <<= 1; 144b83f1527SRafal Ozieblo break; 145b83f1527SRafal Ozieblo case HW_DMA_CAP_64B_PTP: 146b83f1527SRafal Ozieblo desc_idx *= 3; 147b83f1527SRafal Ozieblo break; 148b83f1527SRafal Ozieblo default: 149b83f1527SRafal Ozieblo break; 150b83f1527SRafal Ozieblo } 151b83f1527SRafal Ozieblo #endif 152b83f1527SRafal Ozieblo return desc_idx; 153b83f1527SRafal Ozieblo } 154b83f1527SRafal Ozieblo 155b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 156b83f1527SRafal Ozieblo static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc) 157b83f1527SRafal Ozieblo { 158b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) 159b83f1527SRafal Ozieblo return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc)); 160b83f1527SRafal Ozieblo return NULL; 161b83f1527SRafal Ozieblo } 162b83f1527SRafal Ozieblo #endif 163b83f1527SRafal Ozieblo 164b83f1527SRafal Ozieblo /* Ring buffer accessors */ 165b83f1527SRafal Ozieblo static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index) 166b83f1527SRafal Ozieblo { 167b83f1527SRafal Ozieblo return index & (bp->tx_ring_size - 1); 168b83f1527SRafal Ozieblo } 169b83f1527SRafal Ozieblo 170b83f1527SRafal Ozieblo static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue, 171b83f1527SRafal Ozieblo unsigned int index) 172b83f1527SRafal Ozieblo { 173b83f1527SRafal Ozieblo index = macb_tx_ring_wrap(queue->bp, index); 174b83f1527SRafal Ozieblo index = macb_adj_dma_desc_idx(queue->bp, index); 175b83f1527SRafal Ozieblo return &queue->tx_ring[index]; 176b83f1527SRafal Ozieblo } 177b83f1527SRafal Ozieblo 178b83f1527SRafal Ozieblo static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue, 179b83f1527SRafal Ozieblo unsigned int index) 180b83f1527SRafal Ozieblo { 181b83f1527SRafal Ozieblo return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)]; 182b83f1527SRafal Ozieblo } 183b83f1527SRafal Ozieblo 184b83f1527SRafal Ozieblo static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index) 185b83f1527SRafal Ozieblo { 186b83f1527SRafal Ozieblo dma_addr_t offset; 187b83f1527SRafal Ozieblo 188b83f1527SRafal Ozieblo offset = macb_tx_ring_wrap(queue->bp, index) * 189b83f1527SRafal Ozieblo macb_dma_desc_get_size(queue->bp); 190b83f1527SRafal Ozieblo 191b83f1527SRafal Ozieblo return queue->tx_ring_dma + offset; 192b83f1527SRafal Ozieblo } 193b83f1527SRafal Ozieblo 194b83f1527SRafal Ozieblo static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index) 195b83f1527SRafal Ozieblo { 196b83f1527SRafal Ozieblo return index & (bp->rx_ring_size - 1); 197b83f1527SRafal Ozieblo } 198b83f1527SRafal Ozieblo 199ae1f2a56SRafal Ozieblo static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index) 200b83f1527SRafal Ozieblo { 201ae1f2a56SRafal Ozieblo index = macb_rx_ring_wrap(queue->bp, index); 202ae1f2a56SRafal Ozieblo index = macb_adj_dma_desc_idx(queue->bp, index); 203ae1f2a56SRafal Ozieblo return &queue->rx_ring[index]; 204b83f1527SRafal Ozieblo } 205b83f1527SRafal Ozieblo 206ae1f2a56SRafal Ozieblo static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index) 207b83f1527SRafal Ozieblo { 208ae1f2a56SRafal Ozieblo return queue->rx_buffers + queue->bp->rx_buffer_size * 209ae1f2a56SRafal Ozieblo macb_rx_ring_wrap(queue->bp, index); 210b83f1527SRafal Ozieblo } 211b83f1527SRafal Ozieblo 212b83f1527SRafal Ozieblo /* I/O accessors */ 213b83f1527SRafal Ozieblo static u32 hw_readl_native(struct macb *bp, int offset) 214b83f1527SRafal Ozieblo { 215b83f1527SRafal Ozieblo return __raw_readl(bp->regs + offset); 216b83f1527SRafal Ozieblo } 217b83f1527SRafal Ozieblo 218b83f1527SRafal Ozieblo static void hw_writel_native(struct macb *bp, int offset, u32 value) 219b83f1527SRafal Ozieblo { 220b83f1527SRafal Ozieblo __raw_writel(value, bp->regs + offset); 221b83f1527SRafal Ozieblo } 222b83f1527SRafal Ozieblo 223b83f1527SRafal Ozieblo static u32 hw_readl(struct macb *bp, int offset) 224b83f1527SRafal Ozieblo { 225b83f1527SRafal Ozieblo return readl_relaxed(bp->regs + offset); 226b83f1527SRafal Ozieblo } 227b83f1527SRafal Ozieblo 228b83f1527SRafal Ozieblo static void hw_writel(struct macb *bp, int offset, u32 value) 229b83f1527SRafal Ozieblo { 230b83f1527SRafal Ozieblo writel_relaxed(value, bp->regs + offset); 231b83f1527SRafal Ozieblo } 232b83f1527SRafal Ozieblo 233b83f1527SRafal Ozieblo /* Find the CPU endianness by using the loopback bit of NCR register. When the 234b83f1527SRafal Ozieblo * CPU is in big endian we need to program swapped mode for management 235b83f1527SRafal Ozieblo * descriptor access. 236b83f1527SRafal Ozieblo */ 237b83f1527SRafal Ozieblo static bool hw_is_native_io(void __iomem *addr) 238b83f1527SRafal Ozieblo { 239b83f1527SRafal Ozieblo u32 value = MACB_BIT(LLB); 240b83f1527SRafal Ozieblo 241b83f1527SRafal Ozieblo __raw_writel(value, addr + MACB_NCR); 242b83f1527SRafal Ozieblo value = __raw_readl(addr + MACB_NCR); 243b83f1527SRafal Ozieblo 244b83f1527SRafal Ozieblo /* Write 0 back to disable everything */ 245b83f1527SRafal Ozieblo __raw_writel(0, addr + MACB_NCR); 246b83f1527SRafal Ozieblo 247b83f1527SRafal Ozieblo return value == MACB_BIT(LLB); 248b83f1527SRafal Ozieblo } 249b83f1527SRafal Ozieblo 250b83f1527SRafal Ozieblo static bool hw_is_gem(void __iomem *addr, bool native_io) 251b83f1527SRafal Ozieblo { 252b83f1527SRafal Ozieblo u32 id; 253b83f1527SRafal Ozieblo 254b83f1527SRafal Ozieblo if (native_io) 255b83f1527SRafal Ozieblo id = __raw_readl(addr + MACB_MID); 256b83f1527SRafal Ozieblo else 257b83f1527SRafal Ozieblo id = readl_relaxed(addr + MACB_MID); 258b83f1527SRafal Ozieblo 259b83f1527SRafal Ozieblo return MACB_BFEXT(IDNUM, id) >= 0x2; 260b83f1527SRafal Ozieblo } 261b83f1527SRafal Ozieblo 262b83f1527SRafal Ozieblo static void macb_set_hwaddr(struct macb *bp) 263b83f1527SRafal Ozieblo { 264b83f1527SRafal Ozieblo u32 bottom; 265b83f1527SRafal Ozieblo u16 top; 266b83f1527SRafal Ozieblo 267b83f1527SRafal Ozieblo bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); 268b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA1B, bottom); 269b83f1527SRafal Ozieblo top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); 270b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA1T, top); 271b83f1527SRafal Ozieblo 272b83f1527SRafal Ozieblo /* Clear unused address register sets */ 273b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA2B, 0); 274b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA2T, 0); 275b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA3B, 0); 276b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA3T, 0); 277b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA4B, 0); 278b83f1527SRafal Ozieblo macb_or_gem_writel(bp, SA4T, 0); 279b83f1527SRafal Ozieblo } 280b83f1527SRafal Ozieblo 281b83f1527SRafal Ozieblo static void macb_get_hwaddr(struct macb *bp) 282b83f1527SRafal Ozieblo { 283b83f1527SRafal Ozieblo struct macb_platform_data *pdata; 284b83f1527SRafal Ozieblo u32 bottom; 285b83f1527SRafal Ozieblo u16 top; 286b83f1527SRafal Ozieblo u8 addr[6]; 287b83f1527SRafal Ozieblo int i; 288b83f1527SRafal Ozieblo 289b83f1527SRafal Ozieblo pdata = dev_get_platdata(&bp->pdev->dev); 290b83f1527SRafal Ozieblo 291b83f1527SRafal Ozieblo /* Check all 4 address register for valid address */ 292b83f1527SRafal Ozieblo for (i = 0; i < 4; i++) { 293b83f1527SRafal Ozieblo bottom = macb_or_gem_readl(bp, SA1B + i * 8); 294b83f1527SRafal Ozieblo top = macb_or_gem_readl(bp, SA1T + i * 8); 295b83f1527SRafal Ozieblo 296b83f1527SRafal Ozieblo if (pdata && pdata->rev_eth_addr) { 297b83f1527SRafal Ozieblo addr[5] = bottom & 0xff; 298b83f1527SRafal Ozieblo addr[4] = (bottom >> 8) & 0xff; 299b83f1527SRafal Ozieblo addr[3] = (bottom >> 16) & 0xff; 300b83f1527SRafal Ozieblo addr[2] = (bottom >> 24) & 0xff; 301b83f1527SRafal Ozieblo addr[1] = top & 0xff; 302b83f1527SRafal Ozieblo addr[0] = (top & 0xff00) >> 8; 303b83f1527SRafal Ozieblo } else { 304b83f1527SRafal Ozieblo addr[0] = bottom & 0xff; 305b83f1527SRafal Ozieblo addr[1] = (bottom >> 8) & 0xff; 306b83f1527SRafal Ozieblo addr[2] = (bottom >> 16) & 0xff; 307b83f1527SRafal Ozieblo addr[3] = (bottom >> 24) & 0xff; 308b83f1527SRafal Ozieblo addr[4] = top & 0xff; 309b83f1527SRafal Ozieblo addr[5] = (top >> 8) & 0xff; 310b83f1527SRafal Ozieblo } 311b83f1527SRafal Ozieblo 312b83f1527SRafal Ozieblo if (is_valid_ether_addr(addr)) { 313b83f1527SRafal Ozieblo memcpy(bp->dev->dev_addr, addr, sizeof(addr)); 314b83f1527SRafal Ozieblo return; 315b83f1527SRafal Ozieblo } 316b83f1527SRafal Ozieblo } 317b83f1527SRafal Ozieblo 318b83f1527SRafal Ozieblo dev_info(&bp->pdev->dev, "invalid hw address, using random\n"); 319b83f1527SRafal Ozieblo eth_hw_addr_random(bp->dev); 320b83f1527SRafal Ozieblo } 321b83f1527SRafal Ozieblo 322b83f1527SRafal Ozieblo static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 323b83f1527SRafal Ozieblo { 324b83f1527SRafal Ozieblo struct macb *bp = bus->priv; 325b83f1527SRafal Ozieblo int value; 326b83f1527SRafal Ozieblo 327b83f1527SRafal Ozieblo macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) 328b83f1527SRafal Ozieblo | MACB_BF(RW, MACB_MAN_READ) 329b83f1527SRafal Ozieblo | MACB_BF(PHYA, mii_id) 330b83f1527SRafal Ozieblo | MACB_BF(REGA, regnum) 331b83f1527SRafal Ozieblo | MACB_BF(CODE, MACB_MAN_CODE))); 332b83f1527SRafal Ozieblo 333b83f1527SRafal Ozieblo /* wait for end of transfer */ 334b83f1527SRafal Ozieblo while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) 335b83f1527SRafal Ozieblo cpu_relax(); 336b83f1527SRafal Ozieblo 337b83f1527SRafal Ozieblo value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); 338b83f1527SRafal Ozieblo 339b83f1527SRafal Ozieblo return value; 340b83f1527SRafal Ozieblo } 341b83f1527SRafal Ozieblo 342b83f1527SRafal Ozieblo static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 343b83f1527SRafal Ozieblo u16 value) 344b83f1527SRafal Ozieblo { 345b83f1527SRafal Ozieblo struct macb *bp = bus->priv; 346b83f1527SRafal Ozieblo 347b83f1527SRafal Ozieblo macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) 348b83f1527SRafal Ozieblo | MACB_BF(RW, MACB_MAN_WRITE) 349b83f1527SRafal Ozieblo | MACB_BF(PHYA, mii_id) 350b83f1527SRafal Ozieblo | MACB_BF(REGA, regnum) 351b83f1527SRafal Ozieblo | MACB_BF(CODE, MACB_MAN_CODE) 352b83f1527SRafal Ozieblo | MACB_BF(DATA, value))); 353b83f1527SRafal Ozieblo 354b83f1527SRafal Ozieblo /* wait for end of transfer */ 355b83f1527SRafal Ozieblo while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) 356b83f1527SRafal Ozieblo cpu_relax(); 357b83f1527SRafal Ozieblo 358b83f1527SRafal Ozieblo return 0; 359b83f1527SRafal Ozieblo } 360b83f1527SRafal Ozieblo 361b83f1527SRafal Ozieblo /** 362b83f1527SRafal Ozieblo * macb_set_tx_clk() - Set a clock to a new frequency 363b83f1527SRafal Ozieblo * @clk Pointer to the clock to change 364b83f1527SRafal Ozieblo * @rate New frequency in Hz 365b83f1527SRafal Ozieblo * @dev Pointer to the struct net_device 366b83f1527SRafal Ozieblo */ 367b83f1527SRafal Ozieblo static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) 368b83f1527SRafal Ozieblo { 369b83f1527SRafal Ozieblo long ferr, rate, rate_rounded; 370b83f1527SRafal Ozieblo 371b83f1527SRafal Ozieblo if (!clk) 372b83f1527SRafal Ozieblo return; 373b83f1527SRafal Ozieblo 374b83f1527SRafal Ozieblo switch (speed) { 375b83f1527SRafal Ozieblo case SPEED_10: 376b83f1527SRafal Ozieblo rate = 2500000; 377b83f1527SRafal Ozieblo break; 378b83f1527SRafal Ozieblo case SPEED_100: 379b83f1527SRafal Ozieblo rate = 25000000; 380b83f1527SRafal Ozieblo break; 381b83f1527SRafal Ozieblo case SPEED_1000: 382b83f1527SRafal Ozieblo rate = 125000000; 383b83f1527SRafal Ozieblo break; 384b83f1527SRafal Ozieblo default: 385b83f1527SRafal Ozieblo return; 386b83f1527SRafal Ozieblo } 387b83f1527SRafal Ozieblo 388b83f1527SRafal Ozieblo rate_rounded = clk_round_rate(clk, rate); 389b83f1527SRafal Ozieblo if (rate_rounded < 0) 390b83f1527SRafal Ozieblo return; 391b83f1527SRafal Ozieblo 392b83f1527SRafal Ozieblo /* RGMII allows 50 ppm frequency error. Test and warn if this limit 393b83f1527SRafal Ozieblo * is not satisfied. 394b83f1527SRafal Ozieblo */ 395b83f1527SRafal Ozieblo ferr = abs(rate_rounded - rate); 396b83f1527SRafal Ozieblo ferr = DIV_ROUND_UP(ferr, rate / 100000); 397b83f1527SRafal Ozieblo if (ferr > 5) 398b83f1527SRafal Ozieblo netdev_warn(dev, "unable to generate target frequency: %ld Hz\n", 399b83f1527SRafal Ozieblo rate); 400b83f1527SRafal Ozieblo 401b83f1527SRafal Ozieblo if (clk_set_rate(clk, rate_rounded)) 402b83f1527SRafal Ozieblo netdev_err(dev, "adjusting tx_clk failed.\n"); 403b83f1527SRafal Ozieblo } 404b83f1527SRafal Ozieblo 405b83f1527SRafal Ozieblo static void macb_handle_link_change(struct net_device *dev) 406b83f1527SRafal Ozieblo { 407b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 408b83f1527SRafal Ozieblo struct phy_device *phydev = dev->phydev; 409b83f1527SRafal Ozieblo unsigned long flags; 410b83f1527SRafal Ozieblo int status_change = 0; 411b83f1527SRafal Ozieblo 412b83f1527SRafal Ozieblo spin_lock_irqsave(&bp->lock, flags); 413b83f1527SRafal Ozieblo 414b83f1527SRafal Ozieblo if (phydev->link) { 415b83f1527SRafal Ozieblo if ((bp->speed != phydev->speed) || 416b83f1527SRafal Ozieblo (bp->duplex != phydev->duplex)) { 417b83f1527SRafal Ozieblo u32 reg; 418b83f1527SRafal Ozieblo 419b83f1527SRafal Ozieblo reg = macb_readl(bp, NCFGR); 420b83f1527SRafal Ozieblo reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 421b83f1527SRafal Ozieblo if (macb_is_gem(bp)) 422b83f1527SRafal Ozieblo reg &= ~GEM_BIT(GBE); 423b83f1527SRafal Ozieblo 424b83f1527SRafal Ozieblo if (phydev->duplex) 425b83f1527SRafal Ozieblo reg |= MACB_BIT(FD); 426b83f1527SRafal Ozieblo if (phydev->speed == SPEED_100) 427b83f1527SRafal Ozieblo reg |= MACB_BIT(SPD); 428b83f1527SRafal Ozieblo if (phydev->speed == SPEED_1000 && 429b83f1527SRafal Ozieblo bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) 430b83f1527SRafal Ozieblo reg |= GEM_BIT(GBE); 431b83f1527SRafal Ozieblo 432b83f1527SRafal Ozieblo macb_or_gem_writel(bp, NCFGR, reg); 433b83f1527SRafal Ozieblo 434b83f1527SRafal Ozieblo bp->speed = phydev->speed; 435b83f1527SRafal Ozieblo bp->duplex = phydev->duplex; 436b83f1527SRafal Ozieblo status_change = 1; 437b83f1527SRafal Ozieblo } 438b83f1527SRafal Ozieblo } 439b83f1527SRafal Ozieblo 440b83f1527SRafal Ozieblo if (phydev->link != bp->link) { 441b83f1527SRafal Ozieblo if (!phydev->link) { 442b83f1527SRafal Ozieblo bp->speed = 0; 443b83f1527SRafal Ozieblo bp->duplex = -1; 444b83f1527SRafal Ozieblo } 445b83f1527SRafal Ozieblo bp->link = phydev->link; 446b83f1527SRafal Ozieblo 447b83f1527SRafal Ozieblo status_change = 1; 448b83f1527SRafal Ozieblo } 449b83f1527SRafal Ozieblo 450b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags); 451b83f1527SRafal Ozieblo 452b83f1527SRafal Ozieblo if (status_change) { 453b83f1527SRafal Ozieblo if (phydev->link) { 454b83f1527SRafal Ozieblo /* Update the TX clock rate if and only if the link is 455b83f1527SRafal Ozieblo * up and there has been a link change. 456b83f1527SRafal Ozieblo */ 457b83f1527SRafal Ozieblo macb_set_tx_clk(bp->tx_clk, phydev->speed, dev); 458b83f1527SRafal Ozieblo 459b83f1527SRafal Ozieblo netif_carrier_on(dev); 460b83f1527SRafal Ozieblo netdev_info(dev, "link up (%d/%s)\n", 461b83f1527SRafal Ozieblo phydev->speed, 462b83f1527SRafal Ozieblo phydev->duplex == DUPLEX_FULL ? 463b83f1527SRafal Ozieblo "Full" : "Half"); 464b83f1527SRafal Ozieblo } else { 465b83f1527SRafal Ozieblo netif_carrier_off(dev); 466b83f1527SRafal Ozieblo netdev_info(dev, "link down\n"); 467b83f1527SRafal Ozieblo } 468b83f1527SRafal Ozieblo } 469b83f1527SRafal Ozieblo } 470b83f1527SRafal Ozieblo 471b83f1527SRafal Ozieblo /* based on au1000_eth. c*/ 472b83f1527SRafal Ozieblo static int macb_mii_probe(struct net_device *dev) 473b83f1527SRafal Ozieblo { 474b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 475b83f1527SRafal Ozieblo struct macb_platform_data *pdata; 476b83f1527SRafal Ozieblo struct phy_device *phydev; 477739de9a1SBrad Mouring struct device_node *np; 478739de9a1SBrad Mouring int phy_irq, ret, i; 479739de9a1SBrad Mouring 480739de9a1SBrad Mouring pdata = dev_get_platdata(&bp->pdev->dev); 481739de9a1SBrad Mouring np = bp->pdev->dev.of_node; 482739de9a1SBrad Mouring ret = 0; 483739de9a1SBrad Mouring 484739de9a1SBrad Mouring if (np) { 485739de9a1SBrad Mouring if (of_phy_is_fixed_link(np)) { 486739de9a1SBrad Mouring bp->phy_node = of_node_get(np); 487739de9a1SBrad Mouring } else { 4882105a5d3SBrad Mouring bp->phy_node = of_parse_phandle(np, "phy-handle", 0); 4892105a5d3SBrad Mouring /* fallback to standard phy registration if no 4902105a5d3SBrad Mouring * phy-handle was found nor any phy found during 4912105a5d3SBrad Mouring * dt phy registration 492739de9a1SBrad Mouring */ 4932105a5d3SBrad Mouring if (!bp->phy_node && !phy_find_first(bp->mii_bus)) { 494739de9a1SBrad Mouring for (i = 0; i < PHY_MAX_ADDR; i++) { 495739de9a1SBrad Mouring struct phy_device *phydev; 496739de9a1SBrad Mouring 497739de9a1SBrad Mouring phydev = mdiobus_scan(bp->mii_bus, i); 498739de9a1SBrad Mouring if (IS_ERR(phydev) && 499739de9a1SBrad Mouring PTR_ERR(phydev) != -ENODEV) { 500739de9a1SBrad Mouring ret = PTR_ERR(phydev); 501739de9a1SBrad Mouring break; 502739de9a1SBrad Mouring } 503739de9a1SBrad Mouring } 504739de9a1SBrad Mouring 505739de9a1SBrad Mouring if (ret) 506739de9a1SBrad Mouring return -ENODEV; 507739de9a1SBrad Mouring } 508739de9a1SBrad Mouring } 509739de9a1SBrad Mouring } 510b83f1527SRafal Ozieblo 511b83f1527SRafal Ozieblo if (bp->phy_node) { 512b83f1527SRafal Ozieblo phydev = of_phy_connect(dev, bp->phy_node, 513b83f1527SRafal Ozieblo &macb_handle_link_change, 0, 514b83f1527SRafal Ozieblo bp->phy_interface); 515b83f1527SRafal Ozieblo if (!phydev) 516b83f1527SRafal Ozieblo return -ENODEV; 517b83f1527SRafal Ozieblo } else { 518b83f1527SRafal Ozieblo phydev = phy_find_first(bp->mii_bus); 519b83f1527SRafal Ozieblo if (!phydev) { 520b83f1527SRafal Ozieblo netdev_err(dev, "no PHY found\n"); 521b83f1527SRafal Ozieblo return -ENXIO; 522b83f1527SRafal Ozieblo } 523b83f1527SRafal Ozieblo 524b83f1527SRafal Ozieblo if (pdata) { 525b83f1527SRafal Ozieblo if (gpio_is_valid(pdata->phy_irq_pin)) { 526b83f1527SRafal Ozieblo ret = devm_gpio_request(&bp->pdev->dev, 527b83f1527SRafal Ozieblo pdata->phy_irq_pin, "phy int"); 528b83f1527SRafal Ozieblo if (!ret) { 529b83f1527SRafal Ozieblo phy_irq = gpio_to_irq(pdata->phy_irq_pin); 530b83f1527SRafal Ozieblo phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq; 531b83f1527SRafal Ozieblo } 532b83f1527SRafal Ozieblo } else { 533b83f1527SRafal Ozieblo phydev->irq = PHY_POLL; 534b83f1527SRafal Ozieblo } 535b83f1527SRafal Ozieblo } 536b83f1527SRafal Ozieblo 537b83f1527SRafal Ozieblo /* attach the mac to the phy */ 538b83f1527SRafal Ozieblo ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 539b83f1527SRafal Ozieblo bp->phy_interface); 540b83f1527SRafal Ozieblo if (ret) { 541b83f1527SRafal Ozieblo netdev_err(dev, "Could not attach to PHY\n"); 542b83f1527SRafal Ozieblo return ret; 543b83f1527SRafal Ozieblo } 544b83f1527SRafal Ozieblo } 545b83f1527SRafal Ozieblo 546b83f1527SRafal Ozieblo /* mask with MAC supported features */ 547b83f1527SRafal Ozieblo if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) 54858056c1eSAndrew Lunn phy_set_max_speed(phydev, SPEED_1000); 549b83f1527SRafal Ozieblo else 55058056c1eSAndrew Lunn phy_set_max_speed(phydev, SPEED_100); 551b83f1527SRafal Ozieblo 552b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF) 55341124fa6SAndrew Lunn phy_remove_link_mode(phydev, 55441124fa6SAndrew Lunn ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 555b83f1527SRafal Ozieblo 556b83f1527SRafal Ozieblo bp->link = 0; 557b83f1527SRafal Ozieblo bp->speed = 0; 558b83f1527SRafal Ozieblo bp->duplex = -1; 559b83f1527SRafal Ozieblo 560b83f1527SRafal Ozieblo return 0; 561b83f1527SRafal Ozieblo } 562b83f1527SRafal Ozieblo 563b83f1527SRafal Ozieblo static int macb_mii_init(struct macb *bp) 564b83f1527SRafal Ozieblo { 565b83f1527SRafal Ozieblo struct macb_platform_data *pdata; 566b83f1527SRafal Ozieblo struct device_node *np; 567ab5f1105SAhmad Fatoum int err = -ENXIO; 568b83f1527SRafal Ozieblo 569b83f1527SRafal Ozieblo /* Enable management port */ 570b83f1527SRafal Ozieblo macb_writel(bp, NCR, MACB_BIT(MPE)); 571b83f1527SRafal Ozieblo 572b83f1527SRafal Ozieblo bp->mii_bus = mdiobus_alloc(); 573b83f1527SRafal Ozieblo if (!bp->mii_bus) { 574b83f1527SRafal Ozieblo err = -ENOMEM; 575b83f1527SRafal Ozieblo goto err_out; 576b83f1527SRafal Ozieblo } 577b83f1527SRafal Ozieblo 578b83f1527SRafal Ozieblo bp->mii_bus->name = "MACB_mii_bus"; 579b83f1527SRafal Ozieblo bp->mii_bus->read = &macb_mdio_read; 580b83f1527SRafal Ozieblo bp->mii_bus->write = &macb_mdio_write; 581b83f1527SRafal Ozieblo snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 582b83f1527SRafal Ozieblo bp->pdev->name, bp->pdev->id); 583b83f1527SRafal Ozieblo bp->mii_bus->priv = bp; 584b83f1527SRafal Ozieblo bp->mii_bus->parent = &bp->pdev->dev; 585b83f1527SRafal Ozieblo pdata = dev_get_platdata(&bp->pdev->dev); 586b83f1527SRafal Ozieblo 587b83f1527SRafal Ozieblo dev_set_drvdata(&bp->dev->dev, bp->mii_bus); 588b83f1527SRafal Ozieblo 589b83f1527SRafal Ozieblo np = bp->pdev->dev.of_node; 590ab5f1105SAhmad Fatoum if (np && of_phy_is_fixed_link(np)) { 591ab5f1105SAhmad Fatoum if (of_phy_register_fixed_link(np) < 0) { 592ab5f1105SAhmad Fatoum dev_err(&bp->pdev->dev, 593ab5f1105SAhmad Fatoum "broken fixed-link specification %pOF\n", np); 594ab5f1105SAhmad Fatoum goto err_out_free_mdiobus; 595ab5f1105SAhmad Fatoum } 596ab5f1105SAhmad Fatoum 597ab5f1105SAhmad Fatoum err = mdiobus_register(bp->mii_bus); 598ab5f1105SAhmad Fatoum } else { 599b83f1527SRafal Ozieblo if (pdata) 600b83f1527SRafal Ozieblo bp->mii_bus->phy_mask = pdata->phy_mask; 601b83f1527SRafal Ozieblo 60200e798c7SFlorian Fainelli err = of_mdiobus_register(bp->mii_bus, np); 603ab5f1105SAhmad Fatoum } 604ab5f1105SAhmad Fatoum 605b83f1527SRafal Ozieblo if (err) 606ab5f1105SAhmad Fatoum goto err_out_free_fixed_link; 607b83f1527SRafal Ozieblo 608b83f1527SRafal Ozieblo err = macb_mii_probe(bp->dev); 609b83f1527SRafal Ozieblo if (err) 610b83f1527SRafal Ozieblo goto err_out_unregister_bus; 611b83f1527SRafal Ozieblo 612b83f1527SRafal Ozieblo return 0; 613b83f1527SRafal Ozieblo 614b83f1527SRafal Ozieblo err_out_unregister_bus: 615b83f1527SRafal Ozieblo mdiobus_unregister(bp->mii_bus); 616ab5f1105SAhmad Fatoum err_out_free_fixed_link: 6179ce98140SMichael Grzeschik if (np && of_phy_is_fixed_link(np)) 6189ce98140SMichael Grzeschik of_phy_deregister_fixed_link(np); 619739de9a1SBrad Mouring err_out_free_mdiobus: 620739de9a1SBrad Mouring of_node_put(bp->phy_node); 621b83f1527SRafal Ozieblo mdiobus_free(bp->mii_bus); 622b83f1527SRafal Ozieblo err_out: 623b83f1527SRafal Ozieblo return err; 624b83f1527SRafal Ozieblo } 625b83f1527SRafal Ozieblo 626b83f1527SRafal Ozieblo static void macb_update_stats(struct macb *bp) 627b83f1527SRafal Ozieblo { 628b83f1527SRafal Ozieblo u32 *p = &bp->hw_stats.macb.rx_pause_frames; 629b83f1527SRafal Ozieblo u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; 630b83f1527SRafal Ozieblo int offset = MACB_PFR; 631b83f1527SRafal Ozieblo 632b83f1527SRafal Ozieblo WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); 633b83f1527SRafal Ozieblo 634b83f1527SRafal Ozieblo for (; p < end; p++, offset += 4) 635b83f1527SRafal Ozieblo *p += bp->macb_reg_readl(bp, offset); 636b83f1527SRafal Ozieblo } 637b83f1527SRafal Ozieblo 638b83f1527SRafal Ozieblo static int macb_halt_tx(struct macb *bp) 639b83f1527SRafal Ozieblo { 640b83f1527SRafal Ozieblo unsigned long halt_time, timeout; 641b83f1527SRafal Ozieblo u32 status; 642b83f1527SRafal Ozieblo 643b83f1527SRafal Ozieblo macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); 644b83f1527SRafal Ozieblo 645b83f1527SRafal Ozieblo timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT); 646b83f1527SRafal Ozieblo do { 647b83f1527SRafal Ozieblo halt_time = jiffies; 648b83f1527SRafal Ozieblo status = macb_readl(bp, TSR); 649b83f1527SRafal Ozieblo if (!(status & MACB_BIT(TGO))) 650b83f1527SRafal Ozieblo return 0; 651b83f1527SRafal Ozieblo 65216fe10cfSJia-Ju Bai udelay(250); 653b83f1527SRafal Ozieblo } while (time_before(halt_time, timeout)); 654b83f1527SRafal Ozieblo 655b83f1527SRafal Ozieblo return -ETIMEDOUT; 656b83f1527SRafal Ozieblo } 657b83f1527SRafal Ozieblo 658b83f1527SRafal Ozieblo static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb) 659b83f1527SRafal Ozieblo { 660b83f1527SRafal Ozieblo if (tx_skb->mapping) { 661b83f1527SRafal Ozieblo if (tx_skb->mapped_as_page) 662b83f1527SRafal Ozieblo dma_unmap_page(&bp->pdev->dev, tx_skb->mapping, 663b83f1527SRafal Ozieblo tx_skb->size, DMA_TO_DEVICE); 664b83f1527SRafal Ozieblo else 665b83f1527SRafal Ozieblo dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, 666b83f1527SRafal Ozieblo tx_skb->size, DMA_TO_DEVICE); 667b83f1527SRafal Ozieblo tx_skb->mapping = 0; 668b83f1527SRafal Ozieblo } 669b83f1527SRafal Ozieblo 670b83f1527SRafal Ozieblo if (tx_skb->skb) { 671b83f1527SRafal Ozieblo dev_kfree_skb_any(tx_skb->skb); 672b83f1527SRafal Ozieblo tx_skb->skb = NULL; 673b83f1527SRafal Ozieblo } 674b83f1527SRafal Ozieblo } 675b83f1527SRafal Ozieblo 676b83f1527SRafal Ozieblo static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr) 677b83f1527SRafal Ozieblo { 678b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 679b83f1527SRafal Ozieblo struct macb_dma_desc_64 *desc_64; 680b83f1527SRafal Ozieblo 681b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) { 682b83f1527SRafal Ozieblo desc_64 = macb_64b_desc(bp, desc); 683b83f1527SRafal Ozieblo desc_64->addrh = upper_32_bits(addr); 684e100a897SAnssi Hannula /* The low bits of RX address contain the RX_USED bit, clearing 685e100a897SAnssi Hannula * of which allows packet RX. Make sure the high bits are also 686e100a897SAnssi Hannula * visible to HW at that point. 687e100a897SAnssi Hannula */ 688e100a897SAnssi Hannula dma_wmb(); 689b83f1527SRafal Ozieblo } 690b83f1527SRafal Ozieblo #endif 691b83f1527SRafal Ozieblo desc->addr = lower_32_bits(addr); 692b83f1527SRafal Ozieblo } 693b83f1527SRafal Ozieblo 694b83f1527SRafal Ozieblo static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc) 695b83f1527SRafal Ozieblo { 696b83f1527SRafal Ozieblo dma_addr_t addr = 0; 697b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 698b83f1527SRafal Ozieblo struct macb_dma_desc_64 *desc_64; 699b83f1527SRafal Ozieblo 700b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) { 701b83f1527SRafal Ozieblo desc_64 = macb_64b_desc(bp, desc); 702b83f1527SRafal Ozieblo addr = ((u64)(desc_64->addrh) << 32); 703b83f1527SRafal Ozieblo } 704b83f1527SRafal Ozieblo #endif 705b83f1527SRafal Ozieblo addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); 706b83f1527SRafal Ozieblo return addr; 707b83f1527SRafal Ozieblo } 708b83f1527SRafal Ozieblo 709b83f1527SRafal Ozieblo static void macb_tx_error_task(struct work_struct *work) 710b83f1527SRafal Ozieblo { 711b83f1527SRafal Ozieblo struct macb_queue *queue = container_of(work, struct macb_queue, 712b83f1527SRafal Ozieblo tx_error_task); 713b83f1527SRafal Ozieblo struct macb *bp = queue->bp; 714b83f1527SRafal Ozieblo struct macb_tx_skb *tx_skb; 715b83f1527SRafal Ozieblo struct macb_dma_desc *desc; 716b83f1527SRafal Ozieblo struct sk_buff *skb; 717b83f1527SRafal Ozieblo unsigned int tail; 718b83f1527SRafal Ozieblo unsigned long flags; 719b83f1527SRafal Ozieblo 720b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n", 721b83f1527SRafal Ozieblo (unsigned int)(queue - bp->queues), 722b83f1527SRafal Ozieblo queue->tx_tail, queue->tx_head); 723b83f1527SRafal Ozieblo 724b83f1527SRafal Ozieblo /* Prevent the queue IRQ handlers from running: each of them may call 725b83f1527SRafal Ozieblo * macb_tx_interrupt(), which in turn may call netif_wake_subqueue(). 726b83f1527SRafal Ozieblo * As explained below, we have to halt the transmission before updating 727b83f1527SRafal Ozieblo * TBQP registers so we call netif_tx_stop_all_queues() to notify the 728b83f1527SRafal Ozieblo * network engine about the macb/gem being halted. 729b83f1527SRafal Ozieblo */ 730b83f1527SRafal Ozieblo spin_lock_irqsave(&bp->lock, flags); 731b83f1527SRafal Ozieblo 732b83f1527SRafal Ozieblo /* Make sure nobody is trying to queue up new packets */ 733b83f1527SRafal Ozieblo netif_tx_stop_all_queues(bp->dev); 734b83f1527SRafal Ozieblo 735b83f1527SRafal Ozieblo /* Stop transmission now 736b83f1527SRafal Ozieblo * (in case we have just queued new packets) 737b83f1527SRafal Ozieblo * macb/gem must be halted to write TBQP register 738b83f1527SRafal Ozieblo */ 739b83f1527SRafal Ozieblo if (macb_halt_tx(bp)) 740b83f1527SRafal Ozieblo /* Just complain for now, reinitializing TX path can be good */ 741b83f1527SRafal Ozieblo netdev_err(bp->dev, "BUG: halt tx timed out\n"); 742b83f1527SRafal Ozieblo 743b83f1527SRafal Ozieblo /* Treat frames in TX queue including the ones that caused the error. 744b83f1527SRafal Ozieblo * Free transmit buffers in upper layer. 745b83f1527SRafal Ozieblo */ 746b83f1527SRafal Ozieblo for (tail = queue->tx_tail; tail != queue->tx_head; tail++) { 747b83f1527SRafal Ozieblo u32 ctrl; 748b83f1527SRafal Ozieblo 749b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, tail); 750b83f1527SRafal Ozieblo ctrl = desc->ctrl; 751b83f1527SRafal Ozieblo tx_skb = macb_tx_skb(queue, tail); 752b83f1527SRafal Ozieblo skb = tx_skb->skb; 753b83f1527SRafal Ozieblo 754b83f1527SRafal Ozieblo if (ctrl & MACB_BIT(TX_USED)) { 755b83f1527SRafal Ozieblo /* skb is set for the last buffer of the frame */ 756b83f1527SRafal Ozieblo while (!skb) { 757b83f1527SRafal Ozieblo macb_tx_unmap(bp, tx_skb); 758b83f1527SRafal Ozieblo tail++; 759b83f1527SRafal Ozieblo tx_skb = macb_tx_skb(queue, tail); 760b83f1527SRafal Ozieblo skb = tx_skb->skb; 761b83f1527SRafal Ozieblo } 762b83f1527SRafal Ozieblo 763b83f1527SRafal Ozieblo /* ctrl still refers to the first buffer descriptor 764b83f1527SRafal Ozieblo * since it's the only one written back by the hardware 765b83f1527SRafal Ozieblo */ 766b83f1527SRafal Ozieblo if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) { 767b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n", 768b83f1527SRafal Ozieblo macb_tx_ring_wrap(bp, tail), 769b83f1527SRafal Ozieblo skb->data); 770b83f1527SRafal Ozieblo bp->dev->stats.tx_packets++; 771512286bbSRafal Ozieblo queue->stats.tx_packets++; 772b83f1527SRafal Ozieblo bp->dev->stats.tx_bytes += skb->len; 773512286bbSRafal Ozieblo queue->stats.tx_bytes += skb->len; 774b83f1527SRafal Ozieblo } 775b83f1527SRafal Ozieblo } else { 776b83f1527SRafal Ozieblo /* "Buffers exhausted mid-frame" errors may only happen 777b83f1527SRafal Ozieblo * if the driver is buggy, so complain loudly about 778b83f1527SRafal Ozieblo * those. Statistics are updated by hardware. 779b83f1527SRafal Ozieblo */ 780b83f1527SRafal Ozieblo if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) 781b83f1527SRafal Ozieblo netdev_err(bp->dev, 782b83f1527SRafal Ozieblo "BUG: TX buffers exhausted mid-frame\n"); 783b83f1527SRafal Ozieblo 784b83f1527SRafal Ozieblo desc->ctrl = ctrl | MACB_BIT(TX_USED); 785b83f1527SRafal Ozieblo } 786b83f1527SRafal Ozieblo 787b83f1527SRafal Ozieblo macb_tx_unmap(bp, tx_skb); 788b83f1527SRafal Ozieblo } 789b83f1527SRafal Ozieblo 790b83f1527SRafal Ozieblo /* Set end of TX queue */ 791b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, 0); 792b83f1527SRafal Ozieblo macb_set_addr(bp, desc, 0); 793b83f1527SRafal Ozieblo desc->ctrl = MACB_BIT(TX_USED); 794b83f1527SRafal Ozieblo 795b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */ 796b83f1527SRafal Ozieblo wmb(); 797b83f1527SRafal Ozieblo 798b83f1527SRafal Ozieblo /* Reinitialize the TX desc queue */ 799b83f1527SRafal Ozieblo queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); 800b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 801b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) 802b83f1527SRafal Ozieblo queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); 803b83f1527SRafal Ozieblo #endif 804b83f1527SRafal Ozieblo /* Make TX ring reflect state of hardware */ 805b83f1527SRafal Ozieblo queue->tx_head = 0; 806b83f1527SRafal Ozieblo queue->tx_tail = 0; 807b83f1527SRafal Ozieblo 808b83f1527SRafal Ozieblo /* Housework before enabling TX IRQ */ 809b83f1527SRafal Ozieblo macb_writel(bp, TSR, macb_readl(bp, TSR)); 810b83f1527SRafal Ozieblo queue_writel(queue, IER, MACB_TX_INT_FLAGS); 811b83f1527SRafal Ozieblo 812b83f1527SRafal Ozieblo /* Now we are ready to start transmission again */ 813b83f1527SRafal Ozieblo netif_tx_start_all_queues(bp->dev); 814b83f1527SRafal Ozieblo macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 815b83f1527SRafal Ozieblo 816b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags); 817b83f1527SRafal Ozieblo } 818b83f1527SRafal Ozieblo 819b83f1527SRafal Ozieblo static void macb_tx_interrupt(struct macb_queue *queue) 820b83f1527SRafal Ozieblo { 821b83f1527SRafal Ozieblo unsigned int tail; 822b83f1527SRafal Ozieblo unsigned int head; 823b83f1527SRafal Ozieblo u32 status; 824b83f1527SRafal Ozieblo struct macb *bp = queue->bp; 825b83f1527SRafal Ozieblo u16 queue_index = queue - bp->queues; 826b83f1527SRafal Ozieblo 827b83f1527SRafal Ozieblo status = macb_readl(bp, TSR); 828b83f1527SRafal Ozieblo macb_writel(bp, TSR, status); 829b83f1527SRafal Ozieblo 830b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 831b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(TCOMP)); 832b83f1527SRafal Ozieblo 833b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", 834b83f1527SRafal Ozieblo (unsigned long)status); 835b83f1527SRafal Ozieblo 836b83f1527SRafal Ozieblo head = queue->tx_head; 837b83f1527SRafal Ozieblo for (tail = queue->tx_tail; tail != head; tail++) { 838b83f1527SRafal Ozieblo struct macb_tx_skb *tx_skb; 839b83f1527SRafal Ozieblo struct sk_buff *skb; 840b83f1527SRafal Ozieblo struct macb_dma_desc *desc; 841b83f1527SRafal Ozieblo u32 ctrl; 842b83f1527SRafal Ozieblo 843b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, tail); 844b83f1527SRafal Ozieblo 845b83f1527SRafal Ozieblo /* Make hw descriptor updates visible to CPU */ 846b83f1527SRafal Ozieblo rmb(); 847b83f1527SRafal Ozieblo 848b83f1527SRafal Ozieblo ctrl = desc->ctrl; 849b83f1527SRafal Ozieblo 850b83f1527SRafal Ozieblo /* TX_USED bit is only set by hardware on the very first buffer 851b83f1527SRafal Ozieblo * descriptor of the transmitted frame. 852b83f1527SRafal Ozieblo */ 853b83f1527SRafal Ozieblo if (!(ctrl & MACB_BIT(TX_USED))) 854b83f1527SRafal Ozieblo break; 855b83f1527SRafal Ozieblo 856b83f1527SRafal Ozieblo /* Process all buffers of the current transmitted frame */ 857b83f1527SRafal Ozieblo for (;; tail++) { 858b83f1527SRafal Ozieblo tx_skb = macb_tx_skb(queue, tail); 859b83f1527SRafal Ozieblo skb = tx_skb->skb; 860b83f1527SRafal Ozieblo 861b83f1527SRafal Ozieblo /* First, update TX stats if needed */ 862b83f1527SRafal Ozieblo if (skb) { 863ab91f0a9SRafal Ozieblo if (gem_ptp_do_txstamp(queue, skb, desc) == 0) { 864ab91f0a9SRafal Ozieblo /* skb now belongs to timestamp buffer 865ab91f0a9SRafal Ozieblo * and will be removed later 866ab91f0a9SRafal Ozieblo */ 867ab91f0a9SRafal Ozieblo tx_skb->skb = NULL; 868ab91f0a9SRafal Ozieblo } 869b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", 870b83f1527SRafal Ozieblo macb_tx_ring_wrap(bp, tail), 871b83f1527SRafal Ozieblo skb->data); 872b83f1527SRafal Ozieblo bp->dev->stats.tx_packets++; 873512286bbSRafal Ozieblo queue->stats.tx_packets++; 874b83f1527SRafal Ozieblo bp->dev->stats.tx_bytes += skb->len; 875512286bbSRafal Ozieblo queue->stats.tx_bytes += skb->len; 876b83f1527SRafal Ozieblo } 877b83f1527SRafal Ozieblo 878b83f1527SRafal Ozieblo /* Now we can safely release resources */ 879b83f1527SRafal Ozieblo macb_tx_unmap(bp, tx_skb); 880b83f1527SRafal Ozieblo 881b83f1527SRafal Ozieblo /* skb is set only for the last buffer of the frame. 882b83f1527SRafal Ozieblo * WARNING: at this point skb has been freed by 883b83f1527SRafal Ozieblo * macb_tx_unmap(). 884b83f1527SRafal Ozieblo */ 885b83f1527SRafal Ozieblo if (skb) 886b83f1527SRafal Ozieblo break; 887b83f1527SRafal Ozieblo } 888b83f1527SRafal Ozieblo } 889b83f1527SRafal Ozieblo 890b83f1527SRafal Ozieblo queue->tx_tail = tail; 891b83f1527SRafal Ozieblo if (__netif_subqueue_stopped(bp->dev, queue_index) && 892b83f1527SRafal Ozieblo CIRC_CNT(queue->tx_head, queue->tx_tail, 893b83f1527SRafal Ozieblo bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp)) 894b83f1527SRafal Ozieblo netif_wake_subqueue(bp->dev, queue_index); 895b83f1527SRafal Ozieblo } 896b83f1527SRafal Ozieblo 897ae1f2a56SRafal Ozieblo static void gem_rx_refill(struct macb_queue *queue) 898b83f1527SRafal Ozieblo { 899b83f1527SRafal Ozieblo unsigned int entry; 900b83f1527SRafal Ozieblo struct sk_buff *skb; 901b83f1527SRafal Ozieblo dma_addr_t paddr; 902ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp; 903b83f1527SRafal Ozieblo struct macb_dma_desc *desc; 904b83f1527SRafal Ozieblo 905ae1f2a56SRafal Ozieblo while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail, 906b83f1527SRafal Ozieblo bp->rx_ring_size) > 0) { 907ae1f2a56SRafal Ozieblo entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head); 908b83f1527SRafal Ozieblo 909b83f1527SRafal Ozieblo /* Make hw descriptor updates visible to CPU */ 910b83f1527SRafal Ozieblo rmb(); 911b83f1527SRafal Ozieblo 912ae1f2a56SRafal Ozieblo queue->rx_prepared_head++; 913ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, entry); 914b83f1527SRafal Ozieblo 915ae1f2a56SRafal Ozieblo if (!queue->rx_skbuff[entry]) { 916b83f1527SRafal Ozieblo /* allocate sk_buff for this free entry in ring */ 917b83f1527SRafal Ozieblo skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size); 918b83f1527SRafal Ozieblo if (unlikely(!skb)) { 919b83f1527SRafal Ozieblo netdev_err(bp->dev, 920b83f1527SRafal Ozieblo "Unable to allocate sk_buff\n"); 921b83f1527SRafal Ozieblo break; 922b83f1527SRafal Ozieblo } 923b83f1527SRafal Ozieblo 924b83f1527SRafal Ozieblo /* now fill corresponding descriptor entry */ 925b83f1527SRafal Ozieblo paddr = dma_map_single(&bp->pdev->dev, skb->data, 926b83f1527SRafal Ozieblo bp->rx_buffer_size, 927b83f1527SRafal Ozieblo DMA_FROM_DEVICE); 928b83f1527SRafal Ozieblo if (dma_mapping_error(&bp->pdev->dev, paddr)) { 929b83f1527SRafal Ozieblo dev_kfree_skb(skb); 930b83f1527SRafal Ozieblo break; 931b83f1527SRafal Ozieblo } 932b83f1527SRafal Ozieblo 933ae1f2a56SRafal Ozieblo queue->rx_skbuff[entry] = skb; 934b83f1527SRafal Ozieblo 935b83f1527SRafal Ozieblo if (entry == bp->rx_ring_size - 1) 936b83f1527SRafal Ozieblo paddr |= MACB_BIT(RX_WRAP); 937b83f1527SRafal Ozieblo desc->ctrl = 0; 9388159ecabSAnssi Hannula /* Setting addr clears RX_USED and allows reception, 9398159ecabSAnssi Hannula * make sure ctrl is cleared first to avoid a race. 9408159ecabSAnssi Hannula */ 9418159ecabSAnssi Hannula dma_wmb(); 9428159ecabSAnssi Hannula macb_set_addr(bp, desc, paddr); 943b83f1527SRafal Ozieblo 944b83f1527SRafal Ozieblo /* properly align Ethernet header */ 945b83f1527SRafal Ozieblo skb_reserve(skb, NET_IP_ALIGN); 946b83f1527SRafal Ozieblo } else { 947b83f1527SRafal Ozieblo desc->ctrl = 0; 9488159ecabSAnssi Hannula dma_wmb(); 9498159ecabSAnssi Hannula desc->addr &= ~MACB_BIT(RX_USED); 950b83f1527SRafal Ozieblo } 951b83f1527SRafal Ozieblo } 952b83f1527SRafal Ozieblo 953b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */ 954b83f1527SRafal Ozieblo wmb(); 955b83f1527SRafal Ozieblo 956ae1f2a56SRafal Ozieblo netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n", 957ae1f2a56SRafal Ozieblo queue, queue->rx_prepared_head, queue->rx_tail); 958b83f1527SRafal Ozieblo } 959b83f1527SRafal Ozieblo 960b83f1527SRafal Ozieblo /* Mark DMA descriptors from begin up to and not including end as unused */ 961ae1f2a56SRafal Ozieblo static void discard_partial_frame(struct macb_queue *queue, unsigned int begin, 962b83f1527SRafal Ozieblo unsigned int end) 963b83f1527SRafal Ozieblo { 964b83f1527SRafal Ozieblo unsigned int frag; 965b83f1527SRafal Ozieblo 966b83f1527SRafal Ozieblo for (frag = begin; frag != end; frag++) { 967ae1f2a56SRafal Ozieblo struct macb_dma_desc *desc = macb_rx_desc(queue, frag); 968b83f1527SRafal Ozieblo 969b83f1527SRafal Ozieblo desc->addr &= ~MACB_BIT(RX_USED); 970b83f1527SRafal Ozieblo } 971b83f1527SRafal Ozieblo 972b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */ 973b83f1527SRafal Ozieblo wmb(); 974b83f1527SRafal Ozieblo 975b83f1527SRafal Ozieblo /* When this happens, the hardware stats registers for 976b83f1527SRafal Ozieblo * whatever caused this is updated, so we don't have to record 977b83f1527SRafal Ozieblo * anything. 978b83f1527SRafal Ozieblo */ 979b83f1527SRafal Ozieblo } 980b83f1527SRafal Ozieblo 981ae1f2a56SRafal Ozieblo static int gem_rx(struct macb_queue *queue, int budget) 982b83f1527SRafal Ozieblo { 983ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp; 984b83f1527SRafal Ozieblo unsigned int len; 985b83f1527SRafal Ozieblo unsigned int entry; 986b83f1527SRafal Ozieblo struct sk_buff *skb; 987b83f1527SRafal Ozieblo struct macb_dma_desc *desc; 988b83f1527SRafal Ozieblo int count = 0; 989b83f1527SRafal Ozieblo 990b83f1527SRafal Ozieblo while (count < budget) { 991b83f1527SRafal Ozieblo u32 ctrl; 992b83f1527SRafal Ozieblo dma_addr_t addr; 993b83f1527SRafal Ozieblo bool rxused; 994b83f1527SRafal Ozieblo 995ae1f2a56SRafal Ozieblo entry = macb_rx_ring_wrap(bp, queue->rx_tail); 996ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, entry); 997b83f1527SRafal Ozieblo 998b83f1527SRafal Ozieblo /* Make hw descriptor updates visible to CPU */ 999b83f1527SRafal Ozieblo rmb(); 1000b83f1527SRafal Ozieblo 1001b83f1527SRafal Ozieblo rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false; 1002b83f1527SRafal Ozieblo addr = macb_get_addr(bp, desc); 1003b83f1527SRafal Ozieblo 1004b83f1527SRafal Ozieblo if (!rxused) 1005b83f1527SRafal Ozieblo break; 1006b83f1527SRafal Ozieblo 10076e0af298SAnssi Hannula /* Ensure ctrl is at least as up-to-date as rxused */ 10086e0af298SAnssi Hannula dma_rmb(); 10096e0af298SAnssi Hannula 10106e0af298SAnssi Hannula ctrl = desc->ctrl; 10116e0af298SAnssi Hannula 1012ae1f2a56SRafal Ozieblo queue->rx_tail++; 1013b83f1527SRafal Ozieblo count++; 1014b83f1527SRafal Ozieblo 1015b83f1527SRafal Ozieblo if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) { 1016b83f1527SRafal Ozieblo netdev_err(bp->dev, 1017b83f1527SRafal Ozieblo "not whole frame pointed by descriptor\n"); 1018b83f1527SRafal Ozieblo bp->dev->stats.rx_dropped++; 1019512286bbSRafal Ozieblo queue->stats.rx_dropped++; 1020b83f1527SRafal Ozieblo break; 1021b83f1527SRafal Ozieblo } 1022ae1f2a56SRafal Ozieblo skb = queue->rx_skbuff[entry]; 1023b83f1527SRafal Ozieblo if (unlikely(!skb)) { 1024b83f1527SRafal Ozieblo netdev_err(bp->dev, 1025b83f1527SRafal Ozieblo "inconsistent Rx descriptor chain\n"); 1026b83f1527SRafal Ozieblo bp->dev->stats.rx_dropped++; 1027512286bbSRafal Ozieblo queue->stats.rx_dropped++; 1028b83f1527SRafal Ozieblo break; 1029b83f1527SRafal Ozieblo } 1030b83f1527SRafal Ozieblo /* now everything is ready for receiving packet */ 1031ae1f2a56SRafal Ozieblo queue->rx_skbuff[entry] = NULL; 1032b83f1527SRafal Ozieblo len = ctrl & bp->rx_frm_len_mask; 1033b83f1527SRafal Ozieblo 1034b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len); 1035b83f1527SRafal Ozieblo 1036b83f1527SRafal Ozieblo skb_put(skb, len); 1037b83f1527SRafal Ozieblo dma_unmap_single(&bp->pdev->dev, addr, 1038b83f1527SRafal Ozieblo bp->rx_buffer_size, DMA_FROM_DEVICE); 1039b83f1527SRafal Ozieblo 1040b83f1527SRafal Ozieblo skb->protocol = eth_type_trans(skb, bp->dev); 1041b83f1527SRafal Ozieblo skb_checksum_none_assert(skb); 1042b83f1527SRafal Ozieblo if (bp->dev->features & NETIF_F_RXCSUM && 1043b83f1527SRafal Ozieblo !(bp->dev->flags & IFF_PROMISC) && 1044b83f1527SRafal Ozieblo GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK) 1045b83f1527SRafal Ozieblo skb->ip_summed = CHECKSUM_UNNECESSARY; 1046b83f1527SRafal Ozieblo 1047b83f1527SRafal Ozieblo bp->dev->stats.rx_packets++; 1048512286bbSRafal Ozieblo queue->stats.rx_packets++; 1049b83f1527SRafal Ozieblo bp->dev->stats.rx_bytes += skb->len; 1050512286bbSRafal Ozieblo queue->stats.rx_bytes += skb->len; 1051b83f1527SRafal Ozieblo 1052ab91f0a9SRafal Ozieblo gem_ptp_do_rxstamp(bp, skb, desc); 1053ab91f0a9SRafal Ozieblo 1054b83f1527SRafal Ozieblo #if defined(DEBUG) && defined(VERBOSE_DEBUG) 1055b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", 1056b83f1527SRafal Ozieblo skb->len, skb->csum); 1057b83f1527SRafal Ozieblo print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1, 1058b83f1527SRafal Ozieblo skb_mac_header(skb), 16, true); 1059b83f1527SRafal Ozieblo print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1, 1060b83f1527SRafal Ozieblo skb->data, 32, true); 1061b83f1527SRafal Ozieblo #endif 1062b83f1527SRafal Ozieblo 1063b83f1527SRafal Ozieblo netif_receive_skb(skb); 1064b83f1527SRafal Ozieblo } 1065b83f1527SRafal Ozieblo 1066ae1f2a56SRafal Ozieblo gem_rx_refill(queue); 1067b83f1527SRafal Ozieblo 1068b83f1527SRafal Ozieblo return count; 1069b83f1527SRafal Ozieblo } 1070b83f1527SRafal Ozieblo 1071ae1f2a56SRafal Ozieblo static int macb_rx_frame(struct macb_queue *queue, unsigned int first_frag, 1072b83f1527SRafal Ozieblo unsigned int last_frag) 1073b83f1527SRafal Ozieblo { 1074b83f1527SRafal Ozieblo unsigned int len; 1075b83f1527SRafal Ozieblo unsigned int frag; 1076b83f1527SRafal Ozieblo unsigned int offset; 1077b83f1527SRafal Ozieblo struct sk_buff *skb; 1078b83f1527SRafal Ozieblo struct macb_dma_desc *desc; 1079ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp; 1080b83f1527SRafal Ozieblo 1081ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, last_frag); 1082b83f1527SRafal Ozieblo len = desc->ctrl & bp->rx_frm_len_mask; 1083b83f1527SRafal Ozieblo 1084b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", 1085b83f1527SRafal Ozieblo macb_rx_ring_wrap(bp, first_frag), 1086b83f1527SRafal Ozieblo macb_rx_ring_wrap(bp, last_frag), len); 1087b83f1527SRafal Ozieblo 1088b83f1527SRafal Ozieblo /* The ethernet header starts NET_IP_ALIGN bytes into the 1089b83f1527SRafal Ozieblo * first buffer. Since the header is 14 bytes, this makes the 1090b83f1527SRafal Ozieblo * payload word-aligned. 1091b83f1527SRafal Ozieblo * 1092b83f1527SRafal Ozieblo * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy 1093b83f1527SRafal Ozieblo * the two padding bytes into the skb so that we avoid hitting 1094b83f1527SRafal Ozieblo * the slowpath in memcpy(), and pull them off afterwards. 1095b83f1527SRafal Ozieblo */ 1096b83f1527SRafal Ozieblo skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN); 1097b83f1527SRafal Ozieblo if (!skb) { 1098b83f1527SRafal Ozieblo bp->dev->stats.rx_dropped++; 1099b83f1527SRafal Ozieblo for (frag = first_frag; ; frag++) { 1100ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, frag); 1101b83f1527SRafal Ozieblo desc->addr &= ~MACB_BIT(RX_USED); 1102b83f1527SRafal Ozieblo if (frag == last_frag) 1103b83f1527SRafal Ozieblo break; 1104b83f1527SRafal Ozieblo } 1105b83f1527SRafal Ozieblo 1106b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */ 1107b83f1527SRafal Ozieblo wmb(); 1108b83f1527SRafal Ozieblo 1109b83f1527SRafal Ozieblo return 1; 1110b83f1527SRafal Ozieblo } 1111b83f1527SRafal Ozieblo 1112b83f1527SRafal Ozieblo offset = 0; 1113b83f1527SRafal Ozieblo len += NET_IP_ALIGN; 1114b83f1527SRafal Ozieblo skb_checksum_none_assert(skb); 1115b83f1527SRafal Ozieblo skb_put(skb, len); 1116b83f1527SRafal Ozieblo 1117b83f1527SRafal Ozieblo for (frag = first_frag; ; frag++) { 1118b83f1527SRafal Ozieblo unsigned int frag_len = bp->rx_buffer_size; 1119b83f1527SRafal Ozieblo 1120b83f1527SRafal Ozieblo if (offset + frag_len > len) { 1121b83f1527SRafal Ozieblo if (unlikely(frag != last_frag)) { 1122b83f1527SRafal Ozieblo dev_kfree_skb_any(skb); 1123b83f1527SRafal Ozieblo return -1; 1124b83f1527SRafal Ozieblo } 1125b83f1527SRafal Ozieblo frag_len = len - offset; 1126b83f1527SRafal Ozieblo } 1127b83f1527SRafal Ozieblo skb_copy_to_linear_data_offset(skb, offset, 1128ae1f2a56SRafal Ozieblo macb_rx_buffer(queue, frag), 1129b83f1527SRafal Ozieblo frag_len); 1130b83f1527SRafal Ozieblo offset += bp->rx_buffer_size; 1131ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, frag); 1132b83f1527SRafal Ozieblo desc->addr &= ~MACB_BIT(RX_USED); 1133b83f1527SRafal Ozieblo 1134b83f1527SRafal Ozieblo if (frag == last_frag) 1135b83f1527SRafal Ozieblo break; 1136b83f1527SRafal Ozieblo } 1137b83f1527SRafal Ozieblo 1138b83f1527SRafal Ozieblo /* Make descriptor updates visible to hardware */ 1139b83f1527SRafal Ozieblo wmb(); 1140b83f1527SRafal Ozieblo 1141b83f1527SRafal Ozieblo __skb_pull(skb, NET_IP_ALIGN); 1142b83f1527SRafal Ozieblo skb->protocol = eth_type_trans(skb, bp->dev); 1143b83f1527SRafal Ozieblo 1144b83f1527SRafal Ozieblo bp->dev->stats.rx_packets++; 1145b83f1527SRafal Ozieblo bp->dev->stats.rx_bytes += skb->len; 1146b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", 1147b83f1527SRafal Ozieblo skb->len, skb->csum); 1148b83f1527SRafal Ozieblo netif_receive_skb(skb); 1149b83f1527SRafal Ozieblo 1150b83f1527SRafal Ozieblo return 0; 1151b83f1527SRafal Ozieblo } 1152b83f1527SRafal Ozieblo 1153ae1f2a56SRafal Ozieblo static inline void macb_init_rx_ring(struct macb_queue *queue) 1154b83f1527SRafal Ozieblo { 1155ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp; 1156b83f1527SRafal Ozieblo dma_addr_t addr; 1157b83f1527SRafal Ozieblo struct macb_dma_desc *desc = NULL; 1158b83f1527SRafal Ozieblo int i; 1159b83f1527SRafal Ozieblo 1160ae1f2a56SRafal Ozieblo addr = queue->rx_buffers_dma; 1161b83f1527SRafal Ozieblo for (i = 0; i < bp->rx_ring_size; i++) { 1162ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, i); 1163b83f1527SRafal Ozieblo macb_set_addr(bp, desc, addr); 1164b83f1527SRafal Ozieblo desc->ctrl = 0; 1165b83f1527SRafal Ozieblo addr += bp->rx_buffer_size; 1166b83f1527SRafal Ozieblo } 1167b83f1527SRafal Ozieblo desc->addr |= MACB_BIT(RX_WRAP); 1168ae1f2a56SRafal Ozieblo queue->rx_tail = 0; 1169b83f1527SRafal Ozieblo } 1170b83f1527SRafal Ozieblo 1171ae1f2a56SRafal Ozieblo static int macb_rx(struct macb_queue *queue, int budget) 1172b83f1527SRafal Ozieblo { 1173ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp; 1174b83f1527SRafal Ozieblo bool reset_rx_queue = false; 1175b83f1527SRafal Ozieblo int received = 0; 1176b83f1527SRafal Ozieblo unsigned int tail; 1177b83f1527SRafal Ozieblo int first_frag = -1; 1178b83f1527SRafal Ozieblo 1179ae1f2a56SRafal Ozieblo for (tail = queue->rx_tail; budget > 0; tail++) { 1180ae1f2a56SRafal Ozieblo struct macb_dma_desc *desc = macb_rx_desc(queue, tail); 1181b83f1527SRafal Ozieblo u32 ctrl; 1182b83f1527SRafal Ozieblo 1183b83f1527SRafal Ozieblo /* Make hw descriptor updates visible to CPU */ 1184b83f1527SRafal Ozieblo rmb(); 1185b83f1527SRafal Ozieblo 1186b83f1527SRafal Ozieblo if (!(desc->addr & MACB_BIT(RX_USED))) 1187b83f1527SRafal Ozieblo break; 1188b83f1527SRafal Ozieblo 11896e0af298SAnssi Hannula /* Ensure ctrl is at least as up-to-date as addr */ 11906e0af298SAnssi Hannula dma_rmb(); 11916e0af298SAnssi Hannula 11926e0af298SAnssi Hannula ctrl = desc->ctrl; 11936e0af298SAnssi Hannula 1194b83f1527SRafal Ozieblo if (ctrl & MACB_BIT(RX_SOF)) { 1195b83f1527SRafal Ozieblo if (first_frag != -1) 1196ae1f2a56SRafal Ozieblo discard_partial_frame(queue, first_frag, tail); 1197b83f1527SRafal Ozieblo first_frag = tail; 1198b83f1527SRafal Ozieblo } 1199b83f1527SRafal Ozieblo 1200b83f1527SRafal Ozieblo if (ctrl & MACB_BIT(RX_EOF)) { 1201b83f1527SRafal Ozieblo int dropped; 1202b83f1527SRafal Ozieblo 1203b83f1527SRafal Ozieblo if (unlikely(first_frag == -1)) { 1204b83f1527SRafal Ozieblo reset_rx_queue = true; 1205b83f1527SRafal Ozieblo continue; 1206b83f1527SRafal Ozieblo } 1207b83f1527SRafal Ozieblo 1208ae1f2a56SRafal Ozieblo dropped = macb_rx_frame(queue, first_frag, tail); 1209b83f1527SRafal Ozieblo first_frag = -1; 1210b83f1527SRafal Ozieblo if (unlikely(dropped < 0)) { 1211b83f1527SRafal Ozieblo reset_rx_queue = true; 1212b83f1527SRafal Ozieblo continue; 1213b83f1527SRafal Ozieblo } 1214b83f1527SRafal Ozieblo if (!dropped) { 1215b83f1527SRafal Ozieblo received++; 1216b83f1527SRafal Ozieblo budget--; 1217b83f1527SRafal Ozieblo } 1218b83f1527SRafal Ozieblo } 1219b83f1527SRafal Ozieblo } 1220b83f1527SRafal Ozieblo 1221b83f1527SRafal Ozieblo if (unlikely(reset_rx_queue)) { 1222b83f1527SRafal Ozieblo unsigned long flags; 1223b83f1527SRafal Ozieblo u32 ctrl; 1224b83f1527SRafal Ozieblo 1225b83f1527SRafal Ozieblo netdev_err(bp->dev, "RX queue corruption: reset it\n"); 1226b83f1527SRafal Ozieblo 1227b83f1527SRafal Ozieblo spin_lock_irqsave(&bp->lock, flags); 1228b83f1527SRafal Ozieblo 1229b83f1527SRafal Ozieblo ctrl = macb_readl(bp, NCR); 1230b83f1527SRafal Ozieblo macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); 1231b83f1527SRafal Ozieblo 1232ae1f2a56SRafal Ozieblo macb_init_rx_ring(queue); 1233ae1f2a56SRafal Ozieblo queue_writel(queue, RBQP, queue->rx_ring_dma); 1234b83f1527SRafal Ozieblo 1235b83f1527SRafal Ozieblo macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); 1236b83f1527SRafal Ozieblo 1237b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags); 1238b83f1527SRafal Ozieblo return received; 1239b83f1527SRafal Ozieblo } 1240b83f1527SRafal Ozieblo 1241b83f1527SRafal Ozieblo if (first_frag != -1) 1242ae1f2a56SRafal Ozieblo queue->rx_tail = first_frag; 1243b83f1527SRafal Ozieblo else 1244ae1f2a56SRafal Ozieblo queue->rx_tail = tail; 1245b83f1527SRafal Ozieblo 1246b83f1527SRafal Ozieblo return received; 1247b83f1527SRafal Ozieblo } 1248b83f1527SRafal Ozieblo 1249b83f1527SRafal Ozieblo static int macb_poll(struct napi_struct *napi, int budget) 1250b83f1527SRafal Ozieblo { 1251ae1f2a56SRafal Ozieblo struct macb_queue *queue = container_of(napi, struct macb_queue, napi); 1252ae1f2a56SRafal Ozieblo struct macb *bp = queue->bp; 1253b83f1527SRafal Ozieblo int work_done; 1254b83f1527SRafal Ozieblo u32 status; 1255b83f1527SRafal Ozieblo 1256b83f1527SRafal Ozieblo status = macb_readl(bp, RSR); 1257b83f1527SRafal Ozieblo macb_writel(bp, RSR, status); 1258b83f1527SRafal Ozieblo 1259b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n", 1260b83f1527SRafal Ozieblo (unsigned long)status, budget); 1261b83f1527SRafal Ozieblo 1262ae1f2a56SRafal Ozieblo work_done = bp->macbgem_ops.mog_rx(queue, budget); 1263b83f1527SRafal Ozieblo if (work_done < budget) { 1264b83f1527SRafal Ozieblo napi_complete_done(napi, work_done); 1265b83f1527SRafal Ozieblo 1266b83f1527SRafal Ozieblo /* Packets received while interrupts were disabled */ 1267b83f1527SRafal Ozieblo status = macb_readl(bp, RSR); 1268b83f1527SRafal Ozieblo if (status) { 1269b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1270ae1f2a56SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(RCOMP)); 1271b83f1527SRafal Ozieblo napi_reschedule(napi); 1272b83f1527SRafal Ozieblo } else { 1273ae1f2a56SRafal Ozieblo queue_writel(queue, IER, MACB_RX_INT_FLAGS); 1274b83f1527SRafal Ozieblo } 1275b83f1527SRafal Ozieblo } 1276b83f1527SRafal Ozieblo 1277b83f1527SRafal Ozieblo /* TODO: Handle errors */ 1278b83f1527SRafal Ozieblo 1279b83f1527SRafal Ozieblo return work_done; 1280b83f1527SRafal Ozieblo } 1281b83f1527SRafal Ozieblo 1282032dc41bSHarini Katakam static void macb_hresp_error_task(unsigned long data) 1283032dc41bSHarini Katakam { 1284032dc41bSHarini Katakam struct macb *bp = (struct macb *)data; 1285032dc41bSHarini Katakam struct net_device *dev = bp->dev; 1286032dc41bSHarini Katakam struct macb_queue *queue = bp->queues; 1287032dc41bSHarini Katakam unsigned int q; 1288032dc41bSHarini Katakam u32 ctrl; 1289032dc41bSHarini Katakam 1290032dc41bSHarini Katakam for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 1291032dc41bSHarini Katakam queue_writel(queue, IDR, MACB_RX_INT_FLAGS | 1292032dc41bSHarini Katakam MACB_TX_INT_FLAGS | 1293032dc41bSHarini Katakam MACB_BIT(HRESP)); 1294032dc41bSHarini Katakam } 1295032dc41bSHarini Katakam ctrl = macb_readl(bp, NCR); 1296032dc41bSHarini Katakam ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE)); 1297032dc41bSHarini Katakam macb_writel(bp, NCR, ctrl); 1298032dc41bSHarini Katakam 1299032dc41bSHarini Katakam netif_tx_stop_all_queues(dev); 1300032dc41bSHarini Katakam netif_carrier_off(dev); 1301032dc41bSHarini Katakam 1302032dc41bSHarini Katakam bp->macbgem_ops.mog_init_rings(bp); 1303032dc41bSHarini Katakam 1304032dc41bSHarini Katakam /* Initialize TX and RX buffers */ 1305032dc41bSHarini Katakam for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 1306032dc41bSHarini Katakam queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma)); 1307032dc41bSHarini Katakam #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1308032dc41bSHarini Katakam if (bp->hw_dma_cap & HW_DMA_CAP_64B) 1309032dc41bSHarini Katakam queue_writel(queue, RBQPH, 1310032dc41bSHarini Katakam upper_32_bits(queue->rx_ring_dma)); 1311032dc41bSHarini Katakam #endif 1312032dc41bSHarini Katakam queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); 1313032dc41bSHarini Katakam #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1314032dc41bSHarini Katakam if (bp->hw_dma_cap & HW_DMA_CAP_64B) 1315032dc41bSHarini Katakam queue_writel(queue, TBQPH, 1316032dc41bSHarini Katakam upper_32_bits(queue->tx_ring_dma)); 1317032dc41bSHarini Katakam #endif 1318032dc41bSHarini Katakam 1319032dc41bSHarini Katakam /* Enable interrupts */ 1320032dc41bSHarini Katakam queue_writel(queue, IER, 1321032dc41bSHarini Katakam MACB_RX_INT_FLAGS | 1322032dc41bSHarini Katakam MACB_TX_INT_FLAGS | 1323032dc41bSHarini Katakam MACB_BIT(HRESP)); 1324032dc41bSHarini Katakam } 1325032dc41bSHarini Katakam 1326032dc41bSHarini Katakam ctrl |= MACB_BIT(RE) | MACB_BIT(TE); 1327032dc41bSHarini Katakam macb_writel(bp, NCR, ctrl); 1328032dc41bSHarini Katakam 1329032dc41bSHarini Katakam netif_carrier_on(dev); 1330032dc41bSHarini Katakam netif_tx_start_all_queues(dev); 1331032dc41bSHarini Katakam } 1332032dc41bSHarini Katakam 133342983885SClaudiu Beznea static void macb_tx_restart(struct macb_queue *queue) 133442983885SClaudiu Beznea { 133542983885SClaudiu Beznea unsigned int head = queue->tx_head; 133642983885SClaudiu Beznea unsigned int tail = queue->tx_tail; 133742983885SClaudiu Beznea struct macb *bp = queue->bp; 133842983885SClaudiu Beznea 133942983885SClaudiu Beznea if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 134042983885SClaudiu Beznea queue_writel(queue, ISR, MACB_BIT(TXUBR)); 134142983885SClaudiu Beznea 134242983885SClaudiu Beznea if (head == tail) 134342983885SClaudiu Beznea return; 134442983885SClaudiu Beznea 134542983885SClaudiu Beznea macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 134642983885SClaudiu Beznea } 134742983885SClaudiu Beznea 1348b83f1527SRafal Ozieblo static irqreturn_t macb_interrupt(int irq, void *dev_id) 1349b83f1527SRafal Ozieblo { 1350b83f1527SRafal Ozieblo struct macb_queue *queue = dev_id; 1351b83f1527SRafal Ozieblo struct macb *bp = queue->bp; 1352b83f1527SRafal Ozieblo struct net_device *dev = bp->dev; 1353b83f1527SRafal Ozieblo u32 status, ctrl; 1354b83f1527SRafal Ozieblo 1355b83f1527SRafal Ozieblo status = queue_readl(queue, ISR); 1356b83f1527SRafal Ozieblo 1357b83f1527SRafal Ozieblo if (unlikely(!status)) 1358b83f1527SRafal Ozieblo return IRQ_NONE; 1359b83f1527SRafal Ozieblo 1360b83f1527SRafal Ozieblo spin_lock(&bp->lock); 1361b83f1527SRafal Ozieblo 1362b83f1527SRafal Ozieblo while (status) { 1363b83f1527SRafal Ozieblo /* close possible race with dev_close */ 1364b83f1527SRafal Ozieblo if (unlikely(!netif_running(dev))) { 1365b83f1527SRafal Ozieblo queue_writel(queue, IDR, -1); 1366b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1367b83f1527SRafal Ozieblo queue_writel(queue, ISR, -1); 1368b83f1527SRafal Ozieblo break; 1369b83f1527SRafal Ozieblo } 1370b83f1527SRafal Ozieblo 1371b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n", 1372b83f1527SRafal Ozieblo (unsigned int)(queue - bp->queues), 1373b83f1527SRafal Ozieblo (unsigned long)status); 1374b83f1527SRafal Ozieblo 1375b83f1527SRafal Ozieblo if (status & MACB_RX_INT_FLAGS) { 1376b83f1527SRafal Ozieblo /* There's no point taking any more interrupts 1377b83f1527SRafal Ozieblo * until we have processed the buffers. The 1378b83f1527SRafal Ozieblo * scheduling call may fail if the poll routine 1379b83f1527SRafal Ozieblo * is already scheduled, so disable interrupts 1380b83f1527SRafal Ozieblo * now. 1381b83f1527SRafal Ozieblo */ 1382b83f1527SRafal Ozieblo queue_writel(queue, IDR, MACB_RX_INT_FLAGS); 1383b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1384b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(RCOMP)); 1385b83f1527SRafal Ozieblo 1386ae1f2a56SRafal Ozieblo if (napi_schedule_prep(&queue->napi)) { 1387b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, "scheduling RX softirq\n"); 1388ae1f2a56SRafal Ozieblo __napi_schedule(&queue->napi); 1389b83f1527SRafal Ozieblo } 1390b83f1527SRafal Ozieblo } 1391b83f1527SRafal Ozieblo 1392b83f1527SRafal Ozieblo if (unlikely(status & (MACB_TX_ERR_FLAGS))) { 1393b83f1527SRafal Ozieblo queue_writel(queue, IDR, MACB_TX_INT_FLAGS); 1394b83f1527SRafal Ozieblo schedule_work(&queue->tx_error_task); 1395b83f1527SRafal Ozieblo 1396b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1397b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_TX_ERR_FLAGS); 1398b83f1527SRafal Ozieblo 1399b83f1527SRafal Ozieblo break; 1400b83f1527SRafal Ozieblo } 1401b83f1527SRafal Ozieblo 1402b83f1527SRafal Ozieblo if (status & MACB_BIT(TCOMP)) 1403b83f1527SRafal Ozieblo macb_tx_interrupt(queue); 1404b83f1527SRafal Ozieblo 140542983885SClaudiu Beznea if (status & MACB_BIT(TXUBR)) 140642983885SClaudiu Beznea macb_tx_restart(queue); 140742983885SClaudiu Beznea 1408b83f1527SRafal Ozieblo /* Link change detection isn't possible with RMII, so we'll 1409b83f1527SRafal Ozieblo * add that if/when we get our hands on a full-blown MII PHY. 1410b83f1527SRafal Ozieblo */ 1411b83f1527SRafal Ozieblo 1412b83f1527SRafal Ozieblo /* There is a hardware issue under heavy load where DMA can 1413b83f1527SRafal Ozieblo * stop, this causes endless "used buffer descriptor read" 1414b83f1527SRafal Ozieblo * interrupts but it can be cleared by re-enabling RX. See 1415b83f1527SRafal Ozieblo * the at91 manual, section 41.3.1 or the Zynq manual 1416b83f1527SRafal Ozieblo * section 16.7.4 for details. 1417b83f1527SRafal Ozieblo */ 1418b83f1527SRafal Ozieblo if (status & MACB_BIT(RXUBR)) { 1419b83f1527SRafal Ozieblo ctrl = macb_readl(bp, NCR); 1420b83f1527SRafal Ozieblo macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE)); 1421b83f1527SRafal Ozieblo wmb(); 1422b83f1527SRafal Ozieblo macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); 1423b83f1527SRafal Ozieblo 1424b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1425b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(RXUBR)); 1426b83f1527SRafal Ozieblo } 1427b83f1527SRafal Ozieblo 1428b83f1527SRafal Ozieblo if (status & MACB_BIT(ISR_ROVR)) { 1429b83f1527SRafal Ozieblo /* We missed at least one packet */ 1430b83f1527SRafal Ozieblo if (macb_is_gem(bp)) 1431b83f1527SRafal Ozieblo bp->hw_stats.gem.rx_overruns++; 1432b83f1527SRafal Ozieblo else 1433b83f1527SRafal Ozieblo bp->hw_stats.macb.rx_overruns++; 1434b83f1527SRafal Ozieblo 1435b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1436b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(ISR_ROVR)); 1437b83f1527SRafal Ozieblo } 1438b83f1527SRafal Ozieblo 1439b83f1527SRafal Ozieblo if (status & MACB_BIT(HRESP)) { 1440032dc41bSHarini Katakam tasklet_schedule(&bp->hresp_err_tasklet); 1441b83f1527SRafal Ozieblo netdev_err(dev, "DMA bus error: HRESP not OK\n"); 1442b83f1527SRafal Ozieblo 1443b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1444b83f1527SRafal Ozieblo queue_writel(queue, ISR, MACB_BIT(HRESP)); 1445b83f1527SRafal Ozieblo } 1446b83f1527SRafal Ozieblo status = queue_readl(queue, ISR); 1447b83f1527SRafal Ozieblo } 1448b83f1527SRafal Ozieblo 1449b83f1527SRafal Ozieblo spin_unlock(&bp->lock); 1450b83f1527SRafal Ozieblo 1451b83f1527SRafal Ozieblo return IRQ_HANDLED; 1452b83f1527SRafal Ozieblo } 1453b83f1527SRafal Ozieblo 1454b83f1527SRafal Ozieblo #ifdef CONFIG_NET_POLL_CONTROLLER 1455b83f1527SRafal Ozieblo /* Polling receive - used by netconsole and other diagnostic tools 1456b83f1527SRafal Ozieblo * to allow network i/o with interrupts disabled. 1457b83f1527SRafal Ozieblo */ 1458b83f1527SRafal Ozieblo static void macb_poll_controller(struct net_device *dev) 1459b83f1527SRafal Ozieblo { 1460b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 1461b83f1527SRafal Ozieblo struct macb_queue *queue; 1462b83f1527SRafal Ozieblo unsigned long flags; 1463b83f1527SRafal Ozieblo unsigned int q; 1464b83f1527SRafal Ozieblo 1465b83f1527SRafal Ozieblo local_irq_save(flags); 1466b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 1467b83f1527SRafal Ozieblo macb_interrupt(dev->irq, queue); 1468b83f1527SRafal Ozieblo local_irq_restore(flags); 1469b83f1527SRafal Ozieblo } 1470b83f1527SRafal Ozieblo #endif 1471b83f1527SRafal Ozieblo 1472b83f1527SRafal Ozieblo static unsigned int macb_tx_map(struct macb *bp, 1473b83f1527SRafal Ozieblo struct macb_queue *queue, 1474b83f1527SRafal Ozieblo struct sk_buff *skb, 1475b83f1527SRafal Ozieblo unsigned int hdrlen) 1476b83f1527SRafal Ozieblo { 1477b83f1527SRafal Ozieblo dma_addr_t mapping; 1478b83f1527SRafal Ozieblo unsigned int len, entry, i, tx_head = queue->tx_head; 1479b83f1527SRafal Ozieblo struct macb_tx_skb *tx_skb = NULL; 1480b83f1527SRafal Ozieblo struct macb_dma_desc *desc; 1481b83f1527SRafal Ozieblo unsigned int offset, size, count = 0; 1482b83f1527SRafal Ozieblo unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags; 1483b83f1527SRafal Ozieblo unsigned int eof = 1, mss_mfs = 0; 1484b83f1527SRafal Ozieblo u32 ctrl, lso_ctrl = 0, seq_ctrl = 0; 1485b83f1527SRafal Ozieblo 1486b83f1527SRafal Ozieblo /* LSO */ 1487b83f1527SRafal Ozieblo if (skb_shinfo(skb)->gso_size != 0) { 1488b83f1527SRafal Ozieblo if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1489b83f1527SRafal Ozieblo /* UDP - UFO */ 1490b83f1527SRafal Ozieblo lso_ctrl = MACB_LSO_UFO_ENABLE; 1491b83f1527SRafal Ozieblo else 1492b83f1527SRafal Ozieblo /* TCP - TSO */ 1493b83f1527SRafal Ozieblo lso_ctrl = MACB_LSO_TSO_ENABLE; 1494b83f1527SRafal Ozieblo } 1495b83f1527SRafal Ozieblo 1496b83f1527SRafal Ozieblo /* First, map non-paged data */ 1497b83f1527SRafal Ozieblo len = skb_headlen(skb); 1498b83f1527SRafal Ozieblo 1499b83f1527SRafal Ozieblo /* first buffer length */ 1500b83f1527SRafal Ozieblo size = hdrlen; 1501b83f1527SRafal Ozieblo 1502b83f1527SRafal Ozieblo offset = 0; 1503b83f1527SRafal Ozieblo while (len) { 1504b83f1527SRafal Ozieblo entry = macb_tx_ring_wrap(bp, tx_head); 1505b83f1527SRafal Ozieblo tx_skb = &queue->tx_skb[entry]; 1506b83f1527SRafal Ozieblo 1507b83f1527SRafal Ozieblo mapping = dma_map_single(&bp->pdev->dev, 1508b83f1527SRafal Ozieblo skb->data + offset, 1509b83f1527SRafal Ozieblo size, DMA_TO_DEVICE); 1510b83f1527SRafal Ozieblo if (dma_mapping_error(&bp->pdev->dev, mapping)) 1511b83f1527SRafal Ozieblo goto dma_error; 1512b83f1527SRafal Ozieblo 1513b83f1527SRafal Ozieblo /* Save info to properly release resources */ 1514b83f1527SRafal Ozieblo tx_skb->skb = NULL; 1515b83f1527SRafal Ozieblo tx_skb->mapping = mapping; 1516b83f1527SRafal Ozieblo tx_skb->size = size; 1517b83f1527SRafal Ozieblo tx_skb->mapped_as_page = false; 1518b83f1527SRafal Ozieblo 1519b83f1527SRafal Ozieblo len -= size; 1520b83f1527SRafal Ozieblo offset += size; 1521b83f1527SRafal Ozieblo count++; 1522b83f1527SRafal Ozieblo tx_head++; 1523b83f1527SRafal Ozieblo 1524b83f1527SRafal Ozieblo size = min(len, bp->max_tx_length); 1525b83f1527SRafal Ozieblo } 1526b83f1527SRafal Ozieblo 1527b83f1527SRafal Ozieblo /* Then, map paged data from fragments */ 1528b83f1527SRafal Ozieblo for (f = 0; f < nr_frags; f++) { 1529b83f1527SRafal Ozieblo const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1530b83f1527SRafal Ozieblo 1531b83f1527SRafal Ozieblo len = skb_frag_size(frag); 1532b83f1527SRafal Ozieblo offset = 0; 1533b83f1527SRafal Ozieblo while (len) { 1534b83f1527SRafal Ozieblo size = min(len, bp->max_tx_length); 1535b83f1527SRafal Ozieblo entry = macb_tx_ring_wrap(bp, tx_head); 1536b83f1527SRafal Ozieblo tx_skb = &queue->tx_skb[entry]; 1537b83f1527SRafal Ozieblo 1538b83f1527SRafal Ozieblo mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 1539b83f1527SRafal Ozieblo offset, size, DMA_TO_DEVICE); 1540b83f1527SRafal Ozieblo if (dma_mapping_error(&bp->pdev->dev, mapping)) 1541b83f1527SRafal Ozieblo goto dma_error; 1542b83f1527SRafal Ozieblo 1543b83f1527SRafal Ozieblo /* Save info to properly release resources */ 1544b83f1527SRafal Ozieblo tx_skb->skb = NULL; 1545b83f1527SRafal Ozieblo tx_skb->mapping = mapping; 1546b83f1527SRafal Ozieblo tx_skb->size = size; 1547b83f1527SRafal Ozieblo tx_skb->mapped_as_page = true; 1548b83f1527SRafal Ozieblo 1549b83f1527SRafal Ozieblo len -= size; 1550b83f1527SRafal Ozieblo offset += size; 1551b83f1527SRafal Ozieblo count++; 1552b83f1527SRafal Ozieblo tx_head++; 1553b83f1527SRafal Ozieblo } 1554b83f1527SRafal Ozieblo } 1555b83f1527SRafal Ozieblo 1556b83f1527SRafal Ozieblo /* Should never happen */ 1557b83f1527SRafal Ozieblo if (unlikely(!tx_skb)) { 1558b83f1527SRafal Ozieblo netdev_err(bp->dev, "BUG! empty skb!\n"); 1559b83f1527SRafal Ozieblo return 0; 1560b83f1527SRafal Ozieblo } 1561b83f1527SRafal Ozieblo 1562b83f1527SRafal Ozieblo /* This is the last buffer of the frame: save socket buffer */ 1563b83f1527SRafal Ozieblo tx_skb->skb = skb; 1564b83f1527SRafal Ozieblo 1565b83f1527SRafal Ozieblo /* Update TX ring: update buffer descriptors in reverse order 1566b83f1527SRafal Ozieblo * to avoid race condition 1567b83f1527SRafal Ozieblo */ 1568b83f1527SRafal Ozieblo 1569b83f1527SRafal Ozieblo /* Set 'TX_USED' bit in buffer descriptor at tx_head position 1570b83f1527SRafal Ozieblo * to set the end of TX queue 1571b83f1527SRafal Ozieblo */ 1572b83f1527SRafal Ozieblo i = tx_head; 1573b83f1527SRafal Ozieblo entry = macb_tx_ring_wrap(bp, i); 1574b83f1527SRafal Ozieblo ctrl = MACB_BIT(TX_USED); 1575b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, entry); 1576b83f1527SRafal Ozieblo desc->ctrl = ctrl; 1577b83f1527SRafal Ozieblo 1578b83f1527SRafal Ozieblo if (lso_ctrl) { 1579b83f1527SRafal Ozieblo if (lso_ctrl == MACB_LSO_UFO_ENABLE) 1580b83f1527SRafal Ozieblo /* include header and FCS in value given to h/w */ 1581b83f1527SRafal Ozieblo mss_mfs = skb_shinfo(skb)->gso_size + 1582b83f1527SRafal Ozieblo skb_transport_offset(skb) + 1583b83f1527SRafal Ozieblo ETH_FCS_LEN; 1584b83f1527SRafal Ozieblo else /* TSO */ { 1585b83f1527SRafal Ozieblo mss_mfs = skb_shinfo(skb)->gso_size; 1586b83f1527SRafal Ozieblo /* TCP Sequence Number Source Select 1587b83f1527SRafal Ozieblo * can be set only for TSO 1588b83f1527SRafal Ozieblo */ 1589b83f1527SRafal Ozieblo seq_ctrl = 0; 1590b83f1527SRafal Ozieblo } 1591b83f1527SRafal Ozieblo } 1592b83f1527SRafal Ozieblo 1593b83f1527SRafal Ozieblo do { 1594b83f1527SRafal Ozieblo i--; 1595b83f1527SRafal Ozieblo entry = macb_tx_ring_wrap(bp, i); 1596b83f1527SRafal Ozieblo tx_skb = &queue->tx_skb[entry]; 1597b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, entry); 1598b83f1527SRafal Ozieblo 1599b83f1527SRafal Ozieblo ctrl = (u32)tx_skb->size; 1600b83f1527SRafal Ozieblo if (eof) { 1601b83f1527SRafal Ozieblo ctrl |= MACB_BIT(TX_LAST); 1602b83f1527SRafal Ozieblo eof = 0; 1603b83f1527SRafal Ozieblo } 1604b83f1527SRafal Ozieblo if (unlikely(entry == (bp->tx_ring_size - 1))) 1605b83f1527SRafal Ozieblo ctrl |= MACB_BIT(TX_WRAP); 1606b83f1527SRafal Ozieblo 1607b83f1527SRafal Ozieblo /* First descriptor is header descriptor */ 1608b83f1527SRafal Ozieblo if (i == queue->tx_head) { 1609b83f1527SRafal Ozieblo ctrl |= MACB_BF(TX_LSO, lso_ctrl); 1610b83f1527SRafal Ozieblo ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl); 1611653e92a9SClaudiu Beznea if ((bp->dev->features & NETIF_F_HW_CSUM) && 1612653e92a9SClaudiu Beznea skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl) 1613653e92a9SClaudiu Beznea ctrl |= MACB_BIT(TX_NOCRC); 1614b83f1527SRafal Ozieblo } else 1615b83f1527SRafal Ozieblo /* Only set MSS/MFS on payload descriptors 1616b83f1527SRafal Ozieblo * (second or later descriptor) 1617b83f1527SRafal Ozieblo */ 1618b83f1527SRafal Ozieblo ctrl |= MACB_BF(MSS_MFS, mss_mfs); 1619b83f1527SRafal Ozieblo 1620b83f1527SRafal Ozieblo /* Set TX buffer descriptor */ 1621b83f1527SRafal Ozieblo macb_set_addr(bp, desc, tx_skb->mapping); 1622b83f1527SRafal Ozieblo /* desc->addr must be visible to hardware before clearing 1623b83f1527SRafal Ozieblo * 'TX_USED' bit in desc->ctrl. 1624b83f1527SRafal Ozieblo */ 1625b83f1527SRafal Ozieblo wmb(); 1626b83f1527SRafal Ozieblo desc->ctrl = ctrl; 1627b83f1527SRafal Ozieblo } while (i != queue->tx_head); 1628b83f1527SRafal Ozieblo 1629b83f1527SRafal Ozieblo queue->tx_head = tx_head; 1630b83f1527SRafal Ozieblo 1631b83f1527SRafal Ozieblo return count; 1632b83f1527SRafal Ozieblo 1633b83f1527SRafal Ozieblo dma_error: 1634b83f1527SRafal Ozieblo netdev_err(bp->dev, "TX DMA map failed\n"); 1635b83f1527SRafal Ozieblo 1636b83f1527SRafal Ozieblo for (i = queue->tx_head; i != tx_head; i++) { 1637b83f1527SRafal Ozieblo tx_skb = macb_tx_skb(queue, i); 1638b83f1527SRafal Ozieblo 1639b83f1527SRafal Ozieblo macb_tx_unmap(bp, tx_skb); 1640b83f1527SRafal Ozieblo } 1641b83f1527SRafal Ozieblo 1642b83f1527SRafal Ozieblo return 0; 1643b83f1527SRafal Ozieblo } 1644b83f1527SRafal Ozieblo 1645b83f1527SRafal Ozieblo static netdev_features_t macb_features_check(struct sk_buff *skb, 1646b83f1527SRafal Ozieblo struct net_device *dev, 1647b83f1527SRafal Ozieblo netdev_features_t features) 1648b83f1527SRafal Ozieblo { 1649b83f1527SRafal Ozieblo unsigned int nr_frags, f; 1650b83f1527SRafal Ozieblo unsigned int hdrlen; 1651b83f1527SRafal Ozieblo 1652b83f1527SRafal Ozieblo /* Validate LSO compatibility */ 1653b83f1527SRafal Ozieblo 1654b83f1527SRafal Ozieblo /* there is only one buffer */ 1655b83f1527SRafal Ozieblo if (!skb_is_nonlinear(skb)) 1656b83f1527SRafal Ozieblo return features; 1657b83f1527SRafal Ozieblo 1658b83f1527SRafal Ozieblo /* length of header */ 1659b83f1527SRafal Ozieblo hdrlen = skb_transport_offset(skb); 1660b83f1527SRafal Ozieblo if (ip_hdr(skb)->protocol == IPPROTO_TCP) 1661b83f1527SRafal Ozieblo hdrlen += tcp_hdrlen(skb); 1662b83f1527SRafal Ozieblo 1663b83f1527SRafal Ozieblo /* For LSO: 1664b83f1527SRafal Ozieblo * When software supplies two or more payload buffers all payload buffers 1665b83f1527SRafal Ozieblo * apart from the last must be a multiple of 8 bytes in size. 1666b83f1527SRafal Ozieblo */ 1667b83f1527SRafal Ozieblo if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN)) 1668b83f1527SRafal Ozieblo return features & ~MACB_NETIF_LSO; 1669b83f1527SRafal Ozieblo 1670b83f1527SRafal Ozieblo nr_frags = skb_shinfo(skb)->nr_frags; 1671b83f1527SRafal Ozieblo /* No need to check last fragment */ 1672b83f1527SRafal Ozieblo nr_frags--; 1673b83f1527SRafal Ozieblo for (f = 0; f < nr_frags; f++) { 1674b83f1527SRafal Ozieblo const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1675b83f1527SRafal Ozieblo 1676b83f1527SRafal Ozieblo if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN)) 1677b83f1527SRafal Ozieblo return features & ~MACB_NETIF_LSO; 1678b83f1527SRafal Ozieblo } 1679b83f1527SRafal Ozieblo return features; 1680b83f1527SRafal Ozieblo } 1681b83f1527SRafal Ozieblo 1682b83f1527SRafal Ozieblo static inline int macb_clear_csum(struct sk_buff *skb) 1683b83f1527SRafal Ozieblo { 1684b83f1527SRafal Ozieblo /* no change for packets without checksum offloading */ 1685b83f1527SRafal Ozieblo if (skb->ip_summed != CHECKSUM_PARTIAL) 1686b83f1527SRafal Ozieblo return 0; 1687b83f1527SRafal Ozieblo 1688b83f1527SRafal Ozieblo /* make sure we can modify the header */ 1689b83f1527SRafal Ozieblo if (unlikely(skb_cow_head(skb, 0))) 1690b83f1527SRafal Ozieblo return -1; 1691b83f1527SRafal Ozieblo 1692b83f1527SRafal Ozieblo /* initialize checksum field 1693b83f1527SRafal Ozieblo * This is required - at least for Zynq, which otherwise calculates 1694b83f1527SRafal Ozieblo * wrong UDP header checksums for UDP packets with UDP data len <=2 1695b83f1527SRafal Ozieblo */ 1696b83f1527SRafal Ozieblo *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0; 1697b83f1527SRafal Ozieblo return 0; 1698b83f1527SRafal Ozieblo } 1699b83f1527SRafal Ozieblo 1700653e92a9SClaudiu Beznea static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev) 1701653e92a9SClaudiu Beznea { 1702653e92a9SClaudiu Beznea bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb); 1703653e92a9SClaudiu Beznea int padlen = ETH_ZLEN - (*skb)->len; 1704653e92a9SClaudiu Beznea int headroom = skb_headroom(*skb); 1705653e92a9SClaudiu Beznea int tailroom = skb_tailroom(*skb); 1706653e92a9SClaudiu Beznea struct sk_buff *nskb; 1707653e92a9SClaudiu Beznea u32 fcs; 1708653e92a9SClaudiu Beznea 1709653e92a9SClaudiu Beznea if (!(ndev->features & NETIF_F_HW_CSUM) || 1710653e92a9SClaudiu Beznea !((*skb)->ip_summed != CHECKSUM_PARTIAL) || 1711653e92a9SClaudiu Beznea skb_shinfo(*skb)->gso_size) /* Not available for GSO */ 1712653e92a9SClaudiu Beznea return 0; 1713653e92a9SClaudiu Beznea 1714653e92a9SClaudiu Beznea if (padlen <= 0) { 1715653e92a9SClaudiu Beznea /* FCS could be appeded to tailroom. */ 1716653e92a9SClaudiu Beznea if (tailroom >= ETH_FCS_LEN) 1717653e92a9SClaudiu Beznea goto add_fcs; 1718653e92a9SClaudiu Beznea /* FCS could be appeded by moving data to headroom. */ 1719653e92a9SClaudiu Beznea else if (!cloned && headroom + tailroom >= ETH_FCS_LEN) 1720653e92a9SClaudiu Beznea padlen = 0; 1721653e92a9SClaudiu Beznea /* No room for FCS, need to reallocate skb. */ 1722653e92a9SClaudiu Beznea else 1723899ecaedSTristram Ha padlen = ETH_FCS_LEN; 1724653e92a9SClaudiu Beznea } else { 1725653e92a9SClaudiu Beznea /* Add room for FCS. */ 1726653e92a9SClaudiu Beznea padlen += ETH_FCS_LEN; 1727653e92a9SClaudiu Beznea } 1728653e92a9SClaudiu Beznea 1729653e92a9SClaudiu Beznea if (!cloned && headroom + tailroom >= padlen) { 1730653e92a9SClaudiu Beznea (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len); 1731653e92a9SClaudiu Beznea skb_set_tail_pointer(*skb, (*skb)->len); 1732653e92a9SClaudiu Beznea } else { 1733653e92a9SClaudiu Beznea nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC); 1734653e92a9SClaudiu Beznea if (!nskb) 1735653e92a9SClaudiu Beznea return -ENOMEM; 1736653e92a9SClaudiu Beznea 1737653e92a9SClaudiu Beznea dev_kfree_skb_any(*skb); 1738653e92a9SClaudiu Beznea *skb = nskb; 1739653e92a9SClaudiu Beznea } 1740653e92a9SClaudiu Beznea 1741*ba3e1847SClaudiu Beznea if (padlen > ETH_FCS_LEN) 1742653e92a9SClaudiu Beznea skb_put_zero(*skb, padlen - ETH_FCS_LEN); 1743653e92a9SClaudiu Beznea 1744653e92a9SClaudiu Beznea add_fcs: 1745653e92a9SClaudiu Beznea /* set FCS to packet */ 1746653e92a9SClaudiu Beznea fcs = crc32_le(~0, (*skb)->data, (*skb)->len); 1747653e92a9SClaudiu Beznea fcs = ~fcs; 1748653e92a9SClaudiu Beznea 1749653e92a9SClaudiu Beznea skb_put_u8(*skb, fcs & 0xff); 1750653e92a9SClaudiu Beznea skb_put_u8(*skb, (fcs >> 8) & 0xff); 1751653e92a9SClaudiu Beznea skb_put_u8(*skb, (fcs >> 16) & 0xff); 1752653e92a9SClaudiu Beznea skb_put_u8(*skb, (fcs >> 24) & 0xff); 1753653e92a9SClaudiu Beznea 1754653e92a9SClaudiu Beznea return 0; 1755653e92a9SClaudiu Beznea } 1756653e92a9SClaudiu Beznea 1757d1c38957SClaudiu Beznea static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev) 1758b83f1527SRafal Ozieblo { 1759b83f1527SRafal Ozieblo u16 queue_index = skb_get_queue_mapping(skb); 1760b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 1761b83f1527SRafal Ozieblo struct macb_queue *queue = &bp->queues[queue_index]; 1762b83f1527SRafal Ozieblo unsigned long flags; 1763b83f1527SRafal Ozieblo unsigned int desc_cnt, nr_frags, frag_size, f; 1764b83f1527SRafal Ozieblo unsigned int hdrlen; 1765b83f1527SRafal Ozieblo bool is_lso, is_udp = 0; 1766d1c38957SClaudiu Beznea netdev_tx_t ret = NETDEV_TX_OK; 1767b83f1527SRafal Ozieblo 176833729f25SClaudiu Beznea if (macb_clear_csum(skb)) { 176933729f25SClaudiu Beznea dev_kfree_skb_any(skb); 177033729f25SClaudiu Beznea return ret; 177133729f25SClaudiu Beznea } 177233729f25SClaudiu Beznea 1773653e92a9SClaudiu Beznea if (macb_pad_and_fcs(&skb, dev)) { 1774653e92a9SClaudiu Beznea dev_kfree_skb_any(skb); 1775653e92a9SClaudiu Beznea return ret; 1776653e92a9SClaudiu Beznea } 1777653e92a9SClaudiu Beznea 1778b83f1527SRafal Ozieblo is_lso = (skb_shinfo(skb)->gso_size != 0); 1779b83f1527SRafal Ozieblo 1780b83f1527SRafal Ozieblo if (is_lso) { 1781b83f1527SRafal Ozieblo is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP); 1782b83f1527SRafal Ozieblo 1783b83f1527SRafal Ozieblo /* length of headers */ 1784b83f1527SRafal Ozieblo if (is_udp) 1785b83f1527SRafal Ozieblo /* only queue eth + ip headers separately for UDP */ 1786b83f1527SRafal Ozieblo hdrlen = skb_transport_offset(skb); 1787b83f1527SRafal Ozieblo else 1788b83f1527SRafal Ozieblo hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb); 1789b83f1527SRafal Ozieblo if (skb_headlen(skb) < hdrlen) { 1790b83f1527SRafal Ozieblo netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n"); 1791b83f1527SRafal Ozieblo /* if this is required, would need to copy to single buffer */ 1792b83f1527SRafal Ozieblo return NETDEV_TX_BUSY; 1793b83f1527SRafal Ozieblo } 1794b83f1527SRafal Ozieblo } else 1795b83f1527SRafal Ozieblo hdrlen = min(skb_headlen(skb), bp->max_tx_length); 1796b83f1527SRafal Ozieblo 1797b83f1527SRafal Ozieblo #if defined(DEBUG) && defined(VERBOSE_DEBUG) 1798b83f1527SRafal Ozieblo netdev_vdbg(bp->dev, 1799b83f1527SRafal Ozieblo "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n", 1800b83f1527SRafal Ozieblo queue_index, skb->len, skb->head, skb->data, 1801b83f1527SRafal Ozieblo skb_tail_pointer(skb), skb_end_pointer(skb)); 1802b83f1527SRafal Ozieblo print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, 1803b83f1527SRafal Ozieblo skb->data, 16, true); 1804b83f1527SRafal Ozieblo #endif 1805b83f1527SRafal Ozieblo 1806b83f1527SRafal Ozieblo /* Count how many TX buffer descriptors are needed to send this 1807b83f1527SRafal Ozieblo * socket buffer: skb fragments of jumbo frames may need to be 1808b83f1527SRafal Ozieblo * split into many buffer descriptors. 1809b83f1527SRafal Ozieblo */ 1810b83f1527SRafal Ozieblo if (is_lso && (skb_headlen(skb) > hdrlen)) 1811b83f1527SRafal Ozieblo /* extra header descriptor if also payload in first buffer */ 1812b83f1527SRafal Ozieblo desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1; 1813b83f1527SRafal Ozieblo else 1814b83f1527SRafal Ozieblo desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length); 1815b83f1527SRafal Ozieblo nr_frags = skb_shinfo(skb)->nr_frags; 1816b83f1527SRafal Ozieblo for (f = 0; f < nr_frags; f++) { 1817b83f1527SRafal Ozieblo frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); 1818b83f1527SRafal Ozieblo desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length); 1819b83f1527SRafal Ozieblo } 1820b83f1527SRafal Ozieblo 1821b83f1527SRafal Ozieblo spin_lock_irqsave(&bp->lock, flags); 1822b83f1527SRafal Ozieblo 1823b83f1527SRafal Ozieblo /* This is a hard error, log it. */ 1824b83f1527SRafal Ozieblo if (CIRC_SPACE(queue->tx_head, queue->tx_tail, 1825b83f1527SRafal Ozieblo bp->tx_ring_size) < desc_cnt) { 1826b83f1527SRafal Ozieblo netif_stop_subqueue(dev, queue_index); 1827b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags); 1828b83f1527SRafal Ozieblo netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", 1829b83f1527SRafal Ozieblo queue->tx_head, queue->tx_tail); 1830b83f1527SRafal Ozieblo return NETDEV_TX_BUSY; 1831b83f1527SRafal Ozieblo } 1832b83f1527SRafal Ozieblo 1833b83f1527SRafal Ozieblo /* Map socket buffer for DMA transfer */ 1834b83f1527SRafal Ozieblo if (!macb_tx_map(bp, queue, skb, hdrlen)) { 1835b83f1527SRafal Ozieblo dev_kfree_skb_any(skb); 1836b83f1527SRafal Ozieblo goto unlock; 1837b83f1527SRafal Ozieblo } 1838b83f1527SRafal Ozieblo 1839b83f1527SRafal Ozieblo /* Make newly initialized descriptor visible to hardware */ 1840b83f1527SRafal Ozieblo wmb(); 1841b83f1527SRafal Ozieblo skb_tx_timestamp(skb); 1842b83f1527SRafal Ozieblo 1843b83f1527SRafal Ozieblo macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 1844b83f1527SRafal Ozieblo 1845b83f1527SRafal Ozieblo if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1) 1846b83f1527SRafal Ozieblo netif_stop_subqueue(dev, queue_index); 1847b83f1527SRafal Ozieblo 1848b83f1527SRafal Ozieblo unlock: 1849b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags); 1850b83f1527SRafal Ozieblo 1851d1c38957SClaudiu Beznea return ret; 1852b83f1527SRafal Ozieblo } 1853b83f1527SRafal Ozieblo 1854b83f1527SRafal Ozieblo static void macb_init_rx_buffer_size(struct macb *bp, size_t size) 1855b83f1527SRafal Ozieblo { 1856b83f1527SRafal Ozieblo if (!macb_is_gem(bp)) { 1857b83f1527SRafal Ozieblo bp->rx_buffer_size = MACB_RX_BUFFER_SIZE; 1858b83f1527SRafal Ozieblo } else { 1859b83f1527SRafal Ozieblo bp->rx_buffer_size = size; 1860b83f1527SRafal Ozieblo 1861b83f1527SRafal Ozieblo if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) { 1862b83f1527SRafal Ozieblo netdev_dbg(bp->dev, 1863b83f1527SRafal Ozieblo "RX buffer must be multiple of %d bytes, expanding\n", 1864b83f1527SRafal Ozieblo RX_BUFFER_MULTIPLE); 1865b83f1527SRafal Ozieblo bp->rx_buffer_size = 1866b83f1527SRafal Ozieblo roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE); 1867b83f1527SRafal Ozieblo } 1868b83f1527SRafal Ozieblo } 1869b83f1527SRafal Ozieblo 1870b83f1527SRafal Ozieblo netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n", 1871b83f1527SRafal Ozieblo bp->dev->mtu, bp->rx_buffer_size); 1872b83f1527SRafal Ozieblo } 1873b83f1527SRafal Ozieblo 1874b83f1527SRafal Ozieblo static void gem_free_rx_buffers(struct macb *bp) 1875b83f1527SRafal Ozieblo { 1876b83f1527SRafal Ozieblo struct sk_buff *skb; 1877b83f1527SRafal Ozieblo struct macb_dma_desc *desc; 1878ae1f2a56SRafal Ozieblo struct macb_queue *queue; 1879b83f1527SRafal Ozieblo dma_addr_t addr; 1880ae1f2a56SRafal Ozieblo unsigned int q; 1881b83f1527SRafal Ozieblo int i; 1882b83f1527SRafal Ozieblo 1883ae1f2a56SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 1884ae1f2a56SRafal Ozieblo if (!queue->rx_skbuff) 1885ae1f2a56SRafal Ozieblo continue; 1886b83f1527SRafal Ozieblo 1887b83f1527SRafal Ozieblo for (i = 0; i < bp->rx_ring_size; i++) { 1888ae1f2a56SRafal Ozieblo skb = queue->rx_skbuff[i]; 1889b83f1527SRafal Ozieblo 1890b83f1527SRafal Ozieblo if (!skb) 1891b83f1527SRafal Ozieblo continue; 1892b83f1527SRafal Ozieblo 1893ae1f2a56SRafal Ozieblo desc = macb_rx_desc(queue, i); 1894b83f1527SRafal Ozieblo addr = macb_get_addr(bp, desc); 1895b83f1527SRafal Ozieblo 1896b83f1527SRafal Ozieblo dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size, 1897b83f1527SRafal Ozieblo DMA_FROM_DEVICE); 1898b83f1527SRafal Ozieblo dev_kfree_skb_any(skb); 1899b83f1527SRafal Ozieblo skb = NULL; 1900b83f1527SRafal Ozieblo } 1901b83f1527SRafal Ozieblo 1902ae1f2a56SRafal Ozieblo kfree(queue->rx_skbuff); 1903ae1f2a56SRafal Ozieblo queue->rx_skbuff = NULL; 1904ae1f2a56SRafal Ozieblo } 1905b83f1527SRafal Ozieblo } 1906b83f1527SRafal Ozieblo 1907b83f1527SRafal Ozieblo static void macb_free_rx_buffers(struct macb *bp) 1908b83f1527SRafal Ozieblo { 1909ae1f2a56SRafal Ozieblo struct macb_queue *queue = &bp->queues[0]; 1910ae1f2a56SRafal Ozieblo 1911ae1f2a56SRafal Ozieblo if (queue->rx_buffers) { 1912b83f1527SRafal Ozieblo dma_free_coherent(&bp->pdev->dev, 1913b83f1527SRafal Ozieblo bp->rx_ring_size * bp->rx_buffer_size, 1914ae1f2a56SRafal Ozieblo queue->rx_buffers, queue->rx_buffers_dma); 1915ae1f2a56SRafal Ozieblo queue->rx_buffers = NULL; 1916b83f1527SRafal Ozieblo } 1917b83f1527SRafal Ozieblo } 1918b83f1527SRafal Ozieblo 1919b83f1527SRafal Ozieblo static void macb_free_consistent(struct macb *bp) 1920b83f1527SRafal Ozieblo { 1921b83f1527SRafal Ozieblo struct macb_queue *queue; 1922b83f1527SRafal Ozieblo unsigned int q; 1923404cd086SHarini Katakam int size; 1924b83f1527SRafal Ozieblo 1925b83f1527SRafal Ozieblo bp->macbgem_ops.mog_free_rx_buffers(bp); 1926b83f1527SRafal Ozieblo 1927b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 1928b83f1527SRafal Ozieblo kfree(queue->tx_skb); 1929b83f1527SRafal Ozieblo queue->tx_skb = NULL; 1930b83f1527SRafal Ozieblo if (queue->tx_ring) { 1931404cd086SHarini Katakam size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch; 1932404cd086SHarini Katakam dma_free_coherent(&bp->pdev->dev, size, 1933b83f1527SRafal Ozieblo queue->tx_ring, queue->tx_ring_dma); 1934b83f1527SRafal Ozieblo queue->tx_ring = NULL; 1935b83f1527SRafal Ozieblo } 1936e50b770eSHarini Katakam if (queue->rx_ring) { 1937404cd086SHarini Katakam size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; 1938404cd086SHarini Katakam dma_free_coherent(&bp->pdev->dev, size, 1939e50b770eSHarini Katakam queue->rx_ring, queue->rx_ring_dma); 1940e50b770eSHarini Katakam queue->rx_ring = NULL; 1941e50b770eSHarini Katakam } 1942b83f1527SRafal Ozieblo } 1943b83f1527SRafal Ozieblo } 1944b83f1527SRafal Ozieblo 1945b83f1527SRafal Ozieblo static int gem_alloc_rx_buffers(struct macb *bp) 1946b83f1527SRafal Ozieblo { 1947ae1f2a56SRafal Ozieblo struct macb_queue *queue; 1948ae1f2a56SRafal Ozieblo unsigned int q; 1949b83f1527SRafal Ozieblo int size; 1950b83f1527SRafal Ozieblo 1951ae1f2a56SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 1952b83f1527SRafal Ozieblo size = bp->rx_ring_size * sizeof(struct sk_buff *); 1953ae1f2a56SRafal Ozieblo queue->rx_skbuff = kzalloc(size, GFP_KERNEL); 1954ae1f2a56SRafal Ozieblo if (!queue->rx_skbuff) 1955b83f1527SRafal Ozieblo return -ENOMEM; 1956b83f1527SRafal Ozieblo else 1957b83f1527SRafal Ozieblo netdev_dbg(bp->dev, 1958b83f1527SRafal Ozieblo "Allocated %d RX struct sk_buff entries at %p\n", 1959ae1f2a56SRafal Ozieblo bp->rx_ring_size, queue->rx_skbuff); 1960ae1f2a56SRafal Ozieblo } 1961b83f1527SRafal Ozieblo return 0; 1962b83f1527SRafal Ozieblo } 1963b83f1527SRafal Ozieblo 1964b83f1527SRafal Ozieblo static int macb_alloc_rx_buffers(struct macb *bp) 1965b83f1527SRafal Ozieblo { 1966ae1f2a56SRafal Ozieblo struct macb_queue *queue = &bp->queues[0]; 1967b83f1527SRafal Ozieblo int size; 1968b83f1527SRafal Ozieblo 1969b83f1527SRafal Ozieblo size = bp->rx_ring_size * bp->rx_buffer_size; 1970ae1f2a56SRafal Ozieblo queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, 1971ae1f2a56SRafal Ozieblo &queue->rx_buffers_dma, GFP_KERNEL); 1972ae1f2a56SRafal Ozieblo if (!queue->rx_buffers) 1973b83f1527SRafal Ozieblo return -ENOMEM; 1974b83f1527SRafal Ozieblo 1975b83f1527SRafal Ozieblo netdev_dbg(bp->dev, 1976b83f1527SRafal Ozieblo "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", 1977ae1f2a56SRafal Ozieblo size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers); 1978b83f1527SRafal Ozieblo return 0; 1979b83f1527SRafal Ozieblo } 1980b83f1527SRafal Ozieblo 1981b83f1527SRafal Ozieblo static int macb_alloc_consistent(struct macb *bp) 1982b83f1527SRafal Ozieblo { 1983b83f1527SRafal Ozieblo struct macb_queue *queue; 1984b83f1527SRafal Ozieblo unsigned int q; 1985b83f1527SRafal Ozieblo int size; 1986b83f1527SRafal Ozieblo 1987b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 1988404cd086SHarini Katakam size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch; 1989b83f1527SRafal Ozieblo queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, 1990b83f1527SRafal Ozieblo &queue->tx_ring_dma, 1991b83f1527SRafal Ozieblo GFP_KERNEL); 1992b83f1527SRafal Ozieblo if (!queue->tx_ring) 1993b83f1527SRafal Ozieblo goto out_err; 1994b83f1527SRafal Ozieblo netdev_dbg(bp->dev, 1995b83f1527SRafal Ozieblo "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n", 1996b83f1527SRafal Ozieblo q, size, (unsigned long)queue->tx_ring_dma, 1997b83f1527SRafal Ozieblo queue->tx_ring); 1998b83f1527SRafal Ozieblo 1999b83f1527SRafal Ozieblo size = bp->tx_ring_size * sizeof(struct macb_tx_skb); 2000b83f1527SRafal Ozieblo queue->tx_skb = kmalloc(size, GFP_KERNEL); 2001b83f1527SRafal Ozieblo if (!queue->tx_skb) 2002b83f1527SRafal Ozieblo goto out_err; 2003b83f1527SRafal Ozieblo 2004404cd086SHarini Katakam size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; 2005ae1f2a56SRafal Ozieblo queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, 2006ae1f2a56SRafal Ozieblo &queue->rx_ring_dma, GFP_KERNEL); 2007ae1f2a56SRafal Ozieblo if (!queue->rx_ring) 2008b83f1527SRafal Ozieblo goto out_err; 2009b83f1527SRafal Ozieblo netdev_dbg(bp->dev, 2010b83f1527SRafal Ozieblo "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", 2011ae1f2a56SRafal Ozieblo size, (unsigned long)queue->rx_ring_dma, queue->rx_ring); 2012ae1f2a56SRafal Ozieblo } 2013b83f1527SRafal Ozieblo if (bp->macbgem_ops.mog_alloc_rx_buffers(bp)) 2014b83f1527SRafal Ozieblo goto out_err; 2015b83f1527SRafal Ozieblo 2016b83f1527SRafal Ozieblo return 0; 2017b83f1527SRafal Ozieblo 2018b83f1527SRafal Ozieblo out_err: 2019b83f1527SRafal Ozieblo macb_free_consistent(bp); 2020b83f1527SRafal Ozieblo return -ENOMEM; 2021b83f1527SRafal Ozieblo } 2022b83f1527SRafal Ozieblo 2023b83f1527SRafal Ozieblo static void gem_init_rings(struct macb *bp) 2024b83f1527SRafal Ozieblo { 2025b83f1527SRafal Ozieblo struct macb_queue *queue; 2026b83f1527SRafal Ozieblo struct macb_dma_desc *desc = NULL; 2027b83f1527SRafal Ozieblo unsigned int q; 2028b83f1527SRafal Ozieblo int i; 2029b83f1527SRafal Ozieblo 2030b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2031b83f1527SRafal Ozieblo for (i = 0; i < bp->tx_ring_size; i++) { 2032b83f1527SRafal Ozieblo desc = macb_tx_desc(queue, i); 2033b83f1527SRafal Ozieblo macb_set_addr(bp, desc, 0); 2034b83f1527SRafal Ozieblo desc->ctrl = MACB_BIT(TX_USED); 2035b83f1527SRafal Ozieblo } 2036b83f1527SRafal Ozieblo desc->ctrl |= MACB_BIT(TX_WRAP); 2037b83f1527SRafal Ozieblo queue->tx_head = 0; 2038b83f1527SRafal Ozieblo queue->tx_tail = 0; 2039ae1f2a56SRafal Ozieblo 2040ae1f2a56SRafal Ozieblo queue->rx_tail = 0; 2041ae1f2a56SRafal Ozieblo queue->rx_prepared_head = 0; 2042ae1f2a56SRafal Ozieblo 2043ae1f2a56SRafal Ozieblo gem_rx_refill(queue); 2044b83f1527SRafal Ozieblo } 2045b83f1527SRafal Ozieblo 2046b83f1527SRafal Ozieblo } 2047b83f1527SRafal Ozieblo 2048b83f1527SRafal Ozieblo static void macb_init_rings(struct macb *bp) 2049b83f1527SRafal Ozieblo { 2050b83f1527SRafal Ozieblo int i; 2051b83f1527SRafal Ozieblo struct macb_dma_desc *desc = NULL; 2052b83f1527SRafal Ozieblo 2053ae1f2a56SRafal Ozieblo macb_init_rx_ring(&bp->queues[0]); 2054b83f1527SRafal Ozieblo 2055b83f1527SRafal Ozieblo for (i = 0; i < bp->tx_ring_size; i++) { 2056b83f1527SRafal Ozieblo desc = macb_tx_desc(&bp->queues[0], i); 2057b83f1527SRafal Ozieblo macb_set_addr(bp, desc, 0); 2058b83f1527SRafal Ozieblo desc->ctrl = MACB_BIT(TX_USED); 2059b83f1527SRafal Ozieblo } 2060b83f1527SRafal Ozieblo bp->queues[0].tx_head = 0; 2061b83f1527SRafal Ozieblo bp->queues[0].tx_tail = 0; 2062b83f1527SRafal Ozieblo desc->ctrl |= MACB_BIT(TX_WRAP); 2063b83f1527SRafal Ozieblo } 2064b83f1527SRafal Ozieblo 2065b83f1527SRafal Ozieblo static void macb_reset_hw(struct macb *bp) 2066b83f1527SRafal Ozieblo { 2067b83f1527SRafal Ozieblo struct macb_queue *queue; 2068b83f1527SRafal Ozieblo unsigned int q; 20690da70f80SAnssi Hannula u32 ctrl = macb_readl(bp, NCR); 2070b83f1527SRafal Ozieblo 2071b83f1527SRafal Ozieblo /* Disable RX and TX (XXX: Should we halt the transmission 2072b83f1527SRafal Ozieblo * more gracefully?) 2073b83f1527SRafal Ozieblo */ 20740da70f80SAnssi Hannula ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE)); 2075b83f1527SRafal Ozieblo 2076b83f1527SRafal Ozieblo /* Clear the stats registers (XXX: Update stats first?) */ 20770da70f80SAnssi Hannula ctrl |= MACB_BIT(CLRSTAT); 20780da70f80SAnssi Hannula 20790da70f80SAnssi Hannula macb_writel(bp, NCR, ctrl); 2080b83f1527SRafal Ozieblo 2081b83f1527SRafal Ozieblo /* Clear all status flags */ 2082b83f1527SRafal Ozieblo macb_writel(bp, TSR, -1); 2083b83f1527SRafal Ozieblo macb_writel(bp, RSR, -1); 2084b83f1527SRafal Ozieblo 2085b83f1527SRafal Ozieblo /* Disable all interrupts */ 2086b83f1527SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2087b83f1527SRafal Ozieblo queue_writel(queue, IDR, -1); 2088b83f1527SRafal Ozieblo queue_readl(queue, ISR); 2089b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 2090b83f1527SRafal Ozieblo queue_writel(queue, ISR, -1); 2091b83f1527SRafal Ozieblo } 2092b83f1527SRafal Ozieblo } 2093b83f1527SRafal Ozieblo 2094b83f1527SRafal Ozieblo static u32 gem_mdc_clk_div(struct macb *bp) 2095b83f1527SRafal Ozieblo { 2096b83f1527SRafal Ozieblo u32 config; 2097b83f1527SRafal Ozieblo unsigned long pclk_hz = clk_get_rate(bp->pclk); 2098b83f1527SRafal Ozieblo 2099b83f1527SRafal Ozieblo if (pclk_hz <= 20000000) 2100b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV8); 2101b83f1527SRafal Ozieblo else if (pclk_hz <= 40000000) 2102b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV16); 2103b83f1527SRafal Ozieblo else if (pclk_hz <= 80000000) 2104b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV32); 2105b83f1527SRafal Ozieblo else if (pclk_hz <= 120000000) 2106b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV48); 2107b83f1527SRafal Ozieblo else if (pclk_hz <= 160000000) 2108b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV64); 2109b83f1527SRafal Ozieblo else 2110b83f1527SRafal Ozieblo config = GEM_BF(CLK, GEM_CLK_DIV96); 2111b83f1527SRafal Ozieblo 2112b83f1527SRafal Ozieblo return config; 2113b83f1527SRafal Ozieblo } 2114b83f1527SRafal Ozieblo 2115b83f1527SRafal Ozieblo static u32 macb_mdc_clk_div(struct macb *bp) 2116b83f1527SRafal Ozieblo { 2117b83f1527SRafal Ozieblo u32 config; 2118b83f1527SRafal Ozieblo unsigned long pclk_hz; 2119b83f1527SRafal Ozieblo 2120b83f1527SRafal Ozieblo if (macb_is_gem(bp)) 2121b83f1527SRafal Ozieblo return gem_mdc_clk_div(bp); 2122b83f1527SRafal Ozieblo 2123b83f1527SRafal Ozieblo pclk_hz = clk_get_rate(bp->pclk); 2124b83f1527SRafal Ozieblo if (pclk_hz <= 20000000) 2125b83f1527SRafal Ozieblo config = MACB_BF(CLK, MACB_CLK_DIV8); 2126b83f1527SRafal Ozieblo else if (pclk_hz <= 40000000) 2127b83f1527SRafal Ozieblo config = MACB_BF(CLK, MACB_CLK_DIV16); 2128b83f1527SRafal Ozieblo else if (pclk_hz <= 80000000) 2129b83f1527SRafal Ozieblo config = MACB_BF(CLK, MACB_CLK_DIV32); 2130b83f1527SRafal Ozieblo else 2131b83f1527SRafal Ozieblo config = MACB_BF(CLK, MACB_CLK_DIV64); 2132b83f1527SRafal Ozieblo 2133b83f1527SRafal Ozieblo return config; 2134b83f1527SRafal Ozieblo } 2135b83f1527SRafal Ozieblo 2136b83f1527SRafal Ozieblo /* Get the DMA bus width field of the network configuration register that we 2137b83f1527SRafal Ozieblo * should program. We find the width from decoding the design configuration 2138b83f1527SRafal Ozieblo * register to find the maximum supported data bus width. 2139b83f1527SRafal Ozieblo */ 2140b83f1527SRafal Ozieblo static u32 macb_dbw(struct macb *bp) 2141b83f1527SRafal Ozieblo { 2142b83f1527SRafal Ozieblo if (!macb_is_gem(bp)) 2143b83f1527SRafal Ozieblo return 0; 2144b83f1527SRafal Ozieblo 2145b83f1527SRafal Ozieblo switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { 2146b83f1527SRafal Ozieblo case 4: 2147b83f1527SRafal Ozieblo return GEM_BF(DBW, GEM_DBW128); 2148b83f1527SRafal Ozieblo case 2: 2149b83f1527SRafal Ozieblo return GEM_BF(DBW, GEM_DBW64); 2150b83f1527SRafal Ozieblo case 1: 2151b83f1527SRafal Ozieblo default: 2152b83f1527SRafal Ozieblo return GEM_BF(DBW, GEM_DBW32); 2153b83f1527SRafal Ozieblo } 2154b83f1527SRafal Ozieblo } 2155b83f1527SRafal Ozieblo 2156b83f1527SRafal Ozieblo /* Configure the receive DMA engine 2157b83f1527SRafal Ozieblo * - use the correct receive buffer size 2158b83f1527SRafal Ozieblo * - set best burst length for DMA operations 2159b83f1527SRafal Ozieblo * (if not supported by FIFO, it will fallback to default) 2160b83f1527SRafal Ozieblo * - set both rx/tx packet buffers to full memory size 2161b83f1527SRafal Ozieblo * These are configurable parameters for GEM. 2162b83f1527SRafal Ozieblo */ 2163b83f1527SRafal Ozieblo static void macb_configure_dma(struct macb *bp) 2164b83f1527SRafal Ozieblo { 2165ae1f2a56SRafal Ozieblo struct macb_queue *queue; 2166ae1f2a56SRafal Ozieblo u32 buffer_size; 2167ae1f2a56SRafal Ozieblo unsigned int q; 2168b83f1527SRafal Ozieblo u32 dmacfg; 2169b83f1527SRafal Ozieblo 2170ae1f2a56SRafal Ozieblo buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE; 2171b83f1527SRafal Ozieblo if (macb_is_gem(bp)) { 2172b83f1527SRafal Ozieblo dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); 2173ae1f2a56SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2174ae1f2a56SRafal Ozieblo if (q) 2175ae1f2a56SRafal Ozieblo queue_writel(queue, RBQS, buffer_size); 2176ae1f2a56SRafal Ozieblo else 2177ae1f2a56SRafal Ozieblo dmacfg |= GEM_BF(RXBS, buffer_size); 2178ae1f2a56SRafal Ozieblo } 2179b83f1527SRafal Ozieblo if (bp->dma_burst_length) 2180b83f1527SRafal Ozieblo dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); 2181b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); 2182b83f1527SRafal Ozieblo dmacfg &= ~GEM_BIT(ENDIA_PKT); 2183b83f1527SRafal Ozieblo 2184b83f1527SRafal Ozieblo if (bp->native_io) 2185b83f1527SRafal Ozieblo dmacfg &= ~GEM_BIT(ENDIA_DESC); 2186b83f1527SRafal Ozieblo else 2187b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */ 2188b83f1527SRafal Ozieblo 2189b83f1527SRafal Ozieblo if (bp->dev->features & NETIF_F_HW_CSUM) 2190b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(TXCOEN); 2191b83f1527SRafal Ozieblo else 2192b83f1527SRafal Ozieblo dmacfg &= ~GEM_BIT(TXCOEN); 2193b83f1527SRafal Ozieblo 2194bd620720SMichal Simek dmacfg &= ~GEM_BIT(ADDR64); 2195b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 2196b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) 2197b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(ADDR64); 2198b83f1527SRafal Ozieblo #endif 2199b83f1527SRafal Ozieblo #ifdef CONFIG_MACB_USE_HWSTAMP 2200b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_PTP) 2201b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT); 2202b83f1527SRafal Ozieblo #endif 2203b83f1527SRafal Ozieblo netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n", 2204b83f1527SRafal Ozieblo dmacfg); 2205b83f1527SRafal Ozieblo gem_writel(bp, DMACFG, dmacfg); 2206b83f1527SRafal Ozieblo } 2207b83f1527SRafal Ozieblo } 2208b83f1527SRafal Ozieblo 2209b83f1527SRafal Ozieblo static void macb_init_hw(struct macb *bp) 2210b83f1527SRafal Ozieblo { 2211b83f1527SRafal Ozieblo struct macb_queue *queue; 2212b83f1527SRafal Ozieblo unsigned int q; 2213b83f1527SRafal Ozieblo 2214b83f1527SRafal Ozieblo u32 config; 2215b83f1527SRafal Ozieblo 2216b83f1527SRafal Ozieblo macb_reset_hw(bp); 2217b83f1527SRafal Ozieblo macb_set_hwaddr(bp); 2218b83f1527SRafal Ozieblo 2219b83f1527SRafal Ozieblo config = macb_mdc_clk_div(bp); 2220b83f1527SRafal Ozieblo if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) 2221b83f1527SRafal Ozieblo config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); 2222b83f1527SRafal Ozieblo config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ 2223b83f1527SRafal Ozieblo config |= MACB_BIT(PAE); /* PAuse Enable */ 2224b83f1527SRafal Ozieblo config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ 2225b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_JUMBO) 2226b83f1527SRafal Ozieblo config |= MACB_BIT(JFRAME); /* Enable jumbo frames */ 2227b83f1527SRafal Ozieblo else 2228b83f1527SRafal Ozieblo config |= MACB_BIT(BIG); /* Receive oversized frames */ 2229b83f1527SRafal Ozieblo if (bp->dev->flags & IFF_PROMISC) 2230b83f1527SRafal Ozieblo config |= MACB_BIT(CAF); /* Copy All Frames */ 2231b83f1527SRafal Ozieblo else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM) 2232b83f1527SRafal Ozieblo config |= GEM_BIT(RXCOEN); 2233b83f1527SRafal Ozieblo if (!(bp->dev->flags & IFF_BROADCAST)) 2234b83f1527SRafal Ozieblo config |= MACB_BIT(NBC); /* No BroadCast */ 2235b83f1527SRafal Ozieblo config |= macb_dbw(bp); 2236b83f1527SRafal Ozieblo macb_writel(bp, NCFGR, config); 2237b83f1527SRafal Ozieblo if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len) 2238b83f1527SRafal Ozieblo gem_writel(bp, JML, bp->jumbo_max_len); 2239b83f1527SRafal Ozieblo bp->speed = SPEED_10; 2240b83f1527SRafal Ozieblo bp->duplex = DUPLEX_HALF; 2241b83f1527SRafal Ozieblo bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK; 2242b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_JUMBO) 2243b83f1527SRafal Ozieblo bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; 2244b83f1527SRafal Ozieblo 2245b83f1527SRafal Ozieblo macb_configure_dma(bp); 2246b83f1527SRafal Ozieblo 2247b83f1527SRafal Ozieblo /* Initialize TX and RX buffers */ 2248ae1f2a56SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2249ae1f2a56SRafal Ozieblo queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma)); 2250b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 2251b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) 2252ae1f2a56SRafal Ozieblo queue_writel(queue, RBQPH, upper_32_bits(queue->rx_ring_dma)); 2253b83f1527SRafal Ozieblo #endif 2254b83f1527SRafal Ozieblo queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); 2255b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 2256b83f1527SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) 2257b83f1527SRafal Ozieblo queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); 2258b83f1527SRafal Ozieblo #endif 2259b83f1527SRafal Ozieblo 2260b83f1527SRafal Ozieblo /* Enable interrupts */ 2261b83f1527SRafal Ozieblo queue_writel(queue, IER, 2262b83f1527SRafal Ozieblo MACB_RX_INT_FLAGS | 2263b83f1527SRafal Ozieblo MACB_TX_INT_FLAGS | 2264b83f1527SRafal Ozieblo MACB_BIT(HRESP)); 2265b83f1527SRafal Ozieblo } 2266b83f1527SRafal Ozieblo 2267b83f1527SRafal Ozieblo /* Enable TX and RX */ 22680da70f80SAnssi Hannula macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE)); 2269b83f1527SRafal Ozieblo } 2270b83f1527SRafal Ozieblo 2271b83f1527SRafal Ozieblo /* The hash address register is 64 bits long and takes up two 2272b83f1527SRafal Ozieblo * locations in the memory map. The least significant bits are stored 2273b83f1527SRafal Ozieblo * in EMAC_HSL and the most significant bits in EMAC_HSH. 2274b83f1527SRafal Ozieblo * 2275b83f1527SRafal Ozieblo * The unicast hash enable and the multicast hash enable bits in the 2276b83f1527SRafal Ozieblo * network configuration register enable the reception of hash matched 2277b83f1527SRafal Ozieblo * frames. The destination address is reduced to a 6 bit index into 2278b83f1527SRafal Ozieblo * the 64 bit hash register using the following hash function. The 2279b83f1527SRafal Ozieblo * hash function is an exclusive or of every sixth bit of the 2280b83f1527SRafal Ozieblo * destination address. 2281b83f1527SRafal Ozieblo * 2282b83f1527SRafal Ozieblo * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] 2283b83f1527SRafal Ozieblo * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] 2284b83f1527SRafal Ozieblo * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] 2285b83f1527SRafal Ozieblo * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] 2286b83f1527SRafal Ozieblo * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] 2287b83f1527SRafal Ozieblo * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] 2288b83f1527SRafal Ozieblo * 2289b83f1527SRafal Ozieblo * da[0] represents the least significant bit of the first byte 2290b83f1527SRafal Ozieblo * received, that is, the multicast/unicast indicator, and da[47] 2291b83f1527SRafal Ozieblo * represents the most significant bit of the last byte received. If 2292b83f1527SRafal Ozieblo * the hash index, hi[n], points to a bit that is set in the hash 2293b83f1527SRafal Ozieblo * register then the frame will be matched according to whether the 2294b83f1527SRafal Ozieblo * frame is multicast or unicast. A multicast match will be signalled 2295b83f1527SRafal Ozieblo * if the multicast hash enable bit is set, da[0] is 1 and the hash 2296b83f1527SRafal Ozieblo * index points to a bit set in the hash register. A unicast match 2297b83f1527SRafal Ozieblo * will be signalled if the unicast hash enable bit is set, da[0] is 0 2298b83f1527SRafal Ozieblo * and the hash index points to a bit set in the hash register. To 2299b83f1527SRafal Ozieblo * receive all multicast frames, the hash register should be set with 2300b83f1527SRafal Ozieblo * all ones and the multicast hash enable bit should be set in the 2301b83f1527SRafal Ozieblo * network configuration register. 2302b83f1527SRafal Ozieblo */ 2303b83f1527SRafal Ozieblo 2304b83f1527SRafal Ozieblo static inline int hash_bit_value(int bitnr, __u8 *addr) 2305b83f1527SRafal Ozieblo { 2306b83f1527SRafal Ozieblo if (addr[bitnr / 8] & (1 << (bitnr % 8))) 2307b83f1527SRafal Ozieblo return 1; 2308b83f1527SRafal Ozieblo return 0; 2309b83f1527SRafal Ozieblo } 2310b83f1527SRafal Ozieblo 2311b83f1527SRafal Ozieblo /* Return the hash index value for the specified address. */ 2312b83f1527SRafal Ozieblo static int hash_get_index(__u8 *addr) 2313b83f1527SRafal Ozieblo { 2314b83f1527SRafal Ozieblo int i, j, bitval; 2315b83f1527SRafal Ozieblo int hash_index = 0; 2316b83f1527SRafal Ozieblo 2317b83f1527SRafal Ozieblo for (j = 0; j < 6; j++) { 2318b83f1527SRafal Ozieblo for (i = 0, bitval = 0; i < 8; i++) 2319b83f1527SRafal Ozieblo bitval ^= hash_bit_value(i * 6 + j, addr); 2320b83f1527SRafal Ozieblo 2321b83f1527SRafal Ozieblo hash_index |= (bitval << j); 2322b83f1527SRafal Ozieblo } 2323b83f1527SRafal Ozieblo 2324b83f1527SRafal Ozieblo return hash_index; 2325b83f1527SRafal Ozieblo } 2326b83f1527SRafal Ozieblo 2327b83f1527SRafal Ozieblo /* Add multicast addresses to the internal multicast-hash table. */ 2328b83f1527SRafal Ozieblo static void macb_sethashtable(struct net_device *dev) 2329b83f1527SRafal Ozieblo { 2330b83f1527SRafal Ozieblo struct netdev_hw_addr *ha; 2331b83f1527SRafal Ozieblo unsigned long mc_filter[2]; 2332b83f1527SRafal Ozieblo unsigned int bitnr; 2333b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 2334b83f1527SRafal Ozieblo 2335b83f1527SRafal Ozieblo mc_filter[0] = 0; 2336b83f1527SRafal Ozieblo mc_filter[1] = 0; 2337b83f1527SRafal Ozieblo 2338b83f1527SRafal Ozieblo netdev_for_each_mc_addr(ha, dev) { 2339b83f1527SRafal Ozieblo bitnr = hash_get_index(ha->addr); 2340b83f1527SRafal Ozieblo mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); 2341b83f1527SRafal Ozieblo } 2342b83f1527SRafal Ozieblo 2343b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRB, mc_filter[0]); 2344b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRT, mc_filter[1]); 2345b83f1527SRafal Ozieblo } 2346b83f1527SRafal Ozieblo 2347b83f1527SRafal Ozieblo /* Enable/Disable promiscuous and multicast modes. */ 2348b83f1527SRafal Ozieblo static void macb_set_rx_mode(struct net_device *dev) 2349b83f1527SRafal Ozieblo { 2350b83f1527SRafal Ozieblo unsigned long cfg; 2351b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 2352b83f1527SRafal Ozieblo 2353b83f1527SRafal Ozieblo cfg = macb_readl(bp, NCFGR); 2354b83f1527SRafal Ozieblo 2355b83f1527SRafal Ozieblo if (dev->flags & IFF_PROMISC) { 2356b83f1527SRafal Ozieblo /* Enable promiscuous mode */ 2357b83f1527SRafal Ozieblo cfg |= MACB_BIT(CAF); 2358b83f1527SRafal Ozieblo 2359b83f1527SRafal Ozieblo /* Disable RX checksum offload */ 2360b83f1527SRafal Ozieblo if (macb_is_gem(bp)) 2361b83f1527SRafal Ozieblo cfg &= ~GEM_BIT(RXCOEN); 2362b83f1527SRafal Ozieblo } else { 2363b83f1527SRafal Ozieblo /* Disable promiscuous mode */ 2364b83f1527SRafal Ozieblo cfg &= ~MACB_BIT(CAF); 2365b83f1527SRafal Ozieblo 2366b83f1527SRafal Ozieblo /* Enable RX checksum offload only if requested */ 2367b83f1527SRafal Ozieblo if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM) 2368b83f1527SRafal Ozieblo cfg |= GEM_BIT(RXCOEN); 2369b83f1527SRafal Ozieblo } 2370b83f1527SRafal Ozieblo 2371b83f1527SRafal Ozieblo if (dev->flags & IFF_ALLMULTI) { 2372b83f1527SRafal Ozieblo /* Enable all multicast mode */ 2373b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRB, -1); 2374b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRT, -1); 2375b83f1527SRafal Ozieblo cfg |= MACB_BIT(NCFGR_MTI); 2376b83f1527SRafal Ozieblo } else if (!netdev_mc_empty(dev)) { 2377b83f1527SRafal Ozieblo /* Enable specific multicasts */ 2378b83f1527SRafal Ozieblo macb_sethashtable(dev); 2379b83f1527SRafal Ozieblo cfg |= MACB_BIT(NCFGR_MTI); 2380b83f1527SRafal Ozieblo } else if (dev->flags & (~IFF_ALLMULTI)) { 2381b83f1527SRafal Ozieblo /* Disable all multicast mode */ 2382b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRB, 0); 2383b83f1527SRafal Ozieblo macb_or_gem_writel(bp, HRT, 0); 2384b83f1527SRafal Ozieblo cfg &= ~MACB_BIT(NCFGR_MTI); 2385b83f1527SRafal Ozieblo } 2386b83f1527SRafal Ozieblo 2387b83f1527SRafal Ozieblo macb_writel(bp, NCFGR, cfg); 2388b83f1527SRafal Ozieblo } 2389b83f1527SRafal Ozieblo 2390b83f1527SRafal Ozieblo static int macb_open(struct net_device *dev) 2391b83f1527SRafal Ozieblo { 2392b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 2393b83f1527SRafal Ozieblo size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN; 2394ae1f2a56SRafal Ozieblo struct macb_queue *queue; 2395ae1f2a56SRafal Ozieblo unsigned int q; 2396b83f1527SRafal Ozieblo int err; 2397b83f1527SRafal Ozieblo 2398b83f1527SRafal Ozieblo netdev_dbg(bp->dev, "open\n"); 2399b83f1527SRafal Ozieblo 2400b83f1527SRafal Ozieblo /* carrier starts down */ 2401b83f1527SRafal Ozieblo netif_carrier_off(dev); 2402b83f1527SRafal Ozieblo 2403b83f1527SRafal Ozieblo /* if the phy is not yet register, retry later*/ 2404b83f1527SRafal Ozieblo if (!dev->phydev) 2405b83f1527SRafal Ozieblo return -EAGAIN; 2406b83f1527SRafal Ozieblo 2407b83f1527SRafal Ozieblo /* RX buffers initialization */ 2408b83f1527SRafal Ozieblo macb_init_rx_buffer_size(bp, bufsz); 2409b83f1527SRafal Ozieblo 2410b83f1527SRafal Ozieblo err = macb_alloc_consistent(bp); 2411b83f1527SRafal Ozieblo if (err) { 2412b83f1527SRafal Ozieblo netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", 2413b83f1527SRafal Ozieblo err); 2414b83f1527SRafal Ozieblo return err; 2415b83f1527SRafal Ozieblo } 2416b83f1527SRafal Ozieblo 2417b83f1527SRafal Ozieblo bp->macbgem_ops.mog_init_rings(bp); 2418b83f1527SRafal Ozieblo macb_init_hw(bp); 2419b83f1527SRafal Ozieblo 2420ae1f2a56SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 2421ae1f2a56SRafal Ozieblo napi_enable(&queue->napi); 2422ae1f2a56SRafal Ozieblo 2423b83f1527SRafal Ozieblo /* schedule a link state check */ 2424b83f1527SRafal Ozieblo phy_start(dev->phydev); 2425b83f1527SRafal Ozieblo 2426b83f1527SRafal Ozieblo netif_tx_start_all_queues(dev); 2427b83f1527SRafal Ozieblo 2428b83f1527SRafal Ozieblo if (bp->ptp_info) 2429b83f1527SRafal Ozieblo bp->ptp_info->ptp_init(dev); 2430b83f1527SRafal Ozieblo 2431b83f1527SRafal Ozieblo return 0; 2432b83f1527SRafal Ozieblo } 2433b83f1527SRafal Ozieblo 2434b83f1527SRafal Ozieblo static int macb_close(struct net_device *dev) 2435b83f1527SRafal Ozieblo { 2436b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 2437ae1f2a56SRafal Ozieblo struct macb_queue *queue; 2438b83f1527SRafal Ozieblo unsigned long flags; 2439ae1f2a56SRafal Ozieblo unsigned int q; 2440b83f1527SRafal Ozieblo 2441b83f1527SRafal Ozieblo netif_tx_stop_all_queues(dev); 2442ae1f2a56SRafal Ozieblo 2443ae1f2a56SRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 2444ae1f2a56SRafal Ozieblo napi_disable(&queue->napi); 2445b83f1527SRafal Ozieblo 2446b83f1527SRafal Ozieblo if (dev->phydev) 2447b83f1527SRafal Ozieblo phy_stop(dev->phydev); 2448b83f1527SRafal Ozieblo 2449b83f1527SRafal Ozieblo spin_lock_irqsave(&bp->lock, flags); 2450b83f1527SRafal Ozieblo macb_reset_hw(bp); 2451b83f1527SRafal Ozieblo netif_carrier_off(dev); 2452b83f1527SRafal Ozieblo spin_unlock_irqrestore(&bp->lock, flags); 2453b83f1527SRafal Ozieblo 2454b83f1527SRafal Ozieblo macb_free_consistent(bp); 2455b83f1527SRafal Ozieblo 2456b83f1527SRafal Ozieblo if (bp->ptp_info) 2457b83f1527SRafal Ozieblo bp->ptp_info->ptp_remove(dev); 2458b83f1527SRafal Ozieblo 2459b83f1527SRafal Ozieblo return 0; 2460b83f1527SRafal Ozieblo } 2461b83f1527SRafal Ozieblo 2462b83f1527SRafal Ozieblo static int macb_change_mtu(struct net_device *dev, int new_mtu) 2463b83f1527SRafal Ozieblo { 2464b83f1527SRafal Ozieblo if (netif_running(dev)) 2465b83f1527SRafal Ozieblo return -EBUSY; 2466b83f1527SRafal Ozieblo 2467b83f1527SRafal Ozieblo dev->mtu = new_mtu; 2468b83f1527SRafal Ozieblo 2469b83f1527SRafal Ozieblo return 0; 2470b83f1527SRafal Ozieblo } 2471b83f1527SRafal Ozieblo 2472b83f1527SRafal Ozieblo static void gem_update_stats(struct macb *bp) 2473b83f1527SRafal Ozieblo { 2474512286bbSRafal Ozieblo struct macb_queue *queue; 2475512286bbSRafal Ozieblo unsigned int i, q, idx; 2476512286bbSRafal Ozieblo unsigned long *stat; 2477512286bbSRafal Ozieblo 2478b83f1527SRafal Ozieblo u32 *p = &bp->hw_stats.gem.tx_octets_31_0; 2479b83f1527SRafal Ozieblo 2480b83f1527SRafal Ozieblo for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { 2481b83f1527SRafal Ozieblo u32 offset = gem_statistics[i].offset; 2482b83f1527SRafal Ozieblo u64 val = bp->macb_reg_readl(bp, offset); 2483b83f1527SRafal Ozieblo 2484b83f1527SRafal Ozieblo bp->ethtool_stats[i] += val; 2485b83f1527SRafal Ozieblo *p += val; 2486b83f1527SRafal Ozieblo 2487b83f1527SRafal Ozieblo if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { 2488b83f1527SRafal Ozieblo /* Add GEM_OCTTXH, GEM_OCTRXH */ 2489b83f1527SRafal Ozieblo val = bp->macb_reg_readl(bp, offset + 4); 2490b83f1527SRafal Ozieblo bp->ethtool_stats[i] += ((u64)val) << 32; 2491b83f1527SRafal Ozieblo *(++p) += val; 2492b83f1527SRafal Ozieblo } 2493b83f1527SRafal Ozieblo } 2494512286bbSRafal Ozieblo 2495512286bbSRafal Ozieblo idx = GEM_STATS_LEN; 2496512286bbSRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) 2497512286bbSRafal Ozieblo for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat) 2498512286bbSRafal Ozieblo bp->ethtool_stats[idx++] = *stat; 2499b83f1527SRafal Ozieblo } 2500b83f1527SRafal Ozieblo 2501b83f1527SRafal Ozieblo static struct net_device_stats *gem_get_stats(struct macb *bp) 2502b83f1527SRafal Ozieblo { 2503b83f1527SRafal Ozieblo struct gem_stats *hwstat = &bp->hw_stats.gem; 2504b83f1527SRafal Ozieblo struct net_device_stats *nstat = &bp->dev->stats; 2505b83f1527SRafal Ozieblo 2506b83f1527SRafal Ozieblo gem_update_stats(bp); 2507b83f1527SRafal Ozieblo 2508b83f1527SRafal Ozieblo nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + 2509b83f1527SRafal Ozieblo hwstat->rx_alignment_errors + 2510b83f1527SRafal Ozieblo hwstat->rx_resource_errors + 2511b83f1527SRafal Ozieblo hwstat->rx_overruns + 2512b83f1527SRafal Ozieblo hwstat->rx_oversize_frames + 2513b83f1527SRafal Ozieblo hwstat->rx_jabbers + 2514b83f1527SRafal Ozieblo hwstat->rx_undersized_frames + 2515b83f1527SRafal Ozieblo hwstat->rx_length_field_frame_errors); 2516b83f1527SRafal Ozieblo nstat->tx_errors = (hwstat->tx_late_collisions + 2517b83f1527SRafal Ozieblo hwstat->tx_excessive_collisions + 2518b83f1527SRafal Ozieblo hwstat->tx_underrun + 2519b83f1527SRafal Ozieblo hwstat->tx_carrier_sense_errors); 2520b83f1527SRafal Ozieblo nstat->multicast = hwstat->rx_multicast_frames; 2521b83f1527SRafal Ozieblo nstat->collisions = (hwstat->tx_single_collision_frames + 2522b83f1527SRafal Ozieblo hwstat->tx_multiple_collision_frames + 2523b83f1527SRafal Ozieblo hwstat->tx_excessive_collisions); 2524b83f1527SRafal Ozieblo nstat->rx_length_errors = (hwstat->rx_oversize_frames + 2525b83f1527SRafal Ozieblo hwstat->rx_jabbers + 2526b83f1527SRafal Ozieblo hwstat->rx_undersized_frames + 2527b83f1527SRafal Ozieblo hwstat->rx_length_field_frame_errors); 2528b83f1527SRafal Ozieblo nstat->rx_over_errors = hwstat->rx_resource_errors; 2529b83f1527SRafal Ozieblo nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; 2530b83f1527SRafal Ozieblo nstat->rx_frame_errors = hwstat->rx_alignment_errors; 2531b83f1527SRafal Ozieblo nstat->rx_fifo_errors = hwstat->rx_overruns; 2532b83f1527SRafal Ozieblo nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; 2533b83f1527SRafal Ozieblo nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; 2534b83f1527SRafal Ozieblo nstat->tx_fifo_errors = hwstat->tx_underrun; 2535b83f1527SRafal Ozieblo 2536b83f1527SRafal Ozieblo return nstat; 2537b83f1527SRafal Ozieblo } 2538b83f1527SRafal Ozieblo 2539b83f1527SRafal Ozieblo static void gem_get_ethtool_stats(struct net_device *dev, 2540b83f1527SRafal Ozieblo struct ethtool_stats *stats, u64 *data) 2541b83f1527SRafal Ozieblo { 2542b83f1527SRafal Ozieblo struct macb *bp; 2543b83f1527SRafal Ozieblo 2544b83f1527SRafal Ozieblo bp = netdev_priv(dev); 2545b83f1527SRafal Ozieblo gem_update_stats(bp); 2546512286bbSRafal Ozieblo memcpy(data, &bp->ethtool_stats, sizeof(u64) 2547512286bbSRafal Ozieblo * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES)); 2548b83f1527SRafal Ozieblo } 2549b83f1527SRafal Ozieblo 2550b83f1527SRafal Ozieblo static int gem_get_sset_count(struct net_device *dev, int sset) 2551b83f1527SRafal Ozieblo { 2552512286bbSRafal Ozieblo struct macb *bp = netdev_priv(dev); 2553512286bbSRafal Ozieblo 2554b83f1527SRafal Ozieblo switch (sset) { 2555b83f1527SRafal Ozieblo case ETH_SS_STATS: 2556512286bbSRafal Ozieblo return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN; 2557b83f1527SRafal Ozieblo default: 2558b83f1527SRafal Ozieblo return -EOPNOTSUPP; 2559b83f1527SRafal Ozieblo } 2560b83f1527SRafal Ozieblo } 2561b83f1527SRafal Ozieblo 2562b83f1527SRafal Ozieblo static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p) 2563b83f1527SRafal Ozieblo { 2564512286bbSRafal Ozieblo char stat_string[ETH_GSTRING_LEN]; 2565512286bbSRafal Ozieblo struct macb *bp = netdev_priv(dev); 2566512286bbSRafal Ozieblo struct macb_queue *queue; 2567b83f1527SRafal Ozieblo unsigned int i; 2568512286bbSRafal Ozieblo unsigned int q; 2569b83f1527SRafal Ozieblo 2570b83f1527SRafal Ozieblo switch (sset) { 2571b83f1527SRafal Ozieblo case ETH_SS_STATS: 2572b83f1527SRafal Ozieblo for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN) 2573b83f1527SRafal Ozieblo memcpy(p, gem_statistics[i].stat_string, 2574b83f1527SRafal Ozieblo ETH_GSTRING_LEN); 2575512286bbSRafal Ozieblo 2576512286bbSRafal Ozieblo for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { 2577512286bbSRafal Ozieblo for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) { 2578512286bbSRafal Ozieblo snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s", 2579512286bbSRafal Ozieblo q, queue_statistics[i].stat_string); 2580512286bbSRafal Ozieblo memcpy(p, stat_string, ETH_GSTRING_LEN); 2581512286bbSRafal Ozieblo } 2582512286bbSRafal Ozieblo } 2583b83f1527SRafal Ozieblo break; 2584b83f1527SRafal Ozieblo } 2585b83f1527SRafal Ozieblo } 2586b83f1527SRafal Ozieblo 2587b83f1527SRafal Ozieblo static struct net_device_stats *macb_get_stats(struct net_device *dev) 2588b83f1527SRafal Ozieblo { 2589b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 2590b83f1527SRafal Ozieblo struct net_device_stats *nstat = &bp->dev->stats; 2591b83f1527SRafal Ozieblo struct macb_stats *hwstat = &bp->hw_stats.macb; 2592b83f1527SRafal Ozieblo 2593b83f1527SRafal Ozieblo if (macb_is_gem(bp)) 2594b83f1527SRafal Ozieblo return gem_get_stats(bp); 2595b83f1527SRafal Ozieblo 2596b83f1527SRafal Ozieblo /* read stats from hardware */ 2597b83f1527SRafal Ozieblo macb_update_stats(bp); 2598b83f1527SRafal Ozieblo 2599b83f1527SRafal Ozieblo /* Convert HW stats into netdevice stats */ 2600b83f1527SRafal Ozieblo nstat->rx_errors = (hwstat->rx_fcs_errors + 2601b83f1527SRafal Ozieblo hwstat->rx_align_errors + 2602b83f1527SRafal Ozieblo hwstat->rx_resource_errors + 2603b83f1527SRafal Ozieblo hwstat->rx_overruns + 2604b83f1527SRafal Ozieblo hwstat->rx_oversize_pkts + 2605b83f1527SRafal Ozieblo hwstat->rx_jabbers + 2606b83f1527SRafal Ozieblo hwstat->rx_undersize_pkts + 2607b83f1527SRafal Ozieblo hwstat->rx_length_mismatch); 2608b83f1527SRafal Ozieblo nstat->tx_errors = (hwstat->tx_late_cols + 2609b83f1527SRafal Ozieblo hwstat->tx_excessive_cols + 2610b83f1527SRafal Ozieblo hwstat->tx_underruns + 2611b83f1527SRafal Ozieblo hwstat->tx_carrier_errors + 2612b83f1527SRafal Ozieblo hwstat->sqe_test_errors); 2613b83f1527SRafal Ozieblo nstat->collisions = (hwstat->tx_single_cols + 2614b83f1527SRafal Ozieblo hwstat->tx_multiple_cols + 2615b83f1527SRafal Ozieblo hwstat->tx_excessive_cols); 2616b83f1527SRafal Ozieblo nstat->rx_length_errors = (hwstat->rx_oversize_pkts + 2617b83f1527SRafal Ozieblo hwstat->rx_jabbers + 2618b83f1527SRafal Ozieblo hwstat->rx_undersize_pkts + 2619b83f1527SRafal Ozieblo hwstat->rx_length_mismatch); 2620b83f1527SRafal Ozieblo nstat->rx_over_errors = hwstat->rx_resource_errors + 2621b83f1527SRafal Ozieblo hwstat->rx_overruns; 2622b83f1527SRafal Ozieblo nstat->rx_crc_errors = hwstat->rx_fcs_errors; 2623b83f1527SRafal Ozieblo nstat->rx_frame_errors = hwstat->rx_align_errors; 2624b83f1527SRafal Ozieblo nstat->rx_fifo_errors = hwstat->rx_overruns; 2625b83f1527SRafal Ozieblo /* XXX: What does "missed" mean? */ 2626b83f1527SRafal Ozieblo nstat->tx_aborted_errors = hwstat->tx_excessive_cols; 2627b83f1527SRafal Ozieblo nstat->tx_carrier_errors = hwstat->tx_carrier_errors; 2628b83f1527SRafal Ozieblo nstat->tx_fifo_errors = hwstat->tx_underruns; 2629b83f1527SRafal Ozieblo /* Don't know about heartbeat or window errors... */ 2630b83f1527SRafal Ozieblo 2631b83f1527SRafal Ozieblo return nstat; 2632b83f1527SRafal Ozieblo } 2633b83f1527SRafal Ozieblo 2634b83f1527SRafal Ozieblo static int macb_get_regs_len(struct net_device *netdev) 2635b83f1527SRafal Ozieblo { 2636b83f1527SRafal Ozieblo return MACB_GREGS_NBR * sizeof(u32); 2637b83f1527SRafal Ozieblo } 2638b83f1527SRafal Ozieblo 2639b83f1527SRafal Ozieblo static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs, 2640b83f1527SRafal Ozieblo void *p) 2641b83f1527SRafal Ozieblo { 2642b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 2643b83f1527SRafal Ozieblo unsigned int tail, head; 2644b83f1527SRafal Ozieblo u32 *regs_buff = p; 2645b83f1527SRafal Ozieblo 2646b83f1527SRafal Ozieblo regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) 2647b83f1527SRafal Ozieblo | MACB_GREGS_VERSION; 2648b83f1527SRafal Ozieblo 2649b83f1527SRafal Ozieblo tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail); 2650b83f1527SRafal Ozieblo head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head); 2651b83f1527SRafal Ozieblo 2652b83f1527SRafal Ozieblo regs_buff[0] = macb_readl(bp, NCR); 2653b83f1527SRafal Ozieblo regs_buff[1] = macb_or_gem_readl(bp, NCFGR); 2654b83f1527SRafal Ozieblo regs_buff[2] = macb_readl(bp, NSR); 2655b83f1527SRafal Ozieblo regs_buff[3] = macb_readl(bp, TSR); 2656b83f1527SRafal Ozieblo regs_buff[4] = macb_readl(bp, RBQP); 2657b83f1527SRafal Ozieblo regs_buff[5] = macb_readl(bp, TBQP); 2658b83f1527SRafal Ozieblo regs_buff[6] = macb_readl(bp, RSR); 2659b83f1527SRafal Ozieblo regs_buff[7] = macb_readl(bp, IMR); 2660b83f1527SRafal Ozieblo 2661b83f1527SRafal Ozieblo regs_buff[8] = tail; 2662b83f1527SRafal Ozieblo regs_buff[9] = head; 2663b83f1527SRafal Ozieblo regs_buff[10] = macb_tx_dma(&bp->queues[0], tail); 2664b83f1527SRafal Ozieblo regs_buff[11] = macb_tx_dma(&bp->queues[0], head); 2665b83f1527SRafal Ozieblo 2666b83f1527SRafal Ozieblo if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) 2667b83f1527SRafal Ozieblo regs_buff[12] = macb_or_gem_readl(bp, USRIO); 2668b83f1527SRafal Ozieblo if (macb_is_gem(bp)) 2669b83f1527SRafal Ozieblo regs_buff[13] = gem_readl(bp, DMACFG); 2670b83f1527SRafal Ozieblo } 2671b83f1527SRafal Ozieblo 2672b83f1527SRafal Ozieblo static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2673b83f1527SRafal Ozieblo { 2674b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev); 2675b83f1527SRafal Ozieblo 2676b83f1527SRafal Ozieblo wol->supported = 0; 2677b83f1527SRafal Ozieblo wol->wolopts = 0; 2678b83f1527SRafal Ozieblo 2679b83f1527SRafal Ozieblo if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) { 2680b83f1527SRafal Ozieblo wol->supported = WAKE_MAGIC; 2681b83f1527SRafal Ozieblo 2682b83f1527SRafal Ozieblo if (bp->wol & MACB_WOL_ENABLED) 2683b83f1527SRafal Ozieblo wol->wolopts |= WAKE_MAGIC; 2684b83f1527SRafal Ozieblo } 2685b83f1527SRafal Ozieblo } 2686b83f1527SRafal Ozieblo 2687b83f1527SRafal Ozieblo static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2688b83f1527SRafal Ozieblo { 2689b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev); 2690b83f1527SRafal Ozieblo 2691b83f1527SRafal Ozieblo if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) || 2692b83f1527SRafal Ozieblo (wol->wolopts & ~WAKE_MAGIC)) 2693b83f1527SRafal Ozieblo return -EOPNOTSUPP; 2694b83f1527SRafal Ozieblo 2695b83f1527SRafal Ozieblo if (wol->wolopts & WAKE_MAGIC) 2696b83f1527SRafal Ozieblo bp->wol |= MACB_WOL_ENABLED; 2697b83f1527SRafal Ozieblo else 2698b83f1527SRafal Ozieblo bp->wol &= ~MACB_WOL_ENABLED; 2699b83f1527SRafal Ozieblo 2700b83f1527SRafal Ozieblo device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED); 2701b83f1527SRafal Ozieblo 2702b83f1527SRafal Ozieblo return 0; 2703b83f1527SRafal Ozieblo } 2704b83f1527SRafal Ozieblo 2705b83f1527SRafal Ozieblo static void macb_get_ringparam(struct net_device *netdev, 2706b83f1527SRafal Ozieblo struct ethtool_ringparam *ring) 2707b83f1527SRafal Ozieblo { 2708b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev); 2709b83f1527SRafal Ozieblo 2710b83f1527SRafal Ozieblo ring->rx_max_pending = MAX_RX_RING_SIZE; 2711b83f1527SRafal Ozieblo ring->tx_max_pending = MAX_TX_RING_SIZE; 2712b83f1527SRafal Ozieblo 2713b83f1527SRafal Ozieblo ring->rx_pending = bp->rx_ring_size; 2714b83f1527SRafal Ozieblo ring->tx_pending = bp->tx_ring_size; 2715b83f1527SRafal Ozieblo } 2716b83f1527SRafal Ozieblo 2717b83f1527SRafal Ozieblo static int macb_set_ringparam(struct net_device *netdev, 2718b83f1527SRafal Ozieblo struct ethtool_ringparam *ring) 2719b83f1527SRafal Ozieblo { 2720b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev); 2721b83f1527SRafal Ozieblo u32 new_rx_size, new_tx_size; 2722b83f1527SRafal Ozieblo unsigned int reset = 0; 2723b83f1527SRafal Ozieblo 2724b83f1527SRafal Ozieblo if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 2725b83f1527SRafal Ozieblo return -EINVAL; 2726b83f1527SRafal Ozieblo 2727b83f1527SRafal Ozieblo new_rx_size = clamp_t(u32, ring->rx_pending, 2728b83f1527SRafal Ozieblo MIN_RX_RING_SIZE, MAX_RX_RING_SIZE); 2729b83f1527SRafal Ozieblo new_rx_size = roundup_pow_of_two(new_rx_size); 2730b83f1527SRafal Ozieblo 2731b83f1527SRafal Ozieblo new_tx_size = clamp_t(u32, ring->tx_pending, 2732b83f1527SRafal Ozieblo MIN_TX_RING_SIZE, MAX_TX_RING_SIZE); 2733b83f1527SRafal Ozieblo new_tx_size = roundup_pow_of_two(new_tx_size); 2734b83f1527SRafal Ozieblo 2735b83f1527SRafal Ozieblo if ((new_tx_size == bp->tx_ring_size) && 2736b83f1527SRafal Ozieblo (new_rx_size == bp->rx_ring_size)) { 2737b83f1527SRafal Ozieblo /* nothing to do */ 2738b83f1527SRafal Ozieblo return 0; 2739b83f1527SRafal Ozieblo } 2740b83f1527SRafal Ozieblo 2741b83f1527SRafal Ozieblo if (netif_running(bp->dev)) { 2742b83f1527SRafal Ozieblo reset = 1; 2743b83f1527SRafal Ozieblo macb_close(bp->dev); 2744b83f1527SRafal Ozieblo } 2745b83f1527SRafal Ozieblo 2746b83f1527SRafal Ozieblo bp->rx_ring_size = new_rx_size; 2747b83f1527SRafal Ozieblo bp->tx_ring_size = new_tx_size; 2748b83f1527SRafal Ozieblo 2749b83f1527SRafal Ozieblo if (reset) 2750b83f1527SRafal Ozieblo macb_open(bp->dev); 2751b83f1527SRafal Ozieblo 2752b83f1527SRafal Ozieblo return 0; 2753b83f1527SRafal Ozieblo } 2754b83f1527SRafal Ozieblo 2755ab91f0a9SRafal Ozieblo #ifdef CONFIG_MACB_USE_HWSTAMP 2756ab91f0a9SRafal Ozieblo static unsigned int gem_get_tsu_rate(struct macb *bp) 2757ab91f0a9SRafal Ozieblo { 2758ab91f0a9SRafal Ozieblo struct clk *tsu_clk; 2759ab91f0a9SRafal Ozieblo unsigned int tsu_rate; 2760ab91f0a9SRafal Ozieblo 2761ab91f0a9SRafal Ozieblo tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk"); 2762ab91f0a9SRafal Ozieblo if (!IS_ERR(tsu_clk)) 2763ab91f0a9SRafal Ozieblo tsu_rate = clk_get_rate(tsu_clk); 2764ab91f0a9SRafal Ozieblo /* try pclk instead */ 2765ab91f0a9SRafal Ozieblo else if (!IS_ERR(bp->pclk)) { 2766ab91f0a9SRafal Ozieblo tsu_clk = bp->pclk; 2767ab91f0a9SRafal Ozieblo tsu_rate = clk_get_rate(tsu_clk); 2768ab91f0a9SRafal Ozieblo } else 2769ab91f0a9SRafal Ozieblo return -ENOTSUPP; 2770ab91f0a9SRafal Ozieblo return tsu_rate; 2771ab91f0a9SRafal Ozieblo } 2772ab91f0a9SRafal Ozieblo 2773ab91f0a9SRafal Ozieblo static s32 gem_get_ptp_max_adj(void) 2774ab91f0a9SRafal Ozieblo { 2775ab91f0a9SRafal Ozieblo return 64000000; 2776ab91f0a9SRafal Ozieblo } 2777ab91f0a9SRafal Ozieblo 2778ab91f0a9SRafal Ozieblo static int gem_get_ts_info(struct net_device *dev, 2779ab91f0a9SRafal Ozieblo struct ethtool_ts_info *info) 2780ab91f0a9SRafal Ozieblo { 2781ab91f0a9SRafal Ozieblo struct macb *bp = netdev_priv(dev); 2782ab91f0a9SRafal Ozieblo 2783ab91f0a9SRafal Ozieblo if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) { 2784ab91f0a9SRafal Ozieblo ethtool_op_get_ts_info(dev, info); 2785ab91f0a9SRafal Ozieblo return 0; 2786ab91f0a9SRafal Ozieblo } 2787ab91f0a9SRafal Ozieblo 2788ab91f0a9SRafal Ozieblo info->so_timestamping = 2789ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_TX_SOFTWARE | 2790ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_RX_SOFTWARE | 2791ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_SOFTWARE | 2792ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_TX_HARDWARE | 2793ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_RX_HARDWARE | 2794ab91f0a9SRafal Ozieblo SOF_TIMESTAMPING_RAW_HARDWARE; 2795ab91f0a9SRafal Ozieblo info->tx_types = 2796ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_TX_ONESTEP_SYNC) | 2797ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_TX_OFF) | 2798ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_TX_ON); 2799ab91f0a9SRafal Ozieblo info->rx_filters = 2800ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_FILTER_NONE) | 2801ab91f0a9SRafal Ozieblo (1 << HWTSTAMP_FILTER_ALL); 2802ab91f0a9SRafal Ozieblo 2803ab91f0a9SRafal Ozieblo info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1; 2804ab91f0a9SRafal Ozieblo 2805ab91f0a9SRafal Ozieblo return 0; 2806ab91f0a9SRafal Ozieblo } 2807ab91f0a9SRafal Ozieblo 2808ab91f0a9SRafal Ozieblo static struct macb_ptp_info gem_ptp_info = { 2809ab91f0a9SRafal Ozieblo .ptp_init = gem_ptp_init, 2810ab91f0a9SRafal Ozieblo .ptp_remove = gem_ptp_remove, 2811ab91f0a9SRafal Ozieblo .get_ptp_max_adj = gem_get_ptp_max_adj, 2812ab91f0a9SRafal Ozieblo .get_tsu_rate = gem_get_tsu_rate, 2813ab91f0a9SRafal Ozieblo .get_ts_info = gem_get_ts_info, 2814ab91f0a9SRafal Ozieblo .get_hwtst = gem_get_hwtst, 2815ab91f0a9SRafal Ozieblo .set_hwtst = gem_set_hwtst, 2816ab91f0a9SRafal Ozieblo }; 2817ab91f0a9SRafal Ozieblo #endif 2818ab91f0a9SRafal Ozieblo 2819b83f1527SRafal Ozieblo static int macb_get_ts_info(struct net_device *netdev, 2820b83f1527SRafal Ozieblo struct ethtool_ts_info *info) 2821b83f1527SRafal Ozieblo { 2822b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev); 2823b83f1527SRafal Ozieblo 2824b83f1527SRafal Ozieblo if (bp->ptp_info) 2825b83f1527SRafal Ozieblo return bp->ptp_info->get_ts_info(netdev, info); 2826b83f1527SRafal Ozieblo 2827b83f1527SRafal Ozieblo return ethtool_op_get_ts_info(netdev, info); 2828b83f1527SRafal Ozieblo } 2829b83f1527SRafal Ozieblo 2830ae8223deSRafal Ozieblo static void gem_enable_flow_filters(struct macb *bp, bool enable) 2831ae8223deSRafal Ozieblo { 2832ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item; 2833ae8223deSRafal Ozieblo u32 t2_scr; 2834ae8223deSRafal Ozieblo int num_t2_scr; 2835ae8223deSRafal Ozieblo 2836ae8223deSRafal Ozieblo num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8)); 2837ae8223deSRafal Ozieblo 2838ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) { 2839ae8223deSRafal Ozieblo struct ethtool_rx_flow_spec *fs = &item->fs; 2840ae8223deSRafal Ozieblo struct ethtool_tcpip4_spec *tp4sp_m; 2841ae8223deSRafal Ozieblo 2842ae8223deSRafal Ozieblo if (fs->location >= num_t2_scr) 2843ae8223deSRafal Ozieblo continue; 2844ae8223deSRafal Ozieblo 2845ae8223deSRafal Ozieblo t2_scr = gem_readl_n(bp, SCRT2, fs->location); 2846ae8223deSRafal Ozieblo 2847ae8223deSRafal Ozieblo /* enable/disable screener regs for the flow entry */ 2848ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr); 2849ae8223deSRafal Ozieblo 2850ae8223deSRafal Ozieblo /* only enable fields with no masking */ 2851ae8223deSRafal Ozieblo tp4sp_m = &(fs->m_u.tcp_ip4_spec); 2852ae8223deSRafal Ozieblo 2853ae8223deSRafal Ozieblo if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF)) 2854ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr); 2855ae8223deSRafal Ozieblo else 2856ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr); 2857ae8223deSRafal Ozieblo 2858ae8223deSRafal Ozieblo if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF)) 2859ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr); 2860ae8223deSRafal Ozieblo else 2861ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr); 2862ae8223deSRafal Ozieblo 2863ae8223deSRafal Ozieblo if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF))) 2864ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr); 2865ae8223deSRafal Ozieblo else 2866ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr); 2867ae8223deSRafal Ozieblo 2868ae8223deSRafal Ozieblo gem_writel_n(bp, SCRT2, fs->location, t2_scr); 2869ae8223deSRafal Ozieblo } 2870ae8223deSRafal Ozieblo } 2871ae8223deSRafal Ozieblo 2872ae8223deSRafal Ozieblo static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs) 2873ae8223deSRafal Ozieblo { 2874ae8223deSRafal Ozieblo struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m; 2875ae8223deSRafal Ozieblo uint16_t index = fs->location; 2876ae8223deSRafal Ozieblo u32 w0, w1, t2_scr; 2877ae8223deSRafal Ozieblo bool cmp_a = false; 2878ae8223deSRafal Ozieblo bool cmp_b = false; 2879ae8223deSRafal Ozieblo bool cmp_c = false; 2880ae8223deSRafal Ozieblo 2881ae8223deSRafal Ozieblo tp4sp_v = &(fs->h_u.tcp_ip4_spec); 2882ae8223deSRafal Ozieblo tp4sp_m = &(fs->m_u.tcp_ip4_spec); 2883ae8223deSRafal Ozieblo 2884ae8223deSRafal Ozieblo /* ignore field if any masking set */ 2885ae8223deSRafal Ozieblo if (tp4sp_m->ip4src == 0xFFFFFFFF) { 2886ae8223deSRafal Ozieblo /* 1st compare reg - IP source address */ 2887ae8223deSRafal Ozieblo w0 = 0; 2888ae8223deSRafal Ozieblo w1 = 0; 2889ae8223deSRafal Ozieblo w0 = tp4sp_v->ip4src; 2890ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ 2891ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1); 2892ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1); 2893ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0); 2894ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1); 2895ae8223deSRafal Ozieblo cmp_a = true; 2896ae8223deSRafal Ozieblo } 2897ae8223deSRafal Ozieblo 2898ae8223deSRafal Ozieblo /* ignore field if any masking set */ 2899ae8223deSRafal Ozieblo if (tp4sp_m->ip4dst == 0xFFFFFFFF) { 2900ae8223deSRafal Ozieblo /* 2nd compare reg - IP destination address */ 2901ae8223deSRafal Ozieblo w0 = 0; 2902ae8223deSRafal Ozieblo w1 = 0; 2903ae8223deSRafal Ozieblo w0 = tp4sp_v->ip4dst; 2904ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ 2905ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1); 2906ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1); 2907ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0); 2908ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1); 2909ae8223deSRafal Ozieblo cmp_b = true; 2910ae8223deSRafal Ozieblo } 2911ae8223deSRafal Ozieblo 2912ae8223deSRafal Ozieblo /* ignore both port fields if masking set in both */ 2913ae8223deSRafal Ozieblo if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) { 2914ae8223deSRafal Ozieblo /* 3rd compare reg - source port, destination port */ 2915ae8223deSRafal Ozieblo w0 = 0; 2916ae8223deSRafal Ozieblo w1 = 0; 2917ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1); 2918ae8223deSRafal Ozieblo if (tp4sp_m->psrc == tp4sp_m->pdst) { 2919ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0); 2920ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); 2921ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ 2922ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1); 2923ae8223deSRafal Ozieblo } else { 2924ae8223deSRafal Ozieblo /* only one port definition */ 2925ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */ 2926ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2MASK, 0xFFFF, w0); 2927ae8223deSRafal Ozieblo if (tp4sp_m->psrc == 0xFFFF) { /* src port */ 2928ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0); 2929ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1); 2930ae8223deSRafal Ozieblo } else { /* dst port */ 2931ae8223deSRafal Ozieblo w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); 2932ae8223deSRafal Ozieblo w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1); 2933ae8223deSRafal Ozieblo } 2934ae8223deSRafal Ozieblo } 2935ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0); 2936ae8223deSRafal Ozieblo gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1); 2937ae8223deSRafal Ozieblo cmp_c = true; 2938ae8223deSRafal Ozieblo } 2939ae8223deSRafal Ozieblo 2940ae8223deSRafal Ozieblo t2_scr = 0; 2941ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr); 2942ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr); 2943ae8223deSRafal Ozieblo if (cmp_a) 2944ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr); 2945ae8223deSRafal Ozieblo if (cmp_b) 2946ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr); 2947ae8223deSRafal Ozieblo if (cmp_c) 2948ae8223deSRafal Ozieblo t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr); 2949ae8223deSRafal Ozieblo gem_writel_n(bp, SCRT2, index, t2_scr); 2950ae8223deSRafal Ozieblo } 2951ae8223deSRafal Ozieblo 2952ae8223deSRafal Ozieblo static int gem_add_flow_filter(struct net_device *netdev, 2953ae8223deSRafal Ozieblo struct ethtool_rxnfc *cmd) 2954ae8223deSRafal Ozieblo { 2955ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev); 2956ae8223deSRafal Ozieblo struct ethtool_rx_flow_spec *fs = &cmd->fs; 2957ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item, *newfs; 29587038cdb7SJulia Cartwright unsigned long flags; 2959ae8223deSRafal Ozieblo int ret = -EINVAL; 2960ae8223deSRafal Ozieblo bool added = false; 2961ae8223deSRafal Ozieblo 2962cc1674eeSJulia Cartwright newfs = kmalloc(sizeof(*newfs), GFP_KERNEL); 2963ae8223deSRafal Ozieblo if (newfs == NULL) 2964ae8223deSRafal Ozieblo return -ENOMEM; 2965ae8223deSRafal Ozieblo memcpy(&newfs->fs, fs, sizeof(newfs->fs)); 2966ae8223deSRafal Ozieblo 2967ae8223deSRafal Ozieblo netdev_dbg(netdev, 2968ae8223deSRafal Ozieblo "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n", 2969ae8223deSRafal Ozieblo fs->flow_type, (int)fs->ring_cookie, fs->location, 2970ae8223deSRafal Ozieblo htonl(fs->h_u.tcp_ip4_spec.ip4src), 2971ae8223deSRafal Ozieblo htonl(fs->h_u.tcp_ip4_spec.ip4dst), 2972ae8223deSRafal Ozieblo htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst)); 2973ae8223deSRafal Ozieblo 29747038cdb7SJulia Cartwright spin_lock_irqsave(&bp->rx_fs_lock, flags); 29757038cdb7SJulia Cartwright 2976ae8223deSRafal Ozieblo /* find correct place to add in list */ 2977ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) { 2978ae8223deSRafal Ozieblo if (item->fs.location > newfs->fs.location) { 2979ae8223deSRafal Ozieblo list_add_tail(&newfs->list, &item->list); 2980ae8223deSRafal Ozieblo added = true; 2981ae8223deSRafal Ozieblo break; 2982ae8223deSRafal Ozieblo } else if (item->fs.location == fs->location) { 2983ae8223deSRafal Ozieblo netdev_err(netdev, "Rule not added: location %d not free!\n", 2984ae8223deSRafal Ozieblo fs->location); 2985ae8223deSRafal Ozieblo ret = -EBUSY; 2986ae8223deSRafal Ozieblo goto err; 2987ae8223deSRafal Ozieblo } 2988ae8223deSRafal Ozieblo } 2989ae8223deSRafal Ozieblo if (!added) 2990ae8223deSRafal Ozieblo list_add_tail(&newfs->list, &bp->rx_fs_list.list); 2991ae8223deSRafal Ozieblo 2992ae8223deSRafal Ozieblo gem_prog_cmp_regs(bp, fs); 2993ae8223deSRafal Ozieblo bp->rx_fs_list.count++; 2994ae8223deSRafal Ozieblo /* enable filtering if NTUPLE on */ 2995ae8223deSRafal Ozieblo if (netdev->features & NETIF_F_NTUPLE) 2996ae8223deSRafal Ozieblo gem_enable_flow_filters(bp, 1); 2997ae8223deSRafal Ozieblo 29987038cdb7SJulia Cartwright spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 2999ae8223deSRafal Ozieblo return 0; 3000ae8223deSRafal Ozieblo 3001ae8223deSRafal Ozieblo err: 30027038cdb7SJulia Cartwright spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 3003ae8223deSRafal Ozieblo kfree(newfs); 3004ae8223deSRafal Ozieblo return ret; 3005ae8223deSRafal Ozieblo } 3006ae8223deSRafal Ozieblo 3007ae8223deSRafal Ozieblo static int gem_del_flow_filter(struct net_device *netdev, 3008ae8223deSRafal Ozieblo struct ethtool_rxnfc *cmd) 3009ae8223deSRafal Ozieblo { 3010ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev); 3011ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item; 3012ae8223deSRafal Ozieblo struct ethtool_rx_flow_spec *fs; 30137038cdb7SJulia Cartwright unsigned long flags; 30147038cdb7SJulia Cartwright 30157038cdb7SJulia Cartwright spin_lock_irqsave(&bp->rx_fs_lock, flags); 3016ae8223deSRafal Ozieblo 3017ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) { 3018ae8223deSRafal Ozieblo if (item->fs.location == cmd->fs.location) { 3019ae8223deSRafal Ozieblo /* disable screener regs for the flow entry */ 3020ae8223deSRafal Ozieblo fs = &(item->fs); 3021ae8223deSRafal Ozieblo netdev_dbg(netdev, 3022ae8223deSRafal Ozieblo "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n", 3023ae8223deSRafal Ozieblo fs->flow_type, (int)fs->ring_cookie, fs->location, 3024ae8223deSRafal Ozieblo htonl(fs->h_u.tcp_ip4_spec.ip4src), 3025ae8223deSRafal Ozieblo htonl(fs->h_u.tcp_ip4_spec.ip4dst), 3026ae8223deSRafal Ozieblo htons(fs->h_u.tcp_ip4_spec.psrc), 3027ae8223deSRafal Ozieblo htons(fs->h_u.tcp_ip4_spec.pdst)); 3028ae8223deSRafal Ozieblo 3029ae8223deSRafal Ozieblo gem_writel_n(bp, SCRT2, fs->location, 0); 3030ae8223deSRafal Ozieblo 3031ae8223deSRafal Ozieblo list_del(&item->list); 3032ae8223deSRafal Ozieblo bp->rx_fs_list.count--; 30337038cdb7SJulia Cartwright spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 30347038cdb7SJulia Cartwright kfree(item); 3035ae8223deSRafal Ozieblo return 0; 3036ae8223deSRafal Ozieblo } 3037ae8223deSRafal Ozieblo } 3038ae8223deSRafal Ozieblo 30397038cdb7SJulia Cartwright spin_unlock_irqrestore(&bp->rx_fs_lock, flags); 3040ae8223deSRafal Ozieblo return -EINVAL; 3041ae8223deSRafal Ozieblo } 3042ae8223deSRafal Ozieblo 3043ae8223deSRafal Ozieblo static int gem_get_flow_entry(struct net_device *netdev, 3044ae8223deSRafal Ozieblo struct ethtool_rxnfc *cmd) 3045ae8223deSRafal Ozieblo { 3046ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev); 3047ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item; 3048ae8223deSRafal Ozieblo 3049ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) { 3050ae8223deSRafal Ozieblo if (item->fs.location == cmd->fs.location) { 3051ae8223deSRafal Ozieblo memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs)); 3052ae8223deSRafal Ozieblo return 0; 3053ae8223deSRafal Ozieblo } 3054ae8223deSRafal Ozieblo } 3055ae8223deSRafal Ozieblo return -EINVAL; 3056ae8223deSRafal Ozieblo } 3057ae8223deSRafal Ozieblo 3058ae8223deSRafal Ozieblo static int gem_get_all_flow_entries(struct net_device *netdev, 3059ae8223deSRafal Ozieblo struct ethtool_rxnfc *cmd, u32 *rule_locs) 3060ae8223deSRafal Ozieblo { 3061ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev); 3062ae8223deSRafal Ozieblo struct ethtool_rx_fs_item *item; 3063ae8223deSRafal Ozieblo uint32_t cnt = 0; 3064ae8223deSRafal Ozieblo 3065ae8223deSRafal Ozieblo list_for_each_entry(item, &bp->rx_fs_list.list, list) { 3066ae8223deSRafal Ozieblo if (cnt == cmd->rule_cnt) 3067ae8223deSRafal Ozieblo return -EMSGSIZE; 3068ae8223deSRafal Ozieblo rule_locs[cnt] = item->fs.location; 3069ae8223deSRafal Ozieblo cnt++; 3070ae8223deSRafal Ozieblo } 3071ae8223deSRafal Ozieblo cmd->data = bp->max_tuples; 3072ae8223deSRafal Ozieblo cmd->rule_cnt = cnt; 3073ae8223deSRafal Ozieblo 3074ae8223deSRafal Ozieblo return 0; 3075ae8223deSRafal Ozieblo } 3076ae8223deSRafal Ozieblo 3077ae8223deSRafal Ozieblo static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd, 3078ae8223deSRafal Ozieblo u32 *rule_locs) 3079ae8223deSRafal Ozieblo { 3080ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev); 3081ae8223deSRafal Ozieblo int ret = 0; 3082ae8223deSRafal Ozieblo 3083ae8223deSRafal Ozieblo switch (cmd->cmd) { 3084ae8223deSRafal Ozieblo case ETHTOOL_GRXRINGS: 3085ae8223deSRafal Ozieblo cmd->data = bp->num_queues; 3086ae8223deSRafal Ozieblo break; 3087ae8223deSRafal Ozieblo case ETHTOOL_GRXCLSRLCNT: 3088ae8223deSRafal Ozieblo cmd->rule_cnt = bp->rx_fs_list.count; 3089ae8223deSRafal Ozieblo break; 3090ae8223deSRafal Ozieblo case ETHTOOL_GRXCLSRULE: 3091ae8223deSRafal Ozieblo ret = gem_get_flow_entry(netdev, cmd); 3092ae8223deSRafal Ozieblo break; 3093ae8223deSRafal Ozieblo case ETHTOOL_GRXCLSRLALL: 3094ae8223deSRafal Ozieblo ret = gem_get_all_flow_entries(netdev, cmd, rule_locs); 3095ae8223deSRafal Ozieblo break; 3096ae8223deSRafal Ozieblo default: 3097ae8223deSRafal Ozieblo netdev_err(netdev, 3098ae8223deSRafal Ozieblo "Command parameter %d is not supported\n", cmd->cmd); 3099ae8223deSRafal Ozieblo ret = -EOPNOTSUPP; 3100ae8223deSRafal Ozieblo } 3101ae8223deSRafal Ozieblo 3102ae8223deSRafal Ozieblo return ret; 3103ae8223deSRafal Ozieblo } 3104ae8223deSRafal Ozieblo 3105ae8223deSRafal Ozieblo static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) 3106ae8223deSRafal Ozieblo { 3107ae8223deSRafal Ozieblo struct macb *bp = netdev_priv(netdev); 3108ae8223deSRafal Ozieblo int ret; 3109ae8223deSRafal Ozieblo 3110ae8223deSRafal Ozieblo switch (cmd->cmd) { 3111ae8223deSRafal Ozieblo case ETHTOOL_SRXCLSRLINS: 3112ae8223deSRafal Ozieblo if ((cmd->fs.location >= bp->max_tuples) 3113ae8223deSRafal Ozieblo || (cmd->fs.ring_cookie >= bp->num_queues)) { 3114ae8223deSRafal Ozieblo ret = -EINVAL; 3115ae8223deSRafal Ozieblo break; 3116ae8223deSRafal Ozieblo } 3117ae8223deSRafal Ozieblo ret = gem_add_flow_filter(netdev, cmd); 3118ae8223deSRafal Ozieblo break; 3119ae8223deSRafal Ozieblo case ETHTOOL_SRXCLSRLDEL: 3120ae8223deSRafal Ozieblo ret = gem_del_flow_filter(netdev, cmd); 3121ae8223deSRafal Ozieblo break; 3122ae8223deSRafal Ozieblo default: 3123ae8223deSRafal Ozieblo netdev_err(netdev, 3124ae8223deSRafal Ozieblo "Command parameter %d is not supported\n", cmd->cmd); 3125ae8223deSRafal Ozieblo ret = -EOPNOTSUPP; 3126ae8223deSRafal Ozieblo } 3127ae8223deSRafal Ozieblo 3128ae8223deSRafal Ozieblo return ret; 3129ae8223deSRafal Ozieblo } 3130ae8223deSRafal Ozieblo 3131b83f1527SRafal Ozieblo static const struct ethtool_ops macb_ethtool_ops = { 3132b83f1527SRafal Ozieblo .get_regs_len = macb_get_regs_len, 3133b83f1527SRafal Ozieblo .get_regs = macb_get_regs, 3134b83f1527SRafal Ozieblo .get_link = ethtool_op_get_link, 3135b83f1527SRafal Ozieblo .get_ts_info = ethtool_op_get_ts_info, 3136b83f1527SRafal Ozieblo .get_wol = macb_get_wol, 3137b83f1527SRafal Ozieblo .set_wol = macb_set_wol, 3138b83f1527SRafal Ozieblo .get_link_ksettings = phy_ethtool_get_link_ksettings, 3139b83f1527SRafal Ozieblo .set_link_ksettings = phy_ethtool_set_link_ksettings, 3140b83f1527SRafal Ozieblo .get_ringparam = macb_get_ringparam, 3141b83f1527SRafal Ozieblo .set_ringparam = macb_set_ringparam, 3142b83f1527SRafal Ozieblo }; 3143b83f1527SRafal Ozieblo 3144b83f1527SRafal Ozieblo static const struct ethtool_ops gem_ethtool_ops = { 3145b83f1527SRafal Ozieblo .get_regs_len = macb_get_regs_len, 3146b83f1527SRafal Ozieblo .get_regs = macb_get_regs, 3147b83f1527SRafal Ozieblo .get_link = ethtool_op_get_link, 3148b83f1527SRafal Ozieblo .get_ts_info = macb_get_ts_info, 3149b83f1527SRafal Ozieblo .get_ethtool_stats = gem_get_ethtool_stats, 3150b83f1527SRafal Ozieblo .get_strings = gem_get_ethtool_strings, 3151b83f1527SRafal Ozieblo .get_sset_count = gem_get_sset_count, 3152b83f1527SRafal Ozieblo .get_link_ksettings = phy_ethtool_get_link_ksettings, 3153b83f1527SRafal Ozieblo .set_link_ksettings = phy_ethtool_set_link_ksettings, 3154b83f1527SRafal Ozieblo .get_ringparam = macb_get_ringparam, 3155b83f1527SRafal Ozieblo .set_ringparam = macb_set_ringparam, 3156ae8223deSRafal Ozieblo .get_rxnfc = gem_get_rxnfc, 3157ae8223deSRafal Ozieblo .set_rxnfc = gem_set_rxnfc, 3158b83f1527SRafal Ozieblo }; 3159b83f1527SRafal Ozieblo 3160b83f1527SRafal Ozieblo static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3161b83f1527SRafal Ozieblo { 3162b83f1527SRafal Ozieblo struct phy_device *phydev = dev->phydev; 3163b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 3164b83f1527SRafal Ozieblo 3165b83f1527SRafal Ozieblo if (!netif_running(dev)) 3166b83f1527SRafal Ozieblo return -EINVAL; 3167b83f1527SRafal Ozieblo 3168b83f1527SRafal Ozieblo if (!phydev) 3169b83f1527SRafal Ozieblo return -ENODEV; 3170b83f1527SRafal Ozieblo 3171b83f1527SRafal Ozieblo if (!bp->ptp_info) 3172b83f1527SRafal Ozieblo return phy_mii_ioctl(phydev, rq, cmd); 3173b83f1527SRafal Ozieblo 3174b83f1527SRafal Ozieblo switch (cmd) { 3175b83f1527SRafal Ozieblo case SIOCSHWTSTAMP: 3176b83f1527SRafal Ozieblo return bp->ptp_info->set_hwtst(dev, rq, cmd); 3177b83f1527SRafal Ozieblo case SIOCGHWTSTAMP: 3178b83f1527SRafal Ozieblo return bp->ptp_info->get_hwtst(dev, rq); 3179b83f1527SRafal Ozieblo default: 3180b83f1527SRafal Ozieblo return phy_mii_ioctl(phydev, rq, cmd); 3181b83f1527SRafal Ozieblo } 3182b83f1527SRafal Ozieblo } 3183b83f1527SRafal Ozieblo 3184b83f1527SRafal Ozieblo static int macb_set_features(struct net_device *netdev, 3185b83f1527SRafal Ozieblo netdev_features_t features) 3186b83f1527SRafal Ozieblo { 3187b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev); 3188b83f1527SRafal Ozieblo netdev_features_t changed = features ^ netdev->features; 3189b83f1527SRafal Ozieblo 3190b83f1527SRafal Ozieblo /* TX checksum offload */ 3191b83f1527SRafal Ozieblo if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) { 3192b83f1527SRafal Ozieblo u32 dmacfg; 3193b83f1527SRafal Ozieblo 3194b83f1527SRafal Ozieblo dmacfg = gem_readl(bp, DMACFG); 3195b83f1527SRafal Ozieblo if (features & NETIF_F_HW_CSUM) 3196b83f1527SRafal Ozieblo dmacfg |= GEM_BIT(TXCOEN); 3197b83f1527SRafal Ozieblo else 3198b83f1527SRafal Ozieblo dmacfg &= ~GEM_BIT(TXCOEN); 3199b83f1527SRafal Ozieblo gem_writel(bp, DMACFG, dmacfg); 3200b83f1527SRafal Ozieblo } 3201b83f1527SRafal Ozieblo 3202b83f1527SRafal Ozieblo /* RX checksum offload */ 3203b83f1527SRafal Ozieblo if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) { 3204b83f1527SRafal Ozieblo u32 netcfg; 3205b83f1527SRafal Ozieblo 3206b83f1527SRafal Ozieblo netcfg = gem_readl(bp, NCFGR); 3207b83f1527SRafal Ozieblo if (features & NETIF_F_RXCSUM && 3208b83f1527SRafal Ozieblo !(netdev->flags & IFF_PROMISC)) 3209b83f1527SRafal Ozieblo netcfg |= GEM_BIT(RXCOEN); 3210b83f1527SRafal Ozieblo else 3211b83f1527SRafal Ozieblo netcfg &= ~GEM_BIT(RXCOEN); 3212b83f1527SRafal Ozieblo gem_writel(bp, NCFGR, netcfg); 3213b83f1527SRafal Ozieblo } 3214b83f1527SRafal Ozieblo 3215ae8223deSRafal Ozieblo /* RX Flow Filters */ 3216ae8223deSRafal Ozieblo if ((changed & NETIF_F_NTUPLE) && macb_is_gem(bp)) { 3217ae8223deSRafal Ozieblo bool turn_on = features & NETIF_F_NTUPLE; 3218ae8223deSRafal Ozieblo 3219ae8223deSRafal Ozieblo gem_enable_flow_filters(bp, turn_on); 3220ae8223deSRafal Ozieblo } 3221b83f1527SRafal Ozieblo return 0; 3222b83f1527SRafal Ozieblo } 3223b83f1527SRafal Ozieblo 3224b83f1527SRafal Ozieblo static const struct net_device_ops macb_netdev_ops = { 3225b83f1527SRafal Ozieblo .ndo_open = macb_open, 3226b83f1527SRafal Ozieblo .ndo_stop = macb_close, 3227b83f1527SRafal Ozieblo .ndo_start_xmit = macb_start_xmit, 3228b83f1527SRafal Ozieblo .ndo_set_rx_mode = macb_set_rx_mode, 3229b83f1527SRafal Ozieblo .ndo_get_stats = macb_get_stats, 3230b83f1527SRafal Ozieblo .ndo_do_ioctl = macb_ioctl, 3231b83f1527SRafal Ozieblo .ndo_validate_addr = eth_validate_addr, 3232b83f1527SRafal Ozieblo .ndo_change_mtu = macb_change_mtu, 3233b83f1527SRafal Ozieblo .ndo_set_mac_address = eth_mac_addr, 3234b83f1527SRafal Ozieblo #ifdef CONFIG_NET_POLL_CONTROLLER 3235b83f1527SRafal Ozieblo .ndo_poll_controller = macb_poll_controller, 3236b83f1527SRafal Ozieblo #endif 3237b83f1527SRafal Ozieblo .ndo_set_features = macb_set_features, 3238b83f1527SRafal Ozieblo .ndo_features_check = macb_features_check, 3239b83f1527SRafal Ozieblo }; 3240b83f1527SRafal Ozieblo 3241b83f1527SRafal Ozieblo /* Configure peripheral capabilities according to device tree 3242b83f1527SRafal Ozieblo * and integration options used 3243b83f1527SRafal Ozieblo */ 3244b83f1527SRafal Ozieblo static void macb_configure_caps(struct macb *bp, 3245b83f1527SRafal Ozieblo const struct macb_config *dt_conf) 3246b83f1527SRafal Ozieblo { 3247b83f1527SRafal Ozieblo u32 dcfg; 3248b83f1527SRafal Ozieblo 3249b83f1527SRafal Ozieblo if (dt_conf) 3250b83f1527SRafal Ozieblo bp->caps = dt_conf->caps; 3251b83f1527SRafal Ozieblo 3252b83f1527SRafal Ozieblo if (hw_is_gem(bp->regs, bp->native_io)) { 3253b83f1527SRafal Ozieblo bp->caps |= MACB_CAPS_MACB_IS_GEM; 3254b83f1527SRafal Ozieblo 3255b83f1527SRafal Ozieblo dcfg = gem_readl(bp, DCFG1); 3256b83f1527SRafal Ozieblo if (GEM_BFEXT(IRQCOR, dcfg) == 0) 3257b83f1527SRafal Ozieblo bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; 3258b83f1527SRafal Ozieblo dcfg = gem_readl(bp, DCFG2); 3259b83f1527SRafal Ozieblo if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) 3260b83f1527SRafal Ozieblo bp->caps |= MACB_CAPS_FIFO_MODE; 3261ab91f0a9SRafal Ozieblo #ifdef CONFIG_MACB_USE_HWSTAMP 3262ab91f0a9SRafal Ozieblo if (gem_has_ptp(bp)) { 3263b83f1527SRafal Ozieblo if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5))) 3264b83f1527SRafal Ozieblo pr_err("GEM doesn't support hardware ptp.\n"); 3265ab91f0a9SRafal Ozieblo else { 3266b83f1527SRafal Ozieblo bp->hw_dma_cap |= HW_DMA_CAP_PTP; 3267ab91f0a9SRafal Ozieblo bp->ptp_info = &gem_ptp_info; 3268b83f1527SRafal Ozieblo } 3269b83f1527SRafal Ozieblo } 3270ab91f0a9SRafal Ozieblo #endif 3271ab91f0a9SRafal Ozieblo } 3272b83f1527SRafal Ozieblo 3273b83f1527SRafal Ozieblo dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps); 3274b83f1527SRafal Ozieblo } 3275b83f1527SRafal Ozieblo 3276b83f1527SRafal Ozieblo static void macb_probe_queues(void __iomem *mem, 3277b83f1527SRafal Ozieblo bool native_io, 3278b83f1527SRafal Ozieblo unsigned int *queue_mask, 3279b83f1527SRafal Ozieblo unsigned int *num_queues) 3280b83f1527SRafal Ozieblo { 3281b83f1527SRafal Ozieblo unsigned int hw_q; 3282b83f1527SRafal Ozieblo 3283b83f1527SRafal Ozieblo *queue_mask = 0x1; 3284b83f1527SRafal Ozieblo *num_queues = 1; 3285b83f1527SRafal Ozieblo 3286b83f1527SRafal Ozieblo /* is it macb or gem ? 3287b83f1527SRafal Ozieblo * 3288b83f1527SRafal Ozieblo * We need to read directly from the hardware here because 3289b83f1527SRafal Ozieblo * we are early in the probe process and don't have the 3290b83f1527SRafal Ozieblo * MACB_CAPS_MACB_IS_GEM flag positioned 3291b83f1527SRafal Ozieblo */ 3292b83f1527SRafal Ozieblo if (!hw_is_gem(mem, native_io)) 3293b83f1527SRafal Ozieblo return; 3294b83f1527SRafal Ozieblo 3295b83f1527SRafal Ozieblo /* bit 0 is never set but queue 0 always exists */ 3296b83f1527SRafal Ozieblo *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff; 3297b83f1527SRafal Ozieblo 3298b83f1527SRafal Ozieblo *queue_mask |= 0x1; 3299b83f1527SRafal Ozieblo 3300b83f1527SRafal Ozieblo for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q) 3301b83f1527SRafal Ozieblo if (*queue_mask & (1 << hw_q)) 3302b83f1527SRafal Ozieblo (*num_queues)++; 3303b83f1527SRafal Ozieblo } 3304b83f1527SRafal Ozieblo 3305b83f1527SRafal Ozieblo static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, 3306b83f1527SRafal Ozieblo struct clk **hclk, struct clk **tx_clk, 3307b83f1527SRafal Ozieblo struct clk **rx_clk) 3308b83f1527SRafal Ozieblo { 3309b83f1527SRafal Ozieblo struct macb_platform_data *pdata; 3310b83f1527SRafal Ozieblo int err; 3311b83f1527SRafal Ozieblo 3312b83f1527SRafal Ozieblo pdata = dev_get_platdata(&pdev->dev); 3313b83f1527SRafal Ozieblo if (pdata) { 3314b83f1527SRafal Ozieblo *pclk = pdata->pclk; 3315b83f1527SRafal Ozieblo *hclk = pdata->hclk; 3316b83f1527SRafal Ozieblo } else { 3317b83f1527SRafal Ozieblo *pclk = devm_clk_get(&pdev->dev, "pclk"); 3318b83f1527SRafal Ozieblo *hclk = devm_clk_get(&pdev->dev, "hclk"); 3319b83f1527SRafal Ozieblo } 3320b83f1527SRafal Ozieblo 3321b83f1527SRafal Ozieblo if (IS_ERR(*pclk)) { 3322b83f1527SRafal Ozieblo err = PTR_ERR(*pclk); 3323b83f1527SRafal Ozieblo dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err); 3324b83f1527SRafal Ozieblo return err; 3325b83f1527SRafal Ozieblo } 3326b83f1527SRafal Ozieblo 3327b83f1527SRafal Ozieblo if (IS_ERR(*hclk)) { 3328b83f1527SRafal Ozieblo err = PTR_ERR(*hclk); 3329b83f1527SRafal Ozieblo dev_err(&pdev->dev, "failed to get hclk (%u)\n", err); 3330b83f1527SRafal Ozieblo return err; 3331b83f1527SRafal Ozieblo } 3332b83f1527SRafal Ozieblo 3333b83f1527SRafal Ozieblo *tx_clk = devm_clk_get(&pdev->dev, "tx_clk"); 3334b83f1527SRafal Ozieblo if (IS_ERR(*tx_clk)) 3335b83f1527SRafal Ozieblo *tx_clk = NULL; 3336b83f1527SRafal Ozieblo 3337b83f1527SRafal Ozieblo *rx_clk = devm_clk_get(&pdev->dev, "rx_clk"); 3338b83f1527SRafal Ozieblo if (IS_ERR(*rx_clk)) 3339b83f1527SRafal Ozieblo *rx_clk = NULL; 3340b83f1527SRafal Ozieblo 3341b83f1527SRafal Ozieblo err = clk_prepare_enable(*pclk); 3342b83f1527SRafal Ozieblo if (err) { 3343b83f1527SRafal Ozieblo dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err); 3344b83f1527SRafal Ozieblo return err; 3345b83f1527SRafal Ozieblo } 3346b83f1527SRafal Ozieblo 3347b83f1527SRafal Ozieblo err = clk_prepare_enable(*hclk); 3348b83f1527SRafal Ozieblo if (err) { 3349b83f1527SRafal Ozieblo dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err); 3350b83f1527SRafal Ozieblo goto err_disable_pclk; 3351b83f1527SRafal Ozieblo } 3352b83f1527SRafal Ozieblo 3353b83f1527SRafal Ozieblo err = clk_prepare_enable(*tx_clk); 3354b83f1527SRafal Ozieblo if (err) { 3355b83f1527SRafal Ozieblo dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); 3356b83f1527SRafal Ozieblo goto err_disable_hclk; 3357b83f1527SRafal Ozieblo } 3358b83f1527SRafal Ozieblo 3359b83f1527SRafal Ozieblo err = clk_prepare_enable(*rx_clk); 3360b83f1527SRafal Ozieblo if (err) { 3361b83f1527SRafal Ozieblo dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err); 3362b83f1527SRafal Ozieblo goto err_disable_txclk; 3363b83f1527SRafal Ozieblo } 3364b83f1527SRafal Ozieblo 3365b83f1527SRafal Ozieblo return 0; 3366b83f1527SRafal Ozieblo 3367b83f1527SRafal Ozieblo err_disable_txclk: 3368b83f1527SRafal Ozieblo clk_disable_unprepare(*tx_clk); 3369b83f1527SRafal Ozieblo 3370b83f1527SRafal Ozieblo err_disable_hclk: 3371b83f1527SRafal Ozieblo clk_disable_unprepare(*hclk); 3372b83f1527SRafal Ozieblo 3373b83f1527SRafal Ozieblo err_disable_pclk: 3374b83f1527SRafal Ozieblo clk_disable_unprepare(*pclk); 3375b83f1527SRafal Ozieblo 3376b83f1527SRafal Ozieblo return err; 3377b83f1527SRafal Ozieblo } 3378b83f1527SRafal Ozieblo 3379b83f1527SRafal Ozieblo static int macb_init(struct platform_device *pdev) 3380b83f1527SRafal Ozieblo { 3381b83f1527SRafal Ozieblo struct net_device *dev = platform_get_drvdata(pdev); 3382b83f1527SRafal Ozieblo unsigned int hw_q, q; 3383b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 3384b83f1527SRafal Ozieblo struct macb_queue *queue; 3385b83f1527SRafal Ozieblo int err; 3386ae8223deSRafal Ozieblo u32 val, reg; 3387b83f1527SRafal Ozieblo 3388b83f1527SRafal Ozieblo bp->tx_ring_size = DEFAULT_TX_RING_SIZE; 3389b83f1527SRafal Ozieblo bp->rx_ring_size = DEFAULT_RX_RING_SIZE; 3390b83f1527SRafal Ozieblo 3391b83f1527SRafal Ozieblo /* set the queue register mapping once for all: queue0 has a special 3392b83f1527SRafal Ozieblo * register mapping but we don't want to test the queue index then 3393b83f1527SRafal Ozieblo * compute the corresponding register offset at run time. 3394b83f1527SRafal Ozieblo */ 3395b83f1527SRafal Ozieblo for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) { 3396b83f1527SRafal Ozieblo if (!(bp->queue_mask & (1 << hw_q))) 3397b83f1527SRafal Ozieblo continue; 3398b83f1527SRafal Ozieblo 3399b83f1527SRafal Ozieblo queue = &bp->queues[q]; 3400b83f1527SRafal Ozieblo queue->bp = bp; 3401ae1f2a56SRafal Ozieblo netif_napi_add(dev, &queue->napi, macb_poll, 64); 3402b83f1527SRafal Ozieblo if (hw_q) { 3403b83f1527SRafal Ozieblo queue->ISR = GEM_ISR(hw_q - 1); 3404b83f1527SRafal Ozieblo queue->IER = GEM_IER(hw_q - 1); 3405b83f1527SRafal Ozieblo queue->IDR = GEM_IDR(hw_q - 1); 3406b83f1527SRafal Ozieblo queue->IMR = GEM_IMR(hw_q - 1); 3407b83f1527SRafal Ozieblo queue->TBQP = GEM_TBQP(hw_q - 1); 3408ae1f2a56SRafal Ozieblo queue->RBQP = GEM_RBQP(hw_q - 1); 3409ae1f2a56SRafal Ozieblo queue->RBQS = GEM_RBQS(hw_q - 1); 3410b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 3411ae1f2a56SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) { 3412b83f1527SRafal Ozieblo queue->TBQPH = GEM_TBQPH(hw_q - 1); 3413ae1f2a56SRafal Ozieblo queue->RBQPH = GEM_RBQPH(hw_q - 1); 3414ae1f2a56SRafal Ozieblo } 3415b83f1527SRafal Ozieblo #endif 3416b83f1527SRafal Ozieblo } else { 3417b83f1527SRafal Ozieblo /* queue0 uses legacy registers */ 3418b83f1527SRafal Ozieblo queue->ISR = MACB_ISR; 3419b83f1527SRafal Ozieblo queue->IER = MACB_IER; 3420b83f1527SRafal Ozieblo queue->IDR = MACB_IDR; 3421b83f1527SRafal Ozieblo queue->IMR = MACB_IMR; 3422b83f1527SRafal Ozieblo queue->TBQP = MACB_TBQP; 3423ae1f2a56SRafal Ozieblo queue->RBQP = MACB_RBQP; 3424b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 3425ae1f2a56SRafal Ozieblo if (bp->hw_dma_cap & HW_DMA_CAP_64B) { 3426b83f1527SRafal Ozieblo queue->TBQPH = MACB_TBQPH; 3427ae1f2a56SRafal Ozieblo queue->RBQPH = MACB_RBQPH; 3428ae1f2a56SRafal Ozieblo } 3429b83f1527SRafal Ozieblo #endif 3430b83f1527SRafal Ozieblo } 3431b83f1527SRafal Ozieblo 3432b83f1527SRafal Ozieblo /* get irq: here we use the linux queue index, not the hardware 3433b83f1527SRafal Ozieblo * queue index. the queue irq definitions in the device tree 3434b83f1527SRafal Ozieblo * must remove the optional gaps that could exist in the 3435b83f1527SRafal Ozieblo * hardware queue mask. 3436b83f1527SRafal Ozieblo */ 3437b83f1527SRafal Ozieblo queue->irq = platform_get_irq(pdev, q); 3438b83f1527SRafal Ozieblo err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt, 3439b83f1527SRafal Ozieblo IRQF_SHARED, dev->name, queue); 3440b83f1527SRafal Ozieblo if (err) { 3441b83f1527SRafal Ozieblo dev_err(&pdev->dev, 3442b83f1527SRafal Ozieblo "Unable to request IRQ %d (error %d)\n", 3443b83f1527SRafal Ozieblo queue->irq, err); 3444b83f1527SRafal Ozieblo return err; 3445b83f1527SRafal Ozieblo } 3446b83f1527SRafal Ozieblo 3447b83f1527SRafal Ozieblo INIT_WORK(&queue->tx_error_task, macb_tx_error_task); 3448b83f1527SRafal Ozieblo q++; 3449b83f1527SRafal Ozieblo } 3450b83f1527SRafal Ozieblo 3451b83f1527SRafal Ozieblo dev->netdev_ops = &macb_netdev_ops; 3452b83f1527SRafal Ozieblo 3453b83f1527SRafal Ozieblo /* setup appropriated routines according to adapter type */ 3454b83f1527SRafal Ozieblo if (macb_is_gem(bp)) { 3455b83f1527SRafal Ozieblo bp->max_tx_length = GEM_MAX_TX_LEN; 3456b83f1527SRafal Ozieblo bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers; 3457b83f1527SRafal Ozieblo bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers; 3458b83f1527SRafal Ozieblo bp->macbgem_ops.mog_init_rings = gem_init_rings; 3459b83f1527SRafal Ozieblo bp->macbgem_ops.mog_rx = gem_rx; 3460b83f1527SRafal Ozieblo dev->ethtool_ops = &gem_ethtool_ops; 3461b83f1527SRafal Ozieblo } else { 3462b83f1527SRafal Ozieblo bp->max_tx_length = MACB_MAX_TX_LEN; 3463b83f1527SRafal Ozieblo bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers; 3464b83f1527SRafal Ozieblo bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers; 3465b83f1527SRafal Ozieblo bp->macbgem_ops.mog_init_rings = macb_init_rings; 3466b83f1527SRafal Ozieblo bp->macbgem_ops.mog_rx = macb_rx; 3467b83f1527SRafal Ozieblo dev->ethtool_ops = &macb_ethtool_ops; 3468b83f1527SRafal Ozieblo } 3469b83f1527SRafal Ozieblo 3470b83f1527SRafal Ozieblo /* Set features */ 3471b83f1527SRafal Ozieblo dev->hw_features = NETIF_F_SG; 3472b83f1527SRafal Ozieblo 3473b83f1527SRafal Ozieblo /* Check LSO capability */ 3474b83f1527SRafal Ozieblo if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6))) 3475b83f1527SRafal Ozieblo dev->hw_features |= MACB_NETIF_LSO; 3476b83f1527SRafal Ozieblo 3477b83f1527SRafal Ozieblo /* Checksum offload is only available on gem with packet buffer */ 3478b83f1527SRafal Ozieblo if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) 3479b83f1527SRafal Ozieblo dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM; 3480b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_SG_DISABLED) 3481b83f1527SRafal Ozieblo dev->hw_features &= ~NETIF_F_SG; 3482b83f1527SRafal Ozieblo dev->features = dev->hw_features; 3483b83f1527SRafal Ozieblo 3484ae8223deSRafal Ozieblo /* Check RX Flow Filters support. 3485ae8223deSRafal Ozieblo * Max Rx flows set by availability of screeners & compare regs: 3486ae8223deSRafal Ozieblo * each 4-tuple define requires 1 T2 screener reg + 3 compare regs 3487ae8223deSRafal Ozieblo */ 3488ae8223deSRafal Ozieblo reg = gem_readl(bp, DCFG8); 3489ae8223deSRafal Ozieblo bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3), 3490ae8223deSRafal Ozieblo GEM_BFEXT(T2SCR, reg)); 3491ae8223deSRafal Ozieblo if (bp->max_tuples > 0) { 3492ae8223deSRafal Ozieblo /* also needs one ethtype match to check IPv4 */ 3493ae8223deSRafal Ozieblo if (GEM_BFEXT(SCR2ETH, reg) > 0) { 3494ae8223deSRafal Ozieblo /* program this reg now */ 3495ae8223deSRafal Ozieblo reg = 0; 3496ae8223deSRafal Ozieblo reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg); 3497ae8223deSRafal Ozieblo gem_writel_n(bp, ETHT, SCRT2_ETHT, reg); 3498ae8223deSRafal Ozieblo /* Filtering is supported in hw but don't enable it in kernel now */ 3499ae8223deSRafal Ozieblo dev->hw_features |= NETIF_F_NTUPLE; 3500ae8223deSRafal Ozieblo /* init Rx flow definitions */ 3501ae8223deSRafal Ozieblo INIT_LIST_HEAD(&bp->rx_fs_list.list); 3502ae8223deSRafal Ozieblo bp->rx_fs_list.count = 0; 3503ae8223deSRafal Ozieblo spin_lock_init(&bp->rx_fs_lock); 3504ae8223deSRafal Ozieblo } else 3505ae8223deSRafal Ozieblo bp->max_tuples = 0; 3506ae8223deSRafal Ozieblo } 3507ae8223deSRafal Ozieblo 3508b83f1527SRafal Ozieblo if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { 3509b83f1527SRafal Ozieblo val = 0; 3510b83f1527SRafal Ozieblo if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) 3511b83f1527SRafal Ozieblo val = GEM_BIT(RGMII); 3512b83f1527SRafal Ozieblo else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && 3513b83f1527SRafal Ozieblo (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) 3514b83f1527SRafal Ozieblo val = MACB_BIT(RMII); 3515b83f1527SRafal Ozieblo else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) 3516b83f1527SRafal Ozieblo val = MACB_BIT(MII); 3517b83f1527SRafal Ozieblo 3518b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) 3519b83f1527SRafal Ozieblo val |= MACB_BIT(CLKEN); 3520b83f1527SRafal Ozieblo 3521b83f1527SRafal Ozieblo macb_or_gem_writel(bp, USRIO, val); 3522b83f1527SRafal Ozieblo } 3523b83f1527SRafal Ozieblo 3524b83f1527SRafal Ozieblo /* Set MII management clock divider */ 3525b83f1527SRafal Ozieblo val = macb_mdc_clk_div(bp); 3526b83f1527SRafal Ozieblo val |= macb_dbw(bp); 3527b83f1527SRafal Ozieblo if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) 3528b83f1527SRafal Ozieblo val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); 3529b83f1527SRafal Ozieblo macb_writel(bp, NCFGR, val); 3530b83f1527SRafal Ozieblo 3531b83f1527SRafal Ozieblo return 0; 3532b83f1527SRafal Ozieblo } 3533b83f1527SRafal Ozieblo 3534b83f1527SRafal Ozieblo #if defined(CONFIG_OF) 3535b83f1527SRafal Ozieblo /* 1518 rounded up */ 3536b83f1527SRafal Ozieblo #define AT91ETHER_MAX_RBUFF_SZ 0x600 3537b83f1527SRafal Ozieblo /* max number of receive buffers */ 3538b83f1527SRafal Ozieblo #define AT91ETHER_MAX_RX_DESCR 9 3539b83f1527SRafal Ozieblo 3540b83f1527SRafal Ozieblo /* Initialize and start the Receiver and Transmit subsystems */ 3541b83f1527SRafal Ozieblo static int at91ether_start(struct net_device *dev) 3542b83f1527SRafal Ozieblo { 3543b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev); 3544ae1f2a56SRafal Ozieblo struct macb_queue *q = &lp->queues[0]; 3545b83f1527SRafal Ozieblo struct macb_dma_desc *desc; 3546b83f1527SRafal Ozieblo dma_addr_t addr; 3547b83f1527SRafal Ozieblo u32 ctl; 3548b83f1527SRafal Ozieblo int i; 3549b83f1527SRafal Ozieblo 3550ae1f2a56SRafal Ozieblo q->rx_ring = dma_alloc_coherent(&lp->pdev->dev, 3551b83f1527SRafal Ozieblo (AT91ETHER_MAX_RX_DESCR * 3552b83f1527SRafal Ozieblo macb_dma_desc_get_size(lp)), 3553ae1f2a56SRafal Ozieblo &q->rx_ring_dma, GFP_KERNEL); 3554ae1f2a56SRafal Ozieblo if (!q->rx_ring) 3555b83f1527SRafal Ozieblo return -ENOMEM; 3556b83f1527SRafal Ozieblo 3557ae1f2a56SRafal Ozieblo q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev, 3558b83f1527SRafal Ozieblo AT91ETHER_MAX_RX_DESCR * 3559b83f1527SRafal Ozieblo AT91ETHER_MAX_RBUFF_SZ, 3560ae1f2a56SRafal Ozieblo &q->rx_buffers_dma, GFP_KERNEL); 3561ae1f2a56SRafal Ozieblo if (!q->rx_buffers) { 3562b83f1527SRafal Ozieblo dma_free_coherent(&lp->pdev->dev, 3563b83f1527SRafal Ozieblo AT91ETHER_MAX_RX_DESCR * 3564b83f1527SRafal Ozieblo macb_dma_desc_get_size(lp), 3565ae1f2a56SRafal Ozieblo q->rx_ring, q->rx_ring_dma); 3566ae1f2a56SRafal Ozieblo q->rx_ring = NULL; 3567b83f1527SRafal Ozieblo return -ENOMEM; 3568b83f1527SRafal Ozieblo } 3569b83f1527SRafal Ozieblo 3570ae1f2a56SRafal Ozieblo addr = q->rx_buffers_dma; 3571b83f1527SRafal Ozieblo for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) { 3572ae1f2a56SRafal Ozieblo desc = macb_rx_desc(q, i); 3573b83f1527SRafal Ozieblo macb_set_addr(lp, desc, addr); 3574b83f1527SRafal Ozieblo desc->ctrl = 0; 3575b83f1527SRafal Ozieblo addr += AT91ETHER_MAX_RBUFF_SZ; 3576b83f1527SRafal Ozieblo } 3577b83f1527SRafal Ozieblo 3578b83f1527SRafal Ozieblo /* Set the Wrap bit on the last descriptor */ 3579b83f1527SRafal Ozieblo desc->addr |= MACB_BIT(RX_WRAP); 3580b83f1527SRafal Ozieblo 3581b83f1527SRafal Ozieblo /* Reset buffer index */ 3582ae1f2a56SRafal Ozieblo q->rx_tail = 0; 3583b83f1527SRafal Ozieblo 3584b83f1527SRafal Ozieblo /* Program address of descriptor list in Rx Buffer Queue register */ 3585ae1f2a56SRafal Ozieblo macb_writel(lp, RBQP, q->rx_ring_dma); 3586b83f1527SRafal Ozieblo 3587b83f1527SRafal Ozieblo /* Enable Receive and Transmit */ 3588b83f1527SRafal Ozieblo ctl = macb_readl(lp, NCR); 3589b83f1527SRafal Ozieblo macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE)); 3590b83f1527SRafal Ozieblo 3591b83f1527SRafal Ozieblo return 0; 3592b83f1527SRafal Ozieblo } 3593b83f1527SRafal Ozieblo 3594b83f1527SRafal Ozieblo /* Open the ethernet interface */ 3595b83f1527SRafal Ozieblo static int at91ether_open(struct net_device *dev) 3596b83f1527SRafal Ozieblo { 3597b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev); 3598b83f1527SRafal Ozieblo u32 ctl; 3599b83f1527SRafal Ozieblo int ret; 3600b83f1527SRafal Ozieblo 3601b83f1527SRafal Ozieblo /* Clear internal statistics */ 3602b83f1527SRafal Ozieblo ctl = macb_readl(lp, NCR); 3603b83f1527SRafal Ozieblo macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT)); 3604b83f1527SRafal Ozieblo 3605b83f1527SRafal Ozieblo macb_set_hwaddr(lp); 3606b83f1527SRafal Ozieblo 3607b83f1527SRafal Ozieblo ret = at91ether_start(dev); 3608b83f1527SRafal Ozieblo if (ret) 3609b83f1527SRafal Ozieblo return ret; 3610b83f1527SRafal Ozieblo 3611b83f1527SRafal Ozieblo /* Enable MAC interrupts */ 3612b83f1527SRafal Ozieblo macb_writel(lp, IER, MACB_BIT(RCOMP) | 3613b83f1527SRafal Ozieblo MACB_BIT(RXUBR) | 3614b83f1527SRafal Ozieblo MACB_BIT(ISR_TUND) | 3615b83f1527SRafal Ozieblo MACB_BIT(ISR_RLE) | 3616b83f1527SRafal Ozieblo MACB_BIT(TCOMP) | 3617b83f1527SRafal Ozieblo MACB_BIT(ISR_ROVR) | 3618b83f1527SRafal Ozieblo MACB_BIT(HRESP)); 3619b83f1527SRafal Ozieblo 3620b83f1527SRafal Ozieblo /* schedule a link state check */ 3621b83f1527SRafal Ozieblo phy_start(dev->phydev); 3622b83f1527SRafal Ozieblo 3623b83f1527SRafal Ozieblo netif_start_queue(dev); 3624b83f1527SRafal Ozieblo 3625b83f1527SRafal Ozieblo return 0; 3626b83f1527SRafal Ozieblo } 3627b83f1527SRafal Ozieblo 3628b83f1527SRafal Ozieblo /* Close the interface */ 3629b83f1527SRafal Ozieblo static int at91ether_close(struct net_device *dev) 3630b83f1527SRafal Ozieblo { 3631b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev); 3632ae1f2a56SRafal Ozieblo struct macb_queue *q = &lp->queues[0]; 3633b83f1527SRafal Ozieblo u32 ctl; 3634b83f1527SRafal Ozieblo 3635b83f1527SRafal Ozieblo /* Disable Receiver and Transmitter */ 3636b83f1527SRafal Ozieblo ctl = macb_readl(lp, NCR); 3637b83f1527SRafal Ozieblo macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE))); 3638b83f1527SRafal Ozieblo 3639b83f1527SRafal Ozieblo /* Disable MAC interrupts */ 3640b83f1527SRafal Ozieblo macb_writel(lp, IDR, MACB_BIT(RCOMP) | 3641b83f1527SRafal Ozieblo MACB_BIT(RXUBR) | 3642b83f1527SRafal Ozieblo MACB_BIT(ISR_TUND) | 3643b83f1527SRafal Ozieblo MACB_BIT(ISR_RLE) | 3644b83f1527SRafal Ozieblo MACB_BIT(TCOMP) | 3645b83f1527SRafal Ozieblo MACB_BIT(ISR_ROVR) | 3646b83f1527SRafal Ozieblo MACB_BIT(HRESP)); 3647b83f1527SRafal Ozieblo 3648b83f1527SRafal Ozieblo netif_stop_queue(dev); 3649b83f1527SRafal Ozieblo 3650b83f1527SRafal Ozieblo dma_free_coherent(&lp->pdev->dev, 3651b83f1527SRafal Ozieblo AT91ETHER_MAX_RX_DESCR * 3652b83f1527SRafal Ozieblo macb_dma_desc_get_size(lp), 3653ae1f2a56SRafal Ozieblo q->rx_ring, q->rx_ring_dma); 3654ae1f2a56SRafal Ozieblo q->rx_ring = NULL; 3655b83f1527SRafal Ozieblo 3656b83f1527SRafal Ozieblo dma_free_coherent(&lp->pdev->dev, 3657b83f1527SRafal Ozieblo AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ, 3658ae1f2a56SRafal Ozieblo q->rx_buffers, q->rx_buffers_dma); 3659ae1f2a56SRafal Ozieblo q->rx_buffers = NULL; 3660b83f1527SRafal Ozieblo 3661b83f1527SRafal Ozieblo return 0; 3662b83f1527SRafal Ozieblo } 3663b83f1527SRafal Ozieblo 3664b83f1527SRafal Ozieblo /* Transmit packet */ 3665d1c38957SClaudiu Beznea static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb, 3666d1c38957SClaudiu Beznea struct net_device *dev) 3667b83f1527SRafal Ozieblo { 3668b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev); 3669b83f1527SRafal Ozieblo 3670b83f1527SRafal Ozieblo if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) { 3671b83f1527SRafal Ozieblo netif_stop_queue(dev); 3672b83f1527SRafal Ozieblo 3673b83f1527SRafal Ozieblo /* Store packet information (to free when Tx completed) */ 3674b83f1527SRafal Ozieblo lp->skb = skb; 3675b83f1527SRafal Ozieblo lp->skb_length = skb->len; 3676b83f1527SRafal Ozieblo lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, 3677b83f1527SRafal Ozieblo DMA_TO_DEVICE); 3678b83f1527SRafal Ozieblo if (dma_mapping_error(NULL, lp->skb_physaddr)) { 3679b83f1527SRafal Ozieblo dev_kfree_skb_any(skb); 3680b83f1527SRafal Ozieblo dev->stats.tx_dropped++; 3681b83f1527SRafal Ozieblo netdev_err(dev, "%s: DMA mapping error\n", __func__); 3682b83f1527SRafal Ozieblo return NETDEV_TX_OK; 3683b83f1527SRafal Ozieblo } 3684b83f1527SRafal Ozieblo 3685b83f1527SRafal Ozieblo /* Set address of the data in the Transmit Address register */ 3686b83f1527SRafal Ozieblo macb_writel(lp, TAR, lp->skb_physaddr); 3687b83f1527SRafal Ozieblo /* Set length of the packet in the Transmit Control register */ 3688b83f1527SRafal Ozieblo macb_writel(lp, TCR, skb->len); 3689b83f1527SRafal Ozieblo 3690b83f1527SRafal Ozieblo } else { 3691b83f1527SRafal Ozieblo netdev_err(dev, "%s called, but device is busy!\n", __func__); 3692b83f1527SRafal Ozieblo return NETDEV_TX_BUSY; 3693b83f1527SRafal Ozieblo } 3694b83f1527SRafal Ozieblo 3695b83f1527SRafal Ozieblo return NETDEV_TX_OK; 3696b83f1527SRafal Ozieblo } 3697b83f1527SRafal Ozieblo 3698b83f1527SRafal Ozieblo /* Extract received frame from buffer descriptors and sent to upper layers. 3699b83f1527SRafal Ozieblo * (Called from interrupt context) 3700b83f1527SRafal Ozieblo */ 3701b83f1527SRafal Ozieblo static void at91ether_rx(struct net_device *dev) 3702b83f1527SRafal Ozieblo { 3703b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev); 3704ae1f2a56SRafal Ozieblo struct macb_queue *q = &lp->queues[0]; 3705b83f1527SRafal Ozieblo struct macb_dma_desc *desc; 3706b83f1527SRafal Ozieblo unsigned char *p_recv; 3707b83f1527SRafal Ozieblo struct sk_buff *skb; 3708b83f1527SRafal Ozieblo unsigned int pktlen; 3709b83f1527SRafal Ozieblo 3710ae1f2a56SRafal Ozieblo desc = macb_rx_desc(q, q->rx_tail); 3711b83f1527SRafal Ozieblo while (desc->addr & MACB_BIT(RX_USED)) { 3712ae1f2a56SRafal Ozieblo p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ; 3713b83f1527SRafal Ozieblo pktlen = MACB_BF(RX_FRMLEN, desc->ctrl); 3714b83f1527SRafal Ozieblo skb = netdev_alloc_skb(dev, pktlen + 2); 3715b83f1527SRafal Ozieblo if (skb) { 3716b83f1527SRafal Ozieblo skb_reserve(skb, 2); 3717b83f1527SRafal Ozieblo skb_put_data(skb, p_recv, pktlen); 3718b83f1527SRafal Ozieblo 3719b83f1527SRafal Ozieblo skb->protocol = eth_type_trans(skb, dev); 3720b83f1527SRafal Ozieblo dev->stats.rx_packets++; 3721b83f1527SRafal Ozieblo dev->stats.rx_bytes += pktlen; 3722b83f1527SRafal Ozieblo netif_rx(skb); 3723b83f1527SRafal Ozieblo } else { 3724b83f1527SRafal Ozieblo dev->stats.rx_dropped++; 3725b83f1527SRafal Ozieblo } 3726b83f1527SRafal Ozieblo 3727b83f1527SRafal Ozieblo if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH)) 3728b83f1527SRafal Ozieblo dev->stats.multicast++; 3729b83f1527SRafal Ozieblo 3730b83f1527SRafal Ozieblo /* reset ownership bit */ 3731b83f1527SRafal Ozieblo desc->addr &= ~MACB_BIT(RX_USED); 3732b83f1527SRafal Ozieblo 3733b83f1527SRafal Ozieblo /* wrap after last buffer */ 3734ae1f2a56SRafal Ozieblo if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1) 3735ae1f2a56SRafal Ozieblo q->rx_tail = 0; 3736b83f1527SRafal Ozieblo else 3737ae1f2a56SRafal Ozieblo q->rx_tail++; 3738b83f1527SRafal Ozieblo 3739ae1f2a56SRafal Ozieblo desc = macb_rx_desc(q, q->rx_tail); 3740b83f1527SRafal Ozieblo } 3741b83f1527SRafal Ozieblo } 3742b83f1527SRafal Ozieblo 3743b83f1527SRafal Ozieblo /* MAC interrupt handler */ 3744b83f1527SRafal Ozieblo static irqreturn_t at91ether_interrupt(int irq, void *dev_id) 3745b83f1527SRafal Ozieblo { 3746b83f1527SRafal Ozieblo struct net_device *dev = dev_id; 3747b83f1527SRafal Ozieblo struct macb *lp = netdev_priv(dev); 3748b83f1527SRafal Ozieblo u32 intstatus, ctl; 3749b83f1527SRafal Ozieblo 3750b83f1527SRafal Ozieblo /* MAC Interrupt Status register indicates what interrupts are pending. 3751b83f1527SRafal Ozieblo * It is automatically cleared once read. 3752b83f1527SRafal Ozieblo */ 3753b83f1527SRafal Ozieblo intstatus = macb_readl(lp, ISR); 3754b83f1527SRafal Ozieblo 3755b83f1527SRafal Ozieblo /* Receive complete */ 3756b83f1527SRafal Ozieblo if (intstatus & MACB_BIT(RCOMP)) 3757b83f1527SRafal Ozieblo at91ether_rx(dev); 3758b83f1527SRafal Ozieblo 3759b83f1527SRafal Ozieblo /* Transmit complete */ 3760b83f1527SRafal Ozieblo if (intstatus & MACB_BIT(TCOMP)) { 3761b83f1527SRafal Ozieblo /* The TCOM bit is set even if the transmission failed */ 3762b83f1527SRafal Ozieblo if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE))) 3763b83f1527SRafal Ozieblo dev->stats.tx_errors++; 3764b83f1527SRafal Ozieblo 3765b83f1527SRafal Ozieblo if (lp->skb) { 3766b83f1527SRafal Ozieblo dev_kfree_skb_irq(lp->skb); 3767b83f1527SRafal Ozieblo lp->skb = NULL; 3768b83f1527SRafal Ozieblo dma_unmap_single(NULL, lp->skb_physaddr, 3769b83f1527SRafal Ozieblo lp->skb_length, DMA_TO_DEVICE); 3770b83f1527SRafal Ozieblo dev->stats.tx_packets++; 3771b83f1527SRafal Ozieblo dev->stats.tx_bytes += lp->skb_length; 3772b83f1527SRafal Ozieblo } 3773b83f1527SRafal Ozieblo netif_wake_queue(dev); 3774b83f1527SRafal Ozieblo } 3775b83f1527SRafal Ozieblo 3776b83f1527SRafal Ozieblo /* Work-around for EMAC Errata section 41.3.1 */ 3777b83f1527SRafal Ozieblo if (intstatus & MACB_BIT(RXUBR)) { 3778b83f1527SRafal Ozieblo ctl = macb_readl(lp, NCR); 3779b83f1527SRafal Ozieblo macb_writel(lp, NCR, ctl & ~MACB_BIT(RE)); 3780b83f1527SRafal Ozieblo wmb(); 3781b83f1527SRafal Ozieblo macb_writel(lp, NCR, ctl | MACB_BIT(RE)); 3782b83f1527SRafal Ozieblo } 3783b83f1527SRafal Ozieblo 3784b83f1527SRafal Ozieblo if (intstatus & MACB_BIT(ISR_ROVR)) 3785b83f1527SRafal Ozieblo netdev_err(dev, "ROVR error\n"); 3786b83f1527SRafal Ozieblo 3787b83f1527SRafal Ozieblo return IRQ_HANDLED; 3788b83f1527SRafal Ozieblo } 3789b83f1527SRafal Ozieblo 3790b83f1527SRafal Ozieblo #ifdef CONFIG_NET_POLL_CONTROLLER 3791b83f1527SRafal Ozieblo static void at91ether_poll_controller(struct net_device *dev) 3792b83f1527SRafal Ozieblo { 3793b83f1527SRafal Ozieblo unsigned long flags; 3794b83f1527SRafal Ozieblo 3795b83f1527SRafal Ozieblo local_irq_save(flags); 3796b83f1527SRafal Ozieblo at91ether_interrupt(dev->irq, dev); 3797b83f1527SRafal Ozieblo local_irq_restore(flags); 3798b83f1527SRafal Ozieblo } 3799b83f1527SRafal Ozieblo #endif 3800b83f1527SRafal Ozieblo 3801b83f1527SRafal Ozieblo static const struct net_device_ops at91ether_netdev_ops = { 3802b83f1527SRafal Ozieblo .ndo_open = at91ether_open, 3803b83f1527SRafal Ozieblo .ndo_stop = at91ether_close, 3804b83f1527SRafal Ozieblo .ndo_start_xmit = at91ether_start_xmit, 3805b83f1527SRafal Ozieblo .ndo_get_stats = macb_get_stats, 3806b83f1527SRafal Ozieblo .ndo_set_rx_mode = macb_set_rx_mode, 3807b83f1527SRafal Ozieblo .ndo_set_mac_address = eth_mac_addr, 3808b83f1527SRafal Ozieblo .ndo_do_ioctl = macb_ioctl, 3809b83f1527SRafal Ozieblo .ndo_validate_addr = eth_validate_addr, 3810b83f1527SRafal Ozieblo #ifdef CONFIG_NET_POLL_CONTROLLER 3811b83f1527SRafal Ozieblo .ndo_poll_controller = at91ether_poll_controller, 3812b83f1527SRafal Ozieblo #endif 3813b83f1527SRafal Ozieblo }; 3814b83f1527SRafal Ozieblo 3815b83f1527SRafal Ozieblo static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk, 3816b83f1527SRafal Ozieblo struct clk **hclk, struct clk **tx_clk, 3817b83f1527SRafal Ozieblo struct clk **rx_clk) 3818b83f1527SRafal Ozieblo { 3819b83f1527SRafal Ozieblo int err; 3820b83f1527SRafal Ozieblo 3821b83f1527SRafal Ozieblo *hclk = NULL; 3822b83f1527SRafal Ozieblo *tx_clk = NULL; 3823b83f1527SRafal Ozieblo *rx_clk = NULL; 3824b83f1527SRafal Ozieblo 3825b83f1527SRafal Ozieblo *pclk = devm_clk_get(&pdev->dev, "ether_clk"); 3826b83f1527SRafal Ozieblo if (IS_ERR(*pclk)) 3827b83f1527SRafal Ozieblo return PTR_ERR(*pclk); 3828b83f1527SRafal Ozieblo 3829b83f1527SRafal Ozieblo err = clk_prepare_enable(*pclk); 3830b83f1527SRafal Ozieblo if (err) { 3831b83f1527SRafal Ozieblo dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err); 3832b83f1527SRafal Ozieblo return err; 3833b83f1527SRafal Ozieblo } 3834b83f1527SRafal Ozieblo 3835b83f1527SRafal Ozieblo return 0; 3836b83f1527SRafal Ozieblo } 3837b83f1527SRafal Ozieblo 3838b83f1527SRafal Ozieblo static int at91ether_init(struct platform_device *pdev) 3839b83f1527SRafal Ozieblo { 3840b83f1527SRafal Ozieblo struct net_device *dev = platform_get_drvdata(pdev); 3841b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(dev); 3842b83f1527SRafal Ozieblo int err; 3843b83f1527SRafal Ozieblo u32 reg; 3844b83f1527SRafal Ozieblo 3845fec9d3b1SAlexandre Belloni bp->queues[0].bp = bp; 3846fec9d3b1SAlexandre Belloni 3847b83f1527SRafal Ozieblo dev->netdev_ops = &at91ether_netdev_ops; 3848b83f1527SRafal Ozieblo dev->ethtool_ops = &macb_ethtool_ops; 3849b83f1527SRafal Ozieblo 3850b83f1527SRafal Ozieblo err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt, 3851b83f1527SRafal Ozieblo 0, dev->name, dev); 3852b83f1527SRafal Ozieblo if (err) 3853b83f1527SRafal Ozieblo return err; 3854b83f1527SRafal Ozieblo 3855b83f1527SRafal Ozieblo macb_writel(bp, NCR, 0); 3856b83f1527SRafal Ozieblo 3857b83f1527SRafal Ozieblo reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG); 3858b83f1527SRafal Ozieblo if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) 3859b83f1527SRafal Ozieblo reg |= MACB_BIT(RM9200_RMII); 3860b83f1527SRafal Ozieblo 3861b83f1527SRafal Ozieblo macb_writel(bp, NCFGR, reg); 3862b83f1527SRafal Ozieblo 3863b83f1527SRafal Ozieblo return 0; 3864b83f1527SRafal Ozieblo } 3865b83f1527SRafal Ozieblo 3866b83f1527SRafal Ozieblo static const struct macb_config at91sam9260_config = { 3867b83f1527SRafal Ozieblo .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, 3868b83f1527SRafal Ozieblo .clk_init = macb_clk_init, 3869b83f1527SRafal Ozieblo .init = macb_init, 3870b83f1527SRafal Ozieblo }; 3871b83f1527SRafal Ozieblo 3872eb4ed8e2SNicolas Ferre static const struct macb_config sama5d3macb_config = { 3873eb4ed8e2SNicolas Ferre .caps = MACB_CAPS_SG_DISABLED 3874eb4ed8e2SNicolas Ferre | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, 3875eb4ed8e2SNicolas Ferre .clk_init = macb_clk_init, 3876eb4ed8e2SNicolas Ferre .init = macb_init, 3877eb4ed8e2SNicolas Ferre }; 3878eb4ed8e2SNicolas Ferre 3879b83f1527SRafal Ozieblo static const struct macb_config pc302gem_config = { 3880b83f1527SRafal Ozieblo .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE, 3881b83f1527SRafal Ozieblo .dma_burst_length = 16, 3882b83f1527SRafal Ozieblo .clk_init = macb_clk_init, 3883b83f1527SRafal Ozieblo .init = macb_init, 3884b83f1527SRafal Ozieblo }; 3885b83f1527SRafal Ozieblo 3886b83f1527SRafal Ozieblo static const struct macb_config sama5d2_config = { 3887b83f1527SRafal Ozieblo .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, 3888b83f1527SRafal Ozieblo .dma_burst_length = 16, 3889b83f1527SRafal Ozieblo .clk_init = macb_clk_init, 3890b83f1527SRafal Ozieblo .init = macb_init, 3891b83f1527SRafal Ozieblo }; 3892b83f1527SRafal Ozieblo 3893b83f1527SRafal Ozieblo static const struct macb_config sama5d3_config = { 3894b83f1527SRafal Ozieblo .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE 3895233a1587Svishnuvardhan | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO, 3896b83f1527SRafal Ozieblo .dma_burst_length = 16, 3897b83f1527SRafal Ozieblo .clk_init = macb_clk_init, 3898b83f1527SRafal Ozieblo .init = macb_init, 3899233a1587Svishnuvardhan .jumbo_max_len = 10240, 3900b83f1527SRafal Ozieblo }; 3901b83f1527SRafal Ozieblo 3902b83f1527SRafal Ozieblo static const struct macb_config sama5d4_config = { 3903b83f1527SRafal Ozieblo .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, 3904b83f1527SRafal Ozieblo .dma_burst_length = 4, 3905b83f1527SRafal Ozieblo .clk_init = macb_clk_init, 3906b83f1527SRafal Ozieblo .init = macb_init, 3907b83f1527SRafal Ozieblo }; 3908b83f1527SRafal Ozieblo 3909b83f1527SRafal Ozieblo static const struct macb_config emac_config = { 3910b83f1527SRafal Ozieblo .clk_init = at91ether_clk_init, 3911b83f1527SRafal Ozieblo .init = at91ether_init, 3912b83f1527SRafal Ozieblo }; 3913b83f1527SRafal Ozieblo 3914b83f1527SRafal Ozieblo static const struct macb_config np4_config = { 3915b83f1527SRafal Ozieblo .caps = MACB_CAPS_USRIO_DISABLED, 3916b83f1527SRafal Ozieblo .clk_init = macb_clk_init, 3917b83f1527SRafal Ozieblo .init = macb_init, 3918b83f1527SRafal Ozieblo }; 3919b83f1527SRafal Ozieblo 3920b83f1527SRafal Ozieblo static const struct macb_config zynqmp_config = { 3921ab91f0a9SRafal Ozieblo .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | 3922ab91f0a9SRafal Ozieblo MACB_CAPS_JUMBO | 3923404cd086SHarini Katakam MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH, 3924b83f1527SRafal Ozieblo .dma_burst_length = 16, 3925b83f1527SRafal Ozieblo .clk_init = macb_clk_init, 3926b83f1527SRafal Ozieblo .init = macb_init, 3927b83f1527SRafal Ozieblo .jumbo_max_len = 10240, 3928b83f1527SRafal Ozieblo }; 3929b83f1527SRafal Ozieblo 3930b83f1527SRafal Ozieblo static const struct macb_config zynq_config = { 3931b83f1527SRafal Ozieblo .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF, 3932b83f1527SRafal Ozieblo .dma_burst_length = 16, 3933b83f1527SRafal Ozieblo .clk_init = macb_clk_init, 3934b83f1527SRafal Ozieblo .init = macb_init, 3935b83f1527SRafal Ozieblo }; 3936b83f1527SRafal Ozieblo 3937b83f1527SRafal Ozieblo static const struct of_device_id macb_dt_ids[] = { 3938b83f1527SRafal Ozieblo { .compatible = "cdns,at32ap7000-macb" }, 3939b83f1527SRafal Ozieblo { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, 3940b83f1527SRafal Ozieblo { .compatible = "cdns,macb" }, 3941b83f1527SRafal Ozieblo { .compatible = "cdns,np4-macb", .data = &np4_config }, 3942b83f1527SRafal Ozieblo { .compatible = "cdns,pc302-gem", .data = &pc302gem_config }, 3943b83f1527SRafal Ozieblo { .compatible = "cdns,gem", .data = &pc302gem_config }, 3944b83f1527SRafal Ozieblo { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config }, 3945b83f1527SRafal Ozieblo { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config }, 3946eb4ed8e2SNicolas Ferre { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config }, 3947b83f1527SRafal Ozieblo { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config }, 3948b83f1527SRafal Ozieblo { .compatible = "cdns,at91rm9200-emac", .data = &emac_config }, 3949b83f1527SRafal Ozieblo { .compatible = "cdns,emac", .data = &emac_config }, 3950b83f1527SRafal Ozieblo { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, 3951b83f1527SRafal Ozieblo { .compatible = "cdns,zynq-gem", .data = &zynq_config }, 3952b83f1527SRafal Ozieblo { /* sentinel */ } 3953b83f1527SRafal Ozieblo }; 3954b83f1527SRafal Ozieblo MODULE_DEVICE_TABLE(of, macb_dt_ids); 3955b83f1527SRafal Ozieblo #endif /* CONFIG_OF */ 3956b83f1527SRafal Ozieblo 3957b83f1527SRafal Ozieblo static const struct macb_config default_gem_config = { 3958ab91f0a9SRafal Ozieblo .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | 3959ab91f0a9SRafal Ozieblo MACB_CAPS_JUMBO | 3960ab91f0a9SRafal Ozieblo MACB_CAPS_GEM_HAS_PTP, 3961b83f1527SRafal Ozieblo .dma_burst_length = 16, 3962b83f1527SRafal Ozieblo .clk_init = macb_clk_init, 3963b83f1527SRafal Ozieblo .init = macb_init, 3964b83f1527SRafal Ozieblo .jumbo_max_len = 10240, 3965b83f1527SRafal Ozieblo }; 3966b83f1527SRafal Ozieblo 3967b83f1527SRafal Ozieblo static int macb_probe(struct platform_device *pdev) 3968b83f1527SRafal Ozieblo { 3969b83f1527SRafal Ozieblo const struct macb_config *macb_config = &default_gem_config; 3970b83f1527SRafal Ozieblo int (*clk_init)(struct platform_device *, struct clk **, 3971b83f1527SRafal Ozieblo struct clk **, struct clk **, struct clk **) 3972b83f1527SRafal Ozieblo = macb_config->clk_init; 3973b83f1527SRafal Ozieblo int (*init)(struct platform_device *) = macb_config->init; 3974b83f1527SRafal Ozieblo struct device_node *np = pdev->dev.of_node; 3975b83f1527SRafal Ozieblo struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL; 3976b83f1527SRafal Ozieblo unsigned int queue_mask, num_queues; 3977b83f1527SRafal Ozieblo struct macb_platform_data *pdata; 3978b83f1527SRafal Ozieblo bool native_io; 3979b83f1527SRafal Ozieblo struct phy_device *phydev; 3980b83f1527SRafal Ozieblo struct net_device *dev; 3981b83f1527SRafal Ozieblo struct resource *regs; 3982b83f1527SRafal Ozieblo void __iomem *mem; 3983b83f1527SRafal Ozieblo const char *mac; 3984b83f1527SRafal Ozieblo struct macb *bp; 3985404cd086SHarini Katakam int err, val; 3986b83f1527SRafal Ozieblo 3987b83f1527SRafal Ozieblo regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3988b83f1527SRafal Ozieblo mem = devm_ioremap_resource(&pdev->dev, regs); 3989b83f1527SRafal Ozieblo if (IS_ERR(mem)) 3990b83f1527SRafal Ozieblo return PTR_ERR(mem); 3991b83f1527SRafal Ozieblo 3992b83f1527SRafal Ozieblo if (np) { 3993b83f1527SRafal Ozieblo const struct of_device_id *match; 3994b83f1527SRafal Ozieblo 3995b83f1527SRafal Ozieblo match = of_match_node(macb_dt_ids, np); 3996b83f1527SRafal Ozieblo if (match && match->data) { 3997b83f1527SRafal Ozieblo macb_config = match->data; 3998b83f1527SRafal Ozieblo clk_init = macb_config->clk_init; 3999b83f1527SRafal Ozieblo init = macb_config->init; 4000b83f1527SRafal Ozieblo } 4001b83f1527SRafal Ozieblo } 4002b83f1527SRafal Ozieblo 4003b83f1527SRafal Ozieblo err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk); 4004b83f1527SRafal Ozieblo if (err) 4005b83f1527SRafal Ozieblo return err; 4006b83f1527SRafal Ozieblo 4007b83f1527SRafal Ozieblo native_io = hw_is_native_io(mem); 4008b83f1527SRafal Ozieblo 4009b83f1527SRafal Ozieblo macb_probe_queues(mem, native_io, &queue_mask, &num_queues); 4010b83f1527SRafal Ozieblo dev = alloc_etherdev_mq(sizeof(*bp), num_queues); 4011b83f1527SRafal Ozieblo if (!dev) { 4012b83f1527SRafal Ozieblo err = -ENOMEM; 4013b83f1527SRafal Ozieblo goto err_disable_clocks; 4014b83f1527SRafal Ozieblo } 4015b83f1527SRafal Ozieblo 4016b83f1527SRafal Ozieblo dev->base_addr = regs->start; 4017b83f1527SRafal Ozieblo 4018b83f1527SRafal Ozieblo SET_NETDEV_DEV(dev, &pdev->dev); 4019b83f1527SRafal Ozieblo 4020b83f1527SRafal Ozieblo bp = netdev_priv(dev); 4021b83f1527SRafal Ozieblo bp->pdev = pdev; 4022b83f1527SRafal Ozieblo bp->dev = dev; 4023b83f1527SRafal Ozieblo bp->regs = mem; 4024b83f1527SRafal Ozieblo bp->native_io = native_io; 4025b83f1527SRafal Ozieblo if (native_io) { 4026b83f1527SRafal Ozieblo bp->macb_reg_readl = hw_readl_native; 4027b83f1527SRafal Ozieblo bp->macb_reg_writel = hw_writel_native; 4028b83f1527SRafal Ozieblo } else { 4029b83f1527SRafal Ozieblo bp->macb_reg_readl = hw_readl; 4030b83f1527SRafal Ozieblo bp->macb_reg_writel = hw_writel; 4031b83f1527SRafal Ozieblo } 4032b83f1527SRafal Ozieblo bp->num_queues = num_queues; 4033b83f1527SRafal Ozieblo bp->queue_mask = queue_mask; 4034b83f1527SRafal Ozieblo if (macb_config) 4035b83f1527SRafal Ozieblo bp->dma_burst_length = macb_config->dma_burst_length; 4036b83f1527SRafal Ozieblo bp->pclk = pclk; 4037b83f1527SRafal Ozieblo bp->hclk = hclk; 4038b83f1527SRafal Ozieblo bp->tx_clk = tx_clk; 4039b83f1527SRafal Ozieblo bp->rx_clk = rx_clk; 4040b83f1527SRafal Ozieblo if (macb_config) 4041b83f1527SRafal Ozieblo bp->jumbo_max_len = macb_config->jumbo_max_len; 4042b83f1527SRafal Ozieblo 4043b83f1527SRafal Ozieblo bp->wol = 0; 4044b83f1527SRafal Ozieblo if (of_get_property(np, "magic-packet", NULL)) 4045b83f1527SRafal Ozieblo bp->wol |= MACB_WOL_HAS_MAGIC_PACKET; 4046b83f1527SRafal Ozieblo device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET); 4047b83f1527SRafal Ozieblo 4048b83f1527SRafal Ozieblo spin_lock_init(&bp->lock); 4049b83f1527SRafal Ozieblo 4050b83f1527SRafal Ozieblo /* setup capabilities */ 4051b83f1527SRafal Ozieblo macb_configure_caps(bp, macb_config); 4052b83f1527SRafal Ozieblo 4053b83f1527SRafal Ozieblo #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 4054b83f1527SRafal Ozieblo if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) { 4055b83f1527SRafal Ozieblo dma_set_mask(&pdev->dev, DMA_BIT_MASK(44)); 4056b83f1527SRafal Ozieblo bp->hw_dma_cap |= HW_DMA_CAP_64B; 4057b83f1527SRafal Ozieblo } 4058b83f1527SRafal Ozieblo #endif 4059b83f1527SRafal Ozieblo platform_set_drvdata(pdev, dev); 4060b83f1527SRafal Ozieblo 4061b83f1527SRafal Ozieblo dev->irq = platform_get_irq(pdev, 0); 4062b83f1527SRafal Ozieblo if (dev->irq < 0) { 4063b83f1527SRafal Ozieblo err = dev->irq; 4064b83f1527SRafal Ozieblo goto err_out_free_netdev; 4065b83f1527SRafal Ozieblo } 4066b83f1527SRafal Ozieblo 4067b83f1527SRafal Ozieblo /* MTU range: 68 - 1500 or 10240 */ 4068b83f1527SRafal Ozieblo dev->min_mtu = GEM_MTU_MIN_SIZE; 4069b83f1527SRafal Ozieblo if (bp->caps & MACB_CAPS_JUMBO) 4070b83f1527SRafal Ozieblo dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN; 4071b83f1527SRafal Ozieblo else 4072b83f1527SRafal Ozieblo dev->max_mtu = ETH_DATA_LEN; 4073b83f1527SRafal Ozieblo 4074404cd086SHarini Katakam if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) { 4075404cd086SHarini Katakam val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10)); 4076404cd086SHarini Katakam if (val) 4077404cd086SHarini Katakam bp->rx_bd_rd_prefetch = (2 << (val - 1)) * 4078404cd086SHarini Katakam macb_dma_desc_get_size(bp); 4079404cd086SHarini Katakam 4080404cd086SHarini Katakam val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10)); 4081404cd086SHarini Katakam if (val) 4082404cd086SHarini Katakam bp->tx_bd_rd_prefetch = (2 << (val - 1)) * 4083404cd086SHarini Katakam macb_dma_desc_get_size(bp); 4084404cd086SHarini Katakam } 4085404cd086SHarini Katakam 4086b83f1527SRafal Ozieblo mac = of_get_mac_address(np); 4087aa076e3dSMike Looijmans if (mac) { 4088b83f1527SRafal Ozieblo ether_addr_copy(bp->dev->dev_addr, mac); 4089aa076e3dSMike Looijmans } else { 4090cce41b8fSBartosz Golaszewski err = nvmem_get_mac_address(&pdev->dev, bp->dev->dev_addr); 4091aa076e3dSMike Looijmans if (err) { 4092aa076e3dSMike Looijmans if (err == -EPROBE_DEFER) 4093aa076e3dSMike Looijmans goto err_out_free_netdev; 4094b83f1527SRafal Ozieblo macb_get_hwaddr(bp); 4095aa076e3dSMike Looijmans } 4096aa076e3dSMike Looijmans } 4097b83f1527SRafal Ozieblo 4098b83f1527SRafal Ozieblo err = of_get_phy_mode(np); 4099b83f1527SRafal Ozieblo if (err < 0) { 4100b83f1527SRafal Ozieblo pdata = dev_get_platdata(&pdev->dev); 4101b83f1527SRafal Ozieblo if (pdata && pdata->is_rmii) 4102b83f1527SRafal Ozieblo bp->phy_interface = PHY_INTERFACE_MODE_RMII; 4103b83f1527SRafal Ozieblo else 4104b83f1527SRafal Ozieblo bp->phy_interface = PHY_INTERFACE_MODE_MII; 4105b83f1527SRafal Ozieblo } else { 4106b83f1527SRafal Ozieblo bp->phy_interface = err; 4107b83f1527SRafal Ozieblo } 4108b83f1527SRafal Ozieblo 4109b83f1527SRafal Ozieblo /* IP specific init */ 4110b83f1527SRafal Ozieblo err = init(pdev); 4111b83f1527SRafal Ozieblo if (err) 4112b83f1527SRafal Ozieblo goto err_out_free_netdev; 4113b83f1527SRafal Ozieblo 4114b83f1527SRafal Ozieblo err = macb_mii_init(bp); 4115b83f1527SRafal Ozieblo if (err) 4116b83f1527SRafal Ozieblo goto err_out_free_netdev; 4117b83f1527SRafal Ozieblo 4118b83f1527SRafal Ozieblo phydev = dev->phydev; 4119b83f1527SRafal Ozieblo 4120b83f1527SRafal Ozieblo netif_carrier_off(dev); 4121b83f1527SRafal Ozieblo 4122b83f1527SRafal Ozieblo err = register_netdev(dev); 4123b83f1527SRafal Ozieblo if (err) { 4124b83f1527SRafal Ozieblo dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); 4125b83f1527SRafal Ozieblo goto err_out_unregister_mdio; 4126b83f1527SRafal Ozieblo } 4127b83f1527SRafal Ozieblo 4128032dc41bSHarini Katakam tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task, 4129032dc41bSHarini Katakam (unsigned long)bp); 4130032dc41bSHarini Katakam 4131b83f1527SRafal Ozieblo phy_attached_info(phydev); 4132b83f1527SRafal Ozieblo 4133b83f1527SRafal Ozieblo netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n", 4134b83f1527SRafal Ozieblo macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID), 4135b83f1527SRafal Ozieblo dev->base_addr, dev->irq, dev->dev_addr); 4136b83f1527SRafal Ozieblo 4137b83f1527SRafal Ozieblo return 0; 4138b83f1527SRafal Ozieblo 4139b83f1527SRafal Ozieblo err_out_unregister_mdio: 4140b83f1527SRafal Ozieblo phy_disconnect(dev->phydev); 4141b83f1527SRafal Ozieblo mdiobus_unregister(bp->mii_bus); 414266ee6a06SMichael Grzeschik of_node_put(bp->phy_node); 41439ce98140SMichael Grzeschik if (np && of_phy_is_fixed_link(np)) 41449ce98140SMichael Grzeschik of_phy_deregister_fixed_link(np); 4145b83f1527SRafal Ozieblo mdiobus_free(bp->mii_bus); 4146b83f1527SRafal Ozieblo 4147b83f1527SRafal Ozieblo err_out_free_netdev: 4148b83f1527SRafal Ozieblo free_netdev(dev); 4149b83f1527SRafal Ozieblo 4150b83f1527SRafal Ozieblo err_disable_clocks: 4151b83f1527SRafal Ozieblo clk_disable_unprepare(tx_clk); 4152b83f1527SRafal Ozieblo clk_disable_unprepare(hclk); 4153b83f1527SRafal Ozieblo clk_disable_unprepare(pclk); 4154b83f1527SRafal Ozieblo clk_disable_unprepare(rx_clk); 4155b83f1527SRafal Ozieblo 4156b83f1527SRafal Ozieblo return err; 4157b83f1527SRafal Ozieblo } 4158b83f1527SRafal Ozieblo 4159b83f1527SRafal Ozieblo static int macb_remove(struct platform_device *pdev) 4160b83f1527SRafal Ozieblo { 4161b83f1527SRafal Ozieblo struct net_device *dev; 4162b83f1527SRafal Ozieblo struct macb *bp; 41639ce98140SMichael Grzeschik struct device_node *np = pdev->dev.of_node; 4164b83f1527SRafal Ozieblo 4165b83f1527SRafal Ozieblo dev = platform_get_drvdata(pdev); 4166b83f1527SRafal Ozieblo 4167b83f1527SRafal Ozieblo if (dev) { 4168b83f1527SRafal Ozieblo bp = netdev_priv(dev); 4169b83f1527SRafal Ozieblo if (dev->phydev) 4170b83f1527SRafal Ozieblo phy_disconnect(dev->phydev); 4171b83f1527SRafal Ozieblo mdiobus_unregister(bp->mii_bus); 41729ce98140SMichael Grzeschik if (np && of_phy_is_fixed_link(np)) 41739ce98140SMichael Grzeschik of_phy_deregister_fixed_link(np); 4174b83f1527SRafal Ozieblo dev->phydev = NULL; 4175b83f1527SRafal Ozieblo mdiobus_free(bp->mii_bus); 4176b83f1527SRafal Ozieblo 4177b83f1527SRafal Ozieblo unregister_netdev(dev); 4178b83f1527SRafal Ozieblo clk_disable_unprepare(bp->tx_clk); 4179b83f1527SRafal Ozieblo clk_disable_unprepare(bp->hclk); 4180b83f1527SRafal Ozieblo clk_disable_unprepare(bp->pclk); 4181b83f1527SRafal Ozieblo clk_disable_unprepare(bp->rx_clk); 4182b83f1527SRafal Ozieblo of_node_put(bp->phy_node); 4183b83f1527SRafal Ozieblo free_netdev(dev); 4184b83f1527SRafal Ozieblo } 4185b83f1527SRafal Ozieblo 4186b83f1527SRafal Ozieblo return 0; 4187b83f1527SRafal Ozieblo } 4188b83f1527SRafal Ozieblo 4189b83f1527SRafal Ozieblo static int __maybe_unused macb_suspend(struct device *dev) 4190b83f1527SRafal Ozieblo { 4191ce886a47SWolfram Sang struct net_device *netdev = dev_get_drvdata(dev); 4192b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev); 4193b83f1527SRafal Ozieblo 4194b83f1527SRafal Ozieblo netif_carrier_off(netdev); 4195b83f1527SRafal Ozieblo netif_device_detach(netdev); 4196b83f1527SRafal Ozieblo 4197b83f1527SRafal Ozieblo if (bp->wol & MACB_WOL_ENABLED) { 4198b83f1527SRafal Ozieblo macb_writel(bp, IER, MACB_BIT(WOL)); 4199b83f1527SRafal Ozieblo macb_writel(bp, WOL, MACB_BIT(MAG)); 4200b83f1527SRafal Ozieblo enable_irq_wake(bp->queues[0].irq); 4201b83f1527SRafal Ozieblo } else { 4202b83f1527SRafal Ozieblo clk_disable_unprepare(bp->tx_clk); 4203b83f1527SRafal Ozieblo clk_disable_unprepare(bp->hclk); 4204b83f1527SRafal Ozieblo clk_disable_unprepare(bp->pclk); 4205b83f1527SRafal Ozieblo clk_disable_unprepare(bp->rx_clk); 4206b83f1527SRafal Ozieblo } 4207b83f1527SRafal Ozieblo 4208b83f1527SRafal Ozieblo return 0; 4209b83f1527SRafal Ozieblo } 4210b83f1527SRafal Ozieblo 4211b83f1527SRafal Ozieblo static int __maybe_unused macb_resume(struct device *dev) 4212b83f1527SRafal Ozieblo { 4213ce886a47SWolfram Sang struct net_device *netdev = dev_get_drvdata(dev); 4214b83f1527SRafal Ozieblo struct macb *bp = netdev_priv(netdev); 4215b83f1527SRafal Ozieblo 4216b83f1527SRafal Ozieblo if (bp->wol & MACB_WOL_ENABLED) { 4217b83f1527SRafal Ozieblo macb_writel(bp, IDR, MACB_BIT(WOL)); 4218b83f1527SRafal Ozieblo macb_writel(bp, WOL, 0); 4219b83f1527SRafal Ozieblo disable_irq_wake(bp->queues[0].irq); 4220b83f1527SRafal Ozieblo } else { 4221b83f1527SRafal Ozieblo clk_prepare_enable(bp->pclk); 4222b83f1527SRafal Ozieblo clk_prepare_enable(bp->hclk); 4223b83f1527SRafal Ozieblo clk_prepare_enable(bp->tx_clk); 4224b83f1527SRafal Ozieblo clk_prepare_enable(bp->rx_clk); 4225b83f1527SRafal Ozieblo } 4226b83f1527SRafal Ozieblo 4227b83f1527SRafal Ozieblo netif_device_attach(netdev); 4228b83f1527SRafal Ozieblo 4229b83f1527SRafal Ozieblo return 0; 4230b83f1527SRafal Ozieblo } 4231b83f1527SRafal Ozieblo 4232b83f1527SRafal Ozieblo static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume); 4233b83f1527SRafal Ozieblo 4234b83f1527SRafal Ozieblo static struct platform_driver macb_driver = { 4235b83f1527SRafal Ozieblo .probe = macb_probe, 4236b83f1527SRafal Ozieblo .remove = macb_remove, 4237b83f1527SRafal Ozieblo .driver = { 4238b83f1527SRafal Ozieblo .name = "macb", 4239b83f1527SRafal Ozieblo .of_match_table = of_match_ptr(macb_dt_ids), 4240b83f1527SRafal Ozieblo .pm = &macb_pm_ops, 4241b83f1527SRafal Ozieblo }, 4242b83f1527SRafal Ozieblo }; 4243b83f1527SRafal Ozieblo 4244b83f1527SRafal Ozieblo module_platform_driver(macb_driver); 4245b83f1527SRafal Ozieblo 4246b83f1527SRafal Ozieblo MODULE_LICENSE("GPL"); 4247b83f1527SRafal Ozieblo MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); 4248b83f1527SRafal Ozieblo MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 4249b83f1527SRafal Ozieblo MODULE_ALIAS("platform:macb"); 4250