1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4ce100b8bSAnish Bhatt * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __T4_HW_H 36f7917c00SJeff Kirsher #define __T4_HW_H 37f7917c00SJeff Kirsher 38f7917c00SJeff Kirsher #include <linux/types.h> 39f7917c00SJeff Kirsher 40f7917c00SJeff Kirsher enum { 41f7917c00SJeff Kirsher NCHAN = 4, /* # of HW channels */ 42f7917c00SJeff Kirsher MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ 43f7917c00SJeff Kirsher EEPROMSIZE = 17408,/* Serial EEPROM physical size */ 44f7917c00SJeff Kirsher EEPROMVSIZE = 32768,/* Serial EEPROM virtual address space size */ 45f7917c00SJeff Kirsher EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 46f7917c00SJeff Kirsher RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ 47f988008aSGanesh Goudar T6_RSS_NENTRIES = 4096, /* # of entries in RSS mapping table */ 48f7917c00SJeff Kirsher TCB_SIZE = 128, /* TCB size */ 49f7917c00SJeff Kirsher NMTUS = 16, /* size of MTU table */ 50f7917c00SJeff Kirsher NCCTRL_WIN = 32, /* # of congestion control windows */ 5108c4901bSRahul Lakkireddy NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 52b3bbe36aSHariprasad Shenai PM_NSTATS = 5, /* # of PM stats */ 5344588560SHariprasad Shenai T6_PM_NSTATS = 7, /* # of PM stats in T6 */ 54f7917c00SJeff Kirsher MBOX_LEN = 64, /* mailbox size in bytes */ 55f7917c00SJeff Kirsher TRACE_LEN = 112, /* length of trace data and mask */ 56f7917c00SJeff Kirsher FILTER_OPT_LEN = 36, /* filter tuple width for optional components */ 57f7917c00SJeff Kirsher }; 58f7917c00SJeff Kirsher 59f7917c00SJeff Kirsher enum { 6074b3092cSHariprasad Shenai CIM_NUM_IBQ = 6, /* # of CIM IBQs */ 6174b3092cSHariprasad Shenai CIM_NUM_OBQ = 6, /* # of CIM OBQs */ 6274b3092cSHariprasad Shenai CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ 63f1ff24aaSHariprasad Shenai CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ 6419689609SHariprasad Shenai CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ 6526fae93fSHariprasad Shenai CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ 66e5f0e43bSHariprasad Shenai CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ 67c778af7dSHariprasad Shenai CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ 682d277b3bSHariprasad Shenai TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ 69797ff0f5SHariprasad Shenai ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ 70f1ff24aaSHariprasad Shenai }; 71f1ff24aaSHariprasad Shenai 729e5c598cSRahul Lakkireddy /* SGE context types */ 739e5c598cSRahul Lakkireddy enum ctxt_type { 74736c3b94SRahul Lakkireddy CTXT_EGRESS, 75736c3b94SRahul Lakkireddy CTXT_INGRESS, 76736c3b94SRahul Lakkireddy CTXT_FLM, 779e5c598cSRahul Lakkireddy CTXT_CNM, 789e5c598cSRahul Lakkireddy }; 799e5c598cSRahul Lakkireddy 80f1ff24aaSHariprasad Shenai enum { 81f7917c00SJeff Kirsher SF_PAGE_SIZE = 256, /* serial flash page size */ 825afc8b84SVipul Pandya SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 83f7917c00SJeff Kirsher }; 84f7917c00SJeff Kirsher 85f7917c00SJeff Kirsher enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ 86f7917c00SJeff Kirsher 87f7917c00SJeff Kirsher enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ 88f7917c00SJeff Kirsher 89f7917c00SJeff Kirsher enum { 90f7917c00SJeff Kirsher SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 919e5c598cSRahul Lakkireddy SGE_CTXT_SIZE = 24, /* size of SGE context */ 92f7917c00SJeff Kirsher SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 93f7917c00SJeff Kirsher SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 94d429005fSVishal Kulkarni SGE_NDBQTIMERS = 8, /* # of Doorbell Queue Timer values */ 95cf38be6dSHariprasad Shenai SGE_MAX_IQ_SIZE = 65520, 96f7917c00SJeff Kirsher 97f7917c00SJeff Kirsher SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */ 98f7917c00SJeff Kirsher SGE_TIMER_UPD_CIDX = 7, /* update cidx only */ 99f7917c00SJeff Kirsher 100f7917c00SJeff Kirsher SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */ 101f7917c00SJeff Kirsher 102f7917c00SJeff Kirsher SGE_INTRDST_PCI = 0, /* interrupt destination is PCI-E */ 103f7917c00SJeff Kirsher SGE_INTRDST_IQ = 1, /* destination is an ingress queue */ 104f7917c00SJeff Kirsher 105f7917c00SJeff Kirsher SGE_UPDATEDEL_NONE = 0, /* ingress queue pidx update delivery */ 106f7917c00SJeff Kirsher SGE_UPDATEDEL_INTR = 1, /* interrupt */ 107f7917c00SJeff Kirsher SGE_UPDATEDEL_STPG = 2, /* status page */ 108f7917c00SJeff Kirsher SGE_UPDATEDEL_BOTH = 3, /* interrupt and status page */ 109f7917c00SJeff Kirsher 110f7917c00SJeff Kirsher SGE_HOSTFCMODE_NONE = 0, /* egress queue cidx updates */ 111f7917c00SJeff Kirsher SGE_HOSTFCMODE_IQ = 1, /* sent to ingress queue */ 112f7917c00SJeff Kirsher SGE_HOSTFCMODE_STPG = 2, /* sent to status page */ 113f7917c00SJeff Kirsher SGE_HOSTFCMODE_BOTH = 3, /* ingress queue and status page */ 114f7917c00SJeff Kirsher 115f7917c00SJeff Kirsher SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */ 116f7917c00SJeff Kirsher SGE_FETCHBURSTMIN_32B = 1, 117f7917c00SJeff Kirsher SGE_FETCHBURSTMIN_64B = 2, 118f7917c00SJeff Kirsher SGE_FETCHBURSTMIN_128B = 3, 119f7917c00SJeff Kirsher 120f7917c00SJeff Kirsher SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */ 121f7917c00SJeff Kirsher SGE_FETCHBURSTMAX_128B = 1, 122f7917c00SJeff Kirsher SGE_FETCHBURSTMAX_256B = 2, 123f7917c00SJeff Kirsher SGE_FETCHBURSTMAX_512B = 3, 124f7917c00SJeff Kirsher 125f7917c00SJeff Kirsher SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */ 126f7917c00SJeff Kirsher SGE_CIDXFLUSHTHRESH_2 = 1, 127f7917c00SJeff Kirsher SGE_CIDXFLUSHTHRESH_4 = 2, 128f7917c00SJeff Kirsher SGE_CIDXFLUSHTHRESH_8 = 3, 129f7917c00SJeff Kirsher SGE_CIDXFLUSHTHRESH_16 = 4, 130f7917c00SJeff Kirsher SGE_CIDXFLUSHTHRESH_32 = 5, 131f7917c00SJeff Kirsher SGE_CIDXFLUSHTHRESH_64 = 6, 132f7917c00SJeff Kirsher SGE_CIDXFLUSHTHRESH_128 = 7, 133f7917c00SJeff Kirsher 134f7917c00SJeff Kirsher SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */ 135f7917c00SJeff Kirsher }; 136f7917c00SJeff Kirsher 13749aa284fSHariprasad Shenai /* PCI-e memory window access */ 13849aa284fSHariprasad Shenai enum pcie_memwin { 13949aa284fSHariprasad Shenai MEMWIN_NIC = 0, 14049aa284fSHariprasad Shenai MEMWIN_RSVD1 = 1, 14149aa284fSHariprasad Shenai MEMWIN_RSVD2 = 2, 14249aa284fSHariprasad Shenai MEMWIN_RDMA = 3, 14349aa284fSHariprasad Shenai MEMWIN_RSVD4 = 4, 14449aa284fSHariprasad Shenai MEMWIN_FOISCSI = 5, 14549aa284fSHariprasad Shenai MEMWIN_CSIOSTOR = 6, 14649aa284fSHariprasad Shenai MEMWIN_RSVD7 = 7, 14749aa284fSHariprasad Shenai }; 14849aa284fSHariprasad Shenai 149f7917c00SJeff Kirsher struct sge_qstat { /* data written to SGE queue status entries */ 150f7917c00SJeff Kirsher __be32 qid; 151f7917c00SJeff Kirsher __be16 cidx; 152f7917c00SJeff Kirsher __be16 pidx; 153f7917c00SJeff Kirsher }; 154f7917c00SJeff Kirsher 155f7917c00SJeff Kirsher /* 156f7917c00SJeff Kirsher * Structure for last 128 bits of response descriptors 157f7917c00SJeff Kirsher */ 158f7917c00SJeff Kirsher struct rsp_ctrl { 159f7917c00SJeff Kirsher __be32 hdrbuflen_pidx; 160f7917c00SJeff Kirsher __be32 pldbuflen_qid; 161f7917c00SJeff Kirsher union { 162f7917c00SJeff Kirsher u8 type_gen; 163f7917c00SJeff Kirsher __be64 last_flit; 164f7917c00SJeff Kirsher }; 165f7917c00SJeff Kirsher }; 166f7917c00SJeff Kirsher 1671ecc7b7aSHariprasad Shenai #define RSPD_NEWBUF_S 31 1681ecc7b7aSHariprasad Shenai #define RSPD_NEWBUF_V(x) ((x) << RSPD_NEWBUF_S) 1691ecc7b7aSHariprasad Shenai #define RSPD_NEWBUF_F RSPD_NEWBUF_V(1U) 170f7917c00SJeff Kirsher 1711ecc7b7aSHariprasad Shenai #define RSPD_LEN_S 0 1721ecc7b7aSHariprasad Shenai #define RSPD_LEN_M 0x7fffffff 1731ecc7b7aSHariprasad Shenai #define RSPD_LEN_G(x) (((x) >> RSPD_LEN_S) & RSPD_LEN_M) 174f7917c00SJeff Kirsher 1751ecc7b7aSHariprasad Shenai #define RSPD_QID_S RSPD_LEN_S 1761ecc7b7aSHariprasad Shenai #define RSPD_QID_M RSPD_LEN_M 1771ecc7b7aSHariprasad Shenai #define RSPD_QID_G(x) RSPD_LEN_G(x) 1781ecc7b7aSHariprasad Shenai 1791ecc7b7aSHariprasad Shenai #define RSPD_GEN_S 7 1801ecc7b7aSHariprasad Shenai 1811ecc7b7aSHariprasad Shenai #define RSPD_TYPE_S 4 1821ecc7b7aSHariprasad Shenai #define RSPD_TYPE_M 0x3 1831ecc7b7aSHariprasad Shenai #define RSPD_TYPE_G(x) (((x) >> RSPD_TYPE_S) & RSPD_TYPE_M) 1841ecc7b7aSHariprasad Shenai 1851ecc7b7aSHariprasad Shenai /* Rx queue interrupt deferral fields: counter enable and timer index */ 1861ecc7b7aSHariprasad Shenai #define QINTR_CNT_EN_S 0 1871ecc7b7aSHariprasad Shenai #define QINTR_CNT_EN_V(x) ((x) << QINTR_CNT_EN_S) 1881ecc7b7aSHariprasad Shenai #define QINTR_CNT_EN_F QINTR_CNT_EN_V(1U) 1891ecc7b7aSHariprasad Shenai 1901ecc7b7aSHariprasad Shenai #define QINTR_TIMER_IDX_S 1 1911ecc7b7aSHariprasad Shenai #define QINTR_TIMER_IDX_M 0x7 1921ecc7b7aSHariprasad Shenai #define QINTR_TIMER_IDX_V(x) ((x) << QINTR_TIMER_IDX_S) 1931ecc7b7aSHariprasad Shenai #define QINTR_TIMER_IDX_G(x) (((x) >> QINTR_TIMER_IDX_S) & QINTR_TIMER_IDX_M) 1945afc8b84SVipul Pandya 1955afc8b84SVipul Pandya /* 1965afc8b84SVipul Pandya * Flash layout. 1975afc8b84SVipul Pandya */ 1985afc8b84SVipul Pandya #define FLASH_START(start) ((start) * SF_SEC_SIZE) 1995afc8b84SVipul Pandya #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 2005afc8b84SVipul Pandya 2015afc8b84SVipul Pandya enum { 2025afc8b84SVipul Pandya /* 2035afc8b84SVipul Pandya * Various Expansion-ROM boot images, etc. 2045afc8b84SVipul Pandya */ 2055afc8b84SVipul Pandya FLASH_EXP_ROM_START_SEC = 0, 2065afc8b84SVipul Pandya FLASH_EXP_ROM_NSECS = 6, 2075afc8b84SVipul Pandya FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), 2085afc8b84SVipul Pandya FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), 2095afc8b84SVipul Pandya 2105afc8b84SVipul Pandya /* 2115afc8b84SVipul Pandya * iSCSI Boot Firmware Table (iBFT) and other driver-related 2125afc8b84SVipul Pandya * parameters ... 2135afc8b84SVipul Pandya */ 2145afc8b84SVipul Pandya FLASH_IBFT_START_SEC = 6, 2155afc8b84SVipul Pandya FLASH_IBFT_NSECS = 1, 2165afc8b84SVipul Pandya FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC), 2175afc8b84SVipul Pandya FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS), 2185afc8b84SVipul Pandya 2195afc8b84SVipul Pandya /* 2205afc8b84SVipul Pandya * Boot configuration data. 2215afc8b84SVipul Pandya */ 2225afc8b84SVipul Pandya FLASH_BOOTCFG_START_SEC = 7, 2235afc8b84SVipul Pandya FLASH_BOOTCFG_NSECS = 1, 2245afc8b84SVipul Pandya FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC), 2255afc8b84SVipul Pandya FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS), 2265afc8b84SVipul Pandya 2275afc8b84SVipul Pandya /* 2285afc8b84SVipul Pandya * Location of firmware image in FLASH. 2295afc8b84SVipul Pandya */ 2305afc8b84SVipul Pandya FLASH_FW_START_SEC = 8, 23160d42bf6SHariprasad Shenai FLASH_FW_NSECS = 16, 2325afc8b84SVipul Pandya FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), 2335afc8b84SVipul Pandya FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), 2345afc8b84SVipul Pandya 2350de72738SHariprasad Shenai /* Location of bootstrap firmware image in FLASH. 2360de72738SHariprasad Shenai */ 2370de72738SHariprasad Shenai FLASH_FWBOOTSTRAP_START_SEC = 27, 2380de72738SHariprasad Shenai FLASH_FWBOOTSTRAP_NSECS = 1, 2390de72738SHariprasad Shenai FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC), 2400de72738SHariprasad Shenai FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS), 2410de72738SHariprasad Shenai 2425afc8b84SVipul Pandya /* 2435afc8b84SVipul Pandya * iSCSI persistent/crash information. 2445afc8b84SVipul Pandya */ 2455afc8b84SVipul Pandya FLASH_ISCSI_CRASH_START_SEC = 29, 2465afc8b84SVipul Pandya FLASH_ISCSI_CRASH_NSECS = 1, 2475afc8b84SVipul Pandya FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC), 2485afc8b84SVipul Pandya FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS), 2495afc8b84SVipul Pandya 2505afc8b84SVipul Pandya /* 2515afc8b84SVipul Pandya * FCoE persistent/crash information. 2525afc8b84SVipul Pandya */ 2535afc8b84SVipul Pandya FLASH_FCOE_CRASH_START_SEC = 30, 2545afc8b84SVipul Pandya FLASH_FCOE_CRASH_NSECS = 1, 2555afc8b84SVipul Pandya FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC), 2565afc8b84SVipul Pandya FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS), 2575afc8b84SVipul Pandya 2585afc8b84SVipul Pandya /* 2595afc8b84SVipul Pandya * Location of Firmware Configuration File in FLASH. Since the FPGA 2605afc8b84SVipul Pandya * "FLASH" is smaller we need to store the Configuration File in a 2615afc8b84SVipul Pandya * different location -- which will overlap the end of the firmware 2625afc8b84SVipul Pandya * image if firmware ever gets that large ... 2635afc8b84SVipul Pandya */ 2645afc8b84SVipul Pandya FLASH_CFG_START_SEC = 31, 2655afc8b84SVipul Pandya FLASH_CFG_NSECS = 1, 2665afc8b84SVipul Pandya FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), 2675afc8b84SVipul Pandya FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), 2685afc8b84SVipul Pandya 269c290607eSHariprasad Shenai /* We don't support FLASH devices which can't support the full 270c290607eSHariprasad Shenai * standard set of sections which we need for normal 271c290607eSHariprasad Shenai * operations. 272c290607eSHariprasad Shenai */ 273c290607eSHariprasad Shenai FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE, 274c290607eSHariprasad Shenai 2755afc8b84SVipul Pandya FLASH_FPGA_CFG_START_SEC = 15, 2765afc8b84SVipul Pandya FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC), 2775afc8b84SVipul Pandya 2785afc8b84SVipul Pandya /* 2795afc8b84SVipul Pandya * Sectors 32-63 are reserved for FLASH failover. 2805afc8b84SVipul Pandya */ 2815afc8b84SVipul Pandya }; 2825afc8b84SVipul Pandya 2835afc8b84SVipul Pandya #undef FLASH_START 2845afc8b84SVipul Pandya #undef FLASH_MAX_SIZE 2855afc8b84SVipul Pandya 2865e2a5ebcSHariprasad Shenai #define SGE_TIMESTAMP_S 0 2875e2a5ebcSHariprasad Shenai #define SGE_TIMESTAMP_M 0xfffffffffffffffULL 2885e2a5ebcSHariprasad Shenai #define SGE_TIMESTAMP_V(x) ((__u64)(x) << SGE_TIMESTAMP_S) 2895e2a5ebcSHariprasad Shenai #define SGE_TIMESTAMP_G(x) (((__u64)(x) >> SGE_TIMESTAMP_S) & SGE_TIMESTAMP_M) 2905e2a5ebcSHariprasad Shenai 291f56ec676SArjun Vynipadath #define I2C_DEV_ADDR_A0 0xa0 292f56ec676SArjun Vynipadath #define I2C_DEV_ADDR_A2 0xa2 293f56ec676SArjun Vynipadath #define I2C_PAGE_SIZE 0x100 294f56ec676SArjun Vynipadath #define SFP_DIAG_TYPE_ADDR 0x5c 295f56ec676SArjun Vynipadath #define SFP_DIAG_TYPE_LEN 0x1 296*4ca110bfSRahul Lakkireddy #define SFP_DIAG_ADDRMODE BIT(2) 297*4ca110bfSRahul Lakkireddy #define SFP_DIAG_IMPLEMENTED BIT(6) 298f56ec676SArjun Vynipadath #define SFF_8472_COMP_ADDR 0x5e 299f56ec676SArjun Vynipadath #define SFF_8472_COMP_LEN 0x1 300f56ec676SArjun Vynipadath #define SFF_REV_ADDR 0x1 301f56ec676SArjun Vynipadath #define SFF_REV_LEN 0x1 302f56ec676SArjun Vynipadath 303f7917c00SJeff Kirsher #endif /* __T4_HW_H */ 304