1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */ 3 /* 4 Copyright (c) 2001, 2002 by D-Link Corporation 5 Written by Edward Peng.<edward_peng@dlink.com.tw> 6 Created 03-May-2001, base on Linux' sundance.c. 7 8 */ 9 10 #define DRV_NAME "DL2000/TC902x-based linux driver" 11 #define DRV_VERSION "v1.19" 12 #define DRV_RELDATE "2007/08/12" 13 #include "dl2k.h" 14 #include <linux/dma-mapping.h> 15 16 #define dw32(reg, val) iowrite32(val, ioaddr + (reg)) 17 #define dw16(reg, val) iowrite16(val, ioaddr + (reg)) 18 #define dw8(reg, val) iowrite8(val, ioaddr + (reg)) 19 #define dr32(reg) ioread32(ioaddr + (reg)) 20 #define dr16(reg) ioread16(ioaddr + (reg)) 21 #define dr8(reg) ioread8(ioaddr + (reg)) 22 23 static char version[] = 24 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n"; 25 #define MAX_UNITS 8 26 static int mtu[MAX_UNITS]; 27 static int vlan[MAX_UNITS]; 28 static int jumbo[MAX_UNITS]; 29 static char *media[MAX_UNITS]; 30 static int tx_flow=-1; 31 static int rx_flow=-1; 32 static int copy_thresh; 33 static int rx_coalesce=10; /* Rx frame count each interrupt */ 34 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */ 35 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */ 36 37 38 MODULE_AUTHOR ("Edward Peng"); 39 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter"); 40 MODULE_LICENSE("GPL"); 41 module_param_array(mtu, int, NULL, 0); 42 module_param_array(media, charp, NULL, 0); 43 module_param_array(vlan, int, NULL, 0); 44 module_param_array(jumbo, int, NULL, 0); 45 module_param(tx_flow, int, 0); 46 module_param(rx_flow, int, 0); 47 module_param(copy_thresh, int, 0); 48 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */ 49 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */ 50 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */ 51 52 53 /* Enable the default interrupts */ 54 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \ 55 UpdateStats | LinkEvent) 56 57 static void dl2k_enable_int(struct netdev_private *np) 58 { 59 void __iomem *ioaddr = np->ioaddr; 60 61 dw16(IntEnable, DEFAULT_INTR); 62 } 63 64 static const int max_intrloop = 50; 65 static const int multicast_filter_limit = 0x40; 66 67 static int rio_open (struct net_device *dev); 68 static void rio_timer (struct timer_list *t); 69 static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue); 70 static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev); 71 static irqreturn_t rio_interrupt (int irq, void *dev_instance); 72 static void rio_free_tx (struct net_device *dev, int irq); 73 static void tx_error (struct net_device *dev, int tx_status); 74 static int receive_packet (struct net_device *dev); 75 static void rio_error (struct net_device *dev, int int_status); 76 static void set_multicast (struct net_device *dev); 77 static struct net_device_stats *get_stats (struct net_device *dev); 78 static int clear_stats (struct net_device *dev); 79 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 80 static int rio_close (struct net_device *dev); 81 static int find_miiphy (struct net_device *dev); 82 static int parse_eeprom (struct net_device *dev); 83 static int read_eeprom (struct netdev_private *, int eep_addr); 84 static int mii_wait_link (struct net_device *dev, int wait); 85 static int mii_set_media (struct net_device *dev); 86 static int mii_get_media (struct net_device *dev); 87 static int mii_set_media_pcs (struct net_device *dev); 88 static int mii_get_media_pcs (struct net_device *dev); 89 static int mii_read (struct net_device *dev, int phy_addr, int reg_num); 90 static int mii_write (struct net_device *dev, int phy_addr, int reg_num, 91 u16 data); 92 93 static const struct ethtool_ops ethtool_ops; 94 95 static const struct net_device_ops netdev_ops = { 96 .ndo_open = rio_open, 97 .ndo_start_xmit = start_xmit, 98 .ndo_stop = rio_close, 99 .ndo_get_stats = get_stats, 100 .ndo_validate_addr = eth_validate_addr, 101 .ndo_set_mac_address = eth_mac_addr, 102 .ndo_set_rx_mode = set_multicast, 103 .ndo_do_ioctl = rio_ioctl, 104 .ndo_tx_timeout = rio_tx_timeout, 105 }; 106 107 static int 108 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent) 109 { 110 struct net_device *dev; 111 struct netdev_private *np; 112 static int card_idx; 113 int chip_idx = ent->driver_data; 114 int err, irq; 115 void __iomem *ioaddr; 116 static int version_printed; 117 void *ring_space; 118 dma_addr_t ring_dma; 119 120 if (!version_printed++) 121 printk ("%s", version); 122 123 err = pci_enable_device (pdev); 124 if (err) 125 return err; 126 127 irq = pdev->irq; 128 err = pci_request_regions (pdev, "dl2k"); 129 if (err) 130 goto err_out_disable; 131 132 pci_set_master (pdev); 133 134 err = -ENOMEM; 135 136 dev = alloc_etherdev (sizeof (*np)); 137 if (!dev) 138 goto err_out_res; 139 SET_NETDEV_DEV(dev, &pdev->dev); 140 141 np = netdev_priv(dev); 142 143 /* IO registers range. */ 144 ioaddr = pci_iomap(pdev, 0, 0); 145 if (!ioaddr) 146 goto err_out_dev; 147 np->eeprom_addr = ioaddr; 148 149 #ifdef MEM_MAPPING 150 /* MM registers range. */ 151 ioaddr = pci_iomap(pdev, 1, 0); 152 if (!ioaddr) 153 goto err_out_iounmap; 154 #endif 155 np->ioaddr = ioaddr; 156 np->chip_id = chip_idx; 157 np->pdev = pdev; 158 spin_lock_init (&np->tx_lock); 159 spin_lock_init (&np->rx_lock); 160 161 /* Parse manual configuration */ 162 np->an_enable = 1; 163 np->tx_coalesce = 1; 164 if (card_idx < MAX_UNITS) { 165 if (media[card_idx] != NULL) { 166 np->an_enable = 0; 167 if (strcmp (media[card_idx], "auto") == 0 || 168 strcmp (media[card_idx], "autosense") == 0 || 169 strcmp (media[card_idx], "0") == 0 ) { 170 np->an_enable = 2; 171 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 || 172 strcmp (media[card_idx], "4") == 0) { 173 np->speed = 100; 174 np->full_duplex = 1; 175 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 || 176 strcmp (media[card_idx], "3") == 0) { 177 np->speed = 100; 178 np->full_duplex = 0; 179 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 || 180 strcmp (media[card_idx], "2") == 0) { 181 np->speed = 10; 182 np->full_duplex = 1; 183 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 || 184 strcmp (media[card_idx], "1") == 0) { 185 np->speed = 10; 186 np->full_duplex = 0; 187 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 || 188 strcmp (media[card_idx], "6") == 0) { 189 np->speed=1000; 190 np->full_duplex=1; 191 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 || 192 strcmp (media[card_idx], "5") == 0) { 193 np->speed = 1000; 194 np->full_duplex = 0; 195 } else { 196 np->an_enable = 1; 197 } 198 } 199 if (jumbo[card_idx] != 0) { 200 np->jumbo = 1; 201 dev->mtu = MAX_JUMBO; 202 } else { 203 np->jumbo = 0; 204 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE) 205 dev->mtu = mtu[card_idx]; 206 } 207 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ? 208 vlan[card_idx] : 0; 209 if (rx_coalesce > 0 && rx_timeout > 0) { 210 np->rx_coalesce = rx_coalesce; 211 np->rx_timeout = rx_timeout; 212 np->coalesce = 1; 213 } 214 np->tx_flow = (tx_flow == 0) ? 0 : 1; 215 np->rx_flow = (rx_flow == 0) ? 0 : 1; 216 217 if (tx_coalesce < 1) 218 tx_coalesce = 1; 219 else if (tx_coalesce > TX_RING_SIZE-1) 220 tx_coalesce = TX_RING_SIZE - 1; 221 } 222 dev->netdev_ops = &netdev_ops; 223 dev->watchdog_timeo = TX_TIMEOUT; 224 dev->ethtool_ops = ðtool_ops; 225 #if 0 226 dev->features = NETIF_F_IP_CSUM; 227 #endif 228 /* MTU range: 68 - 1536 or 8000 */ 229 dev->min_mtu = ETH_MIN_MTU; 230 dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE; 231 232 pci_set_drvdata (pdev, dev); 233 234 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma); 235 if (!ring_space) 236 goto err_out_iounmap; 237 np->tx_ring = ring_space; 238 np->tx_ring_dma = ring_dma; 239 240 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma); 241 if (!ring_space) 242 goto err_out_unmap_tx; 243 np->rx_ring = ring_space; 244 np->rx_ring_dma = ring_dma; 245 246 /* Parse eeprom data */ 247 parse_eeprom (dev); 248 249 /* Find PHY address */ 250 err = find_miiphy (dev); 251 if (err) 252 goto err_out_unmap_rx; 253 254 /* Fiber device? */ 255 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0; 256 np->link_status = 0; 257 /* Set media and reset PHY */ 258 if (np->phy_media) { 259 /* default Auto-Negotiation for fiber deivices */ 260 if (np->an_enable == 2) { 261 np->an_enable = 1; 262 } 263 } else { 264 /* Auto-Negotiation is mandatory for 1000BASE-T, 265 IEEE 802.3ab Annex 28D page 14 */ 266 if (np->speed == 1000) 267 np->an_enable = 1; 268 } 269 270 err = register_netdev (dev); 271 if (err) 272 goto err_out_unmap_rx; 273 274 card_idx++; 275 276 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n", 277 dev->name, np->name, dev->dev_addr, irq); 278 if (tx_coalesce > 1) 279 printk(KERN_INFO "tx_coalesce:\t%d packets\n", 280 tx_coalesce); 281 if (np->coalesce) 282 printk(KERN_INFO 283 "rx_coalesce:\t%d packets\n" 284 "rx_timeout: \t%d ns\n", 285 np->rx_coalesce, np->rx_timeout*640); 286 if (np->vlan) 287 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan); 288 return 0; 289 290 err_out_unmap_rx: 291 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma); 292 err_out_unmap_tx: 293 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma); 294 err_out_iounmap: 295 #ifdef MEM_MAPPING 296 pci_iounmap(pdev, np->ioaddr); 297 #endif 298 pci_iounmap(pdev, np->eeprom_addr); 299 err_out_dev: 300 free_netdev (dev); 301 err_out_res: 302 pci_release_regions (pdev); 303 err_out_disable: 304 pci_disable_device (pdev); 305 return err; 306 } 307 308 static int 309 find_miiphy (struct net_device *dev) 310 { 311 struct netdev_private *np = netdev_priv(dev); 312 int i, phy_found = 0; 313 314 np->phy_addr = 1; 315 316 for (i = 31; i >= 0; i--) { 317 int mii_status = mii_read (dev, i, 1); 318 if (mii_status != 0xffff && mii_status != 0x0000) { 319 np->phy_addr = i; 320 phy_found++; 321 } 322 } 323 if (!phy_found) { 324 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name); 325 return -ENODEV; 326 } 327 return 0; 328 } 329 330 static int 331 parse_eeprom (struct net_device *dev) 332 { 333 struct netdev_private *np = netdev_priv(dev); 334 void __iomem *ioaddr = np->ioaddr; 335 int i, j; 336 u8 sromdata[256]; 337 u8 *psib; 338 u32 crc; 339 PSROM_t psrom = (PSROM_t) sromdata; 340 341 int cid, next; 342 343 for (i = 0; i < 128; i++) 344 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i)); 345 346 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */ 347 /* Check CRC */ 348 crc = ~ether_crc_le (256 - 4, sromdata); 349 if (psrom->crc != cpu_to_le32(crc)) { 350 printk (KERN_ERR "%s: EEPROM data CRC error.\n", 351 dev->name); 352 return -1; 353 } 354 } 355 356 /* Set MAC address */ 357 for (i = 0; i < 6; i++) 358 dev->dev_addr[i] = psrom->mac_addr[i]; 359 360 if (np->chip_id == CHIP_IP1000A) { 361 np->led_mode = psrom->led_mode; 362 return 0; 363 } 364 365 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) { 366 return 0; 367 } 368 369 /* Parse Software Information Block */ 370 i = 0x30; 371 psib = (u8 *) sromdata; 372 do { 373 cid = psib[i++]; 374 next = psib[i++]; 375 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) { 376 printk (KERN_ERR "Cell data error\n"); 377 return -1; 378 } 379 switch (cid) { 380 case 0: /* Format version */ 381 break; 382 case 1: /* End of cell */ 383 return 0; 384 case 2: /* Duplex Polarity */ 385 np->duplex_polarity = psib[i]; 386 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]); 387 break; 388 case 3: /* Wake Polarity */ 389 np->wake_polarity = psib[i]; 390 break; 391 case 9: /* Adapter description */ 392 j = (next - i > 255) ? 255 : next - i; 393 memcpy (np->name, &(psib[i]), j); 394 break; 395 case 4: 396 case 5: 397 case 6: 398 case 7: 399 case 8: /* Reversed */ 400 break; 401 default: /* Unknown cell */ 402 return -1; 403 } 404 i = next; 405 } while (1); 406 407 return 0; 408 } 409 410 static void rio_set_led_mode(struct net_device *dev) 411 { 412 struct netdev_private *np = netdev_priv(dev); 413 void __iomem *ioaddr = np->ioaddr; 414 u32 mode; 415 416 if (np->chip_id != CHIP_IP1000A) 417 return; 418 419 mode = dr32(ASICCtrl); 420 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED); 421 422 if (np->led_mode & 0x01) 423 mode |= IPG_AC_LED_MODE; 424 if (np->led_mode & 0x02) 425 mode |= IPG_AC_LED_MODE_BIT_1; 426 if (np->led_mode & 0x08) 427 mode |= IPG_AC_LED_SPEED; 428 429 dw32(ASICCtrl, mode); 430 } 431 432 static inline dma_addr_t desc_to_dma(struct netdev_desc *desc) 433 { 434 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48); 435 } 436 437 static void free_list(struct net_device *dev) 438 { 439 struct netdev_private *np = netdev_priv(dev); 440 struct sk_buff *skb; 441 int i; 442 443 /* Free all the skbuffs in the queue. */ 444 for (i = 0; i < RX_RING_SIZE; i++) { 445 skb = np->rx_skbuff[i]; 446 if (skb) { 447 pci_unmap_single(np->pdev, desc_to_dma(&np->rx_ring[i]), 448 skb->len, PCI_DMA_FROMDEVICE); 449 dev_kfree_skb(skb); 450 np->rx_skbuff[i] = NULL; 451 } 452 np->rx_ring[i].status = 0; 453 np->rx_ring[i].fraginfo = 0; 454 } 455 for (i = 0; i < TX_RING_SIZE; i++) { 456 skb = np->tx_skbuff[i]; 457 if (skb) { 458 pci_unmap_single(np->pdev, desc_to_dma(&np->tx_ring[i]), 459 skb->len, PCI_DMA_TODEVICE); 460 dev_kfree_skb(skb); 461 np->tx_skbuff[i] = NULL; 462 } 463 } 464 } 465 466 static void rio_reset_ring(struct netdev_private *np) 467 { 468 int i; 469 470 np->cur_rx = 0; 471 np->cur_tx = 0; 472 np->old_rx = 0; 473 np->old_tx = 0; 474 475 for (i = 0; i < TX_RING_SIZE; i++) 476 np->tx_ring[i].status = cpu_to_le64(TFDDone); 477 478 for (i = 0; i < RX_RING_SIZE; i++) 479 np->rx_ring[i].status = 0; 480 } 481 482 /* allocate and initialize Tx and Rx descriptors */ 483 static int alloc_list(struct net_device *dev) 484 { 485 struct netdev_private *np = netdev_priv(dev); 486 int i; 487 488 rio_reset_ring(np); 489 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32); 490 491 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */ 492 for (i = 0; i < TX_RING_SIZE; i++) { 493 np->tx_skbuff[i] = NULL; 494 np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma + 495 ((i + 1) % TX_RING_SIZE) * 496 sizeof(struct netdev_desc)); 497 } 498 499 /* Initialize Rx descriptors & allocate buffers */ 500 for (i = 0; i < RX_RING_SIZE; i++) { 501 /* Allocated fixed size of skbuff */ 502 struct sk_buff *skb; 503 504 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); 505 np->rx_skbuff[i] = skb; 506 if (!skb) { 507 free_list(dev); 508 return -ENOMEM; 509 } 510 511 np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma + 512 ((i + 1) % RX_RING_SIZE) * 513 sizeof(struct netdev_desc)); 514 /* Rubicon now supports 40 bits of addressing space. */ 515 np->rx_ring[i].fraginfo = 516 cpu_to_le64(pci_map_single( 517 np->pdev, skb->data, np->rx_buf_sz, 518 PCI_DMA_FROMDEVICE)); 519 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48); 520 } 521 522 return 0; 523 } 524 525 static void rio_hw_init(struct net_device *dev) 526 { 527 struct netdev_private *np = netdev_priv(dev); 528 void __iomem *ioaddr = np->ioaddr; 529 int i; 530 u16 macctrl; 531 532 /* Reset all logic functions */ 533 dw16(ASICCtrl + 2, 534 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset); 535 mdelay(10); 536 537 rio_set_led_mode(dev); 538 539 /* DebugCtrl bit 4, 5, 9 must set */ 540 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230); 541 542 if (np->chip_id == CHIP_IP1000A && 543 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) { 544 /* PHY magic taken from ipg driver, undocumented registers */ 545 mii_write(dev, np->phy_addr, 31, 0x0001); 546 mii_write(dev, np->phy_addr, 27, 0x01e0); 547 mii_write(dev, np->phy_addr, 31, 0x0002); 548 mii_write(dev, np->phy_addr, 27, 0xeb8e); 549 mii_write(dev, np->phy_addr, 31, 0x0000); 550 mii_write(dev, np->phy_addr, 30, 0x005e); 551 /* advertise 1000BASE-T half & full duplex, prefer MASTER */ 552 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700); 553 } 554 555 if (np->phy_media) 556 mii_set_media_pcs(dev); 557 else 558 mii_set_media(dev); 559 560 /* Jumbo frame */ 561 if (np->jumbo != 0) 562 dw16(MaxFrameSize, MAX_JUMBO+14); 563 564 /* Set RFDListPtr */ 565 dw32(RFDListPtr0, np->rx_ring_dma); 566 dw32(RFDListPtr1, 0); 567 568 /* Set station address */ 569 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works 570 * too. However, it doesn't work on IP1000A so we use 16-bit access. 571 */ 572 for (i = 0; i < 3; i++) 573 dw16(StationAddr0 + 2 * i, 574 cpu_to_le16(((u16 *)dev->dev_addr)[i])); 575 576 set_multicast (dev); 577 if (np->coalesce) { 578 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16); 579 } 580 /* Set RIO to poll every N*320nsec. */ 581 dw8(RxDMAPollPeriod, 0x20); 582 dw8(TxDMAPollPeriod, 0xff); 583 dw8(RxDMABurstThresh, 0x30); 584 dw8(RxDMAUrgentThresh, 0x30); 585 dw32(RmonStatMask, 0x0007ffff); 586 /* clear statistics */ 587 clear_stats (dev); 588 589 /* VLAN supported */ 590 if (np->vlan) { 591 /* priority field in RxDMAIntCtrl */ 592 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10); 593 /* VLANId */ 594 dw16(VLANId, np->vlan); 595 /* Length/Type should be 0x8100 */ 596 dw32(VLANTag, 0x8100 << 16 | np->vlan); 597 /* Enable AutoVLANuntagging, but disable AutoVLANtagging. 598 VLAN information tagged by TFC' VID, CFI fields. */ 599 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging); 600 } 601 602 /* Start Tx/Rx */ 603 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable); 604 605 macctrl = 0; 606 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; 607 macctrl |= (np->full_duplex) ? DuplexSelect : 0; 608 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0; 609 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0; 610 dw16(MACCtrl, macctrl); 611 } 612 613 static void rio_hw_stop(struct net_device *dev) 614 { 615 struct netdev_private *np = netdev_priv(dev); 616 void __iomem *ioaddr = np->ioaddr; 617 618 /* Disable interrupts */ 619 dw16(IntEnable, 0); 620 621 /* Stop Tx and Rx logics */ 622 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable); 623 } 624 625 static int rio_open(struct net_device *dev) 626 { 627 struct netdev_private *np = netdev_priv(dev); 628 const int irq = np->pdev->irq; 629 int i; 630 631 i = alloc_list(dev); 632 if (i) 633 return i; 634 635 rio_hw_init(dev); 636 637 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev); 638 if (i) { 639 rio_hw_stop(dev); 640 free_list(dev); 641 return i; 642 } 643 644 timer_setup(&np->timer, rio_timer, 0); 645 np->timer.expires = jiffies + 1 * HZ; 646 add_timer(&np->timer); 647 648 netif_start_queue (dev); 649 650 dl2k_enable_int(np); 651 return 0; 652 } 653 654 static void 655 rio_timer (struct timer_list *t) 656 { 657 struct netdev_private *np = from_timer(np, t, timer); 658 struct net_device *dev = pci_get_drvdata(np->pdev); 659 unsigned int entry; 660 int next_tick = 1*HZ; 661 unsigned long flags; 662 663 spin_lock_irqsave(&np->rx_lock, flags); 664 /* Recover rx ring exhausted error */ 665 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) { 666 printk(KERN_INFO "Try to recover rx ring exhausted...\n"); 667 /* Re-allocate skbuffs to fill the descriptor ring */ 668 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) { 669 struct sk_buff *skb; 670 entry = np->old_rx % RX_RING_SIZE; 671 /* Dropped packets don't need to re-allocate */ 672 if (np->rx_skbuff[entry] == NULL) { 673 skb = netdev_alloc_skb_ip_align(dev, 674 np->rx_buf_sz); 675 if (skb == NULL) { 676 np->rx_ring[entry].fraginfo = 0; 677 printk (KERN_INFO 678 "%s: Still unable to re-allocate Rx skbuff.#%d\n", 679 dev->name, entry); 680 break; 681 } 682 np->rx_skbuff[entry] = skb; 683 np->rx_ring[entry].fraginfo = 684 cpu_to_le64 (pci_map_single 685 (np->pdev, skb->data, np->rx_buf_sz, 686 PCI_DMA_FROMDEVICE)); 687 } 688 np->rx_ring[entry].fraginfo |= 689 cpu_to_le64((u64)np->rx_buf_sz << 48); 690 np->rx_ring[entry].status = 0; 691 } /* end for */ 692 } /* end if */ 693 spin_unlock_irqrestore (&np->rx_lock, flags); 694 np->timer.expires = jiffies + next_tick; 695 add_timer(&np->timer); 696 } 697 698 static void 699 rio_tx_timeout (struct net_device *dev, unsigned int txqueue) 700 { 701 struct netdev_private *np = netdev_priv(dev); 702 void __iomem *ioaddr = np->ioaddr; 703 704 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n", 705 dev->name, dr32(TxStatus)); 706 rio_free_tx(dev, 0); 707 dev->if_port = 0; 708 netif_trans_update(dev); /* prevent tx timeout */ 709 } 710 711 static netdev_tx_t 712 start_xmit (struct sk_buff *skb, struct net_device *dev) 713 { 714 struct netdev_private *np = netdev_priv(dev); 715 void __iomem *ioaddr = np->ioaddr; 716 struct netdev_desc *txdesc; 717 unsigned entry; 718 u64 tfc_vlan_tag = 0; 719 720 if (np->link_status == 0) { /* Link Down */ 721 dev_kfree_skb(skb); 722 return NETDEV_TX_OK; 723 } 724 entry = np->cur_tx % TX_RING_SIZE; 725 np->tx_skbuff[entry] = skb; 726 txdesc = &np->tx_ring[entry]; 727 728 #if 0 729 if (skb->ip_summed == CHECKSUM_PARTIAL) { 730 txdesc->status |= 731 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable | 732 IPChecksumEnable); 733 } 734 #endif 735 if (np->vlan) { 736 tfc_vlan_tag = VLANTagInsert | 737 ((u64)np->vlan << 32) | 738 ((u64)skb->priority << 45); 739 } 740 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data, 741 skb->len, 742 PCI_DMA_TODEVICE)); 743 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48); 744 745 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode 746 * Work around: Always use 1 descriptor in 10Mbps mode */ 747 if (entry % np->tx_coalesce == 0 || np->speed == 10) 748 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag | 749 WordAlignDisable | 750 TxDMAIndicate | 751 (1 << FragCountShift)); 752 else 753 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag | 754 WordAlignDisable | 755 (1 << FragCountShift)); 756 757 /* TxDMAPollNow */ 758 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000); 759 /* Schedule ISR */ 760 dw32(CountDown, 10000); 761 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE; 762 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE 763 < TX_QUEUE_LEN - 1 && np->speed != 10) { 764 /* do nothing */ 765 } else if (!netif_queue_stopped(dev)) { 766 netif_stop_queue (dev); 767 } 768 769 /* The first TFDListPtr */ 770 if (!dr32(TFDListPtr0)) { 771 dw32(TFDListPtr0, np->tx_ring_dma + 772 entry * sizeof (struct netdev_desc)); 773 dw32(TFDListPtr1, 0); 774 } 775 776 return NETDEV_TX_OK; 777 } 778 779 static irqreturn_t 780 rio_interrupt (int irq, void *dev_instance) 781 { 782 struct net_device *dev = dev_instance; 783 struct netdev_private *np = netdev_priv(dev); 784 void __iomem *ioaddr = np->ioaddr; 785 unsigned int_status; 786 int cnt = max_intrloop; 787 int handled = 0; 788 789 while (1) { 790 int_status = dr16(IntStatus); 791 dw16(IntStatus, int_status); 792 int_status &= DEFAULT_INTR; 793 if (int_status == 0 || --cnt < 0) 794 break; 795 handled = 1; 796 /* Processing received packets */ 797 if (int_status & RxDMAComplete) 798 receive_packet (dev); 799 /* TxDMAComplete interrupt */ 800 if ((int_status & (TxDMAComplete|IntRequested))) { 801 int tx_status; 802 tx_status = dr32(TxStatus); 803 if (tx_status & 0x01) 804 tx_error (dev, tx_status); 805 /* Free used tx skbuffs */ 806 rio_free_tx (dev, 1); 807 } 808 809 /* Handle uncommon events */ 810 if (int_status & 811 (HostError | LinkEvent | UpdateStats)) 812 rio_error (dev, int_status); 813 } 814 if (np->cur_tx != np->old_tx) 815 dw32(CountDown, 100); 816 return IRQ_RETVAL(handled); 817 } 818 819 static void 820 rio_free_tx (struct net_device *dev, int irq) 821 { 822 struct netdev_private *np = netdev_priv(dev); 823 int entry = np->old_tx % TX_RING_SIZE; 824 int tx_use = 0; 825 unsigned long flag = 0; 826 827 if (irq) 828 spin_lock(&np->tx_lock); 829 else 830 spin_lock_irqsave(&np->tx_lock, flag); 831 832 /* Free used tx skbuffs */ 833 while (entry != np->cur_tx) { 834 struct sk_buff *skb; 835 836 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone))) 837 break; 838 skb = np->tx_skbuff[entry]; 839 pci_unmap_single (np->pdev, 840 desc_to_dma(&np->tx_ring[entry]), 841 skb->len, PCI_DMA_TODEVICE); 842 if (irq) 843 dev_consume_skb_irq(skb); 844 else 845 dev_kfree_skb(skb); 846 847 np->tx_skbuff[entry] = NULL; 848 entry = (entry + 1) % TX_RING_SIZE; 849 tx_use++; 850 } 851 if (irq) 852 spin_unlock(&np->tx_lock); 853 else 854 spin_unlock_irqrestore(&np->tx_lock, flag); 855 np->old_tx = entry; 856 857 /* If the ring is no longer full, clear tx_full and 858 call netif_wake_queue() */ 859 860 if (netif_queue_stopped(dev) && 861 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE 862 < TX_QUEUE_LEN - 1 || np->speed == 10)) { 863 netif_wake_queue (dev); 864 } 865 } 866 867 static void 868 tx_error (struct net_device *dev, int tx_status) 869 { 870 struct netdev_private *np = netdev_priv(dev); 871 void __iomem *ioaddr = np->ioaddr; 872 int frame_id; 873 int i; 874 875 frame_id = (tx_status & 0xffff0000); 876 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n", 877 dev->name, tx_status, frame_id); 878 dev->stats.tx_errors++; 879 /* Ttransmit Underrun */ 880 if (tx_status & 0x10) { 881 dev->stats.tx_fifo_errors++; 882 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10); 883 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */ 884 dw16(ASICCtrl + 2, 885 TxReset | DMAReset | FIFOReset | NetworkReset); 886 /* Wait for ResetBusy bit clear */ 887 for (i = 50; i > 0; i--) { 888 if (!(dr16(ASICCtrl + 2) & ResetBusy)) 889 break; 890 mdelay (1); 891 } 892 rio_set_led_mode(dev); 893 rio_free_tx (dev, 1); 894 /* Reset TFDListPtr */ 895 dw32(TFDListPtr0, np->tx_ring_dma + 896 np->old_tx * sizeof (struct netdev_desc)); 897 dw32(TFDListPtr1, 0); 898 899 /* Let TxStartThresh stay default value */ 900 } 901 /* Late Collision */ 902 if (tx_status & 0x04) { 903 dev->stats.tx_fifo_errors++; 904 /* TxReset and clear FIFO */ 905 dw16(ASICCtrl + 2, TxReset | FIFOReset); 906 /* Wait reset done */ 907 for (i = 50; i > 0; i--) { 908 if (!(dr16(ASICCtrl + 2) & ResetBusy)) 909 break; 910 mdelay (1); 911 } 912 rio_set_led_mode(dev); 913 /* Let TxStartThresh stay default value */ 914 } 915 /* Maximum Collisions */ 916 if (tx_status & 0x08) 917 dev->stats.collisions++; 918 /* Restart the Tx */ 919 dw32(MACCtrl, dr16(MACCtrl) | TxEnable); 920 } 921 922 static int 923 receive_packet (struct net_device *dev) 924 { 925 struct netdev_private *np = netdev_priv(dev); 926 int entry = np->cur_rx % RX_RING_SIZE; 927 int cnt = 30; 928 929 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */ 930 while (1) { 931 struct netdev_desc *desc = &np->rx_ring[entry]; 932 int pkt_len; 933 u64 frame_status; 934 935 if (!(desc->status & cpu_to_le64(RFDDone)) || 936 !(desc->status & cpu_to_le64(FrameStart)) || 937 !(desc->status & cpu_to_le64(FrameEnd))) 938 break; 939 940 /* Chip omits the CRC. */ 941 frame_status = le64_to_cpu(desc->status); 942 pkt_len = frame_status & 0xffff; 943 if (--cnt < 0) 944 break; 945 /* Update rx error statistics, drop packet. */ 946 if (frame_status & RFS_Errors) { 947 dev->stats.rx_errors++; 948 if (frame_status & (RxRuntFrame | RxLengthError)) 949 dev->stats.rx_length_errors++; 950 if (frame_status & RxFCSError) 951 dev->stats.rx_crc_errors++; 952 if (frame_status & RxAlignmentError && np->speed != 1000) 953 dev->stats.rx_frame_errors++; 954 if (frame_status & RxFIFOOverrun) 955 dev->stats.rx_fifo_errors++; 956 } else { 957 struct sk_buff *skb; 958 959 /* Small skbuffs for short packets */ 960 if (pkt_len > copy_thresh) { 961 pci_unmap_single (np->pdev, 962 desc_to_dma(desc), 963 np->rx_buf_sz, 964 PCI_DMA_FROMDEVICE); 965 skb_put (skb = np->rx_skbuff[entry], pkt_len); 966 np->rx_skbuff[entry] = NULL; 967 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) { 968 pci_dma_sync_single_for_cpu(np->pdev, 969 desc_to_dma(desc), 970 np->rx_buf_sz, 971 PCI_DMA_FROMDEVICE); 972 skb_copy_to_linear_data (skb, 973 np->rx_skbuff[entry]->data, 974 pkt_len); 975 skb_put (skb, pkt_len); 976 pci_dma_sync_single_for_device(np->pdev, 977 desc_to_dma(desc), 978 np->rx_buf_sz, 979 PCI_DMA_FROMDEVICE); 980 } 981 skb->protocol = eth_type_trans (skb, dev); 982 #if 0 983 /* Checksum done by hw, but csum value unavailable. */ 984 if (np->pdev->pci_rev_id >= 0x0c && 985 !(frame_status & (TCPError | UDPError | IPError))) { 986 skb->ip_summed = CHECKSUM_UNNECESSARY; 987 } 988 #endif 989 netif_rx (skb); 990 } 991 entry = (entry + 1) % RX_RING_SIZE; 992 } 993 spin_lock(&np->rx_lock); 994 np->cur_rx = entry; 995 /* Re-allocate skbuffs to fill the descriptor ring */ 996 entry = np->old_rx; 997 while (entry != np->cur_rx) { 998 struct sk_buff *skb; 999 /* Dropped packets don't need to re-allocate */ 1000 if (np->rx_skbuff[entry] == NULL) { 1001 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); 1002 if (skb == NULL) { 1003 np->rx_ring[entry].fraginfo = 0; 1004 printk (KERN_INFO 1005 "%s: receive_packet: " 1006 "Unable to re-allocate Rx skbuff.#%d\n", 1007 dev->name, entry); 1008 break; 1009 } 1010 np->rx_skbuff[entry] = skb; 1011 np->rx_ring[entry].fraginfo = 1012 cpu_to_le64 (pci_map_single 1013 (np->pdev, skb->data, np->rx_buf_sz, 1014 PCI_DMA_FROMDEVICE)); 1015 } 1016 np->rx_ring[entry].fraginfo |= 1017 cpu_to_le64((u64)np->rx_buf_sz << 48); 1018 np->rx_ring[entry].status = 0; 1019 entry = (entry + 1) % RX_RING_SIZE; 1020 } 1021 np->old_rx = entry; 1022 spin_unlock(&np->rx_lock); 1023 return 0; 1024 } 1025 1026 static void 1027 rio_error (struct net_device *dev, int int_status) 1028 { 1029 struct netdev_private *np = netdev_priv(dev); 1030 void __iomem *ioaddr = np->ioaddr; 1031 u16 macctrl; 1032 1033 /* Link change event */ 1034 if (int_status & LinkEvent) { 1035 if (mii_wait_link (dev, 10) == 0) { 1036 printk (KERN_INFO "%s: Link up\n", dev->name); 1037 if (np->phy_media) 1038 mii_get_media_pcs (dev); 1039 else 1040 mii_get_media (dev); 1041 if (np->speed == 1000) 1042 np->tx_coalesce = tx_coalesce; 1043 else 1044 np->tx_coalesce = 1; 1045 macctrl = 0; 1046 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; 1047 macctrl |= (np->full_duplex) ? DuplexSelect : 0; 1048 macctrl |= (np->tx_flow) ? 1049 TxFlowControlEnable : 0; 1050 macctrl |= (np->rx_flow) ? 1051 RxFlowControlEnable : 0; 1052 dw16(MACCtrl, macctrl); 1053 np->link_status = 1; 1054 netif_carrier_on(dev); 1055 } else { 1056 printk (KERN_INFO "%s: Link off\n", dev->name); 1057 np->link_status = 0; 1058 netif_carrier_off(dev); 1059 } 1060 } 1061 1062 /* UpdateStats statistics registers */ 1063 if (int_status & UpdateStats) { 1064 get_stats (dev); 1065 } 1066 1067 /* PCI Error, a catastronphic error related to the bus interface 1068 occurs, set GlobalReset and HostReset to reset. */ 1069 if (int_status & HostError) { 1070 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n", 1071 dev->name, int_status); 1072 dw16(ASICCtrl + 2, GlobalReset | HostReset); 1073 mdelay (500); 1074 rio_set_led_mode(dev); 1075 } 1076 } 1077 1078 static struct net_device_stats * 1079 get_stats (struct net_device *dev) 1080 { 1081 struct netdev_private *np = netdev_priv(dev); 1082 void __iomem *ioaddr = np->ioaddr; 1083 #ifdef MEM_MAPPING 1084 int i; 1085 #endif 1086 unsigned int stat_reg; 1087 1088 /* All statistics registers need to be acknowledged, 1089 else statistic overflow could cause problems */ 1090 1091 dev->stats.rx_packets += dr32(FramesRcvOk); 1092 dev->stats.tx_packets += dr32(FramesXmtOk); 1093 dev->stats.rx_bytes += dr32(OctetRcvOk); 1094 dev->stats.tx_bytes += dr32(OctetXmtOk); 1095 1096 dev->stats.multicast = dr32(McstFramesRcvdOk); 1097 dev->stats.collisions += dr32(SingleColFrames) 1098 + dr32(MultiColFrames); 1099 1100 /* detailed tx errors */ 1101 stat_reg = dr16(FramesAbortXSColls); 1102 dev->stats.tx_aborted_errors += stat_reg; 1103 dev->stats.tx_errors += stat_reg; 1104 1105 stat_reg = dr16(CarrierSenseErrors); 1106 dev->stats.tx_carrier_errors += stat_reg; 1107 dev->stats.tx_errors += stat_reg; 1108 1109 /* Clear all other statistic register. */ 1110 dr32(McstOctetXmtOk); 1111 dr16(BcstFramesXmtdOk); 1112 dr32(McstFramesXmtdOk); 1113 dr16(BcstFramesRcvdOk); 1114 dr16(MacControlFramesRcvd); 1115 dr16(FrameTooLongErrors); 1116 dr16(InRangeLengthErrors); 1117 dr16(FramesCheckSeqErrors); 1118 dr16(FramesLostRxErrors); 1119 dr32(McstOctetXmtOk); 1120 dr32(BcstOctetXmtOk); 1121 dr32(McstFramesXmtdOk); 1122 dr32(FramesWDeferredXmt); 1123 dr32(LateCollisions); 1124 dr16(BcstFramesXmtdOk); 1125 dr16(MacControlFramesXmtd); 1126 dr16(FramesWEXDeferal); 1127 1128 #ifdef MEM_MAPPING 1129 for (i = 0x100; i <= 0x150; i += 4) 1130 dr32(i); 1131 #endif 1132 dr16(TxJumboFrames); 1133 dr16(RxJumboFrames); 1134 dr16(TCPCheckSumErrors); 1135 dr16(UDPCheckSumErrors); 1136 dr16(IPCheckSumErrors); 1137 return &dev->stats; 1138 } 1139 1140 static int 1141 clear_stats (struct net_device *dev) 1142 { 1143 struct netdev_private *np = netdev_priv(dev); 1144 void __iomem *ioaddr = np->ioaddr; 1145 #ifdef MEM_MAPPING 1146 int i; 1147 #endif 1148 1149 /* All statistics registers need to be acknowledged, 1150 else statistic overflow could cause problems */ 1151 dr32(FramesRcvOk); 1152 dr32(FramesXmtOk); 1153 dr32(OctetRcvOk); 1154 dr32(OctetXmtOk); 1155 1156 dr32(McstFramesRcvdOk); 1157 dr32(SingleColFrames); 1158 dr32(MultiColFrames); 1159 dr32(LateCollisions); 1160 /* detailed rx errors */ 1161 dr16(FrameTooLongErrors); 1162 dr16(InRangeLengthErrors); 1163 dr16(FramesCheckSeqErrors); 1164 dr16(FramesLostRxErrors); 1165 1166 /* detailed tx errors */ 1167 dr16(FramesAbortXSColls); 1168 dr16(CarrierSenseErrors); 1169 1170 /* Clear all other statistic register. */ 1171 dr32(McstOctetXmtOk); 1172 dr16(BcstFramesXmtdOk); 1173 dr32(McstFramesXmtdOk); 1174 dr16(BcstFramesRcvdOk); 1175 dr16(MacControlFramesRcvd); 1176 dr32(McstOctetXmtOk); 1177 dr32(BcstOctetXmtOk); 1178 dr32(McstFramesXmtdOk); 1179 dr32(FramesWDeferredXmt); 1180 dr16(BcstFramesXmtdOk); 1181 dr16(MacControlFramesXmtd); 1182 dr16(FramesWEXDeferal); 1183 #ifdef MEM_MAPPING 1184 for (i = 0x100; i <= 0x150; i += 4) 1185 dr32(i); 1186 #endif 1187 dr16(TxJumboFrames); 1188 dr16(RxJumboFrames); 1189 dr16(TCPCheckSumErrors); 1190 dr16(UDPCheckSumErrors); 1191 dr16(IPCheckSumErrors); 1192 return 0; 1193 } 1194 1195 static void 1196 set_multicast (struct net_device *dev) 1197 { 1198 struct netdev_private *np = netdev_priv(dev); 1199 void __iomem *ioaddr = np->ioaddr; 1200 u32 hash_table[2]; 1201 u16 rx_mode = 0; 1202 1203 hash_table[0] = hash_table[1] = 0; 1204 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */ 1205 hash_table[1] |= 0x02000000; 1206 if (dev->flags & IFF_PROMISC) { 1207 /* Receive all frames promiscuously. */ 1208 rx_mode = ReceiveAllFrames; 1209 } else if ((dev->flags & IFF_ALLMULTI) || 1210 (netdev_mc_count(dev) > multicast_filter_limit)) { 1211 /* Receive broadcast and multicast frames */ 1212 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast; 1213 } else if (!netdev_mc_empty(dev)) { 1214 struct netdev_hw_addr *ha; 1215 /* Receive broadcast frames and multicast frames filtering 1216 by Hashtable */ 1217 rx_mode = 1218 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast; 1219 netdev_for_each_mc_addr(ha, dev) { 1220 int bit, index = 0; 1221 int crc = ether_crc_le(ETH_ALEN, ha->addr); 1222 /* The inverted high significant 6 bits of CRC are 1223 used as an index to hashtable */ 1224 for (bit = 0; bit < 6; bit++) 1225 if (crc & (1 << (31 - bit))) 1226 index |= (1 << bit); 1227 hash_table[index / 32] |= (1 << (index % 32)); 1228 } 1229 } else { 1230 rx_mode = ReceiveBroadcast | ReceiveUnicast; 1231 } 1232 if (np->vlan) { 1233 /* ReceiveVLANMatch field in ReceiveMode */ 1234 rx_mode |= ReceiveVLANMatch; 1235 } 1236 1237 dw32(HashTable0, hash_table[0]); 1238 dw32(HashTable1, hash_table[1]); 1239 dw16(ReceiveMode, rx_mode); 1240 } 1241 1242 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1243 { 1244 struct netdev_private *np = netdev_priv(dev); 1245 1246 strlcpy(info->driver, "dl2k", sizeof(info->driver)); 1247 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1248 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info)); 1249 } 1250 1251 static int rio_get_link_ksettings(struct net_device *dev, 1252 struct ethtool_link_ksettings *cmd) 1253 { 1254 struct netdev_private *np = netdev_priv(dev); 1255 u32 supported, advertising; 1256 1257 if (np->phy_media) { 1258 /* fiber device */ 1259 supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE; 1260 advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE; 1261 cmd->base.port = PORT_FIBRE; 1262 } else { 1263 /* copper device */ 1264 supported = SUPPORTED_10baseT_Half | 1265 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half 1266 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | 1267 SUPPORTED_Autoneg | SUPPORTED_MII; 1268 advertising = ADVERTISED_10baseT_Half | 1269 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half | 1270 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full | 1271 ADVERTISED_Autoneg | ADVERTISED_MII; 1272 cmd->base.port = PORT_MII; 1273 } 1274 if (np->link_status) { 1275 cmd->base.speed = np->speed; 1276 cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 1277 } else { 1278 cmd->base.speed = SPEED_UNKNOWN; 1279 cmd->base.duplex = DUPLEX_UNKNOWN; 1280 } 1281 if (np->an_enable) 1282 cmd->base.autoneg = AUTONEG_ENABLE; 1283 else 1284 cmd->base.autoneg = AUTONEG_DISABLE; 1285 1286 cmd->base.phy_address = np->phy_addr; 1287 1288 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1289 supported); 1290 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1291 advertising); 1292 1293 return 0; 1294 } 1295 1296 static int rio_set_link_ksettings(struct net_device *dev, 1297 const struct ethtool_link_ksettings *cmd) 1298 { 1299 struct netdev_private *np = netdev_priv(dev); 1300 u32 speed = cmd->base.speed; 1301 u8 duplex = cmd->base.duplex; 1302 1303 netif_carrier_off(dev); 1304 if (cmd->base.autoneg == AUTONEG_ENABLE) { 1305 if (np->an_enable) { 1306 return 0; 1307 } else { 1308 np->an_enable = 1; 1309 mii_set_media(dev); 1310 return 0; 1311 } 1312 } else { 1313 np->an_enable = 0; 1314 if (np->speed == 1000) { 1315 speed = SPEED_100; 1316 duplex = DUPLEX_FULL; 1317 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n"); 1318 } 1319 switch (speed) { 1320 case SPEED_10: 1321 np->speed = 10; 1322 np->full_duplex = (duplex == DUPLEX_FULL); 1323 break; 1324 case SPEED_100: 1325 np->speed = 100; 1326 np->full_duplex = (duplex == DUPLEX_FULL); 1327 break; 1328 case SPEED_1000: /* not supported */ 1329 default: 1330 return -EINVAL; 1331 } 1332 mii_set_media(dev); 1333 } 1334 return 0; 1335 } 1336 1337 static u32 rio_get_link(struct net_device *dev) 1338 { 1339 struct netdev_private *np = netdev_priv(dev); 1340 return np->link_status; 1341 } 1342 1343 static const struct ethtool_ops ethtool_ops = { 1344 .get_drvinfo = rio_get_drvinfo, 1345 .get_link = rio_get_link, 1346 .get_link_ksettings = rio_get_link_ksettings, 1347 .set_link_ksettings = rio_set_link_ksettings, 1348 }; 1349 1350 static int 1351 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) 1352 { 1353 int phy_addr; 1354 struct netdev_private *np = netdev_priv(dev); 1355 struct mii_ioctl_data *miidata = if_mii(rq); 1356 1357 phy_addr = np->phy_addr; 1358 switch (cmd) { 1359 case SIOCGMIIPHY: 1360 miidata->phy_id = phy_addr; 1361 break; 1362 case SIOCGMIIREG: 1363 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num); 1364 break; 1365 case SIOCSMIIREG: 1366 if (!capable(CAP_NET_ADMIN)) 1367 return -EPERM; 1368 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in); 1369 break; 1370 default: 1371 return -EOPNOTSUPP; 1372 } 1373 return 0; 1374 } 1375 1376 #define EEP_READ 0x0200 1377 #define EEP_BUSY 0x8000 1378 /* Read the EEPROM word */ 1379 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */ 1380 static int read_eeprom(struct netdev_private *np, int eep_addr) 1381 { 1382 void __iomem *ioaddr = np->eeprom_addr; 1383 int i = 1000; 1384 1385 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff)); 1386 while (i-- > 0) { 1387 if (!(dr16(EepromCtrl) & EEP_BUSY)) 1388 return dr16(EepromData); 1389 } 1390 return 0; 1391 } 1392 1393 enum phy_ctrl_bits { 1394 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04, 1395 MII_DUPLEX = 0x08, 1396 }; 1397 1398 #define mii_delay() dr8(PhyCtrl) 1399 static void 1400 mii_sendbit (struct net_device *dev, u32 data) 1401 { 1402 struct netdev_private *np = netdev_priv(dev); 1403 void __iomem *ioaddr = np->ioaddr; 1404 1405 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE; 1406 dw8(PhyCtrl, data); 1407 mii_delay (); 1408 dw8(PhyCtrl, data | MII_CLK); 1409 mii_delay (); 1410 } 1411 1412 static int 1413 mii_getbit (struct net_device *dev) 1414 { 1415 struct netdev_private *np = netdev_priv(dev); 1416 void __iomem *ioaddr = np->ioaddr; 1417 u8 data; 1418 1419 data = (dr8(PhyCtrl) & 0xf8) | MII_READ; 1420 dw8(PhyCtrl, data); 1421 mii_delay (); 1422 dw8(PhyCtrl, data | MII_CLK); 1423 mii_delay (); 1424 return (dr8(PhyCtrl) >> 1) & 1; 1425 } 1426 1427 static void 1428 mii_send_bits (struct net_device *dev, u32 data, int len) 1429 { 1430 int i; 1431 1432 for (i = len - 1; i >= 0; i--) { 1433 mii_sendbit (dev, data & (1 << i)); 1434 } 1435 } 1436 1437 static int 1438 mii_read (struct net_device *dev, int phy_addr, int reg_num) 1439 { 1440 u32 cmd; 1441 int i; 1442 u32 retval = 0; 1443 1444 /* Preamble */ 1445 mii_send_bits (dev, 0xffffffff, 32); 1446 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1447 /* ST,OP = 0110'b for read operation */ 1448 cmd = (0x06 << 10 | phy_addr << 5 | reg_num); 1449 mii_send_bits (dev, cmd, 14); 1450 /* Turnaround */ 1451 if (mii_getbit (dev)) 1452 goto err_out; 1453 /* Read data */ 1454 for (i = 0; i < 16; i++) { 1455 retval |= mii_getbit (dev); 1456 retval <<= 1; 1457 } 1458 /* End cycle */ 1459 mii_getbit (dev); 1460 return (retval >> 1) & 0xffff; 1461 1462 err_out: 1463 return 0; 1464 } 1465 static int 1466 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data) 1467 { 1468 u32 cmd; 1469 1470 /* Preamble */ 1471 mii_send_bits (dev, 0xffffffff, 32); 1472 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1473 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ 1474 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data; 1475 mii_send_bits (dev, cmd, 32); 1476 /* End cycle */ 1477 mii_getbit (dev); 1478 return 0; 1479 } 1480 static int 1481 mii_wait_link (struct net_device *dev, int wait) 1482 { 1483 __u16 bmsr; 1484 int phy_addr; 1485 struct netdev_private *np; 1486 1487 np = netdev_priv(dev); 1488 phy_addr = np->phy_addr; 1489 1490 do { 1491 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1492 if (bmsr & BMSR_LSTATUS) 1493 return 0; 1494 mdelay (1); 1495 } while (--wait > 0); 1496 return -1; 1497 } 1498 static int 1499 mii_get_media (struct net_device *dev) 1500 { 1501 __u16 negotiate; 1502 __u16 bmsr; 1503 __u16 mscr; 1504 __u16 mssr; 1505 int phy_addr; 1506 struct netdev_private *np; 1507 1508 np = netdev_priv(dev); 1509 phy_addr = np->phy_addr; 1510 1511 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1512 if (np->an_enable) { 1513 if (!(bmsr & BMSR_ANEGCOMPLETE)) { 1514 /* Auto-Negotiation not completed */ 1515 return -1; 1516 } 1517 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) & 1518 mii_read (dev, phy_addr, MII_LPA); 1519 mscr = mii_read (dev, phy_addr, MII_CTRL1000); 1520 mssr = mii_read (dev, phy_addr, MII_STAT1000); 1521 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) { 1522 np->speed = 1000; 1523 np->full_duplex = 1; 1524 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1525 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) { 1526 np->speed = 1000; 1527 np->full_duplex = 0; 1528 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); 1529 } else if (negotiate & ADVERTISE_100FULL) { 1530 np->speed = 100; 1531 np->full_duplex = 1; 1532 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n"); 1533 } else if (negotiate & ADVERTISE_100HALF) { 1534 np->speed = 100; 1535 np->full_duplex = 0; 1536 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n"); 1537 } else if (negotiate & ADVERTISE_10FULL) { 1538 np->speed = 10; 1539 np->full_duplex = 1; 1540 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n"); 1541 } else if (negotiate & ADVERTISE_10HALF) { 1542 np->speed = 10; 1543 np->full_duplex = 0; 1544 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n"); 1545 } 1546 if (negotiate & ADVERTISE_PAUSE_CAP) { 1547 np->tx_flow &= 1; 1548 np->rx_flow &= 1; 1549 } else if (negotiate & ADVERTISE_PAUSE_ASYM) { 1550 np->tx_flow = 0; 1551 np->rx_flow &= 1; 1552 } 1553 /* else tx_flow, rx_flow = user select */ 1554 } else { 1555 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR); 1556 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) { 1557 case BMCR_SPEED1000: 1558 printk (KERN_INFO "Operating at 1000 Mbps, "); 1559 break; 1560 case BMCR_SPEED100: 1561 printk (KERN_INFO "Operating at 100 Mbps, "); 1562 break; 1563 case 0: 1564 printk (KERN_INFO "Operating at 10 Mbps, "); 1565 } 1566 if (bmcr & BMCR_FULLDPLX) { 1567 printk (KERN_CONT "Full duplex\n"); 1568 } else { 1569 printk (KERN_CONT "Half duplex\n"); 1570 } 1571 } 1572 if (np->tx_flow) 1573 printk(KERN_INFO "Enable Tx Flow Control\n"); 1574 else 1575 printk(KERN_INFO "Disable Tx Flow Control\n"); 1576 if (np->rx_flow) 1577 printk(KERN_INFO "Enable Rx Flow Control\n"); 1578 else 1579 printk(KERN_INFO "Disable Rx Flow Control\n"); 1580 1581 return 0; 1582 } 1583 1584 static int 1585 mii_set_media (struct net_device *dev) 1586 { 1587 __u16 pscr; 1588 __u16 bmcr; 1589 __u16 bmsr; 1590 __u16 anar; 1591 int phy_addr; 1592 struct netdev_private *np; 1593 np = netdev_priv(dev); 1594 phy_addr = np->phy_addr; 1595 1596 /* Does user set speed? */ 1597 if (np->an_enable) { 1598 /* Advertise capabilities */ 1599 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1600 anar = mii_read (dev, phy_addr, MII_ADVERTISE) & 1601 ~(ADVERTISE_100FULL | ADVERTISE_10FULL | 1602 ADVERTISE_100HALF | ADVERTISE_10HALF | 1603 ADVERTISE_100BASE4); 1604 if (bmsr & BMSR_100FULL) 1605 anar |= ADVERTISE_100FULL; 1606 if (bmsr & BMSR_100HALF) 1607 anar |= ADVERTISE_100HALF; 1608 if (bmsr & BMSR_100BASE4) 1609 anar |= ADVERTISE_100BASE4; 1610 if (bmsr & BMSR_10FULL) 1611 anar |= ADVERTISE_10FULL; 1612 if (bmsr & BMSR_10HALF) 1613 anar |= ADVERTISE_10HALF; 1614 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1615 mii_write (dev, phy_addr, MII_ADVERTISE, anar); 1616 1617 /* Enable Auto crossover */ 1618 pscr = mii_read (dev, phy_addr, MII_PHY_SCR); 1619 pscr |= 3 << 5; /* 11'b */ 1620 mii_write (dev, phy_addr, MII_PHY_SCR, pscr); 1621 1622 /* Soft reset PHY */ 1623 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET); 1624 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; 1625 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1626 mdelay(1); 1627 } else { 1628 /* Force speed setting */ 1629 /* 1) Disable Auto crossover */ 1630 pscr = mii_read (dev, phy_addr, MII_PHY_SCR); 1631 pscr &= ~(3 << 5); 1632 mii_write (dev, phy_addr, MII_PHY_SCR, pscr); 1633 1634 /* 2) PHY Reset */ 1635 bmcr = mii_read (dev, phy_addr, MII_BMCR); 1636 bmcr |= BMCR_RESET; 1637 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1638 1639 /* 3) Power Down */ 1640 bmcr = 0x1940; /* must be 0x1940 */ 1641 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1642 mdelay (100); /* wait a certain time */ 1643 1644 /* 4) Advertise nothing */ 1645 mii_write (dev, phy_addr, MII_ADVERTISE, 0); 1646 1647 /* 5) Set media and Power Up */ 1648 bmcr = BMCR_PDOWN; 1649 if (np->speed == 100) { 1650 bmcr |= BMCR_SPEED100; 1651 printk (KERN_INFO "Manual 100 Mbps, "); 1652 } else if (np->speed == 10) { 1653 printk (KERN_INFO "Manual 10 Mbps, "); 1654 } 1655 if (np->full_duplex) { 1656 bmcr |= BMCR_FULLDPLX; 1657 printk (KERN_CONT "Full duplex\n"); 1658 } else { 1659 printk (KERN_CONT "Half duplex\n"); 1660 } 1661 #if 0 1662 /* Set 1000BaseT Master/Slave setting */ 1663 mscr = mii_read (dev, phy_addr, MII_CTRL1000); 1664 mscr |= MII_MSCR_CFG_ENABLE; 1665 mscr &= ~MII_MSCR_CFG_VALUE = 0; 1666 #endif 1667 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1668 mdelay(10); 1669 } 1670 return 0; 1671 } 1672 1673 static int 1674 mii_get_media_pcs (struct net_device *dev) 1675 { 1676 __u16 negotiate; 1677 __u16 bmsr; 1678 int phy_addr; 1679 struct netdev_private *np; 1680 1681 np = netdev_priv(dev); 1682 phy_addr = np->phy_addr; 1683 1684 bmsr = mii_read (dev, phy_addr, PCS_BMSR); 1685 if (np->an_enable) { 1686 if (!(bmsr & BMSR_ANEGCOMPLETE)) { 1687 /* Auto-Negotiation not completed */ 1688 return -1; 1689 } 1690 negotiate = mii_read (dev, phy_addr, PCS_ANAR) & 1691 mii_read (dev, phy_addr, PCS_ANLPAR); 1692 np->speed = 1000; 1693 if (negotiate & PCS_ANAR_FULL_DUPLEX) { 1694 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1695 np->full_duplex = 1; 1696 } else { 1697 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n"); 1698 np->full_duplex = 0; 1699 } 1700 if (negotiate & PCS_ANAR_PAUSE) { 1701 np->tx_flow &= 1; 1702 np->rx_flow &= 1; 1703 } else if (negotiate & PCS_ANAR_ASYMMETRIC) { 1704 np->tx_flow = 0; 1705 np->rx_flow &= 1; 1706 } 1707 /* else tx_flow, rx_flow = user select */ 1708 } else { 1709 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR); 1710 printk (KERN_INFO "Operating at 1000 Mbps, "); 1711 if (bmcr & BMCR_FULLDPLX) { 1712 printk (KERN_CONT "Full duplex\n"); 1713 } else { 1714 printk (KERN_CONT "Half duplex\n"); 1715 } 1716 } 1717 if (np->tx_flow) 1718 printk(KERN_INFO "Enable Tx Flow Control\n"); 1719 else 1720 printk(KERN_INFO "Disable Tx Flow Control\n"); 1721 if (np->rx_flow) 1722 printk(KERN_INFO "Enable Rx Flow Control\n"); 1723 else 1724 printk(KERN_INFO "Disable Rx Flow Control\n"); 1725 1726 return 0; 1727 } 1728 1729 static int 1730 mii_set_media_pcs (struct net_device *dev) 1731 { 1732 __u16 bmcr; 1733 __u16 esr; 1734 __u16 anar; 1735 int phy_addr; 1736 struct netdev_private *np; 1737 np = netdev_priv(dev); 1738 phy_addr = np->phy_addr; 1739 1740 /* Auto-Negotiation? */ 1741 if (np->an_enable) { 1742 /* Advertise capabilities */ 1743 esr = mii_read (dev, phy_addr, PCS_ESR); 1744 anar = mii_read (dev, phy_addr, MII_ADVERTISE) & 1745 ~PCS_ANAR_HALF_DUPLEX & 1746 ~PCS_ANAR_FULL_DUPLEX; 1747 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD)) 1748 anar |= PCS_ANAR_HALF_DUPLEX; 1749 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD)) 1750 anar |= PCS_ANAR_FULL_DUPLEX; 1751 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC; 1752 mii_write (dev, phy_addr, MII_ADVERTISE, anar); 1753 1754 /* Soft reset PHY */ 1755 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET); 1756 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; 1757 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1758 mdelay(1); 1759 } else { 1760 /* Force speed setting */ 1761 /* PHY Reset */ 1762 bmcr = BMCR_RESET; 1763 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1764 mdelay(10); 1765 if (np->full_duplex) { 1766 bmcr = BMCR_FULLDPLX; 1767 printk (KERN_INFO "Manual full duplex\n"); 1768 } else { 1769 bmcr = 0; 1770 printk (KERN_INFO "Manual half duplex\n"); 1771 } 1772 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1773 mdelay(10); 1774 1775 /* Advertise nothing */ 1776 mii_write (dev, phy_addr, MII_ADVERTISE, 0); 1777 } 1778 return 0; 1779 } 1780 1781 1782 static int 1783 rio_close (struct net_device *dev) 1784 { 1785 struct netdev_private *np = netdev_priv(dev); 1786 struct pci_dev *pdev = np->pdev; 1787 1788 netif_stop_queue (dev); 1789 1790 rio_hw_stop(dev); 1791 1792 free_irq(pdev->irq, dev); 1793 del_timer_sync (&np->timer); 1794 1795 free_list(dev); 1796 1797 return 0; 1798 } 1799 1800 static void 1801 rio_remove1 (struct pci_dev *pdev) 1802 { 1803 struct net_device *dev = pci_get_drvdata (pdev); 1804 1805 if (dev) { 1806 struct netdev_private *np = netdev_priv(dev); 1807 1808 unregister_netdev (dev); 1809 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, 1810 np->rx_ring_dma); 1811 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, 1812 np->tx_ring_dma); 1813 #ifdef MEM_MAPPING 1814 pci_iounmap(pdev, np->ioaddr); 1815 #endif 1816 pci_iounmap(pdev, np->eeprom_addr); 1817 free_netdev (dev); 1818 pci_release_regions (pdev); 1819 pci_disable_device (pdev); 1820 } 1821 } 1822 1823 #ifdef CONFIG_PM_SLEEP 1824 static int rio_suspend(struct device *device) 1825 { 1826 struct net_device *dev = dev_get_drvdata(device); 1827 struct netdev_private *np = netdev_priv(dev); 1828 1829 if (!netif_running(dev)) 1830 return 0; 1831 1832 netif_device_detach(dev); 1833 del_timer_sync(&np->timer); 1834 rio_hw_stop(dev); 1835 1836 return 0; 1837 } 1838 1839 static int rio_resume(struct device *device) 1840 { 1841 struct net_device *dev = dev_get_drvdata(device); 1842 struct netdev_private *np = netdev_priv(dev); 1843 1844 if (!netif_running(dev)) 1845 return 0; 1846 1847 rio_reset_ring(np); 1848 rio_hw_init(dev); 1849 np->timer.expires = jiffies + 1 * HZ; 1850 add_timer(&np->timer); 1851 netif_device_attach(dev); 1852 dl2k_enable_int(np); 1853 1854 return 0; 1855 } 1856 1857 static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume); 1858 #define RIO_PM_OPS (&rio_pm_ops) 1859 1860 #else 1861 1862 #define RIO_PM_OPS NULL 1863 1864 #endif /* CONFIG_PM_SLEEP */ 1865 1866 static struct pci_driver rio_driver = { 1867 .name = "dl2k", 1868 .id_table = rio_pci_tbl, 1869 .probe = rio_probe1, 1870 .remove = rio_remove1, 1871 .driver.pm = RIO_PM_OPS, 1872 }; 1873 1874 module_pci_driver(rio_driver); 1875 /* 1876 1877 Compile command: 1878 1879 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c 1880 1881 Read Documentation/networking/device_drivers/dlink/dl2k.txt for details. 1882 1883 */ 1884 1885