1 /* Copyright 2008 - 2016 Freescale Semiconductor Inc. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are met: 5 * * Redistributions of source code must retain the above copyright 6 * notice, this list of conditions and the following disclaimer. 7 * * Redistributions in binary form must reproduce the above copyright 8 * notice, this list of conditions and the following disclaimer in the 9 * documentation and/or other materials provided with the distribution. 10 * * Neither the name of Freescale Semiconductor nor the 11 * names of its contributors may be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * ALTERNATIVELY, this software may be distributed under the terms of the 15 * GNU General Public License ("GPL") as published by the Free Software 16 * Foundation, either version 2 of that License or (at your option) any 17 * later version. 18 * 19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 32 33 #include <linux/init.h> 34 #include <linux/module.h> 35 #include <linux/of_platform.h> 36 #include <linux/of_mdio.h> 37 #include <linux/of_net.h> 38 #include <linux/io.h> 39 #include <linux/if_arp.h> 40 #include <linux/if_vlan.h> 41 #include <linux/icmp.h> 42 #include <linux/ip.h> 43 #include <linux/ipv6.h> 44 #include <linux/udp.h> 45 #include <linux/tcp.h> 46 #include <linux/net.h> 47 #include <linux/skbuff.h> 48 #include <linux/etherdevice.h> 49 #include <linux/if_ether.h> 50 #include <linux/highmem.h> 51 #include <linux/percpu.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/sort.h> 54 #include <linux/phy_fixed.h> 55 #include <soc/fsl/bman.h> 56 #include <soc/fsl/qman.h> 57 #include "fman.h" 58 #include "fman_port.h" 59 #include "mac.h" 60 #include "dpaa_eth.h" 61 62 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files 63 * using trace events only need to #include <trace/events/sched.h> 64 */ 65 #define CREATE_TRACE_POINTS 66 #include "dpaa_eth_trace.h" 67 68 static int debug = -1; 69 module_param(debug, int, 0444); 70 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)"); 71 72 static u16 tx_timeout = 1000; 73 module_param(tx_timeout, ushort, 0444); 74 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms"); 75 76 #define FM_FD_STAT_RX_ERRORS \ 77 (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL | \ 78 FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \ 79 FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME | \ 80 FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \ 81 FM_FD_ERR_PRS_HDR_ERR) 82 83 #define FM_FD_STAT_TX_ERRORS \ 84 (FM_FD_ERR_UNSUPPORTED_FORMAT | \ 85 FM_FD_ERR_LENGTH | FM_FD_ERR_DMA) 86 87 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 88 NETIF_MSG_LINK | NETIF_MSG_IFUP | \ 89 NETIF_MSG_IFDOWN) 90 91 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000 92 /* Ingress congestion threshold on FMan ports 93 * The size in bytes of the ingress tail-drop threshold on FMan ports. 94 * Traffic piling up above this value will be rejected by QMan and discarded 95 * by FMan. 96 */ 97 98 /* Size in bytes of the FQ taildrop threshold */ 99 #define DPAA_FQ_TD 0x200000 100 101 #define DPAA_CS_THRESHOLD_1G 0x06000000 102 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000 103 * The size in bytes of the egress Congestion State notification threshold on 104 * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a 105 * tight loop (e.g. by sending UDP datagrams at "while(1) speed"), 106 * and the larger the frame size, the more acute the problem. 107 * So we have to find a balance between these factors: 108 * - avoiding the device staying congested for a prolonged time (risking 109 * the netdev watchdog to fire - see also the tx_timeout module param); 110 * - affecting performance of protocols such as TCP, which otherwise 111 * behave well under the congestion notification mechanism; 112 * - preventing the Tx cores from tightly-looping (as if the congestion 113 * threshold was too low to be effective); 114 * - running out of memory if the CS threshold is set too high. 115 */ 116 117 #define DPAA_CS_THRESHOLD_10G 0x10000000 118 /* The size in bytes of the egress Congestion State notification threshold on 119 * 10G ports, range 0x1000 .. 0x10000000 120 */ 121 122 /* Largest value that the FQD's OAL field can hold */ 123 #define FSL_QMAN_MAX_OAL 127 124 125 /* Default alignment for start of data in an Rx FD */ 126 #define DPAA_FD_DATA_ALIGNMENT 16 127 128 /* The DPAA requires 256 bytes reserved and mapped for the SGT */ 129 #define DPAA_SGT_SIZE 256 130 131 /* Values for the L3R field of the FM Parse Results 132 */ 133 /* L3 Type field: First IP Present IPv4 */ 134 #define FM_L3_PARSE_RESULT_IPV4 0x8000 135 /* L3 Type field: First IP Present IPv6 */ 136 #define FM_L3_PARSE_RESULT_IPV6 0x4000 137 /* Values for the L4R field of the FM Parse Results */ 138 /* L4 Type field: UDP */ 139 #define FM_L4_PARSE_RESULT_UDP 0x40 140 /* L4 Type field: TCP */ 141 #define FM_L4_PARSE_RESULT_TCP 0x20 142 143 /* FD status field indicating whether the FM Parser has attempted to validate 144 * the L4 csum of the frame. 145 * Note that having this bit set doesn't necessarily imply that the checksum 146 * is valid. One would have to check the parse results to find that out. 147 */ 148 #define FM_FD_STAT_L4CV 0x00000004 149 150 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */ 151 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */ 152 153 #define FSL_DPAA_BPID_INV 0xff 154 #define FSL_DPAA_ETH_MAX_BUF_COUNT 128 155 #define FSL_DPAA_ETH_REFILL_THRESHOLD 80 156 157 #define DPAA_TX_PRIV_DATA_SIZE 16 158 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result) 159 #define DPAA_TIME_STAMP_SIZE 8 160 #define DPAA_HASH_RESULTS_SIZE 8 161 #define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \ 162 dpaa_rx_extra_headroom) 163 164 #define DPAA_ETH_PCD_RXQ_NUM 128 165 166 #define DPAA_ENQUEUE_RETRIES 100000 167 168 enum port_type {RX, TX}; 169 170 struct fm_port_fqs { 171 struct dpaa_fq *tx_defq; 172 struct dpaa_fq *tx_errq; 173 struct dpaa_fq *rx_defq; 174 struct dpaa_fq *rx_errq; 175 struct dpaa_fq *rx_pcdq; 176 }; 177 178 /* All the dpa bps in use at any moment */ 179 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS]; 180 181 /* The raw buffer size must be cacheline aligned */ 182 #define DPAA_BP_RAW_SIZE 4096 183 /* When using more than one buffer pool, the raw sizes are as follows: 184 * 1 bp: 4KB 185 * 2 bp: 2KB, 4KB 186 * 3 bp: 1KB, 2KB, 4KB 187 * 4 bp: 1KB, 2KB, 4KB, 8KB 188 */ 189 static inline size_t bpool_buffer_raw_size(u8 index, u8 cnt) 190 { 191 size_t res = DPAA_BP_RAW_SIZE / 4; 192 u8 i; 193 194 for (i = (cnt < 3) ? cnt : 3; i < 3 + index; i++) 195 res *= 2; 196 return res; 197 } 198 199 /* FMan-DMA requires 16-byte alignment for Rx buffers, but SKB_DATA_ALIGN is 200 * even stronger (SMP_CACHE_BYTES-aligned), so we just get away with that, 201 * via SKB_WITH_OVERHEAD(). We can't rely on netdev_alloc_frag() giving us 202 * half-page-aligned buffers, so we reserve some more space for start-of-buffer 203 * alignment. 204 */ 205 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD((raw_size) - SMP_CACHE_BYTES) 206 207 static int dpaa_max_frm; 208 209 static int dpaa_rx_extra_headroom; 210 211 #define dpaa_get_max_mtu() \ 212 (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN)) 213 214 static int dpaa_netdev_init(struct net_device *net_dev, 215 const struct net_device_ops *dpaa_ops, 216 u16 tx_timeout) 217 { 218 struct dpaa_priv *priv = netdev_priv(net_dev); 219 struct device *dev = net_dev->dev.parent; 220 struct dpaa_percpu_priv *percpu_priv; 221 const u8 *mac_addr; 222 int i, err; 223 224 /* Although we access another CPU's private data here 225 * we do it at initialization so it is safe 226 */ 227 for_each_possible_cpu(i) { 228 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 229 percpu_priv->net_dev = net_dev; 230 } 231 232 net_dev->netdev_ops = dpaa_ops; 233 mac_addr = priv->mac_dev->addr; 234 235 net_dev->mem_start = priv->mac_dev->res->start; 236 net_dev->mem_end = priv->mac_dev->res->end; 237 238 net_dev->min_mtu = ETH_MIN_MTU; 239 net_dev->max_mtu = dpaa_get_max_mtu(); 240 241 net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 242 NETIF_F_LLTX | NETIF_F_RXHASH); 243 244 net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA; 245 /* The kernels enables GSO automatically, if we declare NETIF_F_SG. 246 * For conformity, we'll still declare GSO explicitly. 247 */ 248 net_dev->features |= NETIF_F_GSO; 249 net_dev->features |= NETIF_F_RXCSUM; 250 251 net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 252 /* we do not want shared skbs on TX */ 253 net_dev->priv_flags &= ~IFF_TX_SKB_SHARING; 254 255 net_dev->features |= net_dev->hw_features; 256 net_dev->vlan_features = net_dev->features; 257 258 memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len); 259 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len); 260 261 net_dev->ethtool_ops = &dpaa_ethtool_ops; 262 263 net_dev->needed_headroom = priv->tx_headroom; 264 net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout); 265 266 /* start without the RUNNING flag, phylib controls it later */ 267 netif_carrier_off(net_dev); 268 269 err = register_netdev(net_dev); 270 if (err < 0) { 271 dev_err(dev, "register_netdev() = %d\n", err); 272 return err; 273 } 274 275 return 0; 276 } 277 278 static int dpaa_stop(struct net_device *net_dev) 279 { 280 struct mac_device *mac_dev; 281 struct dpaa_priv *priv; 282 int i, err, error; 283 284 priv = netdev_priv(net_dev); 285 mac_dev = priv->mac_dev; 286 287 netif_tx_stop_all_queues(net_dev); 288 /* Allow the Fman (Tx) port to process in-flight frames before we 289 * try switching it off. 290 */ 291 usleep_range(5000, 10000); 292 293 err = mac_dev->stop(mac_dev); 294 if (err < 0) 295 netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n", 296 err); 297 298 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) { 299 error = fman_port_disable(mac_dev->port[i]); 300 if (error) 301 err = error; 302 } 303 304 if (net_dev->phydev) 305 phy_disconnect(net_dev->phydev); 306 net_dev->phydev = NULL; 307 308 return err; 309 } 310 311 static void dpaa_tx_timeout(struct net_device *net_dev) 312 { 313 struct dpaa_percpu_priv *percpu_priv; 314 const struct dpaa_priv *priv; 315 316 priv = netdev_priv(net_dev); 317 percpu_priv = this_cpu_ptr(priv->percpu_priv); 318 319 netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n", 320 jiffies_to_msecs(jiffies - dev_trans_start(net_dev))); 321 322 percpu_priv->stats.tx_errors++; 323 } 324 325 /* Calculates the statistics for the given device by adding the statistics 326 * collected by each CPU. 327 */ 328 static void dpaa_get_stats64(struct net_device *net_dev, 329 struct rtnl_link_stats64 *s) 330 { 331 int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64); 332 struct dpaa_priv *priv = netdev_priv(net_dev); 333 struct dpaa_percpu_priv *percpu_priv; 334 u64 *netstats = (u64 *)s; 335 u64 *cpustats; 336 int i, j; 337 338 for_each_possible_cpu(i) { 339 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 340 341 cpustats = (u64 *)&percpu_priv->stats; 342 343 /* add stats from all CPUs */ 344 for (j = 0; j < numstats; j++) 345 netstats[j] += cpustats[j]; 346 } 347 } 348 349 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type, 350 void *type_data) 351 { 352 struct dpaa_priv *priv = netdev_priv(net_dev); 353 struct tc_mqprio_qopt *mqprio = type_data; 354 u8 num_tc; 355 int i; 356 357 if (type != TC_SETUP_QDISC_MQPRIO) 358 return -EOPNOTSUPP; 359 360 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 361 num_tc = mqprio->num_tc; 362 363 if (num_tc == priv->num_tc) 364 return 0; 365 366 if (!num_tc) { 367 netdev_reset_tc(net_dev); 368 goto out; 369 } 370 371 if (num_tc > DPAA_TC_NUM) { 372 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n", 373 DPAA_TC_NUM); 374 return -EINVAL; 375 } 376 377 netdev_set_num_tc(net_dev, num_tc); 378 379 for (i = 0; i < num_tc; i++) 380 netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM, 381 i * DPAA_TC_TXQ_NUM); 382 383 out: 384 priv->num_tc = num_tc ? : 1; 385 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM); 386 return 0; 387 } 388 389 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev) 390 { 391 struct dpaa_eth_data *eth_data; 392 struct device *dpaa_dev; 393 struct mac_device *mac_dev; 394 395 dpaa_dev = &pdev->dev; 396 eth_data = dpaa_dev->platform_data; 397 if (!eth_data) { 398 dev_err(dpaa_dev, "eth_data missing\n"); 399 return ERR_PTR(-ENODEV); 400 } 401 mac_dev = eth_data->mac_dev; 402 if (!mac_dev) { 403 dev_err(dpaa_dev, "mac_dev missing\n"); 404 return ERR_PTR(-EINVAL); 405 } 406 407 return mac_dev; 408 } 409 410 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr) 411 { 412 const struct dpaa_priv *priv; 413 struct mac_device *mac_dev; 414 struct sockaddr old_addr; 415 int err; 416 417 priv = netdev_priv(net_dev); 418 419 memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN); 420 421 err = eth_mac_addr(net_dev, addr); 422 if (err < 0) { 423 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err); 424 return err; 425 } 426 427 mac_dev = priv->mac_dev; 428 429 err = mac_dev->change_addr(mac_dev->fman_mac, 430 (enet_addr_t *)net_dev->dev_addr); 431 if (err < 0) { 432 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n", 433 err); 434 /* reverting to previous address */ 435 eth_mac_addr(net_dev, &old_addr); 436 437 return err; 438 } 439 440 return 0; 441 } 442 443 static void dpaa_set_rx_mode(struct net_device *net_dev) 444 { 445 const struct dpaa_priv *priv; 446 int err; 447 448 priv = netdev_priv(net_dev); 449 450 if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) { 451 priv->mac_dev->promisc = !priv->mac_dev->promisc; 452 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac, 453 priv->mac_dev->promisc); 454 if (err < 0) 455 netif_err(priv, drv, net_dev, 456 "mac_dev->set_promisc() = %d\n", 457 err); 458 } 459 460 if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) { 461 priv->mac_dev->allmulti = !priv->mac_dev->allmulti; 462 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac, 463 priv->mac_dev->allmulti); 464 if (err < 0) 465 netif_err(priv, drv, net_dev, 466 "mac_dev->set_allmulti() = %d\n", 467 err); 468 } 469 470 err = priv->mac_dev->set_multi(net_dev, priv->mac_dev); 471 if (err < 0) 472 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n", 473 err); 474 } 475 476 static struct dpaa_bp *dpaa_bpid2pool(int bpid) 477 { 478 if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS)) 479 return NULL; 480 481 return dpaa_bp_array[bpid]; 482 } 483 484 /* checks if this bpool is already allocated */ 485 static bool dpaa_bpid2pool_use(int bpid) 486 { 487 if (dpaa_bpid2pool(bpid)) { 488 refcount_inc(&dpaa_bp_array[bpid]->refs); 489 return true; 490 } 491 492 return false; 493 } 494 495 /* called only once per bpid by dpaa_bp_alloc_pool() */ 496 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp) 497 { 498 dpaa_bp_array[bpid] = dpaa_bp; 499 refcount_set(&dpaa_bp->refs, 1); 500 } 501 502 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp) 503 { 504 int err; 505 506 if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) { 507 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n", 508 __func__); 509 return -EINVAL; 510 } 511 512 /* If the pool is already specified, we only create one per bpid */ 513 if (dpaa_bp->bpid != FSL_DPAA_BPID_INV && 514 dpaa_bpid2pool_use(dpaa_bp->bpid)) 515 return 0; 516 517 if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) { 518 dpaa_bp->pool = bman_new_pool(); 519 if (!dpaa_bp->pool) { 520 pr_err("%s: bman_new_pool() failed\n", 521 __func__); 522 return -ENODEV; 523 } 524 525 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool); 526 } 527 528 if (dpaa_bp->seed_cb) { 529 err = dpaa_bp->seed_cb(dpaa_bp); 530 if (err) 531 goto pool_seed_failed; 532 } 533 534 dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp); 535 536 return 0; 537 538 pool_seed_failed: 539 pr_err("%s: pool seeding failed\n", __func__); 540 bman_free_pool(dpaa_bp->pool); 541 542 return err; 543 } 544 545 /* remove and free all the buffers from the given buffer pool */ 546 static void dpaa_bp_drain(struct dpaa_bp *bp) 547 { 548 u8 num = 8; 549 int ret; 550 551 do { 552 struct bm_buffer bmb[8]; 553 int i; 554 555 ret = bman_acquire(bp->pool, bmb, num); 556 if (ret < 0) { 557 if (num == 8) { 558 /* we have less than 8 buffers left; 559 * drain them one by one 560 */ 561 num = 1; 562 ret = 1; 563 continue; 564 } else { 565 /* Pool is fully drained */ 566 break; 567 } 568 } 569 570 if (bp->free_buf_cb) 571 for (i = 0; i < num; i++) 572 bp->free_buf_cb(bp, &bmb[i]); 573 } while (ret > 0); 574 } 575 576 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp) 577 { 578 struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid); 579 580 /* the mapping between bpid and dpaa_bp is done very late in the 581 * allocation procedure; if something failed before the mapping, the bp 582 * was not configured, therefore we don't need the below instructions 583 */ 584 if (!bp) 585 return; 586 587 if (!refcount_dec_and_test(&bp->refs)) 588 return; 589 590 if (bp->free_buf_cb) 591 dpaa_bp_drain(bp); 592 593 dpaa_bp_array[bp->bpid] = NULL; 594 bman_free_pool(bp->pool); 595 } 596 597 static void dpaa_bps_free(struct dpaa_priv *priv) 598 { 599 int i; 600 601 for (i = 0; i < DPAA_BPS_NUM; i++) 602 dpaa_bp_free(priv->dpaa_bps[i]); 603 } 604 605 /* Use multiple WQs for FQ assignment: 606 * - Tx Confirmation queues go to WQ1. 607 * - Rx Error and Tx Error queues go to WQ5 (giving them a better chance 608 * to be scheduled, in case there are many more FQs in WQ6). 609 * - Rx Default goes to WQ6. 610 * - Tx queues go to different WQs depending on their priority. Equal 611 * chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and 612 * WQ0 (highest priority). 613 * This ensures that Tx-confirmed buffers are timely released. In particular, 614 * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they 615 * are greatly outnumbered by other FQs in the system, while 616 * dequeue scheduling is round-robin. 617 */ 618 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx) 619 { 620 switch (fq->fq_type) { 621 case FQ_TYPE_TX_CONFIRM: 622 case FQ_TYPE_TX_CONF_MQ: 623 fq->wq = 1; 624 break; 625 case FQ_TYPE_RX_ERROR: 626 case FQ_TYPE_TX_ERROR: 627 fq->wq = 5; 628 break; 629 case FQ_TYPE_RX_DEFAULT: 630 case FQ_TYPE_RX_PCD: 631 fq->wq = 6; 632 break; 633 case FQ_TYPE_TX: 634 switch (idx / DPAA_TC_TXQ_NUM) { 635 case 0: 636 /* Low priority (best effort) */ 637 fq->wq = 6; 638 break; 639 case 1: 640 /* Medium priority */ 641 fq->wq = 2; 642 break; 643 case 2: 644 /* High priority */ 645 fq->wq = 1; 646 break; 647 case 3: 648 /* Very high priority */ 649 fq->wq = 0; 650 break; 651 default: 652 WARN(1, "Too many TX FQs: more than %d!\n", 653 DPAA_ETH_TXQ_NUM); 654 } 655 break; 656 default: 657 WARN(1, "Invalid FQ type %d for FQID %d!\n", 658 fq->fq_type, fq->fqid); 659 } 660 } 661 662 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev, 663 u32 start, u32 count, 664 struct list_head *list, 665 enum dpaa_fq_type fq_type) 666 { 667 struct dpaa_fq *dpaa_fq; 668 int i; 669 670 dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq), 671 GFP_KERNEL); 672 if (!dpaa_fq) 673 return NULL; 674 675 for (i = 0; i < count; i++) { 676 dpaa_fq[i].fq_type = fq_type; 677 dpaa_fq[i].fqid = start ? start + i : 0; 678 list_add_tail(&dpaa_fq[i].list, list); 679 } 680 681 for (i = 0; i < count; i++) 682 dpaa_assign_wq(dpaa_fq + i, i); 683 684 return dpaa_fq; 685 } 686 687 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list, 688 struct fm_port_fqs *port_fqs) 689 { 690 struct dpaa_fq *dpaa_fq; 691 u32 fq_base, fq_base_aligned, i; 692 693 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR); 694 if (!dpaa_fq) 695 goto fq_alloc_failed; 696 697 port_fqs->rx_errq = &dpaa_fq[0]; 698 699 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT); 700 if (!dpaa_fq) 701 goto fq_alloc_failed; 702 703 port_fqs->rx_defq = &dpaa_fq[0]; 704 705 /* the PCD FQIDs range needs to be aligned for correct operation */ 706 if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM)) 707 goto fq_alloc_failed; 708 709 fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM); 710 711 for (i = fq_base; i < fq_base_aligned; i++) 712 qman_release_fqid(i); 713 714 for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM; 715 i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++) 716 qman_release_fqid(i); 717 718 dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM, 719 list, FQ_TYPE_RX_PCD); 720 if (!dpaa_fq) 721 goto fq_alloc_failed; 722 723 port_fqs->rx_pcdq = &dpaa_fq[0]; 724 725 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ)) 726 goto fq_alloc_failed; 727 728 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR); 729 if (!dpaa_fq) 730 goto fq_alloc_failed; 731 732 port_fqs->tx_errq = &dpaa_fq[0]; 733 734 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM); 735 if (!dpaa_fq) 736 goto fq_alloc_failed; 737 738 port_fqs->tx_defq = &dpaa_fq[0]; 739 740 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX)) 741 goto fq_alloc_failed; 742 743 return 0; 744 745 fq_alloc_failed: 746 dev_err(dev, "dpaa_fq_alloc() failed\n"); 747 return -ENOMEM; 748 } 749 750 static u32 rx_pool_channel; 751 static DEFINE_SPINLOCK(rx_pool_channel_init); 752 753 static int dpaa_get_channel(void) 754 { 755 spin_lock(&rx_pool_channel_init); 756 if (!rx_pool_channel) { 757 u32 pool; 758 int ret; 759 760 ret = qman_alloc_pool(&pool); 761 762 if (!ret) 763 rx_pool_channel = pool; 764 } 765 spin_unlock(&rx_pool_channel_init); 766 if (!rx_pool_channel) 767 return -ENOMEM; 768 return rx_pool_channel; 769 } 770 771 static void dpaa_release_channel(void) 772 { 773 qman_release_pool(rx_pool_channel); 774 } 775 776 static void dpaa_eth_add_channel(u16 channel) 777 { 778 u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel); 779 const cpumask_t *cpus = qman_affine_cpus(); 780 struct qman_portal *portal; 781 int cpu; 782 783 for_each_cpu_and(cpu, cpus, cpu_online_mask) { 784 portal = qman_get_affine_portal(cpu); 785 qman_p_static_dequeue_add(portal, pool); 786 } 787 } 788 789 /* Congestion group state change notification callback. 790 * Stops the device's egress queues while they are congested and 791 * wakes them upon exiting congested state. 792 * Also updates some CGR-related stats. 793 */ 794 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr, 795 int congested) 796 { 797 struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr, 798 struct dpaa_priv, cgr_data.cgr); 799 800 if (congested) { 801 priv->cgr_data.congestion_start_jiffies = jiffies; 802 netif_tx_stop_all_queues(priv->net_dev); 803 priv->cgr_data.cgr_congested_count++; 804 } else { 805 priv->cgr_data.congested_jiffies += 806 (jiffies - priv->cgr_data.congestion_start_jiffies); 807 netif_tx_wake_all_queues(priv->net_dev); 808 } 809 } 810 811 static int dpaa_eth_cgr_init(struct dpaa_priv *priv) 812 { 813 struct qm_mcc_initcgr initcgr; 814 u32 cs_th; 815 int err; 816 817 err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid); 818 if (err < 0) { 819 if (netif_msg_drv(priv)) 820 pr_err("%s: Error %d allocating CGR ID\n", 821 __func__, err); 822 goto out_error; 823 } 824 priv->cgr_data.cgr.cb = dpaa_eth_cgscn; 825 826 /* Enable Congestion State Change Notifications and CS taildrop */ 827 memset(&initcgr, 0, sizeof(initcgr)); 828 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES); 829 initcgr.cgr.cscn_en = QM_CGR_EN; 830 831 /* Set different thresholds based on the MAC speed. 832 * This may turn suboptimal if the MAC is reconfigured at a speed 833 * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link. 834 * In such cases, we ought to reconfigure the threshold, too. 835 */ 836 if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full) 837 cs_th = DPAA_CS_THRESHOLD_10G; 838 else 839 cs_th = DPAA_CS_THRESHOLD_1G; 840 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); 841 842 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN); 843 initcgr.cgr.cstd_en = QM_CGR_EN; 844 845 err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT, 846 &initcgr); 847 if (err < 0) { 848 if (netif_msg_drv(priv)) 849 pr_err("%s: Error %d creating CGR with ID %d\n", 850 __func__, err, priv->cgr_data.cgr.cgrid); 851 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 852 goto out_error; 853 } 854 if (netif_msg_drv(priv)) 855 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n", 856 priv->cgr_data.cgr.cgrid, priv->mac_dev->addr, 857 priv->cgr_data.cgr.chan); 858 859 out_error: 860 return err; 861 } 862 863 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv, 864 struct dpaa_fq *fq, 865 const struct qman_fq *template) 866 { 867 fq->fq_base = *template; 868 fq->net_dev = priv->net_dev; 869 870 fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE; 871 fq->channel = priv->channel; 872 } 873 874 static inline void dpaa_setup_egress(const struct dpaa_priv *priv, 875 struct dpaa_fq *fq, 876 struct fman_port *port, 877 const struct qman_fq *template) 878 { 879 fq->fq_base = *template; 880 fq->net_dev = priv->net_dev; 881 882 if (port) { 883 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL; 884 fq->channel = (u16)fman_port_get_qman_channel_id(port); 885 } else { 886 fq->flags = QMAN_FQ_FLAG_NO_MODIFY; 887 } 888 } 889 890 static void dpaa_fq_setup(struct dpaa_priv *priv, 891 const struct dpaa_fq_cbs *fq_cbs, 892 struct fman_port *tx_port) 893 { 894 int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu; 895 const cpumask_t *affine_cpus = qman_affine_cpus(); 896 u16 channels[NR_CPUS]; 897 struct dpaa_fq *fq; 898 899 for_each_cpu_and(cpu, affine_cpus, cpu_online_mask) 900 channels[num_portals++] = qman_affine_channel(cpu); 901 902 if (num_portals == 0) 903 dev_err(priv->net_dev->dev.parent, 904 "No Qman software (affine) channels found"); 905 906 /* Initialize each FQ in the list */ 907 list_for_each_entry(fq, &priv->dpaa_fq_list, list) { 908 switch (fq->fq_type) { 909 case FQ_TYPE_RX_DEFAULT: 910 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq); 911 break; 912 case FQ_TYPE_RX_ERROR: 913 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq); 914 break; 915 case FQ_TYPE_RX_PCD: 916 if (!num_portals) 917 continue; 918 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq); 919 fq->channel = channels[portal_cnt++ % num_portals]; 920 break; 921 case FQ_TYPE_TX: 922 dpaa_setup_egress(priv, fq, tx_port, 923 &fq_cbs->egress_ern); 924 /* If we have more Tx queues than the number of cores, 925 * just ignore the extra ones. 926 */ 927 if (egress_cnt < DPAA_ETH_TXQ_NUM) 928 priv->egress_fqs[egress_cnt++] = &fq->fq_base; 929 break; 930 case FQ_TYPE_TX_CONF_MQ: 931 priv->conf_fqs[conf_cnt++] = &fq->fq_base; 932 /* fall through */ 933 case FQ_TYPE_TX_CONFIRM: 934 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq); 935 break; 936 case FQ_TYPE_TX_ERROR: 937 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq); 938 break; 939 default: 940 dev_warn(priv->net_dev->dev.parent, 941 "Unknown FQ type detected!\n"); 942 break; 943 } 944 } 945 946 /* Make sure all CPUs receive a corresponding Tx queue. */ 947 while (egress_cnt < DPAA_ETH_TXQ_NUM) { 948 list_for_each_entry(fq, &priv->dpaa_fq_list, list) { 949 if (fq->fq_type != FQ_TYPE_TX) 950 continue; 951 priv->egress_fqs[egress_cnt++] = &fq->fq_base; 952 if (egress_cnt == DPAA_ETH_TXQ_NUM) 953 break; 954 } 955 } 956 } 957 958 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv, 959 struct qman_fq *tx_fq) 960 { 961 int i; 962 963 for (i = 0; i < DPAA_ETH_TXQ_NUM; i++) 964 if (priv->egress_fqs[i] == tx_fq) 965 return i; 966 967 return -EINVAL; 968 } 969 970 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable) 971 { 972 const struct dpaa_priv *priv; 973 struct qman_fq *confq = NULL; 974 struct qm_mcc_initfq initfq; 975 struct device *dev; 976 struct qman_fq *fq; 977 int queue_id; 978 int err; 979 980 priv = netdev_priv(dpaa_fq->net_dev); 981 dev = dpaa_fq->net_dev->dev.parent; 982 983 if (dpaa_fq->fqid == 0) 984 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; 985 986 dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY); 987 988 err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base); 989 if (err) { 990 dev_err(dev, "qman_create_fq() failed\n"); 991 return err; 992 } 993 fq = &dpaa_fq->fq_base; 994 995 if (dpaa_fq->init) { 996 memset(&initfq, 0, sizeof(initfq)); 997 998 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL); 999 /* Note: we may get to keep an empty FQ in cache */ 1000 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE); 1001 1002 /* Try to reduce the number of portal interrupts for 1003 * Tx Confirmation FQs. 1004 */ 1005 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM) 1006 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK); 1007 1008 /* FQ placement */ 1009 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ); 1010 1011 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq); 1012 1013 /* Put all egress queues in a congestion group of their own. 1014 * Sensu stricto, the Tx confirmation queues are Rx FQs, 1015 * rather than Tx - but they nonetheless account for the 1016 * memory footprint on behalf of egress traffic. We therefore 1017 * place them in the netdev's CGR, along with the Tx FQs. 1018 */ 1019 if (dpaa_fq->fq_type == FQ_TYPE_TX || 1020 dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM || 1021 dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) { 1022 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); 1023 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE); 1024 initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid; 1025 /* Set a fixed overhead accounting, in an attempt to 1026 * reduce the impact of fixed-size skb shells and the 1027 * driver's needed headroom on system memory. This is 1028 * especially the case when the egress traffic is 1029 * composed of small datagrams. 1030 * Unfortunately, QMan's OAL value is capped to an 1031 * insufficient value, but even that is better than 1032 * no overhead accounting at all. 1033 */ 1034 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); 1035 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG); 1036 qm_fqd_set_oal(&initfq.fqd, 1037 min(sizeof(struct sk_buff) + 1038 priv->tx_headroom, 1039 (size_t)FSL_QMAN_MAX_OAL)); 1040 } 1041 1042 if (td_enable) { 1043 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH); 1044 qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1); 1045 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE); 1046 } 1047 1048 if (dpaa_fq->fq_type == FQ_TYPE_TX) { 1049 queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base); 1050 if (queue_id >= 0) 1051 confq = priv->conf_fqs[queue_id]; 1052 if (confq) { 1053 initfq.we_mask |= 1054 cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1055 /* ContextA: OVOM=1(use contextA2 bits instead of ICAD) 1056 * A2V=1 (contextA A2 field is valid) 1057 * A0V=1 (contextA A0 field is valid) 1058 * B0V=1 (contextB field is valid) 1059 * ContextA A2: EBD=1 (deallocate buffers inside FMan) 1060 * ContextB B0(ASPID): 0 (absolute Virtual Storage ID) 1061 */ 1062 qm_fqd_context_a_set64(&initfq.fqd, 1063 0x1e00000080000000ULL); 1064 } 1065 } 1066 1067 /* Put all the ingress queues in our "ingress CGR". */ 1068 if (priv->use_ingress_cgr && 1069 (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT || 1070 dpaa_fq->fq_type == FQ_TYPE_RX_ERROR || 1071 dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) { 1072 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID); 1073 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE); 1074 initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid; 1075 /* Set a fixed overhead accounting, just like for the 1076 * egress CGR. 1077 */ 1078 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC); 1079 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG); 1080 qm_fqd_set_oal(&initfq.fqd, 1081 min(sizeof(struct sk_buff) + 1082 priv->tx_headroom, 1083 (size_t)FSL_QMAN_MAX_OAL)); 1084 } 1085 1086 /* Initialization common to all ingress queues */ 1087 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) { 1088 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA); 1089 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE | 1090 QM_FQCTRL_CTXASTASHING); 1091 initfq.fqd.context_a.stashing.exclusive = 1092 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX | 1093 QM_STASHING_EXCL_ANNOTATION; 1094 qm_fqd_set_stashing(&initfq.fqd, 1, 2, 1095 DIV_ROUND_UP(sizeof(struct qman_fq), 1096 64)); 1097 } 1098 1099 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq); 1100 if (err < 0) { 1101 dev_err(dev, "qman_init_fq(%u) = %d\n", 1102 qman_fq_fqid(fq), err); 1103 qman_destroy_fq(fq); 1104 return err; 1105 } 1106 } 1107 1108 dpaa_fq->fqid = qman_fq_fqid(fq); 1109 1110 return 0; 1111 } 1112 1113 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq) 1114 { 1115 const struct dpaa_priv *priv; 1116 struct dpaa_fq *dpaa_fq; 1117 int err, error; 1118 1119 err = 0; 1120 1121 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base); 1122 priv = netdev_priv(dpaa_fq->net_dev); 1123 1124 if (dpaa_fq->init) { 1125 err = qman_retire_fq(fq, NULL); 1126 if (err < 0 && netif_msg_drv(priv)) 1127 dev_err(dev, "qman_retire_fq(%u) = %d\n", 1128 qman_fq_fqid(fq), err); 1129 1130 error = qman_oos_fq(fq); 1131 if (error < 0 && netif_msg_drv(priv)) { 1132 dev_err(dev, "qman_oos_fq(%u) = %d\n", 1133 qman_fq_fqid(fq), error); 1134 if (err >= 0) 1135 err = error; 1136 } 1137 } 1138 1139 qman_destroy_fq(fq); 1140 list_del(&dpaa_fq->list); 1141 1142 return err; 1143 } 1144 1145 static int dpaa_fq_free(struct device *dev, struct list_head *list) 1146 { 1147 struct dpaa_fq *dpaa_fq, *tmp; 1148 int err, error; 1149 1150 err = 0; 1151 list_for_each_entry_safe(dpaa_fq, tmp, list, list) { 1152 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq); 1153 if (error < 0 && err >= 0) 1154 err = error; 1155 } 1156 1157 return err; 1158 } 1159 1160 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq, 1161 struct dpaa_fq *defq, 1162 struct dpaa_buffer_layout *buf_layout) 1163 { 1164 struct fman_buffer_prefix_content buf_prefix_content; 1165 struct fman_port_params params; 1166 int err; 1167 1168 memset(¶ms, 0, sizeof(params)); 1169 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content)); 1170 1171 buf_prefix_content.priv_data_size = buf_layout->priv_data_size; 1172 buf_prefix_content.pass_prs_result = true; 1173 buf_prefix_content.pass_hash_result = true; 1174 buf_prefix_content.pass_time_stamp = true; 1175 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT; 1176 1177 params.specific_params.non_rx_params.err_fqid = errq->fqid; 1178 params.specific_params.non_rx_params.dflt_fqid = defq->fqid; 1179 1180 err = fman_port_config(port, ¶ms); 1181 if (err) { 1182 pr_err("%s: fman_port_config failed\n", __func__); 1183 return err; 1184 } 1185 1186 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content); 1187 if (err) { 1188 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n", 1189 __func__); 1190 return err; 1191 } 1192 1193 err = fman_port_init(port); 1194 if (err) 1195 pr_err("%s: fm_port_init failed\n", __func__); 1196 1197 return err; 1198 } 1199 1200 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp **bps, 1201 size_t count, struct dpaa_fq *errq, 1202 struct dpaa_fq *defq, struct dpaa_fq *pcdq, 1203 struct dpaa_buffer_layout *buf_layout) 1204 { 1205 struct fman_buffer_prefix_content buf_prefix_content; 1206 struct fman_port_rx_params *rx_p; 1207 struct fman_port_params params; 1208 int i, err; 1209 1210 memset(¶ms, 0, sizeof(params)); 1211 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content)); 1212 1213 buf_prefix_content.priv_data_size = buf_layout->priv_data_size; 1214 buf_prefix_content.pass_prs_result = true; 1215 buf_prefix_content.pass_hash_result = true; 1216 buf_prefix_content.pass_time_stamp = true; 1217 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT; 1218 1219 rx_p = ¶ms.specific_params.rx_params; 1220 rx_p->err_fqid = errq->fqid; 1221 rx_p->dflt_fqid = defq->fqid; 1222 if (pcdq) { 1223 rx_p->pcd_base_fqid = pcdq->fqid; 1224 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM; 1225 } 1226 1227 count = min(ARRAY_SIZE(rx_p->ext_buf_pools.ext_buf_pool), count); 1228 rx_p->ext_buf_pools.num_of_pools_used = (u8)count; 1229 for (i = 0; i < count; i++) { 1230 rx_p->ext_buf_pools.ext_buf_pool[i].id = bps[i]->bpid; 1231 rx_p->ext_buf_pools.ext_buf_pool[i].size = (u16)bps[i]->size; 1232 } 1233 1234 err = fman_port_config(port, ¶ms); 1235 if (err) { 1236 pr_err("%s: fman_port_config failed\n", __func__); 1237 return err; 1238 } 1239 1240 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content); 1241 if (err) { 1242 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n", 1243 __func__); 1244 return err; 1245 } 1246 1247 err = fman_port_init(port); 1248 if (err) 1249 pr_err("%s: fm_port_init failed\n", __func__); 1250 1251 return err; 1252 } 1253 1254 static int dpaa_eth_init_ports(struct mac_device *mac_dev, 1255 struct dpaa_bp **bps, size_t count, 1256 struct fm_port_fqs *port_fqs, 1257 struct dpaa_buffer_layout *buf_layout, 1258 struct device *dev) 1259 { 1260 struct fman_port *rxport = mac_dev->port[RX]; 1261 struct fman_port *txport = mac_dev->port[TX]; 1262 int err; 1263 1264 err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq, 1265 port_fqs->tx_defq, &buf_layout[TX]); 1266 if (err) 1267 return err; 1268 1269 err = dpaa_eth_init_rx_port(rxport, bps, count, port_fqs->rx_errq, 1270 port_fqs->rx_defq, port_fqs->rx_pcdq, 1271 &buf_layout[RX]); 1272 1273 return err; 1274 } 1275 1276 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp, 1277 struct bm_buffer *bmb, int cnt) 1278 { 1279 int err; 1280 1281 err = bman_release(dpaa_bp->pool, bmb, cnt); 1282 /* Should never occur, address anyway to avoid leaking the buffers */ 1283 if (WARN_ON(err) && dpaa_bp->free_buf_cb) 1284 while (cnt-- > 0) 1285 dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]); 1286 1287 return cnt; 1288 } 1289 1290 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt) 1291 { 1292 struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX]; 1293 struct dpaa_bp *dpaa_bp; 1294 int i = 0, j; 1295 1296 memset(bmb, 0, sizeof(bmb)); 1297 1298 do { 1299 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1300 if (!dpaa_bp) 1301 return; 1302 1303 j = 0; 1304 do { 1305 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1306 1307 bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i])); 1308 1309 j++; i++; 1310 } while (j < ARRAY_SIZE(bmb) && 1311 !qm_sg_entry_is_final(&sgt[i - 1]) && 1312 sgt[i - 1].bpid == sgt[i].bpid); 1313 1314 dpaa_bman_release(dpaa_bp, bmb, j); 1315 } while (!qm_sg_entry_is_final(&sgt[i - 1])); 1316 } 1317 1318 static void dpaa_fd_release(const struct net_device *net_dev, 1319 const struct qm_fd *fd) 1320 { 1321 struct qm_sg_entry *sgt; 1322 struct dpaa_bp *dpaa_bp; 1323 struct bm_buffer bmb; 1324 dma_addr_t addr; 1325 void *vaddr; 1326 1327 bmb.data = 0; 1328 bm_buffer_set64(&bmb, qm_fd_addr(fd)); 1329 1330 dpaa_bp = dpaa_bpid2pool(fd->bpid); 1331 if (!dpaa_bp) 1332 return; 1333 1334 if (qm_fd_get_format(fd) == qm_fd_sg) { 1335 vaddr = phys_to_virt(qm_fd_addr(fd)); 1336 sgt = vaddr + qm_fd_get_offset(fd); 1337 1338 dma_unmap_single(dpaa_bp->dev, qm_fd_addr(fd), dpaa_bp->size, 1339 DMA_FROM_DEVICE); 1340 1341 dpaa_release_sgt_members(sgt); 1342 1343 addr = dma_map_single(dpaa_bp->dev, vaddr, dpaa_bp->size, 1344 DMA_FROM_DEVICE); 1345 if (dma_mapping_error(dpaa_bp->dev, addr)) { 1346 dev_err(dpaa_bp->dev, "DMA mapping failed"); 1347 return; 1348 } 1349 bm_buffer_set64(&bmb, addr); 1350 } 1351 1352 dpaa_bman_release(dpaa_bp, &bmb, 1); 1353 } 1354 1355 static void count_ern(struct dpaa_percpu_priv *percpu_priv, 1356 const union qm_mr_entry *msg) 1357 { 1358 switch (msg->ern.rc & QM_MR_RC_MASK) { 1359 case QM_MR_RC_CGR_TAILDROP: 1360 percpu_priv->ern_cnt.cg_tdrop++; 1361 break; 1362 case QM_MR_RC_WRED: 1363 percpu_priv->ern_cnt.wred++; 1364 break; 1365 case QM_MR_RC_ERROR: 1366 percpu_priv->ern_cnt.err_cond++; 1367 break; 1368 case QM_MR_RC_ORPWINDOW_EARLY: 1369 percpu_priv->ern_cnt.early_window++; 1370 break; 1371 case QM_MR_RC_ORPWINDOW_LATE: 1372 percpu_priv->ern_cnt.late_window++; 1373 break; 1374 case QM_MR_RC_FQ_TAILDROP: 1375 percpu_priv->ern_cnt.fq_tdrop++; 1376 break; 1377 case QM_MR_RC_ORPWINDOW_RETIRED: 1378 percpu_priv->ern_cnt.fq_retired++; 1379 break; 1380 case QM_MR_RC_ORP_ZERO: 1381 percpu_priv->ern_cnt.orp_zero++; 1382 break; 1383 } 1384 } 1385 1386 /* Turn on HW checksum computation for this outgoing frame. 1387 * If the current protocol is not something we support in this regard 1388 * (or if the stack has already computed the SW checksum), we do nothing. 1389 * 1390 * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value 1391 * otherwise. 1392 * 1393 * Note that this function may modify the fd->cmd field and the skb data buffer 1394 * (the Parse Results area). 1395 */ 1396 static int dpaa_enable_tx_csum(struct dpaa_priv *priv, 1397 struct sk_buff *skb, 1398 struct qm_fd *fd, 1399 char *parse_results) 1400 { 1401 struct fman_prs_result *parse_result; 1402 u16 ethertype = ntohs(skb->protocol); 1403 struct ipv6hdr *ipv6h = NULL; 1404 struct iphdr *iph; 1405 int retval = 0; 1406 u8 l4_proto; 1407 1408 if (skb->ip_summed != CHECKSUM_PARTIAL) 1409 return 0; 1410 1411 /* Note: L3 csum seems to be already computed in sw, but we can't choose 1412 * L4 alone from the FM configuration anyway. 1413 */ 1414 1415 /* Fill in some fields of the Parse Results array, so the FMan 1416 * can find them as if they came from the FMan Parser. 1417 */ 1418 parse_result = (struct fman_prs_result *)parse_results; 1419 1420 /* If we're dealing with VLAN, get the real Ethernet type */ 1421 if (ethertype == ETH_P_8021Q) { 1422 /* We can't always assume the MAC header is set correctly 1423 * by the stack, so reset to beginning of skb->data 1424 */ 1425 skb_reset_mac_header(skb); 1426 ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto); 1427 } 1428 1429 /* Fill in the relevant L3 parse result fields 1430 * and read the L4 protocol type 1431 */ 1432 switch (ethertype) { 1433 case ETH_P_IP: 1434 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4); 1435 iph = ip_hdr(skb); 1436 WARN_ON(!iph); 1437 l4_proto = iph->protocol; 1438 break; 1439 case ETH_P_IPV6: 1440 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6); 1441 ipv6h = ipv6_hdr(skb); 1442 WARN_ON(!ipv6h); 1443 l4_proto = ipv6h->nexthdr; 1444 break; 1445 default: 1446 /* We shouldn't even be here */ 1447 if (net_ratelimit()) 1448 netif_alert(priv, tx_err, priv->net_dev, 1449 "Can't compute HW csum for L3 proto 0x%x\n", 1450 ntohs(skb->protocol)); 1451 retval = -EIO; 1452 goto return_error; 1453 } 1454 1455 /* Fill in the relevant L4 parse result fields */ 1456 switch (l4_proto) { 1457 case IPPROTO_UDP: 1458 parse_result->l4r = FM_L4_PARSE_RESULT_UDP; 1459 break; 1460 case IPPROTO_TCP: 1461 parse_result->l4r = FM_L4_PARSE_RESULT_TCP; 1462 break; 1463 default: 1464 if (net_ratelimit()) 1465 netif_alert(priv, tx_err, priv->net_dev, 1466 "Can't compute HW csum for L4 proto 0x%x\n", 1467 l4_proto); 1468 retval = -EIO; 1469 goto return_error; 1470 } 1471 1472 /* At index 0 is IPOffset_1 as defined in the Parse Results */ 1473 parse_result->ip_off[0] = (u8)skb_network_offset(skb); 1474 parse_result->l4_off = (u8)skb_transport_offset(skb); 1475 1476 /* Enable L3 (and L4, if TCP or UDP) HW checksum. */ 1477 fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC); 1478 1479 /* On P1023 and similar platforms fd->cmd interpretation could 1480 * be disabled by setting CONTEXT_A bit ICMD; currently this bit 1481 * is not set so we do not need to check; in the future, if/when 1482 * using context_a we need to check this bit 1483 */ 1484 1485 return_error: 1486 return retval; 1487 } 1488 1489 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp) 1490 { 1491 struct device *dev = dpaa_bp->dev; 1492 struct bm_buffer bmb[8]; 1493 dma_addr_t addr; 1494 void *new_buf; 1495 u8 i; 1496 1497 for (i = 0; i < 8; i++) { 1498 new_buf = netdev_alloc_frag(dpaa_bp->raw_size); 1499 if (unlikely(!new_buf)) { 1500 dev_err(dev, "netdev_alloc_frag() failed, size %zu\n", 1501 dpaa_bp->raw_size); 1502 goto release_previous_buffs; 1503 } 1504 new_buf = PTR_ALIGN(new_buf, SMP_CACHE_BYTES); 1505 1506 addr = dma_map_single(dev, new_buf, 1507 dpaa_bp->size, DMA_FROM_DEVICE); 1508 if (unlikely(dma_mapping_error(dev, addr))) { 1509 dev_err(dpaa_bp->dev, "DMA map failed"); 1510 goto release_previous_buffs; 1511 } 1512 1513 bmb[i].data = 0; 1514 bm_buffer_set64(&bmb[i], addr); 1515 } 1516 1517 release_bufs: 1518 return dpaa_bman_release(dpaa_bp, bmb, i); 1519 1520 release_previous_buffs: 1521 WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n"); 1522 1523 bm_buffer_set64(&bmb[i], 0); 1524 /* Avoid releasing a completely null buffer; bman_release() requires 1525 * at least one buffer. 1526 */ 1527 if (likely(i)) 1528 goto release_bufs; 1529 1530 return 0; 1531 } 1532 1533 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp) 1534 { 1535 int i; 1536 1537 /* Give each CPU an allotment of "config_count" buffers */ 1538 for_each_possible_cpu(i) { 1539 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i); 1540 int j; 1541 1542 /* Although we access another CPU's counters here 1543 * we do it at boot time so it is safe 1544 */ 1545 for (j = 0; j < dpaa_bp->config_count; j += 8) 1546 *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp); 1547 } 1548 return 0; 1549 } 1550 1551 /* Add buffers/(pages) for Rx processing whenever bpool count falls below 1552 * REFILL_THRESHOLD. 1553 */ 1554 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr) 1555 { 1556 int count = *countptr; 1557 int new_bufs; 1558 1559 if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) { 1560 do { 1561 new_bufs = dpaa_bp_add_8_bufs(dpaa_bp); 1562 if (unlikely(!new_bufs)) { 1563 /* Avoid looping forever if we've temporarily 1564 * run out of memory. We'll try again at the 1565 * next NAPI cycle. 1566 */ 1567 break; 1568 } 1569 count += new_bufs; 1570 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT); 1571 1572 *countptr = count; 1573 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT)) 1574 return -ENOMEM; 1575 } 1576 1577 return 0; 1578 } 1579 1580 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv) 1581 { 1582 struct dpaa_bp *dpaa_bp; 1583 int *countptr; 1584 int res, i; 1585 1586 for (i = 0; i < DPAA_BPS_NUM; i++) { 1587 dpaa_bp = priv->dpaa_bps[i]; 1588 if (!dpaa_bp) 1589 return -EINVAL; 1590 countptr = this_cpu_ptr(dpaa_bp->percpu_count); 1591 res = dpaa_eth_refill_bpool(dpaa_bp, countptr); 1592 if (res) 1593 return res; 1594 } 1595 return 0; 1596 } 1597 1598 /* Cleanup function for outgoing frame descriptors that were built on Tx path, 1599 * either contiguous frames or scatter/gather ones. 1600 * Skb freeing is not handled here. 1601 * 1602 * This function may be called on error paths in the Tx function, so guard 1603 * against cases when not all fd relevant fields were filled in. 1604 * 1605 * Return the skb backpointer, since for S/G frames the buffer containing it 1606 * gets freed here. 1607 */ 1608 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv, 1609 const struct qm_fd *fd) 1610 { 1611 const enum dma_data_direction dma_dir = DMA_TO_DEVICE; 1612 struct device *dev = priv->net_dev->dev.parent; 1613 struct skb_shared_hwtstamps shhwtstamps; 1614 dma_addr_t addr = qm_fd_addr(fd); 1615 const struct qm_sg_entry *sgt; 1616 struct sk_buff **skbh, *skb; 1617 int nr_frags, i; 1618 u64 ns; 1619 1620 skbh = (struct sk_buff **)phys_to_virt(addr); 1621 skb = *skbh; 1622 1623 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1624 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1625 1626 if (!fman_port_get_tstamp(priv->mac_dev->port[TX], (void *)skbh, 1627 &ns)) { 1628 shhwtstamps.hwtstamp = ns_to_ktime(ns); 1629 skb_tstamp_tx(skb, &shhwtstamps); 1630 } else { 1631 dev_warn(dev, "fman_port_get_tstamp failed!\n"); 1632 } 1633 } 1634 1635 if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) { 1636 nr_frags = skb_shinfo(skb)->nr_frags; 1637 dma_unmap_single(dev, addr, 1638 qm_fd_get_offset(fd) + DPAA_SGT_SIZE, 1639 dma_dir); 1640 1641 /* The sgt buffer has been allocated with netdev_alloc_frag(), 1642 * it's from lowmem. 1643 */ 1644 sgt = phys_to_virt(addr + qm_fd_get_offset(fd)); 1645 1646 /* sgt[0] is from lowmem, was dma_map_single()-ed */ 1647 dma_unmap_single(dev, qm_sg_addr(&sgt[0]), 1648 qm_sg_entry_get_len(&sgt[0]), dma_dir); 1649 1650 /* remaining pages were mapped with skb_frag_dma_map() */ 1651 for (i = 1; i <= nr_frags; i++) { 1652 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1653 1654 dma_unmap_page(dev, qm_sg_addr(&sgt[i]), 1655 qm_sg_entry_get_len(&sgt[i]), dma_dir); 1656 } 1657 1658 /* Free the page frag that we allocated on Tx */ 1659 skb_free_frag(phys_to_virt(addr)); 1660 } else { 1661 dma_unmap_single(dev, addr, 1662 skb_tail_pointer(skb) - (u8 *)skbh, dma_dir); 1663 } 1664 1665 return skb; 1666 } 1667 1668 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd) 1669 { 1670 /* The parser has run and performed L4 checksum validation. 1671 * We know there were no parser errors (and implicitly no 1672 * L4 csum error), otherwise we wouldn't be here. 1673 */ 1674 if ((priv->net_dev->features & NETIF_F_RXCSUM) && 1675 (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV)) 1676 return CHECKSUM_UNNECESSARY; 1677 1678 /* We're here because either the parser didn't run or the L4 checksum 1679 * was not verified. This may include the case of a UDP frame with 1680 * checksum zero or an L4 proto other than TCP/UDP 1681 */ 1682 return CHECKSUM_NONE; 1683 } 1684 1685 /* Build a linear skb around the received buffer. 1686 * We are guaranteed there is enough room at the end of the data buffer to 1687 * accommodate the shared info area of the skb. 1688 */ 1689 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv, 1690 const struct qm_fd *fd) 1691 { 1692 ssize_t fd_off = qm_fd_get_offset(fd); 1693 dma_addr_t addr = qm_fd_addr(fd); 1694 struct dpaa_bp *dpaa_bp; 1695 struct sk_buff *skb; 1696 void *vaddr; 1697 1698 vaddr = phys_to_virt(addr); 1699 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); 1700 1701 dpaa_bp = dpaa_bpid2pool(fd->bpid); 1702 if (!dpaa_bp) 1703 goto free_buffer; 1704 1705 skb = build_skb(vaddr, dpaa_bp->size + 1706 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); 1707 if (WARN_ONCE(!skb, "Build skb failure on Rx\n")) 1708 goto free_buffer; 1709 WARN_ON(fd_off != priv->rx_headroom); 1710 skb_reserve(skb, fd_off); 1711 skb_put(skb, qm_fd_get_length(fd)); 1712 1713 skb->ip_summed = rx_csum_offload(priv, fd); 1714 1715 return skb; 1716 1717 free_buffer: 1718 skb_free_frag(vaddr); 1719 return NULL; 1720 } 1721 1722 /* Build an skb with the data of the first S/G entry in the linear portion and 1723 * the rest of the frame as skb fragments. 1724 * 1725 * The page fragment holding the S/G Table is recycled here. 1726 */ 1727 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv, 1728 const struct qm_fd *fd) 1729 { 1730 ssize_t fd_off = qm_fd_get_offset(fd); 1731 dma_addr_t addr = qm_fd_addr(fd); 1732 const struct qm_sg_entry *sgt; 1733 struct page *page, *head_page; 1734 struct dpaa_bp *dpaa_bp; 1735 void *vaddr, *sg_vaddr; 1736 int frag_off, frag_len; 1737 struct sk_buff *skb; 1738 dma_addr_t sg_addr; 1739 int page_offset; 1740 unsigned int sz; 1741 int *count_ptr; 1742 int i; 1743 1744 vaddr = phys_to_virt(addr); 1745 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES)); 1746 1747 /* Iterate through the SGT entries and add data buffers to the skb */ 1748 sgt = vaddr + fd_off; 1749 skb = NULL; 1750 for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) { 1751 /* Extension bit is not supported */ 1752 WARN_ON(qm_sg_entry_is_ext(&sgt[i])); 1753 1754 sg_addr = qm_sg_addr(&sgt[i]); 1755 sg_vaddr = phys_to_virt(sg_addr); 1756 WARN_ON(!IS_ALIGNED((unsigned long)sg_vaddr, 1757 SMP_CACHE_BYTES)); 1758 1759 /* We may use multiple Rx pools */ 1760 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1761 if (!dpaa_bp) 1762 goto free_buffers; 1763 1764 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 1765 dma_unmap_single(dpaa_bp->dev, sg_addr, dpaa_bp->size, 1766 DMA_FROM_DEVICE); 1767 if (!skb) { 1768 sz = dpaa_bp->size + 1769 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1770 skb = build_skb(sg_vaddr, sz); 1771 if (WARN_ON(!skb)) 1772 goto free_buffers; 1773 1774 skb->ip_summed = rx_csum_offload(priv, fd); 1775 1776 /* Make sure forwarded skbs will have enough space 1777 * on Tx, if extra headers are added. 1778 */ 1779 WARN_ON(fd_off != priv->rx_headroom); 1780 skb_reserve(skb, fd_off); 1781 skb_put(skb, qm_sg_entry_get_len(&sgt[i])); 1782 } else { 1783 /* Not the first S/G entry; all data from buffer will 1784 * be added in an skb fragment; fragment index is offset 1785 * by one since first S/G entry was incorporated in the 1786 * linear part of the skb. 1787 * 1788 * Caution: 'page' may be a tail page. 1789 */ 1790 page = virt_to_page(sg_vaddr); 1791 head_page = virt_to_head_page(sg_vaddr); 1792 1793 /* Compute offset in (possibly tail) page */ 1794 page_offset = ((unsigned long)sg_vaddr & 1795 (PAGE_SIZE - 1)) + 1796 (page_address(page) - page_address(head_page)); 1797 /* page_offset only refers to the beginning of sgt[i]; 1798 * but the buffer itself may have an internal offset. 1799 */ 1800 frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset; 1801 frag_len = qm_sg_entry_get_len(&sgt[i]); 1802 /* skb_add_rx_frag() does no checking on the page; if 1803 * we pass it a tail page, we'll end up with 1804 * bad page accounting and eventually with segafults. 1805 */ 1806 skb_add_rx_frag(skb, i - 1, head_page, frag_off, 1807 frag_len, dpaa_bp->size); 1808 } 1809 /* Update the pool count for the current {cpu x bpool} */ 1810 (*count_ptr)--; 1811 1812 if (qm_sg_entry_is_final(&sgt[i])) 1813 break; 1814 } 1815 WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n"); 1816 1817 /* free the SG table buffer */ 1818 skb_free_frag(vaddr); 1819 1820 return skb; 1821 1822 free_buffers: 1823 /* compensate sw bpool counter changes */ 1824 for (i--; i >= 0; i--) { 1825 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1826 if (dpaa_bp) { 1827 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 1828 (*count_ptr)++; 1829 } 1830 } 1831 /* free all the SG entries */ 1832 for (i = 0; i < DPAA_SGT_MAX_ENTRIES ; i++) { 1833 sg_addr = qm_sg_addr(&sgt[i]); 1834 sg_vaddr = phys_to_virt(sg_addr); 1835 skb_free_frag(sg_vaddr); 1836 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid); 1837 if (dpaa_bp) { 1838 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 1839 (*count_ptr)--; 1840 } 1841 1842 if (qm_sg_entry_is_final(&sgt[i])) 1843 break; 1844 } 1845 /* free the SGT fragment */ 1846 skb_free_frag(vaddr); 1847 1848 return NULL; 1849 } 1850 1851 static int skb_to_contig_fd(struct dpaa_priv *priv, 1852 struct sk_buff *skb, struct qm_fd *fd, 1853 int *offset) 1854 { 1855 struct net_device *net_dev = priv->net_dev; 1856 struct device *dev = net_dev->dev.parent; 1857 enum dma_data_direction dma_dir; 1858 unsigned char *buffer_start; 1859 struct sk_buff **skbh; 1860 dma_addr_t addr; 1861 int err; 1862 1863 /* We are guaranteed to have at least tx_headroom bytes 1864 * available, so just use that for offset. 1865 */ 1866 fd->bpid = FSL_DPAA_BPID_INV; 1867 buffer_start = skb->data - priv->tx_headroom; 1868 dma_dir = DMA_TO_DEVICE; 1869 1870 skbh = (struct sk_buff **)buffer_start; 1871 *skbh = skb; 1872 1873 /* Enable L3/L4 hardware checksum computation. 1874 * 1875 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may 1876 * need to write into the skb. 1877 */ 1878 err = dpaa_enable_tx_csum(priv, skb, fd, 1879 ((char *)skbh) + DPAA_TX_PRIV_DATA_SIZE); 1880 if (unlikely(err < 0)) { 1881 if (net_ratelimit()) 1882 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n", 1883 err); 1884 return err; 1885 } 1886 1887 /* Fill in the rest of the FD fields */ 1888 qm_fd_set_contig(fd, priv->tx_headroom, skb->len); 1889 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO); 1890 1891 /* Map the entire buffer size that may be seen by FMan, but no more */ 1892 addr = dma_map_single(dev, skbh, 1893 skb_tail_pointer(skb) - buffer_start, dma_dir); 1894 if (unlikely(dma_mapping_error(dev, addr))) { 1895 if (net_ratelimit()) 1896 netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n"); 1897 return -EINVAL; 1898 } 1899 qm_fd_addr_set64(fd, addr); 1900 1901 return 0; 1902 } 1903 1904 static int skb_to_sg_fd(struct dpaa_priv *priv, 1905 struct sk_buff *skb, struct qm_fd *fd) 1906 { 1907 const enum dma_data_direction dma_dir = DMA_TO_DEVICE; 1908 const int nr_frags = skb_shinfo(skb)->nr_frags; 1909 struct net_device *net_dev = priv->net_dev; 1910 struct device *dev = net_dev->dev.parent; 1911 struct qm_sg_entry *sgt; 1912 struct sk_buff **skbh; 1913 int i, j, err, sz; 1914 void *buffer_start; 1915 skb_frag_t *frag; 1916 dma_addr_t addr; 1917 size_t frag_len; 1918 void *sgt_buf; 1919 1920 /* get a page frag to store the SGTable */ 1921 sz = SKB_DATA_ALIGN(priv->tx_headroom + DPAA_SGT_SIZE); 1922 sgt_buf = netdev_alloc_frag(sz); 1923 if (unlikely(!sgt_buf)) { 1924 netdev_err(net_dev, "netdev_alloc_frag() failed for size %d\n", 1925 sz); 1926 return -ENOMEM; 1927 } 1928 1929 /* Enable L3/L4 hardware checksum computation. 1930 * 1931 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may 1932 * need to write into the skb. 1933 */ 1934 err = dpaa_enable_tx_csum(priv, skb, fd, 1935 sgt_buf + DPAA_TX_PRIV_DATA_SIZE); 1936 if (unlikely(err < 0)) { 1937 if (net_ratelimit()) 1938 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n", 1939 err); 1940 goto csum_failed; 1941 } 1942 1943 /* SGT[0] is used by the linear part */ 1944 sgt = (struct qm_sg_entry *)(sgt_buf + priv->tx_headroom); 1945 frag_len = skb_headlen(skb); 1946 qm_sg_entry_set_len(&sgt[0], frag_len); 1947 sgt[0].bpid = FSL_DPAA_BPID_INV; 1948 sgt[0].offset = 0; 1949 addr = dma_map_single(dev, skb->data, 1950 skb_headlen(skb), dma_dir); 1951 if (unlikely(dma_mapping_error(dev, addr))) { 1952 dev_err(dev, "DMA mapping failed"); 1953 err = -EINVAL; 1954 goto sg0_map_failed; 1955 } 1956 qm_sg_entry_set64(&sgt[0], addr); 1957 1958 /* populate the rest of SGT entries */ 1959 for (i = 0; i < nr_frags; i++) { 1960 frag = &skb_shinfo(skb)->frags[i]; 1961 frag_len = skb_frag_size(frag); 1962 WARN_ON(!skb_frag_page(frag)); 1963 addr = skb_frag_dma_map(dev, frag, 0, 1964 frag_len, dma_dir); 1965 if (unlikely(dma_mapping_error(dev, addr))) { 1966 dev_err(dev, "DMA mapping failed"); 1967 err = -EINVAL; 1968 goto sg_map_failed; 1969 } 1970 1971 qm_sg_entry_set_len(&sgt[i + 1], frag_len); 1972 sgt[i + 1].bpid = FSL_DPAA_BPID_INV; 1973 sgt[i + 1].offset = 0; 1974 1975 /* keep the offset in the address */ 1976 qm_sg_entry_set64(&sgt[i + 1], addr); 1977 } 1978 1979 /* Set the final bit in the last used entry of the SGT */ 1980 qm_sg_entry_set_f(&sgt[nr_frags], frag_len); 1981 1982 qm_fd_set_sg(fd, priv->tx_headroom, skb->len); 1983 1984 /* DMA map the SGT page */ 1985 buffer_start = (void *)sgt - priv->tx_headroom; 1986 skbh = (struct sk_buff **)buffer_start; 1987 *skbh = skb; 1988 1989 addr = dma_map_single(dev, buffer_start, 1990 priv->tx_headroom + DPAA_SGT_SIZE, dma_dir); 1991 if (unlikely(dma_mapping_error(dev, addr))) { 1992 dev_err(dev, "DMA mapping failed"); 1993 err = -EINVAL; 1994 goto sgt_map_failed; 1995 } 1996 1997 fd->bpid = FSL_DPAA_BPID_INV; 1998 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO); 1999 qm_fd_addr_set64(fd, addr); 2000 2001 return 0; 2002 2003 sgt_map_failed: 2004 sg_map_failed: 2005 for (j = 0; j < i; j++) 2006 dma_unmap_page(dev, qm_sg_addr(&sgt[j]), 2007 qm_sg_entry_get_len(&sgt[j]), dma_dir); 2008 sg0_map_failed: 2009 csum_failed: 2010 skb_free_frag(sgt_buf); 2011 2012 return err; 2013 } 2014 2015 static inline int dpaa_xmit(struct dpaa_priv *priv, 2016 struct rtnl_link_stats64 *percpu_stats, 2017 int queue, 2018 struct qm_fd *fd) 2019 { 2020 struct qman_fq *egress_fq; 2021 int err, i; 2022 2023 egress_fq = priv->egress_fqs[queue]; 2024 if (fd->bpid == FSL_DPAA_BPID_INV) 2025 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue])); 2026 2027 /* Trace this Tx fd */ 2028 trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd); 2029 2030 for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) { 2031 err = qman_enqueue(egress_fq, fd); 2032 if (err != -EBUSY) 2033 break; 2034 } 2035 2036 if (unlikely(err < 0)) { 2037 percpu_stats->tx_fifo_errors++; 2038 return err; 2039 } 2040 2041 percpu_stats->tx_packets++; 2042 percpu_stats->tx_bytes += qm_fd_get_length(fd); 2043 2044 return 0; 2045 } 2046 2047 static netdev_tx_t 2048 dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev) 2049 { 2050 const int queue_mapping = skb_get_queue_mapping(skb); 2051 bool nonlinear = skb_is_nonlinear(skb); 2052 struct rtnl_link_stats64 *percpu_stats; 2053 struct dpaa_percpu_priv *percpu_priv; 2054 struct netdev_queue *txq; 2055 struct dpaa_priv *priv; 2056 struct qm_fd fd; 2057 int offset = 0; 2058 int err = 0; 2059 2060 priv = netdev_priv(net_dev); 2061 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2062 percpu_stats = &percpu_priv->stats; 2063 2064 qm_fd_clear_fd(&fd); 2065 2066 if (!nonlinear) { 2067 /* We're going to store the skb backpointer at the beginning 2068 * of the data buffer, so we need a privately owned skb 2069 * 2070 * We've made sure skb is not shared in dev->priv_flags, 2071 * we need to verify the skb head is not cloned 2072 */ 2073 if (skb_cow_head(skb, priv->tx_headroom)) 2074 goto enomem; 2075 2076 WARN_ON(skb_is_nonlinear(skb)); 2077 } 2078 2079 /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES; 2080 * make sure we don't feed FMan with more fragments than it supports. 2081 */ 2082 if (unlikely(nonlinear && 2083 (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) { 2084 /* If the egress skb contains more fragments than we support 2085 * we have no choice but to linearize it ourselves. 2086 */ 2087 if (__skb_linearize(skb)) 2088 goto enomem; 2089 2090 nonlinear = skb_is_nonlinear(skb); 2091 } 2092 2093 if (nonlinear) { 2094 /* Just create a S/G fd based on the skb */ 2095 err = skb_to_sg_fd(priv, skb, &fd); 2096 percpu_priv->tx_frag_skbuffs++; 2097 } else { 2098 /* Create a contig FD from this skb */ 2099 err = skb_to_contig_fd(priv, skb, &fd, &offset); 2100 } 2101 if (unlikely(err < 0)) 2102 goto skb_to_fd_failed; 2103 2104 txq = netdev_get_tx_queue(net_dev, queue_mapping); 2105 2106 /* LLTX requires to do our own update of trans_start */ 2107 txq->trans_start = jiffies; 2108 2109 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 2110 fd.cmd |= cpu_to_be32(FM_FD_CMD_UPD); 2111 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2112 } 2113 2114 if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0)) 2115 return NETDEV_TX_OK; 2116 2117 dpaa_cleanup_tx_fd(priv, &fd); 2118 skb_to_fd_failed: 2119 enomem: 2120 percpu_stats->tx_errors++; 2121 dev_kfree_skb(skb); 2122 return NETDEV_TX_OK; 2123 } 2124 2125 static void dpaa_rx_error(struct net_device *net_dev, 2126 const struct dpaa_priv *priv, 2127 struct dpaa_percpu_priv *percpu_priv, 2128 const struct qm_fd *fd, 2129 u32 fqid) 2130 { 2131 if (net_ratelimit()) 2132 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n", 2133 be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS); 2134 2135 percpu_priv->stats.rx_errors++; 2136 2137 if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA) 2138 percpu_priv->rx_errors.dme++; 2139 if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL) 2140 percpu_priv->rx_errors.fpe++; 2141 if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE) 2142 percpu_priv->rx_errors.fse++; 2143 if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR) 2144 percpu_priv->rx_errors.phe++; 2145 2146 dpaa_fd_release(net_dev, fd); 2147 } 2148 2149 static void dpaa_tx_error(struct net_device *net_dev, 2150 const struct dpaa_priv *priv, 2151 struct dpaa_percpu_priv *percpu_priv, 2152 const struct qm_fd *fd, 2153 u32 fqid) 2154 { 2155 struct sk_buff *skb; 2156 2157 if (net_ratelimit()) 2158 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2159 be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS); 2160 2161 percpu_priv->stats.tx_errors++; 2162 2163 skb = dpaa_cleanup_tx_fd(priv, fd); 2164 dev_kfree_skb(skb); 2165 } 2166 2167 static int dpaa_eth_poll(struct napi_struct *napi, int budget) 2168 { 2169 struct dpaa_napi_portal *np = 2170 container_of(napi, struct dpaa_napi_portal, napi); 2171 2172 int cleaned = qman_p_poll_dqrr(np->p, budget); 2173 2174 if (cleaned < budget) { 2175 napi_complete_done(napi, cleaned); 2176 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); 2177 } else if (np->down) { 2178 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI); 2179 } 2180 2181 return cleaned; 2182 } 2183 2184 static void dpaa_tx_conf(struct net_device *net_dev, 2185 const struct dpaa_priv *priv, 2186 struct dpaa_percpu_priv *percpu_priv, 2187 const struct qm_fd *fd, 2188 u32 fqid) 2189 { 2190 struct sk_buff *skb; 2191 2192 if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) { 2193 if (net_ratelimit()) 2194 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2195 be32_to_cpu(fd->status) & 2196 FM_FD_STAT_TX_ERRORS); 2197 2198 percpu_priv->stats.tx_errors++; 2199 } 2200 2201 percpu_priv->tx_confirm++; 2202 2203 skb = dpaa_cleanup_tx_fd(priv, fd); 2204 2205 consume_skb(skb); 2206 } 2207 2208 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv, 2209 struct qman_portal *portal) 2210 { 2211 if (unlikely(in_irq() || !in_serving_softirq())) { 2212 /* Disable QMan IRQ and invoke NAPI */ 2213 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI); 2214 2215 percpu_priv->np.p = portal; 2216 napi_schedule(&percpu_priv->np.napi); 2217 percpu_priv->in_interrupt++; 2218 return 1; 2219 } 2220 return 0; 2221 } 2222 2223 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal, 2224 struct qman_fq *fq, 2225 const struct qm_dqrr_entry *dq) 2226 { 2227 struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base); 2228 struct dpaa_percpu_priv *percpu_priv; 2229 struct net_device *net_dev; 2230 struct dpaa_bp *dpaa_bp; 2231 struct dpaa_priv *priv; 2232 2233 net_dev = dpaa_fq->net_dev; 2234 priv = netdev_priv(net_dev); 2235 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid); 2236 if (!dpaa_bp) 2237 return qman_cb_dqrr_consume; 2238 2239 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2240 2241 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2242 return qman_cb_dqrr_stop; 2243 2244 dpaa_eth_refill_bpools(priv); 2245 dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2246 2247 return qman_cb_dqrr_consume; 2248 } 2249 2250 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal, 2251 struct qman_fq *fq, 2252 const struct qm_dqrr_entry *dq) 2253 { 2254 struct skb_shared_hwtstamps *shhwtstamps; 2255 struct rtnl_link_stats64 *percpu_stats; 2256 struct dpaa_percpu_priv *percpu_priv; 2257 const struct qm_fd *fd = &dq->fd; 2258 dma_addr_t addr = qm_fd_addr(fd); 2259 enum qm_fd_format fd_format; 2260 struct net_device *net_dev; 2261 u32 fd_status, hash_offset; 2262 struct dpaa_bp *dpaa_bp; 2263 struct dpaa_priv *priv; 2264 unsigned int skb_len; 2265 struct sk_buff *skb; 2266 int *count_ptr; 2267 void *vaddr; 2268 u64 ns; 2269 2270 fd_status = be32_to_cpu(fd->status); 2271 fd_format = qm_fd_get_format(fd); 2272 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2273 priv = netdev_priv(net_dev); 2274 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid); 2275 if (!dpaa_bp) 2276 return qman_cb_dqrr_consume; 2277 2278 /* Trace the Rx fd */ 2279 trace_dpaa_rx_fd(net_dev, fq, &dq->fd); 2280 2281 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2282 percpu_stats = &percpu_priv->stats; 2283 2284 if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal))) 2285 return qman_cb_dqrr_stop; 2286 2287 /* Make sure we didn't run out of buffers */ 2288 if (unlikely(dpaa_eth_refill_bpools(priv))) { 2289 /* Unable to refill the buffer pool due to insufficient 2290 * system memory. Just release the frame back into the pool, 2291 * otherwise we'll soon end up with an empty buffer pool. 2292 */ 2293 dpaa_fd_release(net_dev, &dq->fd); 2294 return qman_cb_dqrr_consume; 2295 } 2296 2297 if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) { 2298 if (net_ratelimit()) 2299 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n", 2300 fd_status & FM_FD_STAT_RX_ERRORS); 2301 2302 percpu_stats->rx_errors++; 2303 dpaa_fd_release(net_dev, fd); 2304 return qman_cb_dqrr_consume; 2305 } 2306 2307 dpaa_bp = dpaa_bpid2pool(fd->bpid); 2308 if (!dpaa_bp) 2309 return qman_cb_dqrr_consume; 2310 2311 dma_unmap_single(dpaa_bp->dev, addr, dpaa_bp->size, DMA_FROM_DEVICE); 2312 2313 /* prefetch the first 64 bytes of the frame or the SGT start */ 2314 vaddr = phys_to_virt(addr); 2315 prefetch(vaddr + qm_fd_get_offset(fd)); 2316 2317 /* The only FD types that we may receive are contig and S/G */ 2318 WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg)); 2319 2320 /* Account for either the contig buffer or the SGT buffer (depending on 2321 * which case we were in) having been removed from the pool. 2322 */ 2323 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count); 2324 (*count_ptr)--; 2325 2326 if (likely(fd_format == qm_fd_contig)) 2327 skb = contig_fd_to_skb(priv, fd); 2328 else 2329 skb = sg_fd_to_skb(priv, fd); 2330 if (!skb) 2331 return qman_cb_dqrr_consume; 2332 2333 if (priv->rx_tstamp) { 2334 shhwtstamps = skb_hwtstamps(skb); 2335 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2336 2337 if (!fman_port_get_tstamp(priv->mac_dev->port[RX], vaddr, &ns)) 2338 shhwtstamps->hwtstamp = ns_to_ktime(ns); 2339 else 2340 dev_warn(net_dev->dev.parent, "fman_port_get_tstamp failed!\n"); 2341 } 2342 2343 skb->protocol = eth_type_trans(skb, net_dev); 2344 2345 if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use && 2346 !fman_port_get_hash_result_offset(priv->mac_dev->port[RX], 2347 &hash_offset)) { 2348 enum pkt_hash_types type; 2349 2350 /* if L4 exists, it was used in the hash generation */ 2351 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ? 2352 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3; 2353 skb_set_hash(skb, be32_to_cpu(*(u32 *)(vaddr + hash_offset)), 2354 type); 2355 } 2356 2357 skb_len = skb->len; 2358 2359 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) { 2360 percpu_stats->rx_dropped++; 2361 return qman_cb_dqrr_consume; 2362 } 2363 2364 percpu_stats->rx_packets++; 2365 percpu_stats->rx_bytes += skb_len; 2366 2367 return qman_cb_dqrr_consume; 2368 } 2369 2370 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal, 2371 struct qman_fq *fq, 2372 const struct qm_dqrr_entry *dq) 2373 { 2374 struct dpaa_percpu_priv *percpu_priv; 2375 struct net_device *net_dev; 2376 struct dpaa_priv *priv; 2377 2378 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2379 priv = netdev_priv(net_dev); 2380 2381 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2382 2383 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2384 return qman_cb_dqrr_stop; 2385 2386 dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2387 2388 return qman_cb_dqrr_consume; 2389 } 2390 2391 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal, 2392 struct qman_fq *fq, 2393 const struct qm_dqrr_entry *dq) 2394 { 2395 struct dpaa_percpu_priv *percpu_priv; 2396 struct net_device *net_dev; 2397 struct dpaa_priv *priv; 2398 2399 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2400 priv = netdev_priv(net_dev); 2401 2402 /* Trace the fd */ 2403 trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd); 2404 2405 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2406 2407 if (dpaa_eth_napi_schedule(percpu_priv, portal)) 2408 return qman_cb_dqrr_stop; 2409 2410 dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid); 2411 2412 return qman_cb_dqrr_consume; 2413 } 2414 2415 static void egress_ern(struct qman_portal *portal, 2416 struct qman_fq *fq, 2417 const union qm_mr_entry *msg) 2418 { 2419 const struct qm_fd *fd = &msg->ern.fd; 2420 struct dpaa_percpu_priv *percpu_priv; 2421 const struct dpaa_priv *priv; 2422 struct net_device *net_dev; 2423 struct sk_buff *skb; 2424 2425 net_dev = ((struct dpaa_fq *)fq)->net_dev; 2426 priv = netdev_priv(net_dev); 2427 percpu_priv = this_cpu_ptr(priv->percpu_priv); 2428 2429 percpu_priv->stats.tx_dropped++; 2430 percpu_priv->stats.tx_fifo_errors++; 2431 count_ern(percpu_priv, msg); 2432 2433 skb = dpaa_cleanup_tx_fd(priv, fd); 2434 dev_kfree_skb_any(skb); 2435 } 2436 2437 static const struct dpaa_fq_cbs dpaa_fq_cbs = { 2438 .rx_defq = { .cb = { .dqrr = rx_default_dqrr } }, 2439 .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } }, 2440 .rx_errq = { .cb = { .dqrr = rx_error_dqrr } }, 2441 .tx_errq = { .cb = { .dqrr = conf_error_dqrr } }, 2442 .egress_ern = { .cb = { .ern = egress_ern } } 2443 }; 2444 2445 static void dpaa_eth_napi_enable(struct dpaa_priv *priv) 2446 { 2447 struct dpaa_percpu_priv *percpu_priv; 2448 int i; 2449 2450 for_each_online_cpu(i) { 2451 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 2452 2453 percpu_priv->np.down = 0; 2454 napi_enable(&percpu_priv->np.napi); 2455 } 2456 } 2457 2458 static void dpaa_eth_napi_disable(struct dpaa_priv *priv) 2459 { 2460 struct dpaa_percpu_priv *percpu_priv; 2461 int i; 2462 2463 for_each_online_cpu(i) { 2464 percpu_priv = per_cpu_ptr(priv->percpu_priv, i); 2465 2466 percpu_priv->np.down = 1; 2467 napi_disable(&percpu_priv->np.napi); 2468 } 2469 } 2470 2471 static void dpaa_adjust_link(struct net_device *net_dev) 2472 { 2473 struct mac_device *mac_dev; 2474 struct dpaa_priv *priv; 2475 2476 priv = netdev_priv(net_dev); 2477 mac_dev = priv->mac_dev; 2478 mac_dev->adjust_link(mac_dev); 2479 } 2480 2481 static int dpaa_phy_init(struct net_device *net_dev) 2482 { 2483 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2484 struct mac_device *mac_dev; 2485 struct phy_device *phy_dev; 2486 struct dpaa_priv *priv; 2487 2488 priv = netdev_priv(net_dev); 2489 mac_dev = priv->mac_dev; 2490 2491 phy_dev = of_phy_connect(net_dev, mac_dev->phy_node, 2492 &dpaa_adjust_link, 0, 2493 mac_dev->phy_if); 2494 if (!phy_dev) { 2495 netif_err(priv, ifup, net_dev, "init_phy() failed\n"); 2496 return -ENODEV; 2497 } 2498 2499 /* Remove any features not supported by the controller */ 2500 ethtool_convert_legacy_u32_to_link_mode(mask, mac_dev->if_support); 2501 linkmode_and(phy_dev->supported, phy_dev->supported, mask); 2502 2503 phy_support_asym_pause(phy_dev); 2504 2505 mac_dev->phy_dev = phy_dev; 2506 net_dev->phydev = phy_dev; 2507 2508 return 0; 2509 } 2510 2511 static int dpaa_open(struct net_device *net_dev) 2512 { 2513 struct mac_device *mac_dev; 2514 struct dpaa_priv *priv; 2515 int err, i; 2516 2517 priv = netdev_priv(net_dev); 2518 mac_dev = priv->mac_dev; 2519 dpaa_eth_napi_enable(priv); 2520 2521 err = dpaa_phy_init(net_dev); 2522 if (err) 2523 goto phy_init_failed; 2524 2525 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) { 2526 err = fman_port_enable(mac_dev->port[i]); 2527 if (err) 2528 goto mac_start_failed; 2529 } 2530 2531 err = priv->mac_dev->start(mac_dev); 2532 if (err < 0) { 2533 netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err); 2534 goto mac_start_failed; 2535 } 2536 2537 netif_tx_start_all_queues(net_dev); 2538 2539 return 0; 2540 2541 mac_start_failed: 2542 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) 2543 fman_port_disable(mac_dev->port[i]); 2544 2545 phy_init_failed: 2546 dpaa_eth_napi_disable(priv); 2547 2548 return err; 2549 } 2550 2551 static int dpaa_eth_stop(struct net_device *net_dev) 2552 { 2553 struct dpaa_priv *priv; 2554 int err; 2555 2556 err = dpaa_stop(net_dev); 2557 2558 priv = netdev_priv(net_dev); 2559 dpaa_eth_napi_disable(priv); 2560 2561 return err; 2562 } 2563 2564 static int dpaa_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2565 { 2566 struct dpaa_priv *priv = netdev_priv(dev); 2567 struct hwtstamp_config config; 2568 2569 if (copy_from_user(&config, rq->ifr_data, sizeof(config))) 2570 return -EFAULT; 2571 2572 switch (config.tx_type) { 2573 case HWTSTAMP_TX_OFF: 2574 /* Couldn't disable rx/tx timestamping separately. 2575 * Do nothing here. 2576 */ 2577 priv->tx_tstamp = false; 2578 break; 2579 case HWTSTAMP_TX_ON: 2580 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true); 2581 priv->tx_tstamp = true; 2582 break; 2583 default: 2584 return -ERANGE; 2585 } 2586 2587 if (config.rx_filter == HWTSTAMP_FILTER_NONE) { 2588 /* Couldn't disable rx/tx timestamping separately. 2589 * Do nothing here. 2590 */ 2591 priv->rx_tstamp = false; 2592 } else { 2593 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true); 2594 priv->rx_tstamp = true; 2595 /* TS is set for all frame types, not only those requested */ 2596 config.rx_filter = HWTSTAMP_FILTER_ALL; 2597 } 2598 2599 return copy_to_user(rq->ifr_data, &config, sizeof(config)) ? 2600 -EFAULT : 0; 2601 } 2602 2603 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd) 2604 { 2605 int ret = -EINVAL; 2606 2607 if (cmd == SIOCGMIIREG) { 2608 if (net_dev->phydev) 2609 return phy_mii_ioctl(net_dev->phydev, rq, cmd); 2610 } 2611 2612 if (cmd == SIOCSHWTSTAMP) 2613 return dpaa_ts_ioctl(net_dev, rq, cmd); 2614 2615 return ret; 2616 } 2617 2618 static const struct net_device_ops dpaa_ops = { 2619 .ndo_open = dpaa_open, 2620 .ndo_start_xmit = dpaa_start_xmit, 2621 .ndo_stop = dpaa_eth_stop, 2622 .ndo_tx_timeout = dpaa_tx_timeout, 2623 .ndo_get_stats64 = dpaa_get_stats64, 2624 .ndo_change_carrier = fixed_phy_change_carrier, 2625 .ndo_set_mac_address = dpaa_set_mac_address, 2626 .ndo_validate_addr = eth_validate_addr, 2627 .ndo_set_rx_mode = dpaa_set_rx_mode, 2628 .ndo_do_ioctl = dpaa_ioctl, 2629 .ndo_setup_tc = dpaa_setup_tc, 2630 }; 2631 2632 static int dpaa_napi_add(struct net_device *net_dev) 2633 { 2634 struct dpaa_priv *priv = netdev_priv(net_dev); 2635 struct dpaa_percpu_priv *percpu_priv; 2636 int cpu; 2637 2638 for_each_possible_cpu(cpu) { 2639 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); 2640 2641 netif_napi_add(net_dev, &percpu_priv->np.napi, 2642 dpaa_eth_poll, NAPI_POLL_WEIGHT); 2643 } 2644 2645 return 0; 2646 } 2647 2648 static void dpaa_napi_del(struct net_device *net_dev) 2649 { 2650 struct dpaa_priv *priv = netdev_priv(net_dev); 2651 struct dpaa_percpu_priv *percpu_priv; 2652 int cpu; 2653 2654 for_each_possible_cpu(cpu) { 2655 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu); 2656 2657 netif_napi_del(&percpu_priv->np.napi); 2658 } 2659 } 2660 2661 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp, 2662 struct bm_buffer *bmb) 2663 { 2664 dma_addr_t addr = bm_buf_addr(bmb); 2665 2666 dma_unmap_single(bp->dev, addr, bp->size, DMA_FROM_DEVICE); 2667 2668 skb_free_frag(phys_to_virt(addr)); 2669 } 2670 2671 /* Alloc the dpaa_bp struct and configure default values */ 2672 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev) 2673 { 2674 struct dpaa_bp *dpaa_bp; 2675 2676 dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL); 2677 if (!dpaa_bp) 2678 return ERR_PTR(-ENOMEM); 2679 2680 dpaa_bp->bpid = FSL_DPAA_BPID_INV; 2681 dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count); 2682 if (!dpaa_bp->percpu_count) 2683 return ERR_PTR(-ENOMEM); 2684 2685 dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT; 2686 2687 dpaa_bp->seed_cb = dpaa_bp_seed; 2688 dpaa_bp->free_buf_cb = dpaa_bp_free_pf; 2689 2690 return dpaa_bp; 2691 } 2692 2693 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR. 2694 * We won't be sending congestion notifications to FMan; for now, we just use 2695 * this CGR to generate enqueue rejections to FMan in order to drop the frames 2696 * before they reach our ingress queues and eat up memory. 2697 */ 2698 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv) 2699 { 2700 struct qm_mcc_initcgr initcgr; 2701 u32 cs_th; 2702 int err; 2703 2704 err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid); 2705 if (err < 0) { 2706 if (netif_msg_drv(priv)) 2707 pr_err("Error %d allocating CGR ID\n", err); 2708 goto out_error; 2709 } 2710 2711 /* Enable CS TD, but disable Congestion State Change Notifications. */ 2712 memset(&initcgr, 0, sizeof(initcgr)); 2713 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES); 2714 initcgr.cgr.cscn_en = QM_CGR_EN; 2715 cs_th = DPAA_INGRESS_CS_THRESHOLD; 2716 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1); 2717 2718 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN); 2719 initcgr.cgr.cstd_en = QM_CGR_EN; 2720 2721 /* This CGR will be associated with the SWP affined to the current CPU. 2722 * However, we'll place all our ingress FQs in it. 2723 */ 2724 err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT, 2725 &initcgr); 2726 if (err < 0) { 2727 if (netif_msg_drv(priv)) 2728 pr_err("Error %d creating ingress CGR with ID %d\n", 2729 err, priv->ingress_cgr.cgrid); 2730 qman_release_cgrid(priv->ingress_cgr.cgrid); 2731 goto out_error; 2732 } 2733 if (netif_msg_drv(priv)) 2734 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n", 2735 priv->ingress_cgr.cgrid, priv->mac_dev->addr); 2736 2737 priv->use_ingress_cgr = true; 2738 2739 out_error: 2740 return err; 2741 } 2742 2743 static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl) 2744 { 2745 u16 headroom; 2746 2747 /* The frame headroom must accommodate: 2748 * - the driver private data area 2749 * - parse results, hash results, timestamp if selected 2750 * If either hash results or time stamp are selected, both will 2751 * be copied to/from the frame headroom, as TS is located between PR and 2752 * HR in the IC and IC copy size has a granularity of 16bytes 2753 * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM) 2754 * 2755 * Also make sure the headroom is a multiple of data_align bytes 2756 */ 2757 headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE + 2758 DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE); 2759 2760 return DPAA_FD_DATA_ALIGNMENT ? ALIGN(headroom, 2761 DPAA_FD_DATA_ALIGNMENT) : 2762 headroom; 2763 } 2764 2765 static int dpaa_eth_probe(struct platform_device *pdev) 2766 { 2767 struct dpaa_bp *dpaa_bps[DPAA_BPS_NUM] = {NULL}; 2768 struct net_device *net_dev = NULL; 2769 struct dpaa_fq *dpaa_fq, *tmp; 2770 struct dpaa_priv *priv = NULL; 2771 struct fm_port_fqs port_fqs; 2772 struct mac_device *mac_dev; 2773 int err = 0, i, channel; 2774 struct device *dev; 2775 2776 /* device used for DMA mapping */ 2777 dev = pdev->dev.parent; 2778 err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(40)); 2779 if (err) { 2780 dev_err(dev, "dma_coerce_mask_and_coherent() failed\n"); 2781 return err; 2782 } 2783 2784 /* Allocate this early, so we can store relevant information in 2785 * the private area 2786 */ 2787 net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM); 2788 if (!net_dev) { 2789 dev_err(dev, "alloc_etherdev_mq() failed\n"); 2790 return -ENOMEM; 2791 } 2792 2793 /* Do this here, so we can be verbose early */ 2794 SET_NETDEV_DEV(net_dev, dev); 2795 dev_set_drvdata(dev, net_dev); 2796 2797 priv = netdev_priv(net_dev); 2798 priv->net_dev = net_dev; 2799 2800 priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT); 2801 2802 mac_dev = dpaa_mac_dev_get(pdev); 2803 if (IS_ERR(mac_dev)) { 2804 dev_err(dev, "dpaa_mac_dev_get() failed\n"); 2805 err = PTR_ERR(mac_dev); 2806 goto free_netdev; 2807 } 2808 2809 /* If fsl_fm_max_frm is set to a higher value than the all-common 1500, 2810 * we choose conservatively and let the user explicitly set a higher 2811 * MTU via ifconfig. Otherwise, the user may end up with different MTUs 2812 * in the same LAN. 2813 * If on the other hand fsl_fm_max_frm has been chosen below 1500, 2814 * start with the maximum allowed. 2815 */ 2816 net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN); 2817 2818 netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n", 2819 net_dev->mtu); 2820 2821 priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */ 2822 priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */ 2823 2824 /* bp init */ 2825 for (i = 0; i < DPAA_BPS_NUM; i++) { 2826 dpaa_bps[i] = dpaa_bp_alloc(dev); 2827 if (IS_ERR(dpaa_bps[i])) { 2828 err = PTR_ERR(dpaa_bps[i]); 2829 goto free_dpaa_bps; 2830 } 2831 /* the raw size of the buffers used for reception */ 2832 dpaa_bps[i]->raw_size = bpool_buffer_raw_size(i, DPAA_BPS_NUM); 2833 /* avoid runtime computations by keeping the usable size here */ 2834 dpaa_bps[i]->size = dpaa_bp_size(dpaa_bps[i]->raw_size); 2835 dpaa_bps[i]->dev = dev; 2836 2837 err = dpaa_bp_alloc_pool(dpaa_bps[i]); 2838 if (err < 0) 2839 goto free_dpaa_bps; 2840 priv->dpaa_bps[i] = dpaa_bps[i]; 2841 } 2842 2843 INIT_LIST_HEAD(&priv->dpaa_fq_list); 2844 2845 memset(&port_fqs, 0, sizeof(port_fqs)); 2846 2847 err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs); 2848 if (err < 0) { 2849 dev_err(dev, "dpaa_alloc_all_fqs() failed\n"); 2850 goto free_dpaa_bps; 2851 } 2852 2853 priv->mac_dev = mac_dev; 2854 2855 channel = dpaa_get_channel(); 2856 if (channel < 0) { 2857 dev_err(dev, "dpaa_get_channel() failed\n"); 2858 err = channel; 2859 goto free_dpaa_bps; 2860 } 2861 2862 priv->channel = (u16)channel; 2863 2864 /* Walk the CPUs with affine portals 2865 * and add this pool channel to each's dequeue mask. 2866 */ 2867 dpaa_eth_add_channel(priv->channel); 2868 2869 dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]); 2870 2871 /* Create a congestion group for this netdev, with 2872 * dynamically-allocated CGR ID. 2873 * Must be executed after probing the MAC, but before 2874 * assigning the egress FQs to the CGRs. 2875 */ 2876 err = dpaa_eth_cgr_init(priv); 2877 if (err < 0) { 2878 dev_err(dev, "Error initializing CGR\n"); 2879 goto free_dpaa_bps; 2880 } 2881 2882 err = dpaa_ingress_cgr_init(priv); 2883 if (err < 0) { 2884 dev_err(dev, "Error initializing ingress CGR\n"); 2885 goto delete_egress_cgr; 2886 } 2887 2888 /* Add the FQs to the interface, and make them active */ 2889 list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) { 2890 err = dpaa_fq_init(dpaa_fq, false); 2891 if (err < 0) 2892 goto free_dpaa_fqs; 2893 } 2894 2895 priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]); 2896 priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]); 2897 2898 /* All real interfaces need their ports initialized */ 2899 err = dpaa_eth_init_ports(mac_dev, dpaa_bps, DPAA_BPS_NUM, &port_fqs, 2900 &priv->buf_layout[0], dev); 2901 if (err) 2902 goto free_dpaa_fqs; 2903 2904 /* Rx traffic distribution based on keygen hashing defaults to on */ 2905 priv->keygen_in_use = true; 2906 2907 priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv); 2908 if (!priv->percpu_priv) { 2909 dev_err(dev, "devm_alloc_percpu() failed\n"); 2910 err = -ENOMEM; 2911 goto free_dpaa_fqs; 2912 } 2913 2914 priv->num_tc = 1; 2915 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM); 2916 2917 /* Initialize NAPI */ 2918 err = dpaa_napi_add(net_dev); 2919 if (err < 0) 2920 goto delete_dpaa_napi; 2921 2922 err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout); 2923 if (err < 0) 2924 goto delete_dpaa_napi; 2925 2926 dpaa_eth_sysfs_init(&net_dev->dev); 2927 2928 netif_info(priv, probe, net_dev, "Probed interface %s\n", 2929 net_dev->name); 2930 2931 return 0; 2932 2933 delete_dpaa_napi: 2934 dpaa_napi_del(net_dev); 2935 free_dpaa_fqs: 2936 dpaa_fq_free(dev, &priv->dpaa_fq_list); 2937 qman_delete_cgr_safe(&priv->ingress_cgr); 2938 qman_release_cgrid(priv->ingress_cgr.cgrid); 2939 delete_egress_cgr: 2940 qman_delete_cgr_safe(&priv->cgr_data.cgr); 2941 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 2942 free_dpaa_bps: 2943 dpaa_bps_free(priv); 2944 free_netdev: 2945 dev_set_drvdata(dev, NULL); 2946 free_netdev(net_dev); 2947 2948 return err; 2949 } 2950 2951 static int dpaa_remove(struct platform_device *pdev) 2952 { 2953 struct net_device *net_dev; 2954 struct dpaa_priv *priv; 2955 struct device *dev; 2956 int err; 2957 2958 dev = pdev->dev.parent; 2959 net_dev = dev_get_drvdata(dev); 2960 2961 priv = netdev_priv(net_dev); 2962 2963 dpaa_eth_sysfs_remove(dev); 2964 2965 dev_set_drvdata(dev, NULL); 2966 unregister_netdev(net_dev); 2967 2968 err = dpaa_fq_free(dev, &priv->dpaa_fq_list); 2969 2970 qman_delete_cgr_safe(&priv->ingress_cgr); 2971 qman_release_cgrid(priv->ingress_cgr.cgrid); 2972 qman_delete_cgr_safe(&priv->cgr_data.cgr); 2973 qman_release_cgrid(priv->cgr_data.cgr.cgrid); 2974 2975 dpaa_napi_del(net_dev); 2976 2977 dpaa_bps_free(priv); 2978 2979 free_netdev(net_dev); 2980 2981 return err; 2982 } 2983 2984 static const struct platform_device_id dpaa_devtype[] = { 2985 { 2986 .name = "dpaa-ethernet", 2987 .driver_data = 0, 2988 }, { 2989 } 2990 }; 2991 MODULE_DEVICE_TABLE(platform, dpaa_devtype); 2992 2993 static struct platform_driver dpaa_driver = { 2994 .driver = { 2995 .name = KBUILD_MODNAME, 2996 }, 2997 .id_table = dpaa_devtype, 2998 .probe = dpaa_eth_probe, 2999 .remove = dpaa_remove 3000 }; 3001 3002 static int __init dpaa_load(void) 3003 { 3004 int err; 3005 3006 pr_debug("FSL DPAA Ethernet driver\n"); 3007 3008 /* initialize dpaa_eth mirror values */ 3009 dpaa_rx_extra_headroom = fman_get_rx_extra_headroom(); 3010 dpaa_max_frm = fman_get_max_frm(); 3011 3012 err = platform_driver_register(&dpaa_driver); 3013 if (err < 0) 3014 pr_err("Error, platform_driver_register() = %d\n", err); 3015 3016 return err; 3017 } 3018 module_init(dpaa_load); 3019 3020 static void __exit dpaa_unload(void) 3021 { 3022 platform_driver_unregister(&dpaa_driver); 3023 3024 /* Only one channel is used and needs to be released after all 3025 * interfaces are removed 3026 */ 3027 dpaa_release_channel(); 3028 } 3029 module_exit(dpaa_unload); 3030 3031 MODULE_LICENSE("Dual BSD/GPL"); 3032 MODULE_DESCRIPTION("FSL DPAA Ethernet driver"); 3033