1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only
25adae51aSIgal Libermanconfig FSL_FMAN
346678612SArnd Bergmann	tristate "FMan support"
42e3db5a4SMadalin Bucur	depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
55adae51aSIgal Liberman	select GENERIC_ALLOCATOR
6*a7c2a32eSSean Anderson	select PHYLINK
7*a7c2a32eSSean Anderson	select PCS_LYNX
80b32e91fSArnd Bergmann	select CRC32
95adae51aSIgal Liberman	default n
105adae51aSIgal Liberman	help
115adae51aSIgal Liberman		Freescale Data-Path Acceleration Architecture Frame Manager
125adae51aSIgal Liberman		(FMan) support
13b281f7b9SMadalin Bucur
14b281f7b9SMadalin Bucurconfig DPAA_ERRATUM_A050385
15b281f7b9SMadalin Bucur	bool
16b281f7b9SMadalin Bucur	depends on ARM64 && FSL_DPAA
17b281f7b9SMadalin Bucur	default y
18b281f7b9SMadalin Bucur	help
19b281f7b9SMadalin Bucur		DPAA FMan erratum A050385 software workaround implementation:
20b281f7b9SMadalin Bucur		align buffers, data start, SG fragment length to avoid FMan DMA
21b281f7b9SMadalin Bucur		splits.
22b281f7b9SMadalin Bucur		FMAN DMA read or writes under heavy traffic load may cause FMAN
23b281f7b9SMadalin Bucur		internal resource leak thus stopping further packet processing.
24b281f7b9SMadalin Bucur		The FMAN internal queue can overflow when FMAN splits single
25b281f7b9SMadalin Bucur		read or write transactions into multiple smaller transactions
26b281f7b9SMadalin Bucur		such that more than 17 AXI transactions are in flight from FMAN
27b281f7b9SMadalin Bucur		to interconnect. When the FMAN internal queue overflows, it can
28b281f7b9SMadalin Bucur		stall further packet processing. The issue can occur with any
29b281f7b9SMadalin Bucur		one of the following three conditions:
30b281f7b9SMadalin Bucur		1. FMAN AXI transaction crosses 4K address boundary (Errata
31b281f7b9SMadalin Bucur		A010022)
32b281f7b9SMadalin Bucur		2. FMAN DMA address for an AXI transaction is not 16 byte
33b281f7b9SMadalin Bucur		aligned, i.e. the last 4 bits of an address are non-zero
34b281f7b9SMadalin Bucur		3. Scatter Gather (SG) frames have more than one SG buffer in
35b281f7b9SMadalin Bucur		the SG list and any one of the buffers, except the last
36b281f7b9SMadalin Bucur		buffer in the SG list has data size that is not a multiple
37b281f7b9SMadalin Bucur		of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
38b281f7b9SMadalin Bucur		With any one of the above three conditions present, there is
39b281f7b9SMadalin Bucur		likelihood of stalled FMAN packet processing, especially under
40b281f7b9SMadalin Bucur		stress with multiple ports injecting line-rate traffic.
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