1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later 2 /* 3 * Copyright 2008 - 2015 Freescale Semiconductor Inc. 4 */ 5 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include "fman_tgec.h" 9 #include "fman.h" 10 #include "mac.h" 11 12 #include <linux/slab.h> 13 #include <linux/bitrev.h> 14 #include <linux/io.h> 15 #include <linux/crc32.h> 16 17 /* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */ 18 #define TGEC_TX_IPG_LENGTH_MASK 0x000003ff 19 20 /* Command and Configuration Register (COMMAND_CONFIG) */ 21 #define CMD_CFG_EN_TIMESTAMP 0x00100000 22 #define CMD_CFG_NO_LEN_CHK 0x00020000 23 #define CMD_CFG_PAUSE_IGNORE 0x00000100 24 #define CMF_CFG_CRC_FWD 0x00000040 25 #define CMD_CFG_PROMIS_EN 0x00000010 26 #define CMD_CFG_RX_EN 0x00000002 27 #define CMD_CFG_TX_EN 0x00000001 28 29 /* Interrupt Mask Register (IMASK) */ 30 #define TGEC_IMASK_MDIO_SCAN_EVENT 0x00010000 31 #define TGEC_IMASK_MDIO_CMD_CMPL 0x00008000 32 #define TGEC_IMASK_REM_FAULT 0x00004000 33 #define TGEC_IMASK_LOC_FAULT 0x00002000 34 #define TGEC_IMASK_TX_ECC_ER 0x00001000 35 #define TGEC_IMASK_TX_FIFO_UNFL 0x00000800 36 #define TGEC_IMASK_TX_FIFO_OVFL 0x00000400 37 #define TGEC_IMASK_TX_ER 0x00000200 38 #define TGEC_IMASK_RX_FIFO_OVFL 0x00000100 39 #define TGEC_IMASK_RX_ECC_ER 0x00000080 40 #define TGEC_IMASK_RX_JAB_FRM 0x00000040 41 #define TGEC_IMASK_RX_OVRSZ_FRM 0x00000020 42 #define TGEC_IMASK_RX_RUNT_FRM 0x00000010 43 #define TGEC_IMASK_RX_FRAG_FRM 0x00000008 44 #define TGEC_IMASK_RX_LEN_ER 0x00000004 45 #define TGEC_IMASK_RX_CRC_ER 0x00000002 46 #define TGEC_IMASK_RX_ALIGN_ER 0x00000001 47 48 /* Hashtable Control Register (HASHTABLE_CTRL) */ 49 #define TGEC_HASH_MCAST_SHIFT 23 50 #define TGEC_HASH_MCAST_EN 0x00000200 51 #define TGEC_HASH_ADR_MSK 0x000001ff 52 53 #define DEFAULT_TX_IPG_LENGTH 12 54 #define DEFAULT_MAX_FRAME_LENGTH 0x600 55 #define DEFAULT_PAUSE_QUANT 0xf000 56 57 /* number of pattern match registers (entries) */ 58 #define TGEC_NUM_OF_PADDRS 1 59 60 /* Group address bit indication */ 61 #define GROUP_ADDRESS 0x0000010000000000LL 62 63 /* Hash table size (= 32 bits*8 regs) */ 64 #define TGEC_HASH_TABLE_SIZE 512 65 66 /* tGEC memory map */ 67 struct tgec_regs { 68 u32 tgec_id; /* 0x000 Controller ID */ 69 u32 reserved001[1]; /* 0x004 */ 70 u32 command_config; /* 0x008 Control and configuration */ 71 u32 mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */ 72 u32 mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */ 73 u32 maxfrm; /* 0x014 Maximum frame length */ 74 u32 pause_quant; /* 0x018 Pause quanta */ 75 u32 rx_fifo_sections; /* 0x01c */ 76 u32 tx_fifo_sections; /* 0x020 */ 77 u32 rx_fifo_almost_f_e; /* 0x024 */ 78 u32 tx_fifo_almost_f_e; /* 0x028 */ 79 u32 hashtable_ctrl; /* 0x02c Hash table control */ 80 u32 mdio_cfg_status; /* 0x030 */ 81 u32 mdio_command; /* 0x034 */ 82 u32 mdio_data; /* 0x038 */ 83 u32 mdio_regaddr; /* 0x03c */ 84 u32 status; /* 0x040 */ 85 u32 tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */ 86 u32 mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */ 87 u32 mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */ 88 u32 rx_fifo_ptr_rd; /* 0x050 */ 89 u32 rx_fifo_ptr_wr; /* 0x054 */ 90 u32 tx_fifo_ptr_rd; /* 0x058 */ 91 u32 tx_fifo_ptr_wr; /* 0x05c */ 92 u32 imask; /* 0x060 Interrupt mask */ 93 u32 ievent; /* 0x064 Interrupt event */ 94 u32 udp_port; /* 0x068 Defines a UDP Port number */ 95 u32 type_1588v2; /* 0x06c Type field for 1588v2 */ 96 u32 reserved070[4]; /* 0x070 */ 97 /* 10Ge Statistics Counter */ 98 u32 tfrm_u; /* 80 aFramesTransmittedOK */ 99 u32 tfrm_l; /* 84 aFramesTransmittedOK */ 100 u32 rfrm_u; /* 88 aFramesReceivedOK */ 101 u32 rfrm_l; /* 8c aFramesReceivedOK */ 102 u32 rfcs_u; /* 90 aFrameCheckSequenceErrors */ 103 u32 rfcs_l; /* 94 aFrameCheckSequenceErrors */ 104 u32 raln_u; /* 98 aAlignmentErrors */ 105 u32 raln_l; /* 9c aAlignmentErrors */ 106 u32 txpf_u; /* A0 aPAUSEMACCtrlFramesTransmitted */ 107 u32 txpf_l; /* A4 aPAUSEMACCtrlFramesTransmitted */ 108 u32 rxpf_u; /* A8 aPAUSEMACCtrlFramesReceived */ 109 u32 rxpf_l; /* Ac aPAUSEMACCtrlFramesReceived */ 110 u32 rlong_u; /* B0 aFrameTooLongErrors */ 111 u32 rlong_l; /* B4 aFrameTooLongErrors */ 112 u32 rflr_u; /* B8 aInRangeLengthErrors */ 113 u32 rflr_l; /* Bc aInRangeLengthErrors */ 114 u32 tvlan_u; /* C0 VLANTransmittedOK */ 115 u32 tvlan_l; /* C4 VLANTransmittedOK */ 116 u32 rvlan_u; /* C8 VLANReceivedOK */ 117 u32 rvlan_l; /* Cc VLANReceivedOK */ 118 u32 toct_u; /* D0 if_out_octets */ 119 u32 toct_l; /* D4 if_out_octets */ 120 u32 roct_u; /* D8 if_in_octets */ 121 u32 roct_l; /* Dc if_in_octets */ 122 u32 ruca_u; /* E0 if_in_ucast_pkts */ 123 u32 ruca_l; /* E4 if_in_ucast_pkts */ 124 u32 rmca_u; /* E8 ifInMulticastPkts */ 125 u32 rmca_l; /* Ec ifInMulticastPkts */ 126 u32 rbca_u; /* F0 ifInBroadcastPkts */ 127 u32 rbca_l; /* F4 ifInBroadcastPkts */ 128 u32 terr_u; /* F8 if_out_errors */ 129 u32 terr_l; /* Fc if_out_errors */ 130 u32 reserved100[2]; /* 100-108 */ 131 u32 tuca_u; /* 108 if_out_ucast_pkts */ 132 u32 tuca_l; /* 10c if_out_ucast_pkts */ 133 u32 tmca_u; /* 110 ifOutMulticastPkts */ 134 u32 tmca_l; /* 114 ifOutMulticastPkts */ 135 u32 tbca_u; /* 118 ifOutBroadcastPkts */ 136 u32 tbca_l; /* 11c ifOutBroadcastPkts */ 137 u32 rdrp_u; /* 120 etherStatsDropEvents */ 138 u32 rdrp_l; /* 124 etherStatsDropEvents */ 139 u32 reoct_u; /* 128 etherStatsOctets */ 140 u32 reoct_l; /* 12c etherStatsOctets */ 141 u32 rpkt_u; /* 130 etherStatsPkts */ 142 u32 rpkt_l; /* 134 etherStatsPkts */ 143 u32 trund_u; /* 138 etherStatsUndersizePkts */ 144 u32 trund_l; /* 13c etherStatsUndersizePkts */ 145 u32 r64_u; /* 140 etherStatsPkts64Octets */ 146 u32 r64_l; /* 144 etherStatsPkts64Octets */ 147 u32 r127_u; /* 148 etherStatsPkts65to127Octets */ 148 u32 r127_l; /* 14c etherStatsPkts65to127Octets */ 149 u32 r255_u; /* 150 etherStatsPkts128to255Octets */ 150 u32 r255_l; /* 154 etherStatsPkts128to255Octets */ 151 u32 r511_u; /* 158 etherStatsPkts256to511Octets */ 152 u32 r511_l; /* 15c etherStatsPkts256to511Octets */ 153 u32 r1023_u; /* 160 etherStatsPkts512to1023Octets */ 154 u32 r1023_l; /* 164 etherStatsPkts512to1023Octets */ 155 u32 r1518_u; /* 168 etherStatsPkts1024to1518Octets */ 156 u32 r1518_l; /* 16c etherStatsPkts1024to1518Octets */ 157 u32 r1519x_u; /* 170 etherStatsPkts1519toX */ 158 u32 r1519x_l; /* 174 etherStatsPkts1519toX */ 159 u32 trovr_u; /* 178 etherStatsOversizePkts */ 160 u32 trovr_l; /* 17c etherStatsOversizePkts */ 161 u32 trjbr_u; /* 180 etherStatsJabbers */ 162 u32 trjbr_l; /* 184 etherStatsJabbers */ 163 u32 trfrg_u; /* 188 etherStatsFragments */ 164 u32 trfrg_l; /* 18C etherStatsFragments */ 165 u32 rerr_u; /* 190 if_in_errors */ 166 u32 rerr_l; /* 194 if_in_errors */ 167 }; 168 169 struct tgec_cfg { 170 bool pause_ignore; 171 bool promiscuous_mode_enable; 172 u16 max_frame_length; 173 u16 pause_quant; 174 u32 tx_ipg_length; 175 }; 176 177 struct fman_mac { 178 /* Pointer to the memory mapped registers. */ 179 struct tgec_regs __iomem *regs; 180 /* MAC address of device; */ 181 u64 addr; 182 u16 max_speed; 183 struct mac_device *dev_id; /* device cookie used by the exception cbs */ 184 fman_mac_exception_cb *exception_cb; 185 fman_mac_exception_cb *event_cb; 186 /* pointer to driver's global address hash table */ 187 struct eth_hash_t *multicast_addr_hash; 188 /* pointer to driver's individual address hash table */ 189 struct eth_hash_t *unicast_addr_hash; 190 u8 mac_id; 191 u32 exceptions; 192 struct tgec_cfg *cfg; 193 void *fm; 194 struct fman_rev_info fm_rev_info; 195 bool allmulti_enabled; 196 }; 197 198 static void set_mac_address(struct tgec_regs __iomem *regs, const u8 *adr) 199 { 200 u32 tmp0, tmp1; 201 202 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24); 203 tmp1 = (u32)(adr[4] | adr[5] << 8); 204 iowrite32be(tmp0, ®s->mac_addr_0); 205 iowrite32be(tmp1, ®s->mac_addr_1); 206 } 207 208 static void set_dflts(struct tgec_cfg *cfg) 209 { 210 cfg->promiscuous_mode_enable = false; 211 cfg->pause_ignore = false; 212 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; 213 cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH; 214 cfg->pause_quant = DEFAULT_PAUSE_QUANT; 215 } 216 217 static int init(struct tgec_regs __iomem *regs, struct tgec_cfg *cfg, 218 u32 exception_mask) 219 { 220 u32 tmp; 221 222 /* Config */ 223 tmp = CMF_CFG_CRC_FWD; 224 if (cfg->promiscuous_mode_enable) 225 tmp |= CMD_CFG_PROMIS_EN; 226 if (cfg->pause_ignore) 227 tmp |= CMD_CFG_PAUSE_IGNORE; 228 /* Payload length check disable */ 229 tmp |= CMD_CFG_NO_LEN_CHK; 230 iowrite32be(tmp, ®s->command_config); 231 232 /* Max Frame Length */ 233 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm); 234 /* Pause Time */ 235 iowrite32be(cfg->pause_quant, ®s->pause_quant); 236 237 /* clear all pending events and set-up interrupts */ 238 iowrite32be(0xffffffff, ®s->ievent); 239 iowrite32be(ioread32be(®s->imask) | exception_mask, ®s->imask); 240 241 return 0; 242 } 243 244 static int check_init_parameters(struct fman_mac *tgec) 245 { 246 if (tgec->max_speed < SPEED_10000) { 247 pr_err("10G MAC driver only support 10G speed\n"); 248 return -EINVAL; 249 } 250 if (!tgec->exception_cb) { 251 pr_err("uninitialized exception_cb\n"); 252 return -EINVAL; 253 } 254 if (!tgec->event_cb) { 255 pr_err("uninitialized event_cb\n"); 256 return -EINVAL; 257 } 258 259 return 0; 260 } 261 262 static int get_exception_flag(enum fman_mac_exceptions exception) 263 { 264 u32 bit_mask; 265 266 switch (exception) { 267 case FM_MAC_EX_10G_MDIO_SCAN_EVENT: 268 bit_mask = TGEC_IMASK_MDIO_SCAN_EVENT; 269 break; 270 case FM_MAC_EX_10G_MDIO_CMD_CMPL: 271 bit_mask = TGEC_IMASK_MDIO_CMD_CMPL; 272 break; 273 case FM_MAC_EX_10G_REM_FAULT: 274 bit_mask = TGEC_IMASK_REM_FAULT; 275 break; 276 case FM_MAC_EX_10G_LOC_FAULT: 277 bit_mask = TGEC_IMASK_LOC_FAULT; 278 break; 279 case FM_MAC_EX_10G_TX_ECC_ER: 280 bit_mask = TGEC_IMASK_TX_ECC_ER; 281 break; 282 case FM_MAC_EX_10G_TX_FIFO_UNFL: 283 bit_mask = TGEC_IMASK_TX_FIFO_UNFL; 284 break; 285 case FM_MAC_EX_10G_TX_FIFO_OVFL: 286 bit_mask = TGEC_IMASK_TX_FIFO_OVFL; 287 break; 288 case FM_MAC_EX_10G_TX_ER: 289 bit_mask = TGEC_IMASK_TX_ER; 290 break; 291 case FM_MAC_EX_10G_RX_FIFO_OVFL: 292 bit_mask = TGEC_IMASK_RX_FIFO_OVFL; 293 break; 294 case FM_MAC_EX_10G_RX_ECC_ER: 295 bit_mask = TGEC_IMASK_RX_ECC_ER; 296 break; 297 case FM_MAC_EX_10G_RX_JAB_FRM: 298 bit_mask = TGEC_IMASK_RX_JAB_FRM; 299 break; 300 case FM_MAC_EX_10G_RX_OVRSZ_FRM: 301 bit_mask = TGEC_IMASK_RX_OVRSZ_FRM; 302 break; 303 case FM_MAC_EX_10G_RX_RUNT_FRM: 304 bit_mask = TGEC_IMASK_RX_RUNT_FRM; 305 break; 306 case FM_MAC_EX_10G_RX_FRAG_FRM: 307 bit_mask = TGEC_IMASK_RX_FRAG_FRM; 308 break; 309 case FM_MAC_EX_10G_RX_LEN_ER: 310 bit_mask = TGEC_IMASK_RX_LEN_ER; 311 break; 312 case FM_MAC_EX_10G_RX_CRC_ER: 313 bit_mask = TGEC_IMASK_RX_CRC_ER; 314 break; 315 case FM_MAC_EX_10G_RX_ALIGN_ER: 316 bit_mask = TGEC_IMASK_RX_ALIGN_ER; 317 break; 318 default: 319 bit_mask = 0; 320 break; 321 } 322 323 return bit_mask; 324 } 325 326 static void tgec_err_exception(void *handle) 327 { 328 struct fman_mac *tgec = (struct fman_mac *)handle; 329 struct tgec_regs __iomem *regs = tgec->regs; 330 u32 event; 331 332 /* do not handle MDIO events */ 333 event = ioread32be(®s->ievent) & 334 ~(TGEC_IMASK_MDIO_SCAN_EVENT | 335 TGEC_IMASK_MDIO_CMD_CMPL); 336 337 event &= ioread32be(®s->imask); 338 339 iowrite32be(event, ®s->ievent); 340 341 if (event & TGEC_IMASK_REM_FAULT) 342 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_REM_FAULT); 343 if (event & TGEC_IMASK_LOC_FAULT) 344 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_LOC_FAULT); 345 if (event & TGEC_IMASK_TX_ECC_ER) 346 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_ECC_ER); 347 if (event & TGEC_IMASK_TX_FIFO_UNFL) 348 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_FIFO_UNFL); 349 if (event & TGEC_IMASK_TX_FIFO_OVFL) 350 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_FIFO_OVFL); 351 if (event & TGEC_IMASK_TX_ER) 352 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_ER); 353 if (event & TGEC_IMASK_RX_FIFO_OVFL) 354 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_FIFO_OVFL); 355 if (event & TGEC_IMASK_RX_ECC_ER) 356 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_ECC_ER); 357 if (event & TGEC_IMASK_RX_JAB_FRM) 358 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_JAB_FRM); 359 if (event & TGEC_IMASK_RX_OVRSZ_FRM) 360 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_OVRSZ_FRM); 361 if (event & TGEC_IMASK_RX_RUNT_FRM) 362 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_RUNT_FRM); 363 if (event & TGEC_IMASK_RX_FRAG_FRM) 364 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_FRAG_FRM); 365 if (event & TGEC_IMASK_RX_LEN_ER) 366 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_LEN_ER); 367 if (event & TGEC_IMASK_RX_CRC_ER) 368 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_CRC_ER); 369 if (event & TGEC_IMASK_RX_ALIGN_ER) 370 tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_ALIGN_ER); 371 } 372 373 static void free_init_resources(struct fman_mac *tgec) 374 { 375 fman_unregister_intr(tgec->fm, FMAN_MOD_MAC, tgec->mac_id, 376 FMAN_INTR_TYPE_ERR); 377 378 /* release the driver's group hash table */ 379 free_hash_table(tgec->multicast_addr_hash); 380 tgec->multicast_addr_hash = NULL; 381 382 /* release the driver's individual hash table */ 383 free_hash_table(tgec->unicast_addr_hash); 384 tgec->unicast_addr_hash = NULL; 385 } 386 387 static bool is_init_done(struct tgec_cfg *cfg) 388 { 389 /* Checks if tGEC driver parameters were initialized */ 390 if (!cfg) 391 return true; 392 393 return false; 394 } 395 396 static int tgec_enable(struct fman_mac *tgec) 397 { 398 struct tgec_regs __iomem *regs = tgec->regs; 399 u32 tmp; 400 401 if (!is_init_done(tgec->cfg)) 402 return -EINVAL; 403 404 tmp = ioread32be(®s->command_config); 405 tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN; 406 iowrite32be(tmp, ®s->command_config); 407 408 return 0; 409 } 410 411 static void tgec_disable(struct fman_mac *tgec) 412 { 413 struct tgec_regs __iomem *regs = tgec->regs; 414 u32 tmp; 415 416 WARN_ON_ONCE(!is_init_done(tgec->cfg)); 417 418 tmp = ioread32be(®s->command_config); 419 tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN); 420 iowrite32be(tmp, ®s->command_config); 421 } 422 423 static int tgec_set_promiscuous(struct fman_mac *tgec, bool new_val) 424 { 425 struct tgec_regs __iomem *regs = tgec->regs; 426 u32 tmp; 427 428 if (!is_init_done(tgec->cfg)) 429 return -EINVAL; 430 431 tmp = ioread32be(®s->command_config); 432 if (new_val) 433 tmp |= CMD_CFG_PROMIS_EN; 434 else 435 tmp &= ~CMD_CFG_PROMIS_EN; 436 iowrite32be(tmp, ®s->command_config); 437 438 return 0; 439 } 440 441 static int tgec_set_tx_pause_frames(struct fman_mac *tgec, 442 u8 __maybe_unused priority, u16 pause_time, 443 u16 __maybe_unused thresh_time) 444 { 445 struct tgec_regs __iomem *regs = tgec->regs; 446 447 if (!is_init_done(tgec->cfg)) 448 return -EINVAL; 449 450 iowrite32be((u32)pause_time, ®s->pause_quant); 451 452 return 0; 453 } 454 455 static int tgec_accept_rx_pause_frames(struct fman_mac *tgec, bool en) 456 { 457 struct tgec_regs __iomem *regs = tgec->regs; 458 u32 tmp; 459 460 if (!is_init_done(tgec->cfg)) 461 return -EINVAL; 462 463 tmp = ioread32be(®s->command_config); 464 if (!en) 465 tmp |= CMD_CFG_PAUSE_IGNORE; 466 else 467 tmp &= ~CMD_CFG_PAUSE_IGNORE; 468 iowrite32be(tmp, ®s->command_config); 469 470 return 0; 471 } 472 473 static int tgec_modify_mac_address(struct fman_mac *tgec, 474 const enet_addr_t *p_enet_addr) 475 { 476 if (!is_init_done(tgec->cfg)) 477 return -EINVAL; 478 479 tgec->addr = ENET_ADDR_TO_UINT64(*p_enet_addr); 480 set_mac_address(tgec->regs, (const u8 *)(*p_enet_addr)); 481 482 return 0; 483 } 484 485 static int tgec_add_hash_mac_address(struct fman_mac *tgec, 486 enet_addr_t *eth_addr) 487 { 488 struct tgec_regs __iomem *regs = tgec->regs; 489 struct eth_hash_entry *hash_entry; 490 u32 crc = 0xFFFFFFFF, hash; 491 u64 addr; 492 493 if (!is_init_done(tgec->cfg)) 494 return -EINVAL; 495 496 addr = ENET_ADDR_TO_UINT64(*eth_addr); 497 498 if (!(addr & GROUP_ADDRESS)) { 499 /* Unicast addresses not supported in hash */ 500 pr_err("Unicast Address\n"); 501 return -EINVAL; 502 } 503 /* CRC calculation */ 504 crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN); 505 crc = bitrev32(crc); 506 /* Take 9 MSB bits */ 507 hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; 508 509 /* Create element to be added to the driver hash table */ 510 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC); 511 if (!hash_entry) 512 return -ENOMEM; 513 hash_entry->addr = addr; 514 INIT_LIST_HEAD(&hash_entry->node); 515 516 list_add_tail(&hash_entry->node, 517 &tgec->multicast_addr_hash->lsts[hash]); 518 iowrite32be((hash | TGEC_HASH_MCAST_EN), ®s->hashtable_ctrl); 519 520 return 0; 521 } 522 523 static int tgec_set_allmulti(struct fman_mac *tgec, bool enable) 524 { 525 u32 entry; 526 struct tgec_regs __iomem *regs = tgec->regs; 527 528 if (!is_init_done(tgec->cfg)) 529 return -EINVAL; 530 531 if (enable) { 532 for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++) 533 iowrite32be(entry | TGEC_HASH_MCAST_EN, 534 ®s->hashtable_ctrl); 535 } else { 536 for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++) 537 iowrite32be(entry & ~TGEC_HASH_MCAST_EN, 538 ®s->hashtable_ctrl); 539 } 540 541 tgec->allmulti_enabled = enable; 542 543 return 0; 544 } 545 546 static int tgec_set_tstamp(struct fman_mac *tgec, bool enable) 547 { 548 struct tgec_regs __iomem *regs = tgec->regs; 549 u32 tmp; 550 551 if (!is_init_done(tgec->cfg)) 552 return -EINVAL; 553 554 tmp = ioread32be(®s->command_config); 555 556 if (enable) 557 tmp |= CMD_CFG_EN_TIMESTAMP; 558 else 559 tmp &= ~CMD_CFG_EN_TIMESTAMP; 560 561 iowrite32be(tmp, ®s->command_config); 562 563 return 0; 564 } 565 566 static int tgec_del_hash_mac_address(struct fman_mac *tgec, 567 enet_addr_t *eth_addr) 568 { 569 struct tgec_regs __iomem *regs = tgec->regs; 570 struct eth_hash_entry *hash_entry = NULL; 571 struct list_head *pos; 572 u32 crc = 0xFFFFFFFF, hash; 573 u64 addr; 574 575 if (!is_init_done(tgec->cfg)) 576 return -EINVAL; 577 578 addr = ((*(u64 *)eth_addr) >> 16); 579 580 /* CRC calculation */ 581 crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN); 582 crc = bitrev32(crc); 583 /* Take 9 MSB bits */ 584 hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; 585 586 list_for_each(pos, &tgec->multicast_addr_hash->lsts[hash]) { 587 hash_entry = ETH_HASH_ENTRY_OBJ(pos); 588 if (hash_entry && hash_entry->addr == addr) { 589 list_del_init(&hash_entry->node); 590 kfree(hash_entry); 591 break; 592 } 593 } 594 595 if (!tgec->allmulti_enabled) { 596 if (list_empty(&tgec->multicast_addr_hash->lsts[hash])) 597 iowrite32be((hash & ~TGEC_HASH_MCAST_EN), 598 ®s->hashtable_ctrl); 599 } 600 601 return 0; 602 } 603 604 static void tgec_adjust_link(struct mac_device *mac_dev) 605 { 606 struct phy_device *phy_dev = mac_dev->phy_dev; 607 608 mac_dev->update_speed(mac_dev, phy_dev->speed); 609 } 610 611 static int tgec_set_exception(struct fman_mac *tgec, 612 enum fman_mac_exceptions exception, bool enable) 613 { 614 struct tgec_regs __iomem *regs = tgec->regs; 615 u32 bit_mask = 0; 616 617 if (!is_init_done(tgec->cfg)) 618 return -EINVAL; 619 620 bit_mask = get_exception_flag(exception); 621 if (bit_mask) { 622 if (enable) 623 tgec->exceptions |= bit_mask; 624 else 625 tgec->exceptions &= ~bit_mask; 626 } else { 627 pr_err("Undefined exception\n"); 628 return -EINVAL; 629 } 630 if (enable) 631 iowrite32be(ioread32be(®s->imask) | bit_mask, ®s->imask); 632 else 633 iowrite32be(ioread32be(®s->imask) & ~bit_mask, ®s->imask); 634 635 return 0; 636 } 637 638 static int tgec_init(struct fman_mac *tgec) 639 { 640 struct tgec_cfg *cfg; 641 enet_addr_t eth_addr; 642 int err; 643 644 if (is_init_done(tgec->cfg)) 645 return -EINVAL; 646 647 if (DEFAULT_RESET_ON_INIT && 648 (fman_reset_mac(tgec->fm, tgec->mac_id) != 0)) { 649 pr_err("Can't reset MAC!\n"); 650 return -EINVAL; 651 } 652 653 err = check_init_parameters(tgec); 654 if (err) 655 return err; 656 657 cfg = tgec->cfg; 658 659 if (tgec->addr) { 660 MAKE_ENET_ADDR_FROM_UINT64(tgec->addr, eth_addr); 661 set_mac_address(tgec->regs, (const u8 *)eth_addr); 662 } 663 664 /* interrupts */ 665 /* FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005 Errata workaround */ 666 if (tgec->fm_rev_info.major <= 2) 667 tgec->exceptions &= ~(TGEC_IMASK_REM_FAULT | 668 TGEC_IMASK_LOC_FAULT); 669 670 err = init(tgec->regs, cfg, tgec->exceptions); 671 if (err) { 672 free_init_resources(tgec); 673 pr_err("TGEC version doesn't support this i/f mode\n"); 674 return err; 675 } 676 677 /* Max Frame Length */ 678 err = fman_set_mac_max_frame(tgec->fm, tgec->mac_id, 679 cfg->max_frame_length); 680 if (err) { 681 pr_err("Setting max frame length FAILED\n"); 682 free_init_resources(tgec); 683 return -EINVAL; 684 } 685 686 /* FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 Errata workaround */ 687 if (tgec->fm_rev_info.major == 2) { 688 struct tgec_regs __iomem *regs = tgec->regs; 689 u32 tmp; 690 691 /* restore the default tx ipg Length */ 692 tmp = (ioread32be(®s->tx_ipg_len) & 693 ~TGEC_TX_IPG_LENGTH_MASK) | 12; 694 695 iowrite32be(tmp, ®s->tx_ipg_len); 696 } 697 698 tgec->multicast_addr_hash = alloc_hash_table(TGEC_HASH_TABLE_SIZE); 699 if (!tgec->multicast_addr_hash) { 700 free_init_resources(tgec); 701 pr_err("allocation hash table is FAILED\n"); 702 return -ENOMEM; 703 } 704 705 tgec->unicast_addr_hash = alloc_hash_table(TGEC_HASH_TABLE_SIZE); 706 if (!tgec->unicast_addr_hash) { 707 free_init_resources(tgec); 708 pr_err("allocation hash table is FAILED\n"); 709 return -ENOMEM; 710 } 711 712 fman_register_intr(tgec->fm, FMAN_MOD_MAC, tgec->mac_id, 713 FMAN_INTR_TYPE_ERR, tgec_err_exception, tgec); 714 715 kfree(cfg); 716 tgec->cfg = NULL; 717 718 return 0; 719 } 720 721 static int tgec_free(struct fman_mac *tgec) 722 { 723 free_init_resources(tgec); 724 725 kfree(tgec->cfg); 726 kfree(tgec); 727 728 return 0; 729 } 730 731 static struct fman_mac *tgec_config(struct mac_device *mac_dev, 732 struct fman_mac_params *params) 733 { 734 struct fman_mac *tgec; 735 struct tgec_cfg *cfg; 736 737 /* allocate memory for the UCC GETH data structure. */ 738 tgec = kzalloc(sizeof(*tgec), GFP_KERNEL); 739 if (!tgec) 740 return NULL; 741 742 /* allocate memory for the 10G MAC driver parameters data structure. */ 743 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 744 if (!cfg) { 745 tgec_free(tgec); 746 return NULL; 747 } 748 749 /* Plant parameter structure pointer */ 750 tgec->cfg = cfg; 751 752 set_dflts(cfg); 753 754 tgec->regs = mac_dev->vaddr; 755 tgec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr); 756 tgec->max_speed = params->max_speed; 757 tgec->mac_id = params->mac_id; 758 tgec->exceptions = (TGEC_IMASK_MDIO_SCAN_EVENT | 759 TGEC_IMASK_REM_FAULT | 760 TGEC_IMASK_LOC_FAULT | 761 TGEC_IMASK_TX_ECC_ER | 762 TGEC_IMASK_TX_FIFO_UNFL | 763 TGEC_IMASK_TX_FIFO_OVFL | 764 TGEC_IMASK_TX_ER | 765 TGEC_IMASK_RX_FIFO_OVFL | 766 TGEC_IMASK_RX_ECC_ER | 767 TGEC_IMASK_RX_JAB_FRM | 768 TGEC_IMASK_RX_OVRSZ_FRM | 769 TGEC_IMASK_RX_RUNT_FRM | 770 TGEC_IMASK_RX_FRAG_FRM | 771 TGEC_IMASK_RX_CRC_ER | 772 TGEC_IMASK_RX_ALIGN_ER); 773 tgec->exception_cb = params->exception_cb; 774 tgec->event_cb = params->event_cb; 775 tgec->dev_id = mac_dev; 776 tgec->fm = params->fm; 777 778 /* Save FMan revision */ 779 fman_get_revision(tgec->fm, &tgec->fm_rev_info); 780 781 return tgec; 782 } 783 784 int tgec_initialization(struct mac_device *mac_dev, 785 struct device_node *mac_node, 786 struct fman_mac_params *params) 787 { 788 int err; 789 struct fman_mac *tgec; 790 791 mac_dev->set_promisc = tgec_set_promiscuous; 792 mac_dev->change_addr = tgec_modify_mac_address; 793 mac_dev->add_hash_mac_addr = tgec_add_hash_mac_address; 794 mac_dev->remove_hash_mac_addr = tgec_del_hash_mac_address; 795 mac_dev->set_tx_pause = tgec_set_tx_pause_frames; 796 mac_dev->set_rx_pause = tgec_accept_rx_pause_frames; 797 mac_dev->set_exception = tgec_set_exception; 798 mac_dev->set_allmulti = tgec_set_allmulti; 799 mac_dev->set_tstamp = tgec_set_tstamp; 800 mac_dev->set_multi = fman_set_multi; 801 mac_dev->adjust_link = tgec_adjust_link; 802 mac_dev->enable = tgec_enable; 803 mac_dev->disable = tgec_disable; 804 805 mac_dev->fman_mac = tgec_config(mac_dev, params); 806 if (!mac_dev->fman_mac) { 807 err = -EINVAL; 808 goto _return; 809 } 810 811 tgec = mac_dev->fman_mac; 812 tgec->cfg->max_frame_length = fman_get_max_frm(); 813 err = tgec_init(tgec); 814 if (err < 0) 815 goto _return_fm_mac_free; 816 817 /* For 10G MAC, disable Tx ECC exception */ 818 err = tgec_set_exception(tgec, FM_MAC_EX_10G_TX_ECC_ER, false); 819 if (err < 0) 820 goto _return_fm_mac_free; 821 822 pr_info("FMan XGEC version: 0x%08x\n", 823 ioread32be(&tgec->regs->tgec_id)); 824 goto _return; 825 826 _return_fm_mac_free: 827 tgec_free(mac_dev->fman_mac); 828 829 _return: 830 return err; 831 } 832