1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2021-2021 Hisilicon Limited. 3 4 #ifndef __HCLGE_COMM_CMD_H 5 #define __HCLGE_COMM_CMD_H 6 #include <linux/types.h> 7 8 #include "hnae3.h" 9 10 #define HCLGE_COMM_CMD_FLAG_IN BIT(0) 11 #define HCLGE_COMM_CMD_FLAG_NEXT BIT(2) 12 #define HCLGE_COMM_CMD_FLAG_WR BIT(3) 13 #define HCLGE_COMM_CMD_FLAG_NO_INTR BIT(4) 14 15 #define HCLGE_COMM_SEND_SYNC(flag) \ 16 ((flag) & HCLGE_COMM_CMD_FLAG_NO_INTR) 17 18 #define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 0 19 #define HCLGE_COMM_NCSI_ERROR_REPORT_EN_B 1 20 #define HCLGE_COMM_PHY_IMP_EN_B 2 21 #define HCLGE_COMM_MAC_STATS_EXT_EN_B 3 22 #define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B 4 23 #define HCLGE_COMM_LLRS_FEC_EN_B 5 24 25 #define hclge_comm_dev_phy_imp_supported(ae_dev) \ 26 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (ae_dev)->caps) 27 28 #define HCLGE_COMM_TYPE_CRQ 0 29 #define HCLGE_COMM_TYPE_CSQ 1 30 31 #define HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME 200 32 33 /* bar registers for cmdq */ 34 #define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x27000 35 #define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x27004 36 #define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x27008 37 #define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x27010 38 #define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x27014 39 #define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x27018 40 #define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701C 41 #define HCLGE_COMM_NIC_CRQ_DEPTH_REG 0x27020 42 #define HCLGE_COMM_NIC_CRQ_TAIL_REG 0x27024 43 #define HCLGE_COMM_NIC_CRQ_HEAD_REG 0x27028 44 /* Vector0 interrupt CMDQ event source register(RW) */ 45 #define HCLGE_COMM_VECTOR0_CMDQ_SRC_REG 0x27100 46 /* Vector0 interrupt CMDQ event status register(RO) */ 47 #define HCLGE_COMM_VECTOR0_CMDQ_STATE_REG 0x27104 48 #define HCLGE_COMM_CMDQ_INTR_EN_REG 0x27108 49 #define HCLGE_COMM_CMDQ_INTR_GEN_REG 0x2710C 50 #define HCLGE_COMM_CMDQ_INTR_STS_REG 0x27104 51 52 /* this bit indicates that the driver is ready for hardware reset */ 53 #define HCLGE_COMM_NIC_SW_RST_RDY_B 16 54 #define HCLGE_COMM_NIC_SW_RST_RDY BIT(HCLGE_COMM_NIC_SW_RST_RDY_B) 55 #define HCLGE_COMM_NIC_CMQ_DESC_NUM_S 3 56 #define HCLGE_COMM_NIC_CMQ_DESC_NUM 1024 57 #define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT 30000 58 #define HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS 500000 59 60 enum hclge_opcode_type { 61 /* Generic commands */ 62 HCLGE_OPC_QUERY_FW_VER = 0x0001, 63 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 64 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 65 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 66 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 67 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 68 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 69 HCLGE_OPC_PF_RST_DONE = 0x0026, 70 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027, 71 72 HCLGE_OPC_STATS_64_BIT = 0x0030, 73 HCLGE_OPC_STATS_32_BIT = 0x0031, 74 HCLGE_OPC_STATS_MAC = 0x0032, 75 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 76 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 77 78 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 79 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 80 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 81 HCLGE_OPC_DFX_BD_NUM = 0x0043, 82 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 83 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 84 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 85 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 86 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 87 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 88 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 89 HCLGE_OPC_DFX_RTC_REG = 0x004B, 90 HCLGE_OPC_DFX_PPP_REG = 0x004C, 91 HCLGE_OPC_DFX_RCB_REG = 0x004D, 92 HCLGE_OPC_DFX_TQP_REG = 0x004E, 93 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 94 95 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050, 96 97 /* MAC command */ 98 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 99 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 100 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 101 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 102 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 103 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, 104 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, 105 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, 106 HCLGE_OPC_COMMON_LOOPBACK = 0x0315, 107 HCLGE_OPC_QUERY_FEC_STATS = 0x0316, 108 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, 109 HCLGE_OPC_QUERY_ROH_TYPE_INFO = 0x0389, 110 111 /* PTP commands */ 112 HCLGE_OPC_PTP_INT_EN = 0x0501, 113 HCLGE_OPC_PTP_MODE_CFG = 0x0507, 114 115 /* PFC/Pause commands */ 116 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 117 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 118 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 119 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 120 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 121 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 122 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 123 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 124 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 125 HCLGE_OPC_QOS_MAP = 0x070A, 126 127 /* ETS/scheduler commands */ 128 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 129 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 130 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 131 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 132 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 133 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 134 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 135 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 136 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 137 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 138 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 139 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 140 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 141 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 142 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 143 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 144 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 145 HCLGE_OPC_TM_NODES = 0x0816, 146 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 147 HCLGE_OPC_QSET_DFX_STS = 0x0844, 148 HCLGE_OPC_PRI_DFX_STS = 0x0845, 149 HCLGE_OPC_PG_DFX_STS = 0x0846, 150 HCLGE_OPC_PORT_DFX_STS = 0x0847, 151 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 152 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 153 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 154 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 155 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 156 HCLGE_OPC_TM_FLUSH = 0x0872, 157 158 /* Packet buffer allocate commands */ 159 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 160 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 161 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 162 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 163 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 164 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 165 166 /* TQP management command */ 167 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 168 169 /* TQP commands */ 170 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 171 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 172 HCLGE_OPC_QUERY_TX_STATS = 0x0B03, 173 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 174 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 175 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 176 HCLGE_OPC_QUERY_RX_STATS = 0x0B13, 177 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 178 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 179 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 180 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 181 182 /* PPU commands */ 183 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A, 184 185 /* TSO command */ 186 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 187 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 188 189 /* RSS commands */ 190 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 191 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 192 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 193 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 194 195 /* Promisuous mode command */ 196 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 197 198 /* Vlan offload commands */ 199 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 200 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 201 202 /* Interrupts commands */ 203 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 204 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 205 206 /* MAC commands */ 207 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 208 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 209 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 210 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 211 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 212 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 213 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 214 215 /* MAC VLAN commands */ 216 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033, 217 218 /* VLAN commands */ 219 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 220 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 221 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 222 HCLGE_OPC_PORT_VLAN_BYPASS = 0x1103, 223 224 /* Flow Director commands */ 225 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 226 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 227 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 228 HCLGE_OPC_FD_TCAM_OP = 0x1203, 229 HCLGE_OPC_FD_AD_OP = 0x1204, 230 HCLGE_OPC_FD_CNT_OP = 0x1205, 231 HCLGE_OPC_FD_USER_DEF_OP = 0x1207, 232 HCLGE_OPC_FD_QB_CTRL = 0x1210, 233 HCLGE_OPC_FD_QB_AD_OP = 0x1211, 234 235 /* MDIO command */ 236 HCLGE_OPC_MDIO_CONFIG = 0x1900, 237 238 /* QCN commands */ 239 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 240 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 241 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03, 242 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 243 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 244 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 245 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 246 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 247 248 /* Mailbox command */ 249 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 250 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001, 251 252 /* Led command */ 253 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 254 255 /* clear hardware resource command */ 256 HCLGE_OPC_CLEAR_HW_RESOURCE = 0x700B, 257 258 /* NCL config command */ 259 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, 260 261 /* IMP stats command */ 262 HCLGE_OPC_IMP_STATS_BD = 0x7012, 263 HCLGE_OPC_IMP_STATS_INFO = 0x7013, 264 HCLGE_OPC_IMP_COMPAT_CFG = 0x701A, 265 266 /* SFP command */ 267 HCLGE_OPC_GET_SFP_EEPROM = 0x7100, 268 HCLGE_OPC_GET_SFP_EXIST = 0x7101, 269 HCLGE_OPC_GET_SFP_INFO = 0x7104, 270 271 /* Error INT commands */ 272 HCLGE_MAC_COMMON_INT_EN = 0x030E, 273 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 274 HCLGE_SSU_ECC_INT_CMD = 0x0989, 275 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 276 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 277 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 278 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 279 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 280 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 281 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 282 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 283 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 284 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 285 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 286 HCLGE_QUERY_ALL_ERR_BD_NUM = 0x1516, 287 HCLGE_QUERY_ALL_ERR_INFO = 0x1517, 288 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 289 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 290 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 291 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585, 292 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586, 293 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 294 HCLGE_IGU_COMMON_INT_EN = 0x1806, 295 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 296 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 297 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 298 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 299 HCLGE_OPC_WOL_GET_SUPPORTED_MODE = 0x2201, 300 HCLGE_OPC_WOL_CFG = 0x2202, 301 HCLGE_NCSI_INT_EN = 0x2401, 302 303 /* ROH MAC commands */ 304 HCLGE_OPC_MAC_ADDR_CHECK = 0x9004, 305 306 /* PHY command */ 307 HCLGE_OPC_PHY_LINK_KSETTING = 0x7025, 308 HCLGE_OPC_PHY_REG = 0x7026, 309 310 /* Query link diagnosis info command */ 311 HCLGE_OPC_QUERY_LINK_DIAGNOSIS = 0x702A, 312 }; 313 314 enum hclge_comm_cmd_return_status { 315 HCLGE_COMM_CMD_EXEC_SUCCESS = 0, 316 HCLGE_COMM_CMD_NO_AUTH = 1, 317 HCLGE_COMM_CMD_NOT_SUPPORTED = 2, 318 HCLGE_COMM_CMD_QUEUE_FULL = 3, 319 HCLGE_COMM_CMD_NEXT_ERR = 4, 320 HCLGE_COMM_CMD_UNEXE_ERR = 5, 321 HCLGE_COMM_CMD_PARA_ERR = 6, 322 HCLGE_COMM_CMD_RESULT_ERR = 7, 323 HCLGE_COMM_CMD_TIMEOUT = 8, 324 HCLGE_COMM_CMD_HILINK_ERR = 9, 325 HCLGE_COMM_CMD_QUEUE_ILLEGAL = 10, 326 HCLGE_COMM_CMD_INVALID = 11, 327 }; 328 329 enum HCLGE_COMM_CAP_BITS { 330 HCLGE_COMM_CAP_UDP_GSO_B, 331 HCLGE_COMM_CAP_QB_B, 332 HCLGE_COMM_CAP_FD_FORWARD_TC_B, 333 HCLGE_COMM_CAP_PTP_B, 334 HCLGE_COMM_CAP_INT_QL_B, 335 HCLGE_COMM_CAP_HW_TX_CSUM_B, 336 HCLGE_COMM_CAP_TX_PUSH_B, 337 HCLGE_COMM_CAP_PHY_IMP_B, 338 HCLGE_COMM_CAP_TQP_TXRX_INDEP_B, 339 HCLGE_COMM_CAP_HW_PAD_B, 340 HCLGE_COMM_CAP_STASH_B, 341 HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B, 342 HCLGE_COMM_CAP_RAS_IMP_B = 12, 343 HCLGE_COMM_CAP_FEC_B = 13, 344 HCLGE_COMM_CAP_PAUSE_B = 14, 345 HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15, 346 HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17, 347 HCLGE_COMM_CAP_CQ_B = 18, 348 HCLGE_COMM_CAP_GRO_B = 20, 349 HCLGE_COMM_CAP_FD_B = 21, 350 HCLGE_COMM_CAP_FEC_STATS_B = 25, 351 HCLGE_COMM_CAP_LANE_NUM_B = 27, 352 HCLGE_COMM_CAP_WOL_B = 28, 353 HCLGE_COMM_CAP_TM_FLUSH_B = 31, 354 }; 355 356 enum HCLGE_COMM_API_CAP_BITS { 357 HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B, 358 }; 359 360 /* capabilities bits map between imp firmware and local driver */ 361 struct hclge_comm_caps_bit_map { 362 u16 imp_bit; 363 u16 local_bit; 364 }; 365 366 struct hclge_cmdq_tx_timeout_map { 367 u32 opcode; 368 u32 tx_timeout; 369 }; 370 371 struct hclge_comm_firmware_compat_cmd { 372 __le32 compat; 373 u8 rsv[20]; 374 }; 375 376 enum hclge_comm_cmd_state { 377 HCLGE_COMM_STATE_CMD_DISABLE, 378 }; 379 380 struct hclge_comm_errcode { 381 u32 imp_errcode; 382 int common_errno; 383 }; 384 385 #define HCLGE_COMM_QUERY_CAP_LENGTH 3 386 struct hclge_comm_query_version_cmd { 387 __le32 firmware; 388 __le32 hardware; 389 __le32 api_caps; 390 __le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH]; /* capabilities of device */ 391 }; 392 393 #define HCLGE_DESC_DATA_LEN 6 394 struct hclge_desc { 395 __le16 opcode; 396 __le16 flag; 397 __le16 retval; 398 __le16 rsv; 399 __le32 data[HCLGE_DESC_DATA_LEN]; 400 }; 401 402 struct hclge_comm_cmq_ring { 403 dma_addr_t desc_dma_addr; 404 struct hclge_desc *desc; 405 struct pci_dev *pdev; 406 u32 head; 407 u32 tail; 408 409 u16 buf_size; 410 u16 desc_num; 411 int next_to_use; 412 int next_to_clean; 413 u8 ring_type; /* cmq ring type */ 414 spinlock_t lock; /* Command queue lock */ 415 }; 416 417 enum hclge_comm_cmd_status { 418 HCLGE_COMM_STATUS_SUCCESS = 0, 419 HCLGE_COMM_ERR_CSQ_FULL = -1, 420 HCLGE_COMM_ERR_CSQ_TIMEOUT = -2, 421 HCLGE_COMM_ERR_CSQ_ERROR = -3, 422 }; 423 424 struct hclge_comm_cmq { 425 struct hclge_comm_cmq_ring csq; 426 struct hclge_comm_cmq_ring crq; 427 u16 tx_timeout; 428 enum hclge_comm_cmd_status last_status; 429 }; 430 431 struct hclge_comm_hw { 432 void __iomem *io_base; 433 void __iomem *mem_base; 434 struct hclge_comm_cmq cmq; 435 unsigned long comm_state; 436 }; 437 438 static inline void hclge_comm_write_reg(void __iomem *base, u32 reg, u32 value) 439 { 440 writel(value, base + reg); 441 } 442 443 static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg) 444 { 445 u8 __iomem *reg_addr = READ_ONCE(base); 446 447 return readl(reg_addr + reg); 448 } 449 450 #define hclge_comm_write_dev(a, reg, value) \ 451 hclge_comm_write_reg((a)->io_base, reg, value) 452 #define hclge_comm_read_dev(a, reg) \ 453 hclge_comm_read_reg((a)->io_base, reg) 454 455 void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw); 456 int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev, 457 struct hclge_comm_hw *hw, 458 u32 *fw_version, bool is_pf); 459 int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type); 460 int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 461 int num); 462 void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 463 int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev, 464 struct hclge_comm_hw *hw, bool en); 465 void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring); 466 void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc, 467 enum hclge_opcode_type opcode, 468 bool is_read); 469 void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev, 470 struct hclge_comm_hw *hw); 471 int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw); 472 int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw, 473 u32 *fw_version, bool is_pf, 474 unsigned long reset_pending); 475 476 #endif 477