1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2021-2021 Hisilicon Limited.
3 
4 #ifndef __HCLGE_COMM_TQP_STATS_H
5 #define __HCLGE_COMM_TQP_STATS_H
6 #include <linux/types.h>
7 #include <linux/etherdevice.h>
8 #include "hnae3.h"
9 
10 /* each tqp has TX & RX two queues */
11 #define HCLGE_COMM_QUEUE_PAIR_SIZE 2
12 
13 /* TQP stats */
14 struct hclge_comm_tqp_stats {
15 	/* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
16 	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
17 	/* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
18 	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
19 };
20 
21 struct hclge_comm_tqp {
22 	/* copy of device pointer from pci_dev,
23 	 * used when perform DMA mapping
24 	 */
25 	struct device *dev;
26 	struct hnae3_queue q;
27 	struct hclge_comm_tqp_stats tqp_stats;
28 	u16 index;	/* Global index in a NIC controller */
29 
30 	bool alloced;
31 };
32 
33 u64 *hclge_comm_tqps_get_stats(struct hnae3_handle *handle, u64 *data);
34 int hclge_comm_tqps_get_sset_count(struct hnae3_handle *handle);
35 u8 *hclge_comm_tqps_get_strings(struct hnae3_handle *handle, u8 *data);
36 void hclge_comm_reset_tqp_stats(struct hnae3_handle *handle);
37 int hclge_comm_tqps_update_stats(struct hnae3_handle *handle,
38 				 struct hclge_comm_hw *hw);
39 #endif
40