1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/gro.h> 21 #include <net/ip6_checksum.h> 22 #include <net/pkt_cls.h> 23 #include <net/tcp.h> 24 #include <net/vxlan.h> 25 #include <net/geneve.h> 26 27 #include "hnae3.h" 28 #include "hns3_enet.h" 29 /* All hns3 tracepoints are defined by the include below, which 30 * must be included exactly once across the whole kernel with 31 * CREATE_TRACE_POINTS defined 32 */ 33 #define CREATE_TRACE_POINTS 34 #include "hns3_trace.h" 35 36 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift)) 37 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 38 39 #define hns3_rl_err(fmt, ...) \ 40 do { \ 41 if (net_ratelimit()) \ 42 netdev_err(fmt, ##__VA_ARGS__); \ 43 } while (0) 44 45 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 46 47 static const char hns3_driver_name[] = "hns3"; 48 static const char hns3_driver_string[] = 49 "Hisilicon Ethernet Network Driver for Hip08 Family"; 50 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 51 static struct hnae3_client client; 52 53 static int debug = -1; 54 module_param(debug, int, 0); 55 MODULE_PARM_DESC(debug, " Network interface message level setting"); 56 57 static unsigned int tx_sgl = 1; 58 module_param(tx_sgl, uint, 0600); 59 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping"); 60 61 static bool page_pool_enabled = true; 62 module_param(page_pool_enabled, bool, 0400); 63 64 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \ 65 sizeof(struct sg_table)) 66 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \ 67 dma_get_cache_alignment()) 68 69 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 70 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 71 72 #define HNS3_INNER_VLAN_TAG 1 73 #define HNS3_OUTER_VLAN_TAG 2 74 75 #define HNS3_MIN_TX_LEN 33U 76 #define HNS3_MIN_TUN_PKT_LEN 65U 77 78 /* hns3_pci_tbl - PCI Device ID Table 79 * 80 * Last entry must be all 0s 81 * 82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 83 * Class, Class Mask, private data (not used) } 84 */ 85 static const struct pci_device_id hns3_pci_tbl[] = { 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 89 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 91 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 92 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 93 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 94 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 95 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 96 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 97 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 98 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 99 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 100 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 102 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 103 /* required last entry */ 104 {0,} 105 }; 106 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 107 108 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \ 109 { ptype, \ 110 l, \ 111 CHECKSUM_##s, \ 112 HNS3_L3_TYPE_##t, \ 113 1 } 114 115 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \ 116 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 } 117 118 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = { 119 HNS3_RX_PTYPE_UNUSED_ENTRY(0), 120 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP), 121 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP), 122 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP), 123 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL), 124 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL), 125 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL), 126 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM), 127 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL), 128 HNS3_RX_PTYPE_UNUSED_ENTRY(9), 129 HNS3_RX_PTYPE_UNUSED_ENTRY(10), 130 HNS3_RX_PTYPE_UNUSED_ENTRY(11), 131 HNS3_RX_PTYPE_UNUSED_ENTRY(12), 132 HNS3_RX_PTYPE_UNUSED_ENTRY(13), 133 HNS3_RX_PTYPE_UNUSED_ENTRY(14), 134 HNS3_RX_PTYPE_UNUSED_ENTRY(15), 135 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL), 136 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4), 137 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4), 138 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4), 139 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4), 140 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4), 141 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4), 142 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4), 143 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4), 144 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4), 145 HNS3_RX_PTYPE_UNUSED_ENTRY(26), 146 HNS3_RX_PTYPE_UNUSED_ENTRY(27), 147 HNS3_RX_PTYPE_UNUSED_ENTRY(28), 148 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL), 149 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL), 150 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4), 151 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4), 152 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4), 153 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4), 154 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4), 155 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4), 156 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4), 157 HNS3_RX_PTYPE_UNUSED_ENTRY(38), 158 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6), 159 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6), 160 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6), 161 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6), 162 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6), 163 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6), 164 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6), 165 HNS3_RX_PTYPE_UNUSED_ENTRY(46), 166 HNS3_RX_PTYPE_UNUSED_ENTRY(47), 167 HNS3_RX_PTYPE_UNUSED_ENTRY(48), 168 HNS3_RX_PTYPE_UNUSED_ENTRY(49), 169 HNS3_RX_PTYPE_UNUSED_ENTRY(50), 170 HNS3_RX_PTYPE_UNUSED_ENTRY(51), 171 HNS3_RX_PTYPE_UNUSED_ENTRY(52), 172 HNS3_RX_PTYPE_UNUSED_ENTRY(53), 173 HNS3_RX_PTYPE_UNUSED_ENTRY(54), 174 HNS3_RX_PTYPE_UNUSED_ENTRY(55), 175 HNS3_RX_PTYPE_UNUSED_ENTRY(56), 176 HNS3_RX_PTYPE_UNUSED_ENTRY(57), 177 HNS3_RX_PTYPE_UNUSED_ENTRY(58), 178 HNS3_RX_PTYPE_UNUSED_ENTRY(59), 179 HNS3_RX_PTYPE_UNUSED_ENTRY(60), 180 HNS3_RX_PTYPE_UNUSED_ENTRY(61), 181 HNS3_RX_PTYPE_UNUSED_ENTRY(62), 182 HNS3_RX_PTYPE_UNUSED_ENTRY(63), 183 HNS3_RX_PTYPE_UNUSED_ENTRY(64), 184 HNS3_RX_PTYPE_UNUSED_ENTRY(65), 185 HNS3_RX_PTYPE_UNUSED_ENTRY(66), 186 HNS3_RX_PTYPE_UNUSED_ENTRY(67), 187 HNS3_RX_PTYPE_UNUSED_ENTRY(68), 188 HNS3_RX_PTYPE_UNUSED_ENTRY(69), 189 HNS3_RX_PTYPE_UNUSED_ENTRY(70), 190 HNS3_RX_PTYPE_UNUSED_ENTRY(71), 191 HNS3_RX_PTYPE_UNUSED_ENTRY(72), 192 HNS3_RX_PTYPE_UNUSED_ENTRY(73), 193 HNS3_RX_PTYPE_UNUSED_ENTRY(74), 194 HNS3_RX_PTYPE_UNUSED_ENTRY(75), 195 HNS3_RX_PTYPE_UNUSED_ENTRY(76), 196 HNS3_RX_PTYPE_UNUSED_ENTRY(77), 197 HNS3_RX_PTYPE_UNUSED_ENTRY(78), 198 HNS3_RX_PTYPE_UNUSED_ENTRY(79), 199 HNS3_RX_PTYPE_UNUSED_ENTRY(80), 200 HNS3_RX_PTYPE_UNUSED_ENTRY(81), 201 HNS3_RX_PTYPE_UNUSED_ENTRY(82), 202 HNS3_RX_PTYPE_UNUSED_ENTRY(83), 203 HNS3_RX_PTYPE_UNUSED_ENTRY(84), 204 HNS3_RX_PTYPE_UNUSED_ENTRY(85), 205 HNS3_RX_PTYPE_UNUSED_ENTRY(86), 206 HNS3_RX_PTYPE_UNUSED_ENTRY(87), 207 HNS3_RX_PTYPE_UNUSED_ENTRY(88), 208 HNS3_RX_PTYPE_UNUSED_ENTRY(89), 209 HNS3_RX_PTYPE_UNUSED_ENTRY(90), 210 HNS3_RX_PTYPE_UNUSED_ENTRY(91), 211 HNS3_RX_PTYPE_UNUSED_ENTRY(92), 212 HNS3_RX_PTYPE_UNUSED_ENTRY(93), 213 HNS3_RX_PTYPE_UNUSED_ENTRY(94), 214 HNS3_RX_PTYPE_UNUSED_ENTRY(95), 215 HNS3_RX_PTYPE_UNUSED_ENTRY(96), 216 HNS3_RX_PTYPE_UNUSED_ENTRY(97), 217 HNS3_RX_PTYPE_UNUSED_ENTRY(98), 218 HNS3_RX_PTYPE_UNUSED_ENTRY(99), 219 HNS3_RX_PTYPE_UNUSED_ENTRY(100), 220 HNS3_RX_PTYPE_UNUSED_ENTRY(101), 221 HNS3_RX_PTYPE_UNUSED_ENTRY(102), 222 HNS3_RX_PTYPE_UNUSED_ENTRY(103), 223 HNS3_RX_PTYPE_UNUSED_ENTRY(104), 224 HNS3_RX_PTYPE_UNUSED_ENTRY(105), 225 HNS3_RX_PTYPE_UNUSED_ENTRY(106), 226 HNS3_RX_PTYPE_UNUSED_ENTRY(107), 227 HNS3_RX_PTYPE_UNUSED_ENTRY(108), 228 HNS3_RX_PTYPE_UNUSED_ENTRY(109), 229 HNS3_RX_PTYPE_UNUSED_ENTRY(110), 230 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6), 231 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6), 232 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6), 233 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6), 234 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6), 235 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6), 236 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6), 237 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6), 238 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6), 239 HNS3_RX_PTYPE_UNUSED_ENTRY(120), 240 HNS3_RX_PTYPE_UNUSED_ENTRY(121), 241 HNS3_RX_PTYPE_UNUSED_ENTRY(122), 242 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL), 243 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL), 244 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4), 245 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4), 246 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4), 247 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4), 248 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4), 249 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4), 250 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4), 251 HNS3_RX_PTYPE_UNUSED_ENTRY(132), 252 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6), 253 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6), 254 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6), 255 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6), 256 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6), 257 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6), 258 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6), 259 HNS3_RX_PTYPE_UNUSED_ENTRY(140), 260 HNS3_RX_PTYPE_UNUSED_ENTRY(141), 261 HNS3_RX_PTYPE_UNUSED_ENTRY(142), 262 HNS3_RX_PTYPE_UNUSED_ENTRY(143), 263 HNS3_RX_PTYPE_UNUSED_ENTRY(144), 264 HNS3_RX_PTYPE_UNUSED_ENTRY(145), 265 HNS3_RX_PTYPE_UNUSED_ENTRY(146), 266 HNS3_RX_PTYPE_UNUSED_ENTRY(147), 267 HNS3_RX_PTYPE_UNUSED_ENTRY(148), 268 HNS3_RX_PTYPE_UNUSED_ENTRY(149), 269 HNS3_RX_PTYPE_UNUSED_ENTRY(150), 270 HNS3_RX_PTYPE_UNUSED_ENTRY(151), 271 HNS3_RX_PTYPE_UNUSED_ENTRY(152), 272 HNS3_RX_PTYPE_UNUSED_ENTRY(153), 273 HNS3_RX_PTYPE_UNUSED_ENTRY(154), 274 HNS3_RX_PTYPE_UNUSED_ENTRY(155), 275 HNS3_RX_PTYPE_UNUSED_ENTRY(156), 276 HNS3_RX_PTYPE_UNUSED_ENTRY(157), 277 HNS3_RX_PTYPE_UNUSED_ENTRY(158), 278 HNS3_RX_PTYPE_UNUSED_ENTRY(159), 279 HNS3_RX_PTYPE_UNUSED_ENTRY(160), 280 HNS3_RX_PTYPE_UNUSED_ENTRY(161), 281 HNS3_RX_PTYPE_UNUSED_ENTRY(162), 282 HNS3_RX_PTYPE_UNUSED_ENTRY(163), 283 HNS3_RX_PTYPE_UNUSED_ENTRY(164), 284 HNS3_RX_PTYPE_UNUSED_ENTRY(165), 285 HNS3_RX_PTYPE_UNUSED_ENTRY(166), 286 HNS3_RX_PTYPE_UNUSED_ENTRY(167), 287 HNS3_RX_PTYPE_UNUSED_ENTRY(168), 288 HNS3_RX_PTYPE_UNUSED_ENTRY(169), 289 HNS3_RX_PTYPE_UNUSED_ENTRY(170), 290 HNS3_RX_PTYPE_UNUSED_ENTRY(171), 291 HNS3_RX_PTYPE_UNUSED_ENTRY(172), 292 HNS3_RX_PTYPE_UNUSED_ENTRY(173), 293 HNS3_RX_PTYPE_UNUSED_ENTRY(174), 294 HNS3_RX_PTYPE_UNUSED_ENTRY(175), 295 HNS3_RX_PTYPE_UNUSED_ENTRY(176), 296 HNS3_RX_PTYPE_UNUSED_ENTRY(177), 297 HNS3_RX_PTYPE_UNUSED_ENTRY(178), 298 HNS3_RX_PTYPE_UNUSED_ENTRY(179), 299 HNS3_RX_PTYPE_UNUSED_ENTRY(180), 300 HNS3_RX_PTYPE_UNUSED_ENTRY(181), 301 HNS3_RX_PTYPE_UNUSED_ENTRY(182), 302 HNS3_RX_PTYPE_UNUSED_ENTRY(183), 303 HNS3_RX_PTYPE_UNUSED_ENTRY(184), 304 HNS3_RX_PTYPE_UNUSED_ENTRY(185), 305 HNS3_RX_PTYPE_UNUSED_ENTRY(186), 306 HNS3_RX_PTYPE_UNUSED_ENTRY(187), 307 HNS3_RX_PTYPE_UNUSED_ENTRY(188), 308 HNS3_RX_PTYPE_UNUSED_ENTRY(189), 309 HNS3_RX_PTYPE_UNUSED_ENTRY(190), 310 HNS3_RX_PTYPE_UNUSED_ENTRY(191), 311 HNS3_RX_PTYPE_UNUSED_ENTRY(192), 312 HNS3_RX_PTYPE_UNUSED_ENTRY(193), 313 HNS3_RX_PTYPE_UNUSED_ENTRY(194), 314 HNS3_RX_PTYPE_UNUSED_ENTRY(195), 315 HNS3_RX_PTYPE_UNUSED_ENTRY(196), 316 HNS3_RX_PTYPE_UNUSED_ENTRY(197), 317 HNS3_RX_PTYPE_UNUSED_ENTRY(198), 318 HNS3_RX_PTYPE_UNUSED_ENTRY(199), 319 HNS3_RX_PTYPE_UNUSED_ENTRY(200), 320 HNS3_RX_PTYPE_UNUSED_ENTRY(201), 321 HNS3_RX_PTYPE_UNUSED_ENTRY(202), 322 HNS3_RX_PTYPE_UNUSED_ENTRY(203), 323 HNS3_RX_PTYPE_UNUSED_ENTRY(204), 324 HNS3_RX_PTYPE_UNUSED_ENTRY(205), 325 HNS3_RX_PTYPE_UNUSED_ENTRY(206), 326 HNS3_RX_PTYPE_UNUSED_ENTRY(207), 327 HNS3_RX_PTYPE_UNUSED_ENTRY(208), 328 HNS3_RX_PTYPE_UNUSED_ENTRY(209), 329 HNS3_RX_PTYPE_UNUSED_ENTRY(210), 330 HNS3_RX_PTYPE_UNUSED_ENTRY(211), 331 HNS3_RX_PTYPE_UNUSED_ENTRY(212), 332 HNS3_RX_PTYPE_UNUSED_ENTRY(213), 333 HNS3_RX_PTYPE_UNUSED_ENTRY(214), 334 HNS3_RX_PTYPE_UNUSED_ENTRY(215), 335 HNS3_RX_PTYPE_UNUSED_ENTRY(216), 336 HNS3_RX_PTYPE_UNUSED_ENTRY(217), 337 HNS3_RX_PTYPE_UNUSED_ENTRY(218), 338 HNS3_RX_PTYPE_UNUSED_ENTRY(219), 339 HNS3_RX_PTYPE_UNUSED_ENTRY(220), 340 HNS3_RX_PTYPE_UNUSED_ENTRY(221), 341 HNS3_RX_PTYPE_UNUSED_ENTRY(222), 342 HNS3_RX_PTYPE_UNUSED_ENTRY(223), 343 HNS3_RX_PTYPE_UNUSED_ENTRY(224), 344 HNS3_RX_PTYPE_UNUSED_ENTRY(225), 345 HNS3_RX_PTYPE_UNUSED_ENTRY(226), 346 HNS3_RX_PTYPE_UNUSED_ENTRY(227), 347 HNS3_RX_PTYPE_UNUSED_ENTRY(228), 348 HNS3_RX_PTYPE_UNUSED_ENTRY(229), 349 HNS3_RX_PTYPE_UNUSED_ENTRY(230), 350 HNS3_RX_PTYPE_UNUSED_ENTRY(231), 351 HNS3_RX_PTYPE_UNUSED_ENTRY(232), 352 HNS3_RX_PTYPE_UNUSED_ENTRY(233), 353 HNS3_RX_PTYPE_UNUSED_ENTRY(234), 354 HNS3_RX_PTYPE_UNUSED_ENTRY(235), 355 HNS3_RX_PTYPE_UNUSED_ENTRY(236), 356 HNS3_RX_PTYPE_UNUSED_ENTRY(237), 357 HNS3_RX_PTYPE_UNUSED_ENTRY(238), 358 HNS3_RX_PTYPE_UNUSED_ENTRY(239), 359 HNS3_RX_PTYPE_UNUSED_ENTRY(240), 360 HNS3_RX_PTYPE_UNUSED_ENTRY(241), 361 HNS3_RX_PTYPE_UNUSED_ENTRY(242), 362 HNS3_RX_PTYPE_UNUSED_ENTRY(243), 363 HNS3_RX_PTYPE_UNUSED_ENTRY(244), 364 HNS3_RX_PTYPE_UNUSED_ENTRY(245), 365 HNS3_RX_PTYPE_UNUSED_ENTRY(246), 366 HNS3_RX_PTYPE_UNUSED_ENTRY(247), 367 HNS3_RX_PTYPE_UNUSED_ENTRY(248), 368 HNS3_RX_PTYPE_UNUSED_ENTRY(249), 369 HNS3_RX_PTYPE_UNUSED_ENTRY(250), 370 HNS3_RX_PTYPE_UNUSED_ENTRY(251), 371 HNS3_RX_PTYPE_UNUSED_ENTRY(252), 372 HNS3_RX_PTYPE_UNUSED_ENTRY(253), 373 HNS3_RX_PTYPE_UNUSED_ENTRY(254), 374 HNS3_RX_PTYPE_UNUSED_ENTRY(255), 375 }; 376 377 #define HNS3_INVALID_PTYPE \ 378 ARRAY_SIZE(hns3_rx_ptype_tbl) 379 380 static irqreturn_t hns3_irq_handle(int irq, void *vector) 381 { 382 struct hns3_enet_tqp_vector *tqp_vector = vector; 383 384 napi_schedule_irqoff(&tqp_vector->napi); 385 tqp_vector->event_cnt++; 386 387 return IRQ_HANDLED; 388 } 389 390 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 391 { 392 struct hns3_enet_tqp_vector *tqp_vectors; 393 unsigned int i; 394 395 for (i = 0; i < priv->vector_num; i++) { 396 tqp_vectors = &priv->tqp_vector[i]; 397 398 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 399 continue; 400 401 /* clear the affinity mask */ 402 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 403 404 /* release the irq resource */ 405 free_irq(tqp_vectors->vector_irq, tqp_vectors); 406 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 407 } 408 } 409 410 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 411 { 412 struct hns3_enet_tqp_vector *tqp_vectors; 413 int txrx_int_idx = 0; 414 int rx_int_idx = 0; 415 int tx_int_idx = 0; 416 unsigned int i; 417 int ret; 418 419 for (i = 0; i < priv->vector_num; i++) { 420 tqp_vectors = &priv->tqp_vector[i]; 421 422 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 423 continue; 424 425 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 426 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 427 "%s-%s-%s-%d", hns3_driver_name, 428 pci_name(priv->ae_handle->pdev), 429 "TxRx", txrx_int_idx++); 430 txrx_int_idx++; 431 } else if (tqp_vectors->rx_group.ring) { 432 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 433 "%s-%s-%s-%d", hns3_driver_name, 434 pci_name(priv->ae_handle->pdev), 435 "Rx", rx_int_idx++); 436 } else if (tqp_vectors->tx_group.ring) { 437 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 438 "%s-%s-%s-%d", hns3_driver_name, 439 pci_name(priv->ae_handle->pdev), 440 "Tx", tx_int_idx++); 441 } else { 442 /* Skip this unused q_vector */ 443 continue; 444 } 445 446 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 447 448 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 449 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 450 tqp_vectors->name, tqp_vectors); 451 if (ret) { 452 netdev_err(priv->netdev, "request irq(%d) fail\n", 453 tqp_vectors->vector_irq); 454 hns3_nic_uninit_irq(priv); 455 return ret; 456 } 457 458 irq_set_affinity_hint(tqp_vectors->vector_irq, 459 &tqp_vectors->affinity_mask); 460 461 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 462 } 463 464 return 0; 465 } 466 467 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 468 u32 mask_en) 469 { 470 writel(mask_en, tqp_vector->mask_addr); 471 } 472 473 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 474 { 475 napi_enable(&tqp_vector->napi); 476 enable_irq(tqp_vector->vector_irq); 477 478 /* enable vector */ 479 hns3_mask_vector_irq(tqp_vector, 1); 480 } 481 482 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 483 { 484 /* disable vector */ 485 hns3_mask_vector_irq(tqp_vector, 0); 486 487 disable_irq(tqp_vector->vector_irq); 488 napi_disable(&tqp_vector->napi); 489 cancel_work_sync(&tqp_vector->rx_group.dim.work); 490 cancel_work_sync(&tqp_vector->tx_group.dim.work); 491 } 492 493 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 494 u32 rl_value) 495 { 496 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 497 498 /* this defines the configuration for RL (Interrupt Rate Limiter). 499 * Rl defines rate of interrupts i.e. number of interrupts-per-second 500 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 501 */ 502 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 503 !tqp_vector->rx_group.coal.adapt_enable) 504 /* According to the hardware, the range of rl_reg is 505 * 0-59 and the unit is 4. 506 */ 507 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 508 509 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 510 } 511 512 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 513 u32 gl_value) 514 { 515 u32 new_val; 516 517 if (tqp_vector->rx_group.coal.unit_1us) 518 new_val = gl_value | HNS3_INT_GL_1US; 519 else 520 new_val = hns3_gl_usec_to_reg(gl_value); 521 522 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 523 } 524 525 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 526 u32 gl_value) 527 { 528 u32 new_val; 529 530 if (tqp_vector->tx_group.coal.unit_1us) 531 new_val = gl_value | HNS3_INT_GL_1US; 532 else 533 new_val = hns3_gl_usec_to_reg(gl_value); 534 535 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 536 } 537 538 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 539 u32 ql_value) 540 { 541 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 542 } 543 544 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 545 u32 ql_value) 546 { 547 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 548 } 549 550 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 551 struct hns3_nic_priv *priv) 552 { 553 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 554 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 555 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 556 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal; 557 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal; 558 559 tx_coal->adapt_enable = ptx_coal->adapt_enable; 560 rx_coal->adapt_enable = prx_coal->adapt_enable; 561 562 tx_coal->int_gl = ptx_coal->int_gl; 563 rx_coal->int_gl = prx_coal->int_gl; 564 565 rx_coal->flow_level = prx_coal->flow_level; 566 tx_coal->flow_level = ptx_coal->flow_level; 567 568 /* device version above V3(include V3), GL can configure 1us 569 * unit, so uses 1us unit. 570 */ 571 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 572 tx_coal->unit_1us = 1; 573 rx_coal->unit_1us = 1; 574 } 575 576 if (ae_dev->dev_specs.int_ql_max) { 577 tx_coal->ql_enable = 1; 578 rx_coal->ql_enable = 1; 579 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 580 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 581 tx_coal->int_ql = ptx_coal->int_ql; 582 rx_coal->int_ql = prx_coal->int_ql; 583 } 584 } 585 586 static void 587 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 588 struct hns3_nic_priv *priv) 589 { 590 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 591 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 592 struct hnae3_handle *h = priv->ae_handle; 593 594 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 595 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 596 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 597 598 if (tx_coal->ql_enable) 599 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 600 601 if (rx_coal->ql_enable) 602 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 603 } 604 605 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 606 { 607 struct hnae3_handle *h = hns3_get_handle(netdev); 608 struct hnae3_knic_private_info *kinfo = &h->kinfo; 609 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 610 unsigned int queue_size = kinfo->num_tqps; 611 int i, ret; 612 613 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) { 614 netdev_reset_tc(netdev); 615 } else { 616 ret = netdev_set_num_tc(netdev, tc_info->num_tc); 617 if (ret) { 618 netdev_err(netdev, 619 "netdev_set_num_tc fail, ret=%d!\n", ret); 620 return ret; 621 } 622 623 for (i = 0; i < tc_info->num_tc; i++) 624 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i], 625 tc_info->tqp_offset[i]); 626 } 627 628 ret = netif_set_real_num_tx_queues(netdev, queue_size); 629 if (ret) { 630 netdev_err(netdev, 631 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 632 return ret; 633 } 634 635 ret = netif_set_real_num_rx_queues(netdev, queue_size); 636 if (ret) { 637 netdev_err(netdev, 638 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 639 return ret; 640 } 641 642 return 0; 643 } 644 645 u16 hns3_get_max_available_channels(struct hnae3_handle *h) 646 { 647 u16 alloc_tqps, max_rss_size, rss_size; 648 649 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 650 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc; 651 652 return min_t(u16, rss_size, max_rss_size); 653 } 654 655 static void hns3_tqp_enable(struct hnae3_queue *tqp) 656 { 657 u32 rcb_reg; 658 659 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 660 rcb_reg |= BIT(HNS3_RING_EN_B); 661 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 662 } 663 664 static void hns3_tqp_disable(struct hnae3_queue *tqp) 665 { 666 u32 rcb_reg; 667 668 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 669 rcb_reg &= ~BIT(HNS3_RING_EN_B); 670 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 671 } 672 673 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 674 { 675 #ifdef CONFIG_RFS_ACCEL 676 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 677 netdev->rx_cpu_rmap = NULL; 678 #endif 679 } 680 681 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 682 { 683 #ifdef CONFIG_RFS_ACCEL 684 struct hns3_nic_priv *priv = netdev_priv(netdev); 685 struct hns3_enet_tqp_vector *tqp_vector; 686 int i, ret; 687 688 if (!netdev->rx_cpu_rmap) { 689 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 690 if (!netdev->rx_cpu_rmap) 691 return -ENOMEM; 692 } 693 694 for (i = 0; i < priv->vector_num; i++) { 695 tqp_vector = &priv->tqp_vector[i]; 696 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 697 tqp_vector->vector_irq); 698 if (ret) { 699 hns3_free_rx_cpu_rmap(netdev); 700 return ret; 701 } 702 } 703 #endif 704 return 0; 705 } 706 707 static int hns3_nic_net_up(struct net_device *netdev) 708 { 709 struct hns3_nic_priv *priv = netdev_priv(netdev); 710 struct hnae3_handle *h = priv->ae_handle; 711 int i, j; 712 int ret; 713 714 ret = hns3_nic_reset_all_ring(h); 715 if (ret) 716 return ret; 717 718 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 719 720 /* enable the vectors */ 721 for (i = 0; i < priv->vector_num; i++) 722 hns3_vector_enable(&priv->tqp_vector[i]); 723 724 /* enable rcb */ 725 for (j = 0; j < h->kinfo.num_tqps; j++) 726 hns3_tqp_enable(h->kinfo.tqp[j]); 727 728 /* start the ae_dev */ 729 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 730 if (ret) { 731 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 732 while (j--) 733 hns3_tqp_disable(h->kinfo.tqp[j]); 734 735 for (j = i - 1; j >= 0; j--) 736 hns3_vector_disable(&priv->tqp_vector[j]); 737 } 738 739 return ret; 740 } 741 742 static void hns3_config_xps(struct hns3_nic_priv *priv) 743 { 744 int i; 745 746 for (i = 0; i < priv->vector_num; i++) { 747 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 748 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 749 750 while (ring) { 751 int ret; 752 753 ret = netif_set_xps_queue(priv->netdev, 754 &tqp_vector->affinity_mask, 755 ring->tqp->tqp_index); 756 if (ret) 757 netdev_warn(priv->netdev, 758 "set xps queue failed: %d", ret); 759 760 ring = ring->next; 761 } 762 } 763 } 764 765 static int hns3_nic_net_open(struct net_device *netdev) 766 { 767 struct hns3_nic_priv *priv = netdev_priv(netdev); 768 struct hnae3_handle *h = hns3_get_handle(netdev); 769 struct hnae3_knic_private_info *kinfo; 770 int i, ret; 771 772 if (hns3_nic_resetting(netdev)) 773 return -EBUSY; 774 775 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 776 netdev_warn(netdev, "net open repeatedly!\n"); 777 return 0; 778 } 779 780 netif_carrier_off(netdev); 781 782 ret = hns3_nic_set_real_num_queue(netdev); 783 if (ret) 784 return ret; 785 786 ret = hns3_nic_net_up(netdev); 787 if (ret) { 788 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 789 return ret; 790 } 791 792 kinfo = &h->kinfo; 793 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 794 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]); 795 796 if (h->ae_algo->ops->set_timer_task) 797 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 798 799 hns3_config_xps(priv); 800 801 netif_dbg(h, drv, netdev, "net open\n"); 802 803 return 0; 804 } 805 806 static void hns3_reset_tx_queue(struct hnae3_handle *h) 807 { 808 struct net_device *ndev = h->kinfo.netdev; 809 struct hns3_nic_priv *priv = netdev_priv(ndev); 810 struct netdev_queue *dev_queue; 811 u32 i; 812 813 for (i = 0; i < h->kinfo.num_tqps; i++) { 814 dev_queue = netdev_get_tx_queue(ndev, 815 priv->ring[i].queue_index); 816 netdev_tx_reset_queue(dev_queue); 817 } 818 } 819 820 static void hns3_nic_net_down(struct net_device *netdev) 821 { 822 struct hns3_nic_priv *priv = netdev_priv(netdev); 823 struct hnae3_handle *h = hns3_get_handle(netdev); 824 const struct hnae3_ae_ops *ops; 825 int i; 826 827 /* disable vectors */ 828 for (i = 0; i < priv->vector_num; i++) 829 hns3_vector_disable(&priv->tqp_vector[i]); 830 831 /* disable rcb */ 832 for (i = 0; i < h->kinfo.num_tqps; i++) 833 hns3_tqp_disable(h->kinfo.tqp[i]); 834 835 /* stop ae_dev */ 836 ops = priv->ae_handle->ae_algo->ops; 837 if (ops->stop) 838 ops->stop(priv->ae_handle); 839 840 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 841 * during reset process, because driver may not be able 842 * to disable the ring through firmware when downing the netdev. 843 */ 844 if (!hns3_nic_resetting(netdev)) 845 hns3_clear_all_ring(priv->ae_handle, false); 846 847 hns3_reset_tx_queue(priv->ae_handle); 848 } 849 850 static int hns3_nic_net_stop(struct net_device *netdev) 851 { 852 struct hns3_nic_priv *priv = netdev_priv(netdev); 853 struct hnae3_handle *h = hns3_get_handle(netdev); 854 855 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 856 return 0; 857 858 netif_dbg(h, drv, netdev, "net stop\n"); 859 860 if (h->ae_algo->ops->set_timer_task) 861 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 862 863 netif_carrier_off(netdev); 864 netif_tx_disable(netdev); 865 866 hns3_nic_net_down(netdev); 867 868 return 0; 869 } 870 871 static int hns3_nic_uc_sync(struct net_device *netdev, 872 const unsigned char *addr) 873 { 874 struct hnae3_handle *h = hns3_get_handle(netdev); 875 876 if (h->ae_algo->ops->add_uc_addr) 877 return h->ae_algo->ops->add_uc_addr(h, addr); 878 879 return 0; 880 } 881 882 static int hns3_nic_uc_unsync(struct net_device *netdev, 883 const unsigned char *addr) 884 { 885 struct hnae3_handle *h = hns3_get_handle(netdev); 886 887 /* need ignore the request of removing device address, because 888 * we store the device address and other addresses of uc list 889 * in the function's mac filter list. 890 */ 891 if (ether_addr_equal(addr, netdev->dev_addr)) 892 return 0; 893 894 if (h->ae_algo->ops->rm_uc_addr) 895 return h->ae_algo->ops->rm_uc_addr(h, addr); 896 897 return 0; 898 } 899 900 static int hns3_nic_mc_sync(struct net_device *netdev, 901 const unsigned char *addr) 902 { 903 struct hnae3_handle *h = hns3_get_handle(netdev); 904 905 if (h->ae_algo->ops->add_mc_addr) 906 return h->ae_algo->ops->add_mc_addr(h, addr); 907 908 return 0; 909 } 910 911 static int hns3_nic_mc_unsync(struct net_device *netdev, 912 const unsigned char *addr) 913 { 914 struct hnae3_handle *h = hns3_get_handle(netdev); 915 916 if (h->ae_algo->ops->rm_mc_addr) 917 return h->ae_algo->ops->rm_mc_addr(h, addr); 918 919 return 0; 920 } 921 922 static u8 hns3_get_netdev_flags(struct net_device *netdev) 923 { 924 u8 flags = 0; 925 926 if (netdev->flags & IFF_PROMISC) 927 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 928 else if (netdev->flags & IFF_ALLMULTI) 929 flags = HNAE3_USER_MPE; 930 931 return flags; 932 } 933 934 static void hns3_nic_set_rx_mode(struct net_device *netdev) 935 { 936 struct hnae3_handle *h = hns3_get_handle(netdev); 937 u8 new_flags; 938 939 new_flags = hns3_get_netdev_flags(netdev); 940 941 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 942 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 943 944 /* User mode Promisc mode enable and vlan filtering is disabled to 945 * let all packets in. 946 */ 947 h->netdev_flags = new_flags; 948 hns3_request_update_promisc_mode(h); 949 } 950 951 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 952 { 953 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 954 955 if (ops->request_update_promisc_mode) 956 ops->request_update_promisc_mode(handle); 957 } 958 959 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring) 960 { 961 struct hns3_tx_spare *tx_spare = ring->tx_spare; 962 u32 ntc, ntu; 963 964 /* This smp_load_acquire() pairs with smp_store_release() in 965 * hns3_tx_spare_update() called in tx desc cleaning process. 966 */ 967 ntc = smp_load_acquire(&tx_spare->last_to_clean); 968 ntu = tx_spare->next_to_use; 969 970 if (ntc > ntu) 971 return ntc - ntu - 1; 972 973 /* The free tx buffer is divided into two part, so pick the 974 * larger one. 975 */ 976 return max(ntc, tx_spare->len - ntu) - 1; 977 } 978 979 static void hns3_tx_spare_update(struct hns3_enet_ring *ring) 980 { 981 struct hns3_tx_spare *tx_spare = ring->tx_spare; 982 983 if (!tx_spare || 984 tx_spare->last_to_clean == tx_spare->next_to_clean) 985 return; 986 987 /* This smp_store_release() pairs with smp_load_acquire() in 988 * hns3_tx_spare_space() called in xmit process. 989 */ 990 smp_store_release(&tx_spare->last_to_clean, 991 tx_spare->next_to_clean); 992 } 993 994 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring, 995 struct sk_buff *skb, 996 u32 space) 997 { 998 u32 len = skb->len <= ring->tx_copybreak ? skb->len : 999 skb_headlen(skb); 1000 1001 if (len > ring->tx_copybreak) 1002 return false; 1003 1004 if (ALIGN(len, dma_get_cache_alignment()) > space) { 1005 hns3_ring_stats_update(ring, tx_spare_full); 1006 return false; 1007 } 1008 1009 return true; 1010 } 1011 1012 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring, 1013 struct sk_buff *skb, 1014 u32 space) 1015 { 1016 if (skb->len <= ring->tx_copybreak || !tx_sgl || 1017 (!skb_has_frag_list(skb) && 1018 skb_shinfo(skb)->nr_frags < tx_sgl)) 1019 return false; 1020 1021 if (space < HNS3_MAX_SGL_SIZE) { 1022 hns3_ring_stats_update(ring, tx_spare_full); 1023 return false; 1024 } 1025 1026 return true; 1027 } 1028 1029 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring) 1030 { 1031 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size; 1032 struct hns3_tx_spare *tx_spare; 1033 struct page *page; 1034 dma_addr_t dma; 1035 int order; 1036 1037 if (!alloc_size) 1038 return; 1039 1040 order = get_order(alloc_size); 1041 if (order >= MAX_ORDER) { 1042 if (net_ratelimit()) 1043 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n"); 1044 return; 1045 } 1046 1047 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare), 1048 GFP_KERNEL); 1049 if (!tx_spare) { 1050 /* The driver still work without the tx spare buffer */ 1051 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n"); 1052 goto devm_kzalloc_error; 1053 } 1054 1055 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)), 1056 GFP_KERNEL, order); 1057 if (!page) { 1058 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n"); 1059 goto alloc_pages_error; 1060 } 1061 1062 dma = dma_map_page(ring_to_dev(ring), page, 0, 1063 PAGE_SIZE << order, DMA_TO_DEVICE); 1064 if (dma_mapping_error(ring_to_dev(ring), dma)) { 1065 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n"); 1066 goto dma_mapping_error; 1067 } 1068 1069 tx_spare->dma = dma; 1070 tx_spare->buf = page_address(page); 1071 tx_spare->len = PAGE_SIZE << order; 1072 ring->tx_spare = tx_spare; 1073 return; 1074 1075 dma_mapping_error: 1076 put_page(page); 1077 alloc_pages_error: 1078 devm_kfree(ring_to_dev(ring), tx_spare); 1079 devm_kzalloc_error: 1080 ring->tqp->handle->kinfo.tx_spare_buf_size = 0; 1081 } 1082 1083 /* Use hns3_tx_spare_space() to make sure there is enough buffer 1084 * before calling below function to allocate tx buffer. 1085 */ 1086 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring, 1087 unsigned int size, dma_addr_t *dma, 1088 u32 *cb_len) 1089 { 1090 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1091 u32 ntu = tx_spare->next_to_use; 1092 1093 size = ALIGN(size, dma_get_cache_alignment()); 1094 *cb_len = size; 1095 1096 /* Tx spare buffer wraps back here because the end of 1097 * freed tx buffer is not enough. 1098 */ 1099 if (ntu + size > tx_spare->len) { 1100 *cb_len += (tx_spare->len - ntu); 1101 ntu = 0; 1102 } 1103 1104 tx_spare->next_to_use = ntu + size; 1105 if (tx_spare->next_to_use == tx_spare->len) 1106 tx_spare->next_to_use = 0; 1107 1108 *dma = tx_spare->dma + ntu; 1109 1110 return tx_spare->buf + ntu; 1111 } 1112 1113 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len) 1114 { 1115 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1116 1117 if (len > tx_spare->next_to_use) { 1118 len -= tx_spare->next_to_use; 1119 tx_spare->next_to_use = tx_spare->len - len; 1120 } else { 1121 tx_spare->next_to_use -= len; 1122 } 1123 } 1124 1125 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring, 1126 struct hns3_desc_cb *cb) 1127 { 1128 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1129 u32 ntc = tx_spare->next_to_clean; 1130 u32 len = cb->length; 1131 1132 tx_spare->next_to_clean += len; 1133 1134 if (tx_spare->next_to_clean >= tx_spare->len) { 1135 tx_spare->next_to_clean -= tx_spare->len; 1136 1137 if (tx_spare->next_to_clean) { 1138 ntc = 0; 1139 len = tx_spare->next_to_clean; 1140 } 1141 } 1142 1143 /* This tx spare buffer is only really reclaimed after calling 1144 * hns3_tx_spare_update(), so it is still safe to use the info in 1145 * the tx buffer to do the dma sync or sg unmapping after 1146 * tx_spare->next_to_clean is moved forword. 1147 */ 1148 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) { 1149 dma_addr_t dma = tx_spare->dma + ntc; 1150 1151 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len, 1152 DMA_TO_DEVICE); 1153 } else { 1154 struct sg_table *sgt = tx_spare->buf + ntc; 1155 1156 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 1157 DMA_TO_DEVICE); 1158 } 1159 } 1160 1161 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 1162 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes) 1163 { 1164 u32 l4_offset, hdr_len; 1165 union l3_hdr_info l3; 1166 union l4_hdr_info l4; 1167 u32 l4_paylen; 1168 int ret; 1169 1170 if (!skb_is_gso(skb)) 1171 return 0; 1172 1173 ret = skb_cow_head(skb, 0); 1174 if (unlikely(ret < 0)) 1175 return ret; 1176 1177 l3.hdr = skb_network_header(skb); 1178 l4.hdr = skb_transport_header(skb); 1179 1180 /* Software should clear the IPv4's checksum field when tso is 1181 * needed. 1182 */ 1183 if (l3.v4->version == 4) 1184 l3.v4->check = 0; 1185 1186 /* tunnel packet */ 1187 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 1188 SKB_GSO_GRE_CSUM | 1189 SKB_GSO_UDP_TUNNEL | 1190 SKB_GSO_UDP_TUNNEL_CSUM)) { 1191 /* reset l3&l4 pointers from outer to inner headers */ 1192 l3.hdr = skb_inner_network_header(skb); 1193 l4.hdr = skb_inner_transport_header(skb); 1194 1195 /* Software should clear the IPv4's checksum field when 1196 * tso is needed. 1197 */ 1198 if (l3.v4->version == 4) 1199 l3.v4->check = 0; 1200 } 1201 1202 /* normal or tunnel packet */ 1203 l4_offset = l4.hdr - skb->data; 1204 1205 /* remove payload length from inner pseudo checksum when tso */ 1206 l4_paylen = skb->len - l4_offset; 1207 1208 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 1209 hdr_len = sizeof(*l4.udp) + l4_offset; 1210 csum_replace_by_diff(&l4.udp->check, 1211 (__force __wsum)htonl(l4_paylen)); 1212 } else { 1213 hdr_len = (l4.tcp->doff << 2) + l4_offset; 1214 csum_replace_by_diff(&l4.tcp->check, 1215 (__force __wsum)htonl(l4_paylen)); 1216 } 1217 1218 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len; 1219 1220 /* find the txbd field values */ 1221 *paylen_fdop_ol4cs = skb->len - hdr_len; 1222 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 1223 1224 /* offload outer UDP header checksum */ 1225 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1226 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 1227 1228 /* get MSS for TSO */ 1229 *mss = skb_shinfo(skb)->gso_size; 1230 1231 trace_hns3_tso(skb); 1232 1233 return 0; 1234 } 1235 1236 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 1237 u8 *il4_proto) 1238 { 1239 union l3_hdr_info l3; 1240 unsigned char *l4_hdr; 1241 unsigned char *exthdr; 1242 u8 l4_proto_tmp; 1243 __be16 frag_off; 1244 1245 /* find outer header point */ 1246 l3.hdr = skb_network_header(skb); 1247 l4_hdr = skb_transport_header(skb); 1248 1249 if (skb->protocol == htons(ETH_P_IPV6)) { 1250 exthdr = l3.hdr + sizeof(*l3.v6); 1251 l4_proto_tmp = l3.v6->nexthdr; 1252 if (l4_hdr != exthdr) 1253 ipv6_skip_exthdr(skb, exthdr - skb->data, 1254 &l4_proto_tmp, &frag_off); 1255 } else if (skb->protocol == htons(ETH_P_IP)) { 1256 l4_proto_tmp = l3.v4->protocol; 1257 } else { 1258 return -EINVAL; 1259 } 1260 1261 *ol4_proto = l4_proto_tmp; 1262 1263 /* tunnel packet */ 1264 if (!skb->encapsulation) { 1265 *il4_proto = 0; 1266 return 0; 1267 } 1268 1269 /* find inner header point */ 1270 l3.hdr = skb_inner_network_header(skb); 1271 l4_hdr = skb_inner_transport_header(skb); 1272 1273 if (l3.v6->version == 6) { 1274 exthdr = l3.hdr + sizeof(*l3.v6); 1275 l4_proto_tmp = l3.v6->nexthdr; 1276 if (l4_hdr != exthdr) 1277 ipv6_skip_exthdr(skb, exthdr - skb->data, 1278 &l4_proto_tmp, &frag_off); 1279 } else if (l3.v4->version == 4) { 1280 l4_proto_tmp = l3.v4->protocol; 1281 } 1282 1283 *il4_proto = l4_proto_tmp; 1284 1285 return 0; 1286 } 1287 1288 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 1289 * and it is udp packet, which has a dest port as the IANA assigned. 1290 * the hardware is expected to do the checksum offload, but the 1291 * hardware will not do the checksum offload when udp dest port is 1292 * 4789, 4790 or 6081. 1293 */ 1294 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 1295 { 1296 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1297 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 1298 union l4_hdr_info l4; 1299 1300 /* device version above V3(include V3), the hardware can 1301 * do this checksum offload. 1302 */ 1303 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 1304 return false; 1305 1306 l4.hdr = skb_transport_header(skb); 1307 1308 if (!(!skb->encapsulation && 1309 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 1310 l4.udp->dest == htons(GENEVE_UDP_PORT) || 1311 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT)))) 1312 return false; 1313 1314 return true; 1315 } 1316 1317 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1318 u32 *ol_type_vlan_len_msec) 1319 { 1320 u32 l2_len, l3_len, l4_len; 1321 unsigned char *il2_hdr; 1322 union l3_hdr_info l3; 1323 union l4_hdr_info l4; 1324 1325 l3.hdr = skb_network_header(skb); 1326 l4.hdr = skb_transport_header(skb); 1327 1328 /* compute OL2 header size, defined in 2 Bytes */ 1329 l2_len = l3.hdr - skb->data; 1330 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 1331 1332 /* compute OL3 header size, defined in 4 Bytes */ 1333 l3_len = l4.hdr - l3.hdr; 1334 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 1335 1336 il2_hdr = skb_inner_mac_header(skb); 1337 /* compute OL4 header size, defined in 4 Bytes */ 1338 l4_len = il2_hdr - l4.hdr; 1339 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 1340 1341 /* define outer network header type */ 1342 if (skb->protocol == htons(ETH_P_IP)) { 1343 if (skb_is_gso(skb)) 1344 hns3_set_field(*ol_type_vlan_len_msec, 1345 HNS3_TXD_OL3T_S, 1346 HNS3_OL3T_IPV4_CSUM); 1347 else 1348 hns3_set_field(*ol_type_vlan_len_msec, 1349 HNS3_TXD_OL3T_S, 1350 HNS3_OL3T_IPV4_NO_CSUM); 1351 } else if (skb->protocol == htons(ETH_P_IPV6)) { 1352 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 1353 HNS3_OL3T_IPV6); 1354 } 1355 1356 if (ol4_proto == IPPROTO_UDP) 1357 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1358 HNS3_TUN_MAC_IN_UDP); 1359 else if (ol4_proto == IPPROTO_GRE) 1360 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1361 HNS3_TUN_NVGRE); 1362 } 1363 1364 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3, 1365 u32 *type_cs_vlan_tso) 1366 { 1367 if (l3.v4->version == 4) { 1368 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1369 HNS3_L3T_IPV4); 1370 1371 /* the stack computes the IP header already, the only time we 1372 * need the hardware to recompute it is in the case of TSO. 1373 */ 1374 if (skb_is_gso(skb)) 1375 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 1376 } else if (l3.v6->version == 6) { 1377 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1378 HNS3_L3T_IPV6); 1379 } 1380 } 1381 1382 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4, 1383 u32 l4_proto, u32 *type_cs_vlan_tso) 1384 { 1385 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 1386 switch (l4_proto) { 1387 case IPPROTO_TCP: 1388 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1389 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1390 HNS3_L4T_TCP); 1391 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1392 l4.tcp->doff); 1393 break; 1394 case IPPROTO_UDP: 1395 if (hns3_tunnel_csum_bug(skb)) { 1396 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN); 1397 1398 return ret ? ret : skb_checksum_help(skb); 1399 } 1400 1401 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1402 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1403 HNS3_L4T_UDP); 1404 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1405 (sizeof(struct udphdr) >> 2)); 1406 break; 1407 case IPPROTO_SCTP: 1408 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1409 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1410 HNS3_L4T_SCTP); 1411 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1412 (sizeof(struct sctphdr) >> 2)); 1413 break; 1414 default: 1415 /* drop the skb tunnel packet if hardware don't support, 1416 * because hardware can't calculate csum when TSO. 1417 */ 1418 if (skb_is_gso(skb)) 1419 return -EDOM; 1420 1421 /* the stack computes the IP header already, 1422 * driver calculate l4 checksum when not TSO. 1423 */ 1424 return skb_checksum_help(skb); 1425 } 1426 1427 return 0; 1428 } 1429 1430 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1431 u8 il4_proto, u32 *type_cs_vlan_tso, 1432 u32 *ol_type_vlan_len_msec) 1433 { 1434 unsigned char *l2_hdr = skb->data; 1435 u32 l4_proto = ol4_proto; 1436 union l4_hdr_info l4; 1437 union l3_hdr_info l3; 1438 u32 l2_len, l3_len; 1439 1440 l4.hdr = skb_transport_header(skb); 1441 l3.hdr = skb_network_header(skb); 1442 1443 /* handle encapsulation skb */ 1444 if (skb->encapsulation) { 1445 /* If this is a not UDP/GRE encapsulation skb */ 1446 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 1447 /* drop the skb tunnel packet if hardware don't support, 1448 * because hardware can't calculate csum when TSO. 1449 */ 1450 if (skb_is_gso(skb)) 1451 return -EDOM; 1452 1453 /* the stack computes the IP header already, 1454 * driver calculate l4 checksum when not TSO. 1455 */ 1456 return skb_checksum_help(skb); 1457 } 1458 1459 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 1460 1461 /* switch to inner header */ 1462 l2_hdr = skb_inner_mac_header(skb); 1463 l3.hdr = skb_inner_network_header(skb); 1464 l4.hdr = skb_inner_transport_header(skb); 1465 l4_proto = il4_proto; 1466 } 1467 1468 hns3_set_l3_type(skb, l3, type_cs_vlan_tso); 1469 1470 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 1471 l2_len = l3.hdr - l2_hdr; 1472 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 1473 1474 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 1475 l3_len = l4.hdr - l3.hdr; 1476 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 1477 1478 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso); 1479 } 1480 1481 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1482 struct sk_buff *skb) 1483 { 1484 struct hnae3_handle *handle = tx_ring->tqp->handle; 1485 struct hnae3_ae_dev *ae_dev; 1486 struct vlan_ethhdr *vhdr; 1487 int rc; 1488 1489 if (!(skb->protocol == htons(ETH_P_8021Q) || 1490 skb_vlan_tag_present(skb))) 1491 return 0; 1492 1493 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert 1494 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it 1495 * will cause RAS error. 1496 */ 1497 ae_dev = pci_get_drvdata(handle->pdev); 1498 if (unlikely(skb_vlan_tagged_multi(skb) && 1499 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 1500 handle->port_base_vlan_state == 1501 HNAE3_PORT_BASE_VLAN_ENABLE)) 1502 return -EINVAL; 1503 1504 if (skb->protocol == htons(ETH_P_8021Q) && 1505 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1506 /* When HW VLAN acceleration is turned off, and the stack 1507 * sets the protocol to 802.1q, the driver just need to 1508 * set the protocol to the encapsulated ethertype. 1509 */ 1510 skb->protocol = vlan_get_protocol(skb); 1511 return 0; 1512 } 1513 1514 if (skb_vlan_tag_present(skb)) { 1515 /* Based on hw strategy, use out_vtag in two layer tag case, 1516 * and use inner_vtag in one tag case. 1517 */ 1518 if (skb->protocol == htons(ETH_P_8021Q) && 1519 handle->port_base_vlan_state == 1520 HNAE3_PORT_BASE_VLAN_DISABLE) 1521 rc = HNS3_OUTER_VLAN_TAG; 1522 else 1523 rc = HNS3_INNER_VLAN_TAG; 1524 1525 skb->protocol = vlan_get_protocol(skb); 1526 return rc; 1527 } 1528 1529 rc = skb_cow_head(skb, 0); 1530 if (unlikely(rc < 0)) 1531 return rc; 1532 1533 vhdr = (struct vlan_ethhdr *)skb->data; 1534 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1535 & VLAN_PRIO_MASK); 1536 1537 skb->protocol = vlan_get_protocol(skb); 1538 return 0; 1539 } 1540 1541 /* check if the hardware is capable of checksum offloading */ 1542 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1543 { 1544 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1545 1546 /* Kindly note, due to backward compatibility of the TX descriptor, 1547 * HW checksum of the non-IP packets and GSO packets is handled at 1548 * different place in the following code 1549 */ 1550 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) || 1551 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1552 return false; 1553 1554 return true; 1555 } 1556 1557 struct hns3_desc_param { 1558 u32 paylen_ol4cs; 1559 u32 ol_type_vlan_len_msec; 1560 u32 type_cs_vlan_tso; 1561 u16 mss_hw_csum; 1562 u16 inner_vtag; 1563 u16 out_vtag; 1564 }; 1565 1566 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa) 1567 { 1568 pa->paylen_ol4cs = skb->len; 1569 pa->ol_type_vlan_len_msec = 0; 1570 pa->type_cs_vlan_tso = 0; 1571 pa->mss_hw_csum = 0; 1572 pa->inner_vtag = 0; 1573 pa->out_vtag = 0; 1574 } 1575 1576 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring, 1577 struct sk_buff *skb, 1578 struct hns3_desc_param *param) 1579 { 1580 int ret; 1581 1582 ret = hns3_handle_vtags(ring, skb); 1583 if (unlikely(ret < 0)) { 1584 hns3_ring_stats_update(ring, tx_vlan_err); 1585 return ret; 1586 } else if (ret == HNS3_INNER_VLAN_TAG) { 1587 param->inner_vtag = skb_vlan_tag_get(skb); 1588 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1589 VLAN_PRIO_MASK; 1590 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1591 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1592 param->out_vtag = skb_vlan_tag_get(skb); 1593 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1594 VLAN_PRIO_MASK; 1595 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1596 1); 1597 } 1598 return 0; 1599 } 1600 1601 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring, 1602 struct sk_buff *skb, 1603 struct hns3_desc_cb *desc_cb, 1604 struct hns3_desc_param *param) 1605 { 1606 u8 ol4_proto, il4_proto; 1607 int ret; 1608 1609 if (hns3_check_hw_tx_csum(skb)) { 1610 /* set checksum start and offset, defined in 2 Bytes */ 1611 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1612 skb_checksum_start_offset(skb) >> 1); 1613 hns3_set_field(param->ol_type_vlan_len_msec, 1614 HNS3_TXD_CSUM_OFFSET_S, 1615 skb->csum_offset >> 1); 1616 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1617 return 0; 1618 } 1619 1620 skb_reset_mac_len(skb); 1621 1622 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1623 if (unlikely(ret < 0)) { 1624 hns3_ring_stats_update(ring, tx_l4_proto_err); 1625 return ret; 1626 } 1627 1628 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1629 ¶m->type_cs_vlan_tso, 1630 ¶m->ol_type_vlan_len_msec); 1631 if (unlikely(ret < 0)) { 1632 hns3_ring_stats_update(ring, tx_l2l3l4_err); 1633 return ret; 1634 } 1635 1636 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum, 1637 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes); 1638 if (unlikely(ret < 0)) { 1639 hns3_ring_stats_update(ring, tx_tso_err); 1640 return ret; 1641 } 1642 return 0; 1643 } 1644 1645 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1646 struct sk_buff *skb, struct hns3_desc *desc, 1647 struct hns3_desc_cb *desc_cb) 1648 { 1649 struct hns3_desc_param param; 1650 int ret; 1651 1652 hns3_init_desc_data(skb, ¶m); 1653 ret = hns3_handle_vlan_info(ring, skb, ¶m); 1654 if (unlikely(ret < 0)) 1655 return ret; 1656 1657 desc_cb->send_bytes = skb->len; 1658 1659 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1660 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m); 1661 if (ret) 1662 return ret; 1663 } 1664 1665 /* Set txbd */ 1666 desc->tx.ol_type_vlan_len_msec = 1667 cpu_to_le32(param.ol_type_vlan_len_msec); 1668 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso); 1669 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs); 1670 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum); 1671 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag); 1672 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag); 1673 1674 return 0; 1675 } 1676 1677 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma, 1678 unsigned int size) 1679 { 1680 #define HNS3_LIKELY_BD_NUM 1 1681 1682 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1683 unsigned int frag_buf_num; 1684 int k, sizeoflast; 1685 1686 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1687 desc->addr = cpu_to_le64(dma); 1688 desc->tx.send_size = cpu_to_le16(size); 1689 desc->tx.bdtp_fe_sc_vld_ra_ri = 1690 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1691 1692 trace_hns3_tx_desc(ring, ring->next_to_use); 1693 ring_ptr_move_fw(ring, next_to_use); 1694 return HNS3_LIKELY_BD_NUM; 1695 } 1696 1697 frag_buf_num = hns3_tx_bd_count(size); 1698 sizeoflast = size % HNS3_MAX_BD_SIZE; 1699 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1700 1701 /* When frag size is bigger than hardware limit, split this frag */ 1702 for (k = 0; k < frag_buf_num; k++) { 1703 /* now, fill the descriptor */ 1704 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1705 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1706 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1707 desc->tx.bdtp_fe_sc_vld_ra_ri = 1708 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1709 1710 trace_hns3_tx_desc(ring, ring->next_to_use); 1711 /* move ring pointer to next */ 1712 ring_ptr_move_fw(ring, next_to_use); 1713 1714 desc = &ring->desc[ring->next_to_use]; 1715 } 1716 1717 return frag_buf_num; 1718 } 1719 1720 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv, 1721 unsigned int type) 1722 { 1723 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1724 struct device *dev = ring_to_dev(ring); 1725 unsigned int size; 1726 dma_addr_t dma; 1727 1728 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) { 1729 struct sk_buff *skb = (struct sk_buff *)priv; 1730 1731 size = skb_headlen(skb); 1732 if (!size) 1733 return 0; 1734 1735 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1736 } else if (type & DESC_TYPE_BOUNCE_HEAD) { 1737 /* Head data has been filled in hns3_handle_tx_bounce(), 1738 * just return 0 here. 1739 */ 1740 return 0; 1741 } else { 1742 skb_frag_t *frag = (skb_frag_t *)priv; 1743 1744 size = skb_frag_size(frag); 1745 if (!size) 1746 return 0; 1747 1748 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1749 } 1750 1751 if (unlikely(dma_mapping_error(dev, dma))) { 1752 hns3_ring_stats_update(ring, sw_err_cnt); 1753 return -ENOMEM; 1754 } 1755 1756 desc_cb->priv = priv; 1757 desc_cb->length = size; 1758 desc_cb->dma = dma; 1759 desc_cb->type = type; 1760 1761 return hns3_fill_desc(ring, dma, size); 1762 } 1763 1764 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1765 unsigned int bd_num) 1766 { 1767 unsigned int size; 1768 int i; 1769 1770 size = skb_headlen(skb); 1771 while (size > HNS3_MAX_BD_SIZE) { 1772 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1773 size -= HNS3_MAX_BD_SIZE; 1774 1775 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1776 return bd_num; 1777 } 1778 1779 if (size) { 1780 bd_size[bd_num++] = size; 1781 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1782 return bd_num; 1783 } 1784 1785 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1786 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1787 size = skb_frag_size(frag); 1788 if (!size) 1789 continue; 1790 1791 while (size > HNS3_MAX_BD_SIZE) { 1792 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1793 size -= HNS3_MAX_BD_SIZE; 1794 1795 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1796 return bd_num; 1797 } 1798 1799 bd_size[bd_num++] = size; 1800 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1801 return bd_num; 1802 } 1803 1804 return bd_num; 1805 } 1806 1807 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1808 u8 max_non_tso_bd_num, unsigned int bd_num, 1809 unsigned int recursion_level) 1810 { 1811 #define HNS3_MAX_RECURSION_LEVEL 24 1812 1813 struct sk_buff *frag_skb; 1814 1815 /* If the total len is within the max bd limit */ 1816 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level && 1817 !skb_has_frag_list(skb) && 1818 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1819 return skb_shinfo(skb)->nr_frags + 1U; 1820 1821 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL)) 1822 return UINT_MAX; 1823 1824 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1825 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1826 return bd_num; 1827 1828 skb_walk_frags(skb, frag_skb) { 1829 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num, 1830 bd_num, recursion_level + 1); 1831 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1832 return bd_num; 1833 } 1834 1835 return bd_num; 1836 } 1837 1838 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1839 { 1840 if (!skb->encapsulation) 1841 return skb_tcp_all_headers(skb); 1842 1843 return skb_inner_tcp_all_headers(skb); 1844 } 1845 1846 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1847 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1848 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1849 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1850 * than MSS except the last max_non_tso_bd_num - 1 frags. 1851 */ 1852 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1853 unsigned int bd_num, u8 max_non_tso_bd_num) 1854 { 1855 unsigned int tot_len = 0; 1856 int i; 1857 1858 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1859 tot_len += bd_size[i]; 1860 1861 /* ensure the first max_non_tso_bd_num frags is greater than 1862 * mss + header 1863 */ 1864 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1865 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1866 return true; 1867 1868 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1869 * than mss except the last one. 1870 */ 1871 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1872 tot_len -= bd_size[i]; 1873 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1874 1875 if (tot_len < skb_shinfo(skb)->gso_size) 1876 return true; 1877 } 1878 1879 return false; 1880 } 1881 1882 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1883 { 1884 int i; 1885 1886 for (i = 0; i < MAX_SKB_FRAGS; i++) 1887 size[i] = skb_frag_size(&shinfo->frags[i]); 1888 } 1889 1890 static int hns3_skb_linearize(struct hns3_enet_ring *ring, 1891 struct sk_buff *skb, 1892 unsigned int bd_num) 1893 { 1894 /* 'bd_num == UINT_MAX' means the skb' fraglist has a 1895 * recursion level of over HNS3_MAX_RECURSION_LEVEL. 1896 */ 1897 if (bd_num == UINT_MAX) { 1898 hns3_ring_stats_update(ring, over_max_recursion); 1899 return -ENOMEM; 1900 } 1901 1902 /* The skb->len has exceeded the hw limitation, linearization 1903 * will not help. 1904 */ 1905 if (skb->len > HNS3_MAX_TSO_SIZE || 1906 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) { 1907 hns3_ring_stats_update(ring, hw_limitation); 1908 return -ENOMEM; 1909 } 1910 1911 if (__skb_linearize(skb)) { 1912 hns3_ring_stats_update(ring, sw_err_cnt); 1913 return -ENOMEM; 1914 } 1915 1916 return 0; 1917 } 1918 1919 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1920 struct net_device *netdev, 1921 struct sk_buff *skb) 1922 { 1923 struct hns3_nic_priv *priv = netdev_priv(netdev); 1924 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1925 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1926 unsigned int bd_num; 1927 1928 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0); 1929 if (unlikely(bd_num > max_non_tso_bd_num)) { 1930 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1931 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1932 max_non_tso_bd_num)) { 1933 trace_hns3_over_max_bd(skb); 1934 goto out; 1935 } 1936 1937 if (hns3_skb_linearize(ring, skb, bd_num)) 1938 return -ENOMEM; 1939 1940 bd_num = hns3_tx_bd_count(skb->len); 1941 1942 hns3_ring_stats_update(ring, tx_copy); 1943 } 1944 1945 out: 1946 if (likely(ring_space(ring) >= bd_num)) 1947 return bd_num; 1948 1949 netif_stop_subqueue(netdev, ring->queue_index); 1950 smp_mb(); /* Memory barrier before checking ring_space */ 1951 1952 /* Start queue in case hns3_clean_tx_ring has just made room 1953 * available and has not seen the queue stopped state performed 1954 * by netif_stop_subqueue above. 1955 */ 1956 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1957 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1958 netif_start_subqueue(netdev, ring->queue_index); 1959 return bd_num; 1960 } 1961 1962 hns3_ring_stats_update(ring, tx_busy); 1963 1964 return -EBUSY; 1965 } 1966 1967 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1968 { 1969 struct device *dev = ring_to_dev(ring); 1970 unsigned int i; 1971 1972 for (i = 0; i < ring->desc_num; i++) { 1973 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1974 struct hns3_desc_cb *desc_cb; 1975 1976 memset(desc, 0, sizeof(*desc)); 1977 1978 /* check if this is where we started */ 1979 if (ring->next_to_use == next_to_use_orig) 1980 break; 1981 1982 /* rollback one */ 1983 ring_ptr_move_bw(ring, next_to_use); 1984 1985 desc_cb = &ring->desc_cb[ring->next_to_use]; 1986 1987 if (!desc_cb->dma) 1988 continue; 1989 1990 /* unmap the descriptor dma address */ 1991 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 1992 dma_unmap_single(dev, desc_cb->dma, desc_cb->length, 1993 DMA_TO_DEVICE); 1994 else if (desc_cb->type & 1995 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) 1996 hns3_tx_spare_rollback(ring, desc_cb->length); 1997 else if (desc_cb->length) 1998 dma_unmap_page(dev, desc_cb->dma, desc_cb->length, 1999 DMA_TO_DEVICE); 2000 2001 desc_cb->length = 0; 2002 desc_cb->dma = 0; 2003 desc_cb->type = DESC_TYPE_UNKNOWN; 2004 } 2005 } 2006 2007 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 2008 struct sk_buff *skb, unsigned int type) 2009 { 2010 struct sk_buff *frag_skb; 2011 int i, ret, bd_num = 0; 2012 2013 ret = hns3_map_and_fill_desc(ring, skb, type); 2014 if (unlikely(ret < 0)) 2015 return ret; 2016 2017 bd_num += ret; 2018 2019 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2020 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2021 2022 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE); 2023 if (unlikely(ret < 0)) 2024 return ret; 2025 2026 bd_num += ret; 2027 } 2028 2029 skb_walk_frags(skb, frag_skb) { 2030 ret = hns3_fill_skb_to_desc(ring, frag_skb, 2031 DESC_TYPE_FRAGLIST_SKB); 2032 if (unlikely(ret < 0)) 2033 return ret; 2034 2035 bd_num += ret; 2036 } 2037 2038 return bd_num; 2039 } 2040 2041 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num) 2042 { 2043 #define HNS3_BYTES_PER_64BIT 8 2044 2045 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {}; 2046 int offset = 0; 2047 2048 /* make sure everything is visible to device before 2049 * excuting tx push or updating doorbell 2050 */ 2051 dma_wmb(); 2052 2053 do { 2054 int idx = (ring->next_to_use - num + ring->desc_num) % 2055 ring->desc_num; 2056 2057 u64_stats_update_begin(&ring->syncp); 2058 ring->stats.tx_push++; 2059 u64_stats_update_end(&ring->syncp); 2060 memcpy(&desc[offset], &ring->desc[idx], 2061 sizeof(struct hns3_desc)); 2062 offset++; 2063 } while (--num); 2064 2065 __iowrite64_copy(ring->tqp->mem_base, desc, 2066 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) / 2067 HNS3_BYTES_PER_64BIT); 2068 2069 io_stop_wc(); 2070 } 2071 2072 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring) 2073 { 2074 #define HNS3_MEM_DOORBELL_OFFSET 64 2075 2076 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf); 2077 2078 /* make sure everything is visible to device before 2079 * excuting tx push or updating doorbell 2080 */ 2081 dma_wmb(); 2082 2083 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET, 2084 &bd_num, 1); 2085 u64_stats_update_begin(&ring->syncp); 2086 ring->stats.tx_mem_doorbell += ring->pending_buf; 2087 u64_stats_update_end(&ring->syncp); 2088 2089 io_stop_wc(); 2090 } 2091 2092 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 2093 bool doorbell) 2094 { 2095 struct net_device *netdev = ring_to_netdev(ring); 2096 struct hns3_nic_priv *priv = netdev_priv(netdev); 2097 2098 /* when tx push is enabled, the packet whose number of BD below 2099 * HNS3_MAX_PUSH_BD_NUM can be pushed directly. 2100 */ 2101 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num && 2102 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) { 2103 hns3_tx_push_bd(ring, num); 2104 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 2105 return; 2106 } 2107 2108 ring->pending_buf += num; 2109 2110 if (!doorbell) { 2111 hns3_ring_stats_update(ring, tx_more); 2112 return; 2113 } 2114 2115 if (ring->tqp->mem_base) 2116 hns3_tx_mem_doorbell(ring); 2117 else 2118 writel(ring->pending_buf, 2119 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 2120 2121 ring->pending_buf = 0; 2122 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 2123 } 2124 2125 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb, 2126 struct hns3_desc *desc) 2127 { 2128 struct hnae3_handle *h = hns3_get_handle(netdev); 2129 2130 if (!(h->ae_algo->ops->set_tx_hwts_info && 2131 h->ae_algo->ops->set_tx_hwts_info(h, skb))) 2132 return; 2133 2134 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B)); 2135 } 2136 2137 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring, 2138 struct sk_buff *skb) 2139 { 2140 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2141 unsigned int type = DESC_TYPE_BOUNCE_HEAD; 2142 unsigned int size = skb_headlen(skb); 2143 dma_addr_t dma; 2144 int bd_num = 0; 2145 u32 cb_len; 2146 void *buf; 2147 int ret; 2148 2149 if (skb->len <= ring->tx_copybreak) { 2150 size = skb->len; 2151 type = DESC_TYPE_BOUNCE_ALL; 2152 } 2153 2154 /* hns3_can_use_tx_bounce() is called to ensure the below 2155 * function can always return the tx buffer. 2156 */ 2157 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len); 2158 2159 ret = skb_copy_bits(skb, 0, buf, size); 2160 if (unlikely(ret < 0)) { 2161 hns3_tx_spare_rollback(ring, cb_len); 2162 hns3_ring_stats_update(ring, copy_bits_err); 2163 return ret; 2164 } 2165 2166 desc_cb->priv = skb; 2167 desc_cb->length = cb_len; 2168 desc_cb->dma = dma; 2169 desc_cb->type = type; 2170 2171 bd_num += hns3_fill_desc(ring, dma, size); 2172 2173 if (type == DESC_TYPE_BOUNCE_HEAD) { 2174 ret = hns3_fill_skb_to_desc(ring, skb, 2175 DESC_TYPE_BOUNCE_HEAD); 2176 if (unlikely(ret < 0)) 2177 return ret; 2178 2179 bd_num += ret; 2180 } 2181 2182 dma_sync_single_for_device(ring_to_dev(ring), dma, size, 2183 DMA_TO_DEVICE); 2184 2185 hns3_ring_stats_update(ring, tx_bounce); 2186 2187 return bd_num; 2188 } 2189 2190 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring, 2191 struct sk_buff *skb) 2192 { 2193 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2194 u32 nfrag = skb_shinfo(skb)->nr_frags + 1; 2195 struct sg_table *sgt; 2196 int i, bd_num = 0; 2197 dma_addr_t dma; 2198 u32 cb_len; 2199 int nents; 2200 2201 if (skb_has_frag_list(skb)) 2202 nfrag = HNS3_MAX_TSO_BD_NUM; 2203 2204 /* hns3_can_use_tx_sgl() is called to ensure the below 2205 * function can always return the tx buffer. 2206 */ 2207 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag), 2208 &dma, &cb_len); 2209 2210 /* scatterlist follows by the sg table */ 2211 sgt->sgl = (struct scatterlist *)(sgt + 1); 2212 sg_init_table(sgt->sgl, nfrag); 2213 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len); 2214 if (unlikely(nents < 0)) { 2215 hns3_tx_spare_rollback(ring, cb_len); 2216 hns3_ring_stats_update(ring, skb2sgl_err); 2217 return -ENOMEM; 2218 } 2219 2220 sgt->orig_nents = nents; 2221 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 2222 DMA_TO_DEVICE); 2223 if (unlikely(!sgt->nents)) { 2224 hns3_tx_spare_rollback(ring, cb_len); 2225 hns3_ring_stats_update(ring, map_sg_err); 2226 return -ENOMEM; 2227 } 2228 2229 desc_cb->priv = skb; 2230 desc_cb->length = cb_len; 2231 desc_cb->dma = dma; 2232 desc_cb->type = DESC_TYPE_SGL_SKB; 2233 2234 for (i = 0; i < sgt->nents; i++) 2235 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i), 2236 sg_dma_len(sgt->sgl + i)); 2237 hns3_ring_stats_update(ring, tx_sgl); 2238 2239 return bd_num; 2240 } 2241 2242 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring, 2243 struct sk_buff *skb) 2244 { 2245 u32 space; 2246 2247 if (!ring->tx_spare) 2248 goto out; 2249 2250 space = hns3_tx_spare_space(ring); 2251 2252 if (hns3_can_use_tx_sgl(ring, skb, space)) 2253 return hns3_handle_tx_sgl(ring, skb); 2254 2255 if (hns3_can_use_tx_bounce(ring, skb, space)) 2256 return hns3_handle_tx_bounce(ring, skb); 2257 2258 out: 2259 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 2260 } 2261 2262 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring, 2263 struct sk_buff *skb, 2264 struct hns3_desc_cb *desc_cb, 2265 int next_to_use_head) 2266 { 2267 int ret; 2268 2269 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use], 2270 desc_cb); 2271 if (unlikely(ret < 0)) 2272 goto fill_err; 2273 2274 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is 2275 * zero, which is unlikely, and 'ret > 0' means how many tx desc 2276 * need to be notified to the hw. 2277 */ 2278 ret = hns3_handle_desc_filling(ring, skb); 2279 if (likely(ret > 0)) 2280 return ret; 2281 2282 fill_err: 2283 hns3_clear_desc(ring, next_to_use_head); 2284 return ret; 2285 } 2286 2287 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 2288 { 2289 struct hns3_nic_priv *priv = netdev_priv(netdev); 2290 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 2291 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2292 struct netdev_queue *dev_queue; 2293 int pre_ntu, ret; 2294 bool doorbell; 2295 2296 /* Hardware can only handle short frames above 32 bytes */ 2297 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 2298 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2299 2300 hns3_ring_stats_update(ring, sw_err_cnt); 2301 2302 return NETDEV_TX_OK; 2303 } 2304 2305 /* Prefetch the data used later */ 2306 prefetch(skb->data); 2307 2308 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 2309 if (unlikely(ret <= 0)) { 2310 if (ret == -EBUSY) { 2311 hns3_tx_doorbell(ring, 0, true); 2312 return NETDEV_TX_BUSY; 2313 } 2314 2315 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 2316 goto out_err_tx_ok; 2317 } 2318 2319 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use); 2320 if (unlikely(ret <= 0)) 2321 goto out_err_tx_ok; 2322 2323 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 2324 (ring->desc_num - 1); 2325 2326 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 2327 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]); 2328 2329 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 2330 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 2331 trace_hns3_tx_desc(ring, pre_ntu); 2332 2333 skb_tx_timestamp(skb); 2334 2335 /* Complete translate all packets */ 2336 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 2337 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes, 2338 netdev_xmit_more()); 2339 hns3_tx_doorbell(ring, ret, doorbell); 2340 2341 return NETDEV_TX_OK; 2342 2343 out_err_tx_ok: 2344 dev_kfree_skb_any(skb); 2345 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2346 return NETDEV_TX_OK; 2347 } 2348 2349 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 2350 { 2351 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN]; 2352 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN]; 2353 struct hnae3_handle *h = hns3_get_handle(netdev); 2354 struct sockaddr *mac_addr = p; 2355 int ret; 2356 2357 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 2358 return -EADDRNOTAVAIL; 2359 2360 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 2361 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data); 2362 netdev_info(netdev, "already using mac address %s\n", 2363 format_mac_addr_sa); 2364 return 0; 2365 } 2366 2367 /* For VF device, if there is a perm_addr, then the user will not 2368 * be allowed to change the address. 2369 */ 2370 if (!hns3_is_phys_func(h->pdev) && 2371 !is_zero_ether_addr(netdev->perm_addr)) { 2372 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr); 2373 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data); 2374 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n", 2375 format_mac_addr_perm, format_mac_addr_sa); 2376 return -EPERM; 2377 } 2378 2379 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 2380 if (ret) { 2381 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 2382 return ret; 2383 } 2384 2385 eth_hw_addr_set(netdev, mac_addr->sa_data); 2386 2387 return 0; 2388 } 2389 2390 static int hns3_nic_do_ioctl(struct net_device *netdev, 2391 struct ifreq *ifr, int cmd) 2392 { 2393 struct hnae3_handle *h = hns3_get_handle(netdev); 2394 2395 if (!netif_running(netdev)) 2396 return -EINVAL; 2397 2398 if (!h->ae_algo->ops->do_ioctl) 2399 return -EOPNOTSUPP; 2400 2401 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 2402 } 2403 2404 static int hns3_nic_set_features(struct net_device *netdev, 2405 netdev_features_t features) 2406 { 2407 netdev_features_t changed = netdev->features ^ features; 2408 struct hns3_nic_priv *priv = netdev_priv(netdev); 2409 struct hnae3_handle *h = priv->ae_handle; 2410 bool enable; 2411 int ret; 2412 2413 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 2414 enable = !!(features & NETIF_F_GRO_HW); 2415 ret = h->ae_algo->ops->set_gro_en(h, enable); 2416 if (ret) 2417 return ret; 2418 } 2419 2420 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 2421 h->ae_algo->ops->enable_hw_strip_rxvtag) { 2422 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 2423 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 2424 if (ret) 2425 return ret; 2426 } 2427 2428 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 2429 enable = !!(features & NETIF_F_NTUPLE); 2430 h->ae_algo->ops->enable_fd(h, enable); 2431 } 2432 2433 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 2434 h->ae_algo->ops->cls_flower_active(h)) { 2435 netdev_err(netdev, 2436 "there are offloaded TC filters active, cannot disable HW TC offload"); 2437 return -EINVAL; 2438 } 2439 2440 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 2441 h->ae_algo->ops->enable_vlan_filter) { 2442 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 2443 ret = h->ae_algo->ops->enable_vlan_filter(h, enable); 2444 if (ret) 2445 return ret; 2446 } 2447 2448 netdev->features = features; 2449 return 0; 2450 } 2451 2452 static netdev_features_t hns3_features_check(struct sk_buff *skb, 2453 struct net_device *dev, 2454 netdev_features_t features) 2455 { 2456 #define HNS3_MAX_HDR_LEN 480U 2457 #define HNS3_MAX_L4_HDR_LEN 60U 2458 2459 size_t len; 2460 2461 if (skb->ip_summed != CHECKSUM_PARTIAL) 2462 return features; 2463 2464 if (skb->encapsulation) 2465 len = skb_inner_transport_header(skb) - skb->data; 2466 else 2467 len = skb_transport_header(skb) - skb->data; 2468 2469 /* Assume L4 is 60 byte as TCP is the only protocol with a 2470 * a flexible value, and it's max len is 60 bytes. 2471 */ 2472 len += HNS3_MAX_L4_HDR_LEN; 2473 2474 /* Hardware only supports checksum on the skb with a max header 2475 * len of 480 bytes. 2476 */ 2477 if (len > HNS3_MAX_HDR_LEN) 2478 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2479 2480 return features; 2481 } 2482 2483 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats, 2484 struct hns3_enet_ring *ring, bool is_tx) 2485 { 2486 unsigned int start; 2487 2488 do { 2489 start = u64_stats_fetch_begin(&ring->syncp); 2490 if (is_tx) { 2491 stats->tx_bytes += ring->stats.tx_bytes; 2492 stats->tx_packets += ring->stats.tx_pkts; 2493 stats->tx_dropped += ring->stats.sw_err_cnt; 2494 stats->tx_dropped += ring->stats.tx_vlan_err; 2495 stats->tx_dropped += ring->stats.tx_l4_proto_err; 2496 stats->tx_dropped += ring->stats.tx_l2l3l4_err; 2497 stats->tx_dropped += ring->stats.tx_tso_err; 2498 stats->tx_dropped += ring->stats.over_max_recursion; 2499 stats->tx_dropped += ring->stats.hw_limitation; 2500 stats->tx_dropped += ring->stats.copy_bits_err; 2501 stats->tx_dropped += ring->stats.skb2sgl_err; 2502 stats->tx_dropped += ring->stats.map_sg_err; 2503 stats->tx_errors += ring->stats.sw_err_cnt; 2504 stats->tx_errors += ring->stats.tx_vlan_err; 2505 stats->tx_errors += ring->stats.tx_l4_proto_err; 2506 stats->tx_errors += ring->stats.tx_l2l3l4_err; 2507 stats->tx_errors += ring->stats.tx_tso_err; 2508 stats->tx_errors += ring->stats.over_max_recursion; 2509 stats->tx_errors += ring->stats.hw_limitation; 2510 stats->tx_errors += ring->stats.copy_bits_err; 2511 stats->tx_errors += ring->stats.skb2sgl_err; 2512 stats->tx_errors += ring->stats.map_sg_err; 2513 } else { 2514 stats->rx_bytes += ring->stats.rx_bytes; 2515 stats->rx_packets += ring->stats.rx_pkts; 2516 stats->rx_dropped += ring->stats.l2_err; 2517 stats->rx_errors += ring->stats.l2_err; 2518 stats->rx_errors += ring->stats.l3l4_csum_err; 2519 stats->rx_crc_errors += ring->stats.l2_err; 2520 stats->multicast += ring->stats.rx_multicast; 2521 stats->rx_length_errors += ring->stats.err_pkt_len; 2522 } 2523 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2524 } 2525 2526 static void hns3_nic_get_stats64(struct net_device *netdev, 2527 struct rtnl_link_stats64 *stats) 2528 { 2529 struct hns3_nic_priv *priv = netdev_priv(netdev); 2530 int queue_num = priv->ae_handle->kinfo.num_tqps; 2531 struct hnae3_handle *handle = priv->ae_handle; 2532 struct rtnl_link_stats64 ring_total_stats; 2533 struct hns3_enet_ring *ring; 2534 unsigned int idx; 2535 2536 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 2537 return; 2538 2539 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 2540 2541 memset(&ring_total_stats, 0, sizeof(ring_total_stats)); 2542 for (idx = 0; idx < queue_num; idx++) { 2543 /* fetch the tx stats */ 2544 ring = &priv->ring[idx]; 2545 hns3_fetch_stats(&ring_total_stats, ring, true); 2546 2547 /* fetch the rx stats */ 2548 ring = &priv->ring[idx + queue_num]; 2549 hns3_fetch_stats(&ring_total_stats, ring, false); 2550 } 2551 2552 stats->tx_bytes = ring_total_stats.tx_bytes; 2553 stats->tx_packets = ring_total_stats.tx_packets; 2554 stats->rx_bytes = ring_total_stats.rx_bytes; 2555 stats->rx_packets = ring_total_stats.rx_packets; 2556 2557 stats->rx_errors = ring_total_stats.rx_errors; 2558 stats->multicast = ring_total_stats.multicast; 2559 stats->rx_length_errors = ring_total_stats.rx_length_errors; 2560 stats->rx_crc_errors = ring_total_stats.rx_crc_errors; 2561 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 2562 2563 stats->tx_errors = ring_total_stats.tx_errors; 2564 stats->rx_dropped = ring_total_stats.rx_dropped; 2565 stats->tx_dropped = ring_total_stats.tx_dropped; 2566 stats->collisions = netdev->stats.collisions; 2567 stats->rx_over_errors = netdev->stats.rx_over_errors; 2568 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 2569 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 2570 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 2571 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 2572 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 2573 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 2574 stats->tx_window_errors = netdev->stats.tx_window_errors; 2575 stats->rx_compressed = netdev->stats.rx_compressed; 2576 stats->tx_compressed = netdev->stats.tx_compressed; 2577 } 2578 2579 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 2580 { 2581 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 2582 struct hnae3_knic_private_info *kinfo; 2583 u8 tc = mqprio_qopt->qopt.num_tc; 2584 u16 mode = mqprio_qopt->mode; 2585 u8 hw = mqprio_qopt->qopt.hw; 2586 struct hnae3_handle *h; 2587 2588 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 2589 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 2590 return -EOPNOTSUPP; 2591 2592 if (tc > HNAE3_MAX_TC) 2593 return -EINVAL; 2594 2595 if (!netdev) 2596 return -EINVAL; 2597 2598 h = hns3_get_handle(netdev); 2599 kinfo = &h->kinfo; 2600 2601 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 2602 2603 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 2604 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP; 2605 } 2606 2607 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv, 2608 struct flow_cls_offload *flow) 2609 { 2610 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid); 2611 struct hnae3_handle *h = hns3_get_handle(priv->netdev); 2612 2613 switch (flow->command) { 2614 case FLOW_CLS_REPLACE: 2615 if (h->ae_algo->ops->add_cls_flower) 2616 return h->ae_algo->ops->add_cls_flower(h, flow, tc); 2617 break; 2618 case FLOW_CLS_DESTROY: 2619 if (h->ae_algo->ops->del_cls_flower) 2620 return h->ae_algo->ops->del_cls_flower(h, flow); 2621 break; 2622 default: 2623 break; 2624 } 2625 2626 return -EOPNOTSUPP; 2627 } 2628 2629 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2630 void *cb_priv) 2631 { 2632 struct hns3_nic_priv *priv = cb_priv; 2633 2634 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) 2635 return -EOPNOTSUPP; 2636 2637 switch (type) { 2638 case TC_SETUP_CLSFLOWER: 2639 return hns3_setup_tc_cls_flower(priv, type_data); 2640 default: 2641 return -EOPNOTSUPP; 2642 } 2643 } 2644 2645 static LIST_HEAD(hns3_block_cb_list); 2646 2647 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 2648 void *type_data) 2649 { 2650 struct hns3_nic_priv *priv = netdev_priv(dev); 2651 int ret; 2652 2653 switch (type) { 2654 case TC_SETUP_QDISC_MQPRIO: 2655 ret = hns3_setup_tc(dev, type_data); 2656 break; 2657 case TC_SETUP_BLOCK: 2658 ret = flow_block_cb_setup_simple(type_data, 2659 &hns3_block_cb_list, 2660 hns3_setup_tc_block_cb, 2661 priv, priv, true); 2662 break; 2663 default: 2664 return -EOPNOTSUPP; 2665 } 2666 2667 return ret; 2668 } 2669 2670 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 2671 __be16 proto, u16 vid) 2672 { 2673 struct hnae3_handle *h = hns3_get_handle(netdev); 2674 int ret = -EIO; 2675 2676 if (h->ae_algo->ops->set_vlan_filter) 2677 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 2678 2679 return ret; 2680 } 2681 2682 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 2683 __be16 proto, u16 vid) 2684 { 2685 struct hnae3_handle *h = hns3_get_handle(netdev); 2686 int ret = -EIO; 2687 2688 if (h->ae_algo->ops->set_vlan_filter) 2689 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 2690 2691 return ret; 2692 } 2693 2694 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2695 u8 qos, __be16 vlan_proto) 2696 { 2697 struct hnae3_handle *h = hns3_get_handle(netdev); 2698 int ret = -EIO; 2699 2700 netif_dbg(h, drv, netdev, 2701 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 2702 vf, vlan, qos, ntohs(vlan_proto)); 2703 2704 if (h->ae_algo->ops->set_vf_vlan_filter) 2705 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 2706 qos, vlan_proto); 2707 2708 return ret; 2709 } 2710 2711 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 2712 { 2713 struct hnae3_handle *handle = hns3_get_handle(netdev); 2714 2715 if (hns3_nic_resetting(netdev)) 2716 return -EBUSY; 2717 2718 if (!handle->ae_algo->ops->set_vf_spoofchk) 2719 return -EOPNOTSUPP; 2720 2721 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 2722 } 2723 2724 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 2725 { 2726 struct hnae3_handle *handle = hns3_get_handle(netdev); 2727 2728 if (!handle->ae_algo->ops->set_vf_trust) 2729 return -EOPNOTSUPP; 2730 2731 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 2732 } 2733 2734 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 2735 { 2736 struct hnae3_handle *h = hns3_get_handle(netdev); 2737 int ret; 2738 2739 if (hns3_nic_resetting(netdev)) 2740 return -EBUSY; 2741 2742 if (!h->ae_algo->ops->set_mtu) 2743 return -EOPNOTSUPP; 2744 2745 netif_dbg(h, drv, netdev, 2746 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 2747 2748 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 2749 if (ret) 2750 netdev_err(netdev, "failed to change MTU in hardware %d\n", 2751 ret); 2752 else 2753 netdev->mtu = new_mtu; 2754 2755 return ret; 2756 } 2757 2758 static int hns3_get_timeout_queue(struct net_device *ndev) 2759 { 2760 int i; 2761 2762 /* Find the stopped queue the same way the stack does */ 2763 for (i = 0; i < ndev->num_tx_queues; i++) { 2764 struct netdev_queue *q; 2765 unsigned long trans_start; 2766 2767 q = netdev_get_tx_queue(ndev, i); 2768 trans_start = READ_ONCE(q->trans_start); 2769 if (netif_xmit_stopped(q) && 2770 time_after(jiffies, 2771 (trans_start + ndev->watchdog_timeo))) { 2772 #ifdef CONFIG_BQL 2773 struct dql *dql = &q->dql; 2774 2775 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n", 2776 dql->last_obj_cnt, dql->num_queued, 2777 dql->adj_limit, dql->num_completed); 2778 #endif 2779 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 2780 q->state, 2781 jiffies_to_msecs(jiffies - trans_start)); 2782 break; 2783 } 2784 } 2785 2786 return i; 2787 } 2788 2789 static void hns3_dump_queue_stats(struct net_device *ndev, 2790 struct hns3_enet_ring *tx_ring, 2791 int timeout_queue) 2792 { 2793 struct napi_struct *napi = &tx_ring->tqp_vector->napi; 2794 struct hns3_nic_priv *priv = netdev_priv(ndev); 2795 2796 netdev_info(ndev, 2797 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 2798 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 2799 tx_ring->next_to_clean, napi->state); 2800 2801 netdev_info(ndev, 2802 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 2803 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 2804 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 2805 2806 netdev_info(ndev, 2807 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 2808 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 2809 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 2810 2811 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n", 2812 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell); 2813 } 2814 2815 static void hns3_dump_queue_reg(struct net_device *ndev, 2816 struct hns3_enet_ring *tx_ring) 2817 { 2818 netdev_info(ndev, 2819 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2820 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG), 2821 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG), 2822 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG), 2823 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG), 2824 readl(tx_ring->tqp_vector->mask_addr)); 2825 netdev_info(ndev, 2826 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2827 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG), 2828 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG), 2829 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG), 2830 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG), 2831 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG), 2832 hns3_tqp_read_reg(tx_ring, 2833 HNS3_RING_TX_RING_EBD_OFFSET_REG)); 2834 } 2835 2836 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 2837 { 2838 struct hns3_nic_priv *priv = netdev_priv(ndev); 2839 struct hnae3_handle *h = hns3_get_handle(ndev); 2840 struct hns3_enet_ring *tx_ring; 2841 int timeout_queue; 2842 2843 timeout_queue = hns3_get_timeout_queue(ndev); 2844 if (timeout_queue >= ndev->num_tx_queues) { 2845 netdev_info(ndev, 2846 "no netdev TX timeout queue found, timeout count: %llu\n", 2847 priv->tx_timeout_count); 2848 return false; 2849 } 2850 2851 priv->tx_timeout_count++; 2852 2853 tx_ring = &priv->ring[timeout_queue]; 2854 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue); 2855 2856 /* When mac received many pause frames continuous, it's unable to send 2857 * packets, which may cause tx timeout 2858 */ 2859 if (h->ae_algo->ops->get_mac_stats) { 2860 struct hns3_mac_stats mac_stats; 2861 2862 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 2863 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 2864 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 2865 } 2866 2867 hns3_dump_queue_reg(ndev, tx_ring); 2868 2869 return true; 2870 } 2871 2872 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2873 { 2874 struct hns3_nic_priv *priv = netdev_priv(ndev); 2875 struct hnae3_handle *h = priv->ae_handle; 2876 2877 if (!hns3_get_tx_timeo_queue_info(ndev)) 2878 return; 2879 2880 /* request the reset, and let the hclge to determine 2881 * which reset level should be done 2882 */ 2883 if (h->ae_algo->ops->reset_event) 2884 h->ae_algo->ops->reset_event(h->pdev, h); 2885 } 2886 2887 #ifdef CONFIG_RFS_ACCEL 2888 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2889 u16 rxq_index, u32 flow_id) 2890 { 2891 struct hnae3_handle *h = hns3_get_handle(dev); 2892 struct flow_keys fkeys; 2893 2894 if (!h->ae_algo->ops->add_arfs_entry) 2895 return -EOPNOTSUPP; 2896 2897 if (skb->encapsulation) 2898 return -EPROTONOSUPPORT; 2899 2900 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2901 return -EPROTONOSUPPORT; 2902 2903 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2904 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2905 (fkeys.basic.ip_proto != IPPROTO_TCP && 2906 fkeys.basic.ip_proto != IPPROTO_UDP)) 2907 return -EPROTONOSUPPORT; 2908 2909 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2910 } 2911 #endif 2912 2913 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2914 struct ifla_vf_info *ivf) 2915 { 2916 struct hnae3_handle *h = hns3_get_handle(ndev); 2917 2918 if (!h->ae_algo->ops->get_vf_config) 2919 return -EOPNOTSUPP; 2920 2921 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2922 } 2923 2924 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2925 int link_state) 2926 { 2927 struct hnae3_handle *h = hns3_get_handle(ndev); 2928 2929 if (!h->ae_algo->ops->set_vf_link_state) 2930 return -EOPNOTSUPP; 2931 2932 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2933 } 2934 2935 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2936 int min_tx_rate, int max_tx_rate) 2937 { 2938 struct hnae3_handle *h = hns3_get_handle(ndev); 2939 2940 if (!h->ae_algo->ops->set_vf_rate) 2941 return -EOPNOTSUPP; 2942 2943 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2944 false); 2945 } 2946 2947 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2948 { 2949 struct hnae3_handle *h = hns3_get_handle(netdev); 2950 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 2951 2952 if (!h->ae_algo->ops->set_vf_mac) 2953 return -EOPNOTSUPP; 2954 2955 if (is_multicast_ether_addr(mac)) { 2956 hnae3_format_mac_addr(format_mac_addr, mac); 2957 netdev_err(netdev, 2958 "Invalid MAC:%s specified. Could not set MAC\n", 2959 format_mac_addr); 2960 return -EINVAL; 2961 } 2962 2963 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2964 } 2965 2966 #define HNS3_INVALID_DSCP 0xff 2967 #define HNS3_DSCP_SHIFT 2 2968 2969 static u8 hns3_get_skb_dscp(struct sk_buff *skb) 2970 { 2971 __be16 protocol = skb->protocol; 2972 u8 dscp = HNS3_INVALID_DSCP; 2973 2974 if (protocol == htons(ETH_P_8021Q)) 2975 protocol = vlan_get_protocol(skb); 2976 2977 if (protocol == htons(ETH_P_IP)) 2978 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT; 2979 else if (protocol == htons(ETH_P_IPV6)) 2980 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT; 2981 2982 return dscp; 2983 } 2984 2985 static u16 hns3_nic_select_queue(struct net_device *netdev, 2986 struct sk_buff *skb, 2987 struct net_device *sb_dev) 2988 { 2989 struct hnae3_handle *h = hns3_get_handle(netdev); 2990 u8 dscp; 2991 2992 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP || 2993 !h->ae_algo->ops->get_dscp_prio) 2994 goto out; 2995 2996 dscp = hns3_get_skb_dscp(skb); 2997 if (unlikely(dscp >= HNAE3_MAX_DSCP)) 2998 goto out; 2999 3000 skb->priority = h->kinfo.dscp_prio[dscp]; 3001 if (skb->priority == HNAE3_PRIO_ID_INVALID) 3002 skb->priority = 0; 3003 3004 out: 3005 return netdev_pick_tx(netdev, skb, sb_dev); 3006 } 3007 3008 static const struct net_device_ops hns3_nic_netdev_ops = { 3009 .ndo_open = hns3_nic_net_open, 3010 .ndo_stop = hns3_nic_net_stop, 3011 .ndo_start_xmit = hns3_nic_net_xmit, 3012 .ndo_tx_timeout = hns3_nic_net_timeout, 3013 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 3014 .ndo_eth_ioctl = hns3_nic_do_ioctl, 3015 .ndo_change_mtu = hns3_nic_change_mtu, 3016 .ndo_set_features = hns3_nic_set_features, 3017 .ndo_features_check = hns3_features_check, 3018 .ndo_get_stats64 = hns3_nic_get_stats64, 3019 .ndo_setup_tc = hns3_nic_setup_tc, 3020 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 3021 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 3022 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 3023 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 3024 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 3025 .ndo_set_vf_trust = hns3_set_vf_trust, 3026 #ifdef CONFIG_RFS_ACCEL 3027 .ndo_rx_flow_steer = hns3_rx_flow_steer, 3028 #endif 3029 .ndo_get_vf_config = hns3_nic_get_vf_config, 3030 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 3031 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 3032 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 3033 .ndo_select_queue = hns3_nic_select_queue, 3034 }; 3035 3036 bool hns3_is_phys_func(struct pci_dev *pdev) 3037 { 3038 u32 dev_id = pdev->device; 3039 3040 switch (dev_id) { 3041 case HNAE3_DEV_ID_GE: 3042 case HNAE3_DEV_ID_25GE: 3043 case HNAE3_DEV_ID_25GE_RDMA: 3044 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 3045 case HNAE3_DEV_ID_50GE_RDMA: 3046 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 3047 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 3048 case HNAE3_DEV_ID_200G_RDMA: 3049 return true; 3050 case HNAE3_DEV_ID_VF: 3051 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 3052 return false; 3053 default: 3054 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 3055 dev_id); 3056 } 3057 3058 return false; 3059 } 3060 3061 static void hns3_disable_sriov(struct pci_dev *pdev) 3062 { 3063 /* If our VFs are assigned we cannot shut down SR-IOV 3064 * without causing issues, so just leave the hardware 3065 * available but disabled 3066 */ 3067 if (pci_vfs_assigned(pdev)) { 3068 dev_warn(&pdev->dev, 3069 "disabling driver while VFs are assigned\n"); 3070 return; 3071 } 3072 3073 pci_disable_sriov(pdev); 3074 } 3075 3076 /* hns3_probe - Device initialization routine 3077 * @pdev: PCI device information struct 3078 * @ent: entry in hns3_pci_tbl 3079 * 3080 * hns3_probe initializes a PF identified by a pci_dev structure. 3081 * The OS initialization, configuring of the PF private structure, 3082 * and a hardware reset occur. 3083 * 3084 * Returns 0 on success, negative on failure 3085 */ 3086 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3087 { 3088 struct hnae3_ae_dev *ae_dev; 3089 int ret; 3090 3091 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 3092 if (!ae_dev) 3093 return -ENOMEM; 3094 3095 ae_dev->pdev = pdev; 3096 ae_dev->flag = ent->driver_data; 3097 pci_set_drvdata(pdev, ae_dev); 3098 3099 ret = hnae3_register_ae_dev(ae_dev); 3100 if (ret) 3101 pci_set_drvdata(pdev, NULL); 3102 3103 return ret; 3104 } 3105 3106 /** 3107 * hns3_clean_vf_config 3108 * @pdev: pointer to a pci_dev structure 3109 * @num_vfs: number of VFs allocated 3110 * 3111 * Clean residual vf config after disable sriov 3112 **/ 3113 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs) 3114 { 3115 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3116 3117 if (ae_dev->ops->clean_vf_config) 3118 ae_dev->ops->clean_vf_config(ae_dev, num_vfs); 3119 } 3120 3121 /* hns3_remove - Device removal routine 3122 * @pdev: PCI device information struct 3123 */ 3124 static void hns3_remove(struct pci_dev *pdev) 3125 { 3126 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3127 3128 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 3129 hns3_disable_sriov(pdev); 3130 3131 hnae3_unregister_ae_dev(ae_dev); 3132 pci_set_drvdata(pdev, NULL); 3133 } 3134 3135 /** 3136 * hns3_pci_sriov_configure 3137 * @pdev: pointer to a pci_dev structure 3138 * @num_vfs: number of VFs to allocate 3139 * 3140 * Enable or change the number of VFs. Called when the user updates the number 3141 * of VFs in sysfs. 3142 **/ 3143 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 3144 { 3145 int ret; 3146 3147 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 3148 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 3149 return -EINVAL; 3150 } 3151 3152 if (num_vfs) { 3153 ret = pci_enable_sriov(pdev, num_vfs); 3154 if (ret) 3155 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 3156 else 3157 return num_vfs; 3158 } else if (!pci_vfs_assigned(pdev)) { 3159 int num_vfs_pre = pci_num_vf(pdev); 3160 3161 pci_disable_sriov(pdev); 3162 hns3_clean_vf_config(pdev, num_vfs_pre); 3163 } else { 3164 dev_warn(&pdev->dev, 3165 "Unable to free VFs because some are assigned to VMs.\n"); 3166 } 3167 3168 return 0; 3169 } 3170 3171 static void hns3_shutdown(struct pci_dev *pdev) 3172 { 3173 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3174 3175 hnae3_unregister_ae_dev(ae_dev); 3176 pci_set_drvdata(pdev, NULL); 3177 3178 if (system_state == SYSTEM_POWER_OFF) 3179 pci_set_power_state(pdev, PCI_D3hot); 3180 } 3181 3182 static int __maybe_unused hns3_suspend(struct device *dev) 3183 { 3184 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3185 3186 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3187 dev_info(dev, "Begin to suspend.\n"); 3188 if (ae_dev->ops && ae_dev->ops->reset_prepare) 3189 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET); 3190 } 3191 3192 return 0; 3193 } 3194 3195 static int __maybe_unused hns3_resume(struct device *dev) 3196 { 3197 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3198 3199 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3200 dev_info(dev, "Begin to resume.\n"); 3201 if (ae_dev->ops && ae_dev->ops->reset_done) 3202 ae_dev->ops->reset_done(ae_dev); 3203 } 3204 3205 return 0; 3206 } 3207 3208 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 3209 pci_channel_state_t state) 3210 { 3211 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3212 pci_ers_result_t ret; 3213 3214 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state); 3215 3216 if (state == pci_channel_io_perm_failure) 3217 return PCI_ERS_RESULT_DISCONNECT; 3218 3219 if (!ae_dev || !ae_dev->ops) { 3220 dev_err(&pdev->dev, 3221 "Can't recover - error happened before device initialized\n"); 3222 return PCI_ERS_RESULT_NONE; 3223 } 3224 3225 if (ae_dev->ops->handle_hw_ras_error) 3226 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 3227 else 3228 return PCI_ERS_RESULT_NONE; 3229 3230 return ret; 3231 } 3232 3233 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 3234 { 3235 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3236 const struct hnae3_ae_ops *ops; 3237 enum hnae3_reset_type reset_type; 3238 struct device *dev = &pdev->dev; 3239 3240 if (!ae_dev || !ae_dev->ops) 3241 return PCI_ERS_RESULT_NONE; 3242 3243 ops = ae_dev->ops; 3244 /* request the reset */ 3245 if (ops->reset_event && ops->get_reset_level && 3246 ops->set_default_reset_request) { 3247 if (ae_dev->hw_err_reset_req) { 3248 reset_type = ops->get_reset_level(ae_dev, 3249 &ae_dev->hw_err_reset_req); 3250 ops->set_default_reset_request(ae_dev, reset_type); 3251 dev_info(dev, "requesting reset due to PCI error\n"); 3252 ops->reset_event(pdev, NULL); 3253 } 3254 3255 return PCI_ERS_RESULT_RECOVERED; 3256 } 3257 3258 return PCI_ERS_RESULT_DISCONNECT; 3259 } 3260 3261 static void hns3_reset_prepare(struct pci_dev *pdev) 3262 { 3263 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3264 3265 dev_info(&pdev->dev, "FLR prepare\n"); 3266 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare) 3267 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET); 3268 } 3269 3270 static void hns3_reset_done(struct pci_dev *pdev) 3271 { 3272 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3273 3274 dev_info(&pdev->dev, "FLR done\n"); 3275 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done) 3276 ae_dev->ops->reset_done(ae_dev); 3277 } 3278 3279 static const struct pci_error_handlers hns3_err_handler = { 3280 .error_detected = hns3_error_detected, 3281 .slot_reset = hns3_slot_reset, 3282 .reset_prepare = hns3_reset_prepare, 3283 .reset_done = hns3_reset_done, 3284 }; 3285 3286 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume); 3287 3288 static struct pci_driver hns3_driver = { 3289 .name = hns3_driver_name, 3290 .id_table = hns3_pci_tbl, 3291 .probe = hns3_probe, 3292 .remove = hns3_remove, 3293 .shutdown = hns3_shutdown, 3294 .driver.pm = &hns3_pm_ops, 3295 .sriov_configure = hns3_pci_sriov_configure, 3296 .err_handler = &hns3_err_handler, 3297 }; 3298 3299 /* set default feature to hns3 */ 3300 static void hns3_set_default_feature(struct net_device *netdev) 3301 { 3302 struct hnae3_handle *h = hns3_get_handle(netdev); 3303 struct pci_dev *pdev = h->pdev; 3304 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3305 3306 netdev->priv_flags |= IFF_UNICAST_FLT; 3307 3308 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 3309 3310 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3311 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 3312 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 3313 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 3314 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 3315 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 3316 3317 if (hnae3_ae_dev_gro_supported(ae_dev)) 3318 netdev->features |= NETIF_F_GRO_HW; 3319 3320 if (hnae3_ae_dev_fd_supported(ae_dev)) 3321 netdev->features |= NETIF_F_NTUPLE; 3322 3323 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) 3324 netdev->features |= NETIF_F_GSO_UDP_L4; 3325 3326 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 3327 netdev->features |= NETIF_F_HW_CSUM; 3328 else 3329 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 3330 3331 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) 3332 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 3333 3334 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) 3335 netdev->features |= NETIF_F_HW_TC; 3336 3337 netdev->hw_features |= netdev->features; 3338 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 3339 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 3340 3341 netdev->vlan_features |= netdev->features & 3342 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX | 3343 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE | 3344 NETIF_F_HW_TC); 3345 3346 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID; 3347 } 3348 3349 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 3350 struct hns3_desc_cb *cb) 3351 { 3352 unsigned int order = hns3_page_order(ring); 3353 struct page *p; 3354 3355 if (ring->page_pool) { 3356 p = page_pool_dev_alloc_frag(ring->page_pool, 3357 &cb->page_offset, 3358 hns3_buf_size(ring)); 3359 if (unlikely(!p)) 3360 return -ENOMEM; 3361 3362 cb->priv = p; 3363 cb->buf = page_address(p); 3364 cb->dma = page_pool_get_dma_addr(p); 3365 cb->type = DESC_TYPE_PP_FRAG; 3366 cb->reuse_flag = 0; 3367 return 0; 3368 } 3369 3370 p = dev_alloc_pages(order); 3371 if (!p) 3372 return -ENOMEM; 3373 3374 cb->priv = p; 3375 cb->page_offset = 0; 3376 cb->reuse_flag = 0; 3377 cb->buf = page_address(p); 3378 cb->length = hns3_page_size(ring); 3379 cb->type = DESC_TYPE_PAGE; 3380 page_ref_add(p, USHRT_MAX - 1); 3381 cb->pagecnt_bias = USHRT_MAX; 3382 3383 return 0; 3384 } 3385 3386 static void hns3_free_buffer(struct hns3_enet_ring *ring, 3387 struct hns3_desc_cb *cb, int budget) 3388 { 3389 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD | 3390 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB)) 3391 napi_consume_skb(cb->priv, budget); 3392 else if (!HNAE3_IS_TX_RING(ring)) { 3393 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias) 3394 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 3395 else if (cb->type & DESC_TYPE_PP_FRAG) 3396 page_pool_put_full_page(ring->page_pool, cb->priv, 3397 false); 3398 } 3399 memset(cb, 0, sizeof(*cb)); 3400 } 3401 3402 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 3403 { 3404 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 3405 cb->length, ring_to_dma_dir(ring)); 3406 3407 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 3408 return -EIO; 3409 3410 return 0; 3411 } 3412 3413 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 3414 struct hns3_desc_cb *cb) 3415 { 3416 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 3417 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 3418 ring_to_dma_dir(ring)); 3419 else if ((cb->type & DESC_TYPE_PAGE) && cb->length) 3420 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 3421 ring_to_dma_dir(ring)); 3422 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD | 3423 DESC_TYPE_SGL_SKB)) 3424 hns3_tx_spare_reclaim_cb(ring, cb); 3425 } 3426 3427 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 3428 { 3429 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3430 ring->desc[i].addr = 0; 3431 ring->desc_cb[i].refill = 0; 3432 } 3433 3434 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 3435 int budget) 3436 { 3437 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 3438 3439 if (!ring->desc_cb[i].dma) 3440 return; 3441 3442 hns3_buffer_detach(ring, i); 3443 hns3_free_buffer(ring, cb, budget); 3444 } 3445 3446 static void hns3_free_buffers(struct hns3_enet_ring *ring) 3447 { 3448 int i; 3449 3450 for (i = 0; i < ring->desc_num; i++) 3451 hns3_free_buffer_detach(ring, i, 0); 3452 } 3453 3454 /* free desc along with its attached buffer */ 3455 static void hns3_free_desc(struct hns3_enet_ring *ring) 3456 { 3457 int size = ring->desc_num * sizeof(ring->desc[0]); 3458 3459 hns3_free_buffers(ring); 3460 3461 if (ring->desc) { 3462 dma_free_coherent(ring_to_dev(ring), size, 3463 ring->desc, ring->desc_dma_addr); 3464 ring->desc = NULL; 3465 } 3466 } 3467 3468 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 3469 { 3470 int size = ring->desc_num * sizeof(ring->desc[0]); 3471 3472 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 3473 &ring->desc_dma_addr, GFP_KERNEL); 3474 if (!ring->desc) 3475 return -ENOMEM; 3476 3477 return 0; 3478 } 3479 3480 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 3481 struct hns3_desc_cb *cb) 3482 { 3483 int ret; 3484 3485 ret = hns3_alloc_buffer(ring, cb); 3486 if (ret || ring->page_pool) 3487 goto out; 3488 3489 ret = hns3_map_buffer(ring, cb); 3490 if (ret) 3491 goto out_with_buf; 3492 3493 return 0; 3494 3495 out_with_buf: 3496 hns3_free_buffer(ring, cb, 0); 3497 out: 3498 return ret; 3499 } 3500 3501 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 3502 { 3503 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 3504 3505 if (ret) 3506 return ret; 3507 3508 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3509 ring->desc_cb[i].page_offset); 3510 ring->desc_cb[i].refill = 1; 3511 3512 return 0; 3513 } 3514 3515 /* Allocate memory for raw pkg, and map with dma */ 3516 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 3517 { 3518 int i, j, ret; 3519 3520 for (i = 0; i < ring->desc_num; i++) { 3521 ret = hns3_alloc_and_attach_buffer(ring, i); 3522 if (ret) 3523 goto out_buffer_fail; 3524 } 3525 3526 return 0; 3527 3528 out_buffer_fail: 3529 for (j = i - 1; j >= 0; j--) 3530 hns3_free_buffer_detach(ring, j, 0); 3531 return ret; 3532 } 3533 3534 /* detach a in-used buffer and replace with a reserved one */ 3535 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 3536 struct hns3_desc_cb *res_cb) 3537 { 3538 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3539 ring->desc_cb[i] = *res_cb; 3540 ring->desc_cb[i].refill = 1; 3541 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3542 ring->desc_cb[i].page_offset); 3543 ring->desc[i].rx.bd_base_info = 0; 3544 } 3545 3546 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 3547 { 3548 ring->desc_cb[i].reuse_flag = 0; 3549 ring->desc_cb[i].refill = 1; 3550 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3551 ring->desc_cb[i].page_offset); 3552 ring->desc[i].rx.bd_base_info = 0; 3553 3554 dma_sync_single_for_device(ring_to_dev(ring), 3555 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 3556 hns3_buf_size(ring), 3557 DMA_FROM_DEVICE); 3558 } 3559 3560 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 3561 int *bytes, int *pkts, int budget) 3562 { 3563 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 3564 * smp_store_release() is not used in hns3_tx_doorbell() because 3565 * the doorbell operation already have the needed barrier operation. 3566 */ 3567 int ltu = smp_load_acquire(&ring->last_to_use); 3568 int ntc = ring->next_to_clean; 3569 struct hns3_desc_cb *desc_cb; 3570 bool reclaimed = false; 3571 struct hns3_desc *desc; 3572 3573 while (ltu != ntc) { 3574 desc = &ring->desc[ntc]; 3575 3576 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 3577 BIT(HNS3_TXD_VLD_B)) 3578 break; 3579 3580 desc_cb = &ring->desc_cb[ntc]; 3581 3582 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL | 3583 DESC_TYPE_BOUNCE_HEAD | 3584 DESC_TYPE_SGL_SKB)) { 3585 (*pkts)++; 3586 (*bytes) += desc_cb->send_bytes; 3587 } 3588 3589 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 3590 hns3_free_buffer_detach(ring, ntc, budget); 3591 3592 if (++ntc == ring->desc_num) 3593 ntc = 0; 3594 3595 /* Issue prefetch for next Tx descriptor */ 3596 prefetch(&ring->desc_cb[ntc]); 3597 reclaimed = true; 3598 } 3599 3600 if (unlikely(!reclaimed)) 3601 return false; 3602 3603 /* This smp_store_release() pairs with smp_load_acquire() in 3604 * ring_space called by hns3_nic_net_xmit. 3605 */ 3606 smp_store_release(&ring->next_to_clean, ntc); 3607 3608 hns3_tx_spare_update(ring); 3609 3610 return true; 3611 } 3612 3613 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 3614 { 3615 struct net_device *netdev = ring_to_netdev(ring); 3616 struct hns3_nic_priv *priv = netdev_priv(netdev); 3617 struct netdev_queue *dev_queue; 3618 int bytes, pkts; 3619 3620 bytes = 0; 3621 pkts = 0; 3622 3623 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 3624 return; 3625 3626 ring->tqp_vector->tx_group.total_bytes += bytes; 3627 ring->tqp_vector->tx_group.total_packets += pkts; 3628 3629 u64_stats_update_begin(&ring->syncp); 3630 ring->stats.tx_bytes += bytes; 3631 ring->stats.tx_pkts += pkts; 3632 u64_stats_update_end(&ring->syncp); 3633 3634 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 3635 netdev_tx_completed_queue(dev_queue, pkts, bytes); 3636 3637 if (unlikely(netif_carrier_ok(netdev) && 3638 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 3639 /* Make sure that anybody stopping the queue after this 3640 * sees the new next_to_clean. 3641 */ 3642 smp_mb(); 3643 if (netif_tx_queue_stopped(dev_queue) && 3644 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 3645 netif_tx_wake_queue(dev_queue); 3646 ring->stats.restart_queue++; 3647 } 3648 } 3649 } 3650 3651 static int hns3_desc_unused(struct hns3_enet_ring *ring) 3652 { 3653 int ntc = ring->next_to_clean; 3654 int ntu = ring->next_to_use; 3655 3656 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill)) 3657 return ring->desc_num; 3658 3659 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 3660 } 3661 3662 /* Return true if there is any allocation failure */ 3663 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 3664 int cleand_count) 3665 { 3666 struct hns3_desc_cb *desc_cb; 3667 struct hns3_desc_cb res_cbs; 3668 int i, ret; 3669 3670 for (i = 0; i < cleand_count; i++) { 3671 desc_cb = &ring->desc_cb[ring->next_to_use]; 3672 if (desc_cb->reuse_flag) { 3673 hns3_ring_stats_update(ring, reuse_pg_cnt); 3674 3675 hns3_reuse_buffer(ring, ring->next_to_use); 3676 } else { 3677 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 3678 if (ret) { 3679 hns3_ring_stats_update(ring, sw_err_cnt); 3680 3681 hns3_rl_err(ring_to_netdev(ring), 3682 "alloc rx buffer failed: %d\n", 3683 ret); 3684 3685 writel(i, ring->tqp->io_base + 3686 HNS3_RING_RX_RING_HEAD_REG); 3687 return true; 3688 } 3689 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 3690 3691 hns3_ring_stats_update(ring, non_reuse_pg); 3692 } 3693 3694 ring_ptr_move_fw(ring, next_to_use); 3695 } 3696 3697 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 3698 return false; 3699 } 3700 3701 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 3702 { 3703 return page_count(cb->priv) == cb->pagecnt_bias; 3704 } 3705 3706 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i, 3707 struct hns3_enet_ring *ring, 3708 int pull_len, 3709 struct hns3_desc_cb *desc_cb) 3710 { 3711 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3712 u32 frag_offset = desc_cb->page_offset + pull_len; 3713 int size = le16_to_cpu(desc->rx.size); 3714 u32 frag_size = size - pull_len; 3715 void *frag = napi_alloc_frag(frag_size); 3716 3717 if (unlikely(!frag)) { 3718 hns3_ring_stats_update(ring, frag_alloc_err); 3719 3720 hns3_rl_err(ring_to_netdev(ring), 3721 "failed to allocate rx frag\n"); 3722 return -ENOMEM; 3723 } 3724 3725 desc_cb->reuse_flag = 1; 3726 memcpy(frag, desc_cb->buf + frag_offset, frag_size); 3727 skb_add_rx_frag(skb, i, virt_to_page(frag), 3728 offset_in_page(frag), frag_size, frag_size); 3729 3730 hns3_ring_stats_update(ring, frag_alloc); 3731 return 0; 3732 } 3733 3734 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 3735 struct hns3_enet_ring *ring, int pull_len, 3736 struct hns3_desc_cb *desc_cb) 3737 { 3738 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3739 u32 frag_offset = desc_cb->page_offset + pull_len; 3740 int size = le16_to_cpu(desc->rx.size); 3741 u32 truesize = hns3_buf_size(ring); 3742 u32 frag_size = size - pull_len; 3743 int ret = 0; 3744 bool reused; 3745 3746 if (ring->page_pool) { 3747 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3748 frag_size, truesize); 3749 return; 3750 } 3751 3752 /* Avoid re-using remote or pfmem page */ 3753 if (unlikely(!dev_page_is_reusable(desc_cb->priv))) 3754 goto out; 3755 3756 reused = hns3_can_reuse_page(desc_cb); 3757 3758 /* Rx page can be reused when: 3759 * 1. Rx page is only owned by the driver when page_offset 3760 * is zero, which means 0 @ truesize will be used by 3761 * stack after skb_add_rx_frag() is called, and the rest 3762 * of rx page can be reused by driver. 3763 * Or 3764 * 2. Rx page is only owned by the driver when page_offset 3765 * is non-zero, which means page_offset @ truesize will 3766 * be used by stack after skb_add_rx_frag() is called, 3767 * and 0 @ truesize can be reused by driver. 3768 */ 3769 if ((!desc_cb->page_offset && reused) || 3770 ((desc_cb->page_offset + truesize + truesize) <= 3771 hns3_page_size(ring) && desc_cb->page_offset)) { 3772 desc_cb->page_offset += truesize; 3773 desc_cb->reuse_flag = 1; 3774 } else if (desc_cb->page_offset && reused) { 3775 desc_cb->page_offset = 0; 3776 desc_cb->reuse_flag = 1; 3777 } else if (frag_size <= ring->rx_copybreak) { 3778 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb); 3779 if (ret) 3780 goto out; 3781 } 3782 3783 out: 3784 desc_cb->pagecnt_bias--; 3785 3786 if (unlikely(!desc_cb->pagecnt_bias)) { 3787 page_ref_add(desc_cb->priv, USHRT_MAX); 3788 desc_cb->pagecnt_bias = USHRT_MAX; 3789 } 3790 3791 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3792 frag_size, truesize); 3793 3794 if (unlikely(!desc_cb->reuse_flag)) 3795 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3796 } 3797 3798 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 3799 { 3800 __be16 type = skb->protocol; 3801 struct tcphdr *th; 3802 int depth = 0; 3803 3804 while (eth_type_vlan(type)) { 3805 struct vlan_hdr *vh; 3806 3807 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 3808 return -EFAULT; 3809 3810 vh = (struct vlan_hdr *)(skb->data + depth); 3811 type = vh->h_vlan_encapsulated_proto; 3812 depth += VLAN_HLEN; 3813 } 3814 3815 skb_set_network_header(skb, depth); 3816 3817 if (type == htons(ETH_P_IP)) { 3818 const struct iphdr *iph = ip_hdr(skb); 3819 3820 depth += sizeof(struct iphdr); 3821 skb_set_transport_header(skb, depth); 3822 th = tcp_hdr(skb); 3823 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 3824 iph->daddr, 0); 3825 } else if (type == htons(ETH_P_IPV6)) { 3826 const struct ipv6hdr *iph = ipv6_hdr(skb); 3827 3828 depth += sizeof(struct ipv6hdr); 3829 skb_set_transport_header(skb, depth); 3830 th = tcp_hdr(skb); 3831 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 3832 &iph->daddr, 0); 3833 } else { 3834 hns3_rl_err(skb->dev, 3835 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 3836 be16_to_cpu(type), depth); 3837 return -EFAULT; 3838 } 3839 3840 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 3841 if (th->cwr) 3842 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 3843 3844 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 3845 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 3846 3847 skb->csum_start = (unsigned char *)th - skb->head; 3848 skb->csum_offset = offsetof(struct tcphdr, check); 3849 skb->ip_summed = CHECKSUM_PARTIAL; 3850 3851 trace_hns3_gro(skb); 3852 3853 return 0; 3854 } 3855 3856 static bool hns3_checksum_complete(struct hns3_enet_ring *ring, 3857 struct sk_buff *skb, u32 ptype, u16 csum) 3858 { 3859 if (ptype == HNS3_INVALID_PTYPE || 3860 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE) 3861 return false; 3862 3863 hns3_ring_stats_update(ring, csum_complete); 3864 skb->ip_summed = CHECKSUM_COMPLETE; 3865 skb->csum = csum_unfold((__force __sum16)csum); 3866 3867 return true; 3868 } 3869 3870 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info, 3871 u32 ol_info, u32 ptype) 3872 { 3873 int l3_type, l4_type; 3874 int ol4_type; 3875 3876 if (ptype != HNS3_INVALID_PTYPE) { 3877 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level; 3878 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed; 3879 3880 return; 3881 } 3882 3883 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 3884 HNS3_RXD_OL4ID_S); 3885 switch (ol4_type) { 3886 case HNS3_OL4_TYPE_MAC_IN_UDP: 3887 case HNS3_OL4_TYPE_NVGRE: 3888 skb->csum_level = 1; 3889 fallthrough; 3890 case HNS3_OL4_TYPE_NO_TUN: 3891 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3892 HNS3_RXD_L3ID_S); 3893 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 3894 HNS3_RXD_L4ID_S); 3895 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 3896 if ((l3_type == HNS3_L3_TYPE_IPV4 || 3897 l3_type == HNS3_L3_TYPE_IPV6) && 3898 (l4_type == HNS3_L4_TYPE_UDP || 3899 l4_type == HNS3_L4_TYPE_TCP || 3900 l4_type == HNS3_L4_TYPE_SCTP)) 3901 skb->ip_summed = CHECKSUM_UNNECESSARY; 3902 break; 3903 default: 3904 break; 3905 } 3906 } 3907 3908 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 3909 u32 l234info, u32 bd_base_info, u32 ol_info, 3910 u16 csum) 3911 { 3912 struct net_device *netdev = ring_to_netdev(ring); 3913 struct hns3_nic_priv *priv = netdev_priv(netdev); 3914 u32 ptype = HNS3_INVALID_PTYPE; 3915 3916 skb->ip_summed = CHECKSUM_NONE; 3917 3918 skb_checksum_none_assert(skb); 3919 3920 if (!(netdev->features & NETIF_F_RXCSUM)) 3921 return; 3922 3923 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) 3924 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3925 HNS3_RXD_PTYPE_S); 3926 3927 if (hns3_checksum_complete(ring, skb, ptype, csum)) 3928 return; 3929 3930 /* check if hardware has done checksum */ 3931 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 3932 return; 3933 3934 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 3935 BIT(HNS3_RXD_OL3E_B) | 3936 BIT(HNS3_RXD_OL4E_B)))) { 3937 hns3_ring_stats_update(ring, l3l4_csum_err); 3938 3939 return; 3940 } 3941 3942 hns3_rx_handle_csum(skb, l234info, ol_info, ptype); 3943 } 3944 3945 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 3946 { 3947 if (skb_has_frag_list(skb)) 3948 napi_gro_flush(&ring->tqp_vector->napi, false); 3949 3950 napi_gro_receive(&ring->tqp_vector->napi, skb); 3951 } 3952 3953 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 3954 struct hns3_desc *desc, u32 l234info, 3955 u16 *vlan_tag) 3956 { 3957 struct hnae3_handle *handle = ring->tqp->handle; 3958 struct pci_dev *pdev = ring->tqp->handle->pdev; 3959 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3960 3961 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 3962 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3963 if (!(*vlan_tag & VLAN_VID_MASK)) 3964 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3965 3966 return (*vlan_tag != 0); 3967 } 3968 3969 #define HNS3_STRP_OUTER_VLAN 0x1 3970 #define HNS3_STRP_INNER_VLAN 0x2 3971 #define HNS3_STRP_BOTH 0x3 3972 3973 /* Hardware always insert VLAN tag into RX descriptor when 3974 * remove the tag from packet, driver needs to determine 3975 * reporting which tag to stack. 3976 */ 3977 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 3978 HNS3_RXD_STRP_TAGP_S)) { 3979 case HNS3_STRP_OUTER_VLAN: 3980 if (handle->port_base_vlan_state != 3981 HNAE3_PORT_BASE_VLAN_DISABLE) 3982 return false; 3983 3984 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3985 return true; 3986 case HNS3_STRP_INNER_VLAN: 3987 if (handle->port_base_vlan_state != 3988 HNAE3_PORT_BASE_VLAN_DISABLE) 3989 return false; 3990 3991 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3992 return true; 3993 case HNS3_STRP_BOTH: 3994 if (handle->port_base_vlan_state == 3995 HNAE3_PORT_BASE_VLAN_DISABLE) 3996 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3997 else 3998 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3999 4000 return true; 4001 default: 4002 return false; 4003 } 4004 } 4005 4006 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 4007 { 4008 ring->desc[ring->next_to_clean].rx.bd_base_info &= 4009 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 4010 ring->desc_cb[ring->next_to_clean].refill = 0; 4011 ring->next_to_clean += 1; 4012 4013 if (unlikely(ring->next_to_clean == ring->desc_num)) 4014 ring->next_to_clean = 0; 4015 } 4016 4017 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 4018 unsigned char *va) 4019 { 4020 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 4021 struct net_device *netdev = ring_to_netdev(ring); 4022 struct sk_buff *skb; 4023 4024 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 4025 skb = ring->skb; 4026 if (unlikely(!skb)) { 4027 hns3_rl_err(netdev, "alloc rx skb fail\n"); 4028 hns3_ring_stats_update(ring, sw_err_cnt); 4029 4030 return -ENOMEM; 4031 } 4032 4033 trace_hns3_rx_desc(ring); 4034 prefetchw(skb->data); 4035 4036 ring->pending_buf = 1; 4037 ring->frag_num = 0; 4038 ring->tail_skb = NULL; 4039 if (length <= HNS3_RX_HEAD_SIZE) { 4040 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 4041 4042 /* We can reuse buffer as-is, just make sure it is reusable */ 4043 if (dev_page_is_reusable(desc_cb->priv)) 4044 desc_cb->reuse_flag = 1; 4045 else if (desc_cb->type & DESC_TYPE_PP_FRAG) 4046 page_pool_put_full_page(ring->page_pool, desc_cb->priv, 4047 false); 4048 else /* This page cannot be reused so discard it */ 4049 __page_frag_cache_drain(desc_cb->priv, 4050 desc_cb->pagecnt_bias); 4051 4052 hns3_rx_ring_move_fw(ring); 4053 return 0; 4054 } 4055 4056 if (ring->page_pool) 4057 skb_mark_for_recycle(skb); 4058 4059 hns3_ring_stats_update(ring, seg_pkt_cnt); 4060 4061 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 4062 __skb_put(skb, ring->pull_len); 4063 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 4064 desc_cb); 4065 hns3_rx_ring_move_fw(ring); 4066 4067 return 0; 4068 } 4069 4070 static int hns3_add_frag(struct hns3_enet_ring *ring) 4071 { 4072 struct sk_buff *skb = ring->skb; 4073 struct sk_buff *head_skb = skb; 4074 struct sk_buff *new_skb; 4075 struct hns3_desc_cb *desc_cb; 4076 struct hns3_desc *desc; 4077 u32 bd_base_info; 4078 4079 do { 4080 desc = &ring->desc[ring->next_to_clean]; 4081 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4082 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4083 /* make sure HW write desc complete */ 4084 dma_rmb(); 4085 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 4086 return -ENXIO; 4087 4088 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 4089 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 4090 if (unlikely(!new_skb)) { 4091 hns3_rl_err(ring_to_netdev(ring), 4092 "alloc rx fraglist skb fail\n"); 4093 return -ENXIO; 4094 } 4095 4096 if (ring->page_pool) 4097 skb_mark_for_recycle(new_skb); 4098 4099 ring->frag_num = 0; 4100 4101 if (ring->tail_skb) { 4102 ring->tail_skb->next = new_skb; 4103 ring->tail_skb = new_skb; 4104 } else { 4105 skb_shinfo(skb)->frag_list = new_skb; 4106 ring->tail_skb = new_skb; 4107 } 4108 } 4109 4110 if (ring->tail_skb) { 4111 head_skb->truesize += hns3_buf_size(ring); 4112 head_skb->data_len += le16_to_cpu(desc->rx.size); 4113 head_skb->len += le16_to_cpu(desc->rx.size); 4114 skb = ring->tail_skb; 4115 } 4116 4117 dma_sync_single_for_cpu(ring_to_dev(ring), 4118 desc_cb->dma + desc_cb->page_offset, 4119 hns3_buf_size(ring), 4120 DMA_FROM_DEVICE); 4121 4122 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 4123 trace_hns3_rx_desc(ring); 4124 hns3_rx_ring_move_fw(ring); 4125 ring->pending_buf++; 4126 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 4127 4128 return 0; 4129 } 4130 4131 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 4132 struct sk_buff *skb, u32 l234info, 4133 u32 bd_base_info, u32 ol_info, u16 csum) 4134 { 4135 struct net_device *netdev = ring_to_netdev(ring); 4136 struct hns3_nic_priv *priv = netdev_priv(netdev); 4137 u32 l3_type; 4138 4139 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 4140 HNS3_RXD_GRO_SIZE_M, 4141 HNS3_RXD_GRO_SIZE_S); 4142 /* if there is no HW GRO, do not set gro params */ 4143 if (!skb_shinfo(skb)->gso_size) { 4144 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info, 4145 csum); 4146 return 0; 4147 } 4148 4149 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 4150 HNS3_RXD_GRO_COUNT_M, 4151 HNS3_RXD_GRO_COUNT_S); 4152 4153 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 4154 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 4155 HNS3_RXD_PTYPE_S); 4156 4157 l3_type = hns3_rx_ptype_tbl[ptype].l3_type; 4158 } else { 4159 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 4160 HNS3_RXD_L3ID_S); 4161 } 4162 4163 if (l3_type == HNS3_L3_TYPE_IPV4) 4164 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 4165 else if (l3_type == HNS3_L3_TYPE_IPV6) 4166 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 4167 else 4168 return -EFAULT; 4169 4170 return hns3_gro_complete(skb, l234info); 4171 } 4172 4173 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 4174 struct sk_buff *skb, u32 rss_hash) 4175 { 4176 struct hnae3_handle *handle = ring->tqp->handle; 4177 enum pkt_hash_types rss_type; 4178 4179 if (rss_hash) 4180 rss_type = handle->kinfo.rss_type; 4181 else 4182 rss_type = PKT_HASH_TYPE_NONE; 4183 4184 skb_set_hash(skb, rss_hash, rss_type); 4185 } 4186 4187 static void hns3_handle_rx_ts_info(struct net_device *netdev, 4188 struct hns3_desc *desc, struct sk_buff *skb, 4189 u32 bd_base_info) 4190 { 4191 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) { 4192 struct hnae3_handle *h = hns3_get_handle(netdev); 4193 u32 nsec = le32_to_cpu(desc->ts_nsec); 4194 u32 sec = le32_to_cpu(desc->ts_sec); 4195 4196 if (h->ae_algo->ops->get_rx_hwts) 4197 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec); 4198 } 4199 } 4200 4201 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring, 4202 struct hns3_desc *desc, struct sk_buff *skb, 4203 u32 l234info) 4204 { 4205 struct net_device *netdev = ring_to_netdev(ring); 4206 4207 /* Based on hw strategy, the tag offloaded will be stored at 4208 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 4209 * in one layer tag case. 4210 */ 4211 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 4212 u16 vlan_tag; 4213 4214 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 4215 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 4216 vlan_tag); 4217 } 4218 } 4219 4220 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 4221 { 4222 struct net_device *netdev = ring_to_netdev(ring); 4223 enum hns3_pkt_l2t_type l2_frame_type; 4224 u32 bd_base_info, l234info, ol_info; 4225 struct hns3_desc *desc; 4226 unsigned int len; 4227 int pre_ntc, ret; 4228 u16 csum; 4229 4230 /* bdinfo handled below is only valid on the last BD of the 4231 * current packet, and ring->next_to_clean indicates the first 4232 * descriptor of next packet, so need - 1 below. 4233 */ 4234 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 4235 (ring->desc_num - 1); 4236 desc = &ring->desc[pre_ntc]; 4237 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4238 l234info = le32_to_cpu(desc->rx.l234_info); 4239 ol_info = le32_to_cpu(desc->rx.ol_info); 4240 csum = le16_to_cpu(desc->csum); 4241 4242 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info); 4243 4244 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info); 4245 4246 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 4247 BIT(HNS3_RXD_L2E_B))))) { 4248 u64_stats_update_begin(&ring->syncp); 4249 if (l234info & BIT(HNS3_RXD_L2E_B)) 4250 ring->stats.l2_err++; 4251 else 4252 ring->stats.err_pkt_len++; 4253 u64_stats_update_end(&ring->syncp); 4254 4255 return -EFAULT; 4256 } 4257 4258 len = skb->len; 4259 4260 /* Do update ip stack process */ 4261 skb->protocol = eth_type_trans(skb, netdev); 4262 4263 /* This is needed in order to enable forwarding support */ 4264 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 4265 bd_base_info, ol_info, csum); 4266 if (unlikely(ret)) { 4267 hns3_ring_stats_update(ring, rx_err_cnt); 4268 return ret; 4269 } 4270 4271 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 4272 HNS3_RXD_DMAC_S); 4273 4274 u64_stats_update_begin(&ring->syncp); 4275 ring->stats.rx_pkts++; 4276 ring->stats.rx_bytes += len; 4277 4278 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 4279 ring->stats.rx_multicast++; 4280 4281 u64_stats_update_end(&ring->syncp); 4282 4283 ring->tqp_vector->rx_group.total_bytes += len; 4284 4285 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 4286 return 0; 4287 } 4288 4289 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 4290 { 4291 struct sk_buff *skb = ring->skb; 4292 struct hns3_desc_cb *desc_cb; 4293 struct hns3_desc *desc; 4294 unsigned int length; 4295 u32 bd_base_info; 4296 int ret; 4297 4298 desc = &ring->desc[ring->next_to_clean]; 4299 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4300 4301 prefetch(desc); 4302 4303 if (!skb) { 4304 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4305 /* Check valid BD */ 4306 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 4307 return -ENXIO; 4308 4309 dma_rmb(); 4310 length = le16_to_cpu(desc->rx.size); 4311 4312 ring->va = desc_cb->buf + desc_cb->page_offset; 4313 4314 dma_sync_single_for_cpu(ring_to_dev(ring), 4315 desc_cb->dma + desc_cb->page_offset, 4316 hns3_buf_size(ring), 4317 DMA_FROM_DEVICE); 4318 4319 /* Prefetch first cache line of first page. 4320 * Idea is to cache few bytes of the header of the packet. 4321 * Our L1 Cache line size is 64B so need to prefetch twice to make 4322 * it 128B. But in actual we can have greater size of caches with 4323 * 128B Level 1 cache lines. In such a case, single fetch would 4324 * suffice to cache in the relevant part of the header. 4325 */ 4326 net_prefetch(ring->va); 4327 4328 ret = hns3_alloc_skb(ring, length, ring->va); 4329 skb = ring->skb; 4330 4331 if (ret < 0) /* alloc buffer fail */ 4332 return ret; 4333 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 4334 ret = hns3_add_frag(ring); 4335 if (ret) 4336 return ret; 4337 } 4338 } else { 4339 ret = hns3_add_frag(ring); 4340 if (ret) 4341 return ret; 4342 } 4343 4344 /* As the head data may be changed when GRO enable, copy 4345 * the head data in after other data rx completed 4346 */ 4347 if (skb->len > HNS3_RX_HEAD_SIZE) 4348 memcpy(skb->data, ring->va, 4349 ALIGN(ring->pull_len, sizeof(long))); 4350 4351 ret = hns3_handle_bdinfo(ring, skb); 4352 if (unlikely(ret)) { 4353 dev_kfree_skb_any(skb); 4354 return ret; 4355 } 4356 4357 skb_record_rx_queue(skb, ring->tqp->tqp_index); 4358 return 0; 4359 } 4360 4361 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 4362 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 4363 { 4364 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 4365 int unused_count = hns3_desc_unused(ring); 4366 bool failure = false; 4367 int recv_pkts = 0; 4368 int err; 4369 4370 unused_count -= ring->pending_buf; 4371 4372 while (recv_pkts < budget) { 4373 /* Reuse or realloc buffers */ 4374 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 4375 failure = failure || 4376 hns3_nic_alloc_rx_buffers(ring, unused_count); 4377 unused_count = 0; 4378 } 4379 4380 /* Poll one pkt */ 4381 err = hns3_handle_rx_bd(ring); 4382 /* Do not get FE for the packet or failed to alloc skb */ 4383 if (unlikely(!ring->skb || err == -ENXIO)) { 4384 goto out; 4385 } else if (likely(!err)) { 4386 rx_fn(ring, ring->skb); 4387 recv_pkts++; 4388 } 4389 4390 unused_count += ring->pending_buf; 4391 ring->skb = NULL; 4392 ring->pending_buf = 0; 4393 } 4394 4395 out: 4396 /* sync head pointer before exiting, since hardware will calculate 4397 * FBD number with head pointer 4398 */ 4399 if (unused_count > 0) 4400 failure = failure || 4401 hns3_nic_alloc_rx_buffers(ring, unused_count); 4402 4403 return failure ? budget : recv_pkts; 4404 } 4405 4406 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4407 { 4408 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 4409 struct dim_sample sample = {}; 4410 4411 if (!rx_group->coal.adapt_enable) 4412 return; 4413 4414 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets, 4415 rx_group->total_bytes, &sample); 4416 net_dim(&rx_group->dim, sample); 4417 } 4418 4419 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4420 { 4421 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 4422 struct dim_sample sample = {}; 4423 4424 if (!tx_group->coal.adapt_enable) 4425 return; 4426 4427 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets, 4428 tx_group->total_bytes, &sample); 4429 net_dim(&tx_group->dim, sample); 4430 } 4431 4432 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 4433 { 4434 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 4435 struct hns3_enet_ring *ring; 4436 int rx_pkt_total = 0; 4437 4438 struct hns3_enet_tqp_vector *tqp_vector = 4439 container_of(napi, struct hns3_enet_tqp_vector, napi); 4440 bool clean_complete = true; 4441 int rx_budget = budget; 4442 4443 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4444 napi_complete(napi); 4445 return 0; 4446 } 4447 4448 /* Since the actual Tx work is minimal, we can give the Tx a larger 4449 * budget and be more aggressive about cleaning up the Tx descriptors. 4450 */ 4451 hns3_for_each_ring(ring, tqp_vector->tx_group) 4452 hns3_clean_tx_ring(ring, budget); 4453 4454 /* make sure rx ring budget not smaller than 1 */ 4455 if (tqp_vector->num_tqps > 1) 4456 rx_budget = max(budget / tqp_vector->num_tqps, 1); 4457 4458 hns3_for_each_ring(ring, tqp_vector->rx_group) { 4459 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 4460 hns3_rx_skb); 4461 if (rx_cleaned >= rx_budget) 4462 clean_complete = false; 4463 4464 rx_pkt_total += rx_cleaned; 4465 } 4466 4467 tqp_vector->rx_group.total_packets += rx_pkt_total; 4468 4469 if (!clean_complete) 4470 return budget; 4471 4472 if (napi_complete(napi) && 4473 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4474 hns3_update_rx_int_coalesce(tqp_vector); 4475 hns3_update_tx_int_coalesce(tqp_vector); 4476 4477 hns3_mask_vector_irq(tqp_vector, 1); 4478 } 4479 4480 return rx_pkt_total; 4481 } 4482 4483 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4484 struct hnae3_ring_chain_node **head, 4485 bool is_tx) 4486 { 4487 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX; 4488 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX; 4489 struct hnae3_ring_chain_node *cur_chain = *head; 4490 struct pci_dev *pdev = tqp_vector->handle->pdev; 4491 struct hnae3_ring_chain_node *chain; 4492 struct hns3_enet_ring *ring; 4493 4494 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring; 4495 4496 if (cur_chain) { 4497 while (cur_chain->next) 4498 cur_chain = cur_chain->next; 4499 } 4500 4501 while (ring) { 4502 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 4503 if (!chain) 4504 return -ENOMEM; 4505 if (cur_chain) 4506 cur_chain->next = chain; 4507 else 4508 *head = chain; 4509 chain->tqp_index = ring->tqp->tqp_index; 4510 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 4511 bit_value); 4512 hnae3_set_field(chain->int_gl_idx, 4513 HNAE3_RING_GL_IDX_M, 4514 HNAE3_RING_GL_IDX_S, field_value); 4515 4516 cur_chain = chain; 4517 4518 ring = ring->next; 4519 } 4520 4521 return 0; 4522 } 4523 4524 static struct hnae3_ring_chain_node * 4525 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector) 4526 { 4527 struct pci_dev *pdev = tqp_vector->handle->pdev; 4528 struct hnae3_ring_chain_node *cur_chain = NULL; 4529 struct hnae3_ring_chain_node *chain; 4530 4531 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true)) 4532 goto err_free_chain; 4533 4534 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false)) 4535 goto err_free_chain; 4536 4537 return cur_chain; 4538 4539 err_free_chain: 4540 while (cur_chain) { 4541 chain = cur_chain->next; 4542 devm_kfree(&pdev->dev, cur_chain); 4543 cur_chain = chain; 4544 } 4545 4546 return NULL; 4547 } 4548 4549 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4550 struct hnae3_ring_chain_node *head) 4551 { 4552 struct pci_dev *pdev = tqp_vector->handle->pdev; 4553 struct hnae3_ring_chain_node *chain_tmp, *chain; 4554 4555 chain = head; 4556 4557 while (chain) { 4558 chain_tmp = chain->next; 4559 devm_kfree(&pdev->dev, chain); 4560 chain = chain_tmp; 4561 } 4562 } 4563 4564 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 4565 struct hns3_enet_ring *ring) 4566 { 4567 ring->next = group->ring; 4568 group->ring = ring; 4569 4570 group->count++; 4571 } 4572 4573 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 4574 { 4575 struct pci_dev *pdev = priv->ae_handle->pdev; 4576 struct hns3_enet_tqp_vector *tqp_vector; 4577 int num_vectors = priv->vector_num; 4578 int numa_node; 4579 int vector_i; 4580 4581 numa_node = dev_to_node(&pdev->dev); 4582 4583 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 4584 tqp_vector = &priv->tqp_vector[vector_i]; 4585 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 4586 &tqp_vector->affinity_mask); 4587 } 4588 } 4589 4590 static void hns3_rx_dim_work(struct work_struct *work) 4591 { 4592 struct dim *dim = container_of(work, struct dim, work); 4593 struct hns3_enet_ring_group *group = container_of(dim, 4594 struct hns3_enet_ring_group, dim); 4595 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4596 struct dim_cq_moder cur_moder = 4597 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 4598 4599 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec); 4600 tqp_vector->rx_group.coal.int_gl = cur_moder.usec; 4601 4602 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) { 4603 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts); 4604 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts; 4605 } 4606 4607 dim->state = DIM_START_MEASURE; 4608 } 4609 4610 static void hns3_tx_dim_work(struct work_struct *work) 4611 { 4612 struct dim *dim = container_of(work, struct dim, work); 4613 struct hns3_enet_ring_group *group = container_of(dim, 4614 struct hns3_enet_ring_group, dim); 4615 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4616 struct dim_cq_moder cur_moder = 4617 net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 4618 4619 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec); 4620 tqp_vector->tx_group.coal.int_gl = cur_moder.usec; 4621 4622 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) { 4623 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts); 4624 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts; 4625 } 4626 4627 dim->state = DIM_START_MEASURE; 4628 } 4629 4630 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector) 4631 { 4632 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work); 4633 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work); 4634 } 4635 4636 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 4637 { 4638 struct hnae3_handle *h = priv->ae_handle; 4639 struct hns3_enet_tqp_vector *tqp_vector; 4640 int ret; 4641 int i; 4642 4643 hns3_nic_set_cpumask(priv); 4644 4645 for (i = 0; i < priv->vector_num; i++) { 4646 tqp_vector = &priv->tqp_vector[i]; 4647 hns3_vector_coalesce_init_hw(tqp_vector, priv); 4648 tqp_vector->num_tqps = 0; 4649 hns3_nic_init_dim(tqp_vector); 4650 } 4651 4652 for (i = 0; i < h->kinfo.num_tqps; i++) { 4653 u16 vector_i = i % priv->vector_num; 4654 u16 tqp_num = h->kinfo.num_tqps; 4655 4656 tqp_vector = &priv->tqp_vector[vector_i]; 4657 4658 hns3_add_ring_to_group(&tqp_vector->tx_group, 4659 &priv->ring[i]); 4660 4661 hns3_add_ring_to_group(&tqp_vector->rx_group, 4662 &priv->ring[i + tqp_num]); 4663 4664 priv->ring[i].tqp_vector = tqp_vector; 4665 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 4666 tqp_vector->num_tqps++; 4667 } 4668 4669 for (i = 0; i < priv->vector_num; i++) { 4670 struct hnae3_ring_chain_node *vector_ring_chain; 4671 4672 tqp_vector = &priv->tqp_vector[i]; 4673 4674 tqp_vector->rx_group.total_bytes = 0; 4675 tqp_vector->rx_group.total_packets = 0; 4676 tqp_vector->tx_group.total_bytes = 0; 4677 tqp_vector->tx_group.total_packets = 0; 4678 tqp_vector->handle = h; 4679 4680 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector); 4681 if (!vector_ring_chain) { 4682 ret = -ENOMEM; 4683 goto map_ring_fail; 4684 } 4685 4686 ret = h->ae_algo->ops->map_ring_to_vector(h, 4687 tqp_vector->vector_irq, vector_ring_chain); 4688 4689 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain); 4690 4691 if (ret) 4692 goto map_ring_fail; 4693 4694 netif_napi_add(priv->netdev, &tqp_vector->napi, 4695 hns3_nic_common_poll); 4696 } 4697 4698 return 0; 4699 4700 map_ring_fail: 4701 while (i--) 4702 netif_napi_del(&priv->tqp_vector[i].napi); 4703 4704 return ret; 4705 } 4706 4707 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv) 4708 { 4709 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 4710 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal; 4711 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal; 4712 4713 /* initialize the configuration for interrupt coalescing. 4714 * 1. GL (Interrupt Gap Limiter) 4715 * 2. RL (Interrupt Rate Limiter) 4716 * 3. QL (Interrupt Quantity Limiter) 4717 * 4718 * Default: enable interrupt coalescing self-adaptive and GL 4719 */ 4720 tx_coal->adapt_enable = 1; 4721 rx_coal->adapt_enable = 1; 4722 4723 tx_coal->int_gl = HNS3_INT_GL_50K; 4724 rx_coal->int_gl = HNS3_INT_GL_50K; 4725 4726 rx_coal->flow_level = HNS3_FLOW_LOW; 4727 tx_coal->flow_level = HNS3_FLOW_LOW; 4728 4729 if (ae_dev->dev_specs.int_ql_max) { 4730 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4731 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4732 } 4733 } 4734 4735 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 4736 { 4737 struct hnae3_handle *h = priv->ae_handle; 4738 struct hns3_enet_tqp_vector *tqp_vector; 4739 struct hnae3_vector_info *vector; 4740 struct pci_dev *pdev = h->pdev; 4741 u16 tqp_num = h->kinfo.num_tqps; 4742 u16 vector_num; 4743 int ret = 0; 4744 u16 i; 4745 4746 /* RSS size, cpu online and vector_num should be the same */ 4747 /* Should consider 2p/4p later */ 4748 vector_num = min_t(u16, num_online_cpus(), tqp_num); 4749 4750 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 4751 GFP_KERNEL); 4752 if (!vector) 4753 return -ENOMEM; 4754 4755 /* save the actual available vector number */ 4756 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 4757 4758 priv->vector_num = vector_num; 4759 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 4760 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 4761 GFP_KERNEL); 4762 if (!priv->tqp_vector) { 4763 ret = -ENOMEM; 4764 goto out; 4765 } 4766 4767 for (i = 0; i < priv->vector_num; i++) { 4768 tqp_vector = &priv->tqp_vector[i]; 4769 tqp_vector->idx = i; 4770 tqp_vector->mask_addr = vector[i].io_addr; 4771 tqp_vector->vector_irq = vector[i].vector; 4772 hns3_vector_coalesce_init(tqp_vector, priv); 4773 } 4774 4775 out: 4776 devm_kfree(&pdev->dev, vector); 4777 return ret; 4778 } 4779 4780 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 4781 { 4782 group->ring = NULL; 4783 group->count = 0; 4784 } 4785 4786 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 4787 { 4788 struct hnae3_ring_chain_node *vector_ring_chain; 4789 struct hnae3_handle *h = priv->ae_handle; 4790 struct hns3_enet_tqp_vector *tqp_vector; 4791 int i; 4792 4793 for (i = 0; i < priv->vector_num; i++) { 4794 tqp_vector = &priv->tqp_vector[i]; 4795 4796 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 4797 continue; 4798 4799 /* Since the mapping can be overwritten, when fail to get the 4800 * chain between vector and ring, we should go on to deal with 4801 * the remaining options. 4802 */ 4803 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector); 4804 if (!vector_ring_chain) 4805 dev_warn(priv->dev, "failed to get ring chain\n"); 4806 4807 h->ae_algo->ops->unmap_ring_from_vector(h, 4808 tqp_vector->vector_irq, vector_ring_chain); 4809 4810 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain); 4811 4812 hns3_clear_ring_group(&tqp_vector->rx_group); 4813 hns3_clear_ring_group(&tqp_vector->tx_group); 4814 netif_napi_del(&priv->tqp_vector[i].napi); 4815 } 4816 } 4817 4818 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 4819 { 4820 struct hnae3_handle *h = priv->ae_handle; 4821 struct pci_dev *pdev = h->pdev; 4822 int i, ret; 4823 4824 for (i = 0; i < priv->vector_num; i++) { 4825 struct hns3_enet_tqp_vector *tqp_vector; 4826 4827 tqp_vector = &priv->tqp_vector[i]; 4828 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 4829 if (ret) 4830 return; 4831 } 4832 4833 devm_kfree(&pdev->dev, priv->tqp_vector); 4834 } 4835 4836 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 4837 unsigned int ring_type) 4838 { 4839 int queue_num = priv->ae_handle->kinfo.num_tqps; 4840 struct hns3_enet_ring *ring; 4841 int desc_num; 4842 4843 if (ring_type == HNAE3_RING_TYPE_TX) { 4844 ring = &priv->ring[q->tqp_index]; 4845 desc_num = priv->ae_handle->kinfo.num_tx_desc; 4846 ring->queue_index = q->tqp_index; 4847 ring->tx_copybreak = priv->tx_copybreak; 4848 ring->last_to_use = 0; 4849 } else { 4850 ring = &priv->ring[q->tqp_index + queue_num]; 4851 desc_num = priv->ae_handle->kinfo.num_rx_desc; 4852 ring->queue_index = q->tqp_index; 4853 ring->rx_copybreak = priv->rx_copybreak; 4854 } 4855 4856 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 4857 4858 ring->tqp = q; 4859 ring->desc = NULL; 4860 ring->desc_cb = NULL; 4861 ring->dev = priv->dev; 4862 ring->desc_dma_addr = 0; 4863 ring->buf_size = q->buf_size; 4864 ring->desc_num = desc_num; 4865 ring->next_to_use = 0; 4866 ring->next_to_clean = 0; 4867 } 4868 4869 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 4870 struct hns3_nic_priv *priv) 4871 { 4872 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 4873 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 4874 } 4875 4876 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 4877 { 4878 struct hnae3_handle *h = priv->ae_handle; 4879 struct pci_dev *pdev = h->pdev; 4880 int i; 4881 4882 priv->ring = devm_kzalloc(&pdev->dev, 4883 array3_size(h->kinfo.num_tqps, 4884 sizeof(*priv->ring), 2), 4885 GFP_KERNEL); 4886 if (!priv->ring) 4887 return -ENOMEM; 4888 4889 for (i = 0; i < h->kinfo.num_tqps; i++) 4890 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 4891 4892 return 0; 4893 } 4894 4895 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 4896 { 4897 if (!priv->ring) 4898 return; 4899 4900 devm_kfree(priv->dev, priv->ring); 4901 priv->ring = NULL; 4902 } 4903 4904 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring) 4905 { 4906 struct page_pool_params pp_params = { 4907 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG | 4908 PP_FLAG_DMA_SYNC_DEV, 4909 .order = hns3_page_order(ring), 4910 .pool_size = ring->desc_num * hns3_buf_size(ring) / 4911 (PAGE_SIZE << hns3_page_order(ring)), 4912 .nid = dev_to_node(ring_to_dev(ring)), 4913 .dev = ring_to_dev(ring), 4914 .dma_dir = DMA_FROM_DEVICE, 4915 .offset = 0, 4916 .max_len = PAGE_SIZE << hns3_page_order(ring), 4917 }; 4918 4919 ring->page_pool = page_pool_create(&pp_params); 4920 if (IS_ERR(ring->page_pool)) { 4921 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n", 4922 PTR_ERR(ring->page_pool)); 4923 ring->page_pool = NULL; 4924 } 4925 } 4926 4927 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 4928 { 4929 int ret; 4930 4931 if (ring->desc_num <= 0 || ring->buf_size <= 0) 4932 return -EINVAL; 4933 4934 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 4935 sizeof(ring->desc_cb[0]), GFP_KERNEL); 4936 if (!ring->desc_cb) { 4937 ret = -ENOMEM; 4938 goto out; 4939 } 4940 4941 ret = hns3_alloc_desc(ring); 4942 if (ret) 4943 goto out_with_desc_cb; 4944 4945 if (!HNAE3_IS_TX_RING(ring)) { 4946 if (page_pool_enabled) 4947 hns3_alloc_page_pool(ring); 4948 4949 ret = hns3_alloc_ring_buffers(ring); 4950 if (ret) 4951 goto out_with_desc; 4952 } else { 4953 hns3_init_tx_spare_buffer(ring); 4954 } 4955 4956 return 0; 4957 4958 out_with_desc: 4959 hns3_free_desc(ring); 4960 out_with_desc_cb: 4961 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4962 ring->desc_cb = NULL; 4963 out: 4964 return ret; 4965 } 4966 4967 void hns3_fini_ring(struct hns3_enet_ring *ring) 4968 { 4969 hns3_free_desc(ring); 4970 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4971 ring->desc_cb = NULL; 4972 ring->next_to_clean = 0; 4973 ring->next_to_use = 0; 4974 ring->last_to_use = 0; 4975 ring->pending_buf = 0; 4976 if (!HNAE3_IS_TX_RING(ring) && ring->skb) { 4977 dev_kfree_skb_any(ring->skb); 4978 ring->skb = NULL; 4979 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) { 4980 struct hns3_tx_spare *tx_spare = ring->tx_spare; 4981 4982 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len, 4983 DMA_TO_DEVICE); 4984 free_pages((unsigned long)tx_spare->buf, 4985 get_order(tx_spare->len)); 4986 devm_kfree(ring_to_dev(ring), tx_spare); 4987 ring->tx_spare = NULL; 4988 } 4989 4990 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) { 4991 page_pool_destroy(ring->page_pool); 4992 ring->page_pool = NULL; 4993 } 4994 } 4995 4996 static int hns3_buf_size2type(u32 buf_size) 4997 { 4998 int bd_size_type; 4999 5000 switch (buf_size) { 5001 case 512: 5002 bd_size_type = HNS3_BD_SIZE_512_TYPE; 5003 break; 5004 case 1024: 5005 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 5006 break; 5007 case 2048: 5008 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 5009 break; 5010 case 4096: 5011 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 5012 break; 5013 default: 5014 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 5015 } 5016 5017 return bd_size_type; 5018 } 5019 5020 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 5021 { 5022 dma_addr_t dma = ring->desc_dma_addr; 5023 struct hnae3_queue *q = ring->tqp; 5024 5025 if (!HNAE3_IS_TX_RING(ring)) { 5026 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 5027 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 5028 (u32)((dma >> 31) >> 1)); 5029 5030 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 5031 hns3_buf_size2type(ring->buf_size)); 5032 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 5033 ring->desc_num / 8 - 1); 5034 } else { 5035 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 5036 (u32)dma); 5037 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 5038 (u32)((dma >> 31) >> 1)); 5039 5040 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 5041 ring->desc_num / 8 - 1); 5042 } 5043 } 5044 5045 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 5046 { 5047 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 5048 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 5049 int i; 5050 5051 for (i = 0; i < tc_info->num_tc; i++) { 5052 int j; 5053 5054 for (j = 0; j < tc_info->tqp_count[i]; j++) { 5055 struct hnae3_queue *q; 5056 5057 q = priv->ring[tc_info->tqp_offset[i] + j].tqp; 5058 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i); 5059 } 5060 } 5061 } 5062 5063 int hns3_init_all_ring(struct hns3_nic_priv *priv) 5064 { 5065 struct hnae3_handle *h = priv->ae_handle; 5066 int ring_num = h->kinfo.num_tqps * 2; 5067 int i, j; 5068 int ret; 5069 5070 for (i = 0; i < ring_num; i++) { 5071 ret = hns3_alloc_ring_memory(&priv->ring[i]); 5072 if (ret) { 5073 dev_err(priv->dev, 5074 "Alloc ring memory fail! ret=%d\n", ret); 5075 goto out_when_alloc_ring_memory; 5076 } 5077 5078 u64_stats_init(&priv->ring[i].syncp); 5079 } 5080 5081 return 0; 5082 5083 out_when_alloc_ring_memory: 5084 for (j = i - 1; j >= 0; j--) 5085 hns3_fini_ring(&priv->ring[j]); 5086 5087 return -ENOMEM; 5088 } 5089 5090 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv) 5091 { 5092 struct hnae3_handle *h = priv->ae_handle; 5093 int i; 5094 5095 for (i = 0; i < h->kinfo.num_tqps; i++) { 5096 hns3_fini_ring(&priv->ring[i]); 5097 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 5098 } 5099 } 5100 5101 /* Set mac addr if it is configured. or leave it to the AE driver */ 5102 static int hns3_init_mac_addr(struct net_device *netdev) 5103 { 5104 struct hns3_nic_priv *priv = netdev_priv(netdev); 5105 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 5106 struct hnae3_handle *h = priv->ae_handle; 5107 u8 mac_addr_temp[ETH_ALEN]; 5108 int ret = 0; 5109 5110 if (h->ae_algo->ops->get_mac_addr) 5111 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 5112 5113 /* Check if the MAC address is valid, if not get a random one */ 5114 if (!is_valid_ether_addr(mac_addr_temp)) { 5115 eth_hw_addr_random(netdev); 5116 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr); 5117 dev_warn(priv->dev, "using random MAC address %s\n", 5118 format_mac_addr); 5119 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 5120 eth_hw_addr_set(netdev, mac_addr_temp); 5121 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 5122 } else { 5123 return 0; 5124 } 5125 5126 if (h->ae_algo->ops->set_mac_addr) 5127 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 5128 5129 return ret; 5130 } 5131 5132 static int hns3_init_phy(struct net_device *netdev) 5133 { 5134 struct hnae3_handle *h = hns3_get_handle(netdev); 5135 int ret = 0; 5136 5137 if (h->ae_algo->ops->mac_connect_phy) 5138 ret = h->ae_algo->ops->mac_connect_phy(h); 5139 5140 return ret; 5141 } 5142 5143 static void hns3_uninit_phy(struct net_device *netdev) 5144 { 5145 struct hnae3_handle *h = hns3_get_handle(netdev); 5146 5147 if (h->ae_algo->ops->mac_disconnect_phy) 5148 h->ae_algo->ops->mac_disconnect_phy(h); 5149 } 5150 5151 static int hns3_client_start(struct hnae3_handle *handle) 5152 { 5153 if (!handle->ae_algo->ops->client_start) 5154 return 0; 5155 5156 return handle->ae_algo->ops->client_start(handle); 5157 } 5158 5159 static void hns3_client_stop(struct hnae3_handle *handle) 5160 { 5161 if (!handle->ae_algo->ops->client_stop) 5162 return; 5163 5164 handle->ae_algo->ops->client_stop(handle); 5165 } 5166 5167 static void hns3_info_show(struct hns3_nic_priv *priv) 5168 { 5169 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 5170 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 5171 5172 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr); 5173 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr); 5174 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 5175 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 5176 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 5177 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 5178 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 5179 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 5180 dev_info(priv->dev, "Total number of enabled TCs: %u\n", 5181 kinfo->tc_info.num_tc); 5182 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 5183 } 5184 5185 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv, 5186 enum dim_cq_period_mode mode, bool is_tx) 5187 { 5188 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 5189 struct hnae3_handle *handle = priv->ae_handle; 5190 int i; 5191 5192 if (is_tx) { 5193 priv->tx_cqe_mode = mode; 5194 5195 for (i = 0; i < priv->vector_num; i++) 5196 priv->tqp_vector[i].tx_group.dim.mode = mode; 5197 } else { 5198 priv->rx_cqe_mode = mode; 5199 5200 for (i = 0; i < priv->vector_num; i++) 5201 priv->tqp_vector[i].rx_group.dim.mode = mode; 5202 } 5203 5204 if (hnae3_ae_dev_cq_supported(ae_dev)) { 5205 u32 new_mode; 5206 u64 reg; 5207 5208 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ? 5209 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE; 5210 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG; 5211 5212 writel(new_mode, handle->kinfo.io_base + reg); 5213 } 5214 } 5215 5216 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv, 5217 enum dim_cq_period_mode tx_mode, 5218 enum dim_cq_period_mode rx_mode) 5219 { 5220 hns3_set_cq_period_mode(priv, tx_mode, true); 5221 hns3_set_cq_period_mode(priv, rx_mode, false); 5222 } 5223 5224 static void hns3_state_init(struct hnae3_handle *handle) 5225 { 5226 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 5227 struct net_device *netdev = handle->kinfo.netdev; 5228 struct hns3_nic_priv *priv = netdev_priv(netdev); 5229 5230 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5231 5232 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 5233 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state); 5234 5235 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5236 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags); 5237 5238 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 5239 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 5240 5241 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev)) 5242 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state); 5243 } 5244 5245 static void hns3_state_uninit(struct hnae3_handle *handle) 5246 { 5247 struct hns3_nic_priv *priv = handle->priv; 5248 5249 clear_bit(HNS3_NIC_STATE_INITED, &priv->state); 5250 } 5251 5252 static int hns3_client_init(struct hnae3_handle *handle) 5253 { 5254 struct pci_dev *pdev = handle->pdev; 5255 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5256 u16 alloc_tqps, max_rss_size; 5257 struct hns3_nic_priv *priv; 5258 struct net_device *netdev; 5259 int ret; 5260 5261 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 5262 &max_rss_size); 5263 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 5264 if (!netdev) 5265 return -ENOMEM; 5266 5267 priv = netdev_priv(netdev); 5268 priv->dev = &pdev->dev; 5269 priv->netdev = netdev; 5270 priv->ae_handle = handle; 5271 priv->tx_timeout_count = 0; 5272 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 5273 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 5274 5275 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 5276 5277 handle->kinfo.netdev = netdev; 5278 handle->priv = (void *)priv; 5279 5280 hns3_init_mac_addr(netdev); 5281 5282 hns3_set_default_feature(netdev); 5283 5284 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 5285 netdev->priv_flags |= IFF_UNICAST_FLT; 5286 netdev->netdev_ops = &hns3_nic_netdev_ops; 5287 SET_NETDEV_DEV(netdev, &pdev->dev); 5288 hns3_ethtool_set_ops(netdev); 5289 5290 /* Carrier off reporting is important to ethtool even BEFORE open */ 5291 netif_carrier_off(netdev); 5292 5293 ret = hns3_get_ring_config(priv); 5294 if (ret) { 5295 ret = -ENOMEM; 5296 goto out_get_ring_cfg; 5297 } 5298 5299 hns3_nic_init_coal_cfg(priv); 5300 5301 ret = hns3_nic_alloc_vector_data(priv); 5302 if (ret) { 5303 ret = -ENOMEM; 5304 goto out_alloc_vector_data; 5305 } 5306 5307 ret = hns3_nic_init_vector_data(priv); 5308 if (ret) { 5309 ret = -ENOMEM; 5310 goto out_init_vector_data; 5311 } 5312 5313 ret = hns3_init_all_ring(priv); 5314 if (ret) { 5315 ret = -ENOMEM; 5316 goto out_init_ring; 5317 } 5318 5319 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE, 5320 DIM_CQ_PERIOD_MODE_START_FROM_EQE); 5321 5322 ret = hns3_init_phy(netdev); 5323 if (ret) 5324 goto out_init_phy; 5325 5326 /* the device can work without cpu rmap, only aRFS needs it */ 5327 ret = hns3_set_rx_cpu_rmap(netdev); 5328 if (ret) 5329 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5330 5331 ret = hns3_nic_init_irq(priv); 5332 if (ret) { 5333 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5334 hns3_free_rx_cpu_rmap(netdev); 5335 goto out_init_irq_fail; 5336 } 5337 5338 ret = hns3_client_start(handle); 5339 if (ret) { 5340 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5341 goto out_client_start; 5342 } 5343 5344 hns3_dcbnl_setup(handle); 5345 5346 ret = hns3_dbg_init(handle); 5347 if (ret) { 5348 dev_err(priv->dev, "failed to init debugfs, ret = %d\n", 5349 ret); 5350 goto out_client_start; 5351 } 5352 5353 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); 5354 5355 hns3_state_init(handle); 5356 5357 ret = register_netdev(netdev); 5358 if (ret) { 5359 dev_err(priv->dev, "probe register netdev fail!\n"); 5360 goto out_reg_netdev_fail; 5361 } 5362 5363 if (netif_msg_drv(handle)) 5364 hns3_info_show(priv); 5365 5366 return ret; 5367 5368 out_reg_netdev_fail: 5369 hns3_state_uninit(handle); 5370 hns3_dbg_uninit(handle); 5371 hns3_client_stop(handle); 5372 out_client_start: 5373 hns3_free_rx_cpu_rmap(netdev); 5374 hns3_nic_uninit_irq(priv); 5375 out_init_irq_fail: 5376 hns3_uninit_phy(netdev); 5377 out_init_phy: 5378 hns3_uninit_all_ring(priv); 5379 out_init_ring: 5380 hns3_nic_uninit_vector_data(priv); 5381 out_init_vector_data: 5382 hns3_nic_dealloc_vector_data(priv); 5383 out_alloc_vector_data: 5384 priv->ring = NULL; 5385 out_get_ring_cfg: 5386 priv->ae_handle = NULL; 5387 free_netdev(netdev); 5388 return ret; 5389 } 5390 5391 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 5392 { 5393 struct net_device *netdev = handle->kinfo.netdev; 5394 struct hns3_nic_priv *priv = netdev_priv(netdev); 5395 5396 if (netdev->reg_state != NETREG_UNINITIALIZED) 5397 unregister_netdev(netdev); 5398 5399 hns3_client_stop(handle); 5400 5401 hns3_uninit_phy(netdev); 5402 5403 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5404 netdev_warn(netdev, "already uninitialized\n"); 5405 goto out_netdev_free; 5406 } 5407 5408 hns3_free_rx_cpu_rmap(netdev); 5409 5410 hns3_nic_uninit_irq(priv); 5411 5412 hns3_clear_all_ring(handle, true); 5413 5414 hns3_nic_uninit_vector_data(priv); 5415 5416 hns3_nic_dealloc_vector_data(priv); 5417 5418 hns3_uninit_all_ring(priv); 5419 5420 hns3_put_ring_config(priv); 5421 5422 out_netdev_free: 5423 hns3_dbg_uninit(handle); 5424 free_netdev(netdev); 5425 } 5426 5427 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 5428 { 5429 struct net_device *netdev = handle->kinfo.netdev; 5430 5431 if (!netdev) 5432 return; 5433 5434 if (linkup) { 5435 netif_tx_wake_all_queues(netdev); 5436 netif_carrier_on(netdev); 5437 if (netif_msg_link(handle)) 5438 netdev_info(netdev, "link up\n"); 5439 } else { 5440 netif_carrier_off(netdev); 5441 netif_tx_stop_all_queues(netdev); 5442 if (netif_msg_link(handle)) 5443 netdev_info(netdev, "link down\n"); 5444 } 5445 } 5446 5447 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 5448 { 5449 while (ring->next_to_clean != ring->next_to_use) { 5450 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 5451 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 5452 ring_ptr_move_fw(ring, next_to_clean); 5453 } 5454 5455 ring->pending_buf = 0; 5456 } 5457 5458 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 5459 { 5460 struct hns3_desc_cb res_cbs; 5461 int ret; 5462 5463 while (ring->next_to_use != ring->next_to_clean) { 5464 /* When a buffer is not reused, it's memory has been 5465 * freed in hns3_handle_rx_bd or will be freed by 5466 * stack, so we need to replace the buffer here. 5467 */ 5468 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5469 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 5470 if (ret) { 5471 hns3_ring_stats_update(ring, sw_err_cnt); 5472 /* if alloc new buffer fail, exit directly 5473 * and reclear in up flow. 5474 */ 5475 netdev_warn(ring_to_netdev(ring), 5476 "reserve buffer map failed, ret = %d\n", 5477 ret); 5478 return ret; 5479 } 5480 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 5481 } 5482 ring_ptr_move_fw(ring, next_to_use); 5483 } 5484 5485 /* Free the pending skb in rx ring */ 5486 if (ring->skb) { 5487 dev_kfree_skb_any(ring->skb); 5488 ring->skb = NULL; 5489 ring->pending_buf = 0; 5490 } 5491 5492 return 0; 5493 } 5494 5495 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 5496 { 5497 while (ring->next_to_use != ring->next_to_clean) { 5498 /* When a buffer is not reused, it's memory has been 5499 * freed in hns3_handle_rx_bd or will be freed by 5500 * stack, so only need to unmap the buffer here. 5501 */ 5502 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5503 hns3_unmap_buffer(ring, 5504 &ring->desc_cb[ring->next_to_use]); 5505 ring->desc_cb[ring->next_to_use].dma = 0; 5506 } 5507 5508 ring_ptr_move_fw(ring, next_to_use); 5509 } 5510 } 5511 5512 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 5513 { 5514 struct net_device *ndev = h->kinfo.netdev; 5515 struct hns3_nic_priv *priv = netdev_priv(ndev); 5516 u32 i; 5517 5518 for (i = 0; i < h->kinfo.num_tqps; i++) { 5519 struct hns3_enet_ring *ring; 5520 5521 ring = &priv->ring[i]; 5522 hns3_clear_tx_ring(ring); 5523 5524 ring = &priv->ring[i + h->kinfo.num_tqps]; 5525 /* Continue to clear other rings even if clearing some 5526 * rings failed. 5527 */ 5528 if (force) 5529 hns3_force_clear_rx_ring(ring); 5530 else 5531 hns3_clear_rx_ring(ring); 5532 } 5533 } 5534 5535 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 5536 { 5537 struct net_device *ndev = h->kinfo.netdev; 5538 struct hns3_nic_priv *priv = netdev_priv(ndev); 5539 struct hns3_enet_ring *rx_ring; 5540 int i, j; 5541 int ret; 5542 5543 ret = h->ae_algo->ops->reset_queue(h); 5544 if (ret) 5545 return ret; 5546 5547 for (i = 0; i < h->kinfo.num_tqps; i++) { 5548 hns3_init_ring_hw(&priv->ring[i]); 5549 5550 /* We need to clear tx ring here because self test will 5551 * use the ring and will not run down before up 5552 */ 5553 hns3_clear_tx_ring(&priv->ring[i]); 5554 priv->ring[i].next_to_clean = 0; 5555 priv->ring[i].next_to_use = 0; 5556 priv->ring[i].last_to_use = 0; 5557 5558 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 5559 hns3_init_ring_hw(rx_ring); 5560 ret = hns3_clear_rx_ring(rx_ring); 5561 if (ret) 5562 return ret; 5563 5564 /* We can not know the hardware head and tail when this 5565 * function is called in reset flow, so we reuse all desc. 5566 */ 5567 for (j = 0; j < rx_ring->desc_num; j++) 5568 hns3_reuse_buffer(rx_ring, j); 5569 5570 rx_ring->next_to_clean = 0; 5571 rx_ring->next_to_use = 0; 5572 } 5573 5574 hns3_init_tx_ring_tc(priv); 5575 5576 return 0; 5577 } 5578 5579 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 5580 { 5581 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5582 struct net_device *ndev = kinfo->netdev; 5583 struct hns3_nic_priv *priv = netdev_priv(ndev); 5584 5585 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 5586 return 0; 5587 5588 if (!netif_running(ndev)) 5589 return 0; 5590 5591 return hns3_nic_net_stop(ndev); 5592 } 5593 5594 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 5595 { 5596 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5597 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 5598 int ret = 0; 5599 5600 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5601 netdev_err(kinfo->netdev, "device is not initialized yet\n"); 5602 return -EFAULT; 5603 } 5604 5605 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5606 5607 if (netif_running(kinfo->netdev)) { 5608 ret = hns3_nic_net_open(kinfo->netdev); 5609 if (ret) { 5610 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5611 netdev_err(kinfo->netdev, 5612 "net up fail, ret=%d!\n", ret); 5613 return ret; 5614 } 5615 } 5616 5617 return ret; 5618 } 5619 5620 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 5621 { 5622 struct net_device *netdev = handle->kinfo.netdev; 5623 struct hns3_nic_priv *priv = netdev_priv(netdev); 5624 int ret; 5625 5626 /* Carrier off reporting is important to ethtool even BEFORE open */ 5627 netif_carrier_off(netdev); 5628 5629 ret = hns3_get_ring_config(priv); 5630 if (ret) 5631 return ret; 5632 5633 ret = hns3_nic_alloc_vector_data(priv); 5634 if (ret) 5635 goto err_put_ring; 5636 5637 ret = hns3_nic_init_vector_data(priv); 5638 if (ret) 5639 goto err_dealloc_vector; 5640 5641 ret = hns3_init_all_ring(priv); 5642 if (ret) 5643 goto err_uninit_vector; 5644 5645 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode); 5646 5647 /* the device can work without cpu rmap, only aRFS needs it */ 5648 ret = hns3_set_rx_cpu_rmap(netdev); 5649 if (ret) 5650 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5651 5652 ret = hns3_nic_init_irq(priv); 5653 if (ret) { 5654 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5655 hns3_free_rx_cpu_rmap(netdev); 5656 goto err_init_irq_fail; 5657 } 5658 5659 if (!hns3_is_phys_func(handle->pdev)) 5660 hns3_init_mac_addr(netdev); 5661 5662 ret = hns3_client_start(handle); 5663 if (ret) { 5664 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5665 goto err_client_start_fail; 5666 } 5667 5668 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5669 5670 return ret; 5671 5672 err_client_start_fail: 5673 hns3_free_rx_cpu_rmap(netdev); 5674 hns3_nic_uninit_irq(priv); 5675 err_init_irq_fail: 5676 hns3_uninit_all_ring(priv); 5677 err_uninit_vector: 5678 hns3_nic_uninit_vector_data(priv); 5679 err_dealloc_vector: 5680 hns3_nic_dealloc_vector_data(priv); 5681 err_put_ring: 5682 hns3_put_ring_config(priv); 5683 5684 return ret; 5685 } 5686 5687 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 5688 { 5689 struct net_device *netdev = handle->kinfo.netdev; 5690 struct hns3_nic_priv *priv = netdev_priv(netdev); 5691 5692 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5693 netdev_warn(netdev, "already uninitialized\n"); 5694 return 0; 5695 } 5696 5697 hns3_free_rx_cpu_rmap(netdev); 5698 hns3_nic_uninit_irq(priv); 5699 hns3_clear_all_ring(handle, true); 5700 hns3_reset_tx_queue(priv->ae_handle); 5701 5702 hns3_nic_uninit_vector_data(priv); 5703 5704 hns3_nic_dealloc_vector_data(priv); 5705 5706 hns3_uninit_all_ring(priv); 5707 5708 hns3_put_ring_config(priv); 5709 5710 return 0; 5711 } 5712 5713 int hns3_reset_notify(struct hnae3_handle *handle, 5714 enum hnae3_reset_notify_type type) 5715 { 5716 int ret = 0; 5717 5718 switch (type) { 5719 case HNAE3_UP_CLIENT: 5720 ret = hns3_reset_notify_up_enet(handle); 5721 break; 5722 case HNAE3_DOWN_CLIENT: 5723 ret = hns3_reset_notify_down_enet(handle); 5724 break; 5725 case HNAE3_INIT_CLIENT: 5726 ret = hns3_reset_notify_init_enet(handle); 5727 break; 5728 case HNAE3_UNINIT_CLIENT: 5729 ret = hns3_reset_notify_uninit_enet(handle); 5730 break; 5731 default: 5732 break; 5733 } 5734 5735 return ret; 5736 } 5737 5738 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 5739 bool rxfh_configured) 5740 { 5741 int ret; 5742 5743 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 5744 rxfh_configured); 5745 if (ret) { 5746 dev_err(&handle->pdev->dev, 5747 "Change tqp num(%u) fail.\n", new_tqp_num); 5748 return ret; 5749 } 5750 5751 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 5752 if (ret) 5753 return ret; 5754 5755 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 5756 if (ret) 5757 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 5758 5759 return ret; 5760 } 5761 5762 int hns3_set_channels(struct net_device *netdev, 5763 struct ethtool_channels *ch) 5764 { 5765 struct hnae3_handle *h = hns3_get_handle(netdev); 5766 struct hnae3_knic_private_info *kinfo = &h->kinfo; 5767 bool rxfh_configured = netif_is_rxfh_configured(netdev); 5768 u32 new_tqp_num = ch->combined_count; 5769 u16 org_tqp_num; 5770 int ret; 5771 5772 if (hns3_nic_resetting(netdev)) 5773 return -EBUSY; 5774 5775 if (ch->rx_count || ch->tx_count) 5776 return -EINVAL; 5777 5778 if (kinfo->tc_info.mqprio_active) { 5779 dev_err(&netdev->dev, 5780 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n"); 5781 return -EINVAL; 5782 } 5783 5784 if (new_tqp_num > hns3_get_max_available_channels(h) || 5785 new_tqp_num < 1) { 5786 dev_err(&netdev->dev, 5787 "Change tqps fail, the tqp range is from 1 to %u", 5788 hns3_get_max_available_channels(h)); 5789 return -EINVAL; 5790 } 5791 5792 if (kinfo->rss_size == new_tqp_num) 5793 return 0; 5794 5795 netif_dbg(h, drv, netdev, 5796 "set channels: tqp_num=%u, rxfh=%d\n", 5797 new_tqp_num, rxfh_configured); 5798 5799 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 5800 if (ret) 5801 return ret; 5802 5803 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 5804 if (ret) 5805 return ret; 5806 5807 org_tqp_num = h->kinfo.num_tqps; 5808 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 5809 if (ret) { 5810 int ret1; 5811 5812 netdev_warn(netdev, 5813 "Change channels fail, revert to old value\n"); 5814 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 5815 if (ret1) { 5816 netdev_err(netdev, 5817 "revert to old channel fail\n"); 5818 return ret1; 5819 } 5820 5821 return ret; 5822 } 5823 5824 return 0; 5825 } 5826 5827 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running) 5828 { 5829 struct hns3_nic_priv *priv = netdev_priv(ndev); 5830 struct hnae3_handle *h = priv->ae_handle; 5831 int i; 5832 5833 if (!if_running) 5834 return; 5835 5836 netif_carrier_off(ndev); 5837 netif_tx_disable(ndev); 5838 5839 for (i = 0; i < priv->vector_num; i++) 5840 hns3_vector_disable(&priv->tqp_vector[i]); 5841 5842 for (i = 0; i < h->kinfo.num_tqps; i++) 5843 hns3_tqp_disable(h->kinfo.tqp[i]); 5844 5845 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 5846 * during reset process, because driver may not be able 5847 * to disable the ring through firmware when downing the netdev. 5848 */ 5849 if (!hns3_nic_resetting(ndev)) 5850 hns3_nic_reset_all_ring(priv->ae_handle); 5851 5852 hns3_reset_tx_queue(priv->ae_handle); 5853 } 5854 5855 void hns3_external_lb_restore(struct net_device *ndev, bool if_running) 5856 { 5857 struct hns3_nic_priv *priv = netdev_priv(ndev); 5858 struct hnae3_handle *h = priv->ae_handle; 5859 int i; 5860 5861 if (!if_running) 5862 return; 5863 5864 hns3_nic_reset_all_ring(priv->ae_handle); 5865 5866 for (i = 0; i < priv->vector_num; i++) 5867 hns3_vector_enable(&priv->tqp_vector[i]); 5868 5869 for (i = 0; i < h->kinfo.num_tqps; i++) 5870 hns3_tqp_enable(h->kinfo.tqp[i]); 5871 5872 netif_tx_wake_all_queues(ndev); 5873 5874 if (h->ae_algo->ops->get_status(h)) 5875 netif_carrier_on(ndev); 5876 } 5877 5878 static const struct hns3_hw_error_info hns3_hw_err[] = { 5879 { .type = HNAE3_PPU_POISON_ERROR, 5880 .msg = "PPU poison" }, 5881 { .type = HNAE3_CMDQ_ECC_ERROR, 5882 .msg = "IMP CMDQ error" }, 5883 { .type = HNAE3_IMP_RD_POISON_ERROR, 5884 .msg = "IMP RD poison" }, 5885 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 5886 .msg = "ROCEE AXI RESP error" }, 5887 }; 5888 5889 static void hns3_process_hw_error(struct hnae3_handle *handle, 5890 enum hnae3_hw_error_type type) 5891 { 5892 int i; 5893 5894 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 5895 if (hns3_hw_err[i].type == type) { 5896 dev_err(&handle->pdev->dev, "Detected %s!\n", 5897 hns3_hw_err[i].msg); 5898 break; 5899 } 5900 } 5901 } 5902 5903 static const struct hnae3_client_ops client_ops = { 5904 .init_instance = hns3_client_init, 5905 .uninit_instance = hns3_client_uninit, 5906 .link_status_change = hns3_link_status_change, 5907 .reset_notify = hns3_reset_notify, 5908 .process_hw_error = hns3_process_hw_error, 5909 }; 5910 5911 /* hns3_init_module - Driver registration routine 5912 * hns3_init_module is the first routine called when the driver is 5913 * loaded. All it does is register with the PCI subsystem. 5914 */ 5915 static int __init hns3_init_module(void) 5916 { 5917 int ret; 5918 5919 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 5920 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 5921 5922 client.type = HNAE3_CLIENT_KNIC; 5923 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 5924 hns3_driver_name); 5925 5926 client.ops = &client_ops; 5927 5928 INIT_LIST_HEAD(&client.node); 5929 5930 hns3_dbg_register_debugfs(hns3_driver_name); 5931 5932 ret = hnae3_register_client(&client); 5933 if (ret) 5934 goto err_reg_client; 5935 5936 ret = pci_register_driver(&hns3_driver); 5937 if (ret) 5938 goto err_reg_driver; 5939 5940 return ret; 5941 5942 err_reg_driver: 5943 hnae3_unregister_client(&client); 5944 err_reg_client: 5945 hns3_dbg_unregister_debugfs(); 5946 return ret; 5947 } 5948 module_init(hns3_init_module); 5949 5950 /* hns3_exit_module - Driver exit cleanup routine 5951 * hns3_exit_module is called just before the driver is removed 5952 * from memory. 5953 */ 5954 static void __exit hns3_exit_module(void) 5955 { 5956 pci_unregister_driver(&hns3_driver); 5957 hnae3_unregister_client(&client); 5958 hns3_dbg_unregister_debugfs(); 5959 } 5960 module_exit(hns3_exit_module); 5961 5962 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 5963 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 5964 MODULE_LICENSE("GPL"); 5965 MODULE_ALIAS("pci:hns-nic"); 5966